From nobody Sat Sep 26 20:53:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1789682535; cv=none; d=zohomail.com; s=zohoarc; b=cweQenz817KTWtbMbfU9UJ+NZ7UqIHQc5DbhYj6K5xlmQ7nuDPtg53uCKAbNIcUqkaZzGpaoXoci4xjUoiOl6WDFW8C9WkYewGW009+D5CS3uytovu99SoBA+VgMaRrmnosdS5yxUSn3v69JXeth9IZEOR1eubkbUgdroLypXHA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789682535; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=nwLwQgR42J7eKkcK5W6JtsjBjSmohEpkHacQMA24HDk=; b=GrOuyTVVDU/uGbxWdFVkQ+uOvVqio8eFFg2rMywGpRygCJdU/dZ3LkOg/FUJlHC+vsr26jzqfwWCQ0w5m+/z59MJn9UEFcZ+JdqrkvUV/mZKqlLsH4J+RSHG/z/hUxEZ8HzmsOB7i2z7yQZOK3M05XULIIEK6heCxxmU75haY5I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1789682535429546.1879696148341; Thu, 17 Sep 2026 15:02:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x7KAA-0004En-Et; Thu, 17 Sep 2026 18:01:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x7K9K-00040J-8p; Thu, 17 Sep 2026 18:00:11 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x7K9G-0004ID-N2; Thu, 17 Sep 2026 18:00:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=nwLwQgR42J7eKkcK5W6JtsjBjSmohEpkHacQMA24HDk=; b=FZDDZnoZF989F8c EQqK5c7QcnhceXa8IxVVYvlrRDanlDHr0lpRlZDa9OQnshRS3+gGJnco46gCq2/SDBS/LZz8HAJyh CepgY6nCU4mlRMMauGu4IBvEaEEqLQto0C0mQfi0Fivfomr6E9mBXVPgcuS4JuOHvnhuq0CQEZ0FQ 9I=; Date: Fri, 18 Sep 2026 00:04:55 +0200 Subject: [PATCH v5 01/11] target/riscv: Replace TYPE_RISCV_CPU_BASE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-hw-riscv-cpu-int-v5-1-f98c5a244636@rev.ng> References: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> In-Reply-To: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , qemu-riscv@nongnu.org, daniel.barboza@oss.qualcomm.com, philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com, Chao Liu X-Developer-Signature: v=1; a=ed25519-sha256; t=1789682743; l=2759; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=UBOkEAVcELBmELPjY92jS8lwx3tbFIEInyLiERUp3yM=; b=F01t1nZ613cFVmKsfUez8ILnFOyWb0OGxkzmARE8FTQnbqMbawCQPBJyfzN+fmTaO3LGczLCm f2U+MxkDeSRD5zq9jspAKrAjCTzFLVT9sRBmvmlzNsHBKIP5tvfdGn0 X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1789682537481158500 TYPE_RISCV_CPU_BASE is used only to initialize the correct default machine for 2 machines. Replace it with a runtime check. Reviewed-by: Pierrick Bouvier Reviewed-by: Chao Liu Signed-off-by: Anton Johansson -- Note, this patch is to be replaced by: 20260526095731.63525-1-philmd@linaro= .org --- target/riscv/cpu.h | 6 ------ hw/riscv/microblaze-v-generic.c | 4 +++- hw/riscv/virt.c | 4 +++- 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c2138dbd4b..aee1dcaaf9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -39,12 +39,6 @@ typedef struct CPUArchState CPURISCVState; =20 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU =20 -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - /* * b0: Whether a instruction always raise a store AMO or not. */ diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generi= c.c index b0494b1ac5..3f07ab2132 100644 --- a/hw/riscv/microblaze-v-generic.c +++ b/hw/riscv/microblaze-v-generic.c @@ -15,6 +15,7 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/target-info.h" #include "qapi/error.h" #include "target/riscv/cpu.h" #include "hw/core/sysbus.h" @@ -182,7 +183,8 @@ static void mb_v_generic_machine_init(MachineClass *mc) mc->init =3D mb_v_generic_init; mc->min_cpus =3D 1; mc->max_cpus =3D 1; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D (target_riscv64()) ? TYPE_RISCV_CPU_BASE64 + : TYPE_RISCV_CPU_BASE32; mc->default_cpus =3D 1; } =20 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d4b501802f..4da11db8b9 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -22,6 +22,7 @@ #include "qemu/units.h" #include "qemu/error-report.h" #include "qemu/guest-random.h" +#include "qemu/target-info.h" #include "qapi/error.h" #include "hw/core/boards.h" #include "hw/core/loader.h" @@ -1136,7 +1137,8 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) mc->desc =3D "RISC-V VirtIO board"; mc->init =3D virt_machine_init; mc->max_cpus =3D VIRT_CPUS_MAX; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D (target_riscv64()) ? TYPE_RISCV_CPU_BASE64 + : TYPE_RISCV_CPU_BASE32; mc->block_default_type =3D IF_VIRTIO; mc->no_cdrom =3D 1; mc->pci_allow_0_address =3D true; --=20 2.52.0 From nobody Sat Sep 26 20:53:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1789682491; cv=none; d=zohomail.com; s=zohoarc; b=c7mupuasZBPEaK2MdqHnf0az5aOREsQULT8fcDvo0OTCkCqZwZQhHn9VP+DweZh5TaaGYbWyJvwRNWD1V7kK4a4+UMnRyhYiVFW7Oc3Nf43U6ZCOq83gwneV2z0tJb8oPYCE1bbw/NnAncgNKojcoUIc/ddJU6srnCiaT1erSaI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789682491; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-hw-riscv-cpu-int-v5-2-f98c5a244636@rev.ng> References: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> In-Reply-To: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , qemu-riscv@nongnu.org, daniel.barboza@oss.qualcomm.com, philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com X-Developer-Signature: v=1; a=ed25519-sha256; t=1789682743; l=3291; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=367gC5i9cTxYMUQLiZ7x404bFso1ulNo3mGxqF0oJzI=; b=KH7fQbY3VUbi7lCHCS9uPYJyrGHpirLUQZPvq5tEWn4xsxtAE8YBqEyJzg/6NrEl45MmPid1q AQh2ArB/QJyDq6OAmLYoLOxWF4Waun9dUyxcQDYbCAL4x+1UFNZt0Qk X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1789682493335158500 KVM fields of CPURISCVState are now always exposed as CONFIG_KVM cannot be used in common code. riscv_cpu_mxl() is changed to return CPURISCVState::misa_mxl unconditionally, as use of target_riscv64() would result in an extra load and compare with TargetInfo::target_arch. We might as well just perform a single load. Likewise, for cpu_recompute_xl(), cpu_address_xl(), and riscv_cpu_sxl(), we opt for returning the corresponding CPURISCVState field with ifdefs for system mode adding extra conditions. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- target/riscv/cpu.h | 36 ++++++++---------------------------- 1 file changed, 8 insertions(+), 28 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index aee1dcaaf9..e2e0547eef 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -525,7 +525,6 @@ struct CPUArchState { hwaddr kernel_addr; hwaddr fdt_addr; =20 -#ifdef CONFIG_KVM /* kvm timer */ bool kvm_timer_dirty; uint64_t kvm_timer_time; @@ -536,7 +535,6 @@ struct CPUArchState { /* KVM multiprocessor state */ uint32_t kvm_mp_state; bool kvm_mp_state_loaded; -#endif /* CONFIG_KVM */ }; =20 /* @@ -743,14 +741,10 @@ FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32) FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1) FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1) =20 -#ifdef TARGET_RISCV32 -#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) { return env->misa_mxl; } -#endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) =20 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) @@ -794,9 +788,6 @@ static inline RISCVMXL cpu_get_xl(CPURISCVState *env, p= rivilege_mode_t mode) } #endif =20 -#if defined(TARGET_RISCV32) -#define cpu_recompute_xl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) { #if !defined(CONFIG_USER_ONLY) @@ -805,43 +796,32 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState= *env) return env->misa_mxl; #endif } -#endif =20 -#if defined(TARGET_RISCV32) -#define cpu_address_xl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL cpu_address_xl(CPURISCVState *env) { -#ifdef CONFIG_USER_ONLY - return env->xl; -#else - privilege_mode_t mode =3D cpu_address_mode(env); - - return cpu_get_xl(env, mode); +#ifndef CONFIG_USER_ONLY + if (target_riscv64()) { + privilege_mode_t mode =3D cpu_address_mode(env); + return cpu_get_xl(env, mode); + } #endif + return env->xl; } -#endif =20 static inline uint16_t riscv_cpu_xlen(CPURISCVState *env) { return 16 << env->xl; } =20 -#ifdef TARGET_RISCV32 -#define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) { -#ifdef CONFIG_USER_ONLY - return env->misa_mxl; -#else +#ifndef CONFIG_USER_ONLY if (env->misa_mxl !=3D MXL_RV32) { return get_field(env->mstatus, MSTATUS64_SXL); } #endif - return MXL_RV32; + return env->misa_mxl; } -#endif =20 /* * Returns the current effective privilege mode. --=20 2.52.0 From nobody Sat Sep 26 20:53:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=hHlTPVKBpcV70GoIK5oq1wvEu2STKnhlvWYVKvr1ZZc=; b=J7Pw8N/lQDNGPX5 xKN/Ks+GX/TNY4aDecFwbYFY30ZZoMhQc3VaLc7N/kJZUNmipkscgi5efY5/s6IkQdfA2yiR2cKs3 tvjcsK3rAmcVkmQNRyBT5GzxP/04ao2Fdb/TQyt1ycLoEN5l16fWMkKk6oRNcXIbjRyjivSWgNbze HU=; Date: Fri, 18 Sep 2026 00:04:57 +0200 Subject: [PATCH v5 03/11] target/riscv: Replace TARGET_LONG_BITS in header exposed to common code MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-hw-riscv-cpu-int-v5-3-f98c5a244636@rev.ng> References: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> In-Reply-To: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , qemu-riscv@nongnu.org, daniel.barboza@oss.qualcomm.com, philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com X-Developer-Signature: v=1; a=ed25519-sha256; t=1789682743; l=4286; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=7tERnw+SXhf71aJjBnCLDRIC3GDPPki6F9zqTdNAZ24=; b=a2jmHSArrYWc2TwJuj0NT31Xs8VHzHwh7Ykq/BI5/mXbx5sETW+bNLxv3RpCBSX4IVzYma21N F9ddWyFl0pDBYi9kO3EGi0/1lj85aGgNYjhahs30u188w5K8Crv1GEm X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1789682507265158500 IRQ_LOCAL_GUEST_MAX depends on TARGET_LONG_BITS and is used in hw/intc/riscv_imsic.c. The macro is replaced by a field in RISCVCPUDef initialized in riscv_cpu_class_base_init(). Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- target/riscv/cpu.h | 5 ++++- target/riscv/cpu_bits.h | 2 -- hw/intc/riscv_imsic.c | 4 +++- target/riscv/cpu.c | 16 ++++++++++++++-- 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e2e0547eef..a820ec2f6e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -589,8 +589,11 @@ typedef struct RISCVCPUDef { int32_t vext_spec; RISCVCPUConfig cfg; bool bare; -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) +#if !defined(CONFIG_USER_ONLY) +#if defined(CONFIG_TCG) const RISCVCSR *custom_csrs; +#endif + uint8_t irq_local_guest_max; #endif /* This is just a setter for env->num_triggers. */ uint32_t num_triggers; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c01050ce2b..9c499e33f2 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -811,8 +811,6 @@ typedef enum RISCVException { #define IRQ_S_GEXT 12 #define IRQ_PMU_OVF 13 #define IRQ_LOCAL_MAX 64 -/* -1 is due to bit zero of hgeip and hgeie being ROZ. */ -#define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) =20 /* RNMI causes */ #define RNMI_MAX 16 diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index cb9ce9612c..bf0434e96f 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -501,13 +501,15 @@ DeviceState *riscv_imsic_create(MemoryRegion *contain= er, hwaddr addr, { DeviceState *dev =3D qdev_new(TYPE_RISCV_IMSIC); CPUState *cpu =3D cpu_by_arch_id(hartid); + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(RISCV_CPU(cpu)); uint32_t i; =20 assert(!(addr & (IMSIC_MMIO_PAGE_SZ - 1))); if (mmode) { assert(num_pages =3D=3D 1); } else { - assert(num_pages >=3D 1 && num_pages <=3D (IRQ_LOCAL_GUEST_MAX + 1= )); + assert(num_pages >=3D 1 && + num_pages <=3D (mcc->def->irq_local_guest_max + 1)); } assert(IMSIC_MIN_ID <=3D num_ids); assert(num_ids <=3D IMSIC_MAX_ID); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5fff9d745e..4f58e91b62 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1416,6 +1416,7 @@ void riscv_add_satp_mode_properties(Object *obj) =20 static void riscv_cpu_set_irq(void *opaque, int irq, int level) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(opaque); RISCVCPU *cpu =3D RISCV_CPU(opaque); CPURISCVState *env =3D &cpu->env; =20 @@ -1454,7 +1455,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) default: g_assert_not_reached(); } - } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { + } else if (irq < (IRQ_LOCAL_MAX + mcc->def->irq_local_guest_max)) { /* Require H-extension for handling guest local interrupts */ if (!riscv_has_ext(env, RVH)) { g_assert_not_reached(); @@ -1501,7 +1502,7 @@ static void riscv_cpu_init(Object *obj) =20 #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, - IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); + IRQ_LOCAL_MAX + mcc->def->irq_local_guest_max); if (mcc->def->num_triggers) { env->num_triggers =3D mcc->def->num_triggers; } @@ -3092,6 +3093,17 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , const void *data) mcc->def =3D g_new0(RISCVCPUDef, 1); } =20 +#ifndef CONFIG_USER_ONLY + /* + * RISCVCPUDef::irq_local_guest_max is initialized to + * `target_long_bits()-1` due to bit zero of hgeip and hgeie + * being ROZ. + * + * This value does not vary between CPU types. + */ + mcc->def->irq_local_guest_max =3D target_long_bits() - 1; +#endif + if (data) { const RISCVCPUDef *def =3D data; mcc->def->bare |=3D def->bare; --=20 2.52.0 From nobody Sat Sep 26 20:53:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1789682476733255.97264306612908; Thu, 17 Sep 2026 15:01:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x7K9h-000476-PO; Thu, 17 Sep 2026 18:00:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x7K9K-00040k-NT; Thu, 17 Sep 2026 18:00:11 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x7K9H-0004JM-OR; Thu, 17 Sep 2026 18:00:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; 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Note return type could be made uint32_t and arguments dropped, but I chose to follow the existing CSR OP style of functions, in case there are other plans for this one. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- target/riscv/cpu.h | 4 ++-- target/riscv/cpu.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a820ec2f6e..a5fb75b990 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -953,8 +953,8 @@ void riscv_add_satp_mode_properties(Object *obj); bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); -target_ulong riscv_new_csr_seed(target_ulong new_value, - target_ulong write_mask); +uint64_t riscv_new_csr_seed(uint64_t new_value, + uint64_t write_mask); const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); =20 const char *priv_spec_to_str(int priv_version); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4f58e91b62..3356ba61d2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -546,13 +546,13 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) #endif =20 /* Used by csr.c and the KVM driver */ -target_ulong riscv_new_csr_seed(target_ulong new_value, - target_ulong write_mask) +uint64_t riscv_new_csr_seed(uint64_t new_value, + uint64_t write_mask) { uint16_t random_v; Error *random_e =3D NULL; int random_r; - target_ulong rval; + uint64_t rval; =20 random_r =3D qemu_guest_getrandom(&random_v, 2, &random_e); if (unlikely(random_r < 0)) { --=20 2.52.0 From nobody Sat Sep 26 20:53:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1789682483; cv=none; d=zohomail.com; s=zohoarc; b=FAZyCkPP1YMY6XhjP/Fy1XXgow5mDhj8lvMZeip8/YhGT0TL8lSOxMSvJjQwC+estOgPwlf+l/K0rIljuU07TBjJ/x29Yqm34Patx41nqi5JLDBwm7LgfP7os5cPTR/kLjTPMfAUSFcplKFqWl0sKa+2jplo/HxtDwATJumKZ90= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789682483; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-hw-riscv-cpu-int-v5-5-f98c5a244636@rev.ng> References: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> In-Reply-To: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , qemu-riscv@nongnu.org, daniel.barboza@oss.qualcomm.com, philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com X-Developer-Signature: v=1; a=ed25519-sha256; t=1789682743; l=2075; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=SmQC4q0Y5o0T40JGR8Ackm0oNwRh0OgKntILAQviVXI=; b=cKAh5xGLf3GjCO4rfg0M0uBR4tJWdD4rSkS7Sa/VdpZwuK6qrxeAhM0e6cSXgYhgkxqhl+Q7d dQOHcNZi1nyC0f41NIW/xcpKHdrHPsgsRWYMRX0hs426xj1koEFy3iP X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1789682487407158500 Functions used externally by hw/riscv are stubbed out for non-kvm configurations, allowing a single compilation of hw/riscv. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/kvm/kvm-stub.c | 23 +++++++++++++++++++++++ target/riscv/kvm/meson.build | 1 + target/riscv/meson.build | 3 +++ 3 files changed, 27 insertions(+) diff --git a/target/riscv/kvm/kvm-stub.c b/target/riscv/kvm/kvm-stub.c new file mode 100644 index 0000000000..64e39c96d8 --- /dev/null +++ b/target/riscv/kvm/kvm-stub.c @@ -0,0 +1,23 @@ +/* + * QEMU RISCV specific KVM stubs + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "target/riscv/kvm/kvm_riscv.h" + +void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, + uint64_t aia_irq_num, uint64_t aia_msi_num, + uint64_t aplic_base, uint64_t imsic_base, + uint64_t guest_num) +{ + g_assert_not_reached(); +} + +uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu) +{ + g_assert_not_reached(); +} diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build index 7e92415091..75e35b2150 100644 --- a/target/riscv/kvm/meson.build +++ b/target/riscv/kvm/meson.build @@ -1 +1,2 @@ riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c')) +riscv_stubs_ss.add(files('kvm-stub.c')) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 42d0f6d538..e1b51d2bd4 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -19,6 +19,8 @@ riscv_ss.add(files( 'gdbstub.c', )) =20 +riscv_stubs_ss =3D ss.source_set() + riscv_system_ss =3D ss.source_set() riscv_system_ss.add(files( 'arch_dump.c', @@ -33,3 +35,4 @@ subdir('kvm') =20 target_arch +=3D {'riscv': riscv_ss} target_system_arch +=3D {'riscv': riscv_system_ss} +target_stubs_arch +=3D {'riscv': riscv_stubs_ss} --=20 2.52.0 From nobody Sat Sep 26 20:53:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Date: Fri, 18 Sep 2026 00:05:01 +0200 Subject: [PATCH v5 07/11] hw/riscv: Define SiFive E/U CPUs using runtime conditions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-hw-riscv-cpu-int-v5-7-f98c5a244636@rev.ng> References: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> In-Reply-To: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , qemu-riscv@nongnu.org, daniel.barboza@oss.qualcomm.com, philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com, Chao Liu X-Developer-Signature: v=1; a=ed25519-sha256; t=1789682743; l=5281; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=Q90V/MFI44KOgxihm0cIMXrVnnoPikfVf+Znrq0exHg=; b=/ZjopVeLZBgZegKRQ0XOq92kpGM/lqTXGvX+J0DQNJ41jM0pEtitm2zbQBk4Q/citLReQo53M t77pdFwyPX0AYIazUcssDQ8glYFuUmBtZAdopa6aqp/NviT+KaVZZnX X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1789682501411158500 Macros are removed and replaced with inlined ternary statements. The now empty sifive_cpu.h header is then removed. Reviewed-by: Chao Liu Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- include/hw/riscv/sifive_cpu.h | 31 ------------------------------- include/hw/riscv/sifive_e.h | 1 - include/hw/riscv/sifive_u.h | 1 - hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 7 +++++-- 5 files changed, 7 insertions(+), 36 deletions(-) diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h deleted file mode 100644 index 136799633a..0000000000 --- a/include/hw/riscv/sifive_cpu.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * SiFive CPU types - * - * Copyright (c) 2017 SiFive, Inc. - * Copyright (c) 2019 Bin Meng - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or - * more details. - * - * You should have received a copy of the GNU General Public License along= with - * this program. If not, see . - */ - -#ifndef HW_SIFIVE_CPU_H -#define HW_SIFIVE_CPU_H - -#if defined(TARGET_RISCV32) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 -#elif defined(TARGET_RISCV64) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 -#endif - -#endif /* HW_SIFIVE_CPU_H */ diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 4cf902ebc0..0f0d407d5d 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -20,7 +20,6 @@ #define HW_SIFIVE_E_H =20 #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_cpu.h" #include "hw/gpio/sifive_gpio.h" #include "hw/misc/sifive_e_aon.h" #include "hw/core/boards.h" diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index aed966a62d..c12cf22b41 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -24,7 +24,6 @@ #include "hw/dma/sifive_pdma.h" #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_cpu.h" #include "hw/gpio/sifive_gpio.h" #include "hw/misc/sifive_u_otp.h" #include "hw/misc/sifive_u_prci.h" diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 35ed7f42a4..1b6f9ab4fe 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -150,7 +150,8 @@ static void sifive_e_machine_class_init(ObjectClass *oc= , const void *data) mc->desc =3D "RISC-V Board compatible with SiFive E SDK"; mc->init =3D sifive_e_machine_init; mc->max_cpus =3D 1; - mc->default_cpu_type =3D SIFIVE_E_CPU; + mc->default_cpu_type =3D (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_E51 + : TYPE_RISCV_CPU_SIFIVE_E31; mc->default_ram_id =3D "riscv.sifive.e.ram"; mc->default_ram_size =3D sifive_e_memmap[SIFIVE_E_DEV_DTIM].size; =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b7d5e7b4da..344f3d915d 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -661,7 +661,8 @@ static void sifive_u_machine_class_init(ObjectClass *oc= , const void *data) mc->init =3D sifive_u_machine_init; mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; - mc->default_cpu_type =3D SIFIVE_U_CPU; + mc->default_cpu_type =3D (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_U54 + : TYPE_RISCV_CPU_SIFIVE_U34; mc->default_cpus =3D mc->min_cpus; mc->default_ram_id =3D "riscv.sifive.u.ram"; mc->auto_create_sdcard =3D true; @@ -693,6 +694,8 @@ type_init(sifive_u_machine_init_register_types) static void sifive_u_soc_instance_init(Object *obj) { SiFiveUSoCState *s =3D RISCV_U_SOC(obj); + const char *e_cpu_type =3D (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_= E51 + : TYPE_RISCV_CPU_SIFIVE_E3= 1; =20 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUS= TER); qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); @@ -701,7 +704,7 @@ static void sifive_u_soc_instance_init(Object *obj) TYPE_RISCV_HART_ARRAY); qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); - qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); + qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", e_cpu_type); qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); =20 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUS= TER); --=20 2.52.0 From nobody Sat Sep 26 20:53:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1789682575355994.5199041491129; Thu, 17 Sep 2026 15:02:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x7KBA-0004ls-A1; Thu, 17 Sep 2026 18:02:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x7K9M-00044v-8q; Thu, 17 Sep 2026 18:00:20 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x7K9K-0004KY-CC; Thu, 17 Sep 2026 18:00:11 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=8nJcvvqd+Hg+FjZrfe3++opvD9OVCxHnuP26Jht2yAY=; b=XlL6nGKmT5qVhVX uwtuZ6Xyww0jj0fzwGCKKZIeLSvI+QG5JiaF8JBWqdb9PzPmIGsnt7olJW9t9phdfIDnXk4lBd7PP sZMzt2mWswJf5d6sOURlm5hyQq8OaHpO/ef547RARYoOTT5c50YJIvyzlGZHia2aDGcJG2uJIcUO9 dY=; Date: Fri, 18 Sep 2026 00:05:02 +0200 Subject: [PATCH v5 08/11] hw/riscv: Tenstorrent Atlantis, use hwaddr/vaddr over target_ulong MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-hw-riscv-cpu-int-v5-8-f98c5a244636@rev.ng> References: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> In-Reply-To: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , qemu-riscv@nongnu.org, daniel.barboza@oss.qualcomm.com, philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com X-Developer-Signature: v=1; a=ed25519-sha256; t=1789682743; l=999; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=f2Ng0h49pq1ktTNS5/7JFSoKMmoWzjr68AjcVaZ2T7Y=; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- hw/riscv/tt_atlantis.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 8a219afef7..b2333e7f6a 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -427,7 +427,8 @@ static void tt_atlantis_machine_done(Notifier *n, void = *data) MachineState *machine =3D MACHINE(ams); hwaddr start_addr =3D s->memmap[TT_ATL_DDR_LO].base; hwaddr mem_size; - target_ulong firmware_end_addr, kernel_start_addr; + hwaddr firmware_end_addr; + vaddr kernel_start_addr; const char *firmware_name =3D riscv_default_firmware_name(&s->cpus); uint64_t fdt_load_addr; uint64_t kernel_entry; --=20 2.52.0 From nobody Sat Sep 26 20:53:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=X0coV+oi3hvoEbKAiwh+e4SUhuLgaoL2aJO66pAXpEo=; b=I9CXymp5pFXjXOV Z7ryk/lehJ81WbAeJwcExePPWfG56L6qH3IWrNEowkoP5PLXGiq2vscXjFS7I+zNRaSplFrZt2l70 dc5Pygan3Vv52X11H8fLpzU33X1UPosq5LL2u5HYhfFkR9JzkqBL1zMrM4tTNvqpQID9mk5qDtkyh ec=; Date: Fri, 18 Sep 2026 00:05:03 +0200 Subject: [PATCH v5 09/11] target-info: Introduce target_riscv32 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-hw-riscv-cpu-int-v5-9-f98c5a244636@rev.ng> References: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> In-Reply-To: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , qemu-riscv@nongnu.org, daniel.barboza@oss.qualcomm.com, philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com X-Developer-Signature: v=1; a=ed25519-sha256; t=1789682744; l=1209; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=7XxnFUSw4Is9LNbqT940ttli+604jlutDoDE238ejgI=; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/qemu/target-info.h | 7 +++++++ target-info.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index b23e5bc586..c09e5d2a3e 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -91,6 +91,13 @@ bool target_ppc64(void); */ bool target_s390x(void); =20 +/** + * target_riscv32: + * + * Returns whether the target architecture is riscv32 + */ +bool target_riscv32(void); + /** * target_riscv64: * diff --git a/target-info.c b/target-info.c index 012b384036..bba4503151 100644 --- a/target-info.c +++ b/target-info.c @@ -89,6 +89,11 @@ bool target_s390x(void) return target_arch() =3D=3D SYS_EMU_TARGET_S390X; } =20 +bool target_riscv32(void) +{ + return target_arch() =3D=3D SYS_EMU_TARGET_RISCV32; +} + bool target_riscv64(void) { return target_arch() =3D=3D SYS_EMU_TARGET_RISCV64; --=20 2.52.0 From nobody Sat Sep 26 20:53:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=mMRpVMSst98vUE1cTbcc1vWeWwbqgmyfGyzpZB5Y+BQ=; b=Das+0dYTzD/fB3K YFyqy5p0g1w2ERVLPo18lUCHfpoDUBTiPHI9j50mr4INpNryey8ejGnhWXVZA4Y/lOIE1dEcbXn8l D48UGuVrDAnqaDsSx+6d50uhT/AAc21Ik4BMJtigDUUqHwJsgw0Nhav9kCU7R03ap/SUUjGp/GVJD vk=; Date: Fri, 18 Sep 2026 00:05:04 +0200 Subject: [PATCH v5 10/11] hw/riscv: Filter for 32- or 64-bit machine types MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-hw-riscv-cpu-int-v5-10-f98c5a244636@rev.ng> References: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> In-Reply-To: <20260918-hw-riscv-cpu-int-v5-0-f98c5a244636@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , qemu-riscv@nongnu.org, daniel.barboza@oss.qualcomm.com, philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com X-Developer-Signature: v=1; a=ed25519-sha256; t=1789682744; l=8455; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=UBmbIKF8k5MDtsnP+GDSom1GqHBRktVVsp7PYnJ2xtY=; b=jJ+DyBf0llhQcjtOTOHGWjaQ/PDf/nSqL8Ry+P/ELYtZXZe6KSF8/MjRfL/5rGemILOviKb9Z 2rTITjiFZGiDiCwusB49MUrmYL7hJMOaFkNun9Zei51Ti33jDBJcGWT X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1789682599440158500 Filters for 32- or 64-bit machine types using TypeInfo::is_available, machines available for both 32-bit and 64-bit (amd-microblaze-v-generic, sifive-[e|u], spike, virt) leave the field unset. For boston-aia, DEFINE_MACHINE() has been inlined to set is_available. Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- hw/riscv/boston-aia.c | 34 ++++++++++++++++++++-------------- hw/riscv/k230.c | 3 +++ hw/riscv/microchip_pfsoc.c | 3 +++ hw/riscv/opentitan.c | 3 +++ hw/riscv/shakti_c.c | 3 +++ hw/riscv/tt_atlantis.c | 3 +++ hw/riscv/xiangshan_kmh.c | 3 +++ 7 files changed, 38 insertions(+), 14 deletions(-) diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c index b90da096ea..ba16b7dbc6 100644 --- a/hw/riscv/boston-aia.c +++ b/hw/riscv/boston-aia.c @@ -10,6 +10,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/target-info.h" #include "qemu/units.h" =20 #include "hw/core/boards.h" @@ -263,18 +264,6 @@ static const MemoryRegionOps boston_platreg_ops =3D { }, }; =20 -static const TypeInfo boston_device =3D { - .name =3D TYPE_MIPS_BOSTON_AIA, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(BostonState), -}; - -static void boston_register_types(void) -{ - type_register_static(&boston_device); -} -type_init(boston_register_types) - #define NUM_INSNS 6 static void gen_firmware(uint32_t *p) { @@ -462,8 +451,9 @@ static void boston_mach_init(MachineState *machine) } } =20 -static void boston_mach_class_init(MachineClass *mc) +static void boston_mach_class_init(ObjectClass *oc, const void *data) { + MachineClass *mc =3D MACHINE_CLASS(oc); mc->desc =3D "MIPS Boston-aia"; mc->init =3D boston_mach_init; mc->block_default_type =3D IF_IDE; @@ -473,4 +463,20 @@ static void boston_mach_class_init(MachineClass *mc) mc->default_cpu_type =3D TYPE_RISCV_CPU_MIPS_P8700; } =20 -DEFINE_MACHINE("boston-aia", boston_mach_class_init) +static const TypeInfo boston_types[] =3D { + { + .name =3D TYPE_MIPS_BOSTON_AIA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(BostonState), + .is_available =3D target_riscv64, + }, + { + .name =3D MACHINE_TYPE_NAME("boston-aia"), + .parent =3D TYPE_MACHINE, + .class_init =3D boston_mach_class_init, + .instance_size =3D sizeof(MachineState), + .is_available =3D target_riscv64, + }, +}; + +DEFINE_TYPES(boston_types) diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c index 1e4ca38579..43b6ae6d2f 100644 --- a/hw/riscv/k230.c +++ b/hw/riscv/k230.c @@ -17,6 +17,7 @@ #include "cpu-qom.h" #include "qemu/cutils.h" #include "qemu/error-report.h" +#include "qemu/target-info.h" #include "qapi/error.h" #include "system/device_tree.h" #include "system/system.h" @@ -420,6 +421,7 @@ static const TypeInfo k230_soc_type_info =3D { .instance_size =3D sizeof(K230SoCState), .instance_init =3D k230_soc_init, .class_init =3D k230_soc_class_init, + .is_available =3D target_riscv64, }; =20 static void k230_soc_register_types(void) @@ -558,6 +560,7 @@ static const TypeInfo k230_machine_typeinfo =3D { .class_init =3D k230_machine_class_init, .instance_init =3D k230_machine_instance_init, .instance_size =3D sizeof(K230MachineState), + .is_available =3D target_riscv64, }; =20 static void k230_machine_init_register_types(void) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index edd29626fa..b2991e5a71 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -38,6 +38,7 @@ #include "qemu/error-report.h" #include "qemu/units.h" #include "qemu/cutils.h" +#include "qemu/target-info.h" #include "qapi/error.h" #include "qapi/visitor.h" #include "hw/core/boards.h" @@ -504,6 +505,7 @@ static const TypeInfo microchip_pfsoc_soc_type_info =3D= { .instance_size =3D sizeof(MicrochipPFSoCState), .instance_init =3D microchip_pfsoc_soc_instance_init, .class_init =3D microchip_pfsoc_soc_class_init, + .is_available =3D target_riscv64, }; =20 static void microchip_pfsoc_soc_register_types(void) @@ -757,6 +759,7 @@ static const TypeInfo microchip_icicle_kit_machine_type= info =3D { .class_init =3D microchip_icicle_kit_machine_class_init, .instance_init =3D microchip_icicle_kit_machine_instance_init, .instance_size =3D sizeof(MicrochipIcicleKitState), + .is_available =3D target_riscv64, }; =20 static void microchip_icicle_kit_machine_init_register_types(void) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 8cd660dd41..c3a563db92 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "qemu/cutils.h" +#include "qemu/target-info.h" #include "hw/riscv/opentitan.h" #include "qapi/error.h" #include "qemu/error-report.h" @@ -332,11 +333,13 @@ static const TypeInfo open_titan_types[] =3D { .instance_size =3D sizeof(LowRISCIbexSoCState), .instance_init =3D lowrisc_ibex_soc_init, .class_init =3D lowrisc_ibex_soc_class_init, + .is_available =3D target_riscv32, }, { .name =3D TYPE_OPENTITAN_MACHINE, .parent =3D TYPE_MACHINE, .instance_size =3D sizeof(OpenTitanState), .class_init =3D opentitan_machine_class_init, + .is_available =3D target_riscv32, } }; =20 diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 3b6efd25be..76cfe30918 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -21,6 +21,7 @@ #include "hw/riscv/shakti_c.h" #include "qapi/error.h" #include "qemu/error-report.h" +#include "qemu/target-info.h" #include "hw/intc/sifive_plic.h" #include "hw/intc/riscv_aclint.h" #include "system/system.h" @@ -97,6 +98,7 @@ static const TypeInfo shakti_c_machine_type_info =3D { .class_init =3D shakti_c_machine_class_init, .instance_init =3D shakti_c_machine_instance_init, .instance_size =3D sizeof(ShaktiCMachineState), + .is_available =3D target_riscv64, }; =20 static void shakti_c_machine_type_info_register(void) @@ -186,6 +188,7 @@ static const TypeInfo shakti_c_type_info =3D { .class_init =3D shakti_c_soc_class_init, .instance_init =3D shakti_c_soc_instance_init, .instance_size =3D sizeof(ShaktiCSoCState), + .is_available =3D target_riscv64, }; =20 static void shakti_c_type_info_register(void) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index b2333e7f6a..f54eb942f3 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -11,6 +11,7 @@ #include "qemu/cutils.h" #include "qemu/error-report.h" #include "qemu/guest-random.h" +#include "qemu/target-info.h" #include "qemu/units.h" =20 #include "hw/core/boards.h" @@ -694,11 +695,13 @@ static const TypeInfo tt_atlantis_types[] =3D { .instance_size =3D sizeof(TTAtlantisSoCState), .instance_init =3D tt_atlantis_soc_init, .class_init =3D tt_atlantis_soc_class_init, + .is_available =3D target_riscv64, }, { .name =3D MACHINE_TYPE_NAME("tt-atlantis"), .parent =3D TYPE_MACHINE, .class_init =3D tt_atlantis_machine_class_init, .instance_size =3D sizeof(TTAtlantisState), + .is_available =3D target_riscv64, }, }; =20 diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index a234c5f352..f2383c5399 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -30,6 +30,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/target-info.h" #include "qapi/error.h" #include "system/address-spaces.h" #include "hw/core/boards.h" @@ -157,6 +158,7 @@ static const TypeInfo xiangshan_kmh_soc_info =3D { .instance_size =3D sizeof(XiangshanKmhSoCState), .instance_init =3D xiangshan_kmh_soc_instance_init, .class_init =3D xiangshan_kmh_soc_class_init, + .is_available =3D target_riscv64, }; =20 static void xiangshan_kmh_soc_register_types(void) @@ -220,6 +222,7 @@ static const TypeInfo xiangshan_kmh_machine_info =3D { .parent =3D TYPE_MACHINE, .instance_size =3D sizeof(XiangshanKmhState), .class_init =3D xiangshan_kmh_machine_class_init, + .is_available =3D target_riscv64, }; =20 static void xiangshan_kmh_machine_register_types(void) --=20 2.52.0 From nobody Sat Sep 26 20:53:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=ed25519-sha256; t=1789682744; l=3555; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=9j6u0VO1MNm6eSXRDfR+CmzXxXhtVlrF3pwysoMdPag=; b=GTZP2z3FZuQe1QsF83JwnY0QSoja0HiLRegCeWZC37Cjuf1Fs1oE97f7lz8JOdatnBEN3TpTq O+gEJcWoFUvDjF6JO5QO/7i+7Hut/MKKcyiwku64hSRGFH0fmHKrvQf X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1789682589135158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- hw/riscv/meson.build | 47 ++++++++++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 7aa3c1578d..b53661cf31 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -1,25 +1,26 @@ -riscv_ss =3D ss.source_set() -riscv_ss.add(files('aia.c')) -riscv_ss.add(files('boot.c')) -riscv_ss.add(files('device-common.c')) -riscv_ss.add(files('fdt-common.c')) -riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) -riscv_ss.add(files('riscv_hart.c')) -riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) -riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) -riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) -riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) -riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs= oc.c')) -riscv_ss.add(when: 'CONFIG_TENSTORRENT', if_true: files('tt_atlantis.c')) -riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) -riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files( +riscv_common_ss =3D ss.source_set() +riscv_common_ss.add(files('aia.c')) +riscv_common_ss.add(files('boot.c')) +riscv_common_ss.add(files('device-common.c')) +riscv_common_ss.add(files('fdt-common.c')) +riscv_common_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) +riscv_common_ss.add(files('riscv_hart.c')) +riscv_common_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'= )) +riscv_common_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) +riscv_common_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) +riscv_common_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) +riscv_common_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) +riscv_common_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) +riscv_common_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microc= hip_pfsoc.c')) +riscv_common_ss.add(when: 'CONFIG_TENSTORRENT', if_true: files('tt_atlanti= s.c')) +riscv_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c= ')) +riscv_common_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files( 'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-h= pm.c')) -riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-gen= eric.c')) -riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan= _kmh.c')) -riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c')) -riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'= )) -riscv_ss.add(when: 'CONFIG_K230', if_true: files('k230.c')) +riscv_common_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaz= e-v-generic.c')) +riscv_common_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xi= angshan_kmh.c')) =20 -hw_arch +=3D {'riscv': riscv_ss} +riscv_common_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c')) +riscv_common_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston= -aia.c')) +riscv_common_ss.add(when: 'CONFIG_K230', if_true: files('k230.c')) + +hw_common_arch +=3D {'riscv': riscv_common_ss} --=20 2.52.0