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Thu, 17 Sep 2026 02:33:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 01/13] tcg: add tcg_gen_goto_jc{3}_{i32,i64,tl} Date: Wed, 16 Sep 2026 23:32:55 -1000 Message-ID: <20260917093307.1092084-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917093307.1092084-1-richard.henderson@linaro.org> References: <20260917093307.1092084-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:30::10; envelope-from=richard.henderson@linaro.org; helo=mail-oa2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789637623893158500 Content-Type: text/plain; charset="utf-8" From: Matt Turner At translation time the caller often already has the destination PC in a temp and knows the flags, cflags and cs_base any destination it may reach has to match because they are the same as the ones as the current block being generated. But the promise that the flags are known (or unchanged) is subtle. So add new entry points with new semantics and --enable-debug-tcg checks against get_tb_cpu_state() at run time. Signed-off-by: Matt Turner [rth: Split out target changes; add jc3 variant; expand via tcg-op-def.h.in= c] Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- accel/tcg/tcg-runtime.h | 4 +++ include/tcg/tcg-op-common.h | 29 +++++++++++++++++++ include/tcg/tcg-op.h | 4 +++ include/tcg/tcg-op-def.h.inc | 2 ++ accel/tcg/cpu-exec.c | 27 ++++++++++++++++++ tcg/tcg-op.c | 55 ++++++++++++++++++++++++++++++++---- 6 files changed, 115 insertions(+), 6 deletions(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 0dda2079fd0..098c2235b5f 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -9,6 +9,10 @@ DEF_HELPER_FLAGS_1(ctpop_i64, TCG_CALL_NO_RWG_SE, i64, i64) =20 DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, cptr, env) =20 +#ifdef CONFIG_DEBUG_TCG +DEF_HELPER_FLAGS_4(goto_jc_check, TCG_CALL_NO_WG, void, env, i64, i64, i32) +#endif + DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env) =20 #ifndef IN_HELPER_PROTO diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 2bcf737aa56..5102f9bb4dd 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -85,6 +85,35 @@ void tcg_gen_goto_tb(unsigned idx); */ void tcg_gen_lookup_and_goto_ptr(void); =20 +/** + * tcg_gen_goto_jc3_i32() - dispatch to the destination TB via the jump ca= che + * tcg_gen_goto_jc3_i64() - dispatch to the destination TB via the jump ca= che + * @pc: temp holding the destination guest PC + * @cs_base: temp holding the destination guest cs_base + * @flags: the destination guest flags + * + * The contract is that the values provided inline are exactly the + * cpu state that would be returned by TCGCPUOps::get_tb_cpu_state. + * --enable-debug-tcg checks the contract at runtime. + * + * Using those values, the lookup may be done inline. + * + * Actually declared and defined via tcg-op-def.h.inc. + */ + +/** + * tcg_gen_goto_jc_i32() - dispatch to the destination TB via the jump cac= he + * tcg_gen_goto_jc_i64() - dispatch to the destination TB via the jump cac= he + * @pc: temp holding the destination guest PC + * + * Similar, but cs_base and flags are taken from the current TB. + * + * Thus the contract is that no cpu state changes have occured + * that affect the translation block flags. + * + * Actually declared and defined via tcg-op-def.h.inc. + */ + void tcg_gen_plugin_cb(unsigned from); QEMU_ARG_NONNULL void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned meminf= o); =20 diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index a7d001c959c..02732652b8f 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -175,6 +175,8 @@ typedef TCGv_i64 TCGv; #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64 #define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec #define tcg_gen_dup_tl tcg_gen_dup_i64 +#define tcg_gen_goto_jc_tl tcg_gen_goto_jc_i64 +#define tcg_gen_goto_jc3_tl tcg_gen_goto_jc3_i64 #define dup_const_tl dup_const #else #define tcg_gen_movi_tl tcg_gen_movi_i32 @@ -299,6 +301,8 @@ typedef TCGv_i64 TCGv; #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32 #define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec #define tcg_gen_dup_tl tcg_gen_dup_i32 +#define tcg_gen_goto_jc_tl tcg_gen_goto_jc_i32 +#define tcg_gen_goto_jc3_tl tcg_gen_goto_jc3_i32 =20 #define dup_const_tl(VECE, C) \ (__builtin_constant_p(VECE) \ diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index b60edca6e42..97024fcb222 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -31,6 +31,8 @@ DEF2(ext16u, TCGV, TCGV) DEF4(extract, TCGV, TCGV, unsigned, unsigned) DEF4(extract2, TCGV, TCGV, TCGV, unsigned) DEF3(eqv, TCGV, TCGV, TCGV) +DEF1(goto_jc, TCGV) +DEF3(goto_jc3, TCGV, TCGv_i64, unsigned) DEF3(ld, TCGV, TCGv_ptr, tcg_target_long) DEF3(ld8s, TCGV, TCGv_ptr, tcg_target_long) DEF3(ld8u, TCGV, TCGv_ptr, tcg_target_long) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5226cfb7650..1493fe0c963 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -407,6 +407,33 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) return tb->tc.ptr; } =20 +#ifdef CONFIG_DEBUG_TCG +/** + * helper_goto_jc_check: check the contract of tcg_gen_goto_jc_*() + * @env: current cpu state + * @pc: the destination pc the caller passed at translation time + * @cs_base: the cs_base the dispatching block was translated with + * @flags: the flags the dispatching block was translated with + * + * A goto_jc looks the destination up on the caller's @pc with the flags a= nd + * cs_base of the block doing the dispatching, so all three have to be what + * get_tb_cpu_state() reports by the time the dispatch runs. That is a + * property of the translator, not of the generated code, so check it here + * rather than leaving a target that gets it wrong to be debugged as a blo= ck + * running with someone else's flags. + */ +void HELPER(goto_jc_check)(CPUArchState *env, uint64_t pc, uint64_t cs_bas= e, + uint32_t flags) +{ + CPUState *cpu =3D env_cpu(env); + TCGTBCPUState s =3D cpu->cc->tcg_ops->get_tb_cpu_state(cpu); + + assert(s.pc =3D=3D pc); + assert(s.flags =3D=3D flags); + assert(s.cs_base =3D=3D cs_base); +} +#endif + /* Return the current PC from CPU, which may be cached in TB. */ static vaddr log_pc(CPUState *cpu, const TranslationBlock *tb) { diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index d271d83a7d2..09d9a7963ae 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -277,6 +277,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo) #define DEF6(NAME, T1, T2, T3, T4, T5, T6) \ QEMU_ARG_NONNULL static void glue(gen_,NAME)(TCGType, T1, T2, T3, T4, = T5, T6); =20 +#define TCGv_i64 TCGTemp * #define TCGv_ptr TCGTemp * #define TCGV TCGTemp * #define TINT int64_t @@ -286,6 +287,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo) #undef TINT #undef TCGV #undef TCGv_ptr +#undef TCGv_i64 =20 #undef DEF1 #undef DEF2 @@ -1940,20 +1942,61 @@ void tcg_gen_goto_tb(unsigned idx) tcg_gen_op1i(INDEX_op_goto_tb, 0, idx); } =20 +static void gen_lookup_tb_ptr_and_goto(void) +{ + TCGv_ptr ptr =3D tcg_temp_ebb_new_ptr(); + + gen_helper_lookup_tb_ptr(ptr, tcg_env); + tcg_gen_op1i(INDEX_op_goto_ptr, TCG_TYPE_PTR, tcgv_ptr_arg(ptr)); + tcg_temp_free_ptr(ptr); +} + void tcg_gen_lookup_and_goto_ptr(void) { - TCGv_ptr ptr; - if (tcg_ctx->gen_tb->cflags & CF_NO_GOTO_PTR) { tcg_gen_exit_tb(NULL, 0); return; } =20 plugin_gen_disable_mem_helpers(); - ptr =3D tcg_temp_ebb_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, tcg_env); - tcg_gen_op1i(INDEX_op_goto_ptr, TCG_TYPE_PTR, tcgv_ptr_arg(ptr)); - tcg_temp_free_ptr(ptr); + gen_lookup_tb_ptr_and_goto(); +} + +static void gen_goto_jc3(TCGType type, TCGTemp *pc, + TCGTemp *cs_base, unsigned flags) +{ + plugin_gen_disable_mem_helpers(); + + /* + * Widen @pc to i64 because the jump cache is keyed on a vaddr; + * for a 32-bit guest PC that is its zero extension. + * Note that cs_base is target-specific, not a vaddr, and always 64-bi= t. + */ + if (type =3D=3D TCG_TYPE_I32) { + TCGTemp *pc64 =3D tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB); + gen_extu_i32_i64(pc64, pc); + pc =3D pc64; + } + +#ifdef CONFIG_DEBUG_TCG + /* + * The caller has asserted that no flags-affecting cpu state changes + * happened between this TB and the destination. Check it. + */ + gen_helper_goto_jc_check(tcg_env, temp_tcgv_i64(pc), + temp_tcgv_i64(cs_base), + tcg_constant_i32(flags)); +#endif + + gen_lookup_tb_ptr_and_goto(); +} + +static void gen_goto_jc(TCGType type, TCGTemp *pc) +{ + const TranslationBlock *tb =3D tcg_ctx->gen_tb; + TCGTemp *cs_base =3D tcg_constant_internal(TCG_TYPE_I64, tb->cs_base); + + gen_goto_jc3(type, pc, cs_base, tb->flags); } =20 /* --=20 2.53.0 From nobody Sat Sep 26 20:52:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789637707; cv=none; d=zohomail.com; s=zohoarc; b=PQpQ+mwMDV9R69WfUNSZcVbNF0B3cWMdb83PcZ3gBt6J+Zw0AWV/QFo8X33V5XNx0gjVuEq6JaJCDgBhBu9JoXlsAjBE0MNbCY7Hvl3xXCuOwKzdThC+XpVVCEC7SgpNiVSlTXnaZt5SALcJlPBjgcLV7xVWagCROgNkJUff0RU= ARC-Message-Signature: i=1; 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Thu, 17 Sep 2026 02:33:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 02/13] target/alpha: Use tcg_gen_goto_jc{3}_i64 Date: Wed, 16 Sep 2026 23:32:56 -1000 Message-ID: <20260917093307.1092084-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917093307.1092084-1-richard.henderson@linaro.org> References: <20260917093307.1092084-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:31::e; envelope-from=richard.henderson@linaro.org; helo=mail-oo2-x0e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789637708167158500 Content-Type: text/plain; charset="utf-8" We can use tcg_gen_goto_jc_i64 for direct or indirect branches, where flags are known to not change. We can use tcg_gen_goto_jc3_i64 in gen_call_pal where flags are known to change in a very specific way. Introduce DISAS_PC_STALE_NOJC as a case where flags are changing in an unpredictable way and must therefore use the runtime lookup. Introduce DISAS_PC_STALE_NOCHAIN as a case where we must return to the main loop. Remove DISAS_PC_STALE and use DISAS_TOO_MANY instead, as they wind up having the same semantics. End the translation block when setting PS or FEN, as they represent changes in tbflags. This avoids a subsequent insn incorrectly chaining via the jump cache and failing the assert. Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- target/alpha/translate.c | 60 ++++++++++++++++++++++------------------ 1 file changed, 33 insertions(+), 27 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 6f18b8d1af6..ecb4ac4b023 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -80,9 +80,10 @@ struct DisasContext { /* Target-specific return values from translate_one, indicating the state of the TB. Note that DISAS_NEXT indicates that we are not exiting the TB. */ -#define DISAS_PC_UPDATED_NOCHAIN DISAS_TARGET_0 -#define DISAS_PC_UPDATED DISAS_TARGET_1 -#define DISAS_PC_STALE DISAS_TARGET_2 +#define DISAS_PC_UPDATED DISAS_TARGET_0 +#define DISAS_PC_STALE_NOJC DISAS_TARGET_1 +#define DISAS_PC_STALE_NOCHAIN DISAS_TARGET_2 +#define DISAS_PC_UPDATED_NOCHAIN DISAS_TARGET_3 =20 /* global register indexes */ static TCGv_i64 cpu_std_ir[31]; @@ -449,7 +450,7 @@ static void gen_goto_tb(DisasContext *ctx, unsigned tb_= slot_idx, int32_t disp) tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx); } else { gen_pc_disp(ctx, cpu_pc, disp); - tcg_gen_lookup_and_goto_ptr(); + tcg_gen_goto_jc_i64(cpu_pc); } } =20 @@ -1096,8 +1097,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, = int palcode) } =20 /* Allow interrupts to be recognized right away. */ - gen_pc_disp(ctx, cpu_pc, 0); - return DISAS_PC_UPDATED_NOCHAIN; + return DISAS_PC_STALE_NOCHAIN; =20 case 0x36: /* RDPS */ @@ -1148,6 +1148,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, = int palcode) tcg_gen_ori_i64(tmp, tmp, 1); } else { st_flag_byte(tcg_constant_i64(1), ENV_FLAG_PAL_SHIFT); + ctx->tbflags =3D deposit32(ctx->tbflags, ENV_FLAG_PAL_SHIFT, 8= , 1); } tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUAlphaState, exc_addr)); =20 @@ -1156,7 +1157,9 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, = int palcode) palcode & 0x80 ? 0x2000 + (palcode - 0x80) * 64 : 0x1000 + palcode * 64); - return DISAS_PC_UPDATED; + + tcg_gen_goto_jc3_i64(cpu_pc, load_zero(ctx), ctx->tbflags); + return DISAS_NORETURN; } #endif } @@ -1191,8 +1194,7 @@ static int cpu_pr_data(int pr) =20 static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv_i64 va, int regno) { - void (*helper)(TCGv_i64); - int data; + int data, ret =3D DISAS_NEXT; =20 switch (regno) { case 32 ... 39: @@ -1202,17 +1204,16 @@ static DisasJumpType gen_mfpr(DisasContext *ctx, TC= Gv_i64 va, int regno) break; =20 case 250: /* WALLTIME */ - helper =3D gen_helper_get_walltime; - goto do_helper; - case 249: /* VMTIME */ - helper =3D gen_helper_get_vmtime; - do_helper: if (translator_io_start(&ctx->base)) { - helper(va); - return DISAS_PC_STALE; - } else { - helper(va); + ret =3D DISAS_TOO_MANY; /* i/o insns must be last in tb */ } + gen_helper_get_walltime(va); + break; + case 249: /* VMTIME */ + if (translator_io_start(&ctx->base)) { + ret =3D DISAS_TOO_MANY; /* i/o insns must be last in tb */ + } + gen_helper_get_vmtime(va); break; =20 case 0: /* PS */ @@ -1236,7 +1237,7 @@ static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv= _i64 va, int regno) break; } =20 - return DISAS_NEXT; + return ret; } =20 static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv_i64 vb, int regno) @@ -1264,12 +1265,12 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TC= Gv_i64 vb, int regno) case 252: /* HALT */ gen_helper_halt(vb); - return DISAS_PC_STALE; + return DISAS_PC_STALE_NOCHAIN; =20 case 251: /* ALARM */ if (translator_io_start(&ctx->base)) { - ret =3D DISAS_PC_STALE; + ret =3D DISAS_TOO_MANY; /* i/o insns must be last in tb */ } gen_helper_set_alarm(tcg_env, vb); break; @@ -1287,10 +1288,11 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TC= Gv_i64 vb, int regno) =20 case 0: /* PS */ st_flag_byte(vb, ENV_FLAG_PS_SHIFT); - break; + return DISAS_PC_STALE_NOJC; /* flags updated */ + case 1: /* FEN */ st_flag_byte(vb, ENV_FLAG_FEN_SHIFT); - break; + return DISAS_PC_STALE_NOJC; /* flags updated */ =20 default: /* The basic registers are data only, and unknown registers @@ -2289,7 +2291,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) /* RPCC */ va =3D dest_gpr(ctx, ra); if (translator_io_start(&ctx->base)) { - ret =3D DISAS_PC_STALE; + ret =3D DISAS_TOO_MANY; /* i/o insns must be last in tb */ } gen_helper_load_pcc(va, tcg_env); break; @@ -2905,12 +2907,16 @@ static void alpha_tr_tb_stop(DisasContextBase *dcba= se, CPUState *cpu) case DISAS_TOO_MANY: gen_goto_tb(ctx, 0, 0); break; - case DISAS_PC_STALE: - gen_pc_disp(ctx, cpu_pc, 0); - /* FALLTHRU */ case DISAS_PC_UPDATED: + tcg_gen_goto_jc_i64(cpu_pc); + break; + case DISAS_PC_STALE_NOJC: + gen_pc_disp(ctx, cpu_pc, 0); tcg_gen_lookup_and_goto_ptr(); break; + case DISAS_PC_STALE_NOCHAIN: + gen_pc_disp(ctx, cpu_pc, 0); + /* fallthru */ case DISAS_PC_UPDATED_NOCHAIN: tcg_gen_exit_tb(NULL, 0); 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Thu, 17 Sep 2026 02:33:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 03/13] target/loongarch: Use tcg_gen_goto_jc_tl for JIRL Date: Wed, 16 Sep 2026 23:32:57 -1000 Message-ID: <20260917093307.1092084-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917093307.1092084-1-richard.henderson@linaro.org> References: <20260917093307.1092084-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:31::f; envelope-from=richard.henderson@linaro.org; helo=mail-oo2-x0f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789637716039158500 Content-Type: text/plain; charset="utf-8" From: Matt Turner Allow direct use of the jump cache for direct and indirect branches. Signed-off-by: Matt Turner [rth: Drop the change to DISAS_STOP for now. I suspect both uses should simply use DISAS_TOO_MANY.] Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- target/loongarch/tcg/translate.c | 2 +- target/loongarch/tcg/insn_trans/trans_branch.c.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/transl= ate.c index 124dce62695..b0ff1f7dff7 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -111,7 +111,7 @@ static void gen_goto_tb(DisasContext *ctx, unsigned tb_= slot_idx, vaddr dest) tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx); } else { tcg_gen_movi_tl(cpu_pc, dest); - tcg_gen_lookup_and_goto_ptr(); + tcg_gen_goto_jc_tl(cpu_pc); } } =20 diff --git a/target/loongarch/tcg/insn_trans/trans_branch.c.inc b/target/lo= ongarch/tcg/insn_trans/trans_branch.c.inc index da077786585..d4318dfa437 100644 --- a/target/loongarch/tcg/insn_trans/trans_branch.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_branch.c.inc @@ -27,7 +27,7 @@ static bool trans_jirl(DisasContext *ctx, arg_jirl *a) tcg_gen_mov_tl(cpu_pc, addr); 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Thu, 17 Sep 2026 02:33:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 04/13] target/ppc: Use tcg_gen_goto_jc_tl Date: Wed, 16 Sep 2026 23:32:58 -1000 Message-ID: <20260917093307.1092084-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917093307.1092084-1-richard.henderson@linaro.org> References: <20260917093307.1092084-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::11; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x11.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789637720076158500 Content-Type: text/plain; charset="utf-8" From: Matt Turner The only instance of mid-tb flags change occurs with spr_write_40x_dbcr0, which already uses DISAS_EXIT_UPDATE. Therefore we can always use tcg_gen_goto_jc_tl in preference to tcg_gen_lookup_and_goto_ptr. Signed-off-by: Matt Turner Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- target/ppc/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 467b8f3d4ec..a99ab018b80 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2649,7 +2649,7 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx) pmu_count_insns(ctx); } =20 - tcg_gen_lookup_and_goto_ptr(); + tcg_gen_goto_jc_tl(cpu_nip); } } =20 @@ -5164,7 +5164,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cs) pmu_count_insns(ctx); } =20 - tcg_gen_lookup_and_goto_ptr(); + tcg_gen_goto_jc_tl(cpu_nip); break; =20 case DISAS_EXIT_UPDATE: --=20 2.53.0 From nobody Sat Sep 26 20:52:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 17 Sep 2026 02:33:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 05/13] target/s390x/tcg: Remove DISAS_PC_UPDATED Date: Wed, 16 Sep 2026 23:32:59 -1000 Message-ID: <20260917093307.1092084-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917093307.1092084-1-richard.henderson@linaro.org> References: <20260917093307.1092084-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::10; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789637618060158500 Content-Type: text/plain; charset="utf-8" This value is unused. Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- target/s390x/tcg/translate.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 4eb2eba5e45..991df67a419 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1025,11 +1025,6 @@ typedef struct { =20 /* Return values from translate_one, indicating the state of the TB. */ =20 -/* We are not using a goto_tb (for whatever reason), but have updated - the PC (for whatever reason), so there's no need to do it again on - exiting the TB. */ -#define DISAS_PC_UPDATED DISAS_TARGET_0 - /* We have updated the PC and CC values. */ #define DISAS_PC_CC_UPDATED DISAS_TARGET_2 =20 @@ -6466,10 +6461,6 @@ static void s390x_tr_tb_stop(DisasContextBase *dcbas= e, CPUState *cs) break; case DISAS_TOO_MANY: update_psw_addr(dc); - /* FALLTHRU */ - case DISAS_PC_UPDATED: - /* Next TB starts off with CC_OP_DYNAMIC, so make sure the - cc op type is in env */ update_cc_op(dc); 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Thu, 17 Sep 2026 02:33:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 06/13] target/s390x/tcg: Use tcg_gen_goto_jc3_i64 for branches Date: Wed, 16 Sep 2026 23:33:00 -1000 Message-ID: <20260917093307.1092084-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917093307.1092084-1-richard.henderson@linaro.org> References: <20260917093307.1092084-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::10; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789637716089158500 Content-Type: text/plain; charset="utf-8" Introduce gen_goto_jc as a helper. Use it instead of DISAS_PC_CC_UPDATED or tcg_gen_lookup_and_goto_ptr within help_goto_direct, help_goto_indirect, and help_branch. Always return DISAS_NORETURN from those functions. Do not use goto_jc elsewhere as yet. At least op_ex, op_sacf, op_sam require other updates; icount and PER_IFETCH want to use goto_tb not goto_jc. and PER_IFETCH needs some TLC. Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- target/s390x/tcg/translate.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 991df67a419..2f3e7b36824 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -638,6 +638,15 @@ static bool use_goto_tb(DisasContext *s, uint64_t dest) return translator_use_goto_tb(&s->base, dest); } =20 +static void gen_goto_jc(DisasContext *s) +{ + /* + * ex_value, aka cs_base, is only ever live at the start of a TB + * and is immediately cleared. It is only ever set by op_ex(). + */ + tcg_gen_goto_jc3_i64(psw_addr, tcg_constant_i64(0), s->base.tb->flags); +} + static void account_noninline_branch(DisasContext *s, int cc_op) { #ifdef DEBUG_INLINE_BRANCHES @@ -1082,11 +1091,11 @@ static DisasJumpType help_goto_direct(DisasContext = *s, uint64_t dest) tcg_gen_goto_tb(0); tcg_gen_movi_i64(psw_addr, dest); tcg_gen_exit_tb(s->base.tb, 0); - return DISAS_NORETURN; } else { tcg_gen_movi_i64(psw_addr, dest); - return DISAS_PC_CC_UPDATED; + gen_goto_jc(s); } + return DISAS_NORETURN; } =20 static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) @@ -1095,7 +1104,8 @@ static DisasJumpType help_goto_indirect(DisasContext = *s, TCGv_i64 dest) per_breaking_event(s); tcg_gen_mov_i64(psw_addr, dest); per_branch(s, psw_addr); - return DISAS_PC_CC_UPDATED; + gen_goto_jc(s); + return DISAS_NORETURN; } =20 static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, @@ -1157,7 +1167,7 @@ static DisasJumpType help_branch(DisasContext *s, Dis= asCompare *c, tcg_gen_goto_tb(0); tcg_gen_exit_tb(s->base.tb, 0); } else { - tcg_gen_lookup_and_goto_ptr(); + gen_goto_jc(s); } =20 gen_set_label(lab); @@ -1167,9 +1177,10 @@ static DisasJumpType help_branch(DisasContext *s, Di= sasCompare *c, if (use_goto_tb(s, s->pc_tmp)) { tcg_gen_goto_tb(1); tcg_gen_exit_tb(s->base.tb, 1); - return DISAS_NORETURN; + } else { + gen_goto_jc(s); } - return DISAS_PC_CC_UPDATED; + return DISAS_NORETURN; } =20 /* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ --=20 2.53.0 From nobody Sat Sep 26 20:52:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Thu, 17 Sep 2026 02:33:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 07/13] accel/tcg: add CF_NO_GOTO_JC, set while a breakpoint is present Date: Wed, 16 Sep 2026 23:33:01 -1000 Message-ID: <20260917093307.1092084-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917093307.1092084-1-richard.henderson@linaro.org> References: <20260917093307.1092084-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::10; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789637696029158500 Content-Type: text/plain; charset="utf-8" From: Matt Turner The next patch dispatches a goto_jc by probing the TB jump cache from generated code. That probe cannot check everything helper_lookup_tb_ptr() checks, and the one that matters is breakpoints: check_for_breakpoints() raises EXCP_DEBUG on an exact pc match and selects CF_BP_PAGE cflags for the rest of the page, and inserting a breakpoint deliberately invalidates no TB. The probe compares the destination's cflags against the cflags of the block doing the dispatching, and only takes the destination when they are equal. So a cflag is all that is needed. Add CF_NO_GOTO_JC, set it in CPUState::tcg_cflags while cpu->breakpoints is non-empty, and blocks translated from then on both decline to dispatch inline themselves -- the next patch makes them emit the plain helper call -- and are unreachable from blocks that do, because their cflags no longer match. The two ends of the flag are cpu_breakpoint_insert() and cpu_breakpoint_remove_by_ref(), which are the only places the list changes. Both already run either on the CPU's own thread or with it stopped, or reach another CPU exactly as cpu_single_step() does, which is where the previous patch put the same kind of update. That leaves blocks translated before the breakpoint was inserted, which are still live and still chain to each other. They do so on the old cflags, so inline dispatch among them keeps working until the vCPU reaches its main loop, which then looks up with the new cflags and translates afresh. In system mode gdb inserts breakpoints with the vCPUs stopped, so there is no window at all. In user mode the window is the one goto_tb chaining already has: a chained direct jump consults nothing either, and is not broken by inserting a breakpoint. Nothing reads CF_NO_GOTO_JC yet; the next patch does. Signed-off-by: Matt Turner Signed-off-by: Richard Henderson Message-ID: <20260901034808.3524945-6-mattst88@gmail.com> Reviewed-by: Matt Turner --- include/exec/translation-block.h | 5 +++-- accel/tcg/cpu-exec-common.c | 16 ++++++++++++++-- cpu-common.c | 25 ++++++++++++++++++++++++- 3 files changed, 41 insertions(+), 5 deletions(-) diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index 40cc6990318..f3410dbcb93 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -76,14 +76,15 @@ struct TranslationBlock { #define CF_COUNT_MASK 0x000001ff #define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ #define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ -#define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */ -#define CF_MEMI_ONLY 0x00001000 /* Only instrument memory ops */ +#define CF_NO_GOTO_JC 0x00000800 /* Do not dispatch via the inline prob= e */ +#define CF_SINGLE_STEP 0x00001000 /* gdbstub single-step in effect */ #define CF_USE_ICOUNT 0x00002000 #define CF_INVALID 0x00004000 /* TB is stale. Set with @jmp_lock hel= d */ #define CF_PARALLEL 0x00008000 /* Generate code for a parallel contex= t */ #define CF_NOIRQ 0x00010000 /* Generate an uninterruptible TB */ #define CF_PCREL 0x00020000 /* Opcodes in TB are PC-relative */ #define CF_BP_PAGE 0x00040000 /* Breakpoint present in code page */ +#define CF_MEMI_ONLY 0x00080000 /* Only instrument memory ops */ #define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ #define CF_CLUSTER_SHIFT 24 =20 diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index 9f3517f36b6..9f9555e34f6 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -38,10 +38,11 @@ void tcg_cflags_set(CPUState *cpu, uint32_t flags) =20 /* * The bits of CPUState::tcg_cflags that tcg_cflags_set() never sets, beca= use - * they are derived from gdb single-step, one-insn-per-tb and -d nochain. + * they are derived from gdb single-step, one-insn-per-tb and -d nochain, + * or from various cpu parameters. */ #define CF_DERIVED (CF_COUNT_MASK | CF_NO_GOTO_TB | CF_NO_GOTO_PTR | \ - CF_SINGLE_STEP) + CF_NO_GOTO_JC | CF_SINGLE_STEP) =20 void tcg_update_cflags(CPUState *cpu) { @@ -62,6 +63,17 @@ void tcg_update_cflags(CPUState *cpu) cflags |=3D CF_NO_GOTO_TB; } =20 + /* + * A block that dispatches through the jump cache inline does not cons= ult + * cpu->breakpoints, and inserting a breakpoint deliberately invalidat= es + * nothing. Give blocks translated while one is set a distinct cflags= , so + * that they neither dispatch inline themselves nor are reached by a b= lock + * that does, and check_for_breakpoints() gets to run on every dispatc= h. + */ + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { + cflags |=3D CF_NO_GOTO_JC; + } + cpu->tcg_cflags =3D cflags; } =20 diff --git a/cpu-common.c b/cpu-common.c index adb76b3a786..909f8d059b4 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -22,6 +22,7 @@ #include "exec/cpu-common.h" #include "hw/core/cpu.h" #include "qemu/lockable.h" +#include "system/tcg.h" #include "trace/trace-root.h" =20 QemuMutex qemu_cpu_list_lock; @@ -429,6 +430,11 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int= flags, *breakpoint =3D bp; } =20 + /* The first breakpoint takes the CPU off the inline dispatch path. */ + if (tcg_enabled()) { + tcg_update_cflags(cpu); + } + trace_breakpoint_insert(cpu->cpu_index, pc, flags); return 0; } @@ -452,7 +458,7 @@ int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int = flags) } =20 /* Remove a specific breakpoint by reference. */ -void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp) +static void cpu_breakpoint_remove_by_ref_int(CPUState *cpu, CPUBreakpoint = *bp) { QTAILQ_REMOVE(&cpu->breakpoints, bp, entry); =20 @@ -460,14 +466,31 @@ void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUB= reakpoint *bp) g_free(bp); } =20 +void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp) +{ + cpu_breakpoint_remove_by_ref_int(cpu, bp); + + /* The last breakpoint puts the CPU back on the inline dispatch path. = */ + if (tcg_enabled()) { + tcg_update_cflags(cpu); + } +} + /* Remove all matching breakpoints. */ void cpu_breakpoint_remove_all(CPUState *cpu, int mask) { CPUBreakpoint *bp, *next; + bool removed =3D false; =20 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { if (bp->flags & mask) { cpu_breakpoint_remove_by_ref(cpu, bp); + removed =3D true; } } + + /* The last breakpoint puts the CPU back on the inline dispatch path. = */ + if (tcg_enabled() && removed) { + tcg_update_cflags(cpu); + } } --=20 2.53.0 From nobody Sat Sep 26 20:52:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 17 Sep 2026 02:33:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 08/13] include/exec: Move tc within TranslationBlock Date: Wed, 16 Sep 2026 23:33:02 -1000 Message-ID: <20260917093307.1092084-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917093307.1092084-1-richard.henderson@linaro.org> References: <20260917093307.1092084-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789637710165158500 Content-Type: text/plain; charset="utf-8" Move tc so that it is adjacent to cs_base, flags, cflags. This will allow the s390x backend to load them all at once. Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/exec/translation-block.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index f3410dbcb93..ad31184ee9a 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -92,12 +92,12 @@ struct TranslationBlock { * Above fields used for comparing */ =20 + struct tb_tc tc; + /* size of target code for this block (1 <=3D size <=3D TARGET_PAGE_SI= ZE) */ uint16_t size; uint16_t icount; =20 - struct tb_tc tc; - /* * Track tb_page_addr_t intervals that intersect this TB. * For user-only, the virtual addresses are always contiguous, --=20 2.53.0 From nobody Sat Sep 26 20:52:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 17 Sep 2026 02:33:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 09/13] tcg: Probe the TB jump cache inline instead of calling a helper Date: Wed, 16 Sep 2026 23:33:03 -1000 Message-ID: <20260917093307.1092084-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917093307.1092084-1-richard.henderson@linaro.org> References: <20260917093307.1092084-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:31::d; envelope-from=richard.henderson@linaro.org; helo=mail-oo2-x0d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789637653909158500 Content-Type: text/plain; charset="utf-8" From: Matt Turner Every indirect branch that cannot use goto_tb ends in a dispatch that calls helper_lookup_tb_ptr(). For an emulated compiler that is 8.4 billion helper calls in a single translation unit: 24.6% of all TB exits take this path, because jsr/ret/jmp have a register destination and because goto_tb is restricted to same-page targets. The helper itself is already tight, but each call pays for a call frame, the can_do_io store, the get_tb_cpu_state() indirect call through TCGCPUOps, curr_cflags(), and a breakpoint check, before it gets to the jump cache probe that almost always hits (95.8% for this workload). Emit the probe inline instead, for the callers that have migrated to tcg_gen_goto_jc_*(). Those supply what it needs: the destination PC is in a TCG temp, and the flags, cflags and cs_base the destination must match are constants at translation time. The fast path is therefore a hash, four guarded loads and a goto_ptr. Only a miss calls the helper, which still owns filling the cache. Two details matter for the generated code. The flags and cflags guards are folded into a single aligned 64-bit load and compare, since the fields are adjacent. And each path emits its own goto_ptr rather than branching to a shared one: a temp live across the label is spilled and reloaded on every dispatch, which cost 6.3% on its own. The flags and cflags constants are safe against the other things that can change them. CF_PARALLEL is only ever set by begin_parallel_context(), which flushes first, so no block predating it survives to dispatch. gdb single-step is only turned on with the CPU stopped, and a block translated without CF_SINGLE_STEP can only be re-entered through tb_lookup(), which from then on demands the new cflags -- so a stale-cflags block is never the one running. Breakpoints are handled by CF_NO_GOTO_JC, added by the previous patch: while one is set, blocks are translated with a cflags that both keeps them off the inline path and keeps them unreachable from blocks already on it. What is left is one_insn_per_tb and -d nochain; see below. Measured with qemu-alpha running an emulated alpha gcc 16.2.0 compiling the SQLite 3.45.1 amalgamation (255k lines, -O2) on an x86-64 host, LTO build, on top of the preceding patches: before: 1,402,667,803,616 instructions after: 916,415,123,244 instructions -34.67% before: 115.56s wall clock after: 85.59s wall clock -25.94% The gap between the two is the point at which this stops being a straight-line win: the helper call was highly predictable work that the host pipelined well, so removing it retires far fewer instructions than it saves time. IPC falls from 2.48 to 2.17 across this patch for that reason. Despite emitting more code, this also reduces instruction cache pressure, because a dispatch no longer jumps into qemu's .text and evicts translated code: before: 11,735,141,703 L1-icache-load-misses after: 7,154,863,292 L1-icache-load-misses -39.0% The mechanism is visible directly in a profile: helper_lookup_tb_ptr() falls from 31.01% of samples to 0.35%, and qemu's own .text falls from 38.8% to 5.3%, with the balance moving into generated code. Combined with the preceding patches, against an unmodified LTO build, 1,646,994,254,249 instructions fall to 916,415,123,244, or -44.36%. The emulated compiler produces byte-identical output throughout. A follow-up worth having: the probe is emitted entirely out of generic TCG ops, and several backends can do much better than the result. x86_64 and s390x have memory-operand comparisons; aarch64 can form env + off + h * 16 with a shift-add, load (tb, pc) and (cs_base, flags) with two ldp, and halve the branches with ccmp. That wants a backend expansion of a dedicated opcode, which is a separate series. Signed-off-by: Matt Turner Signed-off-by: Richard Henderson Message-ID: <20260901034808.3524945-7-mattst88@gmail.com> Reviewed-by: Matt Turner --- tcg/tcg-op.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 108 insertions(+), 2 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 09d9a7963ae..cd10a00bf9e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -28,6 +28,8 @@ #include "tcg/tcg-op-common.h" #include "exec/translation-block.h" #include "exec/plugin-gen.h" +#include "hw/core/cpu.h" +#include "../accel/tcg/tb-hash.h" #include "tcg-internal.h" #include "tcg-has.h" =20 @@ -1942,12 +1944,17 @@ void tcg_gen_goto_tb(unsigned idx) tcg_gen_op1i(INDEX_op_goto_tb, 0, idx); } =20 +static void gen_goto_ptr(TCGTemp *ptr) +{ + tcg_gen_op1(INDEX_op_goto_ptr, TCG_TYPE_PTR, temp_arg(ptr)); +} + static void gen_lookup_tb_ptr_and_goto(void) { TCGv_ptr ptr =3D tcg_temp_ebb_new_ptr(); =20 gen_helper_lookup_tb_ptr(ptr, tcg_env); - tcg_gen_op1i(INDEX_op_goto_ptr, TCG_TYPE_PTR, tcgv_ptr_arg(ptr)); + gen_goto_ptr(tcgv_ptr_temp(ptr)); tcg_temp_free_ptr(ptr); } =20 @@ -1962,6 +1969,96 @@ void tcg_gen_lookup_and_goto_ptr(void) gen_lookup_tb_ptr_and_goto(); } =20 +static void gen_jc_hash(TCGTemp *h, TCGTemp *t, TCGTemp *pc) +{ +#ifdef CONFIG_SOFTMMU + /* + * tb_jmp_cache_hash_func(), softmmu form. TARGET_PAGE_BITS is a load + * from target_page in this translation unit, but it is decided long + * before any translation happens, so it is a constant here. + */ + int shift =3D TARGET_PAGE_BITS - TB_JMP_PAGE_BITS; + + gen_shri(TCG_TYPE_I64, t, pc, shift); + gen_xor(TCG_TYPE_I64, t, t, pc); + gen_shri(TCG_TYPE_I64, h, t, shift); + gen_andi(TCG_TYPE_I64, h, h, TB_JMP_PAGE_MASK); + gen_andi(TCG_TYPE_I64, t, t, TB_JMP_ADDR_MASK); + gen_or(TCG_TYPE_I64, h, h, t); +#else + /* tb_jmp_cache_hash_func(), user-only form. */ + gen_shri(TCG_TYPE_I64, h, pc, TB_JMP_CACHE_BITS); + gen_xor(TCG_TYPE_I64, h, h, pc); + gen_andi(TCG_TYPE_I64, h, h, TB_JMP_CACHE_SIZE - 1); +#endif +} + +static void gen_jc_probe(TCGTemp *pc, TCGTemp *cs_base, uint32_t flags) +{ + const TranslationBlock *tb =3D tcg_ctx->gen_tb; + TCGLabel *slow =3D gen_new_label(); + uint64_t fpair; + + QEMU_BUILD_BUG_ON(sizeof_field(CPUJumpCache, array[0]) !=3D 16); + QEMU_BUILD_BUG_ON(offsetof(CPUJumpCache, array[0].pc) % 8 !=3D 0); + /* One 64-bit load has to cover both, so they must be adjacent... */ + QEMU_BUILD_BUG_ON(offsetof(TranslationBlock, cflags) !=3D + offsetof(TranslationBlock, flags) + 4); + /* ...and aligned, which nothing else currently relies on. */ + QEMU_BUILD_BUG_ON(offsetof(TranslationBlock, flags) % 8 !=3D 0); + + { + g_autoptr(TCGTemp) t =3D tcg_temp_new_ebb(TCG_TYPE_I64); + g_autoptr(TCGTemp) h =3D tcg_temp_new_ebb(TCG_TYPE_I64); + g_autoptr(TCGTemp) p =3D tcg_temp_new_ebb(TCG_TYPE_PTR); + + /* p =3D &jc->array[tb_jmp_cache_hash_func(pc)] */ + gen_jc_hash(h, t, pc); + gen_op_tti(INDEX_op_ld, TCG_TYPE_I64, t, tcgv_ptr_temp(tcg_env), + offsetof(CPUState, tb_jmp_cache) - sizeof(CPUState)); + gen_lea(TCG_TYPE_I64, p, t, h, 4, 0); + + /* + * The pc first: on a hash miss it is the field most likely to dif= fer, + * and an entry whose tb is NULL has a zero pc that only pc 0 matc= hes. + */ + gen_ld(TCG_TYPE_I64, t, p, offsetof(CPUJumpCache, array[0].pc)); + gen_brcond(TCG_TYPE_I64, TCG_COND_NE, t, pc, slow); + + gen_ld(TCG_TYPE_PTR, p, p, offsetof(CPUJumpCache, array[0].tb)); + gen_brcond(TCG_TYPE_PTR, TCG_COND_EQ, + p, tcg_constant_internal(TCG_TYPE_PTR, 0), slow); + + /* + * flags and cflags are adjacent uint32_t, so one aligned 64-bit l= oad + * and compare covers both. + */ + fpair =3D (HOST_BIG_ENDIAN + ? deposit64(tb->cflags, 32, 32, flags) + : deposit64(flags, 32, 32, tb->cflags)); + gen_ld(TCG_TYPE_I64, t, p, offsetof(TranslationBlock, flags)); + gen_brcond(TCG_TYPE_I64, TCG_COND_NE, + t, tcg_constant_internal(TCG_TYPE_I64, fpair), slow); + + /* + * cs_base is a second word of target-specific flags despite the n= ame, + * and the pc alone does not imply it on a target that uses it. + */ + gen_ld(TCG_TYPE_I64, t, p, offsetof(TranslationBlock, cs_base)); + gen_brcond(TCG_TYPE_I64, TCG_COND_NE, t, cs_base, slow); + + gen_ld(TCG_TYPE_PTR, p, p, offsetof(TranslationBlock, tc.ptr)); + gen_goto_ptr(p); + } + + /* + * Emit a second goto_ptr rather than branching to a shared one: a temp + * live across the label would be spilled and reloaded on every dispat= ch. + */ + gen_set_label(slow); + gen_lookup_tb_ptr_and_goto(); +} + static void gen_goto_jc3(TCGType type, TCGTemp *pc, TCGTemp *cs_base, unsigned flags) { @@ -1988,7 +2085,16 @@ static void gen_goto_jc3(TCGType type, TCGTemp *pc, tcg_constant_i32(flags)); #endif =20 - gen_lookup_tb_ptr_and_goto(); + /* + * A breakpoint is the one thing the probe cannot check for itself, so + * while one is set the flag is set too and every dispatch takes the + * helper, which does check. See tcg_update_cflags(). + */ + if (tcg_ctx->gen_tb->cflags & (CF_NO_GOTO_PTR | CF_NO_GOTO_JC)) { + gen_lookup_tb_ptr_and_goto(); + } else { + gen_jc_probe(pc, cs_base, flags); + } } =20 static void gen_goto_jc(TCGType type, TCGTemp *pc) --=20 2.53.0 From nobody Sat Sep 26 20:52:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789637674; cv=none; d=zohomail.com; s=zohoarc; b=ITJg5PfIEM0R4G4T2CDdZI9Qj8utUSif0kI0FROdVcydTnv+r+NbUM1yLlQNIYtJQq7QGmnV9vMqRN13OmhurtOyu/qMXKlcqyUnaPriNhuccFIIeSyQzkC2g/Vn/Gjed0Bl1n4ItSgwEPgp3Or03c4dBzuCFdWjS2wKhgLHx9w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789637674; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 17 Sep 2026 02:33:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 10/13] tcg: Add INDEX_op_goto_jc Date: Wed, 16 Sep 2026 23:33:04 -1000 Message-ID: <20260917093307.1092084-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917093307.1092084-1-richard.henderson@linaro.org> References: <20260917093307.1092084-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::10; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789637676044158500 Content-Type: text/plain; charset="utf-8" Allow goto_jc to be implemented in the backend. Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- docs/devel/tcg-ops.rst | 11 +++++ include/tcg/tcg-opc.h | 1 + tcg/tcg-op.c | 73 ++++++++++++++++++++------------ tcg/tcg.c | 22 ++++++++++ tcg/aarch64/tcg-target.c.inc | 4 ++ tcg/loongarch64/tcg-target.c.inc | 4 ++ tcg/ppc64/tcg-target.c.inc | 4 ++ tcg/riscv64/tcg-target.c.inc | 4 ++ tcg/s390x/tcg-target.c.inc | 4 ++ tcg/sparc64/tcg-target.c.inc | 4 ++ tcg/tci/tcg-target.c.inc | 4 ++ tcg/x86_64/tcg-target.c.inc | 4 ++ 12 files changed, 111 insertions(+), 28 deletions(-) diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index 51fa183e911..ca640610b42 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -752,6 +752,17 @@ QEMU specific operations | This operation is optional. If the TCG backend does not implement= the goto_ptr opcode, emitting this op is equivalent to emitting exit_= tb(0). =20 + * - goto_jc *jc*, *pc*, *cs_base*, *flags*, *label* + + - | *jc* is a CPUJumpCache pointer. Generate code for: + | + | if (jc->pc !=3D pc) goto label; + | tb =3D jc->tb; + | if (tb =3D=3D NULL) goto label; + | if (tb->flags !=3D flags) goto label; + | if (tb->cs_base !=3D cs_base) goto label; + | goto tb->tc.ptr; + * - qemu_ld_i32/i64/i128 *t0*, *t1*, *flags*, *memidx* =20 qemu_st_i32/i64/i128 *t0*, *t1*, *flags*, *memidx* diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 884345afe56..ce7703d5830 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -122,6 +122,7 @@ DEF(insn_start, 0, 0, INSN_START_WORDS, TCG_OPF_NOT_PRE= SENT) DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESE= NT) DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESE= NT) DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) +DEF(goto_jc, 0, 4, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) =20 DEF(plugin_cb, 0, 0, 1, TCG_OPF_NOT_PRESENT) DEF(plugin_mem_cb, 0, 1, 1, TCG_OPF_NOT_PRESENT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index cd10a00bf9e..0c609f8b38e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -158,6 +158,14 @@ static TCGOp *gen_op_ttttt(TCGOpcode opc, TCGType type, temp_arg(t3), temp_arg(t4)); } =20 +static TCGOp *gen_op_tttti(TCGOpcode opc, TCGType type, + TCGTemp *t0, TCGTemp *t1, TCGTemp *t2, + TCGTemp *t3, TCGArg a4) +{ + return tcg_gen_op5(opc, type, temp_arg(t0), temp_arg(t1), + temp_arg(t2), temp_arg(t3), a4); +} + static TCGOp *gen_op_ttttti(TCGOpcode opc, TCGType type, TCGTemp *t0, TCGTemp *t1, TCGTemp *t2, TCGTemp *t3, TCGTemp *t4, TCGArg a5) @@ -1997,7 +2005,13 @@ static void gen_jc_probe(TCGTemp *pc, TCGTemp *cs_ba= se, uint32_t flags) { const TranslationBlock *tb =3D tcg_ctx->gen_tb; TCGLabel *slow =3D gen_new_label(); - uint64_t fpair; + /* + * flags and cflags are adjacent uint32_t, so one aligned 64-bit load + * and compare covers both. + */ + uint64_t fpair =3D (HOST_BIG_ENDIAN + ? deposit64(tb->cflags, 32, 32, flags) + : deposit64(flags, 32, 32, tb->cflags)); =20 QEMU_BUILD_BUG_ON(sizeof_field(CPUJumpCache, array[0]) !=3D 16); QEMU_BUILD_BUG_ON(offsetof(CPUJumpCache, array[0].pc) % 8 !=3D 0); @@ -2018,37 +2032,40 @@ static void gen_jc_probe(TCGTemp *pc, TCGTemp *cs_b= ase, uint32_t flags) offsetof(CPUState, tb_jmp_cache) - sizeof(CPUState)); gen_lea(TCG_TYPE_I64, p, t, h, 4, 0); =20 - /* - * The pc first: on a hash miss it is the field most likely to dif= fer, - * and an entry whose tb is NULL has a zero pc that only pc 0 matc= hes. - */ - gen_ld(TCG_TYPE_I64, t, p, offsetof(CPUJumpCache, array[0].pc)); - gen_brcond(TCG_TYPE_I64, TCG_COND_NE, t, pc, slow); + if (tcg_op_supported(INDEX_op_goto_jc, TCG_TYPE_PTR, 0)) { + TCGOp *op =3D gen_op_tttti(INDEX_op_goto_jc, TCG_TYPE_PTR, + p, pc, cs_base, + tcg_constant_internal(TCG_TYPE_I64, f= pair), + label_arg(slow)); + add_as_label_use(slow, op); + } else { + /* + * The pc first: on a hash miss it is the field most likely + * to differ, and an entry whose tb is NULL has a zero pc + * that only pc 0 matches. + */ + gen_ld(TCG_TYPE_I64, t, p, offsetof(CPUJumpCache, array[0].pc)= ); + gen_brcond(TCG_TYPE_I64, TCG_COND_NE, t, pc, slow); =20 - gen_ld(TCG_TYPE_PTR, p, p, offsetof(CPUJumpCache, array[0].tb)); - gen_brcond(TCG_TYPE_PTR, TCG_COND_EQ, - p, tcg_constant_internal(TCG_TYPE_PTR, 0), slow); + gen_ld(TCG_TYPE_PTR, p, p, offsetof(CPUJumpCache, array[0].tb)= ); + gen_brcond(TCG_TYPE_PTR, TCG_COND_EQ, + p, tcg_constant_internal(TCG_TYPE_PTR, 0), slow); =20 - /* - * flags and cflags are adjacent uint32_t, so one aligned 64-bit l= oad - * and compare covers both. - */ - fpair =3D (HOST_BIG_ENDIAN - ? deposit64(tb->cflags, 32, 32, flags) - : deposit64(flags, 32, 32, tb->cflags)); - gen_ld(TCG_TYPE_I64, t, p, offsetof(TranslationBlock, flags)); - gen_brcond(TCG_TYPE_I64, TCG_COND_NE, - t, tcg_constant_internal(TCG_TYPE_I64, fpair), slow); + gen_ld(TCG_TYPE_I64, t, p, offsetof(TranslationBlock, flags)); + gen_brcond(TCG_TYPE_I64, TCG_COND_NE, + t, tcg_constant_internal(TCG_TYPE_I64, fpair), slow= ); =20 - /* - * cs_base is a second word of target-specific flags despite the n= ame, - * and the pc alone does not imply it on a target that uses it. - */ - gen_ld(TCG_TYPE_I64, t, p, offsetof(TranslationBlock, cs_base)); - gen_brcond(TCG_TYPE_I64, TCG_COND_NE, t, cs_base, slow); + /* + * cs_base is a second word of target-specific flags despite + * the name, and the pc alone does not imply it on a target + * that uses it. + */ + gen_ld(TCG_TYPE_I64, t, p, offsetof(TranslationBlock, cs_base)= ); + gen_brcond(TCG_TYPE_I64, TCG_COND_NE, t, cs_base, slow); =20 - gen_ld(TCG_TYPE_PTR, p, p, offsetof(TranslationBlock, tc.ptr)); - gen_goto_ptr(p); + gen_ld(TCG_TYPE_PTR, p, p, offsetof(TranslationBlock, tc.ptr)); + gen_goto_ptr(p); + } } =20 /* diff --git a/tcg/tcg.c b/tcg/tcg.c index b88ee847039..a08e83f3954 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1101,6 +1101,12 @@ typedef struct TCGOutOpLea { TCGReg a2, unsigned sh, tcg_target_long imm); } TCGOutOpLea; =20 +typedef struct TCGOutOpGotoJC { + TCGOutOp base; + void (*out)(TCGContext *s, TCGReg jc, TCGReg pc, TCGArg cs, bool const= _cs, + TCGArg fl, bool const_fl, TCGLabel *l); +} TCGOutOpGotoJC; + #include "tcg-target.c.inc" =20 #ifndef CONFIG_TCG_INTERPRETER @@ -1190,6 +1196,7 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D { OUTOP(INDEX_op_extrh_i64_i32, TCGOutOpUnary, outop_extrh_i64_i32), OUTOP(INDEX_op_extrl_i64_i32, TCGOutOpUnary, outop_extrl_i64_i32), OUTOP(INDEX_op_extu_i32_i64, TCGOutOpUnary, outop_extu_i32_i64), + OUTOP(INDEX_op_goto_jc, TCGOutOpGotoJC, outop_goto_jc), OUTOP(INDEX_op_ld, TCGOutOpLoad, outop_ld), OUTOP(INDEX_op_ld8s, TCGOutOpLoad, outop_ld8s), OUTOP(INDEX_op_ld8u, TCGOutOpLoad, outop_ld8u), @@ -3009,6 +3016,7 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_p= refs) case INDEX_op_set_label: case INDEX_op_br: case INDEX_op_brcond: + case INDEX_op_goto_jc: col +=3D ne_fprintf(f, "%s$L%d", k ? "," : "", arg_label(op->args[k])->id); i++, k++; @@ -3478,6 +3486,9 @@ void tcg_op_remove(TCGContext *s, TCGOp *op) case INDEX_op_brcond: remove_label_use(op, 3); break; + case INDEX_op_goto_jc: + remove_label_use(op, 4); + break; default: break; } @@ -3576,6 +3587,9 @@ static void move_label_uses(TCGLabel *to, TCGLabel *f= rom) case INDEX_op_brcond: op->args[3] =3D label_arg(to); break; + case INDEX_op_goto_jc: + op->args[4] =3D label_arg(to); + break; default: g_assert_not_reached(); } @@ -3650,6 +3664,7 @@ reachable_code_pass(TCGContext *s) case INDEX_op_br: case INDEX_op_exit_tb: case INDEX_op_goto_ptr: + case INDEX_op_goto_jc: /* Unconditional branches; everything following is dead. */ dead =3D true; break; @@ -6017,6 +6032,13 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) tcg_out_goto_ptr(s, new_args[0]); break; =20 + case INDEX_op_goto_jc: + tcg_debug_assert(!const_args[0]); + tcg_debug_assert(!const_args[1]); + outop_goto_jc.out(s, new_args[0], new_args[1], new_args[2], const_= args[2], + new_args[3], const_args[3], arg_label(new_args[4= ])); + break; + default: tcg_debug_assert(def->flags & TCG_OPF_VECTOR); tcg_out_vec_op(s, op->opc, type - TCG_TYPE_V64, diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 6836c0dd94f..a0f23914224 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2008,6 +2008,10 @@ static const TCGOutOpQemuLdSt2 outop_qemu_st2 =3D { .out =3D tgen_qemu_st2, }; =20 +static const TCGOutOpGotoJC outop_goto_jc =3D { + .base.static_constraint =3D C_NotImplemented, +}; + static const tcg_insn_unit *tb_ret_addr; =20 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 377cd9ec08d..733cce516e0 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -2113,6 +2113,10 @@ static const TCGOutOpLea outop_lea =3D { .out =3D tgen_lea, }; =20 +static const TCGOutOpGotoJC outop_goto_jc =3D { + .base.static_constraint =3D C_NotImplemented, +}; + static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg rd, TCGReg rs) { diff --git a/tcg/ppc64/tcg-target.c.inc b/tcg/ppc64/tcg-target.c.inc index 99f4469f4b9..466ae836d5a 100644 --- a/tcg/ppc64/tcg-target.c.inc +++ b/tcg/ppc64/tcg-target.c.inc @@ -3637,6 +3637,10 @@ static const TCGOutOpLea outop_lea =3D { .base.static_constraint =3D C_NotImplemented, }; =20 +static const TCGOutOpGotoJC outop_goto_jc =3D { + .base.static_constraint =3D C_NotImplemented, +}; + int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { switch (opc) { diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index ba7aab9246c..effa9d7a1ac 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -2743,6 +2743,10 @@ static const TCGOutOpLea outop_lea =3D { .out =3D tgen_lea, }; =20 +static const TCGOutOpGotoJC outop_goto_jc =3D { + .base.static_constraint =3D C_NotImplemented, +}; + static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg args[TCG_MAX_OP_ARGS], diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index db3b2fc3c92..3b63383315d 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -3202,6 +3202,10 @@ static const TCGOutOpLea outop_lea =3D { .out =3D tgen_lea, }; =20 +static const TCGOutOpGotoJC outop_goto_jc =3D { + .base.static_constraint =3D C_NotImplemented, +}; + static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src) { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index cb457453ff9..0582dc8bdd3 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -2124,6 +2124,10 @@ static const TCGOutOpLea outop_lea =3D { .base.static_constraint =3D C_NotImplemented, }; =20 +static const TCGOutOpGotoJC outop_goto_jc =3D { + .base.static_constraint =3D C_NotImplemented, +}; + static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) { diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 6942fdbb4e0..5d8892abc44 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -1224,6 +1224,10 @@ static const TCGOutOpLea outop_lea =3D { .base.static_constraint =3D C_NotImplemented, }; =20 +static const TCGOutOpGotoJC outop_goto_jc =3D { + .base.static_constraint =3D C_NotImplemented, +}; + /* Test if a constant matches the constraint. */ static bool tcg_target_const_match(int64_t val, int ct, TCGType type, TCGCond cond, int vece) diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc index a41252782e1..08dec0dace8 100644 --- a/tcg/x86_64/tcg-target.c.inc +++ b/tcg/x86_64/tcg-target.c.inc @@ -3344,6 +3344,10 @@ static const TCGOutOpLea outop_lea =3D { .out =3D tgen_lea, }; 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Thu, 17 Sep 2026 02:33:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 11/13] tcg/x86_64: Implement INDEX_op_goto_jc Date: Wed, 16 Sep 2026 23:33:05 -1000 Message-ID: <20260917093307.1092084-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917093307.1092084-1-richard.henderson@linaro.org> References: <20260917093307.1092084-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:3b::c; envelope-from=richard.henderson@linaro.org; helo=mail-pz2-x0c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789637704016158500 Content-Type: text/plain; charset="utf-8" Use comparisons vs memory, short branches, and an indirect memory jump. Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/x86_64/tcg-target-con-set.h | 1 + tcg/tcg.c | 1 + tcg/x86_64/tcg-target.c.inc | 63 ++++++++++++++++++++++++++++++++- 3 files changed, 64 insertions(+), 1 deletion(-) diff --git a/tcg/x86_64/tcg-target-con-set.h b/tcg/x86_64/tcg-target-con-se= t.h index 5af8c1cb2cd..f3359ae5bce 100644 --- a/tcg/x86_64/tcg-target-con-set.h +++ b/tcg/x86_64/tcg-target-con-set.h @@ -26,6 +26,7 @@ C_O0_I2(x, r) C_O0_I3(L, L, L) C_O0_I3(s, L, L) C_O0_I4(L, L, L, L) +C_O0_I4(r, r, re, re) C_O0_I4(r, r, ri, ri) C_O1_I1(r, 0) C_O1_I1(r, L) diff --git a/tcg/tcg.c b/tcg/tcg.c index a08e83f3954..2650119dedb 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -61,6 +61,7 @@ #ifdef CONFIG_USER_ONLY #include "user/guest-base.h" #endif +#include "../accel/tcg/tb-hash.h" =20 /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc index 08dec0dace8..7f510545b48 100644 --- a/tcg/x86_64/tcg-target.c.inc +++ b/tcg/x86_64/tcg-target.c.inc @@ -1531,6 +1531,25 @@ static int tcg_out_cmp(TCGContext *s, TCGCond cond, = TCGArg arg1, return jz; } =20 +static void tgen_cmp_mem_reg(TCGContext *s, int rexw, TCGReg reg, + TCGReg base, intptr_t ofs) +{ + tcg_out_modrm_offset(s, OPC_CMP_GvEv | rexw, reg, base, ofs); +} + +static void tgen_cmp_mem_imm(TCGContext *s, int rexw, int64_t imm, + TCGReg base, intptr_t ofs) +{ + if (imm =3D=3D (int8_t)imm) { + tcg_out_modrm_offset(s, OPC_ARITH_EvIb | rexw, ARITH_CMP, base, of= s); + tcg_out8(s, imm); + } else { + tcg_debug_assert(imm =3D=3D (int32_t)imm); + tcg_out_modrm_offset(s, OPC_ARITH_EvIz | rexw, ARITH_CMP, base, of= s); + tcg_out32(s, imm); + } +} + static void tcg_out_brcond(TCGContext *s, int rexw, TCGCond cond, TCGArg arg1, TCGArg arg2, int const_arg2, TCGLabel *label, bool small) @@ -3344,8 +3363,50 @@ static const TCGOutOpLea outop_lea =3D { .out =3D tgen_lea, }; =20 +static void tgen_goto_jc(TCGContext *s, TCGReg ptr, TCGReg pc, + TCGArg cs, bool const_cs, TCGArg fl, bool const_f= l, + TCGLabel *label) +{ + /* ptr is CPUJumpCache */ + + /* Validate pc match */ + tgen_cmp_mem_reg(s, P_REXW, pc, ptr, offsetof(CPUJumpCache, array[0].p= c)); + tcg_out_jxx(s, JCC_JNE, label, true); + + /* Load and validate tb non-null */ + tcg_out_ld(s, TCG_TYPE_PTR, ptr, ptr, offsetof(CPUJumpCache, array[0].= tb)); + tcg_out_brcond(s, P_REXW, TCG_COND_EQ, ptr, 0, true, label, true); + + /* ptr is now TranslationBlock */ + + /* Validate cs_base match */ + if (const_cs) { + tgen_cmp_mem_imm(s, P_REXW, cs, ptr, + offsetof(TranslationBlock, cs_base)); + } else { + tgen_cmp_mem_reg(s, P_REXW, cs, ptr, + offsetof(TranslationBlock, cs_base)); + } + tcg_out_jxx(s, JCC_JNE, label, true); + + /* Validate flags:cflags match */ + if (const_fl) { + tgen_cmp_mem_imm(s, P_REXW, fl, ptr, + offsetof(TranslationBlock, flags)); + } else { + tgen_cmp_mem_reg(s, P_REXW, fl, ptr, + offsetof(TranslationBlock, flags)); + } + tcg_out_jxx(s, JCC_JNE, label, true); + + /* Jump to tb */ + tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, + ptr, offsetof(TranslationBlock, tc.ptr)); +} + static const TCGOutOpGotoJC outop_goto_jc =3D { - .base.static_constraint =3D C_NotImplemented, + .base.static_constraint =3D C_O0_I4(r, r, re, re), + .out =3D tgen_goto_jc, }; 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Thu, 17 Sep 2026 02:33:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 12/13] tcg/aarch64: Implement INDEX_op_goto_jc Date: Wed, 16 Sep 2026 23:33:06 -1000 Message-ID: <20260917093307.1092084-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917093307.1092084-1-richard.henderson@linaro.org> References: <20260917093307.1092084-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:31::2b; envelope-from=richard.henderson@linaro.org; helo=mail-oo2-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789637680038158500 Content-Type: text/plain; charset="utf-8" Use ldp to load multiple values at once. Use ccmp to reduce the number of branhes. Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/aarch64/tcg-target-con-set.h | 1 + tcg/aarch64/tcg-target.c.inc | 58 +++++++++++++++++++++++++++++++- 2 files changed, 58 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-= set.h index dd84a9af586..4b076962347 100644 --- a/tcg/aarch64/tcg-target-con-set.h +++ b/tcg/aarch64/tcg-target-con-set.h @@ -14,6 +14,7 @@ C_O0_I2(r, rC) C_O0_I2(rz, r) C_O0_I2(w, r) C_O0_I3(rz, rz, r) +C_O0_I4(r, rz, rz, rz) C_O1_I1(r, r) C_O1_I1(w, r) C_O1_I1(w, w) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index a0f23914224..2994a3f73e7 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -570,6 +570,9 @@ typedef enum { /* Logical shifted register instructions (with a shift). */ Iaddsub_realshift_AND_LSR =3D Ilogic_shift_AND | (1 << 22), =20 + /* Conditional compare register. */ + Iccmp_reg_CCMP =3D 0x7a400000, + /* AdvSIMD copy */ Isimd_copy_DUP =3D 0x0e000400, Isimd_copy_INS =3D 0x4e001c00, @@ -712,6 +715,14 @@ static void tcg_out_insn_bcond_imm(TCGContext *s, AArc= h64Insn insn, tcg_out32(s, insn | tcg_cond_to_aarch64[c] | (imm19 & 0x7ffff) << 5); } =20 +static void tcg_out_insn_ccmp_reg(TCGContext *s, AArch64Insn insn, + TCGType ext, TCGCond c, TCGReg rn, + TCGReg rm, unsigned nzcv) +{ + tcg_out32(s, insn | ext << 31 | tcg_cond_to_aarch64[c] << 12 + | rm << 16 | rn << 5 | nzcv); +} + static void tcg_out_insn_tbz(TCGContext *s, AArch64Insn insn, TCGReg rt, int imm6, int imm14) { @@ -2008,8 +2019,53 @@ static const TCGOutOpQemuLdSt2 outop_qemu_st2 =3D { .out =3D tgen_qemu_st2, }; =20 +static void tgen_goto_jc(TCGContext *s, TCGReg ptr, TCGReg pc, + TCGArg cs, bool const_cs, + TCGArg fl, bool const_fl, TCGLabel *label) +{ + /* ptr is CPUJumpCache */ + + QEMU_BUILD_BUG_ON(offsetof(CPUJumpCache, array[0].pc) !=3D + offsetof(CPUJumpCache, array[0].tb) + 8); + tcg_out_insn(s, ldstpair, LDP, ptr, TCG_REG_TMP0, ptr, + offsetof(CPUJumpCache, array[0].tb), 1, 0); + + /* + * z=3Dcmp(ptr,0) + * if !z, z=3Dcmp(pc,tmp), else z=3D0 + * if !z, goto label + */ + tgen_cmpi(s, TCG_TYPE_I64, TCG_COND_NE, ptr, 0); + tcg_out_insn(s, ccmp_reg, CCMP, TCG_TYPE_I64, TCG_COND_NE, + pc, TCG_REG_TMP0, 0b0000); + tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, label, 0); + tcg_out_insn(s, bcond_imm, B_C, TCG_COND_NE, 0); + + /* ptr is now TranslationBlock */ + + QEMU_BUILD_BUG_ON(offsetof(TranslationBlock, flags) !=3D + offsetof(TranslationBlock, cs_base) + 8); + tcg_out_insn(s, ldstpair, LDP, TCG_REG_TMP0, TCG_REG_TMP1, + ptr, offsetof(TranslationBlock, cs_base), 1, 0); + tcg_out_ld(s, TCG_TYPE_PTR, ptr, ptr, offsetof(TranslationBlock, tc.pt= r)); + + /* + * z=3Dcmp(cs,tmp0) + * if z, z=3Dcmp(fl,tmp1), else z=3D0 + * if !z, goto label + */ + tgen_cmp(s, TCG_TYPE_I64, TCG_COND_EQ, cs, TCG_REG_TMP0); + tcg_out_insn(s, ccmp_reg, CCMP, TCG_TYPE_I64, TCG_COND_EQ, + fl, TCG_REG_TMP1, 0x0000); + tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, label, 0); + tcg_out_insn(s, bcond_imm, B_C, TCG_COND_NE, 0); + + tcg_out_goto_ptr(s, ptr); +} + static const TCGOutOpGotoJC outop_goto_jc =3D { - .base.static_constraint =3D C_NotImplemented, + .base.static_constraint =3D C_O0_I4(r, rz, rz, rz), + .out =3D tgen_goto_jc, }; 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Thu, 17 Sep 2026 02:33:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 13/13] tcg/s390x: Implement INDEX_op_goto_jc Date: Wed, 16 Sep 2026 23:33:07 -1000 Message-ID: <20260917093307.1092084-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917093307.1092084-1-richard.henderson@linaro.org> References: <20260917093307.1092084-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:3b::10; envelope-from=richard.henderson@linaro.org; helo=mail-pz2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789637706039158500 Content-Type: text/plain; charset="utf-8" Use LGM to load multiple values at once. Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target-con-str.h | 1 + tcg/s390x/tcg-target.c.inc | 40 +++++++++++++++++++++++++++++++++- 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index f67fd7898ed..a566a1ca7b4 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -18,6 +18,7 @@ C_O0_I2(r, ri) C_O0_I2(r, rC) C_O0_I2(v, r) C_O0_I3(o, m, r) +C_O0_I4(r, hJU, hJU, hJU) C_O1_I1(r, r) C_O1_I1(v, r) C_O1_I1(v, v) diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h index 636a38a168a..e44b2a92d52 100644 --- a/tcg/s390x/tcg-target-con-str.h +++ b/tcg/s390x/tcg-target-con-str.h @@ -9,6 +9,7 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) +REGS('h', 0xfff8) /* general regs other than r0-r2 */ REGS('v', ALL_VECTOR_REGS) REGS('o', 0xaaaa) /* odd numbered general regs */ =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 3b63383315d..b04c54e26d3 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -3202,8 +3202,46 @@ static const TCGOutOpLea outop_lea =3D { .out =3D tgen_lea, }; =20 +static void tgen_goto_jc(TCGContext *s, TCGReg ptr, TCGReg pc, + TCGArg cs, bool const_cs, + TCGArg fl, bool const_fl, TCGLabel *label) +{ + /* + * Note that pc, cs, fl are constrained to r3 or higher, r0 and r1 + * are always reserved as scratch, this is the end of the translation + * block so r2 may now be clobbered, and the input ptr * is dead + * after the initial LMG. + */ + + /* ptr is CPUJumpCache */ + + QEMU_BUILD_BUG_ON(offsetof(CPUJumpCache, array[0].pc) !=3D + offsetof(CPUJumpCache, array[0].tb) + 8); + /* lmg r1,r2,tb(ptr) */ + tcg_out_insn(s, RXY, LMG, TCG_REG_R1, ptr, TCG_REG_R2, + offsetof(CPUJumpCache, array[0].tb)); + + tgen_brcond(s, TCG_TYPE_I64, TCG_COND_NE, TCG_REG_R2, pc, false, label= ); + tgen_brcond(s, TCG_TYPE_PTR, TCG_COND_EQ, TCG_REG_R1, 0, true, label); + + /* R1 is now TranslationBlock */ + + QEMU_BUILD_BUG_ON(offsetof(TranslationBlock, flags) !=3D + offsetof(TranslationBlock, cs_base) + 8); + QEMU_BUILD_BUG_ON(offsetof(TranslationBlock, tc.ptr) !=3D + offsetof(TranslationBlock, cs_base) + 16); + /* lmg r0,r2,cs(r1) */ + tcg_out_insn(s, RXY, LMG, TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, + offsetof(TranslationBlock, cs_base)); + + tgen_brcond(s, TCG_TYPE_I64, TCG_COND_NE, TCG_REG_R0, cs, const_cs, la= bel); + tgen_brcond(s, TCG_TYPE_I64, TCG_COND_NE, TCG_REG_R1, fl, const_fl, la= bel); + tcg_out_goto_ptr(s, TCG_REG_R2); +} + static const TCGOutOpGotoJC outop_goto_jc =3D { - .base.static_constraint =3D C_NotImplemented, + .base.static_constraint =3D C_O0_I4(r, hJU, hJU, hJU), + .out =3D tgen_goto_jc, }; =20 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, --=20 2.53.0