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Thu, 17 Sep 2026 01:17:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Matt Turner , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 01/16] tcg: Add INDEX_op_lea Date: Wed, 16 Sep 2026 22:17:01 -1000 Message-ID: <20260917081716.946668-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917081716.946668-1-richard.henderson@linaro.org> References: <20260917081716.946668-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:30::10; envelope-from=richard.henderson@linaro.org; helo=mail-oa2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633151051158500 Add an opcode for compound address formation. Reviewed-by: Matt Turner Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- docs/devel/tcg-ops.rst | 4 ++++ include/tcg/tcg-opc.h | 1 + tcg/aarch64/tcg-target-has.h | 3 +++ tcg/loongarch64/tcg-target-has.h | 3 +++ tcg/ppc64/tcg-target-has.h | 3 +++ tcg/riscv64/tcg-target-has.h | 3 +++ tcg/s390x/tcg-target-has.h | 3 +++ tcg/sparc64/tcg-target-has.h | 3 +++ tcg/tci/tcg-target-has.h | 3 +++ tcg/x86_64/tcg-target-has.h | 3 +++ tcg/tcg.c | 22 ++++++++++++++++++++++ tcg/aarch64/tcg-target.c.inc | 4 ++++ tcg/loongarch64/tcg-target.c.inc | 4 ++++ tcg/ppc64/tcg-target.c.inc | 3 +++ tcg/riscv64/tcg-target.c.inc | 3 +++ tcg/s390x/tcg-target.c.inc | 3 +++ tcg/sparc64/tcg-target.c.inc | 3 +++ tcg/tci/tcg-target.c.inc | 4 ++++ tcg/x86_64/tcg-target.c.inc | 4 ++++ 19 files changed, 79 insertions(+) diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index 88d48a1f99a..51fa183e911 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -524,6 +524,10 @@ Misc =20 - | Reverse the 64 bits of input *t1* with output in *dest*. =20 + * - lea *dest*, *t1*, *t2*, *sh*, *imm* + + - | *dest* =3D *t1* + (*t2* << *sh*) + *imm*. + Conditional moves ----------------- =20 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index f3a81d5d7fb..884345afe56 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -64,6 +64,7 @@ DEF(ld16s, 1, 1, 1, TCG_OPF_INT) DEF(ld32u, 1, 1, 1, TCG_OPF_INT) DEF(ld32s, 1, 1, 1, TCG_OPF_INT) DEF(ld, 1, 1, 1, TCG_OPF_INT) +DEF(lea, 1, 2, 2, TCG_OPF_INT) DEF(movcond, 1, 4, 1, TCG_OPF_INT) DEF(mul, 1, 2, 0, TCG_OPF_INT) DEF(muls2, 2, 2, 0, TCG_OPF_INT) diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h index 69e83efb69d..86672b2eab4 100644 --- a/tcg/aarch64/tcg-target-has.h +++ b/tcg/aarch64/tcg-target-has.h @@ -57,4 +57,7 @@ #define TCG_TARGET_sextract_valid(type, ofs, len) 1 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-= has.h index 32abc6f4574..31e6ea9632d 100644 --- a/tcg/loongarch64/tcg-target-has.h +++ b/tcg/loongarch64/tcg-target-has.h @@ -54,4 +54,7 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, uns= igned len) } #define TCG_TARGET_sextract_valid tcg_target_sextract_valid =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/ppc64/tcg-target-has.h b/tcg/ppc64/tcg-target-has.h index a3711feeae2..d11d82f1844 100644 --- a/tcg/ppc64/tcg-target-has.h +++ b/tcg/ppc64/tcg-target-has.h @@ -66,4 +66,7 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, uns= igned len) } #define TCG_TARGET_sextract_valid tcg_target_sextract_valid =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/riscv64/tcg-target-has.h b/tcg/riscv64/tcg-target-has.h index aef10c2d9d6..93f8baad09f 100644 --- a/tcg/riscv64/tcg-target-has.h +++ b/tcg/riscv64/tcg-target-has.h @@ -69,4 +69,7 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, uns= igned len) =20 #define TCG_TARGET_deposit_valid(type, ofs, len) 0 =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h index 0aeb5ba01a9..58e3afe5266 100644 --- a/tcg/s390x/tcg-target-has.h +++ b/tcg/s390x/tcg-target-has.h @@ -77,4 +77,7 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, uns= igned len) } #define TCG_TARGET_sextract_valid tcg_target_sextract_valid =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/sparc64/tcg-target-has.h b/tcg/sparc64/tcg-target-has.h index b29fd177f69..4182a7c1aae 100644 --- a/tcg/sparc64/tcg-target-has.h +++ b/tcg/sparc64/tcg-target-has.h @@ -19,4 +19,7 @@ =20 #define TCG_TARGET_deposit_valid(type, ofs, len) 0 =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h index 64742cf0b71..f4f9ddf595f 100644 --- a/tcg/tci/tcg-target-has.h +++ b/tcg/tci/tcg-target-has.h @@ -17,4 +17,7 @@ #define TCG_TARGET_sextract_valid(type, ofs, len) 1 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/x86_64/tcg-target-has.h b/tcg/x86_64/tcg-target-has.h index d249c1b3e7f..6ffae51f923 100644 --- a/tcg/x86_64/tcg-target-has.h +++ b/tcg/x86_64/tcg-target-has.h @@ -105,4 +105,7 @@ tcg_target_extract_valid(TCGType type, unsigned ofs, un= signed len) } #define TCG_TARGET_extract_valid tcg_target_extract_valid =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/tcg.c b/tcg/tcg.c index df1590166e7..b88ee847039 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1095,6 +1095,12 @@ typedef struct TCGOutOpSubtract { TCGReg a0, tcg_target_long a1, TCGReg a2); } TCGOutOpSubtract; =20 +typedef struct TCGOutOpLea { + TCGOutOp base; + void (*out)(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + TCGReg a2, unsigned sh, tcg_target_long imm); +} TCGOutOpLea; + #include "tcg-target.c.inc" =20 #ifndef CONFIG_TCG_INTERPRETER @@ -1191,6 +1197,7 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D { OUTOP(INDEX_op_ld16u, TCGOutOpLoad, outop_ld16u), OUTOP(INDEX_op_ld32s, TCGOutOpLoad, outop_ld32s), OUTOP(INDEX_op_ld32u, TCGOutOpLoad, outop_ld32u), + OUTOP(INDEX_op_lea, TCGOutOpLea, outop_lea), OUTOP(INDEX_op_movcond, TCGOutOpMovcond, outop_movcond), OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul), OUTOP(INDEX_op_muls2, TCGOutOpMul2, outop_muls2), @@ -5990,6 +5997,21 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) } break; =20 + case INDEX_op_lea: + { + const TCGOutOpLea *out =3D &outop_lea; + int sh =3D new_args[3]; + tcg_target_long imm =3D new_args[4]; + + tcg_debug_assert(!const_args[1]); + tcg_debug_assert(!const_args[2]); + tcg_debug_assert(TCG_TARGET_lea_sh_valid(type, sh)); + tcg_debug_assert(TCG_TARGET_lea_imm_valid(type, imm)); + + out->out(s, type, new_args[0], new_args[1], new_args[2], sh, i= mm); + } + break; + case INDEX_op_goto_ptr: tcg_debug_assert(!const_args[0]); tcg_out_goto_ptr(s, new_args[0]); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 4ebdef7e077..76adb2256f9 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -3081,6 +3081,10 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; + static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg args[TCG_MAX_OP_ARGS], diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 69e76807d6e..17784d8bbe2 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -2098,6 +2098,10 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; + static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg rd, TCGReg rs) { diff --git a/tcg/ppc64/tcg-target.c.inc b/tcg/ppc64/tcg-target.c.inc index cd1c2343672..99f4469f4b9 100644 --- a/tcg/ppc64/tcg-target.c.inc +++ b/tcg/ppc64/tcg-target.c.inc @@ -3633,6 +3633,9 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; =20 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index 2ce9d47a633..df4c4a9789b 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -2725,6 +2725,9 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 4d1a779c47c..2fd7012d047 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -3187,6 +3187,9 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; =20 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 35cd14a5b65..cb457453ff9 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -2120,6 +2120,9 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; =20 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 4cd1c1431ce..6942fdbb4e0 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -1220,6 +1220,10 @@ static inline bool tcg_out_sti(TCGContext *s, TCGTyp= e type, TCGArg val, return false; } =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; + /* Test if a constant matches the constraint. */ static bool tcg_target_const_match(int64_t val, int ct, TCGType type, TCGCond cond, int vece) diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc index 2c8f1f3e580..660350b963d 100644 --- a/tcg/x86_64/tcg-target.c.inc +++ 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envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633087322158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Matt Turner Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 2 ++ include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 43 ++++++++++++++++++++++++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 37211642365..a7d001c959c 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -83,6 +83,7 @@ typedef TCGv_i64 TCGv; #define tcg_gen_shri_tl tcg_gen_shri_i64 #define tcg_gen_sar_tl tcg_gen_sar_i64 #define tcg_gen_sari_tl tcg_gen_sari_i64 +#define tcg_gen_lea_tl tcg_gen_lea_i64 #define tcg_gen_brcond_tl tcg_gen_brcond_i64 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 #define tcg_gen_setcond_tl tcg_gen_setcond_i64 @@ -209,6 +210,7 @@ typedef TCGv_i64 TCGv; #define tcg_gen_shri_tl tcg_gen_shri_i32 #define tcg_gen_sar_tl tcg_gen_sar_i32 #define tcg_gen_sari_tl tcg_gen_sari_i32 +#define tcg_gen_lea_tl tcg_gen_lea_i32 #define tcg_gen_brcond_tl tcg_gen_brcond_i32 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 #define tcg_gen_setcond_tl tcg_gen_setcond_i32 diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 4d121470bec..b60edca6e42 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -36,6 +36,7 @@ DEF3(ld8s, TCGV, TCGv_ptr, tcg_target_long) DEF3(ld8u, TCGV, TCGv_ptr, tcg_target_long) DEF3(ld16s, TCGV, TCGv_ptr, tcg_target_long) DEF3(ld16u, TCGV, TCGv_ptr, tcg_target_long) +DEF5(lea, TCGV, TCGV, TCGV, unsigned, TINT) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF6(movcond, TCGCond, TCGV, TCGV, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 855a81c886f..d271d83a7d2 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -930,6 +930,49 @@ static void gen_ld16u(TCGType type, TCGTemp *dst, gen_op_tti(INDEX_op_ld16u, type, dst, base, ofs); } =20 +static void gen_lea(TCGType type, TCGTemp *dst, TCGTemp *base, + TCGTemp *index, unsigned sh, int64_t imm) +{ + g_autoptr(TCGTemp) t =3D tcg_temp_new_ebb(type); + + if (imm !=3D 0) { + if (TCG_TARGET_lea_imm_valid(type, imm)) { + /* + * The immediate is non-zero and valid. + * If the shift is out of range, perform the shift first + * so that we can still emit (base + t + imm) as one insn. + */ + if (!TCG_TARGET_lea_sh_valid(type, sh)) { + gen_shli(type, t, index, sh); + index =3D t; + sh =3D 0; + } + gen_op_tttii(INDEX_op_lea, type, dst, base, index, sh, imm); + return; + } + + /* + * If we can make the immediate smaller by folding it + * into index before the shift, do so. + */ + if (sh !=3D 0 && imm =3D=3D (imm >> sh) << sh) { + gen_addi(type, t, index, imm >> sh); + index =3D t; + imm =3D 0; + } + } + + if (sh =3D=3D 0) { + gen_add(type, dst, base, index); + } else if (TCG_TARGET_lea_sh_valid(TCG_TYPE_I32, sh)) { + gen_op_tttii(INDEX_op_lea, type, dst, base, index, sh, 0); + } else { + gen_shli(type, t, index, sh); + gen_add(type, dst, base, t); + } + gen_addi(type, dst, dst, imm); +} + static void gen_mov(TCGType type, TCGTemp *dst, TCGTemp *src) { if (src !=3D dst) { --=20 2.53.0 From nobody Sat Sep 26 20:52:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 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<20260917081716.946668-1-richard.henderson@linaro.org> References: <20260917081716.946668-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:3b::e; envelope-from=richard.henderson@linaro.org; helo=mail-pz2-x0e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633087320158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Matt Turner Signed-off-by: Richard Henderson --- tcg/optimize.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 1e4d2a0a425..a7f45bdd541 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2106,6 +2106,68 @@ static bool fold_extu(OptContext *ctx, TCGOp *op) return fold_masks_zo(ctx, op, z_mask, o_mask); } =20 +static bool fold_shift(OptContext *ctx, TCGOp *op); +static bool fold_lea(OptContext *ctx, TCGOp *op) +{ + TCGArg sh =3D op->args[3]; + TCGArg imm =3D op->args[4]; + int var_mask =3D 0; + + if (arg_is_const(op->args[1])) { + imm +=3D arg_const_val(op->args[1]); + } else { + var_mask |=3D 1; + } + if (arg_is_const(op->args[2])) { + imm +=3D arg_const_val(op->args[2]) << sh; + } else { + var_mask |=3D 2; + } + + switch (var_mask) { + case 0: + return tcg_opt_gen_movi(ctx, op, op->args[0], imm); + + case 1: + if (imm =3D=3D 0) { + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); + } + op->opc =3D INDEX_op_add; + op->args[2] =3D arg_new_constant(ctx, imm); + break; + + case 2: + if (sh =3D=3D 0) { + if (imm =3D=3D 0) { + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]); + } + op->opc =3D INDEX_op_add; + op->args[1] =3D op->args[2]; + op->args[2] =3D arg_new_constant(ctx, imm); + break; + } + if (imm =3D=3D 0) { + op->opc =3D INDEX_op_shl; + op->args[1] =3D op->args[2]; + op->args[2] =3D arg_new_constant(ctx, sh); + return fold_shift(ctx, op); + } + + /* If arg1 was not already 0, fold the immediates. */ + if (arg_const_val(op->args[1]) !=3D 0) { + if (TCG_TARGET_lea_imm_valid(ctx->type, imm)) { + op->args[1] =3D arg_new_constant(ctx, 0); + op->args[4] =3D imm; + } else { + op->args[1] =3D arg_new_constant(ctx, imm); + op->args[4] =3D 0; + } + } + break; + } + return finish_folding(ctx, op); +} + static bool fold_mb(OptContext *ctx, TCGOp *op) { /* Eliminate duplicate and redundant fence instructions. */ @@ -2218,7 +2280,6 @@ static bool fold_mul_highpart(OptContext *ctx, TCGOp = *op) return finish_folding(ctx, op); } =20 -static bool fold_shift(OptContext *ctx, TCGOp *op); static bool fold_multiply2(OptContext *ctx, TCGOp *op) { swap_commutative(op->args[0], &op->args[2], &op->args[3]); @@ -3211,6 +3272,9 @@ void tcg_optimize(TCGContext *s) case INDEX_op_st_vec: done =3D fold_tcg_st_memcopy(&ctx, op); break; + case INDEX_op_lea: + done =3D fold_lea(&ctx, op); + break; case INDEX_op_mb: done =3D fold_mb(&ctx, op); break; --=20 2.53.0 From nobody Sat Sep 26 20:52:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1789633114895158500 Reviewed-by: Matt Turner Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/alpha/translate.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index c66e3f9c146..6f18b8d1af6 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -1474,10 +1474,8 @@ static DisasJumpType translate_one(DisasContext *ctx= , uint32_t insn) break; case 0x02: /* S4ADDL */ - tmp =3D tcg_temp_new_i64(); - tcg_gen_shli_i64(tmp, va, 2); - tcg_gen_add_i64(tmp, tmp, vb); - tcg_gen_ext32s_i64(vc, tmp); + tcg_gen_lea_i64(vc, vb, va, 2, 0); + tcg_gen_ext32s_i64(vc, vc); break; case 0x09: /* SUBL */ @@ -1502,10 +1500,8 @@ static DisasJumpType translate_one(DisasContext *ctx= , uint32_t insn) break; case 0x12: /* S8ADDL */ - tmp =3D tcg_temp_new_i64(); - tcg_gen_shli_i64(tmp, va, 3); - tcg_gen_add_i64(tmp, tmp, vb); - tcg_gen_ext32s_i64(vc, tmp); + tcg_gen_lea_i64(vc, vb, va, 3, 0); + tcg_gen_ext32s_i64(vc, vc); break; case 0x1B: /* S8SUBL */ @@ -1524,9 +1520,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) break; case 0x22: /* S4ADDQ */ - tmp =3D tcg_temp_new_i64(); - tcg_gen_shli_i64(tmp, va, 2); - tcg_gen_add_i64(vc, tmp, vb); + tcg_gen_lea_i64(vc, vb, va, 2, 0); break; case 0x29: /* SUBQ */ @@ -1544,9 +1538,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) break; case 0x32: /* S8ADDQ */ - tmp =3D tcg_temp_new_i64(); - tcg_gen_shli_i64(tmp, va, 3); - tcg_gen_add_i64(vc, tmp, vb); + tcg_gen_lea_i64(vc, vb, va, 3, 0); break; case 0x3B: /* S8SUBQ */ --=20 2.53.0 From nobody Sat Sep 26 20:52:34 2026 Delivered-To: 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Turner , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/16] target/loongarch: Use tcg_gen_lea_tl for ALSL Date: Wed, 16 Sep 2026 22:17:05 -1000 Message-ID: <20260917081716.946668-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917081716.946668-1-richard.henderson@linaro.org> References: <20260917081716.946668-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:3b::e; envelope-from=richard.henderson@linaro.org; helo=mail-pz2-x0e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633128780158500 Reviewed-by: Matt Turner Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/loongarch/tcg/insn_trans/trans_arith.c.inc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/loongarch/tcg/insn_trans/trans_arith.c.inc b/target/loo= ngarch/tcg/insn_trans/trans_arith.c.inc index 2be057e9320..c358e642649 100644 --- a/target/loongarch/tcg/insn_trans/trans_arith.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_arith.c.inc @@ -188,9 +188,7 @@ static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2) =20 static void gen_alsl(TCGv dest, TCGv src1, TCGv src2, target_long sa) { - TCGv t0 =3D tcg_temp_new(); - tcg_gen_shli_tl(t0, src1, sa); - tcg_gen_add_tl(dest, t0, src2); + tcg_gen_lea_tl(dest, src2, src1, sa, 0); } =20 static bool trans_lu32i_d(DisasContext *ctx, arg_lu32i_d *a) --=20 2.53.0 From nobody Sat Sep 26 20:52:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789633165; cv=none; d=zohomail.com; s=zohoarc; b=V5bQmXsySK6o12JCneoa9GtGM0mlX8TsaF1gykouAI1Y+AwNCsmbNLnZ578uhgenj9cEPUe0ox3v8MpzMGYMSYYto6VaxT/aSZqYCHGNYU28SvYgLhhuWX6Rq5kV4UcMhn+hXv1sl7o17InAngITVz5GxpnDBUKxNwdlAOy+sG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633166920158500 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20260831062630.58771-1-philmd@oss.qualcomm.com> --- target/mips/tcg/mxu_translate.c | 3 +-- target/mips/tcg/translate_addr_const.c | 6 ++---- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index a38f4da12ba..5361c94b343 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -1596,8 +1596,7 @@ static void gen_mxu_s32ldxvx(DisasContext *ctx, bool = reversed, =20 gen_load_gpr(t0, Rb); gen_load_gpr(t1, Rc); - tcg_gen_shli_i32(t1, t1, strd2); - tcg_gen_add_i32(t0, t0, t1); + tcg_gen_lea_i32(t0, t0, t1, strd2, 0); =20 tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_SL | mo_endian_rev(ctx, reversed) | diff --git a/target/mips/tcg/translate_addr_const.c b/target/mips/tcg/trans= late_addr_const.c index 1d140e918da..910177e43bc 100644 --- a/target/mips/tcg/translate_addr_const.c +++ b/target/mips/tcg/translate_addr_const.c @@ -26,8 +26,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, i= nt sa) t1 =3D tcg_temp_new(); gen_load_gpr(t0, rs); gen_load_gpr(t1, rt); - tcg_gen_shli_tl(t0, t0, sa); - tcg_gen_add_tl(cpu_gpr[rd], t0, t1); + tcg_gen_lea_tl(cpu_gpr[rd], t1, t0, sa, 0); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); return true; } @@ -47,7 +46,6 @@ bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, = int sa) t1 =3D tcg_temp_new(); gen_load_gpr(t0, rs); gen_load_gpr(t1, rt); - tcg_gen_shli_tl(t0, t0, sa); - tcg_gen_add_tl(cpu_gpr[rd], t0, t1); + tcg_gen_lea_tl(cpu_gpr[rd], t1, t0, sa, 0); return true; } --=20 2.53.0 From nobody Sat Sep 26 20:52:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org 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List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633166909158500 Reviewed-by: Matt Turner Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/riscv/tcg/insn_trans/trans_rvb.c.inc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/riscv/tcg/insn_trans/trans_rvb.c.inc b/target/riscv/tcg= /insn_trans/trans_rvb.c.inc index 3e74be223b0..82e715c7b73 100644 --- a/target/riscv/tcg/insn_trans/trans_rvb.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvb.c.inc @@ -336,10 +336,7 @@ static bool trans_orc_b(DisasContext *ctx, arg_orc_b *= a) #define GEN_SHADD(SHAMT) \ static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \ { \ - TCGv t =3D tcg_temp_new(); \ - \ - tcg_gen_shli_tl(t, arg1, SHAMT); \ - tcg_gen_add_tl(ret, t, arg2); \ + tcg_gen_lea_tl(ret, arg2, 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006d021491bc7-6c7d1fcb286mr5613099eaf.18.1789633047786; Thu, 17 Sep 2026 01:17:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Matt Turner , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 08/16] target/s390x: Use tcg_gen_lea_i64 in get_address Date: Wed, 16 Sep 2026 22:17:08 -1000 Message-ID: <20260917081716.946668-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917081716.946668-1-richard.henderson@linaro.org> References: <20260917081716.946668-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:30::10; envelope-from=richard.henderson@linaro.org; helo=mail-oa2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633178982158500 While there's no actual shift, use the compound function to add two registers and an immediate in one step. Reviewed-by: Matt Turner Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 1b6023168bb..4eb2eba5e45 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -460,8 +460,8 @@ static TCGv_i64 get_address(DisasContext *s, int x2, in= t b2, int d2) * displacements early we create larger immediate addends. */ if (b2 && x2) { - tcg_gen_add_i64(tmp, regs[b2], regs[x2]); - gen_addi_and_wrap_i64(s, tmp, tmp, d2); + tcg_gen_lea_i64(tmp, regs[b2], regs[x2], 0, d2); + gen_addi_and_wrap_i64(s, tmp, tmp, 0); } else if (b2) { gen_addi_and_wrap_i64(s, tmp, regs[b2], d2); } else if (x2) { --=20 2.53.0 From nobody Sat Sep 26 20:52:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 17 Sep 2026 01:17:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Matt Turner Subject: [PATCH v2 09/16] target/i386: Use tcg_gen_lea_tl in gen_lea_modrm_1 Date: Wed, 16 Sep 2026 22:17:09 -1000 Message-ID: <20260917081716.946668-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917081716.946668-1-richard.henderson@linaro.org> References: <20260917081716.946668-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::e; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x0e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633120906158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Matt Turner Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 192cf43215e..ce14d1be028 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1615,31 +1615,32 @@ static TCGv gen_shiftd_rm_T1(DisasContext *s, MemOp= ot, /* Compute the address, with a minimum number of TCG ops. */ static TCGv gen_lea_modrm_1(DisasContext *s, AddressParts a, bool is_vsib) { - TCGv ea =3D NULL; + TCGv ea =3D (a.base >=3D 0 ? cpu_regs[a.base] : NULL); =20 if (a.index >=3D 0 && !is_vsib) { + TCGv index =3D cpu_regs[a.index]; + + if (ea) { + tcg_gen_lea_tl(s->A0, ea, index, a.scale, a.disp); + return s->A0; + } if (a.scale =3D=3D 0) { - ea =3D cpu_regs[a.index]; + ea =3D index; } else { - tcg_gen_shli_tl(s->A0, cpu_regs[a.index], a.scale); + tcg_gen_shli_tl(s->A0, index, a.scale); ea =3D s->A0; } - if (a.base >=3D 0) { - tcg_gen_add_tl(s->A0, ea, cpu_regs[a.base]); - ea =3D s->A0; - } - } else if (a.base >=3D 0) { - ea =3D cpu_regs[a.base]; - } - if (!ea) { + } else if (!ea) { if (tb_cflags(s->base.tb) & CF_PCREL && a.base =3D=3D -2) { /* With cpu_eip ~=3D pc_save, the expression is pc-relative. */ tcg_gen_addi_tl(s->A0, cpu_eip, a.disp - s->pc_save); } else { tcg_gen_movi_tl(s->A0, a.disp); } - ea =3D s->A0; - } else if (a.disp !=3D 0) { + return s->A0; + } + + if (a.disp !=3D 0) { tcg_gen_addi_tl(s->A0, ea, a.disp); ea =3D s->A0; } --=20 2.53.0 From nobody Sat Sep 26 20:52:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789633134; cv=none; d=zohomail.com; s=zohoarc; b=hg0s8u9KCGlqgySOmz2w6gjJmkUugc1z8cvZcyRb8yviZOcQf4PMEJ71mJ7ZqbxkpFYyGfz85v/AlRWLYTUFFvbz0fplYm7MvTg+HQ5U7LuXiUtahp2dQ+RCnl7ePE4jO0knlO070clbNmB5HR7mdJhZMBa8TNOqKtCWFHgAta8= ARC-Message-Signature: i=1; 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Thu, 17 Sep 2026 01:17:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Matt Turner Subject: [PATCH v2 10/16] tcg/x86_64: Introduce TCG_REG_NONE Date: Wed, 16 Sep 2026 22:17:10 -1000 Message-ID: <20260917081716.946668-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917081716.946668-1-richard.henderson@linaro.org> References: <20260917081716.946668-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:30::26; envelope-from=richard.henderson@linaro.org; helo=mail-oa2-x26.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633136887158500 Content-Type: text/plain; charset="utf-8" Rather than hard-code -1, or compare < 0, use something more descriptive. This also allows more use of TCGReg. Reviewed-by: Matt Turner Signed-off-by: Richard Henderson --- tcg/x86_64/tcg-target.h | 1 + tcg/x86_64/tcg-target.c.inc | 66 ++++++++++++++++++++----------------- 2 files changed, 36 insertions(+), 31 deletions(-) diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h index 7ebae56a7d7..7109722f240 100644 --- a/tcg/x86_64/tcg-target.h +++ b/tcg/x86_64/tcg-target.h @@ -31,6 +31,7 @@ #define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB) =20 typedef enum { + TCG_REG_NONE =3D -1, TCG_REG_EAX =3D 0, TCG_REG_ECX, TCG_REG_EDX, diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc index 660350b963d..ec397e287c0 100644 --- a/tcg/x86_64/tcg-target.c.inc +++ b/tcg/x86_64/tcg-target.c.inc @@ -210,7 +210,8 @@ static bool tcg_target_const_match(int64_t val, int ct, return 0; } =20 -# define LOWREGMASK(x) ((x) & 7) +#define LOWREGMASK(x) ((x) & 7) +#define REGOR0(x) ((x) =3D=3D TCG_REG_NONE ? 0 : (x)) =20 #define P_EXT 0x100 /* 0x0f opcode prefix */ #define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ @@ -524,7 +525,7 @@ static const uint8_t tcg_cond_to_jcc[] =3D { [TCG_COND_TSTNE] =3D JCC_JNE, }; =20 -static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) +static void tcg_out_opc(TCGContext *s, int opc, TCGReg r, TCGReg rm, TCGRe= g x) { int rex; =20 @@ -572,14 +573,14 @@ static void tcg_out_opc(TCGContext *s, int opc, int r= , int rm, int x) tcg_out8(s, opc); } =20 -static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) +static void tcg_out_modrm(TCGContext *s, int opc, TCGReg r, TCGReg rm) { tcg_out_opc(s, opc, r, rm, 0); tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } =20 -static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, - int rm, int index) +static void tcg_out_vex_opc(TCGContext *s, int opc, TCGReg r, TCGReg v, + TCGReg rm, TCGReg index) { int tmp; =20 @@ -630,8 +631,8 @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int= r, int v, tcg_out8(s, opc); } =20 -static void tcg_out_evex_opc(TCGContext *s, int opc, int r, int v, - int rm, int index, int aaa, bool z) +static void tcg_out_evex_opc(TCGContext *s, int opc, TCGReg r, TCGReg v, + TCGReg rm, TCGReg index, int aaa, bool z) { /* The entire 4-byte evex prefix; with R' and V' set. */ uint32_t p =3D 0x08041062; @@ -676,7 +677,8 @@ static void tcg_out_evex_opc(TCGContext *s, int opc, in= t r, int v, tcg_out8(s, opc); } =20 -static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) +static void tcg_out_vex_modrm(TCGContext *s, int opc, TCGReg r, + TCGReg v, TCGReg rm) { if (opc & P_EVEX) { tcg_out_evex_opc(s, opc, r, v, rm, 0, 0, false); @@ -687,7 +689,7 @@ static void tcg_out_vex_modrm(TCGContext *s, int opc, i= nt r, int v, int rm) } =20 static void tcg_out_vex_modrm_type(TCGContext *s, int opc, - int r, int v, int rm, TCGType type) + TCGReg r, TCGReg v, TCGReg rm, TCGType = type) { if (type =3D=3D TCG_TYPE_V256) { opc |=3D P_VEXL; @@ -695,8 +697,8 @@ static void tcg_out_vex_modrm_type(TCGContext *s, int o= pc, tcg_out_vex_modrm(s, opc, r, v, rm); } =20 -static void tcg_out_evex_modrm_type(TCGContext *s, int opc, int r, int v, - int rm, int aaa, bool z, TCGType type) +static void tcg_out_evex_modrm_type(TCGContext *s, int opc, TCGReg r, TCGR= eg v, + TCGReg rm, int aaa, bool z, TCGType ty= pe) { if (type =3D=3D TCG_TYPE_V256) { opc |=3D P_VEXL; @@ -710,12 +712,12 @@ static void tcg_out_evex_modrm_type(TCGContext *s, in= t opc, int r, int v, mode for absolute addresses, ~RM is the size of the immediate operand that will follow the instruction. */ =20 -static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, +static void tcg_out_sib_offset(TCGContext *s, TCGReg r, TCGReg rm, TCGReg = index, int shift, intptr_t offset) { int mod, len; =20 - if (index < 0 && rm < 0) { + if (index =3D=3D TCG_REG_NONE && rm =3D=3D TCG_REG_NONE) { /* * Try for a rip-relative addressing mode. This has replaced * the 32-bit-mode absolute addressing encoding. @@ -746,7 +748,7 @@ static void tcg_out_sib_offset(TCGContext *s, int r, in= t rm, int index, =20 /* Find the length of the immediate addend. Note that the encoding that would be used for (%ebp) indicates absolute addressing. */ - if (rm < 0) { + if (rm =3D=3D TCG_REG_NONE) { mod =3D 0, len =3D 4, rm =3D 5; } else if (offset =3D=3D 0 && LOWREGMASK(rm) !=3D TCG_REG_EBP) { mod =3D 0, len =3D 0; @@ -758,7 +760,7 @@ static void tcg_out_sib_offset(TCGContext *s, int r, in= t rm, int index, =20 /* Use a single byte MODRM format if possible. Note that the encoding that would be used for %esp is the escape to the two byte form. */ - if (index < 0 && LOWREGMASK(rm) !=3D TCG_REG_ESP) { + if (index =3D=3D TCG_REG_NONE && LOWREGMASK(rm) !=3D TCG_REG_ESP) { /* Single byte MODRM format. */ tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } else { @@ -767,7 +769,7 @@ static void tcg_out_sib_offset(TCGContext *s, int r, in= t rm, int index, /* Note that the encoding that would place %esp into the index field indicates no index register. In 64-bit mode, the REX.X bit counts, so %r12 can be used as the index. */ - if (index < 0) { + if (index =3D=3D TCG_REG_NONE) { index =3D 4; } else { tcg_debug_assert(index !=3D TCG_REG_ESP); @@ -784,32 +786,34 @@ static void tcg_out_sib_offset(TCGContext *s, int r, = int rm, int index, } } =20 -static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, - int index, int shift, intptr_t offset) +static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, TCGReg r, + TCGReg rm, TCGReg index, + int shift, intptr_t offset) { - tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index); + tcg_out_opc(s, opc, r, REGOR0(rm), REGOR0(index)); tcg_out_sib_offset(s, r, rm, index, shift, offset); } =20 -static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, in= t v, - int rm, int index, int shift, +static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, + TCGReg r, TCGReg v, TCGReg rm, + TCGReg index, int shift, intptr_t offset) { - tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index); + tcg_out_vex_opc(s, opc, r, v, REGOR0(rm), REGOR0(index)); tcg_out_sib_offset(s, r, rm, index, shift, offset); } =20 /* A simplification of the above with no index or shift. */ -static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, - int rm, intptr_t offset) +static void tcg_out_modrm_offset(TCGContext *s, int opc, TCGReg r, + TCGReg rm, intptr_t offset) { - tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset); + tcg_out_modrm_sib_offset(s, opc, r, rm, TCG_REG_NONE, 0, offset); } =20 -static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r, - int v, int rm, intptr_t offset) +static void tcg_out_vex_modrm_offset(TCGContext *s, int opc, TCGReg r, + TCGReg v, TCGReg rm, intptr_t offset) { - tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset); + tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, TCG_REG_NONE, 0, offset= ); } =20 /* Output an opcode with an expected reference to the constant pool. */ @@ -1889,7 +1893,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 #ifdef CONFIG_USER_ONLY static HostAddress x86_guest_base =3D { - .index =3D -1 + .index =3D TCG_REG_NONE }; =20 #if defined(__linux__) @@ -2173,7 +2177,7 @@ static void tgen_qemu_ld(TCGContext *s, TCGType type,= TCGReg data, HostAddress h; =20 ldst =3D prepare_host_addr(s, &h, addr, oi, true); - tcg_out_qemu_ld_direct(s, data, -1, h, type, get_memop(oi)); + tcg_out_qemu_ld_direct(s, data, TCG_REG_NONE, h, type, get_memop(oi)); =20 if (ldst) { ldst->type =3D type; @@ -2311,7 +2315,7 @@ static void tgen_qemu_st(TCGContext *s, TCGType type,= TCGReg data, HostAddress h; =20 ldst =3D prepare_host_addr(s, &h, addr, oi, false); - tcg_out_qemu_st_direct(s, data, -1, h, get_memop(oi)); + tcg_out_qemu_st_direct(s, data, TCG_REG_NONE, h, get_memop(oi)); =20 if (ldst) { ldst->type =3D type; --=20 2.53.0 From nobody Sat Sep 26 20:52:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Thu, 17 Sep 2026 01:17:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Matt Turner Subject: [PATCH v2 11/16] tcg/x86_64: Implement INDEX_op_lea Date: Wed, 16 Sep 2026 22:17:11 -1000 Message-ID: <20260917081716.946668-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917081716.946668-1-richard.henderson@linaro.org> References: <20260917081716.946668-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633102749158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Matt Turner Signed-off-by: Richard Henderson --- tcg/x86_64/tcg-target-con-set.h | 1 + tcg/x86_64/tcg-target-has.h | 4 ++-- tcg/x86_64/tcg-target.h | 2 ++ tcg/x86_64/tcg-target.c.inc | 11 ++++++++++- 4 files changed, 15 insertions(+), 3 deletions(-) diff --git a/tcg/x86_64/tcg-target-con-set.h b/tcg/x86_64/tcg-target-con-se= t.h index 458d69c3c07..5af8c1cb2cd 100644 --- a/tcg/x86_64/tcg-target-con-set.h +++ b/tcg/x86_64/tcg-target-con-set.h @@ -46,6 +46,7 @@ C_O1_I2(r, r, r) C_O1_I2(r, r, re) C_O1_I2(r, r, ri) C_O1_I2(r, rO, re) +C_O1_I2(r, rz, r) C_O1_I2(x, x, x) C_N1_I2(r, r, r) C_N1_I2(r, r, rW) diff --git a/tcg/x86_64/tcg-target-has.h b/tcg/x86_64/tcg-target-has.h index 6ffae51f923..f1d3d256eeb 100644 --- a/tcg/x86_64/tcg-target-has.h +++ b/tcg/x86_64/tcg-target-has.h @@ -105,7 +105,7 @@ tcg_target_extract_valid(TCGType type, unsigned ofs, un= signed len) } #define TCG_TARGET_extract_valid tcg_target_extract_valid =20 -#define TCG_TARGET_lea_sh_valid(type, sh) 0 -#define TCG_TARGET_lea_imm_valid(type, imm) 0 +#define TCG_TARGET_lea_sh_valid(type, sh) ((sh) <=3D 3) +#define TCG_TARGET_lea_imm_valid(type, imm) ((imm) =3D=3D (int32_t)= (imm)) =20 #endif diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h index 7109722f240..3444bcdca0a 100644 --- a/tcg/x86_64/tcg-target.h +++ b/tcg/x86_64/tcg-target.h @@ -80,4 +80,6 @@ typedef enum { TCG_REG_CALL_STACK =3D TCG_REG_ESP } TCGReg; =20 +#define TCG_REG_ZERO TCG_REG_NONE + #endif diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc index ec397e287c0..a41252782e1 100644 --- a/tcg/x86_64/tcg-target.c.inc +++ b/tcg/x86_64/tcg-target.c.inc @@ -3331,8 +3331,17 @@ static const TCGOutOpStore outop_st =3D { .out_i =3D tgen_st_i, }; =20 +static void tgen_lea(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + TCGReg a2, unsigned sh, tcg_target_long imm) +{ + int rexw =3D type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW; + tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, sh, imm); +} + static const TCGOutOpLea outop_lea =3D { - .base.static_constraint =3D C_NotImplemented, + /* Allow "lea imm(, a2, sh), a0" via TCG_REG_ZERO constraint */ + .base.static_constraint =3D C_O1_I2(r, rz, r), + .out =3D tgen_lea, }; =20 static int const umin_insn[4] =3D { --=20 2.53.0 From nobody Sat Sep 26 20:52:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 17 Sep 2026 01:17:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Matt Turner Subject: [PATCH v2 12/16] tcg/loongarch64: Import SLADD insns Date: Wed, 16 Sep 2026 22:17:12 -1000 Message-ID: <20260917081716.946668-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917081716.946668-1-richard.henderson@linaro.org> References: <20260917081716.946668-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::11; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x11.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633087118158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Matt Turner Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-insn-defs.c.inc | 30 ++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc b/tcg/loongarch64/tcg-insn= -defs.c.inc index e907fc755f5..ececc6a3dd5 100644 --- a/tcg/loongarch64/tcg-insn-defs.c.inc +++ b/tcg/loongarch64/tcg-insn-defs.c.inc @@ -4,7 +4,7 @@ * * This file is auto-generated by genqemutcgdefs from * https://github.com/loongson-community/loongarch-opcodes, - * from commit 1b95bb8c443ad71e266120fd97bd227df2d8ecfc. + * from commit 2d84c975e8894afc8b3ee9b8559f10308a658440. * DO NOT EDIT. */ =20 @@ -24,6 +24,7 @@ typedef enum { OPC_REVBIT_D =3D 0x00005400, OPC_SEXT_H =3D 0x00005800, OPC_SEXT_B =3D 0x00005c00, + OPC_SLADD_W =3D 0x00040000, OPC_ADD_W =3D 0x00100000, OPC_ADD_D =3D 0x00108000, OPC_SUB_W =3D 0x00110000, @@ -62,6 +63,7 @@ typedef enum { OPC_MOD_D =3D 0x00228000, OPC_DIV_DU =3D 0x00230000, OPC_MOD_DU =3D 0x00238000, + OPC_SLADD_D =3D 0x002c0000, OPC_SLLI_W =3D 0x00408000, OPC_SLLI_D =3D 0x00410000, OPC_SRLI_W =3D 0x00448000, @@ -619,6 +621,18 @@ encode_djk_insn(LoongArchInsn opc, TCGReg d, TCGReg j,= TCGReg k) return encode_djk_slots(opc, d, j, k); } =20 +static int32_t __attribute__((unused)) encode_djkua2_insn(LoongArchInsn op= c, + TCGReg d, TCGReg= j, + TCGReg k, + uint32_t ua2) +{ + tcg_debug_assert(d >=3D 0 && d <=3D 0x1f); + tcg_debug_assert(j >=3D 0 && j <=3D 0x1f); + tcg_debug_assert(k >=3D 0 && k <=3D 0x1f); + tcg_debug_assert(ua2 <=3D 0x3); + return encode_djka_slots(opc, d, j, k, ua2); +} + static int32_t __attribute__((unused)) encode_djsk12_insn(LoongArchInsn opc, TCGReg d, TCGReg j, int32_t sk12) { @@ -1426,6 +1440,13 @@ static void __attribute__((unused)) tcg_out_opc_sext= _b(TCGContext *s, TCGReg d, tcg_out32(s, encode_dj_insn(OPC_SEXT_B, d, j)); } =20 +/* Emits the `sladd.w d, j, k, ua2` instruction. */ +static void __attribute__((unused)) +tcg_out_opc_sladd_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k, uint32_t = ua2) +{ + tcg_out32(s, encode_djkua2_insn(OPC_SLADD_W, d, j, k, ua2)); +} + /* Emits the `add.w d, j, k` instruction. */ static void __attribute__((unused)) tcg_out_opc_add_w(TCGContext *s, TCGRe= g d, TCGReg j, TCGReg k) @@ -1692,6 +1713,13 @@ static void __attribute__((unused)) tcg_out_opc_mod_= du(TCGContext *s, TCGReg d, tcg_out32(s, encode_djk_insn(OPC_MOD_DU, d, j, k)); } =20 +/* Emits the `sladd.d d, j, k, ua2` instruction. */ +static void __attribute__((unused)) +tcg_out_opc_sladd_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k, uint32_t = ua2) +{ + tcg_out32(s, encode_djkua2_insn(OPC_SLADD_D, d, j, k, ua2)); +} + /* Emits the `slli.w d, j, uk5` instruction. */ static void __attribute__((unused)) tcg_out_opc_slli_w(TCGContext *s, TCGR= eg d, TCGReg j, uint32_t = uk5) --=20 2.53.0 From nobody Sat Sep 26 20:52:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789633099; cv=none; d=zohomail.com; s=zohoarc; b=dwULFakTJYZ9+UTzAAj7j2UcDfVcFnHZXB/Yma7X/ieZ5ABBFvwCMyDRGHznleOpnKNAa+OUfd6wPqHlEjLTuDZQnpRRkq/rp+gX2VMorpUyLrIC3R6N/MYusrkWlrsiD6zo9pB2RFxY08amMzenSd/+g8jowIp+HXoKiOiRxdc= ARC-Message-Signature: i=1; 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Thu, 17 Sep 2026 01:17:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Matt Turner Subject: [PATCH v2 13/16] tcg/loongarch64: Implement INDEX_op_lea Date: Wed, 16 Sep 2026 22:17:13 -1000 Message-ID: <20260917081716.946668-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917081716.946668-1-richard.henderson@linaro.org> References: <20260917081716.946668-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::10; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633100703158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Matt Turner Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-has.h | 4 ++-- tcg/loongarch64/tcg-target.c.inc | 13 ++++++++++++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-= has.h index 31e6ea9632d..53b7ca40571 100644 --- a/tcg/loongarch64/tcg-target-has.h +++ b/tcg/loongarch64/tcg-target-has.h @@ -54,7 +54,7 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, uns= igned len) } #define TCG_TARGET_sextract_valid tcg_target_sextract_valid =20 -#define TCG_TARGET_lea_sh_valid(type, sh) 0 -#define TCG_TARGET_lea_imm_valid(type, imm) 0 +#define TCG_TARGET_lea_sh_valid(type, sh) ((sh) >=3D 1 && (sh) <= =3D 4) +#define TCG_TARGET_lea_imm_valid(type, imm) ((imm) =3D=3D 0) =20 #endif diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 17784d8bbe2..377cd9ec08d 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -2098,8 +2098,19 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static void tgen_lea(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + TCGReg a2, unsigned sh, tcg_target_long imm) +{ + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_opc_sladd_w(s, a0, a2, a1, sh - 1); + } else { + tcg_out_opc_sladd_d(s, a0, a2, a1, sh - 1); + } +} + static const TCGOutOpLea outop_lea =3D { - .base.static_constraint =3D C_NotImplemented, + .base.static_constraint =3D C_O1_I2(r, r, r), + .out =3D tgen_lea, }; =20 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, --=20 2.53.0 From nobody Sat Sep 26 20:52:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789633167; cv=none; d=zohomail.com; s=zohoarc; b=diTtYmXLzlX7GketRsbddLvxfrlVzJD8RkFYwk5rG1v6Y63SwbEsWXCNDFpV4IhtcQgbuFjA329bJ8u2i36nBMIHjRu8P2Jzaot0isVzJz8IkZc895rk11afXWuYYXUr+yoT+2f7Az9U1wdpg5eXS/wkqUFQ2B8nOP3pHw0TyPA= ARC-Message-Signature: i=1; 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Thu, 17 Sep 2026 01:17:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Matt Turner Subject: [PATCH v2 14/16] tcg/aarch64: Implement INDEX_op_lea Date: Wed, 16 Sep 2026 22:17:14 -1000 Message-ID: <20260917081716.946668-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917081716.946668-1-richard.henderson@linaro.org> References: <20260917081716.946668-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633168915158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Matt Turner Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 4 ++-- tcg/aarch64/tcg-target.c.inc | 9 ++++++++- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h index 86672b2eab4..9420a7bc73c 100644 --- a/tcg/aarch64/tcg-target-has.h +++ b/tcg/aarch64/tcg-target-has.h @@ -57,7 +57,7 @@ #define TCG_TARGET_sextract_valid(type, ofs, len) 1 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 =20 -#define TCG_TARGET_lea_sh_valid(type, sh) 0 -#define TCG_TARGET_lea_imm_valid(type, imm) 0 +#define TCG_TARGET_lea_sh_valid(type, sh) ((sh) < tcg_type_size(type)= * 8) +#define TCG_TARGET_lea_imm_valid(type, imm) ((imm) =3D=3D 0) =20 #endif diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 76adb2256f9..6836c0dd94f 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -3081,8 +3081,15 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static void tgen_lea(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + TCGReg a2, unsigned sh, tcg_target_long imm) +{ + tcg_out_insn(s, addsub_realshift, ADD_LSL, type, a0, a1, a2, sh); +} + static const TCGOutOpLea outop_lea =3D { - .base.static_constraint =3D C_NotImplemented, + .base.static_constraint =3D C_O1_I2(r, r, r), + .out =3D tgen_lea, }; =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, --=20 2.53.0 From nobody Sat Sep 26 20:52:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789633099; cv=none; d=zohomail.com; s=zohoarc; b=OFJ1NXz9dJBTUw55CWLQB2E8KuVfKZiOCLCOjHa13FustLAtaZuUMVDeSX1kzfqvFNue9Ibpz12bq6f38+o0ZYeXUsR1QA0TY5iHgVGBoGzKkKxqUqlT2JLlXHFXeG9tk1dWVGxzs7i4WdCmKx/7zCc0+5EZF+se+p5QiVBLSfU= ARC-Message-Signature: i=1; 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Thu, 17 Sep 2026 01:17:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Matt Turner Subject: [PATCH v2 15/16] tcg/riscv64: Implement INDEX_op_lea Date: Wed, 16 Sep 2026 22:17:15 -1000 Message-ID: <20260917081716.946668-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917081716.946668-1-richard.henderson@linaro.org> References: <20260917081716.946668-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:31::d; envelope-from=richard.henderson@linaro.org; helo=mail-oo2-x0d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633100710158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Matt Turner Signed-off-by: Richard Henderson --- tcg/riscv64/tcg-target-has.h | 12 ++++++++++-- tcg/riscv64/tcg-target.c.inc | 16 +++++++++++++++- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/tcg/riscv64/tcg-target-has.h b/tcg/riscv64/tcg-target-has.h index 93f8baad09f..3cdeb5c3900 100644 --- a/tcg/riscv64/tcg-target-has.h +++ b/tcg/riscv64/tcg-target-has.h @@ -69,7 +69,15 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, un= signed len) =20 #define TCG_TARGET_deposit_valid(type, ofs, len) 0 =20 -#define TCG_TARGET_lea_sh_valid(type, sh) 0 -#define TCG_TARGET_lea_imm_valid(type, imm) 0 +/* + * The SH*ADD instructions only operate on full register width. + * To allow TCG_TYPE_I32, we'd need a subsequent extension, + * with the result no better than the separate shift+add insns. + */ +#define TCG_TARGET_lea_sh_valid(type, sh) \ + (cpuinfo & CPUINFO_ZBA && \ + (type) =3D=3D TCG_TYPE_REG && \ + (sh) >=3D 1 && (sh) <=3D 3) +#define TCG_TARGET_lea_imm_valid(type, imm) ((imm) =3D=3D 0) =20 #endif diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index df4c4a9789b..ba7aab9246c 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -224,6 +224,7 @@ typedef enum { =20 /* Zba: Bit manipulation extension, address generation */ OPC_ADD_UW =3D 0x0800003b, + OPC_SHxADD =3D 0x20000033, /* plus sh << 13 */ =20 /* Zbb: Bit manipulation extension, basic bit manipulation */ OPC_ANDN =3D 0x40007033, @@ -2725,8 +2726,21 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static void tgen_lea(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + TCGReg a2, unsigned sh, tcg_target_long imm) +{ + tcg_out32(s, encode_r(OPC_SHxADD, a0, a2, a1) | (sh << 13)); +} + +static TCGConstraintSetIndex cset_zba_rrr(TCGType type, unsigned flags) +{ + return cpuinfo & CPUINFO_ZBA ? C_O1_I2(r, r, r) : C_NotImplemented; +} + static const TCGOutOpLea outop_lea =3D { - .base.static_constraint =3D C_NotImplemented, + .base.static_constraint =3D C_Dynamic, + .base.dynamic_constraint =3D cset_zba_rrr, + .out =3D tgen_lea, }; =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, --=20 2.53.0 From nobody Sat Sep 26 20:52:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789633176; cv=none; d=zohomail.com; s=zohoarc; b=IaFnnVl/B/UeStwM1O0aYFDQ9uY7dE6VswTcTxUT6gk58qemCjNuud+cGD26FUvJapm3uMJYKdqRwqwtTCbrKMKJWrIlrzk2CrqIUSqd0iLnhRXJN6GXIE2o5+j++OPHU95pBkAj6AQ0VItghTBtvqBCOERxG6tTEov8FWpA4sQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789633176; 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Thu, 17 Sep 2026 01:17:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Matt Turner Subject: [PATCH v2 16/16] tcg/s390x: Implement INDEX_op_lea Date: Wed, 16 Sep 2026 22:17:16 -1000 Message-ID: <20260917081716.946668-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917081716.946668-1-richard.henderson@linaro.org> References: <20260917081716.946668-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:31::2b; envelope-from=richard.henderson@linaro.org; helo=mail-oo2-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789633176980158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Matt Turner Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-has.h | 5 +++-- tcg/s390x/tcg-target.c.inc | 13 ++++++++++++- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h index 58e3afe5266..33a3b72318e 100644 --- a/tcg/s390x/tcg-target-has.h +++ b/tcg/s390x/tcg-target-has.h @@ -77,7 +77,8 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, uns= igned len) } #define TCG_TARGET_sextract_valid tcg_target_sextract_valid =20 -#define TCG_TARGET_lea_sh_valid(type, sh) 0 -#define TCG_TARGET_lea_imm_valid(type, imm) 0 +#define TCG_TARGET_lea_sh_valid(type, sh) ((sh) =3D=3D 0) +#define TCG_TARGET_lea_imm_valid(type, imm) \ + ((imm) >=3D -0x80000 && (imm) < 0x80000) =20 #endif diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 2fd7012d047..db3b2fc3c92 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -3187,8 +3187,19 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static void tgen_lea(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + TCGReg a2, unsigned sh, tcg_target_long imm) +{ + if (imm >=3D 0 && imm < 0x1000) { + tcg_out_insn(s, RX, LA, a0, a1, a2, imm); + } else { + tcg_out_insn(s, RXY, LAY, a0, a1, a2, imm); + } +} + static const TCGOutOpLea outop_lea =3D { - .base.static_constraint =3D C_NotImplemented, + .base.static_constraint =3D C_O1_I2(r, r, r), + .out =3D tgen_lea, }; =20 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, --=20 2.53.0