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Wed, 16 Sep 2026 22:23:21 -0700 (PDT) X-Received: by 2002:a17:90b:2250:b0:39d:e1f2:3400 with SMTP id 98e67ed59e1d1-39e1e5285d8mr7859141a91.5.1789622600736; Wed, 16 Sep 2026 22:23:20 -0700 (PDT) From: Subrahmanya Lingappa To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Subrahmanya Lingappa , Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Sunil V L , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v11 01/10] build: add optional librpmi dependency Date: Thu, 17 Sep 2026 10:52:40 +0530 Message-ID: <20260917052250.1041262-2-subrahmanya.lingappa@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917052250.1041262-1-subrahmanya.lingappa@oss.qualcomm.com> References: <20260917052250.1041262-1-subrahmanya.lingappa@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=subrahmanya.lingappa@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789622733232158500 Add a meson option and config probe for librpmi so RISC-V machines can opt into RPMI support when the library is available. Keep the dependency optional so default builds without librpmi continue to work. Signed-off-by: Subrahmanya Lingappa Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Sunil V L --- Kconfig.host | 3 +++ meson.build | 14 ++++++++++++++ meson_options.txt | 2 ++ scripts/meson-buildoptions.sh | 3 +++ 4 files changed, 22 insertions(+) diff --git a/Kconfig.host b/Kconfig.host index 933425c74b..6f98dadb2e 100644 --- a/Kconfig.host +++ b/Kconfig.host @@ -8,6 +8,9 @@ config LINUX config LIBCBOR bool =20 +config LIBRPMI + bool + config GNUTLS bool =20 diff --git a/meson.build b/meson.build index 6dcfdceb50..1e1e19e655 100644 --- a/meson.build +++ b/meson.build @@ -2018,6 +2018,17 @@ if lzo.found() and not cc.links(''' endif endif =20 +librpmi =3D not_found +if not get_option('librpmi').auto() or have_system + librpmi =3D dependency('librpmi', required: get_option('librpmi'), + method: 'pkg-config') + if librpmi.found() and not cc.has_header_symbol('librpmi.h', + 'rpmi_service_group_syss= usp_create', + dependencies: librpmi) + error('librpmi support requires the RPMI system suspend service group = API') + endif +endif + numa =3D not_found if not get_option('numa').auto() or have_system or have_tools numa =3D cc.find_library('numa', has_headers: ['numa.h'], @@ -2440,6 +2451,7 @@ config_host_data.set('CONFIG_LINUX', host_os =3D=3D '= linux') config_host_data.set('CONFIG_POSIX', host_os !=3D 'windows') config_host_data.set('CONFIG_WIN32', host_os =3D=3D 'windows') config_host_data.set('CONFIG_LZO', lzo.found()) +config_host_data.set('CONFIG_LIBRPMI', librpmi.found()) config_host_data.set('CONFIG_MPATH', mpathpersist.found()) config_host_data.set('CONFIG_BLKIO', blkio.found()) if blkio.found() @@ -3272,6 +3284,7 @@ host_kconfig =3D \ (multiprocess_allowed ? ['CONFIG_MULTIPROCESS_ALLOWED=3Dy'] : []) + \ (vfio_user_server_allowed ? ['CONFIG_VFIO_USER_SERVER_ALLOWED=3Dy'] : []= ) + \ (hv_balloon ? ['CONFIG_HV_BALLOON_POSSIBLE=3Dy'] : []) + \ + (librpmi.found() ? ['CONFIG_LIBRPMI=3Dy'] : []) + \ (have_rust ? ['CONFIG_HAVE_RUST=3Dy'] : []) =20 ignored =3D [ 'TARGET_XML_FILES', 'TARGET_ABI_DIR' ] @@ -4988,6 +5001,7 @@ summary_info +=3D {'TPM support': have_tpm} summary_info +=3D {'IGVM support': igvm} summary_info +=3D {'libssh support': libssh} summary_info +=3D {'lzo support': lzo} +summary_info +=3D {'RPMI support': librpmi} summary_info +=3D {'snappy support': snappy} summary_info +=3D {'bzip2 support': libbzip2} summary_info +=3D {'lzfse support': liblzfse} diff --git a/meson_options.txt b/meson_options.txt index a07cb47d35..a65af0e633 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -204,6 +204,8 @@ option('lzfse', type : 'feature', value : 'auto', description: 'lzfse support for DMG images') option('lzo', type : 'feature', value : 'auto', description: 'lzo compression support') +option('librpmi', type : 'feature', value : 'auto', + description: 'RPMI support') option('pvg', type: 'feature', value: 'auto', description: 'macOS paravirtualized graphics support') option('rbd', type : 'feature', value : 'auto', diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh index c003985047..12179f6024 100644 --- a/scripts/meson-buildoptions.sh +++ b/scripts/meson-buildoptions.sh @@ -140,6 +140,7 @@ meson_options_help() { printf "%s\n" ' libkeyutils Linux keyutils support' printf "%s\n" ' libnfs libnfs block device driver' printf "%s\n" ' libpmem libpmem support' + printf "%s\n" ' librpmi RPMI support' printf "%s\n" ' libssh ssh block device support' printf "%s\n" ' libudev Use libudev to enumerate host devices' printf "%s\n" ' libusb libusb support for USB passthrough' @@ -376,6 +377,8 @@ _meson_option_parse() { --disable-libnfs) printf "%s" -Dlibnfs=3Ddisabled ;; --enable-libpmem) printf "%s" -Dlibpmem=3Denabled ;; --disable-libpmem) printf "%s" -Dlibpmem=3Ddisabled ;; + --enable-librpmi) printf "%s" -Dlibrpmi=3Denabled ;; + --disable-librpmi) printf "%s" -Dlibrpmi=3Ddisabled ;; --enable-libssh) printf "%s" -Dlibssh=3Denabled ;; --disable-libssh) printf "%s" -Dlibssh=3Ddisabled ;; --enable-libudev) printf "%s" -Dlibudev=3Denabled ;; From nobody Sat Sep 26 20:51:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1789622651; cv=none; d=zohomail.com; s=zohoarc; b=aAg5FQUB6MpaU4lsjYQBWyzpa0npfOLMm63BaQpoC3IGuB0jx7Np2ylMhR/QtnaFncJg3steSpyvlTuX8t/gZo8suLSS7hnRHEE4HlqbxFFS205v3H/GU2yYQOFBH5lTtfk41OCaX06oiBtJ9EJklpPntZDUuYoyeDQzcKptAUc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789622651; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=E631Se8A4HeWtqwcqGDdhCC23cSAAKsM1GyrG66Xa/I=; b=LEtyWP6JWKiVaAk7X4ZKCLHyLwNFaoArcjd5BeUhqpMBLdYlMauhgqDIpD0gGYxHVhA2PNquCA38AlmRusBaLtbxJZMF2xUMaqq/p5R4ItIxMoqeCEtV13VUGq7H2or04E8YXBUVynraKz2fHauPz41MwagXWAdE1mqJjZoKdgo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1789622651564574.0736103057393; Wed, 16 Sep 2026 22:24:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x74at-0007iB-7y; Thu, 17 Sep 2026 01:23:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x74ar-0007hu-1R for qemu-devel@nongnu.org; Thu, 17 Sep 2026 01:23:33 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x74am-0003zg-PM for qemu-devel@nongnu.org; Thu, 17 Sep 2026 01:23:31 -0400 Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68H1DIOo210481 for ; Thu, 17 Sep 2026 05:23:27 GMT Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gqxw8tquw-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 17 Sep 2026 05:23:26 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-39924189378so143366a91.1 for ; Wed, 16 Sep 2026 22:23:26 -0700 (PDT) Received: from hu-slingapp-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=subrahmanya.lingappa@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789622653472158500 Content-Type: text/plain; charset="utf-8" RPMI (RISC-V Platform Management Interface) is the RISC-V non-ISA platform management specification. It defines a shared-memory transport, message protocol, and service groups for platform management. Add the QEMU transport backend and Base service plumbing for virt using librpmi. This implementation targets the RISC-V Platform Management Interface (RPMI) Specification v1.0 Ratified: https://github.com/riscv-non-isa/riscv-rpmi/releases/download/v1.0/riscv-rp= mi.pdf The librpmi backend is maintained at: https://github.com/riscv-software-src/librpmi Signed-off-by: Subrahmanya Lingappa --- MAINTAINERS | 2 + hw/misc/Kconfig | 4 + hw/misc/meson.build | 3 + hw/misc/riscv_rpmi-stub.c | 16 ++ hw/misc/riscv_rpmi.c | 505 ++++++++++++++++++++++++++++++++++ hw/misc/riscv_rpmi_internal.h | 24 ++ include/hw/misc/riscv_rpmi.h | 95 +++++++ 7 files changed, 649 insertions(+) create mode 100644 hw/misc/riscv_rpmi-stub.c create mode 100644 hw/misc/riscv_rpmi.c create mode 100644 hw/misc/riscv_rpmi_internal.h create mode 100644 include/hw/misc/riscv_rpmi.h diff --git a/MAINTAINERS b/MAINTAINERS index 6c18b8a419..d0973d470c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -372,6 +372,8 @@ F: target/riscv/ F: hw/char/riscv_htif.c F: hw/riscv/ F: hw/intc/riscv* +F: hw/misc/riscv_rpmi* +F: include/hw/misc/riscv_rpmi.h F: include/hw/char/riscv_htif.h F: include/hw/riscv/ F: common-user/host/riscv* diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 46e3c03cc8..4b75f7a706 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -264,3 +264,7 @@ config K230_DECOMP_GZIP bool =20 source macio/Kconfig + +config RISCV_RPMI + bool + depends on LIBRPMI diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 54e07aacda..1b8220c6be 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -176,3 +176,6 @@ system_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('= sbsa_ec.c')) system_ss.add(when: 'CONFIG_LASI', if_true: files('lasi.c')) =20 system_ss.add(when: 'CONFIG_AXIADO_CLK', if_true: files('axiado_clk.c')) +system_ss.add(when: 'CONFIG_RISCV_RPMI', if_true: [files( + 'riscv_rpmi.c', +), librpmi], if_false: files('riscv_rpmi-stub.c')) diff --git a/hw/misc/riscv_rpmi-stub.c b/hw/misc/riscv_rpmi-stub.c new file mode 100644 index 0000000000..dc32b43227 --- /dev/null +++ b/hw/misc/riscv_rpmi-stub.c @@ -0,0 +1,16 @@ +/* + * RISC-V RPMI stubs. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/misc/riscv_rpmi.h" + +DeviceState *riscv_rpmi_create(const RiscvRpmiConfig *cfg G_GNUC_UNUSED, + Error **errp) +{ + error_setg(errp, "RISC-V RPMI support is not compiled in"); + return NULL; +} diff --git a/hw/misc/riscv_rpmi.c b/hw/misc/riscv_rpmi.c new file mode 100644 index 0000000000..c73408714a --- /dev/null +++ b/hw/misc/riscv_rpmi.c @@ -0,0 +1,505 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * RISC-V RPMI transport device. + * + * Copyright (c) 2026 Qualcomm Technologies, Inc. + * Author: + * Subrahmanya Lingappa + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/core/qdev-properties.h" +#include "hw/misc/riscv_rpmi.h" +#include "hw/misc/riscv_rpmi_internal.h" +#include "migration/vmstate.h" +#include "system/address-spaces.h" +#include "system/memory.h" +#include "system/runstate.h" +#include "librpmi.h" +#include "librpmi_env.h" + +/* + * These functions implement the platform hooks declared by librpmi_env.h. + * See https://github.com/riscv-software-src/librpmi/blob/main/include/ + * librpmi_env.h for the external hook declarations and their contract. + */ +void *rpmi_env_zalloc(rpmi_size_t size) +{ + return g_malloc0(size); +} + +void rpmi_env_free(void *ptr) +{ + g_free(ptr); +} + +void rpmi_env_writel(rpmi_uint64_t addr, rpmi_uint32_t val) +{ + MemTxResult result; + + address_space_stl_le(&address_space_memory, addr, val, + MEMTXATTRS_UNSPECIFIED, &result); + if (result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: failed write at 0x%" PRIx64 + " (result 0x%x)\n", + __func__, (uint64_t)addr, result); + } +} + +static enum rpmi_error riscv_rpmi_memtx_result_to_error(MemTxResult result) +{ + return result =3D=3D MEMTX_OK ? RPMI_SUCCESS : RPMI_ERR_IO; +} + +static bool riscv_rpmi_addr_in_range(uint64_t addr, uint32_t len, + uint64_t base, uint64_t size) +{ + return len && size >=3D len && addr >=3D base && addr - base <=3D size= - len; +} + +static enum rpmi_error shmem_qemu_read(void *priv, rpmi_uint64_t addr, + void *buf, rpmi_uint32_t len) +{ + RiscvRpmiState *s =3D RISCV_RPMI(priv); + + if (!s || !buf || + !riscv_rpmi_addr_in_range(addr, len, s->shmem_base, + s->shmem_size)) { + return RPMI_ERR_BAD_RANGE; + } + + return riscv_rpmi_memtx_result_to_error( + address_space_read(&address_space_memory, addr, + MEMTXATTRS_UNSPECIFIED, buf, len)); +} + +static enum rpmi_error shmem_qemu_write(void *priv, rpmi_uint64_t addr, + const void *buf, rpmi_uint32_t len) +{ + RiscvRpmiState *s =3D RISCV_RPMI(priv); + + if (!s || !buf || + !riscv_rpmi_addr_in_range(addr, len, s->shmem_base, + s->shmem_size)) { + return RPMI_ERR_BAD_RANGE; + } + + return riscv_rpmi_memtx_result_to_error( + address_space_write(&address_space_memory, addr, + MEMTXATTRS_UNSPECIFIED, buf, len)); +} + +static enum rpmi_error shmem_qemu_fill(void *priv, rpmi_uint64_t addr, + char ch, rpmi_uint32_t len) +{ + RiscvRpmiState *s =3D RISCV_RPMI(priv); + + if (!s || + !riscv_rpmi_addr_in_range(addr, len, s->shmem_base, + s->shmem_size)) { + return RPMI_ERR_BAD_RANGE; + } + + return riscv_rpmi_memtx_result_to_error( + address_space_set(&address_space_memory, addr, (uint8_t)ch, len, + MEMTXATTRS_UNSPECIFIED)); +} + +const struct rpmi_shmem_platform_ops rpmi_shmem_qemu_ops =3D { + .read =3D shmem_qemu_read, + .write =3D shmem_qemu_write, + .fill =3D shmem_qemu_fill, +}; + +static uint64_t riscv_rpmi_read(void *opaque, hwaddr offset, unsigned int = size) +{ + RiscvRpmiState *s =3D opaque; + + if (offset !=3D 0 || size !=3D 4) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid read at 0x%" HWADDR_PRIx " size %u\n", + __func__, offset, size); + return 0; + } + + return s->doorbell; +} + +static bool riscv_rpmi_transport_indices_valid(RiscvRpmiState *s); + +static void riscv_rpmi_write(void *opaque, hwaddr offset, uint64_t value, + unsigned int size) +{ + RiscvRpmiState *s =3D opaque; + + if (offset !=3D 0 || size !=3D 4) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid write at 0x%" HWADDR_PRIx " size %u\n", + __func__, offset, size); + return; + } + + s->doorbell =3D value; + + if (value =3D=3D 1) { + if (s->context && riscv_rpmi_transport_indices_valid(s)) { + rpmi_context_process_a2p_request(s->context); + rpmi_context_process_all_events(s->context); + } + s->doorbell =3D 0; + } +} + +static const MemoryRegionOps riscv_rpmi_ops =3D { + .read =3D riscv_rpmi_read, + .write =3D riscv_rpmi_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static bool riscv_rpmi_queue_indices_valid(RiscvRpmiState *s, + uint64_t queue_base, + uint32_t queue_size) +{ + uint8_t *shmem =3D memory_region_get_ram_ptr(&s->shmem); + uint32_t data_slots =3D queue_size / RPMI_QUEUE_SLOT_SIZE - 2; + uint32_t head; + uint32_t tail; + + head =3D ldl_le_p(shmem + queue_base); + tail =3D ldl_le_p(shmem + queue_base + RPMI_QUEUE_SLOT_SIZE); + if (head >=3D data_slots || tail >=3D data_slots) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid queue indices head %u tail %u slots %u\= n", + __func__, head, tail, data_slots); + return false; + } + + return true; +} + +static bool riscv_rpmi_transport_indices_valid(RiscvRpmiState *s) +{ + if (!s->has_shmem || !s->a2p_req_size) { + return false; + } + + if (!riscv_rpmi_queue_indices_valid(s, 0, s->a2p_req_size)) { + return false; + } + + return riscv_rpmi_queue_indices_valid(s, s->a2p_req_size, + s->a2p_req_size); +} + +static void riscv_rpmi_configure_base(RiscvRpmiState *s, + const RiscvRpmiConfig *cfg) +{ + s->platform_info =3D g_strdup(cfg->platform_info); + s->services =3D cfg->services; + s->service_count =3D cfg->service_count; + + if (cfg->hart_count) { + s->hart_count =3D cfg->hart_count; + if (cfg->hart_ids) { + s->hart_ids =3D g_memdup2(cfg->hart_ids, + cfg->hart_count * sizeof(*cfg->hart_id= s)); + } + } +} + +static void riscv_rpmi_init(Object *obj) +{ + RiscvRpmiState *s =3D RISCV_RPMI(obj); + + memory_region_init_io(&s->mmio, obj, &riscv_rpmi_ops, s, + TYPE_RISCV_RPMI, RPMI_DBREG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void riscv_rpmi_reset_hold(Object *obj, ResetType type) +{ + RiscvRpmiState *s =3D RISCV_RPMI(obj); + + s->doorbell =3D 0; + + if (s->has_shmem) { + memset(memory_region_get_ram_ptr(&s->shmem), 0, s->shmem_size); + memory_region_set_dirty(&s->shmem, 0, s->shmem_size); + } + +} + +static void riscv_rpmi_cleanup(RiscvRpmiState *s) +{ + + + if (s->context) { + rpmi_context_destroy(s->context); + s->context =3D NULL; + } + + if (s->transport) { + rpmi_transport_shmem_destroy(s->transport); + s->transport =3D NULL; + } + + if (s->rpmi_shmem) { + rpmi_shmem_destroy(s->rpmi_shmem); + s->rpmi_shmem =3D NULL; + } + + if (s->has_shmem) { + memory_region_del_subregion(get_system_memory(), &s->shmem); + s->has_shmem =3D false; + } +} + +bool riscv_rpmi_service_enabled(RiscvRpmiState *s, + enum rpmi_servicegroup_id service_group) +{ + uint32_t i; + + for (i =3D 0; i < s->service_count; i++) { + if (s->services[i].service_group =3D=3D service_group) { + return true; + } + } + + return false; +} + +static bool riscv_rpmi_validate_config(RiscvRpmiState *s, Error **errp) +{ + uint64_t queue_bytes; + + if (!s->shmem_size) { + error_setg(errp, "RPMI shared memory size must be non-zero"); + return false; + } + + if (s->shmem_base & (RPMI_QUEUE_SLOT_SIZE - 1)) { + error_setg(errp, "RPMI shared memory base must be %u-byte aligned", + RPMI_QUEUE_SLOT_SIZE); + return false; + } + + if (!s->a2p_req_size) { + error_setg(errp, "RPMI A2P request queue size must be non-zero"); + return false; + } + + if (!s->hart_count || !s->hart_ids) { + error_setg(errp, "RPMI transport requires hart IDs"); + return false; + } + + for (uint32_t i =3D 0; i < s->hart_count; i++) { + for (uint32_t j =3D i + 1; j < s->hart_count; j++) { + if (s->hart_ids[i] =3D=3D s->hart_ids[j]) { + error_setg(errp, "RPMI hart ID %u is duplicated", + s->hart_ids[i]); + return false; + } + } + } + + if (s->service_count && !s->services) { + error_setg(errp, "RPMI service count requires service descriptors"= ); + return false; + } + + if (s->a2p_req_size % RPMI_QUEUE_SLOT_SIZE) { + error_setg(errp, + "RPMI A2P request queue size must be a multiple of %u", + RPMI_QUEUE_SLOT_SIZE); + return false; + } + + if (s->p2a_req_size % RPMI_QUEUE_SLOT_SIZE) { + error_setg(errp, + "RPMI P2A request queue size must be a multiple of %u", + RPMI_QUEUE_SLOT_SIZE); + return false; + } + + queue_bytes =3D 2 * (uint64_t)s->a2p_req_size + + 2 * (uint64_t)s->p2a_req_size; + if (queue_bytes > s->shmem_size) { + error_setg(errp, + "RPMI shared memory size 0x%" PRIx64 + " is too small for queues 0x%" PRIx64, + s->shmem_size, queue_bytes); + return false; + } + + return true; +} + +static bool riscv_rpmi_add_service_group(RiscvRpmiState *s, + const RiscvRpmiServiceConfig *ser= vice, + Error **errp) +{ + error_setg(errp, "unsupported RPMI service group %u", + service->service_group); + return false; +} + +static bool riscv_rpmi_init_services(RiscvRpmiState *s, Error **errp) +{ + uint32_t i; + + for (i =3D 0; i < s->service_count; i++) { + if (!riscv_rpmi_add_service_group(s, &s->services[i], errp)) { + return false; + } + } + + return true; +} + +static bool riscv_rpmi_init_context(RiscvRpmiState *s, Error **errp) +{ + const char *platform_info =3D s->platform_info ?: RPMI_PLAT_INFO; + + s->rpmi_shmem =3D rpmi_shmem_create("rpmi-shmem", s->shmem_base, + s->shmem_size, + &rpmi_shmem_qemu_ops, s); + if (!s->rpmi_shmem) { + error_setg(errp, "failed to create RPMI shared memory backend"); + return false; + } + + s->transport =3D rpmi_transport_shmem_create("rpmi-shmem-transport", + RPMI_QUEUE_SLOT_SIZE, + s->a2p_req_size, + s->p2a_req_size, + s->rpmi_shmem); + if (!s->transport) { + error_setg(errp, "failed to create RPMI shared memory transport"); + return false; + } + + s->context =3D rpmi_context_create("rpmi-virt", s->transport, + RPMI_SRVGRP_ID_MAX_COUNT, + RPMI_PRIVILEGE_M_MODE, + strlen(platform_info) + 1, + platform_info); + if (!s->context) { + error_setg(errp, "failed to create RPMI context"); + return false; + } + + return riscv_rpmi_init_services(s, errp); +} + +static void riscv_rpmi_realize(DeviceState *dev, Error **errp) +{ + RiscvRpmiState *s =3D RISCV_RPMI(dev); + g_autofree char *name =3D NULL; + + if (!riscv_rpmi_validate_config(s, errp)) { + return; + } + + name =3D g_strdup_printf("rpmi-shmem@%" PRIx64, s->shmem_base); + if (!memory_region_init_ram(&s->shmem, OBJECT(dev), name, s->shmem_siz= e, + errp)) { + return; + } + + memory_region_add_subregion(get_system_memory(), s->shmem_base, &s->sh= mem); + s->has_shmem =3D true; + + if (!riscv_rpmi_init_context(s, errp)) { + riscv_rpmi_cleanup(s); + } +} + +static void riscv_rpmi_unrealize(DeviceState *dev) +{ + riscv_rpmi_cleanup(RISCV_RPMI(dev)); +} + +static const VMStateDescription riscv_rpmi_vmstate =3D { + .name =3D TYPE_RISCV_RPMI, + .unmigratable =3D 1, +}; + +static const Property riscv_rpmi_properties[] =3D { + DEFINE_PROP_UINT64("shmem-base", RiscvRpmiState, shmem_base, 0), + DEFINE_PROP_UINT64("shmem-size", RiscvRpmiState, shmem_size, 0), + DEFINE_PROP_UINT32("a2p-req-size", RiscvRpmiState, a2p_req_size, 0), + DEFINE_PROP_UINT32("p2a-req-size", RiscvRpmiState, p2a_req_size, 0), +}; + +static void riscv_rpmi_finalize(Object *obj) +{ + RiscvRpmiState *s =3D RISCV_RPMI(obj); + + g_free(s->platform_info); + g_free(s->hart_ids); +} + +static void riscv_rpmi_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->realize =3D riscv_rpmi_realize; + dc->unrealize =3D riscv_rpmi_unrealize; + dc->vmsd =3D &riscv_rpmi_vmstate; + rc->phases.hold =3D riscv_rpmi_reset_hold; + device_class_set_props(dc, riscv_rpmi_properties); +} + +static const TypeInfo riscv_rpmi_info =3D { + .name =3D TYPE_RISCV_RPMI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RiscvRpmiState), + .instance_init =3D riscv_rpmi_init, + .instance_finalize =3D riscv_rpmi_finalize, + .class_init =3D riscv_rpmi_class_init, +}; + +static void riscv_rpmi_register_types(void) +{ + type_register_static(&riscv_rpmi_info); +} + +type_init(riscv_rpmi_register_types) + +DeviceState *riscv_rpmi_create(const RiscvRpmiConfig *cfg, Error **errp) +{ + DeviceState *dev; + RiscvRpmiState *s; + + if (!cfg) { + error_setg(errp, "missing RPMI configuration"); + return NULL; + } + + dev =3D qdev_new(TYPE_RISCV_RPMI); + qdev_prop_set_uint64(dev, "shmem-base", cfg->shmem_base); + qdev_prop_set_uint64(dev, "shmem-size", cfg->shmem_size); + qdev_prop_set_uint32(dev, "a2p-req-size", cfg->a2p_req_size); + qdev_prop_set_uint32(dev, "p2a-req-size", cfg->p2a_req_size); + + s =3D RISCV_RPMI(dev); + riscv_rpmi_configure_base(s, cfg); + + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { + return NULL; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, cfg->doorbell_base); + return dev; +} diff --git a/hw/misc/riscv_rpmi_internal.h b/hw/misc/riscv_rpmi_internal.h new file mode 100644 index 0000000000..c0cb1b64e6 --- /dev/null +++ b/hw/misc/riscv_rpmi_internal.h @@ -0,0 +1,24 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * RISC-V RPMI internal service helpers. + * + * Copyright (c) 2026 Qualcomm Technologies, Inc. + * Author: + * Subrahmanya Lingappa + */ + +#ifndef HW_MISC_RISCV_RPMI_INTERNAL_H +#define HW_MISC_RISCV_RPMI_INTERNAL_H + +#include "qapi/error.h" +#include "hw/misc/riscv_rpmi.h" +#include "librpmi.h" + +#define RPMI_PLAT_INFO "QEMU RISC-V RPMI" + +extern const struct rpmi_shmem_platform_ops rpmi_shmem_qemu_ops; +bool riscv_rpmi_service_enabled(RiscvRpmiState *s, + enum rpmi_servicegroup_id service_group); + +#endif diff --git a/include/hw/misc/riscv_rpmi.h b/include/hw/misc/riscv_rpmi.h new file mode 100644 index 0000000000..93d128f2e2 --- /dev/null +++ b/include/hw/misc/riscv_rpmi.h @@ -0,0 +1,95 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * RISC-V RPMI definitions shared by RPMI transport and FDT helpers. + * + * Copyright (c) 2026 Qualcomm Technologies, Inc. + * Author: + * Subrahmanya Lingappa + */ + +#ifndef HW_MISC_RISCV_RPMI_H +#define HW_MISC_RISCV_RPMI_H + +#include "exec/hwaddr.h" +#include "hw/core/sysbus.h" +#include "qom/object.h" +#include "qemu/notify.h" + +#ifdef CONFIG_LIBRPMI +#include "librpmi.h" +#else +enum rpmi_servicegroup_id { + RPMI_SRVGRP_SYSTEM_RESET =3D 0x0003, + RPMI_SRVGRP_SYSTEM_SUSPEND =3D 0x0004, + RPMI_SRVGRP_HSM =3D 0x0005, +}; +#endif + +#define RPMI_QUEUE_SLOT_SIZE 64 +#define RPMI_DBREG_SIZE 0x1000 + +#define RPMI_ALL_NUM_QUEUES 4 +#define RPMI_A2P_NUM_QUEUES 2 +#define RPMI_ALL_NUM_REGS (RPMI_ALL_NUM_QUEUES + 1) +#define RPMI_A2P_NUM_REGS (RPMI_A2P_NUM_QUEUES + 1) + +#define VIRT_RPMI_A2P_REQ_SIZE (16 * RPMI_QUEUE_SLOT_SIZE) +#define VIRT_RPMI_P2A_REQ_SIZE 0 + + +#define TYPE_RISCV_RPMI "riscv-rpmi" +OBJECT_DECLARE_SIMPLE_TYPE(RiscvRpmiState, RISCV_RPMI) + +struct rpmi_context; +struct rpmi_service_group; +struct rpmi_shmem; +struct rpmi_transport; + +typedef struct RiscvRpmiServiceConfig { + const char *node_name; + const char *compatible; + enum rpmi_servicegroup_id service_group; + bool has_mpxy_channel; + uint32_t mpxy_channel; +} RiscvRpmiServiceConfig; + +typedef struct RiscvRpmiConfig { + hwaddr doorbell_base; + hwaddr shmem_base; + hwaddr shmem_size; + uint32_t a2p_req_size; + uint32_t p2a_req_size; + const char *platform_info; + + const uint32_t *hart_ids; + uint32_t hart_count; + const RiscvRpmiServiceConfig *services; + uint32_t service_count; +} RiscvRpmiConfig; + +struct RiscvRpmiState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + MemoryRegion shmem; + uint64_t shmem_base; + uint64_t shmem_size; + uint32_t a2p_req_size; + uint32_t p2a_req_size; + char *platform_info; + + uint32_t *hart_ids; + uint32_t hart_count; + const RiscvRpmiServiceConfig *services; + uint32_t service_count; + uint32_t doorbell; + struct rpmi_shmem *rpmi_shmem; + struct rpmi_transport *transport; + struct rpmi_context *context; + bool has_shmem; +}; + +DeviceState *riscv_rpmi_create(const RiscvRpmiConfig *cfg, Error **errp); + +#endif From nobody Sat Sep 26 20:51:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1789622695; cv=none; d=zohomail.com; s=zohoarc; b=fOU1vDcXLHO2yL7f5z4KS6K4oeFXef9zfrfSNCCqqhpRoxNQijabULwdviGk4SmWmhUD5ei281DryH5h9apnqUilGXmAvW6MYTt8dc4+pz13+/lTBkrElpFtbPLkaG0Vdfl25/t6/aB0H8MRo5mfAShN0cf5qqFaimC033e5YwI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789622695; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=subrahmanya.lingappa@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789622697021158500 Content-Type: text/plain; charset="utf-8" Add helper routines for describing RPMI shared-memory mailbox transports and service child nodes in the RISC-V virt device tree. The helpers keep RPMI node construction in one place so the virt machine can add service groups without open-coding compatible strings, channel IDs, interrupts, and shared-memory references at each call site. Signed-off-by: Subrahmanya Lingappa Reviewed-by: Daniel Henrique Barboza --- hw/riscv/meson.build | 3 ++ hw/riscv/rpmi-fdt-stub.c | 16 ++++++ hw/riscv/rpmi-fdt.c | 103 ++++++++++++++++++++++++++++++++++++ include/hw/riscv/rpmi-fdt.h | 30 +++++++++++ 4 files changed, 152 insertions(+) create mode 100644 hw/riscv/rpmi-fdt-stub.c create mode 100644 hw/riscv/rpmi-fdt.c create mode 100644 include/hw/riscv/rpmi-fdt.h diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 0d82ceacc4..87601f8523 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -4,6 +4,9 @@ riscv_ss.add(files('boot.c')) riscv_ss.add(files('fdt-common.c')) riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) riscv_ss.add(files('riscv_hart.c')) +riscv_ss.add(when: 'CONFIG_RISCV_RPMI', + if_true: files('rpmi-fdt.c'), + if_false: files('rpmi-fdt-stub.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) diff --git a/hw/riscv/rpmi-fdt-stub.c b/hw/riscv/rpmi-fdt-stub.c new file mode 100644 index 0000000000..9866236ab3 --- /dev/null +++ b/hw/riscv/rpmi-fdt-stub.c @@ -0,0 +1,16 @@ +/* + * RISC-V RPMI device-tree helper stubs. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/riscv/rpmi-fdt.h" + +void riscv_rpmi_fdt_add_mbox(void *fdt G_GNUC_UNUSED, + const RiscvRpmiFdtMboxConfig *cfg G_GNUC_UNUS= ED, + uint32_t *phandle G_GNUC_UNUSED, + uint32_t *mbox_handle G_GNUC_UNUSED) +{ + g_assert_not_reached(); +} diff --git a/hw/riscv/rpmi-fdt.c b/hw/riscv/rpmi-fdt.c new file mode 100644 index 0000000000..439c91c894 --- /dev/null +++ b/hw/riscv/rpmi-fdt.c @@ -0,0 +1,103 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * RISC-V RPMI device-tree helpers + * + * Copyright (c) 2026 Qualcomm Technologies, Inc. + * Author: + * Subrahmanya Lingappa + */ + +#include "qemu/osdep.h" +#include "qemu/bswap.h" +#include "hw/riscv/rpmi-fdt.h" +#include "hw/misc/riscv_rpmi.h" +#include "system/device_tree.h" + +void riscv_rpmi_fdt_add_mbox(void *fdt, + const RiscvRpmiFdtMboxConfig *cfg, + uint32_t *phandle, + uint32_t *mbox_handle) +{ + g_autofree char *name =3D NULL; + hwaddr a2p_req_base, p2a_ack_base, p2a_req_base, a2p_ack_base; + static const char * const regnames_all[RPMI_ALL_NUM_REGS] =3D { + "a2p-req", "p2a-ack", "p2a-req", "a2p-ack", "a2p-doorbell" + }; + static const char * const regnames_a2p[RPMI_A2P_NUM_REGS] =3D { + "a2p-req", "p2a-ack", "a2p-doorbell" + }; + + a2p_req_base =3D cfg->shmem_base; + p2a_ack_base =3D a2p_req_base + cfg->a2p_req_size; + p2a_req_base =3D p2a_ack_base + cfg->a2p_req_size; + a2p_ack_base =3D p2a_req_base + cfg->p2a_req_size; + + *mbox_handle =3D (*phandle)++; + name =3D g_strdup_printf("/soc/mailbox@%" HWADDR_PRIx, cfg->shmem_base= ); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "riscv,rpmi-shmem-mbo= x"); + qemu_fdt_setprop_cell(fdt, name, "riscv,slot-size", RPMI_QUEUE_SLOT_SI= ZE); + qemu_fdt_setprop_cell(fdt, name, "#mbox-cells", 1); + + if (cfg->p2a_req_size) { + qemu_fdt_setprop_string_array(fdt, name, "reg-names", + (char **)®names_all, + ARRAY_SIZE(regnames_all)); + qemu_fdt_setprop_cells(fdt, name, "reg", + (uint32_t)(a2p_req_base >> 32), (uint32_t)a2p_req_base, + 0x0, cfg->a2p_req_size, + (uint32_t)(p2a_ack_base >> 32), (uint32_t)p2a_ack_base, + 0x0, cfg->a2p_req_size, + (uint32_t)(p2a_req_base >> 32), (uint32_t)p2a_req_base, + 0x0, cfg->p2a_req_size, + (uint32_t)(a2p_ack_base >> 32), (uint32_t)a2p_ack_base, + 0x0, cfg->p2a_req_size, + (uint32_t)(cfg->doorbell_base >> 32), (uint32_t)cfg->doorbell_= base, + 0x0, cfg->doorbell_size); + } else { + qemu_fdt_setprop_string_array(fdt, name, "reg-names", + (char **)®names_a2p, + ARRAY_SIZE(regnames_a2p)); + qemu_fdt_setprop_cells(fdt, name, "reg", + (uint32_t)(a2p_req_base >> 32), (uint32_t)a2p_req_base, + 0x0, cfg->a2p_req_size, + (uint32_t)(p2a_ack_base >> 32), (uint32_t)p2a_ack_base, + 0x0, cfg->a2p_req_size, + (uint32_t)(cfg->doorbell_base >> 32), (uint32_t)cfg->doorbell_= base, + 0x0, cfg->doorbell_size); + } + + qemu_fdt_setprop_cells(fdt, name, "phandle", *mbox_handle); +} + +void riscv_rpmi_fdt_add_service(void *fdt, hwaddr shmem_base, + const char *node_name, + const char *compatible, + uint32_t mbox_handle, + uint32_t service_group, + bool has_mpxy_channel, + uint32_t mpxy_channel) +{ + g_autofree char *name =3D g_strdup_printf("/soc/mailbox@%" HWADDR_PRIx= "/%s", + shmem_base, node_name); + + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", compatible); + qemu_fdt_setprop_cells(fdt, name, "mboxes", mbox_handle, service_group= ); + if (has_mpxy_channel) { + qemu_fdt_setprop_cell(fdt, name, "riscv,sbi-mpxy-channel-id", + mpxy_channel); + } +} + +void riscv_rpmi_fdt_add_service_node(void *fdt, hwaddr shmem_base, + const RiscvRpmiServiceConfig *service, + uint32_t mbox_handle) +{ + riscv_rpmi_fdt_add_service(fdt, shmem_base, service->node_name, + service->compatible, mbox_handle, + service->service_group, + service->has_mpxy_channel, + service->mpxy_channel); +} diff --git a/include/hw/riscv/rpmi-fdt.h b/include/hw/riscv/rpmi-fdt.h new file mode 100644 index 0000000000..b157bda1d1 --- /dev/null +++ b/include/hw/riscv/rpmi-fdt.h @@ -0,0 +1,30 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * RISC-V RPMI device-tree helpers + * + * Copyright (c) 2026 Qualcomm Technologies, Inc. + * Author: + * Subrahmanya Lingappa + */ + +#ifndef HW_RISCV_RPMI_FDT_H +#define HW_RISCV_RPMI_FDT_H + +#include "exec/hwaddr.h" +#include "hw/misc/riscv_rpmi.h" + +typedef struct RiscvRpmiFdtMboxConfig { + hwaddr shmem_base; + hwaddr doorbell_base; + uint32_t a2p_req_size; + uint32_t p2a_req_size; + uint32_t doorbell_size; +} RiscvRpmiFdtMboxConfig; + +void riscv_rpmi_fdt_add_mbox(void *fdt, + const RiscvRpmiFdtMboxConfig *cfg, + uint32_t *phandle, + uint32_t *mbox_handle); + +#endif From nobody Sat Sep 26 20:51:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1789622711; cv=none; d=zohomail.com; s=zohoarc; b=fih17mw0ngefDTMTxZ4vdHEm634eWp/zvFVxIoiZwizFCSofAB8RqDun0I7vk45JEW9GzpiYCrQql82eJ/WvpBHQ8bqbtU99a1sGm4u8885jbZMBvt8AW2xpBcCbpm7otGDIxVMe6kaGdNKKUYzBiUiRmHxT+7lwJbMHk98ELJE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789622711; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=subrahmanya.lingappa@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789622713113158500 Content-Type: text/plain; charset="utf-8" Add the virt machine rpmi=3Don/off option and wire the initial RPMI Base transport into machine realization. The option remains disabled by default and requires TCG plus librpmi. Invalid accelerator/build combinations fail during machine initialization. When enabled, virt allocates the RPMI shared-memory transport, creates the RPMI device, configures Base service metadata, and emits the corresponding device-tree nodes for firmware discovery. Signed-off-by: Subrahmanya Lingappa --- hw/riscv/Kconfig | 1 + hw/riscv/virt.c | 96 +++++++++++++++++++++++++++++++++++++++++ include/hw/riscv/virt.h | 3 ++ 3 files changed, 100 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index d06ac26648..c3f9d7580b 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -49,6 +49,7 @@ config RISCV_VIRT imply VIRTIO_VGA imply TEST_DEVICES imply TPM_TIS_SYSBUS + imply RISCV_RPMI select DEVICE_TREE select RISCV_NUMA select GOLDFISH_RTC diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d58656f70d..c822cc15ca 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -44,6 +44,8 @@ #include "hw/intc/riscv_aplic.h" #include "hw/intc/sifive_plic.h" #include "hw/misc/sifive_test.h" +#include "hw/misc/riscv_rpmi.h" +#include "hw/riscv/rpmi-fdt.h" #include "hw/core/platform-bus.h" #include "chardev/char.h" #include "system/device_tree.h" @@ -100,6 +102,8 @@ static const MemMapEntry virt_memmap[] =3D { /* UART1 supports page isolation from UART0 */ [VIRT_UART1] =3D { 0x1000a000, 0x100 }, [VIRT_FW_CFG] =3D { 0x10100000, 0x18 }, + [VIRT_RPMI_SHMEM] =3D { 0x10200000, 0x20000 }, + [VIRT_RPMI_DOORBELL] =3D { 0x10230000, 0x1000 }, [VIRT_FLASH] =3D { 0x20000000, 0x4000000 }, [VIRT_IMSIC_M] =3D { 0x24000000, VIRT_IMSIC_MAX_SIZE }, [VIRT_IMSIC_S] =3D { 0x28000000, VIRT_IMSIC_MAX_SIZE }, @@ -988,6 +992,40 @@ static void create_fdt_iommu(RISCVVirtState *s, uint16= _t bdf) s->pci_iommu_bdf =3D bdf; } =20 + +static RiscvRpmiConfig virt_rpmi_config(RISCVVirtState *s, + const uint32_t *hart_ids, + uint32_t hart_count) +{ + return (RiscvRpmiConfig) { + .doorbell_base =3D s->memmap[VIRT_RPMI_DOORBELL].base, + .shmem_base =3D s->memmap[VIRT_RPMI_SHMEM].base, + .shmem_size =3D s->memmap[VIRT_RPMI_SHMEM].size, + .a2p_req_size =3D VIRT_RPMI_A2P_REQ_SIZE, + .p2a_req_size =3D VIRT_RPMI_P2A_REQ_SIZE, + .platform_info =3D "QEMU RISC-V virt RPMI", + .hart_ids =3D hart_ids, + .hart_count =3D hart_count, + }; +} + +static void create_fdt_rpmi(RISCVVirtState *s, uint32_t *phandle, + uint32_t msi_phandle) +{ + RiscvRpmiConfig rpmi_cfg =3D virt_rpmi_config(s, NULL, 0); + uint32_t rpmi_mbox_handle; + RiscvRpmiFdtMboxConfig cfg =3D { + .shmem_base =3D rpmi_cfg.shmem_base, + .doorbell_base =3D rpmi_cfg.doorbell_base, + .a2p_req_size =3D rpmi_cfg.a2p_req_size, + .p2a_req_size =3D rpmi_cfg.p2a_req_size, + .doorbell_size =3D s->memmap[VIRT_RPMI_DOORBELL].size, + }; + + riscv_rpmi_fdt_add_mbox(MACHINE(s)->fdt, &cfg, phandle, + &rpmi_mbox_handle); +} + static void finalize_fdt(RISCVVirtState *s) { uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; @@ -1007,6 +1045,10 @@ static void finalize_fdt(RISCVVirtState *s) create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle, iommu_sys_phandle); =20 + if (s->have_rpmi) { + create_fdt_rpmi(s, &phandle, msi_pcie_phandle); + } + create_fdt_reset(s, &phandle); =20 create_fdt_uarts(s, irq_mmio_phandle); @@ -1334,6 +1376,18 @@ static void virt_machine_init(MachineState *machine) exit(1); } =20 + + if (s->have_rpmi) { +#ifndef CONFIG_LIBRPMI + error_report("RISC-V RPMI support is not compiled in"); + exit(1); +#else + if (kvm_enabled()) { + error_report("RISC-V RPMI support is not available with KVM"); + exit(1); + } +#endif + } /* Initialize sockets */ mmio_irqchip =3D virtio_irqchip =3D pcie_irqchip =3D NULL; for (i =3D 0; i < socket_count; i++) { @@ -1484,6 +1538,25 @@ static void virt_machine_init(MachineState *machine) /* SiFive Test MMIO device */ sifive_test_create(s->memmap[VIRT_TEST].base); =20 + if (s->have_rpmi) { + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + const CPUArchIdList *possible_cpus =3D mc->possible_cpu_arch_ids(m= achine); + g_autofree uint32_t *rpmi_hart_ids =3D + g_new0(uint32_t, machine->smp.cpus); + RiscvRpmiConfig rpmi_cfg; + Error *local_err =3D NULL; + + for (i =3D 0; i < machine->smp.cpus; i++) { + rpmi_hart_ids[i] =3D possible_cpus->cpus[i].arch_id; + } + + rpmi_cfg =3D virt_rpmi_config(s, rpmi_hart_ids, machine->smp.cpus); + if (!riscv_rpmi_create(&rpmi_cfg, &local_err)) { + error_report_err(local_err); + exit(1); + } + } + /* VirtIO MMIO devices */ for (i =3D 0; i < VIRTIO_COUNT; i++) { sysbus_create_simple("virtio-mmio", @@ -1575,6 +1648,7 @@ static void virt_machine_instance_init(Object *obj) =20 s->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); s->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); + s->have_rpmi =3D false; s->acpi =3D ON_OFF_AUTO_AUTO; s->iommu_sys =3D ON_OFF_AUTO_AUTO; s->num_sources =3D VIRT_IRQCHIP_NUM_SOURCES; @@ -1650,6 +1724,21 @@ static void virt_set_aclint(Object *obj, bool value,= Error **errp) s->have_aclint =3D value; } =20 + +static bool virt_get_rpmi(Object *obj, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + return s->have_rpmi; +} + +static void virt_set_rpmi(Object *obj, bool value, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + s->have_rpmi =3D value; +} + bool virt_is_iommu_sys_enabled(RISCVVirtState *s) { return s->iommu_sys =3D=3D ON_OFF_AUTO_ON; @@ -1771,6 +1860,13 @@ static void virt_machine_class_init(ObjectClass *oc,= const void *data) "enable/disable emulating " "ACLINT devices"); =20 + + object_class_property_add_bool(oc, "rpmi", virt_get_rpmi, + virt_set_rpmi); + object_class_property_set_description(oc, "rpmi", + "Set on/off to enable/disable " + "RISC-V RPMI devices"); + object_class_property_add_str(oc, "aia", virt_get_aia, virt_set_aia); object_class_property_set_description(oc, "aia", diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 7c862b0da2..76b5a57001 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -55,6 +55,7 @@ struct RISCVVirtState { =20 int fdt_size; bool have_aclint; + bool have_rpmi; RISCVVirtAIAType aia_type; int aia_guests; char *oem_id; @@ -82,6 +83,8 @@ enum { VIRT_VIRTIO, VIRT_UART1, VIRT_FW_CFG, + VIRT_RPMI_SHMEM, + VIRT_RPMI_DOORBELL, VIRT_IMSIC_M, VIRT_IMSIC_S, VIRT_FLASH, From nobody Sat Sep 26 20:51:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1789622716; cv=none; d=zohomail.com; s=zohoarc; b=R5F9zLQTTvPmRxJeXDlKkxCRx3ypbQjkV3+aCaUnbwXUJqrApplWESdu/4f8BYvskbG2nimhgHibAvDQ/r50DLFNemAWxZZIbB84s6TK1iyZKHwz1SR9h3pL2zWhrCmAet8cqFVkX3z2vKYEn36qVcC1kQiCBrBBihQgAZ0yHYw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789622716; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=subrahmanya.lingappa@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789622717241158500 Content-Type: text/plain; charset="utf-8" Add a QEMU implementation of the RPMI System Reset service group. The service advertises shutdown and cold reboot reset types, validates guest requests, and dispatches accepted requests through the machine reset and shutdown callbacks. This lets firmware use RPMI reset commands while keeping the board-specific reset policy in the RISC-V virt machine. Signed-off-by: Subrahmanya Lingappa Reviewed-by: Daniel Henrique Barboza --- hw/misc/meson.build | 1 + hw/misc/riscv_rpmi.c | 68 ++++++++++- hw/misc/riscv_rpmi_internal.h | 9 ++ hw/misc/riscv_rpmi_sysreset.c | 206 ++++++++++++++++++++++++++++++++++ hw/riscv/rpmi-fdt-stub.c | 22 ++++ hw/riscv/rpmi-fdt.c | 2 +- hw/riscv/virt.c | 51 ++++++++- include/hw/misc/riscv_rpmi.h | 11 +- include/hw/riscv/rpmi-fdt.h | 11 ++ 9 files changed, 371 insertions(+), 10 deletions(-) create mode 100644 hw/misc/riscv_rpmi_sysreset.c diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 1b8220c6be..25916c93ed 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -178,4 +178,5 @@ system_ss.add(when: 'CONFIG_LASI', if_true: files('lasi= .c')) system_ss.add(when: 'CONFIG_AXIADO_CLK', if_true: files('axiado_clk.c')) system_ss.add(when: 'CONFIG_RISCV_RPMI', if_true: [files( 'riscv_rpmi.c', + 'riscv_rpmi_sysreset.c', ), librpmi], if_false: files('riscv_rpmi-stub.c')) diff --git a/hw/misc/riscv_rpmi.c b/hw/misc/riscv_rpmi.c index c73408714a..7d55215fa0 100644 --- a/hw/misc/riscv_rpmi.c +++ b/hw/misc/riscv_rpmi.c @@ -200,10 +200,37 @@ static bool riscv_rpmi_transport_indices_valid(RiscvR= pmiState *s) s->a2p_req_size); } =20 +typedef struct RiscvRpmiServiceOps { + enum rpmi_servicegroup_id service_group; + bool (*add)(RiscvRpmiState *s, Error **errp); + void (*remove)(RiscvRpmiState *s); +} RiscvRpmiServiceOps; + +static const RiscvRpmiServiceOps riscv_rpmi_service_ops[] =3D { + { + .service_group =3D RPMI_SRVGRP_SYSTEM_RESET, + .add =3D riscv_rpmi_sysreset_add, + .remove =3D riscv_rpmi_sysreset_remove, + }, +}; + +static const RiscvRpmiServiceOps *riscv_rpmi_service_ops_by_group( + enum rpmi_servicegroup_id service_group) +{ + for (uint32_t i =3D 0; i < ARRAY_SIZE(riscv_rpmi_service_ops); i++) { + if (riscv_rpmi_service_ops[i].service_group =3D=3D service_group) { + return &riscv_rpmi_service_ops[i]; + } + } + + return NULL; +} + static void riscv_rpmi_configure_base(RiscvRpmiState *s, const RiscvRpmiConfig *cfg) { s->platform_info =3D g_strdup(cfg->platform_info); + s->machine_ops =3D cfg->machine_ops; s->services =3D cfg->services; s->service_count =3D cfg->service_count; =20 @@ -240,7 +267,9 @@ static void riscv_rpmi_reset_hold(Object *obj, ResetTyp= e type) =20 static void riscv_rpmi_cleanup(RiscvRpmiState *s) { - + for (uint32_t i =3D ARRAY_SIZE(riscv_rpmi_service_ops); i > 0; i--) { + riscv_rpmi_service_ops[i - 1].remove(s); + } =20 if (s->context) { rpmi_context_destroy(s->context); @@ -277,6 +306,30 @@ bool riscv_rpmi_service_enabled(RiscvRpmiState *s, return false; } =20 +bool riscv_rpmi_context_add_group(RiscvRpmiState *s, + struct rpmi_service_group *group, + const char *name, + Error **errp) +{ + enum rpmi_error rc; + + rc =3D rpmi_context_add_group(s->context, group); + if (rc !=3D RPMI_SUCCESS) { + error_setg(errp, "failed to add RPMI %s service group: %d", name, = rc); + return false; + } + + return true; +} + +void riscv_rpmi_context_remove_group(RiscvRpmiState *s, + struct rpmi_service_group *group) +{ + if (s->context && group) { + rpmi_context_remove_group(s->context, group); + } +} + static bool riscv_rpmi_validate_config(RiscvRpmiState *s, Error **errp) { uint64_t queue_bytes; @@ -348,9 +401,16 @@ static bool riscv_rpmi_add_service_group(RiscvRpmiStat= e *s, const RiscvRpmiServiceConfig *ser= vice, Error **errp) { - error_setg(errp, "unsupported RPMI service group %u", - service->service_group); - return false; + const RiscvRpmiServiceOps *ops; + + ops =3D riscv_rpmi_service_ops_by_group(service->service_group); + if (!ops) { + error_setg(errp, "unsupported RPMI service group %u", + service->service_group); + return false; + } + + return ops->add(s, errp); } =20 static bool riscv_rpmi_init_services(RiscvRpmiState *s, Error **errp) diff --git a/hw/misc/riscv_rpmi_internal.h b/hw/misc/riscv_rpmi_internal.h index c0cb1b64e6..1d7445b2d1 100644 --- a/hw/misc/riscv_rpmi_internal.h +++ b/hw/misc/riscv_rpmi_internal.h @@ -20,5 +20,14 @@ extern const struct rpmi_shmem_platform_ops rpmi_shmem_qemu_ops; bool riscv_rpmi_service_enabled(RiscvRpmiState *s, enum rpmi_servicegroup_id service_group); +bool riscv_rpmi_context_add_group(RiscvRpmiState *s, + struct rpmi_service_group *group, + const char *name, + Error **errp); +void riscv_rpmi_context_remove_group(RiscvRpmiState *s, + struct rpmi_service_group *group); + +bool riscv_rpmi_sysreset_add(RiscvRpmiState *s, Error **errp); +void riscv_rpmi_sysreset_remove(RiscvRpmiState *s); =20 #endif diff --git a/hw/misc/riscv_rpmi_sysreset.c b/hw/misc/riscv_rpmi_sysreset.c new file mode 100644 index 0000000000..775eb5483f --- /dev/null +++ b/hw/misc/riscv_rpmi_sysreset.c @@ -0,0 +1,206 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * RISC-V RPMI System Reset service. + * + * Copyright (c) 2026 Qualcomm Technologies, Inc. + * Author: + * Subrahmanya Lingappa + */ + +#include "qemu/osdep.h" +#include "riscv_rpmi_internal.h" +#include "qemu/log.h" +#include "librpmi_env.h" + +typedef struct RiscvRpmiSysresetType { + uint32_t type; + void (*action)(RiscvRpmiState *s); +} RiscvRpmiSysresetType; + +typedef struct RiscvRpmiSysresetGroup { + struct rpmi_service_group group; + struct rpmi_service services[RPMI_SYSRST_SRV_ID_MAX]; + RiscvRpmiState *rpmi; +} RiscvRpmiSysresetGroup; + +static void riscv_rpmi_sysreset_reboot(RiscvRpmiState *s) +{ + const RiscvRpmiMachineOps *ops =3D s->machine_ops; + + if (ops && ops->system_reset) { + ops->system_reset(); + } +} + +static void riscv_rpmi_sysreset_shutdown(RiscvRpmiState *s) +{ + const RiscvRpmiMachineOps *ops =3D s->machine_ops; + + if (ops && ops->system_shutdown) { + ops->system_shutdown(); + } +} + +static const RiscvRpmiSysresetType riscv_rpmi_sysreset_types[] =3D { + { + .type =3D RPMI_SYSRST_TYPE_SHUTDOWN, + .action =3D riscv_rpmi_sysreset_shutdown, + }, { + .type =3D RPMI_SYSRST_TYPE_COLD_REBOOT, + .action =3D riscv_rpmi_sysreset_reboot, + }, +}; + +static const RiscvRpmiSysresetType *riscv_rpmi_sysreset_type_by_id( + uint32_t reset_type) +{ + for (uint32_t index =3D 0; index < ARRAY_SIZE(riscv_rpmi_sysreset_type= s); + index++) { + if (riscv_rpmi_sysreset_types[index].type =3D=3D reset_type) { + return &riscv_rpmi_sysreset_types[index]; + } + } + + return NULL; +} + +static void riscv_rpmi_do_system_reset(RiscvRpmiState *s, + rpmi_uint32_t reset_type) +{ + const RiscvRpmiSysresetType *type; + + type =3D riscv_rpmi_sysreset_type_by_id(reset_type); + if (type) { + type->action(s); + return; + } + + qemu_log_mask(LOG_GUEST_ERROR, "%s: unsupported reset type %u\n", + __func__, reset_type); +} + +static enum rpmi_error riscv_rpmi_sysreset_get_attributes( + struct rpmi_service_group *group, struct rpmi_service *service, + struct rpmi_transport *trans, rpmi_uint16_t request_data_len, + const rpmi_uint8_t *request_data, rpmi_uint16_t *response_data_len, + rpmi_uint8_t *response_data) +{ + uint32_t reset_type =3D ldl_le_p(request_data); + uint32_t *resp =3D (uint32_t *)response_data; + + *response_data_len =3D 2 * sizeof(*resp); + stl_le_p(&resp[0], RPMI_SUCCESS); + stl_le_p(&resp[1], riscv_rpmi_sysreset_type_by_id(reset_type) ? + RPMI_SYSRST_ATTRS_FLAGS_RESETTYPE : 0); + + return RPMI_SUCCESS; +} + +static enum rpmi_error riscv_rpmi_sysreset_do_reset( + struct rpmi_service_group *group, struct rpmi_service *service, + struct rpmi_transport *trans, rpmi_uint16_t request_data_len, + const rpmi_uint8_t *request_data, rpmi_uint16_t *response_data_len, + rpmi_uint8_t *response_data) +{ + RiscvRpmiSysresetGroup *sysreset =3D group->priv; + uint32_t reset_type =3D ldl_le_p(request_data); + uint32_t *resp =3D (uint32_t *)response_data; + + *response_data_len =3D sizeof(*resp); + + if (!riscv_rpmi_sysreset_type_by_id(reset_type)) { + stl_le_p(resp, (uint32_t)RPMI_ERR_INVALID_PARAM); + return RPMI_SUCCESS; + } + + stl_le_p(resp, RPMI_SUCCESS); + riscv_rpmi_do_system_reset(sysreset->rpmi, reset_type); + return RPMI_SUCCESS; +} + +static const struct rpmi_service riscv_rpmi_sysreset_services[] =3D { + [RPMI_SYSRST_SRV_ENABLE_NOTIFICATION] =3D { + .service_id =3D RPMI_SYSRST_SRV_ENABLE_NOTIFICATION, + .min_a2p_request_datalen =3D 8, + }, + [RPMI_SYSRST_SRV_GET_ATTRIBUTES] =3D { + .service_id =3D RPMI_SYSRST_SRV_GET_ATTRIBUTES, + .min_a2p_request_datalen =3D 4, + .process_a2p_request =3D riscv_rpmi_sysreset_get_attributes, + }, + [RPMI_SYSRST_SRV_SYSTEM_RESET] =3D { + .service_id =3D RPMI_SYSRST_SRV_SYSTEM_RESET, + .min_a2p_request_datalen =3D 4, + .process_a2p_request =3D riscv_rpmi_sysreset_do_reset, + }, +}; + +static struct rpmi_service_group *riscv_rpmi_sysreset_create(RiscvRpmiStat= e *s) +{ + RiscvRpmiSysresetGroup *sysreset; + struct rpmi_service_group *group; + + sysreset =3D g_new0(RiscvRpmiSysresetGroup, 1); + sysreset->rpmi =3D s; + memcpy(sysreset->services, riscv_rpmi_sysreset_services, + sizeof(riscv_rpmi_sysreset_services)); + + group =3D &sysreset->group; + group->name =3D "sysreset"; + group->servicegroup_id =3D RPMI_SRVGRP_SYSTEM_RESET; + group->max_service_id =3D RPMI_SYSRST_SRV_ID_MAX; + group->servicegroup_version =3D + RPMI_BASE_VERSION(RPMI_SPEC_VERSION_MAJOR, RPMI_SPEC_VERSION_MINOR= ); + group->privilege_level_bitmap =3D RPMI_PRIVILEGE_M_MODE_MASK; + group->services =3D sysreset->services; + group->lock =3D rpmi_env_alloc_lock(); + group->priv =3D sysreset; + + return group; +} + +static void riscv_rpmi_sysreset_destroy(struct rpmi_service_group *group) +{ + if (!group) { + return; + } + + rpmi_env_free_lock(group->lock); + g_free(group->priv); +} + +bool riscv_rpmi_sysreset_add(RiscvRpmiState *s, Error **errp) +{ + struct rpmi_service_group *group; + + if (s->sysreset_group) { + error_setg(errp, "duplicate RPMI sysreset service descriptor"); + return false; + } + + group =3D riscv_rpmi_sysreset_create(s); + if (!group) { + error_setg(errp, "failed to create RPMI sysreset service group"); + return false; + } + + if (!riscv_rpmi_context_add_group(s, group, "sysreset", errp)) { + riscv_rpmi_sysreset_destroy(group); + return false; + } + + s->sysreset_group =3D group; + return true; +} + +void riscv_rpmi_sysreset_remove(RiscvRpmiState *s) +{ + if (!s->sysreset_group) { + return; + } + + riscv_rpmi_context_remove_group(s, s->sysreset_group); + riscv_rpmi_sysreset_destroy(s->sysreset_group); + s->sysreset_group =3D NULL; +} diff --git a/hw/riscv/rpmi-fdt-stub.c b/hw/riscv/rpmi-fdt-stub.c index 9866236ab3..439a053c62 100644 --- a/hw/riscv/rpmi-fdt-stub.c +++ b/hw/riscv/rpmi-fdt-stub.c @@ -14,3 +14,25 @@ void riscv_rpmi_fdt_add_mbox(void *fdt G_GNUC_UNUSED, { g_assert_not_reached(); } + +void riscv_rpmi_fdt_add_service(void *fdt G_GNUC_UNUSED, + hwaddr shmem_base G_GNUC_UNUSED, + const char *node_name G_GNUC_UNUSED, + const char *compatible G_GNUC_UNUSED, + uint32_t mbox_handle G_GNUC_UNUSED, + enum rpmi_servicegroup_id service_group + G_GNUC_UNUSED, + bool has_mpxy_channel G_GNUC_UNUSED, + uint32_t mpxy_channel G_GNUC_UNUSED) +{ + g_assert_not_reached(); +} + +void riscv_rpmi_fdt_add_service_node(void *fdt G_GNUC_UNUSED, + hwaddr shmem_base G_GNUC_UNUSED, + const RiscvRpmiServiceConfig *service + G_GNUC_UNUSED, + uint32_t mbox_handle G_GNUC_UNUSED) +{ + g_assert_not_reached(); +} diff --git a/hw/riscv/rpmi-fdt.c b/hw/riscv/rpmi-fdt.c index 439c91c894..506be5d43b 100644 --- a/hw/riscv/rpmi-fdt.c +++ b/hw/riscv/rpmi-fdt.c @@ -75,7 +75,7 @@ void riscv_rpmi_fdt_add_service(void *fdt, hwaddr shmem_b= ase, const char *node_name, const char *compatible, uint32_t mbox_handle, - uint32_t service_group, + enum rpmi_servicegroup_id service_group, bool has_mpxy_channel, uint32_t mpxy_channel) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c822cc15ca..7a97dfcf89 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -770,7 +770,8 @@ static void create_fdt_pcie(RISCVVirtState *s, create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); } =20 -static void create_fdt_reset(RISCVVirtState *s, uint32_t *phandle) +static void create_fdt_reset(RISCVVirtState *s, uint32_t *phandle, + bool use_syscon_reset) { char *name; uint32_t test_phandle; @@ -794,6 +795,14 @@ static void create_fdt_reset(RISCVVirtState *s, uint32= _t *phandle) test_phandle =3D qemu_fdt_get_phandle(ms->fdt, name); g_free(name); =20 + /* + * When RPMI is enabled, advertise reset and shutdown through RPMI so + * firmware routes these operations through the RPMI system reset serv= ice. + */ + if (!use_syscon_reset) { + return; + } + name =3D g_strdup_printf("/reboot"); qemu_fdt_add_subnode(ms->fdt, name); qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); @@ -993,6 +1002,34 @@ static void create_fdt_iommu(RISCVVirtState *s, uint1= 6_t bdf) } =20 =20 +static const RiscvRpmiServiceConfig virt_rpmi_services[] =3D { + { + .node_name =3D "sysreset", + .compatible =3D "riscv,rpmi-system-reset", + .service_group =3D RPMI_SRVGRP_SYSTEM_RESET, + }, +}; + +static uint32_t virt_rpmi_service_count(RISCVVirtState *s) +{ + return ARRAY_SIZE(virt_rpmi_services); +} + +static void virt_rpmi_system_reset(void) +{ + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); +} + +static void virt_rpmi_system_shutdown(void) +{ + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); +} + +static const RiscvRpmiMachineOps virt_rpmi_machine_ops =3D { + .system_reset =3D virt_rpmi_system_reset, + .system_shutdown =3D virt_rpmi_system_shutdown, +}; + static RiscvRpmiConfig virt_rpmi_config(RISCVVirtState *s, const uint32_t *hart_ids, uint32_t hart_count) @@ -1004,8 +1041,11 @@ static RiscvRpmiConfig virt_rpmi_config(RISCVVirtSta= te *s, .a2p_req_size =3D VIRT_RPMI_A2P_REQ_SIZE, .p2a_req_size =3D VIRT_RPMI_P2A_REQ_SIZE, .platform_info =3D "QEMU RISC-V virt RPMI", + .machine_ops =3D &virt_rpmi_machine_ops, .hart_ids =3D hart_ids, .hart_count =3D hart_count, + .services =3D virt_rpmi_services, + .service_count =3D virt_rpmi_service_count(s), }; } =20 @@ -1014,6 +1054,7 @@ static void create_fdt_rpmi(RISCVVirtState *s, uint32= _t *phandle, { RiscvRpmiConfig rpmi_cfg =3D virt_rpmi_config(s, NULL, 0); uint32_t rpmi_mbox_handle; + uint32_t i; RiscvRpmiFdtMboxConfig cfg =3D { .shmem_base =3D rpmi_cfg.shmem_base, .doorbell_base =3D rpmi_cfg.doorbell_base, @@ -1024,6 +1065,12 @@ static void create_fdt_rpmi(RISCVVirtState *s, uint3= 2_t *phandle, =20 riscv_rpmi_fdt_add_mbox(MACHINE(s)->fdt, &cfg, phandle, &rpmi_mbox_handle); + + for (i =3D 0; i < rpmi_cfg.service_count; i++) { + riscv_rpmi_fdt_add_service_node(MACHINE(s)->fdt, rpmi_cfg.shmem_ba= se, + &rpmi_cfg.services[i], + rpmi_mbox_handle); + } } =20 static void finalize_fdt(RISCVVirtState *s) @@ -1049,7 +1096,7 @@ static void finalize_fdt(RISCVVirtState *s) create_fdt_rpmi(s, &phandle, msi_pcie_phandle); } =20 - create_fdt_reset(s, &phandle); + create_fdt_reset(s, &phandle, !s->have_rpmi); =20 create_fdt_uarts(s, irq_mmio_phandle); =20 diff --git a/include/hw/misc/riscv_rpmi.h b/include/hw/misc/riscv_rpmi.h index 93d128f2e2..1500ff1b8b 100644 --- a/include/hw/misc/riscv_rpmi.h +++ b/include/hw/misc/riscv_rpmi.h @@ -37,7 +37,6 @@ enum rpmi_servicegroup_id { #define VIRT_RPMI_A2P_REQ_SIZE (16 * RPMI_QUEUE_SLOT_SIZE) #define VIRT_RPMI_P2A_REQ_SIZE 0 =20 - #define TYPE_RISCV_RPMI "riscv-rpmi" OBJECT_DECLARE_SIMPLE_TYPE(RiscvRpmiState, RISCV_RPMI) =20 @@ -46,6 +45,11 @@ struct rpmi_service_group; struct rpmi_shmem; struct rpmi_transport; =20 +typedef struct RiscvRpmiMachineOps { + void (*system_reset)(void); + void (*system_shutdown)(void); +} RiscvRpmiMachineOps; + typedef struct RiscvRpmiServiceConfig { const char *node_name; const char *compatible; @@ -61,7 +65,7 @@ typedef struct RiscvRpmiConfig { uint32_t a2p_req_size; uint32_t p2a_req_size; const char *platform_info; - + const RiscvRpmiMachineOps *machine_ops; const uint32_t *hart_ids; uint32_t hart_count; const RiscvRpmiServiceConfig *services; @@ -78,7 +82,8 @@ struct RiscvRpmiState { uint32_t a2p_req_size; uint32_t p2a_req_size; char *platform_info; - + const RiscvRpmiMachineOps *machine_ops; + struct rpmi_service_group *sysreset_group; uint32_t *hart_ids; uint32_t hart_count; const RiscvRpmiServiceConfig *services; diff --git a/include/hw/riscv/rpmi-fdt.h b/include/hw/riscv/rpmi-fdt.h index b157bda1d1..d96c9c37e4 100644 --- a/include/hw/riscv/rpmi-fdt.h +++ b/include/hw/riscv/rpmi-fdt.h @@ -26,5 +26,16 @@ void riscv_rpmi_fdt_add_mbox(void *fdt, const RiscvRpmiFdtMboxConfig *cfg, uint32_t *phandle, uint32_t *mbox_handle); +void riscv_rpmi_fdt_add_service(void *fdt, hwaddr shmem_base, + const char *node_name, + const char *compatible, + uint32_t mbox_handle, + enum rpmi_servicegroup_id service_group, + bool has_mpxy_channel, + uint32_t mpxy_channel); + +void riscv_rpmi_fdt_add_service_node(void *fdt, hwaddr shmem_base, + const RiscvRpmiServiceConfig *service, + uint32_t mbox_handle); =20 #endif From nobody Sat Sep 26 20:51:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1789622651; cv=none; d=zohomail.com; s=zohoarc; b=WM6DJc9oIXtNl57dtCc1K1LAUAJAauP9BUq1+s3LJKW13Usu+aajGCRHdcYO3jRk6UePR0U+35VZvvyCSS34A2b34/62FYU1z4NHAR7lMJNiC43R37mJFlQ32TYxG3G1hDAUEdK2DY99Kf5UMsOTJdSYfG/XrDCFfaoFENAeXaA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789622651; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=subrahmanya.lingappa@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789622653405158500 Content-Type: text/plain; charset="utf-8" Add the RPMI Hart State Management service group for RISC-V virt. The service exposes the configured virt hart IDs to librpmi and keeps per-hart RPMI hardware state in the RPMI device. Start, stop, and suspend requests update QEMU CPU halted state and resume/kick vCPUs as needed so firmware can exercise RPMI HSM operations against the emulated topology. Signed-off-by: Subrahmanya Lingappa Reviewed-by: Daniel Henrique Barboza --- hw/misc/meson.build | 1 + hw/misc/riscv_rpmi.c | 5 + hw/misc/riscv_rpmi_hsm.c | 281 ++++++++++++++++++++++++++++++++++ hw/misc/riscv_rpmi_internal.h | 4 + hw/riscv/virt.c | 5 + include/hw/misc/riscv_rpmi.h | 4 + 6 files changed, 300 insertions(+) create mode 100644 hw/misc/riscv_rpmi_hsm.c diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 25916c93ed..3f2caaf06f 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -179,4 +179,5 @@ system_ss.add(when: 'CONFIG_AXIADO_CLK', if_true: files= ('axiado_clk.c')) system_ss.add(when: 'CONFIG_RISCV_RPMI', if_true: [files( 'riscv_rpmi.c', 'riscv_rpmi_sysreset.c', + 'riscv_rpmi_hsm.c', ), librpmi], if_false: files('riscv_rpmi-stub.c')) diff --git a/hw/misc/riscv_rpmi.c b/hw/misc/riscv_rpmi.c index 7d55215fa0..b3b9a202a5 100644 --- a/hw/misc/riscv_rpmi.c +++ b/hw/misc/riscv_rpmi.c @@ -211,6 +211,10 @@ static const RiscvRpmiServiceOps riscv_rpmi_service_op= s[] =3D { .service_group =3D RPMI_SRVGRP_SYSTEM_RESET, .add =3D riscv_rpmi_sysreset_add, .remove =3D riscv_rpmi_sysreset_remove, + }, { + .service_group =3D RPMI_SRVGRP_HSM, + .add =3D riscv_rpmi_hsm_add, + .remove =3D riscv_rpmi_hsm_remove, }, }; =20 @@ -263,6 +267,7 @@ static void riscv_rpmi_reset_hold(Object *obj, ResetTyp= e type) memory_region_set_dirty(&s->shmem, 0, s->shmem_size); } =20 + riscv_rpmi_hsm_reset(s); } =20 static void riscv_rpmi_cleanup(RiscvRpmiState *s) diff --git a/hw/misc/riscv_rpmi_hsm.c b/hw/misc/riscv_rpmi_hsm.c new file mode 100644 index 0000000000..08a985cb30 --- /dev/null +++ b/hw/misc/riscv_rpmi_hsm.c @@ -0,0 +1,281 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * RISC-V RPMI HSM service. + * + * Copyright (c) 2026 Qualcomm Technologies, Inc. + * Author: + * Subrahmanya Lingappa + */ + +#include "qemu/osdep.h" +#include "riscv_rpmi_internal.h" +#include "hw/core/cpu.h" +#include "librpmi_env.h" + +static const struct rpmi_hsm_suspend_type riscv_rpmi_hsm_suspend_types[] = =3D { + { + .type =3D 0, + .info =3D { + .flags =3D 0, + .entry_latency_us =3D 0, + .exit_latency_us =3D 0, + .wakeup_latency_us =3D 0, + .min_residency_us =3D 0, + }, + }, +}; + +typedef struct RiscvRpmiHsmStateTransition { + enum rpmi_hart_hw_state state; + bool halted; + bool resume; +} RiscvRpmiHsmStateTransition; + +static const RiscvRpmiHsmStateTransition riscv_rpmi_hsm_state_transitions[= ] =3D { + { + .state =3D RPMI_HART_HW_STATE_STARTED, + .halted =3D false, + .resume =3D true, + }, { + .state =3D RPMI_HART_HW_STATE_STOPPED, + .halted =3D true, + .resume =3D false, + }, { + .state =3D RPMI_HART_HW_STATE_SUSPENDED, + .halted =3D true, + .resume =3D false, + }, +}; + +static const RiscvRpmiHsmStateTransition *riscv_rpmi_hsm_state_transition( + enum rpmi_hart_hw_state state) +{ + for (uint32_t index =3D 0; + index < ARRAY_SIZE(riscv_rpmi_hsm_state_transitions); index++) { + if (riscv_rpmi_hsm_state_transitions[index].state =3D=3D state) { + return &riscv_rpmi_hsm_state_transitions[index]; + } + } + + return NULL; +} + +static CPUState *riscv_rpmi_hart_cpu(RiscvRpmiState *s, uint32_t hart_inde= x) +{ + if (hart_index >=3D s->hart_count || !s->hart_ids) { + return NULL; + } + + return cpu_by_arch_id(s->hart_ids[hart_index]); +} + +static void riscv_rpmi_hsm_set_hw_state(RiscvRpmiState *s, + uint32_t hart_index, + enum rpmi_hart_hw_state state) +{ + CPUState *cpu =3D riscv_rpmi_hart_cpu(s, hart_index); + const RiscvRpmiHsmStateTransition *transition; + + if (hart_index >=3D s->hart_count || !s->hsm_hw_states) { + return; + } + + s->hsm_hw_states[hart_index] =3D state; + if (!cpu) { + return; + } + + transition =3D riscv_rpmi_hsm_state_transition(state); + if (!transition) { + return; + } + + cpu->halted =3D transition->halted; + if (transition->resume) { + cpu_resume(cpu); + } else { + qemu_cpu_kick(cpu); + } +} + +static enum rpmi_error riscv_rpmi_hsm_start_prepare( + void *priv, rpmi_uint32_t hart_index, rpmi_uint64_t start_addr) +{ + RiscvRpmiState *s =3D priv; + CPUState *cpu =3D riscv_rpmi_hart_cpu(s, hart_index); + + if (!cpu) { + return RPMI_ERR_INVALID_PARAM; + } + + cpu_set_pc(cpu, start_addr); + riscv_rpmi_hsm_set_hw_state(s, hart_index, RPMI_HART_HW_STATE_STARTED); + return RPMI_SUCCESS; +} + +static void riscv_rpmi_hsm_start_finalize(void *priv, + rpmi_uint32_t hart_index, + rpmi_uint64_t start_addr) +{ +} + +static enum rpmi_error riscv_rpmi_hsm_stop_prepare(void *priv, + rpmi_uint32_t hart_inde= x) +{ + RiscvRpmiState *s =3D priv; + + if (!riscv_rpmi_hart_cpu(s, hart_index)) { + return RPMI_ERR_INVALID_PARAM; + } + + riscv_rpmi_hsm_set_hw_state(s, hart_index, RPMI_HART_HW_STATE_STOPPED); + return RPMI_SUCCESS; +} + +static void riscv_rpmi_hsm_stop_finalize(void *priv, rpmi_uint32_t hart_in= dex) +{ +} + +static enum rpmi_error riscv_rpmi_hsm_suspend_prepare( + void *priv, rpmi_uint32_t hart_index, + const struct rpmi_hsm_suspend_type *suspend_type, + rpmi_uint64_t resume_addr) +{ + RiscvRpmiState *s =3D priv; + + if (!suspend_type || !riscv_rpmi_hart_cpu(s, hart_index)) { + return RPMI_ERR_INVALID_PARAM; + } + + riscv_rpmi_hsm_set_hw_state(s, hart_index, RPMI_HART_HW_STATE_SUSPENDE= D); + return RPMI_SUCCESS; +} + +static void riscv_rpmi_hsm_suspend_finalize( + void *priv, rpmi_uint32_t hart_index, + const struct rpmi_hsm_suspend_type *suspend_type, + rpmi_uint64_t resume_addr) +{ +} + +static enum rpmi_hart_hw_state riscv_rpmi_hsm_get_hw_state( + void *priv, rpmi_uint32_t hart_index) +{ + RiscvRpmiState *s =3D priv; + + if (hart_index >=3D s->hart_count || !s->hsm_hw_states) { + return RPMI_HART_HW_STATE_STOPPED; + } + + return s->hsm_hw_states[hart_index]; +} + +static const struct rpmi_hsm_platform_ops riscv_rpmi_hsm_ops =3D { + .hart_get_hw_state =3D riscv_rpmi_hsm_get_hw_state, + .hart_start_prepare =3D riscv_rpmi_hsm_start_prepare, + .hart_start_finalize =3D riscv_rpmi_hsm_start_finalize, + .hart_stop_prepare =3D riscv_rpmi_hsm_stop_prepare, + .hart_stop_finalize =3D riscv_rpmi_hsm_stop_finalize, + .hart_suspend_prepare =3D riscv_rpmi_hsm_suspend_prepare, + .hart_suspend_finalize =3D riscv_rpmi_hsm_suspend_finalize, +}; + +static bool riscv_rpmi_hsm_create(RiscvRpmiState *s, + struct rpmi_service_group **group, + Error **errp) +{ + struct rpmi_hsm *hsm; + + if (!s->hart_count || !s->hart_ids) { + error_setg(errp, "RPMI HSM service requires hart IDs"); + return false; + } + + s->hsm_hw_states =3D g_new0(uint32_t, s->hart_count); + for (uint32_t i =3D 0; i < s->hart_count; i++) { + s->hsm_hw_states[i] =3D RPMI_HART_HW_STATE_STARTED; + } + + hsm =3D rpmi_hsm_create(s->hart_count, s->hart_ids, + ARRAY_SIZE(riscv_rpmi_hsm_suspend_types), + riscv_rpmi_hsm_suspend_types, + &riscv_rpmi_hsm_ops, s); + if (!hsm) { + g_clear_pointer(&s->hsm_hw_states, g_free); + error_setg(errp, "failed to create RPMI HSM context"); + return false; + } + + *group =3D rpmi_service_group_hsm_create(hsm); + if (!*group) { + rpmi_hsm_destroy(hsm); + g_clear_pointer(&s->hsm_hw_states, g_free); + error_setg(errp, "failed to create RPMI HSM service group"); + return false; + } + + s->hsm =3D hsm; + return true; +} + +static void riscv_rpmi_hsm_destroy(RiscvRpmiState *s) +{ + if (s->hsm_group) { + rpmi_env_free_lock(s->hsm_group->lock); + s->hsm_group->lock =3D NULL; + rpmi_service_group_hsm_destroy(s->hsm_group); + s->hsm_group =3D NULL; + } + + if (s->hsm) { + rpmi_hsm_destroy(s->hsm); + s->hsm =3D NULL; + } + + g_clear_pointer(&s->hsm_hw_states, g_free); +} + + +bool riscv_rpmi_hsm_add(RiscvRpmiState *s, Error **errp) +{ + struct rpmi_service_group *group; + + if (s->hsm_group) { + error_setg(errp, "duplicate RPMI HSM service descriptor"); + return false; + } + + if (!riscv_rpmi_hsm_create(s, &group, errp)) { + return false; + } + + if (!riscv_rpmi_context_add_group(s, group, "HSM", errp)) { + s->hsm_group =3D group; + riscv_rpmi_hsm_destroy(s); + return false; + } + + s->hsm_group =3D group; + return true; +} + +void riscv_rpmi_hsm_remove(RiscvRpmiState *s) +{ + riscv_rpmi_context_remove_group(s, s->hsm_group); + riscv_rpmi_hsm_destroy(s); +} + +void riscv_rpmi_hsm_reset(RiscvRpmiState *s) +{ + if (!s->hsm_hw_states) { + return; + } + + for (uint32_t i =3D 0; i < s->hart_count; i++) { + s->hsm_hw_states[i] =3D RPMI_HART_HW_STATE_STARTED; + } + if (s->hsm) { + rpmi_hsm_process_state_changes(s->hsm); + } +} diff --git a/hw/misc/riscv_rpmi_internal.h b/hw/misc/riscv_rpmi_internal.h index 1d7445b2d1..7f9d110776 100644 --- a/hw/misc/riscv_rpmi_internal.h +++ b/hw/misc/riscv_rpmi_internal.h @@ -30,4 +30,8 @@ void riscv_rpmi_context_remove_group(RiscvRpmiState *s, bool riscv_rpmi_sysreset_add(RiscvRpmiState *s, Error **errp); void riscv_rpmi_sysreset_remove(RiscvRpmiState *s); =20 +bool riscv_rpmi_hsm_add(RiscvRpmiState *s, Error **errp); +void riscv_rpmi_hsm_remove(RiscvRpmiState *s); +void riscv_rpmi_hsm_reset(RiscvRpmiState *s); + #endif diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 7a97dfcf89..7c29e3634c 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1008,6 +1008,11 @@ static const RiscvRpmiServiceConfig virt_rpmi_servic= es[] =3D { .compatible =3D "riscv,rpmi-system-reset", .service_group =3D RPMI_SRVGRP_SYSTEM_RESET, }, + { + .node_name =3D "hsm", + .compatible =3D "riscv,rpmi-hsm", + .service_group =3D RPMI_SRVGRP_HSM, + }, }; =20 static uint32_t virt_rpmi_service_count(RISCVVirtState *s) diff --git a/include/hw/misc/riscv_rpmi.h b/include/hw/misc/riscv_rpmi.h index 1500ff1b8b..9f7aa9f6ef 100644 --- a/include/hw/misc/riscv_rpmi.h +++ b/include/hw/misc/riscv_rpmi.h @@ -44,6 +44,7 @@ struct rpmi_context; struct rpmi_service_group; struct rpmi_shmem; struct rpmi_transport; +struct rpmi_hsm; =20 typedef struct RiscvRpmiMachineOps { void (*system_reset)(void); @@ -84,6 +85,9 @@ struct RiscvRpmiState { char *platform_info; const RiscvRpmiMachineOps *machine_ops; struct rpmi_service_group *sysreset_group; + struct rpmi_hsm *hsm; + struct rpmi_service_group *hsm_group; + uint32_t *hsm_hw_states; uint32_t *hart_ids; uint32_t hart_count; const RiscvRpmiServiceConfig *services; From nobody Sat Sep 26 20:51:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1789622744; cv=none; d=zohomail.com; s=zohoarc; b=D0AY2xdNNy9qs8WN8XFCrhuX12gbuebeirFjaZqi/zFCOAkYyarjIG0F7UqGop5q2Ev40BmF+CYBlkvONnasFzDmy1S8r8YjYVb6ZRR/M5PQjKd9BNKzysLrWUXyv2yOYOWFvkf7XU0j2BwLhCvkAO0WyxzbIogVVh/qpAjUu/4= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=subrahmanya.lingappa@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789622747187158500 Content-Type: text/plain; charset="utf-8" Add the RPMI System Suspend service group for RISC-V virt. The service advertises suspend-to-RAM support through librpmi, registers QEMU wakeup support, and routes the suspend finalize callback to the machine suspend path. On wakeup it processes RPMI group events and defers the HSM hart resume until vCPUs are ready to run again. Signed-off-by: Subrahmanya Lingappa Reviewed-by: Daniel Henrique Barboza --- hw/misc/meson.build | 1 + hw/misc/riscv_rpmi.c | 4 + hw/misc/riscv_rpmi_hsm.c | 10 +- hw/misc/riscv_rpmi_internal.h | 6 ++ hw/misc/riscv_rpmi_syssusp.c | 194 ++++++++++++++++++++++++++++++++++ hw/riscv/virt.c | 24 +++++ include/hw/misc/riscv_rpmi.h | 10 ++ 7 files changed, 248 insertions(+), 1 deletion(-) create mode 100644 hw/misc/riscv_rpmi_syssusp.c diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 3f2caaf06f..a0b15aaf2e 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -180,4 +180,5 @@ system_ss.add(when: 'CONFIG_RISCV_RPMI', if_true: [file= s( 'riscv_rpmi.c', 'riscv_rpmi_sysreset.c', 'riscv_rpmi_hsm.c', + 'riscv_rpmi_syssusp.c', ), librpmi], if_false: files('riscv_rpmi-stub.c')) diff --git a/hw/misc/riscv_rpmi.c b/hw/misc/riscv_rpmi.c index b3b9a202a5..83a41cb71c 100644 --- a/hw/misc/riscv_rpmi.c +++ b/hw/misc/riscv_rpmi.c @@ -215,6 +215,10 @@ static const RiscvRpmiServiceOps riscv_rpmi_service_op= s[] =3D { .service_group =3D RPMI_SRVGRP_HSM, .add =3D riscv_rpmi_hsm_add, .remove =3D riscv_rpmi_hsm_remove, + }, { + .service_group =3D RPMI_SRVGRP_SYSTEM_SUSPEND, + .add =3D riscv_rpmi_syssusp_add, + .remove =3D riscv_rpmi_syssusp_remove, }, }; =20 diff --git a/hw/misc/riscv_rpmi_hsm.c b/hw/misc/riscv_rpmi_hsm.c index 08a985cb30..928fe3e52e 100644 --- a/hw/misc/riscv_rpmi_hsm.c +++ b/hw/misc/riscv_rpmi_hsm.c @@ -236,7 +236,6 @@ static void riscv_rpmi_hsm_destroy(RiscvRpmiState *s) g_clear_pointer(&s->hsm_hw_states, g_free); } =20 - bool riscv_rpmi_hsm_add(RiscvRpmiState *s, Error **errp) { struct rpmi_service_group *group; @@ -279,3 +278,12 @@ void riscv_rpmi_hsm_reset(RiscvRpmiState *s) rpmi_hsm_process_state_changes(s->hsm); } } + +void riscv_rpmi_hsm_resume(RiscvRpmiState *s, uint32_t hart_index, + uint64_t resume_addr) +{ + riscv_rpmi_hsm_set_hw_state(s, hart_index, RPMI_HART_HW_STATE_STARTED); + if (s->hsm) { + rpmi_hsm_process_state_changes(s->hsm); + } +} diff --git a/hw/misc/riscv_rpmi_internal.h b/hw/misc/riscv_rpmi_internal.h index 7f9d110776..2c4723ad6b 100644 --- a/hw/misc/riscv_rpmi_internal.h +++ b/hw/misc/riscv_rpmi_internal.h @@ -33,5 +33,11 @@ void riscv_rpmi_sysreset_remove(RiscvRpmiState *s); bool riscv_rpmi_hsm_add(RiscvRpmiState *s, Error **errp); void riscv_rpmi_hsm_remove(RiscvRpmiState *s); void riscv_rpmi_hsm_reset(RiscvRpmiState *s); +void riscv_rpmi_hsm_resume(RiscvRpmiState *s, uint32_t hart_index, + uint64_t resume_addr); + +bool riscv_rpmi_syssusp_add(RiscvRpmiState *s, Error **errp); +void riscv_rpmi_syssusp_remove(RiscvRpmiState *s); + =20 #endif diff --git a/hw/misc/riscv_rpmi_syssusp.c b/hw/misc/riscv_rpmi_syssusp.c new file mode 100644 index 0000000000..f4a9bbdaf4 --- /dev/null +++ b/hw/misc/riscv_rpmi_syssusp.c @@ -0,0 +1,194 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * RISC-V RPMI System Suspend service. + * + * Copyright (c) 2026 Qualcomm Technologies, Inc. + * Author: + * Subrahmanya Lingappa + */ + +#include "qemu/osdep.h" +#include "riscv_rpmi_internal.h" +#include "qemu/timer.h" +#include "system/runstate.h" + +static const struct rpmi_system_suspend_type riscv_rpmi_syssusp_types[] = =3D { + { + .type =3D RPMI_SYSSUSP_TYPE_SUSPEND_TO_RAM, + .attr =3D RPMI_SYSSUSP_ATTRS_FLAGS_RESUMEADDR, + }, +}; + +static enum rpmi_error riscv_rpmi_syssusp_prepare( + void *priv, rpmi_uint32_t hart_index, + const struct rpmi_system_suspend_type *syssusp_type, + rpmi_uint64_t resume_addr) +{ + RiscvRpmiState *s =3D priv; + + if (s->machine_ops && s->machine_ops->register_wakeup_support) { + s->machine_ops->register_wakeup_support(); + } + return RPMI_SUCCESS; +} + +static rpmi_bool_t riscv_rpmi_syssusp_ready(void *priv, + rpmi_uint32_t hart_index) +{ + return true; +} + +static void riscv_rpmi_syssusp_finalize( + void *priv, rpmi_uint32_t hart_index, + const struct rpmi_system_suspend_type *syssusp_type, + rpmi_uint64_t resume_addr) +{ + RiscvRpmiState *s =3D priv; + + if (s->machine_ops && s->machine_ops->system_suspend) { + s->machine_ops->system_suspend(); + } +} + +static rpmi_bool_t riscv_rpmi_syssusp_can_resume(void *priv, + rpmi_uint32_t hart_index) +{ + RiscvRpmiState *s =3D priv; + + if (s->machine_ops && s->machine_ops->system_can_resume) { + return s->machine_ops->system_can_resume(); + } + + return true; +} + +static enum rpmi_error riscv_rpmi_syssusp_resume( + void *priv, rpmi_uint32_t hart_index, + const struct rpmi_system_suspend_type *syssusp_type, + rpmi_uint64_t resume_addr) +{ + RiscvRpmiState *s =3D priv; + + s->syssusp_resume_hart_index =3D hart_index; + s->syssusp_resume_addr =3D resume_addr; + s->syssusp_resume_pending =3D true; + return RPMI_SUCCESS; +} + +static const struct rpmi_syssusp_platform_ops riscv_rpmi_syssusp_ops =3D { + .system_suspend_prepare =3D riscv_rpmi_syssusp_prepare, + .system_suspend_ready =3D riscv_rpmi_syssusp_ready, + .system_suspend_finalize =3D riscv_rpmi_syssusp_finalize, + .system_suspend_can_resume =3D riscv_rpmi_syssusp_can_resume, + .system_suspend_resume =3D riscv_rpmi_syssusp_resume, +}; + +static void riscv_rpmi_wakeup_timer(void *opaque) +{ + RiscvRpmiState *s =3D opaque; + + if (s->syssusp_resume_pending) { + riscv_rpmi_hsm_resume(s, s->syssusp_resume_hart_index, + s->syssusp_resume_addr); + s->syssusp_resume_pending =3D false; + s->syssusp_resume_addr =3D 0; + } +} + +static void riscv_rpmi_wakeup_notify(Notifier *notifier, void *data) +{ + RiscvRpmiState *s =3D container_of(notifier, RiscvRpmiState, + wakeup_notifier); + + if (s->context) { + rpmi_context_process_group_events(s->context, + RPMI_SRVGRP_SYSTEM_SUSPEND); + } + if (s->wakeup_timer) { + /* + * Wakeup notifiers run before vCPUs resume. Defer the HSM + * kick so OpenSBI can leave WFI after QEMU restarts execution. + */ + timer_mod(s->wakeup_timer, qemu_clock_get_ms(QEMU_CLOCK_REALTIME) = + 10); + } +} + +static bool riscv_rpmi_syssusp_create(RiscvRpmiState *s, + struct rpmi_service_group **group, + Error **errp) +{ + if (!s->hsm) { + error_setg(errp, "RPMI system suspend service requires HSM service= "); + return false; + } + + if (s->machine_ops && s->machine_ops->register_wakeup_support) { + s->machine_ops->register_wakeup_support(); + } + if (!s->wakeup_timer) { + s->wakeup_timer =3D timer_new_ms(QEMU_CLOCK_REALTIME, + riscv_rpmi_wakeup_timer, s); + } + if (!s->wakeup_notifier_registered) { + s->wakeup_notifier.notify =3D riscv_rpmi_wakeup_notify; + qemu_register_wakeup_notifier(&s->wakeup_notifier); + s->wakeup_notifier_registered =3D true; + } + + *group =3D rpmi_service_group_syssusp_create( + s->hsm, ARRAY_SIZE(riscv_rpmi_syssusp_types), + riscv_rpmi_syssusp_types, &riscv_rpmi_syssusp_ops, s); + if (!*group) { + error_setg(errp, "failed to create RPMI system suspend service gro= up"); + return false; + } + + return true; +} + +static void riscv_rpmi_syssusp_destroy(RiscvRpmiState *s) +{ + if (s->wakeup_notifier_registered) { + notifier_remove(&s->wakeup_notifier); + s->wakeup_notifier_registered =3D false; + } + if (s->wakeup_timer) { + timer_free(s->wakeup_timer); + s->wakeup_timer =3D NULL; + } + + if (s->syssusp_group) { + rpmi_service_group_syssusp_destroy(s->syssusp_group); + s->syssusp_group =3D NULL; + } +} + +bool riscv_rpmi_syssusp_add(RiscvRpmiState *s, Error **errp) +{ + struct rpmi_service_group *group; + + if (s->syssusp_group) { + error_setg(errp, "duplicate RPMI system suspend descriptor"); + return false; + } + + if (!riscv_rpmi_syssusp_create(s, &group, errp)) { + return false; + } + + if (!riscv_rpmi_context_add_group(s, group, "system suspend", errp)) { + s->syssusp_group =3D group; + riscv_rpmi_syssusp_destroy(s); + return false; + } + + s->syssusp_group =3D group; + return true; +} + +void riscv_rpmi_syssusp_remove(RiscvRpmiState *s) +{ + riscv_rpmi_context_remove_group(s, s->syssusp_group); + riscv_rpmi_syssusp_destroy(s); +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 7c29e3634c..87399ed803 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -50,6 +50,7 @@ #include "chardev/char.h" #include "system/device_tree.h" #include "system/system.h" +#include "system/runstate.h" #include "system/tcg.h" #include "system/kvm.h" #include "system/tpm.h" @@ -1013,6 +1014,11 @@ static const RiscvRpmiServiceConfig virt_rpmi_servic= es[] =3D { .compatible =3D "riscv,rpmi-hsm", .service_group =3D RPMI_SRVGRP_HSM, }, + { + .node_name =3D "suspend", + .compatible =3D "riscv,rpmi-system-suspend", + .service_group =3D RPMI_SRVGRP_SYSTEM_SUSPEND, + }, }; =20 static uint32_t virt_rpmi_service_count(RISCVVirtState *s) @@ -1030,9 +1036,27 @@ static void virt_rpmi_system_shutdown(void) qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); } =20 +static void virt_rpmi_system_suspend(void) +{ + qemu_system_suspend_request(); +} + +static void virt_rpmi_register_wakeup_support(void) +{ + qemu_register_wakeup_support(); +} + +static bool virt_rpmi_system_can_resume(void) +{ + return runstate_check(RUN_STATE_RUNNING); +} + static const RiscvRpmiMachineOps virt_rpmi_machine_ops =3D { .system_reset =3D virt_rpmi_system_reset, .system_shutdown =3D virt_rpmi_system_shutdown, + .system_suspend =3D virt_rpmi_system_suspend, + .register_wakeup_support =3D virt_rpmi_register_wakeup_support, + .system_can_resume =3D virt_rpmi_system_can_resume, }; =20 static RiscvRpmiConfig virt_rpmi_config(RISCVVirtState *s, diff --git a/include/hw/misc/riscv_rpmi.h b/include/hw/misc/riscv_rpmi.h index 9f7aa9f6ef..a0381e31d7 100644 --- a/include/hw/misc/riscv_rpmi.h +++ b/include/hw/misc/riscv_rpmi.h @@ -49,6 +49,9 @@ struct rpmi_hsm; typedef struct RiscvRpmiMachineOps { void (*system_reset)(void); void (*system_shutdown)(void); + void (*system_suspend)(void); + void (*register_wakeup_support)(void); + bool (*system_can_resume)(void); } RiscvRpmiMachineOps; =20 typedef struct RiscvRpmiServiceConfig { @@ -85,9 +88,16 @@ struct RiscvRpmiState { char *platform_info; const RiscvRpmiMachineOps *machine_ops; struct rpmi_service_group *sysreset_group; + struct rpmi_service_group *syssusp_group; struct rpmi_hsm *hsm; struct rpmi_service_group *hsm_group; uint32_t *hsm_hw_states; + Notifier wakeup_notifier; + bool wakeup_notifier_registered; + QEMUTimer *wakeup_timer; + bool syssusp_resume_pending; + uint32_t syssusp_resume_hart_index; + uint64_t syssusp_resume_addr; uint32_t *hart_ids; uint32_t hart_count; const RiscvRpmiServiceConfig *services; From nobody Sat Sep 26 20:51:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1789622744; cv=none; d=zohomail.com; s=zohoarc; b=NI8ggy09SaywraI28jzEJRsQut1eAhRxqI+XBRzfiz/8ARCdOGmmI5mELOFXsdfGBBcupFgOiHPlCvE71xihlTWwDPb+CGfMx/S2CfdglJi4Q0fZ7u4Yt23+o9DnCQHxCdISET8BKlovMjun9vEx/kJwc9+GRAZtoTKwLOHIf80= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=subrahmanya.lingappa@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789622745125158500 Content-Type: text/plain; charset="utf-8" Document the opt-in virt RPMI transport and the initial HSM, system reset, and system suspend service groups. Signed-off-by: Subrahmanya Lingappa Reviewed-by: Daniel Henrique Barboza --- docs/system/riscv/virt.rst | 80 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index 3c87246891..0d719c4c0d 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -149,6 +149,86 @@ The following machine-specific options are supported: =20 Enables the riscv-iommu-sys platform device. Defaults to 'off'. =20 +- rpmi=3D[on|off] + + Enables the RISC-V RPMI shared-memory transport. This option defaults to + "off", is TCG-only, and is available only when QEMU is built with librpmi + support. This support targets the RISC-V Platform Management Interface + (RPMI) Specification v1.0 Ratified (`RPMI v1.0 specification`_). The ini= tial + ``virt`` implementation exposes RPMI system reset, system suspend, and H= SM + service groups. System reset can request shutdown or cold reboot through + RPMI. HSM uses the ``virt`` hart IDs and supports hart discovery, status, + start, stop, and suspend commands. System suspend uses QEMU's suspend and + wakeup path. Migration is currently blocked while RPMI transport and ser= vice + VMState support is being designed. + + The build dependency is provided by `librpmi`_. QEMU requires librpmi 1.= 0.0 + or newer. If the host distribution does not provide a librpmi development + package, build and install it from the upstream source tree so that + ``pkg-config`` can find ``librpmi.pc``: + + .. code-block:: bash + + $ git clone https://github.com/riscv-software-src/librpmi.git + $ cd librpmi + $ make + $ make install I=3D/usr/local + $ export PKG_CONFIG_PATH=3D/usr/local/lib/pkgconfig:$PKG_CONFIG_PATH + $ pkg-config --modversion librpmi + + The librpmi repository can also generate installable ``librpmi-dev`` Deb= ian + packages with ``make deb-pkg`` and ``librpmi-devel`` RPM packages with + ``make rpm-pkg``. After installing librpmi, configure QEMU with + ``--enable-librpmi`` or ``-Dlibrpmi=3Denabled``. + +.. _RPMI v1.0 specification: https://github.com/riscv-non-isa/riscv-rpmi/r= eleases/download/v1.0/riscv-rpmi.pdf +.. _librpmi: https://github.com/riscv-software-src/librpmi + +RPMI qtest coverage +------------------- + +QEMU includes qtest coverage for the RPMI transport and the initial service +groups in ``tests/qtest/riscv-rpmi-test.c``. To run the qtest from a build +configured with librpmi support and the ``riscv64-softmmu`` target: + +.. code-block:: bash + + $ meson test -C build qemu:qtest-riscv64/riscv-rpmi-test + +The qtest covers Base service discovery, System Reset, HSM, System Suspend, +negative transport cases, reset behavior, and migration blocking while RPMI +VMState support is being designed. + +RPMI firmware and guest smoke +----------------------------- + +A firmware-level RPMI smoke test can be run with OpenSBI, a Linux kernel, = and a +RISC-V disk image: + +.. code-block:: bash + + $ qemu-system-riscv64 \ + -machine virt,rpmi=3Don \ + -cpu rv64 -smp 4 -m 4G -nographic \ + -bios /path/to/fw_jump.bin \ + -kernel /path/to/Image \ + -append "root=3D/dev/vda rw console=3DttyS0 earlycon=3Dsbi" \ + -drive file=3D/path/to/rootfs.img,format=3Draw,if=3Dvirtio,snapshot= =3Don + +The OpenSBI banner should report RPMI-backed HSM and system suspend suppor= t. +After the guest reaches a shell, normal guest reboot/poweroff commands exe= rcise +the RPMI system reset path. + +RPMI device tree policy +----------------------- + +RPMI is currently described through FDT only; no ACPI representation is em= itted +for the RPMI transport or service groups. The ``virt`` machine uses the +``riscv,rpmi-shmem-mbox`` shared-memory mailbox node plus child service no= des +with ``riscv,rpmi-*`` compatible strings. These binding names are part of = the +RPMI RFC surface and may be revised if the RISC-V RPMI bindings change dur= ing +review. + Running Linux kernel -------------------- From nobody Sat Sep 26 20:51:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1789622744; cv=none; d=zohomail.com; s=zohoarc; b=PAa+lBagjzc0MEdgA7uxzkGpRS/Xqrx4Q3pIetf5HndP/D2KskqkQUuVoRS9QDLvlIZYzqwQpJV6A2s+8LyTzCoYzIv+MlHgKnhcVelcQd/Ww3w38grsi7D0r2Avt6frh9pYf2GpFVnLo0whd3otfhaLw3Wy4tPmPJySIYolfww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789622744; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Kdhi+is1bOov2r5UgWP1UbjUYrcUQDWxNr0OFYSDwOM=; b=RDZvHvFs13kOFosoKqjIgb0M1A7awz6a0dj1dJ4m2LCpO/7aTPgMgMLUY1zD4947IzRapcCDXHJCZ/3wDUYlFCOzL+RF4IDExq2wI+y9XJfssBUtIM85UkPITCSNyMcwUDuxJ6H6Q2/2wB4dEv9ylLNjm4+0TwbdbvXSGYkEKeU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1789622744808104.05877530777218; Wed, 16 Sep 2026 22:25:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x74bL-0007r4-87; Thu, 17 Sep 2026 01:24:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x74bG-0007oC-8z for qemu-devel@nongnu.org; Thu, 17 Sep 2026 01:23:58 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x74bD-0004DD-AK for qemu-devel@nongnu.org; Thu, 17 Sep 2026 01:23:58 -0400 Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68H2Gqar1239348 for ; Thu, 17 Sep 2026 05:23:54 GMT Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gr79m0kny-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 17 Sep 2026 05:23:53 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-38dc0eee75dso143214a91.0 for ; Wed, 16 Sep 2026 22:23:53 -0700 (PDT) Received: from hu-slingapp-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=subrahmanya.lingappa@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789622745238158500 Content-Type: text/plain; charset="utf-8" Add qtests for the RPMI transport plus Base, system reset, HSM, and system suspend service groups. Signed-off-by: Subrahmanya Lingappa Reviewed-by: Daniel Henrique Barboza --- MAINTAINERS | 1 + tests/qtest/meson.build | 2 + tests/qtest/riscv-rpmi-test.c | 625 ++++++++++++++++++++++++++++++++++ 3 files changed, 628 insertions(+) create mode 100644 tests/qtest/riscv-rpmi-test.c diff --git a/MAINTAINERS b/MAINTAINERS index d0973d470c..c2939e5bfa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -374,6 +374,7 @@ F: hw/riscv/ F: hw/intc/riscv* F: hw/misc/riscv_rpmi* F: include/hw/misc/riscv_rpmi.h +F: tests/qtest/riscv-rpmi-test.c F: include/hw/char/riscv_htif.h F: include/hw/riscv/ F: common-user/host/riscv* diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index cbdef5a545..96f9ba9d4b 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -296,6 +296,8 @@ qtests_riscv32 =3D \ =20 qtests_riscv64 =3D ['riscv-csr-test'] + \ (unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ + (config_all_devices.has_key('CONFIG_RISCV_RPMI') ? + ['riscv-rpmi-test'] : []) + \ (config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') and config_all_devices.has_key('CONFIG_RISCV_IOMMU') ? ['iommu-riscv-test'] : []) + \ diff --git a/tests/qtest/riscv-rpmi-test.c b/tests/qtest/riscv-rpmi-test.c new file mode 100644 index 0000000000..fa23ab73db --- /dev/null +++ b/tests/qtest/riscv-rpmi-test.c @@ -0,0 +1,625 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * QTests for RISC-V RPMI devices. + * + * Copyright (c) 2026 Qualcomm Technologies, Inc. + * Author: + * Subrahmanya Lingappa + */ + +#include "qemu/osdep.h" +#include +#include "libqtest.h" +#include "qobject/qdict.h" + +#define RPMI_SHMEM_BASE 0x10200000ULL +#define RPMI_DOORBELL_BASE 0x10230000ULL +#define RPMI_SLOT_SIZE 64 + +#define RPMI_A2P_HEAD RPMI_SHMEM_BASE +#define RPMI_A2P_TAIL (RPMI_SHMEM_BASE + RPMI_SLOT_SIZE) +#define RPMI_A2P_SLOT0 (RPMI_SHMEM_BASE + 2 * RPMI_SLOT_SIZE) + +#define RPMI_SRVGRP_BASE 0x0001 +#define RPMI_SRVGRP_SYSTEM_RESET 0x0003 +#define RPMI_SRVGRP_SYSTEM_SUSPEND 0x0004 +#define RPMI_SRVGRP_HSM 0x0005 +#define RPMI_BASE_SRV_GET_PLATFORM_INFO 0x05 +#define RPMI_BASE_SRV_PROBE_SERVICE_GROUP 0x06 +#define RPMI_SYSRST_SRV_GET_ATTRIBUTES 0x02 +#define RPMI_SYSRST_SRV_SYSTEM_RESET 0x03 +#define RPMI_HSM_SRV_GET_HART_STATUS 0x02 +#define RPMI_HSM_SRV_GET_HART_LIST 0x03 +#define RPMI_HSM_SRV_GET_SUSPEND_TYPES 0x04 +#define RPMI_HSM_SRV_GET_SUSPEND_INFO 0x05 +#define RPMI_HSM_SRV_HART_START 0x06 +#define RPMI_HSM_SRV_HART_STOP 0x07 +#define RPMI_HSM_SRV_HART_SUSPEND 0x08 +#define RPMI_SYSSUSP_SRV_GET_ATTRIBUTES 0x02 +#define RPMI_SYSSUSP_SRV_SYSTEM_SUSPEND 0x03 +#define RPMI_MSG_NORMAL_REQUEST 0x00 +#define RPMI_MSG_POSTED_REQUEST 0x01 +#define RPMI_MSG_ACKNOWLEDGEMENT 0x02 +#define RPMI_SYSRST_TYPE_SHUTDOWN 0x00 +#define RPMI_SYSRST_TYPE_COLD_REBOOT 0x01 +#define RPMI_SYSRST_TYPE_INVALID 0x03 +#define RPMI_SYSRST_ATTRS_FLAGS_RESETTYPE 1 +#define RPMI_TOKEN 0x55aa +#define RPMI_ERR_NOTSUPP 0xfffffffeU +#define RPMI_ERR_INVALID_PARAM 0xfffffffdU +#define RPMI_ERR_INVALID_ADDR 0xfffffffbU +#define RPMI_ERR_DENIED 0xfffffffcU +#define RPMI_HSM_HART_STATE_STARTED 0x00 +#define RPMI_HSM_HART_STATE_STOPPED 0x01 +#define RPMI_HSM_HART_STATE_SUSPENDED 0x04 +#define RPMI_HSM_TEST_START_ADDR 0x80000000ULL +#define RPMI_HSM_TEST_RESUME_ADDR 0x80001000ULL + +#define RPMI_P2A_ACK_BASE (RPMI_SHMEM_BASE + 16 * RPMI_SLOT_SIZE) +#define RPMI_P2A_ACK_HEAD RPMI_P2A_ACK_BASE +#define RPMI_P2A_ACK_TAIL (RPMI_P2A_ACK_BASE + RPMI_SLOT_SIZE) +#define RPMI_P2A_ACK_SLOT0 (RPMI_P2A_ACK_BASE + 2 * RPMI_SLOT_SIZE) + +static uint64_t rpmi_response_base; + +static uint64_t rpmi_queue_slot(uint64_t queue_base, uint32_t index) +{ + return queue_base + (index + 2) * RPMI_SLOT_SIZE; +} + +static void rpmi_send_request(QTestState *qts, uint16_t service_group, + uint8_t service_id, uint8_t request_type, + const uint32_t *data, size_t data_words) +{ + uint32_t tail =3D qtest_readl(qts, RPMI_A2P_TAIL); + uint64_t slot =3D rpmi_queue_slot(RPMI_SHMEM_BASE, tail); + size_t i; + + qtest_writew(qts, slot, service_group); + qtest_writeb(qts, slot + 2, service_id); + qtest_writeb(qts, slot + 3, request_type); + qtest_writew(qts, slot + 4, data_words * sizeof(*data)); + qtest_writew(qts, slot + 6, RPMI_TOKEN); + + for (i =3D 0; i < data_words; i++) { + qtest_writel(qts, slot + 8 + i * sizeof(*data), data[i]); + } + + g_test_message( + "RPMI_A2P_REQ shmem=3D0x%016" PRIx64 " doorbell=3D0x%016" PRIx64 + " group=3D0x%04x service=3D0x%02x type=3D0x%02x data_len=3D%zu" + " token=3D0x%04x a2p_tail=3D%u slot=3D0x%016" PRIx64, + (uint64_t)RPMI_SHMEM_BASE, (uint64_t)RPMI_DOORBELL_BASE, + service_group, service_id, request_type, data_words * sizeof(*data= ), + RPMI_TOKEN, tail, slot); + + qtest_writel(qts, RPMI_A2P_TAIL, (tail + 1) % 16); + qtest_writel(qts, RPMI_DOORBELL_BASE, 1); +} + +static uint32_t rpmi_response_word(QTestState *qts, unsigned int word) +{ + return qtest_readl(qts, rpmi_response_base + 8 + word * sizeof(uint32_= t)); +} + +static void rpmi_expect_ack(QTestState *qts, uint16_t service_group, + uint8_t service_id, uint16_t data_len) +{ + uint32_t head =3D qtest_readl(qts, RPMI_P2A_ACK_HEAD); + uint32_t tail =3D qtest_readl(qts, RPMI_P2A_ACK_TAIL); + + g_assert_cmphex(tail, !=3D, head); + rpmi_response_base =3D rpmi_queue_slot(RPMI_P2A_ACK_BASE, head); + g_assert_cmphex(qtest_readw(qts, rpmi_response_base), =3D=3D, service_= group); + g_assert_cmphex(qtest_readb(qts, rpmi_response_base + 2), =3D=3D, + service_id); + g_assert_cmphex(qtest_readb(qts, rpmi_response_base + 3), =3D=3D, + RPMI_MSG_ACKNOWLEDGEMENT); + g_assert_cmphex(qtest_readw(qts, rpmi_response_base + 4), =3D=3D, data= _len); + g_assert_cmphex(qtest_readw(qts, rpmi_response_base + 6), =3D=3D, + RPMI_TOKEN); + g_test_message( + "RPMI_P2A_ACK shmem=3D0x%016" PRIx64 + " group=3D0x%04x service=3D0x%02x type=3D0x%02x data_len=3D%u" + " token=3D0x%04x p2a_head=3D%u slot=3D0x%016" PRIx64 + " status=3D0x%08x", + (uint64_t)RPMI_SHMEM_BASE, service_group, service_id, + RPMI_MSG_ACKNOWLEDGEMENT, data_len, RPMI_TOKEN, head, + rpmi_response_base, + data_len >=3D sizeof(uint32_t) ? rpmi_response_word(qts, 0) : 0); + qtest_writel(qts, RPMI_P2A_ACK_HEAD, (head + 1) % 16); +} + +static void rpmi_send_sysreset(QTestState *qts, uint32_t reset_type, + uint8_t request_type) +{ + rpmi_send_request(qts, RPMI_SRVGRP_SYSTEM_RESET, + RPMI_SYSRST_SRV_SYSTEM_RESET, request_type, + &reset_type, 1); +} + +static void rpmi_expect_qemu_failure(const char *extra_args, + const char *stderr_needle) +{ + g_autoptr(GError) error =3D NULL; + g_auto(GStrv) split_args =3D NULL; + g_autoptr(GPtrArray) argv =3D g_ptr_array_new(); + g_autofree char *stderr_data =3D NULL; + gint wait_status; + gboolean spawned; + + g_assert_true(g_shell_parse_argv(extra_args, NULL, &split_args, &error= )); + g_assert_no_error(error); + + g_ptr_array_add(argv, (gpointer)qtest_qemu_binary(NULL)); + for (char **arg =3D split_args; *arg; arg++) { + g_ptr_array_add(argv, *arg); + } + g_ptr_array_add(argv, NULL); + + spawned =3D g_spawn_sync(NULL, (char **)argv->pdata, NULL, + G_SPAWN_STDOUT_TO_DEV_NULL, + NULL, NULL, NULL, &stderr_data, + &wait_status, &error); + g_assert_true(spawned); + g_assert_no_error(error); + g_assert_false(g_spawn_check_exit_status(wait_status, NULL)); + g_assert_nonnull(stderr_data); + g_assert_nonnull(strstr(stderr_data, stderr_needle)); +} + +static void test_rpmi_machine_realize_off(void) +{ + QTestState *qts; + + qts =3D qtest_init("-machine virt,rpmi=3Doff"); + qtest_quit(qts); +} + +static void test_rpmi_machine_rejects_too_many_harts(void) +{ + rpmi_expect_qemu_failure( + "-machine virt,rpmi=3Don -smp 513 -display none -S", + "max CPUs supported by machine 'virt' is 512"); +} + +static void test_rpmi_base_platform_info(void) +{ + static const char expected[] =3D "QEMU RISC-V virt RPMI"; + QTestState *qts; + size_t i; + + qts =3D qtest_init("-machine virt,rpmi=3Don"); + rpmi_send_request(qts, RPMI_SRVGRP_BASE, + RPMI_BASE_SRV_GET_PLATFORM_INFO, + RPMI_MSG_NORMAL_REQUEST, NULL, 0); + + rpmi_expect_ack(qts, RPMI_SRVGRP_BASE, + RPMI_BASE_SRV_GET_PLATFORM_INFO, + 2 * sizeof(uint32_t) + sizeof(expected)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 1), =3D=3D, sizeof(expected)); + for (i =3D 0; i < sizeof(expected); i++) { + g_assert_cmphex(qtest_readb(qts, RPMI_P2A_ACK_SLOT0 + 16 + i), =3D= =3D, + expected[i]); + } + + qtest_quit(qts); +} + +static void rpmi_probe_group(QTestState *qts, uint32_t service_group, + bool present) +{ + rpmi_send_request(qts, RPMI_SRVGRP_BASE, + RPMI_BASE_SRV_PROBE_SERVICE_GROUP, + RPMI_MSG_NORMAL_REQUEST, &service_group, 1); + + rpmi_expect_ack(qts, RPMI_SRVGRP_BASE, + RPMI_BASE_SRV_PROBE_SERVICE_GROUP, + 2 * sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + if (present) { + g_assert_cmphex(rpmi_response_word(qts, 1), !=3D, 0); + } else { + g_assert_cmphex(rpmi_response_word(qts, 1), =3D=3D, 0); + } +} + +static void test_rpmi_base_probe_service_groups(void) +{ + QTestState *qts; + + qts =3D qtest_init("-machine virt,rpmi=3Don,aia=3Daplic-imsic"); + rpmi_probe_group(qts, RPMI_SRVGRP_BASE, true); + qtest_system_reset(qts); + rpmi_probe_group(qts, RPMI_SRVGRP_SYSTEM_RESET, true); + qtest_system_reset(qts); + rpmi_probe_group(qts, RPMI_SRVGRP_HSM, true); + qtest_system_reset(qts); + rpmi_probe_group(qts, RPMI_SRVGRP_SYSTEM_SUSPEND, true); + + qtest_quit(qts); +} + +static void test_rpmi_sysreset_attrs(void) +{ + QTestState *qts; + uint32_t reset_type =3D RPMI_SYSRST_TYPE_SHUTDOWN; + + qts =3D qtest_init("-machine virt,rpmi=3Don"); + rpmi_send_request(qts, RPMI_SRVGRP_SYSTEM_RESET, + RPMI_SYSRST_SRV_GET_ATTRIBUTES, + RPMI_MSG_NORMAL_REQUEST, &reset_type, 1); + rpmi_expect_ack(qts, RPMI_SRVGRP_SYSTEM_RESET, + RPMI_SYSRST_SRV_GET_ATTRIBUTES, 2 * sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 1), =3D=3D, + RPMI_SYSRST_ATTRS_FLAGS_RESETTYPE); + + qtest_system_reset(qts); + reset_type =3D RPMI_SYSRST_TYPE_COLD_REBOOT; + rpmi_send_request(qts, RPMI_SRVGRP_SYSTEM_RESET, + RPMI_SYSRST_SRV_GET_ATTRIBUTES, + RPMI_MSG_NORMAL_REQUEST, &reset_type, 1); + rpmi_expect_ack(qts, RPMI_SRVGRP_SYSTEM_RESET, + RPMI_SYSRST_SRV_GET_ATTRIBUTES, 2 * sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 1), =3D=3D, + RPMI_SYSRST_ATTRS_FLAGS_RESETTYPE); + + qtest_system_reset(qts); + reset_type =3D RPMI_SYSRST_TYPE_INVALID; + rpmi_send_request(qts, RPMI_SRVGRP_SYSTEM_RESET, + RPMI_SYSRST_SRV_GET_ATTRIBUTES, + RPMI_MSG_NORMAL_REQUEST, &reset_type, 1); + rpmi_expect_ack(qts, RPMI_SRVGRP_SYSTEM_RESET, + RPMI_SYSRST_SRV_GET_ATTRIBUTES, 2 * sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 1), =3D=3D, 0); + + qtest_quit(qts); +} + +static void test_rpmi_sysreset_shutdown(void) +{ + QTestState *qts; + + qts =3D qtest_init("-machine virt,rpmi=3Don"); + rpmi_send_sysreset(qts, RPMI_SYSRST_TYPE_SHUTDOWN, + RPMI_MSG_POSTED_REQUEST); + qtest_qmp_eventwait(qts, "SHUTDOWN"); + qtest_quit(qts); +} + +static void test_rpmi_sysreset_cold_reboot(void) +{ + QTestState *qts; + + qts =3D qtest_init("-machine virt,rpmi=3Don -no-reboot"); + rpmi_send_sysreset(qts, RPMI_SYSRST_TYPE_COLD_REBOOT, + RPMI_MSG_POSTED_REQUEST); + qtest_qmp_eventwait(qts, "SHUTDOWN"); + qtest_quit(qts); +} + +static void test_rpmi_sysreset_invalid_type(void) +{ + QTestState *qts; + + qts =3D qtest_init("-machine virt,rpmi=3Don"); + rpmi_send_sysreset(qts, RPMI_SYSRST_TYPE_INVALID, + RPMI_MSG_NORMAL_REQUEST); + + rpmi_expect_ack(qts, RPMI_SRVGRP_SYSTEM_RESET, + RPMI_SYSRST_SRV_SYSTEM_RESET, sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, + RPMI_ERR_INVALID_PARAM); + + qtest_quit(qts); +} + +static void test_rpmi_repeated_reset_after_traffic(void) +{ + QTestState *qts; + uint32_t reset_type =3D RPMI_SYSRST_TYPE_SHUTDOWN; + + qts =3D qtest_init("-machine virt,rpmi=3Don,aia=3Daplic-imsic"); + for (uint32_t i =3D 0; i < 5; i++) { + rpmi_send_request(qts, RPMI_SRVGRP_SYSTEM_RESET, + RPMI_SYSRST_SRV_GET_ATTRIBUTES, + RPMI_MSG_NORMAL_REQUEST, + &reset_type, 1); + rpmi_expect_ack(qts, RPMI_SRVGRP_SYSTEM_RESET, + RPMI_SYSRST_SRV_GET_ATTRIBUTES, + 2 * sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + qtest_system_reset(qts); + } + qtest_quit(qts); +} + +static void test_rpmi_reset_clears_transport(void) +{ + QTestState *qts; + + qts =3D qtest_init("-machine virt,rpmi=3Don"); + rpmi_send_sysreset(qts, RPMI_SYSRST_TYPE_INVALID, + RPMI_MSG_NORMAL_REQUEST); + rpmi_expect_ack(qts, RPMI_SRVGRP_SYSTEM_RESET, + RPMI_SYSRST_SRV_SYSTEM_RESET, sizeof(uint32_t)); + + qtest_system_reset(qts); + + g_assert_cmphex(qtest_readl(qts, RPMI_A2P_TAIL), =3D=3D, 0); + g_assert_cmphex(qtest_readl(qts, RPMI_P2A_ACK_TAIL), =3D=3D, 0); + g_assert_cmphex(qtest_readl(qts, RPMI_DOORBELL_BASE), =3D=3D, 0); + + qtest_quit(qts); +} + +static void test_rpmi_doorbell_invalid_access(void) +{ + QTestState *qts; + + qts =3D qtest_init("-machine virt,rpmi=3Don"); + qtest_writeb(qts, RPMI_DOORBELL_BASE, 1); + qtest_writel(qts, RPMI_DOORBELL_BASE + 4, 1); + g_assert_cmphex(qtest_readl(qts, RPMI_DOORBELL_BASE), =3D=3D, 0); + + qtest_quit(qts); +} + +static void test_rpmi_queue_bounds(void) +{ + QTestState *qts; + + qts =3D qtest_init("-machine virt,rpmi=3Don"); + qtest_writel(qts, RPMI_A2P_TAIL, 0x1000); + qtest_writel(qts, RPMI_DOORBELL_BASE, 1); + g_assert_cmphex(qtest_readl(qts, RPMI_A2P_HEAD), =3D=3D, 0); + g_assert_cmphex(qtest_readl(qts, RPMI_P2A_ACK_TAIL), =3D=3D, 0); + + qtest_quit(qts); +} + +static void test_rpmi_migration_blocked(void) +{ + QTestState *qts; + QDict *error; + const char *desc; + + qts =3D qtest_init("-machine virt,rpmi=3Don -S"); + error =3D qtest_qmp_assert_failure_ref(qts, + "{ 'execute': 'migrate'," + " 'arguments': { 'uri': 'exec:cat > /dev/null' } }"); + desc =3D qdict_get_try_str(error, "desc"); + + g_assert_nonnull(desc); + g_assert_nonnull(strstr(desc, "non-migratable device")); + g_assert_nonnull(strstr(desc, "riscv-rpmi")); + + qobject_unref(error); + qtest_quit(qts); +} + +static void test_rpmi_hsm_hart_list(void) +{ + QTestState *qts; + uint32_t start_index =3D 0; + + qts =3D qtest_init("-machine virt,rpmi=3Don -smp 4"); + rpmi_send_request(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_GET_HART_LIST, + RPMI_MSG_NORMAL_REQUEST, &start_index, 1); + + rpmi_expect_ack(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_GET_HART_LIST, + 7 * sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 1), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 2), =3D=3D, 4); + g_assert_cmphex(rpmi_response_word(qts, 3), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 4), =3D=3D, 1); + g_assert_cmphex(rpmi_response_word(qts, 5), =3D=3D, 2); + g_assert_cmphex(rpmi_response_word(qts, 6), =3D=3D, 3); + + qtest_quit(qts); +} + +static void test_rpmi_hsm_multi_socket_hart_list(void) +{ + QTestState *qts; + uint32_t start_index =3D 0; + + qts =3D qtest_init("-machine virt,rpmi=3Don " + "-smp 4,sockets=3D2,cores=3D2,threads=3D1"); + rpmi_send_request(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_GET_HART_LIST, + RPMI_MSG_NORMAL_REQUEST, &start_index, 1); + + rpmi_expect_ack(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_GET_HART_LIST, + 7 * sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 1), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 2), =3D=3D, 4); + g_assert_cmphex(rpmi_response_word(qts, 3), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 4), =3D=3D, 1); + g_assert_cmphex(rpmi_response_word(qts, 5), =3D=3D, 2); + g_assert_cmphex(rpmi_response_word(qts, 6), =3D=3D, 3); + + qtest_quit(qts); +} + +static void test_rpmi_hsm_hart_status(void) +{ + QTestState *qts; + uint32_t hart_id =3D 3; + + qts =3D qtest_init("-machine virt,rpmi=3Don -smp 4"); + rpmi_send_request(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_GET_HART_STATUS, + RPMI_MSG_NORMAL_REQUEST, &hart_id, 1); + + rpmi_expect_ack(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_GET_HART_STATUS, + 2 * sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 1), =3D=3D, + RPMI_HSM_HART_STATE_STARTED); + + qtest_quit(qts); +} + +static void rpmi_expect_hsm_status(QTestState *qts, uint32_t hart_id, + uint32_t expected_state) +{ + rpmi_send_request(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_GET_HART_STATUS, + RPMI_MSG_NORMAL_REQUEST, &hart_id, 1); + rpmi_expect_ack(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_GET_HART_STATUS, + 2 * sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 1), =3D=3D, expected_state); +} + +static uint64_t rpmi_hart_pc(QTestState *qts, uint32_t cpu_index) +{ + g_autofree char *registers =3D qtest_hmp(qts, "info registers %u", + cpu_index); + const char *pc_line; + uint64_t pc; + + pc_line =3D strstr(registers, "\n pc"); + g_assert_nonnull(pc_line); + g_assert_cmpint(sscanf(pc_line, "\n pc %" SCNx64, &pc), =3D=3D, 1); + + return pc; +} + +static void test_rpmi_hsm_hart_control(void) +{ + QTestState *qts; + uint32_t hart_id =3D 1; + uint32_t stop_request[] =3D { hart_id }; + uint32_t start_request[] =3D { hart_id, RPMI_HSM_TEST_START_ADDR, 0 }; + uint32_t suspend_request[] =3D { hart_id, 0, RPMI_HSM_TEST_RESUME_ADDR= , 0 }; + uint32_t start_index =3D 0; + uint32_t suspend_type =3D 0; + + qts =3D qtest_init("-machine virt,rpmi=3Don -smp 2"); + rpmi_send_request(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_GET_SUSPEND_TYPES, + RPMI_MSG_NORMAL_REQUEST, &start_index, 1); + rpmi_expect_ack(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_GET_SUSPEND_TYPES, + 4 * sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 1), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 2), =3D=3D, 1); + g_assert_cmphex(rpmi_response_word(qts, 3), =3D=3D, 0); + + qtest_system_reset(qts); + rpmi_send_request(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_GET_SUSPEND_INFO, + RPMI_MSG_NORMAL_REQUEST, &suspend_type, 1); + rpmi_expect_ack(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_GET_SUSPEND_INFO, + 6 * sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + + qtest_system_reset(qts); + rpmi_send_request(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_HART_STOP, + RPMI_MSG_NORMAL_REQUEST, stop_request, + ARRAY_SIZE(stop_request)); + rpmi_expect_ack(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_HART_STOP, + sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + rpmi_expect_hsm_status(qts, hart_id, RPMI_HSM_HART_STATE_STOPPED); + + rpmi_send_request(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_HART_START, + RPMI_MSG_NORMAL_REQUEST, start_request, + ARRAY_SIZE(start_request)); + rpmi_expect_ack(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_HART_START, + sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + rpmi_expect_hsm_status(qts, hart_id, RPMI_HSM_HART_STATE_STARTED); + g_assert_cmphex(rpmi_hart_pc(qts, hart_id), =3D=3D, RPMI_HSM_TEST_STAR= T_ADDR); + + rpmi_send_request(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_HART_SUSPEND, + RPMI_MSG_NORMAL_REQUEST, suspend_request, + ARRAY_SIZE(suspend_request)); + rpmi_expect_ack(qts, RPMI_SRVGRP_HSM, RPMI_HSM_SRV_HART_SUSPEND, + sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + rpmi_expect_hsm_status(qts, hart_id, RPMI_HSM_HART_STATE_SUSPENDED); + + qtest_quit(qts); +} + +static void test_rpmi_syssusp_attrs_and_suspend(void) +{ + QTestState *qts; + uint32_t suspend_type =3D 0; + uint32_t suspend_request[] =3D { 0, 0, 0x80000000, 0 }; + + qts =3D qtest_init("-machine virt,rpmi=3Don -smp 1"); + rpmi_send_request(qts, RPMI_SRVGRP_SYSTEM_SUSPEND, + RPMI_SYSSUSP_SRV_GET_ATTRIBUTES, + RPMI_MSG_NORMAL_REQUEST, &suspend_type, 1); + rpmi_expect_ack(qts, RPMI_SRVGRP_SYSTEM_SUSPEND, + RPMI_SYSSUSP_SRV_GET_ATTRIBUTES, + 2 * sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + g_assert_cmphex(rpmi_response_word(qts, 1), =3D=3D, 3); + + qtest_system_reset(qts); + rpmi_send_request(qts, RPMI_SRVGRP_SYSTEM_SUSPEND, + RPMI_SYSSUSP_SRV_SYSTEM_SUSPEND, + RPMI_MSG_NORMAL_REQUEST, suspend_request, + ARRAY_SIZE(suspend_request)); + rpmi_expect_ack(qts, RPMI_SRVGRP_SYSTEM_SUSPEND, + RPMI_SYSSUSP_SRV_SYSTEM_SUSPEND, sizeof(uint32_t)); + g_assert_cmphex(rpmi_response_word(qts, 0), =3D=3D, 0); + qtest_qmp_eventwait(qts, "SUSPEND"); + qtest_qmp_assert_success(qts, "{ 'execute': 'system_wakeup' }"); + qtest_qmp_eventwait(qts, "WAKEUP"); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + if (qtest_has_machine("virt")) { + qtest_add_func("/riscv/rpmi/machine/realize-off", + test_rpmi_machine_realize_off); + qtest_add_func("/riscv/rpmi/machine/rejects-too-many-harts", + test_rpmi_machine_rejects_too_many_harts); + qtest_add_func("/riscv/rpmi/base/platform-info", + test_rpmi_base_platform_info); + qtest_add_func("/riscv/rpmi/base/probe-service-groups", + test_rpmi_base_probe_service_groups); + qtest_add_func("/riscv/rpmi/sysreset/attrs", + test_rpmi_sysreset_attrs); + qtest_add_func("/riscv/rpmi/sysreset/shutdown", + test_rpmi_sysreset_shutdown); + qtest_add_func("/riscv/rpmi/sysreset/cold-reboot", + test_rpmi_sysreset_cold_reboot); + qtest_add_func("/riscv/rpmi/sysreset/invalid-type", + test_rpmi_sysreset_invalid_type); + qtest_add_func("/riscv/rpmi/reset/clears-transport", + test_rpmi_reset_clears_transport); + qtest_add_func("/riscv/rpmi/negative/doorbell-invalid-access", + test_rpmi_doorbell_invalid_access); + qtest_add_func("/riscv/rpmi/negative/queue-bounds", + test_rpmi_queue_bounds); + qtest_add_func("/riscv/rpmi/reset/repeated-after-traffic", + test_rpmi_repeated_reset_after_traffic); + qtest_add_func("/riscv/rpmi/migration/blocked", + test_rpmi_migration_blocked); + qtest_add_func("/riscv/rpmi/hsm/hart-list", + test_rpmi_hsm_hart_list); + qtest_add_func("/riscv/rpmi/hsm/multi-socket-hart-list", + test_rpmi_hsm_multi_socket_hart_list); + qtest_add_func("/riscv/rpmi/hsm/hart-status", + test_rpmi_hsm_hart_status); + qtest_add_func("/riscv/rpmi/hsm/hart-control", + test_rpmi_hsm_hart_control); + qtest_add_func("/riscv/rpmi/syssusp/attrs-and-suspend", + test_rpmi_syssusp_attrs_and_suspend); + } + + return g_test_run(); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=subrahmanya.lingappa@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789622745180158500 Content-Type: text/plain; charset="utf-8" Boot an RPMI-enabled RISC-V virt guest and exercise the initial HSM, system suspend, and system reset paths. Signed-off-by: Subrahmanya Lingappa --- tests/functional/riscv64/meson.build | 2 + tests/functional/riscv64/test_rpmi_virt.py | 184 +++++++++++++++++++++ 2 files changed, 186 insertions(+) create mode 100644 tests/functional/riscv64/test_rpmi_virt.py diff --git a/tests/functional/riscv64/meson.build b/tests/functional/riscv6= 4/meson.build index d1a3e6c2bf..1b35ba8cd7 100644 --- a/tests/functional/riscv64/meson.build +++ b/tests/functional/riscv64/meson.build @@ -4,6 +4,7 @@ test_riscv64_timeouts =3D { 'boston' : 120, 'k230' : 120, 'tuxrun' : 120, + 'rpmi_virt' : 300, } =20 tests_riscv64_system_quick =3D [ @@ -18,4 +19,5 @@ tests_riscv64_system_thorough =3D [ 'sifive_u', 'tt_atlantis', 'tuxrun', + 'rpmi_virt', ] diff --git a/tests/functional/riscv64/test_rpmi_virt.py b/tests/functional/= riscv64/test_rpmi_virt.py new file mode 100644 index 0000000000..831895103c --- /dev/null +++ b/tests/functional/riscv64/test_rpmi_virt.py @@ -0,0 +1,184 @@ +#!/usr/bin/env python3 +# +# RISC-V virt RPMI Linux guest integration tests +# +# Copyright (c) 2026 Qualcomm Technologies, Inc. +# +# Author: +# Subrahmanya Lingappa +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import os +from pathlib import Path +import subprocess +import time + +from qemu_test import QemuSystemTest +from qemu_test import exec_command +from qemu_test import exec_command_and_wait_for_pattern +from qemu_test import get_qemu_img +from qemu_test import wait_for_console_pattern + + +class RiscvVirtRpmiGuestTest(QemuSystemTest): + """Boot Linux and exercise RPMI-backed services through guest APIs. + + This test intentionally keeps guest artifacts external. Set: + + QEMU_TEST_RPMI_OPENSBI=3D/path/to/fw_jump.bin + QEMU_TEST_RPMI_KERNEL=3D/path/to/Image + QEMU_TEST_RPMI_ROOTFS=3D/path/to/rootfs.ext4 + + Exact RPMI packet command-ID coverage remains in riscv-rpmi qtests. Th= is + functional test verifies Linux/OpenSBI integration paths visible from a + real guest without adding probe hooks to production RPMI sources. + """ + + timeout =3D 360 + PROMPT =3D 'root@tuxtest:~#' + + def _require_path(self, env_name): + value =3D os.getenv(env_name) + if not value: + self.skipTest(f'{env_name} is required') + path =3D Path(value) + if not path.exists(): + self.skipTest(f'{env_name} does not exist: {path}') + return path + + def setUp(self): + super().setUp() + self.opensbi =3D self._require_path('QEMU_TEST_RPMI_OPENSBI') + self.kernel =3D self._require_path('QEMU_TEST_RPMI_KERNEL') + self.rootfs =3D self._require_path('QEMU_TEST_RPMI_ROOTFS') + self.qemu_img =3D get_qemu_img(self) + + def _create_rootfs_overlay(self): + overlay =3D Path(self.scratch_file('rootfs.qcow2')) + subprocess.run([ + self.qemu_img, 'create', '-q', '-f', 'qcow2', '-F', 'raw', + '-b', str(self.rootfs), str(overlay), + ], check=3DTrue) + return overlay + + def _boot_guest(self, smp=3D4): + self.set_machine('virt') + self.machine =3D 'virt,rpmi=3Don,aia=3Daplic-imsic' + rootfs_overlay =3D self._create_rootfs_overlay() + + self.vm.set_console() + self.vm.add_args( + '-cpu', 'rv64', + '-smp', str(smp), + '-m', '1G', + '-bios', str(self.opensbi), + '-kernel', str(self.kernel), + '-append', 'printk.time=3D0 root=3D/dev/vda rw console=3DttyS0= ' + 'earlycon=3Dsbi loglevel=3D8 no_console_suspend', + '-blockdev', 'driver=3Dqcow2,file.driver=3Dfile,' + f'file.filename=3D{rootfs_overlay},node-name=3Dhd= 0', + '-device', 'virtio-blk-device,drive=3Dhd0', + ) + self.vm.launch() + + def _expect_rpmi_firmware_and_linux(self): + patterns =3D [ + 'Platform HSM Device : rpmi-hsm', + 'Platform Reboot Device : rpmi-system-reset', + 'Platform Shutdown Device : rpmi-system-reset', + 'Platform Suspend Device : rpmi-system-suspend', + 'Standard SBI Extensions', + 'susp', + 'tuxtest login:', + ] + for pattern in patterns: + wait_for_console_pattern(self, pattern) + exec_command_and_wait_for_pattern(self, 'root', self.PROMPT) + + def _run_marker_command(self, command, marker, failure_marker=3DNone): + out =3D exec_command_and_wait_for_pattern(self, command, marker, + failure_message=3Dfailure_= marker) + self.assertIn(marker.encode(), out) + return out + + def _validate_hsm_boot_start(self, online_cpus): + self._run_marker_command( + 'echo RPMI_LINUX_HSM_START_BEGIN; ' + 'cat /sys/devices/system/cpu/present; ' + 'online=3D$(cat /sys/devices/system/cpu/online); ' + 'echo "$online"; ' + f'if [ "$online" =3D "{online_cpus}" ]; ' + 'then echo RPMI_LINUX_HSM_START_PASS; ' + 'else echo RPMI_LINUX_HSM_START_FAIL; fi', + 'RPMI_LINUX_HSM_START_PASS', 'RPMI_LINUX_HSM_START_FAIL') + + def _validate_hsm_stop(self): + self._run_marker_command( + 'echo RPMI_LINUX_HSM_STOP_BEGIN; ' + 'if [ -w /sys/devices/system/cpu/cpu1/online ]; then ' + 'echo 0 > /sys/devices/system/cpu/cpu1/online && ' + '[ "$(cat /sys/devices/system/cpu/online)" =3D 0 ] && ' + 'echo RPMI_LINUX_HSM_STOP_PASS || echo RPMI_LINUX_HSM_STOP_FAI= L; ' + 'else echo RPMI_LINUX_HSM_STOP_FAIL; fi', + 'RPMI_LINUX_HSM_STOP_PASS', 'RPMI_LINUX_HSM_STOP_FAIL') + + def _validate_system_suspend(self): + exec_command( + self, + 'echo RPMI_LINUX_SUSPEND_BEGIN; ' + 'if grep -qw mem /sys/power/state; then ' + 'echo mem > /sys/power/state; ' + 'else echo RPMI_LINUX_SUSPEND_FAIL; fi') + wait_for_console_pattern(self, 'RPMI_LINUX_SUSPEND_BEGIN') + wait_for_console_pattern(self, 'PM: suspend entry') + self.vm.event_wait('SUSPEND', 10) + self.vm.qmp('system_wakeup') + self.vm.event_wait('WAKEUP', 10) + wait_for_console_pattern(self, 'PM: suspend exit') + wait_for_console_pattern(self, self.PROMPT) + self._run_marker_command( + 'marker=3DRPMI_LINUX_WAKEUP; echo ${marker}_PASS', + 'RPMI_LINUX_WAKEUP_PASS') + + def _validate_reset_poweroff(self): + exec_command(self, 'echo RPMI_LINUX_RESET_POWEROFF_BEGIN; poweroff= -f') + wait_for_console_pattern(self, 'RPMI_LINUX_RESET_POWEROFF_BEGIN') + wait_for_console_pattern(self, 'reboot: Power down') + self.vm.wait() + + def _validate_reset_reboot(self): + exec_command(self, 'echo RPMI_LINUX_RESET_REBOOT_BEGIN; reboot -f') + wait_for_console_pattern(self, 'RPMI_LINUX_RESET_REBOOT_BEGIN') + wait_for_console_pattern(self, 'reboot: Restarting system') + wait_for_console_pattern(self, 'OpenSBI') + + def test_linux_guest_service_enumeration(self): + self._boot_guest(smp=3D4) + self._expect_rpmi_firmware_and_linux() + self._validate_hsm_boot_start('0-3') + + def test_linux_guest_hsm_stop(self): + self._boot_guest(smp=3D2) + self._expect_rpmi_firmware_and_linux() + self._validate_hsm_boot_start('0-1') + self._validate_hsm_stop() + + def test_linux_guest_suspend(self): + self._boot_guest(smp=3D1) + self._expect_rpmi_firmware_and_linux() + self._validate_system_suspend() + + def test_linux_guest_reset_poweroff(self): + self._boot_guest(smp=3D1) + self._expect_rpmi_firmware_and_linux() + self._validate_reset_poweroff() + + def test_linux_guest_reset_reboot(self): + self._boot_guest(smp=3D1) + self._expect_rpmi_firmware_and_linux() + self._validate_reset_reboot() + + +if __name__ =3D=3D '__main__': + QemuSystemTest.main()