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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c105::7; envelope-from=tdave@nvidia.com; helo=CH4PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1789585055905158500 Content-Type: text/plain; charset="utf-8" Add fixed-bar-N properties to PCIDevice to allow the guest address of an individual PCI BAR to be explicitly specified. The properties are available for PCI BARs 0 through 5 and accept QEMU size values, for example fixed-bar-0=3D0x40000000 or fixed-bar-0=3D64G. e.g. -device some-device,fixed-bar-0=3D[,fixed-bar-1=3D]... During realize, validate that each specified BAR exists and is a memory BAR, and reject fixed BAR configuration for hot-plugged devices. Signed-off-by: Tushar Dave --- hw/pci/pci.c | 43 +++++++++++++++++++++++++++++++++++++ include/hw/pci/pci_device.h | 7 ++++++ 2 files changed, 50 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 0efb4eb4bb..775fef1beb 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -89,6 +89,12 @@ static const Property pci_props[] =3D { DEFINE_PROP_STRING("romfile", PCIDevice, romfile), DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, UINT32_MAX), DEFINE_PROP_INT32("rombar", PCIDevice, rom_bar, -1), + DEFINE_PROP_SIZE("fixed-bar-0", PCIDevice, fixed_bar_addr[0], PCI_BAR_= UNMAPPED), + DEFINE_PROP_SIZE("fixed-bar-1", PCIDevice, fixed_bar_addr[1], PCI_BAR_= UNMAPPED), + DEFINE_PROP_SIZE("fixed-bar-2", PCIDevice, fixed_bar_addr[2], PCI_BAR_= UNMAPPED), + DEFINE_PROP_SIZE("fixed-bar-3", PCIDevice, fixed_bar_addr[3], PCI_BAR_= UNMAPPED), + DEFINE_PROP_SIZE("fixed-bar-4", PCIDevice, fixed_bar_addr[4], PCI_BAR_= UNMAPPED), + DEFINE_PROP_SIZE("fixed-bar-5", PCIDevice, fixed_bar_addr[5], PCI_BAR_= UNMAPPED), DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, @@ -228,6 +234,36 @@ static void pci_bus_unrealize(BusState *qbus) vmstate_unregister(NULL, &vmstate_pcibus, bus); } =20 +static void pci_check_fixed_bars(PCIDevice *pci_dev, Error **errp) +{ + PCIIORegion *r; + int i; + + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + if (pci_dev->fixed_bar_addr[i] =3D=3D PCI_BAR_UNMAPPED) { + continue; + } + + if (DEVICE(pci_dev)->hotplugged) { + error_setg(errp, "fixed-bar-%d is not supported on " + "hot-plugged devices", i); + return; + } + + r =3D &pci_dev->io_regions[i]; + if (!r->size) { + error_setg(errp, "fixed-bar-%d: bar%d does not exist on %s", + i, i, pci_dev->name); + return; + } + if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { + error_setg(errp, "fixed-bar-%d: bar%d on %s is an I/O BAR, " + "not a memory BAR", i, i, pci_dev->name); + return; + } + } +} + static int pcibus_num(PCIBus *bus) { if (pci_bus_is_root(bus)) { @@ -2393,6 +2429,13 @@ static void pci_qdev_realize(DeviceState *qdev, Erro= r **errp) is_default_rom =3D true; } =20 + pci_check_fixed_bars(pci_dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + pci_qdev_unrealize(DEVICE(pci_dev)); + return; + } + pci_add_option_rom(pci_dev, is_default_rom, &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index 5cac6e1688..fc5f50a1c4 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -187,6 +187,13 @@ struct PCIDevice { uint32_t max_bounce_buffer_size; =20 char *sriov_pf; + + /* + * fixed_bar_addr[N] holds the guest address configured via the + * fixed-bar-N property for memory BAR N. PCI_BAR_UNMAPPED means + * the BAR's address is not fixed. + */ + uint64_t fixed_bar_addr[PCI_NUM_REGIONS - 1]; }; =20 static inline int pci_intx(PCIDevice *pci_dev) --=20 2.34.1 From nobody Sat Sep 26 22:15:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1789585024; cv=pass; d=zohomail.com; s=zohoarc; b=D4x1v2RTT32rd2Ho/UbO/ldaKsQoVH3QJnS5pDn59gMGE83K8GYaCj82R34AkrM5hMwHj7MLS1ddVb6YyCbotDGm0wmLEWGSyQiNhrVQyaQF6GvEzGHtCLcVm3cBJtCN/wl9a4mgP6eW5i89ifUbfD/WeH+RsRtzxvAXcr1kD4I= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789585024; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c110::1; envelope-from=tdave@nvidia.com; helo=BN1PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1789585026435158500 Validate the fixed BAR configuration specified through the fixed-bar-N properties on PCI endpoint devices. Configuring any fixed-bar-N property on an endpoint device requires every memory BAR on that device to have a fixed address. Validate that each assigned address: - is aligned to its BAR size; - is within the appropriate PCIe MMIO aperture; and - does not overlap any other fixed BAR. Under a PCIe topology with a root port, fixed BAR placement is all-or-nothing within that root port's subtree. If any one endpoint device below the root port has a fixed BAR, every other endpoint device below that same root port with a memory BAR must have all of its memory BARs fixed too. Endpoint devices with no root port in their ancestry, such as those attached directly to the host bridge, are not required to match their sibling devices. One such device may use fixed-bar-N for all of its memory BARs while another sibling device on the same host bridge uses none at all. Per-device completeness still applies regardless of ancestry. Once any fixed-bar-N property is set on a device, every memory BAR on that device must be fixed. Abort QEMU if any validation fails. Signed-off-by: Tushar Dave --- hw/pci/meson.build | 1 + hw/pci/pci-fixed-bar-validate.c | 326 ++++++++++++++++++++++++++++++++ hw/pci/pci-fixed-bar-validate.h | 21 ++ 3 files changed, 348 insertions(+) create mode 100644 hw/pci/pci-fixed-bar-validate.c create mode 100644 hw/pci/pci-fixed-bar-validate.h diff --git a/hw/pci/meson.build b/hw/pci/meson.build index 984c7327e5..150085c997 100644 --- a/hw/pci/meson.build +++ b/hw/pci/meson.build @@ -19,6 +19,7 @@ endif pci_ss.add(files('pcie.c', 'pcie_aer.c')) pci_ss.add(files('pcie_doe.c')) system_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pcie_port.c', 'p= cie_host.c')) +system_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pci-fixed-bar-va= lidate.c')) system_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss) =20 stub_ss.add(files('pci-stub.c')) diff --git a/hw/pci/pci-fixed-bar-validate.c b/hw/pci/pci-fixed-bar-validat= e.c new file mode 100644 index 0000000000..0b5baad8a0 --- /dev/null +++ b/hw/pci/pci-fixed-bar-validate.c @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved + * BAR address validation for fixed-BAR placement. + * + * Written by Tushar Dave + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pci_host.h" +#include "hw/pci/pcie_port.h" +#include "qemu/error-report.h" +#include "qemu/range.h" +#include "qemu/units.h" +#include "pci-internal.h" +#include "pci-fixed-bar-validate.h" + +/* + * Claimed BAR ranges =E2=80=94 detect inter-device and inter-hierarchy ov= erlaps + * across all fixed BARs system-wide. + */ + +typedef struct { + uint64_t start; + uint64_t end; + const char *owner; /* device name, for error messages */ + int bar; +} FixedClaim; + +static GArray *fixed_claims; + +static void fixed_claims_init(void) +{ + if (fixed_claims) { + g_array_free(fixed_claims, true); + } + fixed_claims =3D g_array_new(false, true, sizeof(FixedClaim)); +} + +static void fixed_claims_free(void) +{ + g_array_free(fixed_claims, true); + fixed_claims =3D NULL; +} + +static bool fixed_claims_overlap(uint64_t start, uint64_t end, + const char **owner_out, int *bar_out, + uint64_t *start_out, uint64_t *end_out) +{ + FixedClaim *c; + guint i; + + for (i =3D 0; i < fixed_claims->len; i++) { + c =3D &g_array_index(fixed_claims, FixedClaim, i); + if (ranges_overlap(start, end - start + 1, + c->start, c->end - c->start + 1)) { + *owner_out =3D c->owner; + *bar_out =3D c->bar; + *start_out =3D c->start; + *end_out =3D c->end; + return true; + } + } + return false; +} + +static void fixed_claims_add(uint64_t start, uint64_t end, + const char *owner, int bar) +{ + FixedClaim cl; + + cl.start =3D start; + cl.end =3D end; + cl.owner =3D owner; + cl.bar =3D bar; + g_array_append_val(fixed_claims, cl); +} + +static bool validate_bars(PCIDevice *pdev, FixedBarsInfo *info, + bool is_fixed_subtree) +{ + const char *devname =3D DEVICE(pdev)->id ? DEVICE(pdev)->id : pdev->n= ame; + const char *overlap_owner; + const char *wname; + bool has_fixed_bars =3D false; + bool is_64bit; + uint64_t addr, end, wbase, wlim, overlap_start, overlap_end; + PCIIORegion *r; + int overlap_bar; + int i; + + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + if (pdev->fixed_bar_addr[i] !=3D PCI_BAR_UNMAPPED) { + has_fixed_bars =3D true; + break; + } + } + + if (is_fixed_subtree && !has_fixed_bars) { + error_report("fixed-bar: %s [%02x:%02x.%x] under fixed-bar root " + "port has memory BARs but no fixed-bar-N=3D specified= ", + devname, pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); + exit(1); + } + + if (!has_fixed_bars) { + return false; + } + + /* Completeness: every memory BAR must have an address. */ + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + r =3D &pdev->io_regions[i]; + if (!r->size || (r->type & PCI_BASE_ADDRESS_SPACE_IO)) { + continue; + } + if (pdev->fixed_bar_addr[i] =3D=3D PCI_BAR_UNMAPPED) { + error_report("fixed-bar: %s [%02x:%02x.%x] BAR%d " + "missing a fixed-bar-N=3D value", + devname, pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), i); + exit(1); + } + } + + /* Per-BAR checks: alignment, MMIO window, overlap. */ + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + r =3D &pdev->io_regions[i]; + if (!r->size || (r->type & PCI_BASE_ADDRESS_SPACE_IO)) { + continue; + } + + is_64bit =3D !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); + addr =3D (uint64_t)pdev->fixed_bar_addr[i]; + + if (r->size - 1 > UINT64_MAX - addr) { + error_report("fixed-bar: %s [%02x:%02x.%x] BAR%d " + "addr=3D0x%"PRIx64" + size=3D0x%"PRIx64" overflow= s", + devname, pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), + i, addr, r->size); + exit(1); + } + end =3D addr + r->size - 1; + + if (is_64bit && !(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH) && + !pci_bus_is_root(pci_get_bus(pdev)) && addr >=3D 4 * GiB) { + error_report("fixed-bar: %s [%02x:%02x.%x] BAR%d is a " + "non-prefetchable 64-bit BAR behind a PCI bridge " + "and cannot be placed above 4GB", + devname, pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), i); + exit(1); + } + + /* + * wbase/wlim are both inclusive bounds (mmio*_limit =3D base+size= -1, + * set by the caller alongside mmio*_base), matching end's own + * inclusive computation above. + */ + if (is_64bit) { + wbase =3D info->mmio64_base; + wlim =3D info->mmio64_limit; + wname =3D "64-bit MMIO"; + } else { + wbase =3D info->mmio32_base; + wlim =3D info->mmio32_limit; + wname =3D "32-bit MMIO"; + } + + if (addr & (r->size - 1)) { + error_report("fixed-bar: %s [%02x:%02x.%x] BAR%d " + "addr=3D0x%"PRIx64" not aligned to size=3D0x%"PRI= x64, + devname, pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), + i, addr, r->size); + exit(1); + } + + if (addr < wbase || end > wlim) { + error_report("fixed-bar: %s [%02x:%02x.%x] BAR%d " + "[0x%"PRIx64"..0x%"PRIx64"] outside %s window " + "[0x%"PRIx64"..0x%"PRIx64"]", + devname, pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), + i, addr, end, wname, wbase, wlim); + exit(1); + } + + if (fixed_claims_overlap(addr, end, &overlap_owner, &overlap_bar, + &overlap_start, &overlap_end)) { + error_report("fixed-bar: %s [%02x:%02x.%x] BAR%d " + "[0x%"PRIx64"..0x%"PRIx64"] overlaps %s BAR%d " + "[0x%"PRIx64"..0x%"PRIx64"]", + devname, pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), + i, addr, end, overlap_owner, overlap_bar, + overlap_start, overlap_end); + exit(1); + } + + fixed_claims_add(addr, end, devname, i); + } + + return true; +} + +typedef struct { + FixedBarsInfo *info; + bool is_fixed_subtree; +} ScanState; + +static void scan_bus(PCIBus *bus, ScanState *state); + +static void mark_if_fixed(PCIBus *bus, PCIDevice *pdev, void *opaque) +{ + bool *found =3D opaque; + PCIBus *sec; + int i; + + if (*found) { + return; + } + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + if (pdev->fixed_bar_addr[i] !=3D PCI_BAR_UNMAPPED) { + *found =3D true; + return; + } + } + if (object_dynamic_cast(OBJECT(pdev), TYPE_PCI_BRIDGE)) { + sec =3D pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); + if (sec) { + pci_for_each_device_under_bus(sec, mark_if_fixed, found); + } + } +} + +/* + * True if any device in rp_bus's subtree (the bus behind a root port) + * has a fixed BAR. + */ +static bool root_port_subtree_has_fixed_bar(PCIBus *rp_bus) +{ + bool found =3D false; + + pci_for_each_device_under_bus(rp_bus, mark_if_fixed, &found); + return found; +} + +static void scan_bus_device(PCIBus *bus, PCIDevice *pdev, void *opaque) +{ + ScanState *state =3D opaque; + bool has_mem_bar =3D false; + PCIIORegion *r; + PCIBus *sec; + int i; + + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + r =3D &pdev->io_regions[i]; + if (r->size && !(r->type & PCI_BASE_ADDRESS_SPACE_IO)) { + has_mem_bar =3D true; + break; + } + } + + if (has_mem_bar) { + if (validate_bars(pdev, state->info, state->is_fixed_subtree)) { + state->info->any_fixed =3D true; + } + } + + if (!object_dynamic_cast(OBJECT(pdev), TYPE_PCI_BRIDGE)) { + return; + } + sec =3D pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); + if (!sec) { + return; + } + + if (object_dynamic_cast(OBJECT(pdev), TYPE_PCIE_ROOT_PORT)) { + ScanState child =3D { + .info =3D state->info, + .is_fixed_subtree =3D root_port_subtree_has_fixed_bar(sec), + }; + scan_bus(sec, &child); + } else { + scan_bus(sec, state); + } +} + +static void scan_bus(PCIBus *bus, ScanState *state) +{ + pci_for_each_device_under_bus(bus, scan_bus_device, state); +} + +static void scan_all_host_bridges(FixedBarsInfo *info) +{ + PCIHostState *hb; + ScanState state =3D { .info =3D info, .is_fixed_subtree =3D false }; + + fixed_claims_init(); + QLIST_FOREACH(hb, &pci_host_bridges, next) { + if (hb->bus) { + scan_bus(hb->bus, &state); + } + } + fixed_claims_free(); +} + +/* + * fixed_bars_validate - scan all PCI devices, validate fixed BAR addresse= s. + * + * @info: carries MMIO window bounds for validation. + * + * Returns true if any fixed BAR devices were found, false if there is + * nothing to do. Aborts on any validation error. + */ +bool fixed_bars_validate(FixedBarsInfo *info) +{ + info->any_fixed =3D false; + scan_all_host_bridges(info); + return info->any_fixed; +} diff --git a/hw/pci/pci-fixed-bar-validate.h b/hw/pci/pci-fixed-bar-validat= e.h new file mode 100644 index 0000000000..297d1480c0 --- /dev/null +++ b/hw/pci/pci-fixed-bar-validate.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved + * + * Written by Tushar Dave + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_PCI_FIXED_BAR_VALIDATE_H +#define HW_PCI_FIXED_BAR_VALIDATE_H + +typedef struct { + bool any_fixed; + uint64_t mmio32_base; + uint64_t mmio32_limit; + uint64_t mmio64_base; + uint64_t mmio64_limit; +} FixedBarsInfo; + +bool fixed_bars_validate(FixedBarsInfo *info); + +#endif /* HW_PCI_FIXED_BAR_VALIDATE_H */ --=20 2.34.1 From nobody Sat Sep 26 22:15:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1789585087; cv=pass; d=zohomail.com; s=zohoarc; b=DSm0hxeNT4+6XJ7AyGpa5DL1umPpsqIpHKgba7unopJo1vDjjRc4akE5kMp5ZhZ2PibWDVpjv32tJidZEzLIQhv7/2He1YHCYOe+kgYcHgefU+5gAmLhQkawo+bUUCcAGX6FL1Rg/F3t4L5aHZEJvcj3D0G/SFVz545WD+F1UDM= ARC-Message-Signature: i=2; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c105::7; envelope-from=tdave@nvidia.com; helo=CH4PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1789585088190158500 Introduce a fixed BAR fw_cfg blob exporter that serializes PCI device and BAR information into the "etc/fixed-bars" fw_cfg file. The blob contains an entry for every PCI function with memory BARs. Each entry carries the device's vendor and device ID, whether it has a fixed BAR configuration, and its firmware device path. Fixed BAR entries also include the configured BAR address, size, and type information for each BAR. Signed-off-by: Tushar Dave --- hw/pci/meson.build | 1 + hw/pci/pci-fixed-bar-blob.c | 305 ++++++++++++++++++++++++++++++++++++ hw/pci/pci-fixed-bar.h | 63 ++++++++ 3 files changed, 369 insertions(+) create mode 100644 hw/pci/pci-fixed-bar-blob.c create mode 100644 hw/pci/pci-fixed-bar.h diff --git a/hw/pci/meson.build b/hw/pci/meson.build index 150085c997..b81cc056c0 100644 --- a/hw/pci/meson.build +++ b/hw/pci/meson.build @@ -20,6 +20,7 @@ pci_ss.add(files('pcie.c', 'pcie_aer.c')) pci_ss.add(files('pcie_doe.c')) system_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pcie_port.c', 'p= cie_host.c')) system_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pci-fixed-bar-va= lidate.c')) +system_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pci-fixed-bar-bl= ob.c')) system_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss) =20 stub_ss.add(files('pci-stub.c')) diff --git a/hw/pci/pci-fixed-bar-blob.c b/hw/pci/pci-fixed-bar-blob.c new file mode 100644 index 0000000000..b9fdc6b7d4 --- /dev/null +++ b/hw/pci/pci-fixed-bar-blob.c @@ -0,0 +1,305 @@ +/* + * Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved + * Write validated fixed-BAR device info to the etc/fixed-bars fw_cfg blob. + * + * Written by Tushar Dave + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/nvram/fw_cfg.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pci_host.h" +#include "hw/pci/pcie_port.h" +#include "hw/core/qdev.h" +#include "qemu/error-report.h" +#include "pci-internal.h" +#include "pci-fixed-bar.h" +#include "pci-fixed-bar-validate.h" + +typedef struct { + uint8_t bar; + uint32_t flags; + uint64_t addr; + uint64_t size; +} BarInfo; + +/* One PCI function entry to be written to the blob. */ +typedef struct { + uint8_t rp_bus; /* primary bus of the root port this device is un= der */ + uint16_t vendor_id; + uint16_t device_id; + bool is_fixed; + char fw_path[QEMU_FIXED_BARS_MAX_PATH]; + GArray *bars; /* array of BarInfo */ +} DeviceInfo; + +typedef struct { + GArray *devices; + PCIBus *root_bus; +} CollectCtx; + +static void collect_device(PCIBus *bus, PCIDevice *pdev, void *opaque); + +/* Visit every device on this bus, in devfn order. */ +static void collect_bus(PCIBus *bus, void *opaque) +{ + pci_for_each_device_under_bus(bus, collect_device, opaque); +} + +/* + * Primary bus number of the nearest TYPE_PCIE_ROOT_PORT ancestor of bus + * =E2=80=94 i.e. the bus the root port device itself lives on, not its + * secondary bus. Falls back to the host bridge's own bus number if bus + * isn't under any root port (e.g. a device directly on the host + * bridge's primary bus). + */ +static uint8_t find_root_port_bus(PCIBus *bus, PCIBus *host_bus) +{ + PCIDevice *parent; + + while (bus) { + parent =3D bus->parent_dev; + if (!parent) { + break; + } + if (object_dynamic_cast(OBJECT(parent), TYPE_PCIE_ROOT_PORT)) { + return pci_bus_num(pci_get_bus(parent)); + } + bus =3D pci_get_bus(parent); + } + return pci_bus_num(host_bus); +} + +static void collect_device(PCIBus *bus, PCIDevice *pdev, void *opaque) +{ + CollectCtx *ctx =3D opaque; + bool has_mem_bar =3D false; + bool is_64bit, is_pref; + DeviceInfo dev; + PCIIORegion *r; + PCIBus *sec; + BarInfo bi; + int i; + + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + r =3D &pdev->io_regions[i]; + if (r->size && !(r->type & PCI_BASE_ADDRESS_SPACE_IO)) { + has_mem_bar =3D true; + break; + } + } + + /* + * Every device with a memory BAR gets an entry, fixed or not =E2=80= =94 not + * just ones with fixed-bar-N=3D set. This preserves the exact device + * sequence CheckDevice() needs for positional VID:DID matching (see + * collect_all_host_bridges()); only fixed devices carry BAR records + * (dev.bars stays empty, dev.is_fixed false, otherwise). + */ + if (has_mem_bar) { + g_autofree char *fw_path =3D qdev_get_fw_dev_path(DEVICE(pdev)); + + memset(&dev, 0, sizeof(dev)); + dev.rp_bus =3D find_root_port_bus(bus, ctx->root_bus); + dev.vendor_id =3D pci_get_word(pdev->config + PCI_VENDOR_ID); + dev.device_id =3D pci_get_word(pdev->config + PCI_DEVICE_ID); + dev.is_fixed =3D false; + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + if (pdev->fixed_bar_addr[i] !=3D PCI_BAR_UNMAPPED) { + dev.is_fixed =3D true; + break; + } + } + if (fw_path) { + g_strlcpy(dev.fw_path, fw_path, sizeof(dev.fw_path)); + } + dev.bars =3D g_array_new(false, true, sizeof(BarInfo)); + + if (dev.is_fixed) { + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + r =3D &pdev->io_regions[i]; + if (!r->size || (r->type & PCI_BASE_ADDRESS_SPACE_IO)) { + continue; + } + is_64bit =3D !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); + is_pref =3D !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); + + memset(&bi, 0, sizeof(bi)); + bi.bar =3D i; + bi.addr =3D (uint64_t)pdev->fixed_bar_addr[i]; + bi.size =3D r->size; + bi.flags =3D (is_64bit ? QEMU_FIXED_BAR_F_MEM64 : 0) | + (is_pref ? QEMU_FIXED_BAR_F_PREF : 0); + g_array_append_val(dev.bars, bi); + } + } + g_array_append_val(ctx->devices, dev); + } + + if (!object_dynamic_cast(OBJECT(pdev), TYPE_PCI_BRIDGE)) { + return; + } + sec =3D pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); + if (sec) { + collect_bus(sec, opaque); + } +} + +static gint cmp_host_bus_num(gconstpointer a, gconstpointer b) +{ + PCIHostState *ha =3D *(PCIHostState **)a; + PCIHostState *hb =3D *(PCIHostState **)b; + return (gint)pci_bus_num(ha->bus) - (gint)pci_bus_num(hb->bus); +} + +/* + * EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL's CheckDevice interface + * (UEFI PI Spec 1.2 Vol 5) only passes VendorId/DeviceId/RevisionId/ + * SubsystemVendorId/SubsystemDeviceId, no BDF =E2=80=94 so in EDK2 we can= 't + * match a blob entry to a specific device directly using BDF. To work + * around that, we prepare the blob entries in the same order PciBusDxe + * discovers devices, so matching by VID:DID inherently works. + */ +static void collect_all_host_bridges(CollectCtx *ctx) +{ + PCIHostState *hb; + GPtrArray *sorted; + guint i; + + sorted =3D g_ptr_array_new(); + QLIST_FOREACH(hb, &pci_host_bridges, next) { + if (hb->bus) { + g_ptr_array_add(sorted, hb); + } + } + g_ptr_array_sort(sorted, cmp_host_bus_num); + + for (i =3D 0; i < sorted->len; i++) { + hb =3D g_ptr_array_index(sorted, i); + ctx->root_bus =3D hb->bus; + collect_bus(hb->bus, ctx); + } + + g_ptr_array_free(sorted, true); +} + +static uint8_t *create_blob(CollectCtx *ctx, size_t *blob_size) +{ + QemuFixedBarsDevice *dout; + QemuFixedBarsBar *bout; + QemuFixedBarsHdr *hdr; + DeviceInfo *dev; + uint8_t *blob; + uint8_t *ptr; + BarInfo *bi; + size_t sz; + guint d, b; + + sz =3D sizeof(QemuFixedBarsHdr); + for (d =3D 0; d < ctx->devices->len; d++) { + dev =3D &g_array_index(ctx->devices, DeviceInfo, d); + sz +=3D sizeof(QemuFixedBarsDevice); + sz +=3D dev->bars->len * sizeof(QemuFixedBarsBar); + } + + blob =3D g_malloc0(sz); + hdr =3D (QemuFixedBarsHdr *)blob; + hdr->version =3D cpu_to_le32(QEMU_FIXED_BARS_VERSION); + hdr->num_devices =3D cpu_to_le32(ctx->devices->len); + + ptr =3D blob + sizeof(*hdr); + for (d =3D 0; d < ctx->devices->len; d++) { + dev =3D &g_array_index(ctx->devices, DeviceInfo, d); + dout =3D (QemuFixedBarsDevice *)ptr; + + dout->vendor_id =3D cpu_to_le16(dev->vendor_id); + dout->device_id =3D cpu_to_le16(dev->device_id); + dout->dev_flags =3D dev->is_fixed ? QEMU_FIXED_BARS_DEV_F_FIXED : = 0; + dout->rp_bus =3D dev->rp_bus; + dout->num_bars =3D dev->bars->len; + dout->reserved =3D 0; + memcpy(dout->fw_path, dev->fw_path, sizeof(dout->fw_path)); + ptr +=3D sizeof(QemuFixedBarsDevice); + + for (b =3D 0; b < dev->bars->len; b++) { + bi =3D &g_array_index(dev->bars, BarInfo, b); + bout =3D (QemuFixedBarsBar *)ptr; + + bout->bar =3D bi->bar; + bout->flags =3D cpu_to_le32(bi->flags); + bout->address =3D cpu_to_le64(bi->addr); + bout->size =3D cpu_to_le64(bi->size); + ptr +=3D sizeof(QemuFixedBarsBar); + } + } + + *blob_size =3D sz; + return blob; +} + +/* + * fixed_bars_write_blob - validate fixed BAR addresses and write fw_cfg b= lob. + * + * @fw_cfg: fw_cfg state to write the etc/fixed-bars blob into. + * @mmio32_base: base of the machine's 32-bit PCIe MMIO aperture. + * @mmio32_size: size of the machine's 32-bit PCIe MMIO aperture. + * @mmio64_base: base of the machine's 64-bit PCIe MMIO aperture. + * @mmio64_size: size of the machine's 64-bit PCIe MMIO aperture. + * + * Returns true if any fixed BAR device was found and the blob was + * written, false if there was nothing to do. Aborts if any BAR + * address fails validation. + */ +bool fixed_bars_write_blob(FWCfgState *fw_cfg, + uint64_t mmio32_base, + uint64_t mmio32_size, + uint64_t mmio64_base, + uint64_t mmio64_size) +{ + FixedBarsInfo info; + CollectCtx ctx; + uint8_t *blob; + size_t blob_size; + guint d; + + if (!mmio32_size || !mmio64_size) { + error_report("fixed-bar: zero-size PCIe MMIO aperture " + "(32-bit=3D0x%"PRIx64", 64-bit=3D0x%"PRIx64")", + mmio32_size, mmio64_size); + exit(1); + } + if (mmio32_size - 1 > UINT64_MAX - mmio32_base || + mmio64_size - 1 > UINT64_MAX - mmio64_base) { + error_report("fixed-bar: PCIe MMIO aperture base+size overflows " + "(32-bit base=3D0x%"PRIx64" size=3D0x%"PRIx64", " + "64-bit base=3D0x%"PRIx64" size=3D0x%"PRIx64")", + mmio32_base, mmio32_size, mmio64_base, mmio64_size); + exit(1); + } + + info.mmio32_base =3D mmio32_base; + info.mmio32_limit =3D mmio32_base + mmio32_size - 1; + info.mmio64_base =3D mmio64_base; + info.mmio64_limit =3D mmio64_base + mmio64_size - 1; + + if (!fixed_bars_validate(&info)) { + return false; + } + + ctx.devices =3D g_array_new(false, true, sizeof(DeviceInfo)); + ctx.root_bus =3D NULL; + collect_all_host_bridges(&ctx); + + blob =3D create_blob(&ctx, &blob_size); + fw_cfg_add_file(fw_cfg, FW_CFG_FIXED_BARS, blob, blob_size); + + for (d =3D 0; d < ctx.devices->len; d++) { + g_array_free(g_array_index(ctx.devices, DeviceInfo, d).bars, true); + } + g_array_free(ctx.devices, true); + + return true; +} diff --git a/hw/pci/pci-fixed-bar.h b/hw/pci/pci-fixed-bar.h new file mode 100644 index 0000000000..0d4e31b301 --- /dev/null +++ b/hw/pci/pci-fixed-bar.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved + * Fixed-BAR =E2=80=94 QEMU side declarations. + * + * Written by Tushar Dave + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_PCI_FIXED_BAR_H +#define HW_PCI_FIXED_BAR_H + +#include "hw/nvram/fw_cfg.h" +#include "hw/pci/pci_bus.h" + +#define FW_CFG_FIXED_BARS "etc/fixed-bars" +#define QEMU_FIXED_BARS_VERSION 1 +#define QEMU_FIXED_BARS_MAX_PATH 128 + +/* + * On-wire layout (little-endian, packed): + * + * QemuFixedBarsHdr + * + * For each device (num_devices total): + * QemuFixedBarsDevice -- device header + * QemuFixedBarsBar[num_bars] -- one record per BAR (FIXED only) + */ + +typedef struct { + uint32_t version; /* QEMU_FIXED_BARS_VERSION */ + uint32_t num_devices; +} QEMU_PACKED QemuFixedBarsHdr; /* 8 bytes */ + +typedef struct { + uint16_t vendor_id; + uint16_t device_id; + uint8_t dev_flags; /* QEMU_FIXED_BARS_DEV_F_* */ + uint8_t rp_bus; /* primary bus of the root port this device is un= der */ + uint8_t num_bars; + uint8_t reserved; + /* qdev_get_fw_dev_path(), NUL-terminated */ + char fw_path[QEMU_FIXED_BARS_MAX_PATH]; +} QEMU_PACKED QemuFixedBarsDevice; /* 8 + QEMU_FIXED_BARS_MAX_PATH bytes = */ + +typedef struct { + uint8_t bar; + uint8_t reserved[3]; + uint32_t flags; /* QEMU_FIXED_BAR_F_* */ + uint64_t address; + uint64_t size; +} QEMU_PACKED QemuFixedBarsBar; /* 24 bytes */ + +#define QEMU_FIXED_BAR_F_MEM64 (1u << 0) +#define QEMU_FIXED_BAR_F_PREF (1u << 1) +#define QEMU_FIXED_BARS_DEV_F_FIXED (1u << 0) + +bool fixed_bars_write_blob(FWCfgState *fw_cfg, + uint64_t mmio32_base, + uint64_t mmio32_size, + uint64_t mmio64_base, + uint64_t mmio64_size); + +#endif /* HW_PCI_FIXED_BAR_H */ --=20 2.34.1 From nobody Sat Sep 26 22:15:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; 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From: Tushar Dave To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, marcel@redhat.com, devel@edk2.groups.io, alwilliamson@nvidia.com, jgg@nvidia.com, skolothumtho@nvidia.com Subject: [PATCH 4/5] hw/arm/virt: export fixed BAR metadata via fw_cfg Date: Wed, 16 Sep 2026 13:55:53 -0500 Message-Id: <20260916185554.917526-5-tdave@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260916185554.917526-1-tdave@nvidia.com> References: <20260916185554.917526-1-tdave@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SA9PR13CA0174.namprd13.prod.outlook.com (2603:10b6:806:28::29) To IA3PR12MB923065.namprd12.prod.outlook.com (2603:10b6:208:627::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA3PR12MB923065:EE_|CY3PR12MB9631:EE_ X-MS-Office365-Filtering-Correlation-Id: ed978799-ed10-41c1-09f4-08df14242a5f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c110::1; envelope-from=tdave@nvidia.com; helo=BN1PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1789585052036158500 Content-Type: text/plain; charset="utf-8" Export fixed BAR metadata from the virt machine through the "etc/fixed-bars" fw_cfg file during machine initialization. Fixed BAR placement requires firmware to preserve the PCI resource configuration established by QEMU. ACPI provides this via the PCI boot configuration preservation mechanism, _DSM function 5. Reject fixed BAR configuration when ACPI is disabled, and request PCI boot configuration preservation when ACPI is enabled. Signed-off-by: Tushar Dave --- hw/arm/virt.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3eecf094bc..c5db663858 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -95,6 +95,7 @@ #include "hw/cxl/cxl_host.h" #include "qemu/guest-random.h" #include "hw/watchdog/sbsa_gwdt.h" +#include "hw/pci/pci-fixed-bar.h" =20 static GlobalProperty arm_virt_compat_defaults[] =3D { { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" }, @@ -2438,6 +2439,21 @@ void virt_machine_done(Notifier *notifier, void *dat= a) vms->memmap[VIRT_PLATFORM_BUS].size, vms->irqmap[VIRT_PLATFORM_BUS]); } + if (fixed_bars_write_blob(vms->fw_cfg, + vms->memmap[VIRT_PCIE_MMIO].base, + vms->memmap[VIRT_PCIE_MMIO].size, + vms->memmap[VIRT_HIGH_PCIE_MMIO].base, + vms->memmap[VIRT_HIGH_PCIE_MMIO].size)) { + if (!virt_is_acpi_enabled(vms)) { + error_report("fixed-bar: fixed BAR placement requires ACPI to " + "preserve the PCI boot configuration, otherwise " + "these BAR assignments could be reassigned later " + "with no protection"); + exit(1); + } + vms->pci_preserve_config =3D true; + } + if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) = < 0) { exit(1); } --=20 2.34.1 From nobody Sat Sep 26 22:15:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1789585081; cv=pass; d=zohomail.com; s=zohoarc; b=a+McFOejczs9NfxoIbllualHCL9h6LIdXxJySk5pJ+v4hz9zHV2iVz9a72Gogx6+Hb4uZSPhUEVSkXXtc8uNNv+bXnJixObdcklnUMYUVTlLQuiv1SAB/fOP4vlitxVYzqE6siz7Eud/DQPMCdx4Zq/jsU7nJ2BLudU+MlvePNE= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789585081; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c105::7; envelope-from=tdave@nvidia.com; helo=CH4PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1789585082190158500 Content-Type: text/plain; charset="utf-8" Add a highmem-mmio-base property to override the base of the virt machine's high PCIe MMIO window, alongside the existing highmem-mmio-size: -machine virt,highmem-mmio-base=3D,highmem-mmio-size=3D Some PCI devices require MMIO resources to be placed within a specific address range that cannot be satisfied by the default placement. The configured base is validated to be non-zero, aligned to highmem-mmio-size, non-overlapping with the existing high memory layout, and within the configured physical address space. Signed-off-by: Tushar Dave --- hw/arm/virt.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c5db663858..3a554dd26c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2513,9 +2513,34 @@ static void virt_set_high_memmap(VirtMachineState *v= ms, =20 for (i =3D VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { region_enabled =3D virt_get_high_memmap_enabled(vms, i); - region_base =3D ROUND_UP(base, extended_memmap[i].size); region_size =3D extended_memmap[i].size; =20 + if (i =3D=3D VIRT_HIGH_PCIE_MMIO && extended_memmap[i].base) { + region_base =3D extended_memmap[i].base; + + if (region_base < base) { + error_report("highmem-mmio-base 0x%"PRIx64" overlaps prior= " + "high memory layout (must be >=3D 0x%"PRIx64"= )", + region_base, base); + exit(1); + } + if (region_base % region_size !=3D 0) { + error_report("highmem-mmio-base 0x%"PRIx64" must be " + "aligned to highmem-mmio-size 0x%"PRIx64, + region_base, region_size); + exit(1); + } + if (region_base + region_size > BIT_ULL(pa_bits)) { + error_report("highmem-mmio-base + highmem-mmio-size " + "[0x%"PRIx64", 0x%"PRIx64") exceeds %d-bit PA= " + "space", region_base, + region_base + region_size, pa_bits); + exit(1); + } + } else { + region_base =3D ROUND_UP(base, region_size); + } + vms->memmap[i].base =3D region_base; vms->memmap[i].size =3D region_size; =20 @@ -3416,6 +3441,33 @@ static void virt_set_highmem_mmio_size(Object *obj, = Visitor *v, extended_memmap[VIRT_HIGH_PCIE_MMIO].size =3D size; } =20 +static void virt_get_highmem_mmio_base(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + uint64_t base =3D extended_memmap[VIRT_HIGH_PCIE_MMIO].base; + + visit_type_size(v, name, &base, errp); +} + +static void virt_set_highmem_mmio_base(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + uint64_t base; + + if (!visit_type_size(v, name, &base, errp)) { + return; + } + + if (base =3D=3D 0) { + error_setg(errp, "highmem-mmio-base cannot be 0"); + return; + } + + extended_memmap[VIRT_HIGH_PCIE_MMIO].base =3D base; +} + static char *virt_get_msi(Object *obj, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); @@ -4286,6 +4338,14 @@ static void virt_machine_class_init(ObjectClass *oc,= const void *data) "Set the high memory region size= " "for PCI MMIO"); =20 + object_class_property_add(oc, "highmem-mmio-base", "size", + virt_get_highmem_mmio_base, + virt_set_highmem_mmio_base, + NULL, NULL); + object_class_property_set_description(oc, "highmem-mmio-base", + "Set the high memory region base= " + "for PCI MMIO"); + object_class_property_add(oc, "virtio-mmio-transports", "uint8", virt_get_virtio_transports, virt_set_virtio_transports, --=20 2.34.1