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Mon, 14 Sep 2026 16:09:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@oss.qualcomm.com Subject: [PATCH 1/6] target/mips/tcg: Fix zero in gen_mxu_d8sum Date: Mon, 14 Sep 2026 13:08:53 -1000 Message-ID: <20260914230901.1781309-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260914230901.1781309-1-richard.henderson@linaro.org> References: <20260914230901.1781309-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::11; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x11.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789427414593158500 Content-Type: text/plain; charset="utf-8" This is obviously an attempt to set temps to 0, but accidentally passed NULL to a regular move. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/mxu_translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index 7961b073144..9559b8aada3 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -3109,7 +3109,7 @@ static void gen_mxu_d8sum(DisasContext *ctx, bool sum= c) tcg_gen_add_i32(t4, t4, t2); tcg_gen_add_i32(t4, t4, t3); } else { - tcg_gen_mov_i32(t4, 0); + tcg_gen_movi_i32(t4, 0); } if (XRc !=3D 0) { tcg_gen_extract_i32(t0, mxu_gpr[XRc - 1], 0, 8); @@ -3120,7 +3120,7 @@ static void gen_mxu_d8sum(DisasContext *ctx, bool sum= c) tcg_gen_add_i32(t5, t5, t2); tcg_gen_add_i32(t5, t5, t3); } else { - tcg_gen_mov_i32(t5, 0); + tcg_gen_movi_i32(t5, 0); } =20 if (sumc) { --=20 2.53.0 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 14 Sep 2026 16:09:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@oss.qualcomm.com Subject: [PATCH 2/6] target/mips/tcg: Drop zero optimization in gen_mxu_s32mul Date: Mon, 14 Sep 2026 13:08:54 -1000 Message-ID: <20260914230901.1781309-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260914230901.1781309-1-richard.henderson@linaro.org> References: <20260914230901.1781309-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789427404843158500 Content-Type: text/plain; charset="utf-8" In the unlikely event of the architecturally valid case of using the zero register as a multiply input, this will be folded away during optimize. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/mxu_translate.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index 9559b8aada3..f30883f976f 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -964,18 +964,13 @@ static void gen_mxu_s32mul(DisasContext *ctx, bool mu= lu) rs =3D extract32(ctx->opcode, 16, 5); rt =3D extract32(ctx->opcode, 21, 5); =20 - if (unlikely(rs =3D=3D 0 || rt =3D=3D 0)) { - tcg_gen_movi_i32(t0, 0); - tcg_gen_movi_i32(t1, 0); - } else { - gen_load_gpr(t0, rs); - gen_load_gpr(t1, rt); + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); =20 - if (mulu) { - tcg_gen_mulu2_i32(t0, t1, t0, t1); - } else { - tcg_gen_muls2_i32(t0, t1, t0, t1); - } + if (mulu) { + tcg_gen_mulu2_i32(t0, t1, t0, t1); + } else { + tcg_gen_muls2_i32(t0, t1, t0, t1); } tcg_gen_mov_i32(cpu_HI[0], t1); tcg_gen_mov_i32(cpu_LO[0], t0); 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Mon, 14 Sep 2026 16:09:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@oss.qualcomm.com Subject: [PATCH 3/6] target/mips/tcg: Split out gen_mxu_logic Date: Mon, 14 Sep 2026 13:08:55 -1000 Message-ID: <20260914230901.1781309-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260914230901.1781309-1-richard.henderson@linaro.org> References: <20260914230901.1781309-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::11; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x11.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789427406515158500 Content-Type: text/plain; charset="utf-8" Split out a helper for common expansion of a 3-operand insns. Drop all the special cases for 0 and let the optimizer handle them. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/mxu_translate.c | 122 +++++++------------------------- 1 file changed, 24 insertions(+), 98 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index f30883f976f..3f8acfcdb8f 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -1685,14 +1685,11 @@ static void gen_mxu_s32stxvx(DisasContext *ctx, boo= l reversed, * S32NOR S32AND S32OR S32XOR */ =20 -/* - * S32NOR XRa, XRb, XRc - * Update XRa with the result of logical bitwise 'nor' operation - * applied to the content of XRb and XRc. - */ -static void gen_mxu_S32NOR(DisasContext *ctx) +static void gen_mxu_logic(DisasContext *ctx, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) { uint32_t pad, XRc, XRb, XRa; + TCGv_i32 t0, t1; =20 pad =3D extract32(ctx->opcode, 21, 5); XRc =3D extract32(ctx->opcode, 14, 4); @@ -1701,24 +1698,25 @@ static void gen_mxu_S32NOR(DisasContext *ctx) =20 if (unlikely(pad !=3D 0)) { /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to all 1s = */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0xFFFFFFFF); - } else if (unlikely(XRb =3D=3D 0)) { - /* XRb zero register -> just set destination to the negation of XR= c */ - tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); - } else if (unlikely(XRc =3D=3D 0)) { - /* XRa zero register -> just set destination to the negation of XR= b */ - tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to the negation of X= Rb */ - tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - tcg_gen_nor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); + return; } + + t0 =3D tcg_temp_new_i32(); + t1 =3D tcg_temp_new_i32(); + gen_load_mxu_gpr(t0, XRb); + gen_load_mxu_gpr(t1, XRc); + gen(t0, t0, t1); + gen_store_mxu_gpr(t0, XRa); +} + +/* + * S32NOR XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'nor' operation + * applied to the content of XRb and XRc. + */ +static void gen_mxu_S32NOR(DisasContext *ctx) +{ + gen_mxu_logic(ctx, tcg_gen_nor_i32); } =20 /* @@ -1728,27 +1726,7 @@ static void gen_mxu_S32NOR(DisasContext *ctx) */ static void gen_mxu_S32AND(DisasContext *ctx) { - uint32_t pad, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { - /* one of operands zero register -> just set destination to all 0s= */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to one of them */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - tcg_gen_and_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); - } + gen_mxu_logic(ctx, tcg_gen_and_i32); } =20 /* @@ -1758,33 +1736,7 @@ static void gen_mxu_S32AND(DisasContext *ctx) */ static void gen_mxu_S32OR(DisasContext *ctx) { - uint32_t pad, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to all 0s = */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely(XRb =3D=3D 0)) { - /* XRb zero register -> just set destination to the content of XRc= */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); - } else if (unlikely(XRc =3D=3D 0)) { - /* XRc zero register -> just set destination to the content of XRb= */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to one of them */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1= ]); - } + gen_mxu_logic(ctx, tcg_gen_or_i32); } =20 /* @@ -1794,33 +1746,7 @@ static void gen_mxu_S32OR(DisasContext *ctx) */ static void gen_mxu_S32XOR(DisasContext *ctx) { - uint32_t pad, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to all 0s = */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely(XRb =3D=3D 0)) { - /* XRb zero register -> just set destination to the content of XRc= */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); - } else if (unlikely(XRc =3D=3D 0)) { - /* XRc zero register -> just set destination to the content of XRb= */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to all 0s */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else { - /* the most general case */ - tcg_gen_xor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); - } + gen_mxu_logic(ctx, tcg_gen_xor_i32); } =20 /* --=20 2.53.0 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789427413; cv=none; d=zohomail.com; s=zohoarc; b=S7Daji9YOWwNtdan56YqOAe3LB92FAa6DGucD8k9qUjQQSSq315nrEfaVyFrTBXYSdo2MmF4UCwX899YZ10mQ3kTqt+ksJcp2DOI6j60inGe6Bb971GOsOMU8UIgc+SdxXResSkhjx1+9wYt+tgnRcalMMY7fZixg1Xhcma0+6k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789427413; 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Mon, 14 Sep 2026 16:09:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@oss.qualcomm.com Subject: [PATCH 4/6] target/mips/tcg: Use gen_mxu_logic for gen_mxu_S32MAX_S32MIN Date: Mon, 14 Sep 2026 13:08:56 -1000 Message-ID: <20260914230901.1781309-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260914230901.1781309-1-richard.henderson@linaro.org> References: <20260914230901.1781309-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789427414635158500 Content-Type: text/plain; charset="utf-8" Split S32MAX, S32MIN to separate functions. Fixes a bug in that "0" was passed in one of the zero reg cases, aka NULL, instead of a proper zero constant. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/mxu_translate.c | 47 +++++++-------------------------- 1 file changed, 9 insertions(+), 38 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index 3f8acfcdb8f..4b2c264f031 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -2045,45 +2045,14 @@ static void gen_mxu_q16sxxv(DisasContext *ctx, bool= right, bool arithmetic) * Update XRa with the minimum of signed 32-bit integers contained * in XRb and XRc. */ -static void gen_mxu_S32MAX_S32MIN(DisasContext *ctx) +static void gen_mxu_S32MAX(DisasContext *ctx) { - uint32_t pad, opc, XRc, XRb, XRa; + gen_mxu_logic(ctx, tcg_gen_smax_i32); +} =20 - pad =3D extract32(ctx->opcode, 21, 5); - opc =3D extract32(ctx->opcode, 18, 3); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to zero */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { - /* exactly one operand is zero register - find which one is not...= */ - uint32_t XRx =3D XRb ? XRb : XRc; - /* ...and do max/min operation with one operand 0 */ - if (opc =3D=3D OPC_MXU_S32MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); - } - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to one of them */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - if (opc =3D=3D OPC_MXU_S32MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], - mxu_gpr[XRc - 1]); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], - mxu_gpr[XRc - 1]); - } - } +static void gen_mxu_S32MIN(DisasContext *ctx) +{ + gen_mxu_logic(ctx, tcg_gen_smin_i32); } =20 /* @@ -4328,8 +4297,10 @@ static void decode_opc_mxu__pool00(DisasContext *ctx) =20 switch (opcode) { case OPC_MXU_S32MAX: + gen_mxu_S32MAX(ctx); + break; case OPC_MXU_S32MIN: - gen_mxu_S32MAX_S32MIN(ctx); + gen_mxu_S32MIN(ctx); break; case OPC_MXU_D16MAX: case OPC_MXU_D16MIN: --=20 2.53.0 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 14 Sep 2026 16:09:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@oss.qualcomm.com Subject: [PATCH 5/6] target/mips/tcg: Use gen_mxu_logic for gen_mxu_S32SLT Date: Mon, 14 Sep 2026 13:08:57 -1000 Message-ID: <20260914230901.1781309-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260914230901.1781309-1-richard.henderson@linaro.org> References: <20260914230901.1781309-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::10; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789427406403158501 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/mxu_translate.c | 33 +++++++-------------------------- 1 file changed, 7 insertions(+), 26 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index 4b2c264f031..293eeb46c23 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -2313,34 +2313,15 @@ static void gen_mxu_q8slt(DisasContext *ctx, bool s= ltu) * Update XRa with the signed "set less than" comparison of XRb and XRc. * a.k.a. XRa =3D XRb < XRc ? 1 : 0; */ + +static void gen_setcond_lt_i32(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2) +{ + tcg_gen_setcond_i32(TCG_COND_LT, d, s1, s2); +} + static void gen_mxu_S32SLT(DisasContext *ctx) { - uint32_t pad, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to zero */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same registers -> just set destination to zero */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else { - /* the most general case */ - TCGv_i32 t0 =3D tcg_temp_new_i32(); - TCGv_i32 t1 =3D tcg_temp_new_i32(); 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Mon, 14 Sep 2026 16:09:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@oss.qualcomm.com Subject: [PATCH 6/6] target/mips/tcg: Use gen_mxu_logic for gen_mxu_S32CPS Date: Mon, 14 Sep 2026 13:08:58 -1000 Message-ID: <20260914230901.1781309-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260914230901.1781309-1-richard.henderson@linaro.org> References: <20260914230901.1781309-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::10; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789427404928158500 Content-Type: text/plain; charset="utf-8" Use movcond instead of a pair of branches to perform the computation, packed in a new gen_cps_i32. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/mxu_translate.c | 42 +++++++++------------------------ 1 file changed, 11 insertions(+), 31 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index 293eeb46c23..a38f4da12ba 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -2640,39 +2640,19 @@ static void gen_mxu_s32movzn(DisasContext *ctx, TCG= Cond cond) * Update XRa if XRc < 0 by value of 0 - XRb * else XRa =3D XRb */ + +static void gen_cps_i32(TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) +{ + TCGv_i32 n =3D tcg_temp_new_i32(); + TCGv_i32 z =3D tcg_constant_i32(0); + + tcg_gen_neg_i32(n, b); + tcg_gen_movcond_i32(TCG_COND_LT, a, c, z, n, b); +} + static void gen_mxu_S32CPS(DisasContext *ctx) { - uint32_t pad, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely(XRb =3D=3D 0)) { - /* XRc make no sense 0 - 0 =3D 0 -> just set destination to zero */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely(XRc =3D=3D 0)) { - /* condition always false -> just move XRb to XRa */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - TCGv_i32 t0 =3D tcg_temp_new_i32(); - TCGLabel *l_not_less =3D gen_new_label(); - TCGLabel *l_done =3D gen_new_label(); - - tcg_gen_brcondi_i32(TCG_COND_GE, mxu_gpr[XRc - 1], 0, l_not_less); - tcg_gen_neg_i32(t0, mxu_gpr[XRb - 1]); - tcg_gen_br(l_done); - gen_set_label(l_not_less); - gen_load_mxu_gpr(t0, XRb); - gen_set_label(l_done); - gen_store_mxu_gpr(t0, XRa); - } + gen_mxu_logic(ctx, gen_cps_i32); } =20 /* --=20 2.53.0