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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-486eb350686sm30797695f8f.27.2026.09.14.09.00.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 09:00:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1789401623; x=1790006423; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=TifGTPPkGOKDLGobPWLql5F+xJCFO44YItkMr2umQYs=; b=GS3Sm2Rzas8SOHoRoShwOKyC+9qWvXyMbobA1YI7qKVQyG05Ga+dNYu7oRhO6vFU3I +J+t+pRwejy4kTOSyCO51A5IGwL3uc+j9gJllSkJ2/85rVAhwAPZEeruVkLRKHNhXV3q FmpaZYlGBWTfAvtLzXzii5FIoOKNsafTMKu/RMr8HmPLpVO+RHqlGdIjnr58lBq6a1Cd KDCh4YLPsBGuesJP06WddPnnIO2icF4+tZnD/AZV604bONw6Sc0U5EYk9cfCLukIs7GS 2+4antHgDX77xgYJEPTGmce/pUhOBwzqnUUm/pSM3V2/AeITlUyn1EjqzrrOt80gk7GN 6ANQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1789401623; x=1790006423; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=TifGTPPkGOKDLGobPWLql5F+xJCFO44YItkMr2umQYs=; b=pHuIhpYlh2iI3q42lzorL7DwE0RsimFzHYi2xoeyEsbBSPN9CkIPQ0rILdrvCD05oc hWcTfU+/BqCwHO6O1Mj2L8GOhbo1L3WT4lGL5WBFmjebnmOGb9vM2w5Df8+i/GGaW4kQ dZg+HWll2+QcZeKcR/tirlXuj9iCQTOFb1jqmGAgF00aAL+EOz0c7FI+U6X1bUVnLcWb f5ls7y480Uva19d3e/Qu0SSwZuB1wD67RnQNLbz3pc+IkHzbLePw3MTNvMTMPzb6gvKw ZSEs+TXp2hXsuzp3zzqfQd5Y1wFrE9Yrra9N1ZEAJA5liJH71kYRuaEX8/IiBS1aAdE4 R1DA== X-Forwarded-Encrypted: i=1; AKwUvBwoI3AC8uwC/sPWQIEVAJ91lJmMCBqWDyZSRwARAtp7CMmtNqtWHkuwRHRaKzofygHor0TyYrryCxHM@nongnu.org X-Gm-Message-State: AFuF++k7xqguuk9wz6VIF7D1QHQOjLOW96CQpVYyMErJYvKt24U2IXkW 6ILS1uaNKGf8OkvAncvciO9EDIltH4zonhlv/aS/yiKpcNiJzKQlt0RYzvz6cI1JHNM= X-Gm-Gg: AYBFou10cxtFN6/Fk4wE2U1QArhWfpQ6HeE4accnjAdX89dj0sIBt4l/YVr8BCV1oTc e+MxzfsImib5xkx2x0B8shh/HRTkypE0/y1HWpB9FR+D0RWFRDmQ6glRQQNhtVChg8uIFjtOS85 e53tuhZE857hBINEq+1yl8Gb4FgogrK/7ARh0UZwtUYmKkgQ2VvZPB0/koDOsEIzTMr6rxhndqm 1GogkupJcFKC6Ai/UGCT9Vvi+f7fFCPxKA96LeYZRCq7rjFXNp+ypPSDDFEla7Q1y0ZfBdkp3mi Bzs7RBgH6sbliWReSv7kVT3nNUF9MMHHczBiyDssJNzHAWHmV1tM6LH+Ohns0R7nwmQs3S2Bs4n +PWAmY82V2+7x48eIwBY+TVEkUv3WlDDU2FOqNgfm78j/e+F+Q+Vq8xyRRF+gE0gYgMhBnUHkb/ 0CMrChaLKF7oNjyUFX70EGaU8ooqSAeE8yHI34UXOIK5RubOJEo1iUd/sUf6ZbeTsALytB9LYsi QKnkfHqJI2qSRPdNZvAZQT3RtnaVXJ2nQFvs2MVYu5rkni+GU2cI7DNo59FJ0H2M4qzWdEpVeYi Lqpt X-Received: by 2002:a05:6000:1785:b0:485:8a46:b3c4 with SMTP id ffacd0b85a97d-48702b5e64bmr3846156f8f.44.1789401623451; Mon, 14 Sep 2026 09:00:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 1/9] hw/intc/arm_gicv5: Ignore low bits in IRS_IST_BASER.ADDR Date: Mon, 14 Sep 2026 17:00:12 +0100 Message-ID: <20260914160020.327787-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260914160020.327787-1-peter.maydell@linaro.org> References: <20260914160020.327787-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:30::10; envelope-from=peter.maydell@linaro.org; helo=mail-wr2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789401740595158500 Content-Type: text/plain; charset="utf-8" The IRS_IST_BASER.ADDR documentation says: For IRS_IST_CFGR.STRUCTURE =3D 0: Bits[N:0] of the resulting address are 0 where N depends on the ISTSZ and LPI_ID_BITS fields in IRS_IST_CFGR as follows: N =3D Max(5, (ISTSZ + 1) + LPI_ID_BITS) For IRS_IST_CFGR.STRUCTURE =3D 1: Bits[N:0] of the resulting address are 0 where N depends on L2SZ, ISTSZ, and LPI_ID_BITS in IRS_IST_CFGR as follows: N =3D Max(5, LPI_ID_BITS - ((10 - ISTSZ) + (2 * L2SZ)) + 2) This enforces that the IST is aligned to the size of the IST table, or to a 64-byte boundary if the table is smaller than 64 bytes, even if the guest programs the low bits in the ADDR field to specify an insufficiently aligned address. We were missing this check, and instead trusted the guest-provided address to be sufficiently aligned already; add the alignment enforcement. The GICv5 spec defines the masking to be used with the expressions quoted above, which work with the raw field values from the IRS_IST_CFGR register; these simplify down to some straightforward expressions based on the sanitized values we've already extracted form those fields. You can get to the expressions we use here either by working through the simplification of the GIC spec expressions, or from first principles (the number of bits needed for the size of the table in bytes is the number of bits that index it plus the number of bits specifying the size of an individual table entry). Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 08878193dfc..34c3ee90d43 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1313,6 +1313,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain= domain, uint64_t value) */ GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; uint8_t istbits, l2bits, l2_idx_bits; + int tableszbits; uint8_t id_bits =3D FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, LPI_ID_BITS); id_bits =3D MIN(MAX(id_bits, QEMU_GICV5_MIN_LPI_ID_BITS), QEMU_GIC= V5_ID_BITS); @@ -1359,6 +1360,33 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domai= n domain, uint64_t value) cfg->l2_idx_bits =3D l2_idx_bits; cfg->structure =3D FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, STRUCTURE); + + /* + * Bits [N:0] of the base addr are ignored, to enforce that in a + * 1-level IST it is aligned to the size of the ISTE array, + * and in a 2-level IST it is aligned to the size of the L1 table. + * The spec defines N in terms of the raw L2SZ, ISTSZ and LPI_ID_B= ITS + * fields, but we have already sanitized these to + * istbits =3D ISTSZ + 2 + * l2bits =3D (L2SZ * 2) + 12 + * id_bits =3D LPI_ID_BITS + * We have also already enforced the "bottom 6 bits are 0" via + * R_IRS_IST_BASER_ADDR_MASK, so can skip the Max() operation. + * We want tableszbits =3D=3D the number of bits to zero, which is= N + 1. + */ + if (cfg->structure) { + /* + * L1 table is indexed by the (id_bits - l2_idx_bits) bits in + * the ID, so has 2^(id_bits - l2_idx_bits) entries, and each + * entry is 8 bytes =3D=3D 2^3. + */ + tableszbits =3D id_bits - l2_idx_bits + 3; + } else { + /* table has 2^id_bits entries of 2^istbits size each */ + tableszbits =3D id_bits + istbits; + } + cfg->base &=3D ~MAKE_64BIT_MASK(0, tableszbits); + if (!cfg->lpi_cache) { /* * Keys are GINT_TO_POINTER(intid), so we want the g_direct_ha= sh --=20 2.43.0 From nobody Sat Sep 26 20:51:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789401752; cv=none; d=zohomail.com; s=zohoarc; b=C2EzA0JfOjLeTQvk+3oJUaYCwjCItYsMzQrmaOr6Q1cqgrQlqukD6Kv4jVIBiIBoBDEXNMr7EIRvIFTln6+vpRp8O1XQMaRJdXHXUbGA9FdiM/jRfvR/S90AU5qNaCOfxG9kQrdW6+A68mCC9NTrvXDUizMHOiCe3eyFLEGGLGk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789401752; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=QaixVAXZvjT9gFneZWDufUXIFchBE7kGOyICDN3WKug=; b=EgcHhnmqQT1/Prwg1/7Qw8FVXeggBQX3Fc/oeWc9gNby4NJ/2KFflKZPMGwhb6T2WkPH6qIIKTP5j6RY3UDmpjBKlb96ahGiFIqFX0e9bGkZMEir2iDvvjBk3diM3kC3fsxWT5i6MPQ4rM80uvqSQM/AKJXKzs+04Sa++Aivlvc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1789401752587913.4119704920034; Mon, 14 Sep 2026 09:02:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x697K-0003eF-IZ; Mon, 14 Sep 2026 12:01:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x696a-000318-AZ for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:28 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x696X-0004cS-T0 for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:27 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-48586861639so1406851f8f.0 for ; Mon, 14 Sep 2026 09:00:25 -0700 (PDT) Received: from lanath.. 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Add the missing masking of low bits. We already needed to calculate the number of bits needed to index each byte in the L2 table, so add it to the GICv5ISTConfig to save having to re-calculate it later. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 6 ++++++ include/hw/intc/arm_gicv5.h | 1 + 2 files changed, 7 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 34c3ee90d43..124816d864c 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -595,6 +595,11 @@ static bool get_l2_iste_addr(GICv5Common *cs, const GI= Cv5ISTConfig *cfg, return false; } l2_base =3D l1_iste & R_L1_ISTE_L2_ADDR_MASK; + /* + * The effective base address of the L2 table is always + * aligned to the size of the L2 table. + */ + l2_base &=3D ~MAKE_64BIT_MASK(0, cfg->l2bits); id =3D extract32(id, 0, cfg->l2_idx_bits); } else { /* 1-level table */ @@ -1358,6 +1363,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain= domain, uint64_t value) cfg->id_bits =3D id_bits; cfg->istsz =3D 1 << istbits; cfg->l2_idx_bits =3D l2_idx_bits; + cfg->l2bits =3D l2bits; cfg->structure =3D FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, STRUCTURE); =20 diff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h index b8baf003ad6..d763a7939c7 100644 --- a/include/hw/intc/arm_gicv5.h +++ b/include/hw/intc/arm_gicv5.h @@ -23,6 +23,7 @@ typedef struct GICv5ISTConfig { uint8_t id_bits; /* number of bits in an ID for this table */ uint8_t l2_idx_bits; /* number of ID bits that index into L2 table */ uint8_t istsz; /* L2 ISTE size in bytes */ + uint8_t l2bits; /* bits needed to index L2 table in bytes */ bool structure; /* true if using 2-level table */ bool valid; /* true if this table is valid and usable */ /* This caches IST information about pending LPIs */ --=20 2.43.0 From nobody Sat Sep 26 20:51:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789401771; cv=none; d=zohomail.com; s=zohoarc; b=Ez11nRFDR7xwqUcu3QUI07EdUNvnKy0JUqTPc6+BgEQD4gye5j0mkfzukllMmJPbAzd2IeMhHG7G5ws827k6z+L2hzN7PdDImfQ034Hky1VCIxfjP95D5L6GlSLBsCuY114qhh5Oe9UY9gzwXLR9ZpNg3a2eIiVq2D1tu9g2l5U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789401771; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=IdKJzGBUWRrrYUn+MEqvsitMdRE0ew6RnIW7SSHXtRs=; b=WDRB7t8PMcqIeDvteg7C2lJu/NpqDkVu84hzH8BwMPHIqjCj0we0Aqj03wkKwW1w406ViXAdk7Lsbpyed0hPszVxLBup+ULdCkOc8CVMePqp40SCvBfisdxZra0KLir3MC6Ry7gKEhI8Y/pzrGx8V7xvCXqIySbrF+7kLIAo2h0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1789401771330935.1047447883777; Mon, 14 Sep 2026 09:02:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x697N-0003iY-41; Mon, 14 Sep 2026 12:01:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x696b-00032h-OP for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:30 -0400 Received: from mail-wr2-x10.google.com ([2a00:1450:4864:30::10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x696Z-0004cq-O2 for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:29 -0400 Received: by mail-wr2-x10.google.com with SMTP id ffacd0b85a97d-485b1d2874aso1778060f8f.1 for ; Mon, 14 Sep 2026 09:00:26 -0700 (PDT) Received: from lanath.. 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Delete the blank lines to make it consistent with itself and the rest of the file. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/arm_gicv5.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 124816d864c..e477c805b43 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1468,53 +1468,41 @@ static bool config_readl(GICv5 *s, GICv5Domain doma= in, hwaddr offset, v &=3D ~R_IRS_IDR0_VIRT_ONE_N_MASK; } return true; - case A_IRS_IDR1: *data =3D cs->irs_idr1; return true; - case A_IRS_IDR2: *data =3D cs->irs_idr2; return true; - case A_IRS_IDR3: /* In EL3 IDR0.VIRT is 0 so this is RES0 */ *data =3D domain =3D=3D GICV5_ID_EL3 ? 0 : cs->irs_idr3; return true; - case A_IRS_IDR4: /* In EL3 IDR0.VIRT is 0 so this is RES0 */ *data =3D domain =3D=3D GICV5_ID_EL3 ? 0 : cs->irs_idr4; return true; - case A_IRS_IDR5: *data =3D cs->irs_idr5; return true; - case A_IRS_IDR6: *data =3D cs->irs_idr6; return true; - case A_IRS_IDR7: *data =3D cs->irs_idr7; return true; - case A_IRS_IIDR: *data =3D cs->irs_iidr; return true; - case A_IRS_AIDR: *data =3D cs->irs_aidr; return true; - case A_IRS_IST_BASER: *data =3D extract64(cs->irs_ist_baser[domain], 0, 32); return true; - case A_IRS_IST_BASER + 4: *data =3D extract64(cs->irs_ist_baser[domain], 32, 32); return true; - case A_IRS_IST_STATUSR: /* * For QEMU writes to IRS_IST_BASER and IRS_MAP_L2_ISTR take effect @@ -1522,11 +1510,9 @@ static bool config_readl(GICv5 *s, GICv5Domain domai= n, hwaddr offset, */ *data =3D R_IRS_IST_STATUSR_IDLE_MASK; return true; - case A_IRS_IST_CFGR: *data =3D cs->irs_ist_cfgr[domain]; return true; - case A_IRS_SPI_STATUSR: /* * QEMU writes to IRS_SPI_{CFGR,DOMAINR,SELR,VMR} take effect @@ -1537,7 +1523,6 @@ static bool config_readl(GICv5 *s, GICv5Domain domain= , hwaddr offset, v =3D FIELD_DP32(v, IRS_SPI_STATUSR, IDLE, 1); *data =3D v; return true; - case A_IRS_SPI_CFGR: { GICv5SPIState *spi =3D spi_for_selr(cs, domain); --=20 2.43.0 From nobody Sat Sep 26 20:51:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789401841; cv=none; d=zohomail.com; s=zohoarc; b=fkwXGti0CQEGzWujgK3D/f7d2W7LN7w+GZqGA7/bLKNnOaxUB8Q9pxyXuWDk1ulQD4bYZuUFML0JYqV5xKI6JiJbGwHiVVeDzMLIC807mjYw34IgUck5yz5WgI2aTCkQHn1K0p900XhHxl/O960awqHj6cU86VPl93oeyUSmK4g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789401841; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=krib+ep6Ku4rcBL3FL/xOeC0nOLV1cZ4Dzi0yim0mVw=; b=A28quld3jn0Ft/o2LiKMPXJ3ZrySb6FJq3yyYndnz1EROgNs4Q8KzXsU4jT6VCLEsQuqvHpXM5EUDD8ihSthnVGvjb/PNsrpKNDL97l/aSVK3crTQxkMs96wxnplT9Dv0MVvcCPSfec3dgNHIWATlEhmVgERG5z/SUFaUPzUl4w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1789401841479735.3454697345171; Mon, 14 Sep 2026 09:04:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x697Y-0003zl-8D; Mon, 14 Sep 2026 12:01:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x696d-00039O-Cs for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:31 -0400 Received: from mail-wr2-x10.google.com ([2a00:1450:4864:30::10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x696b-0004dA-5a for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:30 -0400 Received: by mail-wr2-x10.google.com with SMTP id ffacd0b85a97d-4843378fb37so1032554f8f.3 for ; Mon, 14 Sep 2026 09:00:28 -0700 (PDT) Received: from lanath.. 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In a few places we check whether the IST is valid by doing a bit extract on the register value; switch those to look at cfg->structure instead. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index e477c805b43..c6914f7310c 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1223,8 +1223,7 @@ static void irs_map_l2_istr_write(GICv5 *s, GICv5Doma= in domain, uint64_t value) uint64_t l1_iste; MemTxResult res; =20 - if (!FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID) || - !cfg->structure) { + if (!cfg->valid || !cfg->structure) { /* WI if no IST set up or it is not 2-level */ return; } @@ -1294,7 +1293,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain= domain, uint64_t value) { GICv5Common *cs =3D ARM_GICV5_COMMON(s); =20 - if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { + if (s->phys_lpi_config[domain].valid) { /* If VALID is set, ADDR is RO and we can only update VALID */ bool valid =3D FIELD_EX64(value, IRS_IST_BASER, VALID); if (valid) { @@ -1604,7 +1603,7 @@ static bool config_writel(GICv5 *s, GICv5Domain domai= n, hwaddr offset, deposit64(cs->irs_ist_baser[domain], 32, 32, d= ata)); return true; case A_IRS_IST_CFGR: - if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { + if (s->phys_lpi_config[domain].valid) { qemu_log_mask(LOG_GUEST_ERROR, "guest tried to write IRS_IST_CFGR for %s config= frame " "while IST_BASER.VALID set\n", domain_name[domai= n]); --=20 2.43.0 From nobody Sat Sep 26 20:51:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789402065; cv=none; d=zohomail.com; s=zohoarc; b=EtZ62gxwKSQAlnUqsaWbO6gs85a7ERmI1rzL/Hi0vo7AFE0MWfBICDGGoxP8adrreAsrqfHGyl8chOWFR0fk6cp1+UBEkYRyfau2FkAcuwhdyuLAT4NrQWMOYgpgGH5tvuK1D2W7VfRq2u0WMiIbCFNQVcP8nlG8lUEyiHGrdRc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789402065; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=kkXdxdxtkGFvjB+esa9le+MPJYdqX0voNJcK0mIKJXQ=; b=LNjHnIdhOvIi6+QDYbFwzrKyXa3mjANQfRpFJuua6bP7uAmoAYXTLjfClBp2YA/INTcxTGAUmQapJNVCTcOpdmoaITwJ94wpHSO5S0d6bssH55yiHyh5t+M+4ZEMEBU+BS/3Jhyf0wBdQozKtK0gQtEwAWaEKYgdm5rF/ozekDo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1789402065323419.6618918770473; Mon, 14 Sep 2026 09:07:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x697d-0004FR-Q2; Mon, 14 Sep 2026 12:01:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x696j-0003FN-5T for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:39 -0400 Received: from mail-wr2-x10.google.com ([2a00:1450:4864:30::10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x696f-0004eN-W3 for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:36 -0400 Received: by mail-wr2-x10.google.com with SMTP id ffacd0b85a97d-482f6350f88so1232917f8f.2 for ; Mon, 14 Sep 2026 09:00:33 -0700 (PDT) Received: from lanath.. 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Free those resources in finalize. Since the GICv5 is created at QEMU startup and remains in existence for the lifetime of the process, this isn't an in-practice leak, only a theoretical one. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 11 +++++++++++ hw/intc/arm_gicv5_common.c | 3 +++ 2 files changed, 14 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index c6914f7310c..6b72870439b 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1970,6 +1970,17 @@ static void gicv5_init(Object *obj) =20 static void gicv5_finalize(Object *obj) { + GICv5 *s =3D ARM_GICV5(obj); + + for (int i =3D 0; i < NUM_GICV5_DOMAINS; i++) { + GHashTable *ht =3D s->phys_lpi_config[i].lpi_cache; + + if (ht) { + g_hash_table_destroy(ht); + } + + g_free(s->hppi[i]); + } } =20 static void gicv5_class_init(ObjectClass *oc, const void *data) diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index b155486af65..cc67246686e 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -112,6 +112,9 @@ static void gicv5_common_init(Object *obj) =20 static void gicv5_common_finalize(Object *obj) { + GICv5Common *cs =3D ARM_GICV5_COMMON(obj); + + g_free(cs->spi); } =20 static void gicv5_common_realize(DeviceState *dev, Error **errp) --=20 2.43.0 From nobody Sat Sep 26 20:51:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789401873; cv=none; d=zohomail.com; s=zohoarc; b=TQzg1oUYu/mj1o3OVkLjfJy22vS5O3a1RbIB2VRVmAAYd2OWmJuQwYNdqvJeVGHWK4TVP2ekIgUN448fgrd/bvJ8G+DLao15J98gbwe/JEmImmzRzApwtZ1Uho1nPBpFpV5//5SMlaYHwKty0R5uiZqczEFiWqCICqBD6dIgjzI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789401873; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=6E734XzpINz7DVCD4hyOh+TtFltl3kWyJgieC8778LU=; b=XxnVCeJMpNkgMhSyqG6EqjD70IEA4gB5pGrIEaI8hnMCDrIPNoxTLyKEyaFjwBKHVl8yko6BO0vkLcyB/StKWp4LAuLlDeLfqWdJ1khl927oXOXpkv1IhZNtEYI/3Euwo/u5mWY0jRItN1gfTNcCkuXDGdMIOIleegheLvVSIdY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1789401873527862.8351531332871; Mon, 14 Sep 2026 09:04:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x697d-0004EN-L0; Mon, 14 Sep 2026 12:01:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x696k-0003Gi-5d for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:47 -0400 Received: from mail-wm2-x11.google.com ([2a00:1450:4864:31::11]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x696i-0004eq-7f for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:37 -0400 Received: by mail-wm2-x11.google.com with SMTP id 5b1f17b1804b1-49e71cdb22bso13177485e9.2 for ; Mon, 14 Sep 2026 09:00:35 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-486eb350686sm30797695f8f.27.2026.09.14.09.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 09:00:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1789401634; x=1790006434; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=6E734XzpINz7DVCD4hyOh+TtFltl3kWyJgieC8778LU=; b=KlZ5qU2KhHLC64DgRGE7qplcHWXoQRQuzhtOYh9eQ3O68bqg3FAI54xQApG6X1WAau 7x7HvPnnWmrIJqU8zbJ7tt1R/EZrHrg7y+4c6gqczZoTuI/SXA3G8bZaDEiFj9tGMb/6 9nJbyrLv+TW4CPGbUhC7dKwdgJ3MD6aEsSEJJorrwSI4HIJoEEyiRQAbXvvhp4gtvdoT uiG2VEOEyT755rh+vKIOptPMyuWRUJimdYQU1WilH49iqVnR0znPr7gZD/1npJk2NfQp EUvf3wn3lX+/Uh4qR290SekubiH3+yUrylGHAM87SwmazQU6rab25VZvQyQzmS7LnWva YnFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1789401634; x=1790006434; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=6E734XzpINz7DVCD4hyOh+TtFltl3kWyJgieC8778LU=; b=n6nhghvkmLplSYwpnbzJo6kYgUuz60cor+vjL9rZjHr3jwd+ABUXp6d/egyHDS6WdM PosN5h/Hp2EvRay8tTL9sdNVOBQ90FSi7rJUaeE2XN8QdgMWviGG+rdR3PpOODrJRyes u5/I3UQkXdULEBDx8EisoG2KUnzxFKhaLTCCD6zg0pQDlkIvs1/KM91+upta0uVmfM2/ se9ewaFJi+usS+kF0Z0w0yE2c0eWPmYWUWAh16VsVYGOd6zRqheThyYE3BQ0V3syj21R pJSpNlG5TEIdvz/zgdbjb42vFo+wWXtu2vVqXYIhRn6o0kOdbUjWIQ/Fv7r5TWOcnurw Jsfw== X-Forwarded-Encrypted: i=1; AKwUvByLGx7ZrerDse0+7xpA+HgH+zIzFl9+D3mja76f3AmEV/UVrcntJK7U0IW28GtzgTkvEhqZL0nTka8f@nongnu.org X-Gm-Message-State: AFuF++nwUDEPyv4xFYui1CcEvHmTCQGR06TyKs+mzvqdUNyq7Jh4LMJ5 pI9jG9LHGKeOSwKPLAMzM2X1Giw9MKF1xkDns3bhYxTY4PjJyOyNUzsq7Ir4VI+pUerHEMXo2hT 7D8gGMJg= X-Gm-Gg: AYBFou2EkM2smiRqVtJ949Js+FBV3dWcumhrCbKV4aLUChV+gBDS13rInKsib2v5L6B VoZ4wlVR7j1w1A19FcroTc20yS6BqH5BvcocnWxv/xqYltgEya0Fqo9gQ64OX7l04oKVD6Lny67 RwDKO3pLXVN+p9p44zFtg+zSFtqHl/gwmhyePjkBrykiZA3fu9LfXMlRl03MbutWdA5o3u4BUBu mXRYvjRMZFyC1sm2OCT9vEWKB1sVzqLX+EpSKsDljgqW/xPDOvGUXJQQLCXn0MN3bMsdmJ7fZht e3vFm2q+Zy3iD3rNulw64Y2aKqHC/nHEzPnplxNSxYr8Xt1/kS7ozs7KwA5qMtJ8R+LFMB6jd6U dpiQDFXtFYsLbrhprBo4gEHENGmvVY6Y+iz/JYR2xC1idzGaypT9E3nYA1FWclq4VJ/MkKMn5ms x0ss/FRU3e2+T5KfbMOlvKheSGTynLv5HtUClXJRK8Y+77TKv3Z0wL+47hSaIcoqkw6xU2ngH8t xYd9XaWcE4uGKuER5tEfzQgFCAQ+FTF1KCKCVsRGzi1vyLaRWqjvd8OlXuON75/YoezK5CEsRPf WtlE X-Received: by 2002:a05:600c:474e:b0:49d:39:90ba with SMTP id 5b1f17b1804b1-49e7a638725mr42904245e9.3.1789401630887; Mon, 14 Sep 2026 09:00:30 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 6/9] target/arm: GICv5 cpuif: Use arm_cpu_set_irq() to set IRQ/FIQ status Date: Mon, 14 Sep 2026 17:00:17 +0100 Message-ID: <20260914160020.327787-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260914160020.327787-1-peter.maydell@linaro.org> References: <20260914160020.327787-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:31::11; envelope-from=peter.maydell@linaro.org; helo=mail-wm2-x11.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789401875891158500 Content-Type: text/plain; charset="utf-8" Currently the GICv5 cpu interface directly calls cpu_interrupt() and cpu_reset_interrupt() to raise and lower IRQ and FIQ. This is almost but not exactly what we do for GICv2/GICv3 external GPIO IRQ/FIQ line changes. Those are handled by arm_cpu_set_irq(), and as well as calling cpu_interrupt() or cpu_reset_interrupt() they also update env->irq_line_state. For IRQ and FIQ it doesn't matter whether we set and clear the bits in irq_line_state, because nothing looks at them. But for VIRQ and VFIQ it will matter, because VIRQ and VFIQ are the logical OR of the line state and some bits in HCR_EL2. We're going to need to call arm_cpu_set_irq() for VIRQ and VFIQ; for consistency, handle IRQ and FIQ that way too. Since arm_cpu_set_irq() is now a function called from other parts of the CPU code, we make its first argument a properly typed one, with a wrapper taking void* for when we need to use it as a qemu_irq_handler. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 14 +++++++++++--- target/arm/internals.h | 14 ++++++++++++++ target/arm/tcg/gicv5-cpuif.c | 35 ++++------------------------------- 3 files changed, 29 insertions(+), 34 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 77aa78f00e2..2b1b87b0ed4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -806,9 +806,8 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int= target_el) =20 =20 #ifndef CONFIG_USER_ONLY -static void arm_cpu_set_irq(void *opaque, int irq, int level) +void arm_cpu_set_irq(ARMCPU *cpu, int irq, int level) { - ARMCPU *cpu =3D opaque; CPUARMState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); static const int mask[] =3D { @@ -860,6 +859,15 @@ static void arm_cpu_set_irq(void *opaque, int irq, int= level) } } =20 +/* + * Wrapper of arm_cpu_set_irq with the right argument types to be a + * qemu_irq_handler function for our inbound GPIO lines. + */ +static void arm_cpu_gpio_set_irq(void *opaque, int irq, int level) +{ + arm_cpu_set_irq(opaque, irq, level); +} + static bool arm_cpu_internal_is_big_endian(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -1263,7 +1271,7 @@ static void arm_cpu_initfn(Object *obj) */ qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6); } else { - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6); + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_gpio_set_irq, 6); } =20 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, diff --git a/target/arm/internals.h b/target/arm/internals.h index 1775835ad50..c623e875136 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1883,6 +1883,20 @@ void define_gcs_cpregs(ARMCPU *cpu); /* Add the cpreg definitions for OMAP CP15 regs */ void define_omap_cp_regs(ARMCPU *cpu); =20 +#ifndef CONFIG_USER_ONLY +/** + * arm_cpu_set_irq: Assert or clear an IRQ/FIQ/etc interrupt line + * @cpu: CPU to set interrupt on + * @irq: one of the ARM_CPU_IRQ/ARM_CPU_FIQ/ARM_CPU_VIRQ/etc values + * @level: 0 to deassert, non-zero to assert + * + * This function is called by the qemu_irq_handler function + * when IRQ etc are real inbound GPIO lines; it is also called + * directly by the GICv5 CPU interface. + */ +void arm_cpu_set_irq(ARMCPU *cpu, int irq, int level); +#endif + /* Add the cpreg definitions for the GICv5 CPU interface */ void define_gicv5_cpuif_regs(ARMCPU *cpu); =20 diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index a6e6c440849..517c780d1f7 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -173,33 +173,6 @@ static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv= 5Domain domain) return best; } =20 -static void cpu_interrupt_update(CPUARMState *env, int irqtype, bool new_s= tate) -{ - CPUState *cs =3D env_cpu(env); - - /* - * OPT: calling cpu_interrupt() and cpu_reset_interrupt() has the - * correct behaviour, but is not optimal for the case where we're - * setting the interrupt line to the same level it already has. - * - * Clearing an already clear interrupt is free (it's just doing an - * atomic AND operation). Signalling an already set interrupt is a - * bit less ideal (it might unnecessarily kick the CPU). - * - * We could potentially use cpu_test_interrupt(), like - * arm_cpu_update_{virq,vfiq,vinmi,vserr}, since we always hold - * the BQL here; or perhaps there is an abstraction we could - * provide in the core code that all these places could call. - * - * For now, this is simple and definitely correct. - */ - if (new_state) { - cpu_interrupt(cs, irqtype); - } else { - cpu_reset_interrupt(cs, irqtype); - } -} - static void gicv5_update_irq_fiq(CPUARMState *env) { /* @@ -243,12 +216,12 @@ static void gicv5_update_irq_fiq(CPUARMState *env) /* * Unlike a GICv3 or GICv2, there is no external IRQ or FIQ line * to the CPU. Instead we directly signal the interrupt via - * cpu_interrupt()/cpu_reset_interrupt(). + * arm_cpu_set_irq(). */ trace_gicv5_update_irq_fiq(irq, fiq, superpriority); - cpu_interrupt_update(env, CPU_INTERRUPT_HARD, irq); - cpu_interrupt_update(env, CPU_INTERRUPT_FIQ, fiq); - cpu_interrupt_update(env, CPU_INTERRUPT_NMI, superpriority); + arm_cpu_set_irq(env_archcpu(env), ARM_CPU_IRQ, irq); + arm_cpu_set_irq(env_archcpu(env), ARM_CPU_FIQ, fiq); + arm_cpu_set_irq(env_archcpu(env), ARM_CPU_NMI, superpriority); } =20 static void gic_recalc_ppi_hppi(CPUARMState *env) --=20 2.43.0 From nobody Sat Sep 26 20:51:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789401757; cv=none; d=zohomail.com; s=zohoarc; b=MOI/7EuQtSlT7i8dhKyzdi1jB+++uJFgI7+GXuloBBsUbGxHpQYF94vdXz4tyoOQpM8G27Eu7LGJkwXH9MwsPEJaFRBhih2NdMlXpPY5Vi405mGiCPYXsSSxcZEeeElpQOnHzHjbp7R3Iuf0YPMSyO5ZMnLtxX690+g5JEFIJIg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789401757; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=tvOn/pAIjzvCed7vyXKyUkE525/C0NZBVLFzB/DrGUI=; b=DXoyCSBD+nO6H4F2LsIplMoD+MbGHV0ual13zXJkfWG5l2Q6Ccvudcv1tVRdx+S2WjVxJNDMy+9ZGu9qTZQe3Rdu5OrZ+VugCQXUqvkMANpJuHomGDn4o4gCycrmIydNtPfNvykrQTVNaJXMiZLI+s438S4YZ2kM0gvInj+5QU4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178940175722333.281883245420886; Mon, 14 Sep 2026 09:02:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x697d-0004Cq-1e; Mon, 14 Sep 2026 12:01:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x696i-0003F3-ED for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:37 -0400 Received: from mail-wr2-x10.google.com ([2a00:1450:4864:30::10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x696f-0004eK-LV for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:35 -0400 Received: by mail-wr2-x10.google.com with SMTP id ffacd0b85a97d-48449f62b93so681857f8f.0 for ; Mon, 14 Sep 2026 09:00:33 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-486eb350686sm30797695f8f.27.2026.09.14.09.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 09:00:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1789401632; x=1790006432; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=tvOn/pAIjzvCed7vyXKyUkE525/C0NZBVLFzB/DrGUI=; b=Wq7W+bhichAtZQhMLjmullrqYyP3wd5SW3KFAeaR8BCL6T4SHsjEKGcLa9BaKrZkcg Mj1FRDd+YgCAXbX4mhLAe+mIlR7y9aoBw2p22x+mA5ZXMpNQKuw96MUXsP+eX77ZqxJ4 CAb4p8kDR5W5knHjcZuKqQxysEE98bT24ADx+ge7oGzIF3z9oemAx9Bpau6qNIDWpsCk bXDr3dV5J8Cb+xQqo6DgRmen95po3sStTe+R9+KKmPLxkBsej9Rhg+VNZ8v0gnTH1FO5 AW+vdCZniQepDCBRK1acup9QQlVIE/51UlOPYazIkm+oOXjiSkBFBSZ5wQWnKHMTwKmY nK6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1789401632; x=1790006432; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=tvOn/pAIjzvCed7vyXKyUkE525/C0NZBVLFzB/DrGUI=; b=ZpZueLAiM8kl1pjYmqcE0ll0gxjJQTGvZMNBjlAFk1ckYunhTMHqFX1VqUxVhJBh7X NCwhBXleujqEJucsAIf4JAzGhTJSwqrXO4nZR44nREQ8DKxfKJRhtVBdBfa/QTcVDISW wVLq+r5oZMVesep0uLSKW65NrhdXx3cF8lyjrg6FeN3WrnPJ9QR+wAe1xraR6gZJ++bM VF0ZI/S8Sh/zj0wAYNGlz183XH72B/nk9gM4m3n5EQ2e7HMPOwlJJufmWXt6tSzWI6Ox cBTgPAh3eP6HJZM8v8VruCKSVE4t/Dcxs11mhCvR1sOviW4IpeHCitlZyLsfH7sRBDFp CfRw== X-Forwarded-Encrypted: i=1; AKwUvBw0xxNnZefchG5soIKqGyi3wxykH+DBm9k/CZ9FhBdzMN+AAOVmd7MkDT8U1A6vVa9bKSFw65URvH5T@nongnu.org X-Gm-Message-State: AFuF++l52zas4BBKj6mgQdGY2C6Fb7GNnVKsfed4Q56hBrgC3ckBmVjM 4wxTsPqPrZ6hZyGwQvhLCID+Qqd8EFFRTDfN61mZUDwNz6sO1f8uoZUxxrNOf64CYkNcgaZQlU0 ZbhHSteo= X-Gm-Gg: AYBFou0Seh2fwqC8s45k3U5Z353lmeCIg3fqGwR5e+tq9GvS1PR0llkYelHNXy30sqx Gh+TG9nlMtmqLjwhgzITUrtpduW80vQA6doeDqGaslMMV6XJF2NbrVSM6p63/M6YmcgKA+QuzY7 1DtmtXinnP1nXW81uPSvm11j2ujA3xHSYWqK+lRkfqIEgDyTbFbR39d33aMK3A04QIvZIDNC+z6 x8Akdfp+zCiOIhR02b9Q+9fpGKxqe50tQLMTw9nZe5kKKIRhRvmKruUXFyjObZfa3Z3Bde1XK2W Ec/HtP0mulepQq0iL4qHBJjJYc/FtMWxz+YY7lBCVzOg4W+wSFyo6crbS+nfQ8nM5r2e8YFvxal s0DyxuATdW8cN/WWXIJHT0THx3vjBjuvL3u+uiYSs4QOoCAQ4+q+Md2CTjqKmB3iz7+YiMg4CI6 4tqYotC/rkqxCK11qtSv+ELL2Tw6WzEQuT+Wy6dJ3snZj/jE06t3Nb9foq4D+z0A42Se55ekzfE Eu+O3w+kCKvqgXM/GTG8Aj4K0EMpxNoHzCKziN64/Ve9ktY9A6LYg9RJY+ekrQAslkX2iukrVuy ETHL X-Received: by 2002:a5d:664f:0:b0:47f:9158:5924 with SMTP id ffacd0b85a97d-48705a44dc3mr62141f8f.9.1789401632218; Mon, 14 Sep 2026 09:00:32 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 7/9] target/arm: Only allow GICv5 on CPUs without AArch32 at EL1..3 Date: Mon, 14 Sep 2026 17:00:18 +0100 Message-ID: <20260914160020.327787-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260914160020.327787-1-peter.maydell@linaro.org> References: <20260914160020.327787-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:30::10; envelope-from=peter.maydell@linaro.org; helo=mail-wr2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789401758539158500 Content-Type: text/plain; charset="utf-8" We previously allowed the GICv5 on any 64-bit CPU, with a hack where enabling the GICv5 silently disabled AArch32 for EL1..3. Now that we have a separate 'max-v8' and 'max-v9' where max-v9 correctly doesn't implement AArch32 at EL1..3, we can fix the "when do we expose the has_gcie property" condition so that we only allow the GICv5 when AArch32 doesn't exist above EL0, and remove the hack disabling AArch32. We could instead have defined a new ARM_FEATURE_V9, but "allow the feature to be present on CPUs where it doesn't actively break anything" fits the way we've generally handled things in QEMU, and it avoids having a new V9 feature bit that we only use for this one thing and where it's not clear when we should be setting it for KVM, hvf, etc accelerators. In practice the only CPUs which will allow GICv5 now are max, max-v9 and a64fx. Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 8 ++++++++ target/arm/cpu.c | 37 +++++++------------------------------ 2 files changed, 15 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index eecbc3b889e..c4029c0f73c 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1129,6 +1129,14 @@ static inline bool isar_feature_aa64_aa32_el3(const = ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL3) >=3D 2; } =20 +static inline bool isar_feature_aa64_aa32_above_el0(const ARMISARegisters = *id) +{ + /* True if any EL above EL0 has AArch32 support */ + return isar_feature_aa64_aa32_el1(id) || + isar_feature_aa64_aa32_el2(id) || + isar_feature_aa64_aa32_el3(id); +} + static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) !=3D 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2b1b87b0ed4..bbf4e0aa465 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1584,8 +1584,13 @@ static void arm_cpu_post_init(Object *obj) &cpu->rvbar_prop, OBJ_PROP_FLAG_READWRITE); =20 - /* We only allow GICv5 on a 64-bit v8 CPU */ - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + /* + * We only allow GICv5 on a CPU with no AArch32 support above EL0 + * (which is typically a v9 CPU), because GICv5 defines no AArch32 + * system registers to control it. + */ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && + !cpu_isar_feature(aa64_aa32_above_el0, cpu)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_gcie_proper= ty); } } @@ -2235,34 +2240,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 /* Report FEAT_GCIE in our ID registers if property was set */ FIELD_DP64_IDREG(isar, ID_AA64PFR2, GCIE, cpu->has_gcie); - if (cpu_isar_feature(aa64_gcie, cpu)) { - if (!arm_feature(env, ARM_FEATURE_AARCH64)) { - /* - * We only create the have_gcie property for AArch64 CPUs, - * but the user might have tried aarch64=3Doff with has_gcie= =3Don. - */ - error_setg(errp, "Cannot both enable has_gcie and disable aarc= h64"); - return; - } - - /* - * FEAT_GCIE implies Armv9, which implies no AArch32 above EL0. - * Usually we don't strictly insist on this kind of feature - * dependency, but in this case we enforce it, because the - * GICv5 CPU interface has no AArch32 versions of its system - * registers, so interrupts wouldn't work if we allowed AArch32 - * in EL1 or above. Downgrade "AArch32 and AArch64" to "AArch64". - */ - if (cpu_isar_feature(aa64_aa32_el3, cpu)) { - FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 1); - } - if (cpu_isar_feature(aa64_aa32_el2, cpu)) { - FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 1); - } - if (cpu_isar_feature(aa64_aa32_el1, cpu)) { - FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL1, 1); - } - } =20 if (cpu_isar_feature(aa64_mte, cpu)) { /* --=20 2.43.0 From nobody Sat Sep 26 20:51:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1789401752; cv=none; d=zohomail.com; s=zohoarc; b=WfugA8/vldTbQ5Gou4/LsFgyMvmO6Q2j8fHevSiLdf+Jnm11hmoqQ8JJgi06dB1RsUhdD8EDmF7tEmK2LB+lYEhatXrCz7g1s/C1VcaMOiOmjtDDc7qsAP20MOmR55w/P7uAbG+ivHcTLwFJyN3UH2dQT5HYXOgEHVGMhaji4gA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789401752; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Ma7EhGHQRutJnTccF+GlJMgT+aCYxDR9KoZVGOT5NJI=; b=TxljbMFnWdNw5fAC2V10uLDhglKTd5Iz+4sHYcrIlMmnYbVNQN6L7UaW1ser+yBp2bApRNn4mNn464n5QPU2U2VOTzgkcTcCaYzK7ouI9Tp0oXygn9h9B6whXVRgChI1iJ0/+DBhG29RqrJJu7/ugSwu/5Z9N39TMXElKR1kOsw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178940175260159.68576345774136; Mon, 14 Sep 2026 09:02:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x697R-0003tG-Pg; Mon, 14 Sep 2026 12:01:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x696t-0003Ns-Qn for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:52 -0400 Received: from mail-wr2-x10.google.com ([2a00:1450:4864:30::10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x696q-0004eX-In for qemu-devel@nongnu.org; Mon, 14 Sep 2026 12:00:47 -0400 Received: by mail-wr2-x10.google.com with SMTP id ffacd0b85a97d-482f633cd78so1103802f8f.1 for ; Mon, 14 Sep 2026 09:00:34 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-486eb350686sm30797695f8f.27.2026.09.14.09.00.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 09:00:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1789401633; x=1790006433; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=Ma7EhGHQRutJnTccF+GlJMgT+aCYxDR9KoZVGOT5NJI=; b=lu+zwPMs4460O2jxQTupZmvKh6LrOR0nNLhCIUqMBMOc0WWMa+zKwb06KagKfWAvZj tORLVZt8pUg5GAlgOW28Yt4I7TBW9gdWDNq4gGh5C1Jv5sKNvQwLxKqwxZKe7hmxCyeO wVaSvHuGW61733ODyZ+sEbspjm8+jcNeOKgj0JU2+rI8PMrhCwRF9rXsZAaHURaKxJ2R seuajVBiMn+dJM4aSTnCAw6WCm/QCCQRmrWs9yiPg1+9PSQDJMSlgpvjsJCcwYFrL5sp aRJNPd+183hNbw2DxwJbiWuALD+xWYcNQPSKXoxB4MmwQGCiB0YzWZ8QVe2u7jmRy2sP qVkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1789401633; x=1790006433; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=Ma7EhGHQRutJnTccF+GlJMgT+aCYxDR9KoZVGOT5NJI=; b=rJ+Gu7WXmukfw8uO8HPixDuPlDs4mvKsq5NaEiTFibqsUy4XkjUiN8Ag343ehE+87U 0gU5dDsqNHYva6Wi89lAaMSy5CrCjKZUBPaaBZRFuniGAHki/7g/Q9p6GWeO5xPOrgKN csquqhbpN1PKVAZ1a5SMrVr/ADsSKoI+0MnAFL8AVrx2E5WyYVkJ7WEdvBfTdEnU7nok B0OaHjhxeDb8agx9oPHR/rzl/M/7LJL17usSVMHC9OPbcq2tCfb28QCFHGfXqS/OdJAG fqN2uul9oD8XfaTQlcBj6kvRuebezUiaRRCa4fDalAqDjS3TINevywA3LkFXV7sjoQDG rvQg== X-Forwarded-Encrypted: i=1; AKwUvBxQX+UETMMr/Awzz3dKAM/b8hFKLTfX3aHWdCA0sIKFNfAM8oxvhcBjTnR53wTPn3bI5J9ZWpazCtQU@nongnu.org X-Gm-Message-State: AFuF++m5mhgfUFX6Ft1555oLFEPy87wc+FMPtNANPz5gsWTRLF8waSM3 +j8XBufQOwnL/BwGLp7IAMe7+xb8TYiMShlaTfdRlF4dh7NQEgvmUeUEQRVANDJj4JsS8GljF7d 2J2GMhms= X-Gm-Gg: AYBFou0d5BhkmnXug0MTU++t98rlXuhJKvCht26GRgJD6XgCs1vUO6C1uM1ac4LTo+S FW4O/96JNpHq2YzNeIiz8jJ4ziix5rFFGtakWd1DnOAiQ7SJ58zz9tLpLbj1jMUG+bVWEdFg9cS muHlkWRzlBbMJD72BzhPV7uH3U6iLtfF0IFFDaAXqJ2mU/gYuYbzEhyM1RTPNXMcb8TSHPGBRY6 hV3GkptJfZq8yNuarkbVeUlEfTacV1GyCngv2FHv1ROqfGBDxXx0TMSxT1lZC13XXO/86uDVbq+ 3TK1sA6XUmI6vOahBXu8Ynb3fH31n0r/An1q5pNMiXBuE7ltNFKZZ9z5hPXREv/cj4LwYxPcN3q dMrWb/Zh2YS76oQoYNTnZx3NapoHlw116MJk8rIQbxEcZRNcp27gpustr8vIm/TOX8cLfTjDZi8 wSh5nN2qpQk/hKeeFzessnP7sDyQ7EOTL0y32tFO9NfXD036NeNjYdxBbAq5GEaRRBgiWSAv51D ltVlPmiLLDxB1S9CEABqAaJWZIkoD9qfRFNufB5RAdoUr/hrqNuUeHJ0SEfZHZN52iXtB0mcMgS IIkD X-Received: by 2002:a05:6000:41ed:b0:487:4:bd86 with SMTP id ffacd0b85a97d-48702b5b792mr3993303f8f.42.1789401633069; Mon, 14 Sep 2026 09:00:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 8/9] hw/intc/arm_gicv5: Pass CPU index to CPU interface Date: Mon, 14 Sep 2026 17:00:19 +0100 Message-ID: <20260914160020.327787-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260914160020.327787-1-peter.maydell@linaro.org> References: <20260914160020.327787-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:30::10; envelope-from=peter.maydell@linaro.org; helo=mail-wr2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789401754639158500 Content-Type: text/plain; charset="utf-8" In a real hardware GICv5, the IRS knows which CPU is talking to it because each IRS<->cpuif link is a separate 1:1 connection. In QEMU's implementation, the cpuif code calls functions like gicv5_set_priority(), and currently we usually don't pass anything to tell the IRS which cpuif is making the call, because mostly the IRS doesn't need to care. There are a few places where it does need to know, notably in gicv5_get_hppi(). Here we have the cpuif pass its IAFFID; the IRS then looks that up by doing a linear search of the cpu_iaffids[] array to get the index of the CPU. For virtualization, many of the stream commands which don't currently need to say which cpuif is making the call will have to start doing so, because changing the state of a virtual interrupt requires the IRS to look up the VPE which is resident on the calling cpuif. This makes the IAFFID->cpuidx lookup seem increasingly awkward. Change gicv5_set_gicv5state() to pass the IRS's CPU index value for the cpuif as well as the guest-visible IAFFID, and make the stream functions identify the cpuif by CPU index rather than IAFFID, to avoid the unnecessary IAFFID->cpuidx lookup. As this is now three GICv5-related things that we are keeping in the CPU state struct, we push them into a sub-struct to keep them tidy. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/arm_gicv5_common.c | 2 +- include/hw/intc/arm_gicv5_stream.h | 6 ++++-- target/arm/cpu.c | 10 ++++++---- target/arm/cpu.h | 10 ++++++---- target/arm/tcg/gicv5-cpuif.c | 6 +++--- 5 files changed, 20 insertions(+), 14 deletions(-) diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index cc67246686e..cfadfee4f05 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -176,7 +176,7 @@ static void gicv5_common_realize(DeviceState *dev, Erro= r **errp) } =20 for (int i =3D 0; i < cs->num_cpus; i++) { - if (!gicv5_set_gicv5state(cs->cpus[i], cs, cs->cpu_iaffids[i])) { + if (!gicv5_set_gicv5state(cs->cpus[i], cs, cs->cpu_iaffids[i], i))= { error_setg(errp, "CPU %d (IAFFID 0x%x) does not implement GICv5 CPU = interface", i, cs->cpu_iaffids[i]); diff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5= _stream.h index 3cc9f611557..f45072d8c57 100644 --- a/include/hw/intc/arm_gicv5_stream.h +++ b/include/hw/intc/arm_gicv5_stream.h @@ -20,7 +20,8 @@ typedef struct GICv5Common GICv5Common; * gicv5_set_gicv5state * @cpu: CPU object to tell about its IRS * @cs: the GIC IRS it is connected to - * @iaffid: the IAFFID of this CPU + * @iaffid: the IAFFID of this CPU (guest-visible) + * @cpuidx: the index of this CPU for this IRS (QEMU-internal) * * Set the CPU object's GICv5 pointer to point to this GIC IRS. The * IRS must call this when it is realized, for each CPU it is @@ -29,7 +30,8 @@ typedef struct GICv5Common GICv5Common; * Returns true on success, false if the CPU doesn't implement the * GICv5 CPU interface. */ -bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs, uint32_t iaffid); +bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs, uint32_t iaffid, + uint32_t cpuidx); =20 /* * The architected Stream Protocol is asynchronous; commands can be diff --git a/target/arm/cpu.c b/target/arm/cpu.c index bbf4e0aa465..a64cdb8e895 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1213,17 +1213,19 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *= f, int flags) } =20 #ifndef CONFIG_USER_ONLY -bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs, uint32_t iaffid) +bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs, uint32_t iaffid, + uint32_t cpuidx) { /* * Set this CPU's gicv5state pointer to point to the GIC that we are - * connected to, and record our IAFFID. + * connected to, and record our IAFFID and CPU index. */ if (!cpu_isar_feature(aa64_gcie, cpu)) { return false; } - cpu->env.gicv5state =3D cs; - cpu->env.gicv5_iaffid =3D iaffid; + cpu->env.gicv5.gicv5state =3D cs; + cpu->env.gicv5.iaffid =3D iaffid; + cpu->env.gicv5.cpuidx =3D cpuidx; return true; } #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e3f931dba26..41a8770b121 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -814,10 +814,12 @@ typedef struct CPUArchState { const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; - /* Similarly, for a GICv5Common */ - void *gicv5state; - /* For GICv5, this CPU's IAFFID */ - uint64_t gicv5_iaffid; + /* Information the GICv5 IRS passes to us */ + struct { + void *gicv5state; /* GICv5Common struct */ + uint64_t iaffid; /* this CPU's IAFFID */ + uint32_t cpuidx; /* GIC IRS-internal index of this CPU */ + } gicv5; #else /* CONFIG_USER_ONLY */ /* For usermode syscall translation. */ bool eabi; diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 517c780d1f7..eea66a4140e 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -87,7 +87,7 @@ FIELD(ICC_HPPIR_EL1, HPPIV, 32, 1) =20 static GICv5Common *gicv5_get_gic(CPUARMState *env) { - return env->gicv5state; + return env->gicv5.gicv5state; } =20 static GICv5Domain gicv5_logical_domain(CPUARMState *env) @@ -147,7 +147,7 @@ static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv5= Domain domain) return GICV5_PENDING_IRQ_NONE; } =20 - irs_hppi =3D gicv5_get_hppi(gic, domain, env->gicv5_iaffid); + irs_hppi =3D gicv5_get_hppi(gic, domain, env->gicv5.iaffid); =20 /* * If the best PPI and the best interrupt from the IRS have the @@ -788,7 +788,7 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 5, .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, /* ICC_IAFFIDR_EL1 holds the IAFFID only, in its low bits */ - .fieldoffset =3D offsetof(CPUARMState, gicv5_iaffid), + .fieldoffset =3D offsetof(CPUARMState, gicv5.iaffid), /* * The field is a constant value set in gicv5_set_gicv5state(), * so don't allow it to be overwritten by reset. --=20 2.43.0 From nobody Sat Sep 26 20:51:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/arm_gicv5.c | 5 ++--- include/hw/intc/arm_gicv5_stream.h | 4 ++-- target/arm/tcg/gicv5-cpuif.c | 2 +- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 6b72870439b..66953606419 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -531,12 +531,11 @@ static void irs_recall_hppis(GICv5 *s, GICv5Domain do= main) } =20 GICv5PendingIrq gicv5_get_hppi(GICv5Common *cs, GICv5Domain domain, - uint32_t iaffid) + uint32_t cpuidx) { GICv5 *s =3D ARM_GICV5(cs); - int cpuidx =3D irs_cpuidx_from_iaffid(cs, iaffid); =20 - assert(cpuidx >=3D 0); + assert(cpuidx < cs->num_cpus); return s->hppi[domain][cpuidx]; } =20 diff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5= _stream.h index f45072d8c57..641f3d0f499 100644 --- a/include/hw/intc/arm_gicv5_stream.h +++ b/include/hw/intc/arm_gicv5_stream.h @@ -204,14 +204,14 @@ void gicv5_forward_interrupt(ARMCPU *cpu, GICv5Domain= domain); * gicv5_get_hppi * @cs: GIC IRS to query * @domain: interrupt domain to act on - * @iaffid: IAFFID of this CPU interface + * @cpuidx: IRS CPU index of this CPU interface * * Ask the IRS for the highest priority pending interrupt that it has * for this CPU. This returns the equivalent of what in the stream * protocol is the outstanding interrupt sent with a Forward packet. */ GICv5PendingIrq gicv5_get_hppi(GICv5Common *cs, GICv5Domain domain, - uint32_t iaffid); + uint32_t cpuidx); =20 /** * gicv5_deactivate diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index eea66a4140e..0b1033c1ef0 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -147,7 +147,7 @@ static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv5= Domain domain) return GICV5_PENDING_IRQ_NONE; } =20 - irs_hppi =3D gicv5_get_hppi(gic, domain, env->gicv5.iaffid); + irs_hppi =3D gicv5_get_hppi(gic, domain, env->gicv5.cpuidx); =20 /* * If the best PPI and the best interrupt from the IRS have the --=20 2.43.0