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Lima" Subject: [PATCH v2] target/riscv/tcg: svinval instructions raise virtual instruction Message-ID: <20260911191436.23402-1-christianslima@proton.me> Feedback-ID: 169431447:user:proton X-Pm-Message-ID: 6f9d31e07e97cbd225425dbce9c105d71b2f15f2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=185.70.43.16; envelope-from=christianslima@proton.me; helo=mail-4316.protonmail.ch X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @proton.me) X-ZM-MESSAGEID: 1789154164179158500 Content-Type: text/plain; charset="utf-8" The risc v privileged specification requires hinval.vvma, hinval.gvma, sfence.w.inval and sfence.inval.ir should raise a virtual instruction exception when executed in the vu-mode. This patch add the check to raise the virtual instruction exception when is in the vu-mode. changes in v2: - Remove the wrong `return true;` from macro Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3621 Signed-off-by: Christian S. Lima --- target/riscv/tcg/insn_trans/trans_svinval.c.inc | 3 +++ target/riscv/tcg/insn_trans/trans_xthead.c.inc | 12 +++++++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/target/riscv/tcg/insn_trans/trans_svinval.c.inc b/target/riscv= /tcg/insn_trans/trans_svinval.c.inc index 4614c1489c..5b1172672e 100644 --- a/target/riscv/tcg/insn_trans/trans_svinval.c.inc +++ b/target/riscv/tcg/insn_trans/trans_svinval.c.inc @@ -25,6 +25,9 @@ /* Test if priv level is M or S. */ #define REQUIRE_PRIV_MS(ctx) do { \ if (ctx->priv =3D=3D PRV_U) { \ + if (ctx->virt_enabled) { \ + ctx->virt_inst_excp =3D true \ + } \ return false; \ } \ } while (0) diff --git a/target/riscv/tcg/insn_trans/trans_xthead.c.inc b/target/riscv/= tcg/insn_trans/trans_xthead.c.inc index f4e3051000..4bf6594747 100644 --- a/target/riscv/tcg/insn_trans/trans_xthead.c.inc +++ b/target/riscv/tcg/insn_trans/trans_xthead.c.inc @@ -267,11 +267,13 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_ts= t *a) #define REQUIRE_PRIV_MSU(ctx) =20 /* Test if priv level is M or S. */ -#define REQUIRE_PRIV_MS(ctx) \ -do { \ - if (ctx->priv =3D=3D PRV_U) { \ - return false; \ - } \ +#define REQUIRE_PRIV_MS(ctx) do { \ + if (ctx->priv =3D=3D PRV_U) { \ + if (ctx->virt_enabled) { \ + ctx->virt_inst_excp =3D true \ + } \ + return false; \ + } \ } while (0) =20 #define NOP_PRIVCHECK(insn, extcheck, privcheck) \ --=20 2.55.0