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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1789129662; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AniVVytWrOiQcAtPHQ982ORVDQ1BdQzn9xV2WxqQDcA=; b=P2L7EO8rYZLGGj4oEZeWTzdz/qzunC5lIoDhOPlw+SuzLMWIZBSNBmcvG7vpy18wRMiG2Z 59MesW83Qc4kAN9gdf7OZFgTZcrVEOQdIOTJyeTjGov7fYmMeq4zH+WIaOckfqg+ghmNd/ E3gBoSFnUfw0V0u2DUEeGmD+v98rJRI= X-MC-Unique: bEGvFzE-MfONsnHStvTmJw-1 X-Mimecast-MFC-AGG-ID: bEGvFzE-MfONsnHStvTmJw_1789129657 From: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Date: Fri, 11 Sep 2026 16:27:24 +0400 Subject: [PATCH 01/10] hmp: don't crash on invalid register MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260911-query-reg-v1-1-0c04f0c02cf3@redhat.com> References: <20260911-query-reg-v1-0-0c04f0c02cf3@redhat.com> In-Reply-To: <20260911-query-reg-v1-0-0c04f0c02cf3@redhat.com> To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Zhao Liu , Peter Maydell , Chinmay Rath , Nicholas Piggin , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Paolo Bonzini , Laurent Vivier , Mark Cave-Ayland , Artyom Tarasenko , Helge Deller , Pierrick Bouvier , Warner Losh , Kyle Evans , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= X-Developer-Signature: v=1; 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Signed-off-by: Marc-Andr=C3=A9 Lureau --- monitor/hmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/monitor/hmp.c b/monitor/hmp.c index 488ec23937df..10e19e417aba 100644 --- a/monitor/hmp.c +++ b/monitor/hmp.c @@ -424,7 +424,7 @@ static bool gdb_get_register(MonitorHMP *hmp, int64_t *= pval, const char *name) =20 buf =3D g_byte_array_new(); reg_size =3D gdb_read_register(cs, buf, reg->gdb_reg); - if (reg_size > sizeof(*pval)) { + if (reg_size =3D=3D 0 || reg_size > sizeof(*pval)) { return false; } =20 --=20 2.55.0.543.g5ebe2ebe4ea8 From nobody Mon Sep 28 00:09:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1789129817; cv=none; d=zohomail.com; s=zohoarc; b=n5/SEUogipxLdVVMfCMYtzi4sPeH2iP/6seKVLqelG3R6U9jcJdRRIHpW6Xk8gK4Rqf0CRvZp3EA17oVr9QlfuH6qEMz98D+yB5h3r9QfCUEY+6SDvRAbj98n4ay4ib4x2ylQy3PBtKuxJCVmivhuPWX6313NNLKssd21qRwaxI= ARC-Message-Signature: i=1; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.6 on 10.30.177.95 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1789129819720158500 Commit b3e88abb200c ("gdbstub: Consider GDBFeature::base_reg in gdb_register_coprocessor()") identified that register numbers may have gaps. We also need to adjust the next base_reg correctly to avoid overlapping registers. Rename the field to be more explicit about its usage. Signed-off-by: Marc-Andr=C3=A9 Lureau Acked-by: Alex Benn=C3=A9e --- gdbstub/gdbstub.c | 13 ++++++------- include/hw/core/cpu.h | 2 +- target/arm/gdbstub.c | 8 +++++--- target/arm/gdbstub64.c | 10 ++++++---- target/ppc/gdbstub.c | 2 +- target/riscv/gdbstub.c | 9 ++++++--- target/xtensa/cpu.c | 2 +- 7 files changed, 26 insertions(+), 20 deletions(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 0a328b0dd488..0ce871d74929 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -605,13 +605,13 @@ void gdb_init_cpu(CPUState *cpu) gdb_register_feature(cpu, 0, cc->gdb_read_register, cc->gdb_write_register, feature); - cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D feature->num_regs; + cpu->gdb_next_base_reg =3D cpu->gdb_num_g_regs =3D feature->num_re= gs; } else { - cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D cc->gdb_num_core_reg= s; + cpu->gdb_next_base_reg =3D cpu->gdb_num_g_regs =3D cc->gdb_num_cor= e_regs; } =20 trace_gdbxml_init_cpu(object_get_typename(OBJECT(cpu)), cpu->cpu_index, - cpu->gdb_num_regs, cpu->gdb_num_g_regs, + cpu->gdb_next_base_reg, cpu->gdb_num_g_regs, cc->gdb_num_core_regs); } =20 @@ -621,7 +621,7 @@ void gdb_register_coprocessor(CPUState *cpu, { GDBRegisterState *s; guint i; - int base_reg =3D cpu->gdb_num_regs; + int base_reg =3D cpu->gdb_next_base_reg; =20 for (i =3D 0; i < cpu->gdb_regs->len; i++) { /* Check for duplicates. */ @@ -639,7 +639,7 @@ void gdb_register_coprocessor(CPUState *cpu, gdb_register_feature(cpu, base_reg, get_reg, set_reg, feature); =20 /* Add to end of list. */ - cpu->gdb_num_regs +=3D feature->num_regs; + cpu->gdb_next_base_reg =3D base_reg + feature->num_regs; } =20 void gdb_unregister_coprocessor_all(CPUState *cpu) @@ -651,7 +651,7 @@ void gdb_unregister_coprocessor_all(CPUState *cpu) g_array_free(cpu->gdb_regs, true); =20 cpu->gdb_regs =3D NULL; - cpu->gdb_num_regs =3D 0; + cpu->gdb_next_base_reg =3D 0; cpu->gdb_num_g_regs =3D 0; } =20 @@ -2522,4 +2522,3 @@ void gdb_create_default_process(GDBState *s) process->attached =3D false; process->target_xml =3D NULL; } - diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 328e30045ce1..02212f555c2e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -521,7 +521,7 @@ struct CPUState { struct CPUJumpCache *tb_jmp_cache; =20 GArray *gdb_regs; - int gdb_num_regs; + int gdb_next_base_reg; int gdb_num_g_regs; QTAILQ_ENTRY(CPUState) node; =20 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index d6e29c4cf467..e5cbe4d951ef 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -555,19 +555,21 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg, gdb_find_static_feature("arm-m-profile-mv= e.xml")); } + GDBFeature *feature =3D + arm_gen_dynamic_sysreg_feature(cs, cs->gdb_next_base_reg); gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_sysreg_feature(cs, cs->gdb_nu= m_regs)); + feature); =20 #ifdef CONFIG_TCG if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { gdb_register_coprocessor(cs, arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, - arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs)); + arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_next_base_reg)= ); #ifndef CONFIG_USER_ONLY if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { gdb_register_coprocessor(cs, arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg, - arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs)); + arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_next_base_= reg)); } #endif } diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 0c3e5b30bd6a..cf5b95b54641 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -885,7 +885,8 @@ void aarch64_cpu_register_gdb_regs_for_features(ARMCPU = *cpu) CPUState *cs =3D CPU(cpu); if (isar_feature_aa64_sve(&cpu->isar) || isar_feature_aa64_sme(&cpu->isar)) { - GDBFeature *feature =3D arm_gen_dynamic_svereg_feature(cs, cs->gdb= _num_regs); + GDBFeature *feature =3D + arm_gen_dynamic_svereg_feature(cs, cs->gdb_next_base_reg); gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, aarch64_gdb_set_sve_reg, feature); } else { @@ -896,7 +897,7 @@ void aarch64_cpu_register_gdb_regs_for_features(ARMCPU = *cpu) =20 if (isar_feature_aa64_sme(&cpu->isar)) { GDBFeature *sme_feature =3D - arm_gen_dynamic_smereg_feature(cs, cs->gdb_num_regs); + arm_gen_dynamic_smereg_feature(cs, cs->gdb_next_base_reg); gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg, aarch64_gdb_set_sme_reg, sme_feature); if (isar_feature_aa64_sme2(&cpu->isar)) { @@ -927,7 +928,8 @@ void aarch64_cpu_register_gdb_regs_for_features(ARMCPU = *cpu) #endif =20 /* All AArch64 CPUs have at least TPIDR */ + GDBFeature *tls_feature =3D + arm_gen_dynamic_tls_feature(cs, cs->gdb_next_base_reg); gdb_register_coprocessor(cs, aarch64_gdb_get_tls_reg, - aarch64_gdb_set_tls_reg, - arm_gen_dynamic_tls_feature(cs, cs->gdb_num_r= egs)); + aarch64_gdb_set_tls_reg, tls_feature); } diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 4d622c5cad59..ec25c541c685 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -206,7 +206,7 @@ static void gdb_gen_spr_feature(CPUState *cs) =20 gdb_feature_builder_init(&builder, &pcc->gdb_spr, "org.qemu.power.spr", "power-spr.xml", - cs->gdb_num_regs); + cs->gdb_next_base_reg); =20 for (i =3D 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr =3D &env->spr_cb[i]; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 9abbf5bcdf0e..f279f4ab2461 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -348,9 +348,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState= *cs) gdb_find_static_feature("riscv-32bit-fpu.= xml")); } if (cpu->cfg.ext_zve32x) { + GDBFeature *feature =3D + ricsv_gen_dynamic_vector_feature(cs, cs->gdb_next_base_reg); gdb_register_coprocessor(cs, riscv_gdb_get_vector, - riscv_gdb_set_vector, - ricsv_gen_dynamic_vector_feature(cs, cs->= gdb_num_regs)); + riscv_gdb_set_vector, feature); } =20 #ifdef CONFIG_TCG @@ -373,8 +374,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState= *cs) } =20 if (cpu->cfg.ext_zicsr) { + GDBFeature *feature =3D + riscv_gen_dynamic_csr_feature(cs, cs->gdb_next_base_reg); gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - riscv_gen_dynamic_csr_feature(cs, cs->gdb= _num_regs)); + feature); } #endif } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 7c25b9ab707a..48863a1859d4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -263,7 +263,7 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Erro= r **errp) return; } =20 - cs->gdb_num_regs =3D xcc->config->gdb_regmap.num_regs; + cs->gdb_next_base_reg =3D xcc->config->gdb_regmap.num_regs; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1789129743179158500 gdb_feature_builder_end() never propagated builder->base_reg into feature->base_reg, leaving it at 0 for all dynamically-built features. This made the trace log at gdb_get_register_list() report an incorrect base_reg for dynamic features. GDBRegisterState::base_reg was correctly set, so this doesn't fix an actual issue. Signed-off-by: Marc-Andr=C3=A9 Lureau --- gdbstub/gdbstub.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 0ce871d74929..912e31b66744 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -476,6 +476,7 @@ void gdb_feature_builder_end(const GDBFeatureBuilder *b= uilder) =20 g_ptr_array_free(builder->xml, TRUE); =20 + builder->feature->base_reg =3D builder->base_reg; builder->feature->num_regs =3D builder->regs->len; builder->feature->regs =3D (void *)g_ptr_array_free(builder->regs, FAL= SE); trace_gdbxml_feature_builder_header(builder->feature->name, --=20 2.55.0.543.g5ebe2ebe4ea8 From nobody Mon Sep 28 00:09:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1789129771133158500 Add an i386-segments.xml GDB feature that exposes the six segment limit registers (cs, ds, es, ss, fs, gs) as read-only system registers through the GDB coprocessor interface. This makes them accessible to both GDB and HMP without relying on the legacy MonitorDef table, which will be removed in a subsequent commit. Signed-off-by: Marc-Andr=C3=A9 Lureau --- configs/targets/i386-softmmu.mak | 2 +- configs/targets/x86_64-softmmu.mak | 2 +- gdbstub/gdb-xml/i386-segments.xml | 14 ++++++++++++++ target/i386/gdbstub.c | 24 ++++++++++++++++++++++++ 4 files changed, 40 insertions(+), 2 deletions(-) diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmm= u.mak index 38a8f85201f9..89cdaa072ef7 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Di386 TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy -TARGET_XML_FILES=3D i386-32bit.xml +TARGET_XML_FILES=3D i386-32bit.xml i386-segments.xml TARGET_LONG_BITS=3D32 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-so= ftmmu.mak index c7f8746b4f58..0af699971de0 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -2,6 +2,6 @@ TARGET_ARCH=3Dx86_64 TARGET_BASE_ARCH=3Di386 TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy -TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-apx.xml +TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-apx.xml i386-segments.xml TARGET_LONG_BITS=3D64 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy diff --git a/gdbstub/gdb-xml/i386-segments.xml b/gdbstub/gdb-xml/i386-segme= nts.xml new file mode 100644 index 000000000000..6fbf3f91957e --- /dev/null +++ b/gdbstub/gdb-xml/i386-segments.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 5c5fa7272163..2729b0f5bc1e 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -493,6 +493,25 @@ static int i386_cpu_gdb_set_egprs(CPUState *cs, uint8_= t *mem_buf, int n) } #endif =20 +#ifndef CONFIG_USER_ONLY +static int x86_gdb_read_segment_limit(CPUState *cs, GByteArray *buf, int n) +{ + CPUX86State *env =3D cpu_env(cs); + static const int segments[] =3D { R_CS, R_DS, R_ES, R_SS, R_FS, R_GS }; + + if (n < 0 || n >=3D ARRAY_SIZE(segments)) { + return 0; + } + return gdb_get_reg32(buf, env->segs[segments[n]].limit); +} + +static int x86_gdb_write_segment_limit(CPUState *cs, uint8_t *buf, int n) +{ + /* Segment caches are exposed for inspection only. Ignore writes. */ + return 4; +} +#endif + void x86_cpu_gdb_init(CPUState *cs) { #ifdef TARGET_X86_64 @@ -514,4 +533,9 @@ void x86_cpu_gdb_init(CPUState *cs) gdb_find_static_feature("i386-32bit-linux.xml= ")); #endif #endif +#ifndef CONFIG_USER_ONLY + gdb_register_coprocessor(cs, x86_gdb_read_segment_limit, + x86_gdb_write_segment_limit, + gdb_find_static_feature("i386-segments.xml")); +#endif } --=20 2.55.0.543.g5ebe2ebe4ea8 From nobody Mon Sep 28 00:09:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1789129750; cv=none; d=zohomail.com; s=zohoarc; b=cF14rfPaClj9kEE+lZIZn0gO7FOvjmmEWx77pdJXdAh6JQiWxqzNy5X4GPjR2s5E4343wtydgx+Wg1E8pejkjjVJwsi8xml3VoaA62OFTkIzWoQ9lW4E4f1i2IfYm+zU8uWLbZin0YPlyYp2NrvRNdYAWU/n0F0cQkId4k6Ew/M= ARC-Message-Signature: i=1; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1789129753292158500 Some targets, including x86, have no GDB register named "pc" (x86 uses eip/rip). When the GDB register lookup fails for "$pc" in HMP expressions, fall back to CPUClass::get_pc so that "p $pc", "x $pc" etc. work without relying on the legacy MonitorDef table. This prepares for the eventual removal of MonitorDef while making $pc available immediately for all targets that implement get_pc. Signed-off-by: Marc-Andr=C3=A9 Lureau --- monitor/hmp.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/monitor/hmp.c b/monitor/hmp.c index 10e19e417aba..0a74247ca66a 100644 --- a/monitor/hmp.c +++ b/monitor/hmp.c @@ -402,7 +402,7 @@ void hmp_help_cmd(MonitorHMP *mon, const char *name) * Set @pval to the value in the register identified by @name. * return %true if the register is found, %false otherwise. */ -static bool gdb_get_register(MonitorHMP *hmp, int64_t *pval, const char *n= ame) +static bool get_register(MonitorHMP *hmp, int64_t *pval, const char *name) { g_autoptr(GArray) regs =3D NULL; CPUState *cs =3D monitor_hmp_get_cpu(hmp); @@ -435,6 +435,10 @@ static bool gdb_get_register(MonitorHMP *hmp, int64_t = *pval, const char *name) } return true; } + if (!strcmp(name, "pc") && cs->cc->get_pc) { + *pval =3D cs->cc->get_pc(cs); + return true; + } return false; } =20 @@ -526,7 +530,7 @@ static int64_t expr_unary(MonitorHMP *mon) pch++; } *q =3D 0; - if (!gdb_get_register(mon, ®, buf) + if (!get_register(mon, ®, buf) && get_monitor_def(mon, ®, buf) < 0) { expr_error(mon, "unknown register"); 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1789129779121158500 Add an m68k-system.xml GDB feature that exposes supervisor stack pointers (ssp, usp, isp), function code registers (sfc, dfc), MMU registers (urp, srp, dttr0/1, ittr0/1, mmusr) as read-only system registers through the GDB coprocessor interface. Signed-off-by: Marc-Andr=C3=A9 Lureau --- configs/targets/m68k-softmmu.mak | 2 +- gdbstub/gdb-xml/m68k-system.xml | 32 +++++++++++++++++++++++++++ target/m68k/helper.c | 47 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 80 insertions(+), 1 deletion(-) diff --git a/configs/targets/m68k-softmmu.mak b/configs/targets/m68k-softmm= u.mak index 0bc889f326e3..f3ac9b74c862 100644 --- a/configs/targets/m68k-softmmu.mak +++ b/configs/targets/m68k-softmmu.mak @@ -1,4 +1,4 @@ TARGET_ARCH=3Dm68k TARGET_BIG_ENDIAN=3Dy -TARGET_XML_FILES=3D cf-core.xml cf-fp.xml m68k-core.xml m68k-fp.xml +TARGET_XML_FILES=3D cf-core.xml cf-fp.xml m68k-core.xml m68k-fp.xml m68k-s= ystem.xml TARGET_LONG_BITS=3D32 diff --git a/gdbstub/gdb-xml/m68k-system.xml b/gdbstub/gdb-xml/m68k-system.= xml new file mode 100644 index 000000000000..0a91be0edc00 --- /dev/null +++ b/gdbstub/gdb-xml/m68k-system.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 5f91d206f596..f2615d5bcfb8 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -123,6 +123,48 @@ static int m68k_fpu_gdb_set_reg(CPUState *cs, uint8_t = *mem_buf, int n) return 0; } =20 +#ifndef CONFIG_USER_ONLY +static int m68k_gdb_read_system_register(CPUState *cs, GByteArray *buf, in= t n) +{ + CPUM68KState *env =3D cpu_env(cs); + static const int stacks[] =3D { M68K_SSP, M68K_USP, M68K_ISP }; + + if (n >=3D 0 && n < ARRAY_SIZE(stacks)) { + int sp =3D stacks[n]; + + return gdb_get_reg32(buf, env->sp[sp]); + } + switch (n) { + case 3: + return gdb_get_reg32(buf, env->sfc); + case 4: + return gdb_get_reg32(buf, env->dfc); + case 5: + return gdb_get_reg32(buf, env->mmu.urp); + case 6: + return gdb_get_reg32(buf, env->mmu.srp); + case 7: + return gdb_get_reg32(buf, env->mmu.ttr[M68K_DTTR0]); + case 8: + return gdb_get_reg32(buf, env->mmu.ttr[M68K_DTTR1]); + case 9: + return gdb_get_reg32(buf, env->mmu.ttr[M68K_ITTR0]); + case 10: + return gdb_get_reg32(buf, env->mmu.ttr[M68K_ITTR1]); + case 11: + return gdb_get_reg32(buf, env->mmu.mmusr); + default: + return 0; + } +} + +static int m68k_gdb_write_system_register(CPUState *cs, uint8_t *buf, int = n) +{ + /* These registers are exposed for inspection only. Ignore writes. */ + return 4; +} +#endif + void m68k_cpu_init_gdb(M68kCPU *cpu) { CPUState *cs =3D CPU(cpu); @@ -135,6 +177,11 @@ void m68k_cpu_init_gdb(M68kCPU *cpu) gdb_register_coprocessor(cs, m68k_fpu_gdb_get_reg, m68k_fpu_gdb_se= t_reg, gdb_find_static_feature("m68k-fp.xml")); } +#ifndef CONFIG_USER_ONLY + gdb_register_coprocessor(cs, m68k_gdb_read_system_register, + m68k_gdb_write_system_register, + gdb_find_static_feature("m68k-system.xml")); +#endif /* TODO: Add [E]MAC registers. */ } =20 --=20 2.55.0.543.g5ebe2ebe4ea8 From nobody Mon Sep 28 00:09:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1789129778; cv=none; d=zohomail.com; s=zohoarc; b=HRxEuVlU127Qg73XcBUuoHrRkHpviDYCsSaAkNgSG38rJBR2p84+F+zkIvh/Rc2qvEUZcOQSifcdlZEM138ef16uGwhuoE1fyQFuLU00eUT3psJ2P+/VbFs8WAulHEKYNSYu6K4uWRHFffrKJhp8qyb4ry+Zq8RfZSRm0i1LPq0= ARC-Message-Signature: i=1; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1789129779178158501 Add a sparc64-system.xml GDB feature that exposes asi, pstate, cansave, canrestore, otherwin, wstate, and cleanwin as read-only system registers through the GDB coprocessor interface. Signed-off-by: Marc-Andr=C3=A9 Lureau --- configs/targets/sparc64-softmmu.mak | 2 +- gdbstub/gdb-xml/sparc64-system.xml | 22 +++++++++++++++++++++ target/sparc/gdbstub.c | 38 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 61 insertions(+), 1 deletion(-) diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-= softmmu.mak index 4e621fb8e39e..7f2789136653 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,7 +1,7 @@ TARGET_ARCH=3Dsparc64 TARGET_BASE_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy -TARGET_XML_FILES=3Dsparc64-cpu.xml sparc64-fpu.xml sparc64-cp0.xml +TARGET_XML_FILES=3Dsparc64-cpu.xml sparc64-fpu.xml sparc64-cp0.xml sparc64= -system.xml TARGET_LONG_BITS=3D64 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy diff --git a/gdbstub/gdb-xml/sparc64-system.xml b/gdbstub/gdb-xml/sparc64-s= ystem.xml new file mode 100644 index 000000000000..e00baedb467e --- /dev/null +++ b/gdbstub/gdb-xml/sparc64-system.xml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index 2874ce1b3501..ca23a4a94532 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -266,6 +266,39 @@ static int sparc_cp0_gdb_write_register(CPUState *cs, = uint8_t *mem_buf, int n) #endif } =20 +#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) +static int sparc64_gdb_read_system_register(CPUState *cs, GByteArray *buf, + int n) +{ + CPUSPARCState *env =3D cpu_env(cs); + + switch (n) { + case 0: + return gdb_get_reg32(buf, env->asi); + case 1: + return gdb_get_reg32(buf, env->pstate); + case 2: + return gdb_get_reg32(buf, env->cansave); + case 3: + return gdb_get_reg32(buf, env->canrestore); + case 4: + return gdb_get_reg32(buf, env->otherwin); + case 5: + return gdb_get_reg32(buf, env->wstate); + case 6: + return gdb_get_reg32(buf, env->cleanwin); + default: + return 0; + } +} + +static int sparc64_gdb_write_system_register(CPUState *cs, uint8_t *buf, i= nt n) +{ + /* These registers are exposed for inspection only. Ignore writes. */ + return 4; +} +#endif + void sparc_cpu_register_gdb_regs(CPUState *cs) { #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) @@ -282,5 +315,10 @@ void sparc_cpu_register_gdb_regs(CPUState *cs) gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register, sparc_cp0_gdb_write_register, gdb_find_static_feature("sparc64-cp0.xml")); +#ifndef CONFIG_USER_ONLY + gdb_register_coprocessor(cs, sparc64_gdb_read_system_register, + sparc64_gdb_write_system_register, + gdb_find_static_feature("sparc64-system.xml")= ); +#endif #endif } --=20 2.55.0.543.g5ebe2ebe4ea8 From nobody Mon Sep 28 00:09:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1789129732; cv=none; d=zohomail.com; s=zohoarc; b=Qnu9Wyvcw29F6GeEvPwcMjjQKxwsB+OTFH+JgitI1hMkBRBp+shZbu8yrsw4ZCH59G2FSJhmruipQj0Z8U16lgvekcvoU9vVwEbBOxoyEkniGOsh5EzYo6Z7s1sQDRLxIK5/fSk001CdgFzRLuqQXO217AGibZQAhNrUAysK9UM= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260911-query-reg-v1-8-0c04f0c02cf3@redhat.com> References: <20260911-query-reg-v1-0-0c04f0c02cf3@redhat.com> In-Reply-To: <20260911-query-reg-v1-0-0c04f0c02cf3@redhat.com> To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Zhao Liu , Peter Maydell , Chinmay Rath , Nicholas Piggin , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Paolo Bonzini , Laurent Vivier , Mark Cave-Ayland , Artyom Tarasenko , Helge Deller , Pierrick Bouvier , Warner Losh , Kyle Evans , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= X-Developer-Signature: v=1; a=openpgp-sha256; l=773; i=marcandre.lureau@redhat.com; h=from:subject:message-id; bh=LMrjJTVTVpO2R0XX7vgTv//RHImMSQWNJTx8uS10AB0=; b=owEBbQKS/ZANAwAKAdro4Ql1lpzlAcsmYgBqo/OvQ16YWYZ57x+2HOU3K6EmSbrY109lK5myr 95vNB0h1MCJAjMEAAEKAB0WIQSHqb2TP4fGBtJ29i3a6OEJdZac5QUCaqPzrwAKCRDa6OEJdZac 5QTzD/oCsf37URwa3TSnmZOnWsq92c/+qvcBVl3Qd3wHnFHLkALTL0WNNBAYB++IYWAKtaqfXjB nRy4e+rOdJ4I6v9qj1jp6R26mqxr+dGeQ6wJMwQcisK5FdE0Exga7cpdi+ly9D+6fciYOGjsgrs ttmCSTmlvm3hy433P0CvuXt4FOYbIuD5AW4AFtpRTdoyL8eAzJvOKxPrzLV69Wqsh6ltRp/zWBc xOPPLrZe/Gc9HfXKOrl8bBJ64xXrR0w+bf0KdyBxCK4XmNah4TbwO+jAH+PVxL+2CIzylic/6BP BKxIlnwM9Lttyb/eCsCJwL7EGhhBJ0QoifkvFRHdxH985VKVmA6ezdj22A4tTi4BoASVdsXIpg4 BgGTtE7O01PG4qlN3ZBMFnpLdA7vJVSdoXQd4ntCAMIKsEUUD6me1N18Pt+iML9OChBCOhRXkKc cTKxhHO32ysCBGi26TwSButCTucJwy2kMv+ATX9h5X/vteqcVuF9a1RVodkEaq1VJcPYzjIwneC DfGILKR8CL6IxXEENNl/BDcVYuZ5fElHVKvpgvmGwyh9UW5HRthu5BYjw2jRHdwriyaKDudsNCr cSe/klj/Lw9BBTe+euWPoolpDO9OJONZc/2NyJ9te+mShEmsObXeQejTmCS8nVjhULAkeoG+PBl 1vQjIoI2Q8a5JOA== X-Developer-Key: i=marcandre.lureau@redhat.com; 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Signed-off-by: Marc-Andr=C3=A9 Lureau --- target/riscv/tcg/csr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index bd4b6dc114bc..93a7f419f29f 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -53,7 +53,8 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int i= ndex, uint64_t bit) { bool virt =3D env->virt_enabled; =20 - if (env->priv =3D=3D PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) { + if (env->debugger || env->priv =3D=3D PRV_M || + !riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_NONE; } =20 --=20 2.55.0.543.g5ebe2ebe4ea8 From nobody Mon Sep 28 00:09:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1789129763; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.6 on 10.30.177.95 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1789129765264158500 The core GDB XML uses ABI names (zero, ra, sp, fp, ft0, fs0, etc.) but users also refer to registers by their numeric names (x0-x31, f0-f31) and the s0 alias for fp. The legacy MonitorDef mechanism supported both via split "x0/zero" name matching. Register a feature that maps: - x0-x31 and s0 to the corresponding core integer registers - x0h-x31h and their ABI aliases (zeroh, rah, ...) to env->gprh[] - f0-f31 to the corresponding FPU registers (when FPU is present) This preserves full HMP $register compatibility after the MonitorDef removal. Signed-off-by: Marc-Andr=C3=A9 Lureau --- configs/targets/riscv32-linux-user.mak | 2 +- configs/targets/riscv32-softmmu.mak | 2 +- configs/targets/riscv64-bsd-user.mak | 2 +- configs/targets/riscv64-linux-user.mak | 2 +- configs/targets/riscv64-softmmu.mak | 2 +- gdbstub/gdb-xml/riscv-32bit-alias.xml | 105 ++++++++++++++++++++++++++= ++++ gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml | 40 ++++++++++++ gdbstub/gdb-xml/riscv-64bit-alias.xml | 105 ++++++++++++++++++++++++++= ++++ gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml | 46 +++++++++++++ target/riscv/gdbstub.c | 43 ++++++++++++ 10 files changed, 344 insertions(+), 5 deletions(-) diff --git a/configs/targets/riscv32-linux-user.mak b/configs/targets/riscv= 32-linux-user.mak index d88fdf5e1b2f..8ee14fa14383 100644 --- a/configs/targets/riscv32-linux-user.mak +++ b/configs/targets/riscv32-linux-user.mak @@ -1,7 +1,7 @@ TARGET_ARCH=3Driscv32 TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv -TARGET_XML_FILES=3D riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-32bit-virtual.xml +TARGET_XML_FILES=3D riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-32bit-fpu-alias.x= ml riscv-64bit-fpu-alias.xml CONFIG_SEMIHOSTING=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy TARGET_SYSTBL_ABI=3D32 diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-= softmmu.mak index 5d5016d00832..c717940344f0 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Driscv32 TARGET_BASE_ARCH=3Driscv -TARGET_XML_FILES=3D riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-32bit-virtual.xml +TARGET_XML_FILES=3D riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-32bit-fpu-alias.x= ml riscv-64bit-fpu-alias.xml # needed by boot.c TARGET_NEED_FDT=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/riscv64-bsd-user.mak b/configs/targets/riscv64= -bsd-user.mak index 5b4e138099fc..1d37e018c871 100644 --- a/configs/targets/riscv64-bsd-user.mak +++ b/configs/targets/riscv64-bsd-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Driscv64 TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv -TARGET_XML_FILES=3D riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-64bit-virtual.xml +TARGET_XML_FILES=3D riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-64bit-virtual.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.x= ml riscv-64bit-fpu-alias.xml TARGET_LONG_BITS=3D64 TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy diff --git a/configs/targets/riscv64-linux-user.mak b/configs/targets/riscv= 64-linux-user.mak index 35621520c560..564d15aaca8c 100644 --- a/configs/targets/riscv64-linux-user.mak +++ b/configs/targets/riscv64-linux-user.mak @@ -1,7 +1,7 @@ TARGET_ARCH=3Driscv64 TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv -TARGET_XML_FILES=3D riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-64bit-virtual.xml +TARGET_XML_FILES=3D riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-64bit-virtual.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.x= ml riscv-64bit-fpu-alias.xml CONFIG_SEMIHOSTING=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy TARGET_SYSTBL_ABI=3D64 diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-= softmmu.mak index a10dc03c04c8..28bfcdc575fb 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -1,7 +1,7 @@ TARGET_ARCH=3Driscv64 TARGET_BASE_ARCH=3Driscv TARGET_KVM_HAVE_GUEST_DEBUG=3Dy -TARGET_XML_FILES=3D riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-64bit-virtual.xml riscv-32bit-cpu.xml riscv-32bit-virtual.xml +TARGET_XML_FILES=3D riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-64bit-virtual.xml riscv-32bit-cpu.xml riscv-32bit-virtual.xml r= iscv-32bit-alias.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-= 64bit-fpu-alias.xml # needed by boot.c TARGET_NEED_FDT=3Dy TARGET_LONG_BITS=3D64 diff --git a/gdbstub/gdb-xml/riscv-32bit-alias.xml b/gdbstub/gdb-xml/riscv-= 32bit-alias.xml new file mode 100644 index 000000000000..a00a86ebdf95 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-32bit-alias.xml @@ -0,0 +1,105 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml b/gdbstub/gdb-xml/ri= scv-32bit-fpu-alias.xml new file mode 100644 index 000000000000..3935f72ea289 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/riscv-64bit-alias.xml b/gdbstub/gdb-xml/riscv-= 64bit-alias.xml new file mode 100644 index 000000000000..28781b230226 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-64bit-alias.xml @@ -0,0 +1,105 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml b/gdbstub/gdb-xml/ri= scv-64bit-fpu-alias.xml new file mode 100644 index 000000000000..13e6b341a0f8 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index f279f4ab2461..6694fa86fd84 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -336,16 +336,59 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(C= PUState *cs, int base_reg) return &cpu->dyn_vreg_feature; } =20 +/* x0-x31, s0, then pairs of numeric and ABI high-half aliases. */ +static int riscv_gdb_get_alias(CPUState *cs, GByteArray *buf, int n) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + uint64_t val; + + if (n < 33) { + return riscv_cpu_gdb_read_register(cs, buf, n =3D=3D 32 ? 8 : n); + } + + val =3D cpu->env.gprh[(n - 33) / 2]; + if (riscv_cpu_is_32bit(cpu)) { + return gdb_get_reg32(buf, val); + } + return gdb_get_reg64(buf, val); +} + +static int riscv_gdb_set_alias(CPUState *cs, uint8_t *buf, int n) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + const unsigned regsz =3D riscv_cpu_is_32bit(cpu) ? 4 : 8; + + if (n < 33) { + return riscv_cpu_gdb_write_register(cs, buf, n =3D=3D 32 ? 8 : n); + } + + env->gprh[(n - 33) / 2] =3D ldn(env, buf, regsz); + return regsz; +} + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + + gdb_register_coprocessor(cs, riscv_gdb_get_alias, riscv_gdb_set_alias, + gdb_find_static_feature(riscv_cpu_is_32bit(cp= u) ? + "riscv-32bit-alias.xm= l" : + "riscv-64bit-alias.xm= l")); + if (env->misa_ext & RVD) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, gdb_find_static_feature("riscv-64bit-fpu.= xml")); + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, + riscv_gdb_set_fpu, + gdb_find_static_feature("riscv-64bit-fpu-alias.xml")); } else if (env->misa_ext & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, gdb_find_static_feature("riscv-32bit-fpu.= xml")); + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, + riscv_gdb_set_fpu, + gdb_find_static_feature("riscv-32bit-fpu-alias.xml")); } if (cpu->cfg.ext_zve32x) { GDBFeature *feature =3D --=20 2.55.0.543.g5ebe2ebe4ea8 From nobody Mon Sep 28 00:09:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1789129840158158500 Now that all targets expose their system registers via GDB register descriptions (i386 segment limits, m68k, sparc64) and $pc is handled by the CPUClass::get_pc fallback, the legacy MonitorDef table and SysemuCPUOps::monitor_get_register callback are no longer needed. Remove MonitorDef struct, the per-target monitor_defs arrays (i386, m68k, sparc64), riscv_monitor_get_register_legacy(), and the get_monitor_def() fallback in expr_unary(). HMP $register expressions now use gdb_get_register_list() exclusively. For RISC-V, the legacy callback provided case-insensitive register name matching (e.g. $Mstatus) and a special message for vector registers ("Unable to print the value of vector vreg"). The GDB-based lookup is case-sensitive (consistent with all other targets) and reports oversized registers as "unknown register" instead. Signed-off-by: Marc-Andr=C3=A9 Lureau --- include/hw/core/sysemu-cpu-ops.h | 16 ----- include/monitor/hmp.h | 6 -- include/qemu/typedefs.h | 1 - monitor/hmp.c | 44 +----------- target/i386/cpu.c | 32 --------- target/m68k/cpu.c | 22 ------ target/riscv/cpu.c | 1 - target/riscv/internals.h | 3 - target/riscv/monitor.c | 140 -----------------------------------= ---- target/sparc/cpu.c | 19 ------ 10 files changed, 2 insertions(+), 282 deletions(-) diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index e56eea18b785..3a85aa47e243 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -101,22 +101,6 @@ typedef struct SysemuCPUOps { */ bool (*internal_is_big_endian)(CPUState *cpu); =20 - /** - * @monitor_get_register: Callback to fill @pval with register @name v= alue. - * This field is legacy, use @gdb_core_xml_file - * to dump registers instead. - * Returns: 0 on success or negative errno on failure. - */ - int (*monitor_get_register)(CPUState *cs, const char *name, int64_t *p= val); - -#ifdef CONFIG_HMP - /** - * @monitor_defs: Array of MonitorDef entries. This field is legacy, - * use @gdb_core_xml_file to dump registers instead. - */ - const MonitorDef *monitor_defs; -#endif - /** * @legacy_vmsd: Legacy state for migration. * Do not use in new targets, use #DeviceClass::vmsd ins= tead. diff --git a/include/monitor/hmp.h b/include/monitor/hmp.h index ef53e87f7608..950dd931d452 100644 --- a/include/monitor/hmp.h +++ b/include/monitor/hmp.h @@ -31,12 +31,6 @@ MonitorHMP *monitor_cur_hmp(void); g_assert_not_reached(); \ } =20 -struct MonitorDef { - const char *name; - int offset; - int64_t (*get_value)(MonitorHMP *hmp, const MonitorDef *md, int offset= ); -}; - void monitor_new_hmp(const char *id, const char *chardev_id, bool use_readline, Error **errp); =20 diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 2344c92182ea..5580e1fc4aba 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -72,7 +72,6 @@ typedef struct MemoryRegionSection MemoryRegionSection; typedef struct MigrationIncomingState MigrationIncomingState; typedef struct MigrationState MigrationState; typedef struct Monitor Monitor; -typedef struct MonitorDef MonitorDef; typedef struct MSIMessage MSIMessage; typedef struct NetClientState NetClientState; typedef struct NetFilterState NetFilterState; diff --git a/monitor/hmp.c b/monitor/hmp.c index 0a74247ca66a..f9621ce90aaf 100644 --- a/monitor/hmp.c +++ b/monitor/hmp.c @@ -24,8 +24,8 @@ =20 #include "qemu/osdep.h" #include +#include "hw/core/cpu.h" #include "hw/core/qdev.h" -#include "hw/core/sysemu-cpu-ops.h" #include "monitor-internal.h" #include "monitor-hmp-internal.h" #include "monitor/hmp.h" @@ -447,8 +447,6 @@ static bool get_register(MonitorHMP *hmp, int64_t *pval= , const char *name) static const char *pch; static sigjmp_buf expr_env; =20 -static int get_monitor_def(MonitorHMP *mon, int64_t *pval, const char *nam= e); - static G_NORETURN G_GNUC_PRINTF(2, 3) void expr_error(MonitorHMP *mon, const char *fmt, ...) { @@ -530,8 +528,7 @@ static int64_t expr_unary(MonitorHMP *mon) pch++; } *q =3D 0; - if (!get_register(mon, ®, buf) - && get_monitor_def(mon, ®, buf) < 0) { + if (!get_register(mon, ®, buf)) { expr_error(mon, "unknown register"); } n =3D reg; @@ -1723,43 +1720,6 @@ void monitor_register_hmp_info_hrt(const char *name, g_assert_not_reached(); } =20 -/* - * Set @pval to the value in the register identified by @name. - * return 0 if OK, -1 if not found - */ -static int get_monitor_def(MonitorHMP *hmp, int64_t *pval, const char *nam= e) -{ - CPUState *cs =3D monitor_hmp_get_cpu(hmp); - const MonitorDef *md =3D NULL; - void *ptr; - - if (cs =3D=3D NULL) { - return -1; - } - md =3D cs->cc->sysemu_ops->monitor_defs; - if (md =3D=3D NULL) { - return -1; - } - - for (; md->name !=3D NULL; md++) { - if (hmp_compare_cmd(name, md->name)) { - if (md->get_value) { - *pval =3D md->get_value(hmp, md, md->offset); - } else { - CPUArchState *env =3D monitor_hmp_get_cpu_env(hmp); - ptr =3D (uint8_t *)env + md->offset; - *pval =3D *(int32_t *)ptr; - } - return 0; - } - } - - if (!cs->cc->sysemu_ops->monitor_get_register) { - return -1; - } - return cs->cc->sysemu_ops->monitor_get_register(cs, name, pval); -} - int monitor_hmp_vprintf(MonitorHMP *hmp, const char *fmt, va_list ap) { g_autofree char *buf =3D g_strdup_vprintf(fmt, ap); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b97f144aea5a..3218eae62854 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -42,7 +42,6 @@ #include "exec/watchpoint.h" #ifndef CONFIG_USER_ONLY #include "confidential-guest.h" -#include "monitor/hmp.h" #include "system/reset.h" #include "qapi/qapi-commands-machine.h" #include "system/address-spaces.h" @@ -10852,34 +10851,6 @@ static const Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY =20 -#ifdef CONFIG_HMP -static int64_t monitor_get_pc(MonitorHMP *hmp, const struct MonitorDef *md, - int offset) -{ - CPUArchState *env =3D monitor_hmp_get_cpu_env(hmp); - int64_t ret =3D env->eip + env->segs[R_CS].base; - - if (!(env->hflags & HF_CS64_MASK)) { - ret =3D (int32_t)ret; - } - return ret; -} - -static const MonitorDef x86_monitor_defs[] =3D { -#define SEG(name, seg) \ - { name ".limit", offsetof(CPUX86State, segs[seg].limit) }, - SEG("cs", R_CS) - SEG("ds", R_DS) - SEG("es", R_ES) - SEG("ss", R_SS) - SEG("fs", R_FS) - SEG("gs", R_GS) - { "pc", 0, monitor_get_pc, }, - { NULL }, -#undef SEG -}; -#endif - #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps i386_sysemu_ops =3D { @@ -10893,9 +10864,6 @@ static const struct SysemuCPUOps i386_sysemu_ops = =3D { .write_elf64_note =3D x86_cpu_write_elf64_note, .write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote, .write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote, -#ifdef CONFIG_HMP - .monitor_defs =3D x86_monitor_defs, -#endif .legacy_vmsd =3D &vmstate_x86_cpu, }; #endif diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 9b52ad5fc234..ad7303305848 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -25,7 +25,6 @@ #include "disas/capstone.h" #ifndef CONFIG_USER_ONLY #include "migration/vmstate.h" -#include "monitor/hmp.h" #endif =20 #include "cpu.h" @@ -666,32 +665,11 @@ static const VMStateDescription vmstate_m68k_cpu =3D { }, }; =20 -#ifdef CONFIG_HMP -static const MonitorDef m68k_monitor_defs[] =3D { - { "ssp", offsetof(CPUM68KState, sp[0]) }, - { "usp", offsetof(CPUM68KState, sp[1]) }, - { "isp", offsetof(CPUM68KState, sp[2]) }, - { "sfc", offsetof(CPUM68KState, sfc) }, - { "dfc", offsetof(CPUM68KState, dfc) }, - { "urp", offsetof(CPUM68KState, mmu.urp) }, - { "srp", offsetof(CPUM68KState, mmu.srp) }, - { "dttr0", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR0]) }, - { "dttr1", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR1]) }, - { "ittr0", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR0]) }, - { "ittr1", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR1]) }, - { "mmusr", offsetof(CPUM68KState, mmu.mmusr) }, - { NULL }, -}; -#endif - #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps m68k_sysemu_ops =3D { .has_work =3D m68k_cpu_has_work, .get_phys_addr_debug =3D m68k_cpu_get_phys_addr_debug, -#ifdef CONFIG_HMP - .monitor_defs =3D m68k_monitor_defs, -#endif }; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5fff9d745e9b..9a57873ea5d3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3015,7 +3015,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops =3D= { .legacy_vmsd =3D &vmstate_riscv_cpu, #ifdef CONFIG_TCG .translate_for_debug =3D riscv_cpu_translate_for_debug, - .monitor_get_register =3D riscv_monitor_get_register_legacy, #endif }; #endif diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 5d84e4de960a..09aa2701197e 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -263,7 +263,4 @@ static inline int insn_len(uint16_t first_word) return (first_word & 3) =3D=3D 3 ? 4 : 2; } =20 -int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, - int64_t *pval); - #endif diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 7e61ae2a4717..20f3ba57ae57 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -19,10 +19,7 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/ctype.h" -#include "qemu/qemu-print.h" #include "cpu.h" -#include "target/riscv/tcg/csr.h" #include "cpu_bits.h" #include "monitor/monitor.h" #include "monitor/hmp.h" @@ -247,140 +244,3 @@ void hmp_info_mem(MonitorHMP *hmp, const QDict *qdict) mem_info_svxx(hmp, env); } #endif /* CONFIG_HMP */ - -#ifdef CONFIG_TCG -static bool reg_is_ulong_integer(CPURISCVState *env, const char *name, - target_ulong *val, bool is_gprh) -{ - const char * const *reg_names; - uint64_t *vals; - - if (is_gprh) { - reg_names =3D riscv_int_regnamesh; - vals =3D env->gprh; - } else { - reg_names =3D riscv_int_regnames; - vals =3D env->gpr; - } - - for (int i =3D 0; i < 32; i++) { - g_auto(GStrv) reg_name =3D g_strsplit(reg_names[i], "/", 2); - - g_assert(reg_name[0]); - g_assert(reg_name[1]); - - if (g_ascii_strcasecmp(reg_name[0], name) =3D=3D 0 || - g_ascii_strcasecmp(reg_name[1], name) =3D=3D 0) { - *val =3D vals[i]; - return true; - } - } - - return false; -} - -static bool reg_is_u64_fpu(CPURISCVState *env, const char *name, uint64_t = *val) -{ - if (qemu_tolower(name[0]) !=3D 'f') { - return false; - } - - for (int i =3D 0; i < 32; i++) { - g_auto(GStrv) reg_name =3D g_strsplit(riscv_fpr_regnames[i], "/", = 2); - - g_assert(reg_name[0]); - g_assert(reg_name[1]); - - if (g_ascii_strcasecmp(reg_name[0], name) =3D=3D 0 || - g_ascii_strcasecmp(reg_name[1], name) =3D=3D 0) { - *val =3D env->fpr[i]; - return true; - } - } - - return false; -} - -static bool reg_is_vreg(const char *name) -{ - if (qemu_tolower(name[0]) !=3D 'v' || strlen(name) > 3) { - return false; - } - - for (int i =3D 0; i < 32; i++) { - if (g_ascii_strcasecmp(name, riscv_rvv_regnames[i]) =3D=3D 0) { - return true; - } - } - - return false; -} - -int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, - int64_t *pval) -{ - RISCVCPU *hart =3D RISCV_CPU(cs); - CPURISCVState *env =3D cpu_env(cs); - target_ulong val =3D 0; - uint64_t val64 =3D 0; - int i; - - if (reg_is_ulong_integer(env, name, &val, false) || - reg_is_ulong_integer(env, name, &val, true)) { - *pval =3D riscv_cpu_is_32bit(hart) ? (int32_t)val : val; - return 0; - } - - if (reg_is_u64_fpu(env, name, &val64)) { - *pval =3D val64; - return 0; - } - - if (reg_is_vreg(name)) { - if (!riscv_cpu_cfg(env)->ext_zve32x) { - return -EINVAL; - } - - qemu_printf("Unable to print the value of vector " - "vreg '%s' from this API\n", name); - - /* - * We're returning 0 because returning -EINVAL triggers - * an 'unknown register' message in exp_unary() later, - * which feels ankward after our own error message. - */ - *pval =3D 0; - return 0; - } - - for (i =3D 0; i < ARRAY_SIZE(csr_ops); i++) { - RISCVException res; - int csrno =3D i; - - /* - * Early skip when possible since we're going - * through a lot of NULL entries. - */ - if (csr_ops[csrno].predicate =3D=3D NULL) { - continue; - } - - if (g_ascii_strcasecmp(csr_ops[csrno].name, name) !=3D 0) { - continue; - } - - res =3D riscv_csrrw_debug(env, csrno, &val, 0, 0); - - /* - * Rely on the smode, hmode, etc, predicates within csr.c - * to do the filtering of the registers that are present. - */ - if (res =3D=3D RISCV_EXCP_NONE) { - *pval =3D riscv_cpu_is_32bit(hart) ? (int32_t)val : val; - return 0; - } - } - - return -EINVAL; -} -#endif diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ae9bdca9df82..89dfb091ca87 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -995,31 +995,12 @@ static const Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY =20 -#ifdef TARGET_SPARC64 -#include "monitor/hmp.h" -#ifdef CONFIG_HMP -static const MonitorDef sparc64_monitor_defs[] =3D { - { "asi", offsetof(CPUSPARCState, asi) }, - { "pstate", offsetof(CPUSPARCState, pstate) }, - { "cansave", offsetof(CPUSPARCState, cansave) }, - { "canrestore", offsetof(CPUSPARCState, canrestore) }, - { "otherwin", offsetof(CPUSPARCState, otherwin) }, - { "wstate", offsetof(CPUSPARCState, wstate) }, - { "cleanwin", offsetof(CPUSPARCState, cleanwin) }, - { NULL }, -}; -#endif -#endif - #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps sparc_sysemu_ops =3D { .has_work =3D sparc_cpu_has_work, .get_phys_addr_debug =3D sparc_cpu_get_phys_addr_debug, .legacy_vmsd =3D &vmstate_sparc_cpu, -#if defined(TARGET_SPARC64) && defined(CONFIG_HMP) - .monitor_defs =3D sparc64_monitor_defs, -#endif }; #endif =20 --=20 2.55.0.543.g5ebe2ebe4ea8