From nobody Sat Sep 26 20:01:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788988135; cv=none; d=zohomail.com; s=zohoarc; b=UVQeqlEdRcuPRpHlflo1FycnjRkNZgZaAOyn1rdrehubPAjktI+lowqbfytii34YDcA9Nw0AR9jOPIppIWpc7cnbQe+YOP9cPS9UZB3voAaFVPpriadDQZfDcNR9GUTCSv6mwAshGe3zuOh/koFfqgXxBv4N4onhvekNIgzKQdE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788988135; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rsVgFCfA8/6VrdcTgI54XidQGha/ag0fLThsBSj5BQc=; b=fpk9RH5Fr0y9pgYPyE1IA/zdpUjbF5SOUqu/3dkujkdoRrC6ht93Qfx3QDG762vzdTFyA5VeFIX31E6GgnmymBmdLCh1o2OZDtYHxg+lmakJMtQj2tJD8SqqcPvNF9FCmZSph7rwCVaYybtJJIrK7sw7rdR2YScXtekjGhRscZw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788988135869451.4358853551356; Wed, 9 Sep 2026 14:08:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x4PWd-0000wq-TH; Wed, 09 Sep 2026 17:08:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x4PWc-0000wU-9h for qemu-devel@nongnu.org; Wed, 09 Sep 2026 17:08:10 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x4PWa-0000Vp-Ku for qemu-devel@nongnu.org; Wed, 09 Sep 2026 17:08:09 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 689JI6na2363657 for ; Wed, 9 Sep 2026 21:08:07 GMT Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gkcydrmkg-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 09 Sep 2026 21:08:06 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-93903982af1so1294125585a.3 for ; Wed, 09 Sep 2026 14:08:06 -0700 (PDT) Received: from QCOM-UWl2o8bcGT.qualcomm.com ([177.18.66.131]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-91040646d59sm151811336d6.8.2026.09.09.14.08.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 14:08:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=rsVgFCfA8/6 VrdcTgI54XidQGha/ag0fLThsBSj5BQc=; b=AUZtL2DavxkxGIix4C0ZuI+rG7a x6n+8g3JaiF3JN9IBWxaPyeTka6WKHBAuHRlo8W3A0uQHRirEZHQ+EZELmf8X/DJ nMTit6wuxTStdfXmRs//pZM5GSPmx/enuHm9OtPkN+1Yr2omu9LRb6Pf8TQDLnpL i5YER+LVj0v0fgG+C3D6eJSvctnSZDrA2kXmUz0bpnUycrA4EHzB09S2zDxHw0Ce fQ7S1mMdXKeJlo4sz6dhKIWlBeOF6wCj0jp9twosDnepDbXZAcWrItRuXzU+4mIu jRnOAwD+/Ly/ZjBgbLgERKblad3/AQp+XqjJtBZdKL5Nn92G8s0haUUFxdQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1788988086; x=1789592886; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=rsVgFCfA8/6VrdcTgI54XidQGha/ag0fLThsBSj5BQc=; b=cVaQDF4wzAzwfhcB5YMWbbdxL5ViNdHVZPhLahBsCXGrFPNIfCiuNGpIWz7m/jmIpN tHU1cN9recyP3HHpKkVvCo5N7mPI9E0/sjNAfRFDxjHtDOev/Hf2YylH36Qmuah4pzL8 qTfEdd4/GwUJMuHGDg2nN4YjKgY7UAioQjVfww38mZupRiajLk/uYl27QNcs6rbKrq/A F4h+0RUpeFAMmaEvVSpyTvUS9a+zPSVLQcaDiNEM/+amgQDJwGL2RCoLIfUHsxS/UhZm BuEXBxgmzuS9apsts850F9xyCb7Z25WJUYGdyWEl1GHDa9aINzZZcyAH8D4oGVeIGJrY Qv9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788988086; x=1789592886; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=rsVgFCfA8/6VrdcTgI54XidQGha/ag0fLThsBSj5BQc=; b=etrUeqg2litzcosWxMByTcAqPMxiV53FQ77xSET4ej6yL//Bqfh59I7OpQIHqCTDpR evDG0036HUh6QfMmHDx4R49bIZQszguTPF/ek95oc5MUjF76yl32XqeO5cPlNFr+qQb8 xNbTdrm7rygLB9bLkk38U8xlr+i/ONoh6oBlgBwJpjxJ5esgmX0SDTz3dcXfxZPZLw+h s1oFfhAzqzus8W3vs6a/crHAgHh7zX3Usp17d2PM+rThxKPUJ++kUAOwi9Bg1VHAf6/T zm88Ebx5tXTYgLtzx1p2Bdc3xw8sBRWVs5DN064/AmreEP/8J0yzgYntiHSJzPq6UZdW /pZw== X-Gm-Message-State: AFuF++kKb+PU8FDfEkMdsNeDH2KcE13aLc28kP14U7dvESrfyMH7vuTA jNMJbNhB3gVRYRBJ1LWEnXg/gop+ZNofsfwrM0uZPE382AhbajqBE+v/qxwWJK6bgAfpcXUW52t cT13o0ytmlmUtb2xxyZqcVsWhgWpDw751x3b93laXMCuoDUxDKHdjDsvoOfw0s60/nw== X-Gm-Gg: AYBFou24dcKcDFidy88hpN7tZ2H1lPJXrBhciJv7pgWpV/myYZoWY3dJBQAMZIbh8qJ x72NK7SoT7owLUWCW//GiQeBMpjMgMoXEcBJFlTmf3BSExpNfnc48ZD9Wdr1yIAo4mROTr5CW8S JDxKFdvOgtvt/pxeyTkSwsGR9UAwyYXQEn01pB39BC50fkUiKkAFvpDcVVbahVJV09Y4HzbbJhb V80yKvprOZ4YkMYPoFWbKMHYqMaQiVBCp4G7yhox9LfV+6T/Wvh1cfKDi+8yJhTjhqoF54igqrn omhkl7YqmUTU8tx2qouFxUt5GbmMG10oiF4DT1yvrhXfOZAMlP51qpLoS/LmNs9oyv3eHCxxK+4 3ianWJPRfPJ7WRxsTpLNGUW0Qrmoy+uZ1Q0mN X-Received: by 2002:a05:620a:1a06:b0:930:f35d:41ba with SMTP id af79cd13be357-939807284bdmr3996662185a.36.1788988085768; Wed, 09 Sep 2026 14:08:05 -0700 (PDT) X-Received: by 2002:a05:620a:1a06:b0:930:f35d:41ba with SMTP id af79cd13be357-939807284bdmr3996655985a.36.1788988085262; Wed, 09 Sep 2026 14:08:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, Daniel Henrique Barboza , Andrew Jones , Sunil V L , Palmer Dabbelt Subject: [PATCH v11 1/5] target/riscv/cpu.c: remove 'bare' condition for .profile Date: Wed, 9 Sep 2026 18:07:51 -0300 Message-ID: <20260909210756.1767711-2-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260909210756.1767711-1-daniel.barboza@oss.qualcomm.com> References: <20260909210756.1767711-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=IfsSymqa c=1 sm=1 tr=0 ts=6aa1cab6 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=CQQxcbsX5Byh3TlVSSGwig==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=JF9118EUAAAA:8 a=FRSEYCzRAAAA:8 a=GhL2bEVCvcqOW28JNKkA:9 a=IoWCM6iH3mJn3m4BftBB:22 a=xVlTc564ipvMDusKsbsT:22 a=H4N_Y-AU75W7NKDNhZlT:22 X-Proofpoint-GUID: IhIDCRU3J4aAMYGY2mb9zVsRaNb9HNIk X-Proofpoint-ORIG-GUID: IhIDCRU3J4aAMYGY2mb9zVsRaNb9HNIk X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDIzNyBTYWx0ZWRfX4tWNZxW8wepU TTlciVsi+CDGoPDWnzRN69t8x4bTuqHvNr8/ce0JV9MqHnULNrLodc7+3Zjcjqm1dhT3VDkBpPY 5+i8h+jQEqtHMWY8+mmHG3Z6Hfupcmg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDIzNyBTYWx0ZWRfXwTkyjpFpI38m RLHuDPJh+7rMClyEfzHZhjV4xhyp6IhlfcGDaDkIzZbcSSUoKUm3SZ7vYUf0ec0cNxuz+8o0AO5 CWAkjatRIOAvAhdHnh3dPH9vkxwFEG/HMoEPE/R0Xm78l0gKrjBx2t3Zl5G2GT8rwR37QnCKSXP bcat9xpLBF6FCjSZ3Rsfe9BASO2lQGCDTVnxhwszMg104DItNgZbxoPFLZvyRNDmjOJmjYVZado iPJDFfYFqkJ1HFRkoNzX2aRsyKg/GAX2OWllY8uSxGyRIL/owtud4hh9SgyV9MXrh0TPi2d67eJ 6fsb+CHs06NrYiEyOH/QinifX4sRfDBaqMe3KGxG2P5/foO6oQobLUMxGCuHjASePS1+QbLL6oU HMZM6J3Nup1LuJ413KMdlcq0mgyGksDuNafuXo18jUbKVg4W961LClvZRQ4pjIoqfu2jhLAqwvT R10ImQkw0wTJg3yTqhA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-09_01,2026-09-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 spamscore=0 adultscore=0 suspectscore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609090237 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788988137634158501 Content-Type: text/plain; charset="utf-8" We want to configure other CPU types to use profiles as an alternative to adding every profile extension explicitly, i.e. a profile is nothing more than an extension bundle. This means that a vendor CPU can set .profile=3Drva23s64 while having the same handling as any other vendor CPU. Same thing with all other CPU types. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Chao Liu Reviewed-by: Sunil V L --- target/riscv/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c71986da61..773aeba8da 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3103,7 +3103,6 @@ static void riscv_cpu_class_base_init(ObjectClass *c,= const void *data) mcc->def->bare |=3D def->bare; if (def->profile) { assert(profile_extends(def->profile, mcc->def->profile)); - assert(mcc->def->bare); mcc->def->profile =3D def->profile; } if (def->misa_mxl_max) { --=20 2.43.0 From nobody Sat Sep 26 20:01:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788988141; cv=none; d=zohomail.com; s=zohoarc; b=Z/fDjme4dpnUMdD30tCaQhLuH3+xN35xbDwWAP9AAQhavXMUz126IEyvApNSnIodM68ppnupVSSR4umn7PpGOpn6KMuk0jg4Dpa/NK8g5yGKbhV+Kfe8fjnEVfWrBJmR+7vWRrPf8FYIYIjw/QQ3WUsYYfE3d6MZml+u97alrEo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788988141; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=S1lXxqviL5/yxkT8bRuVehG/I464kIAL8gID/sBy0xc=; b=ReR5JlHe0z9kkeg8Rzsmipx/N4DOuobY7pc/V8ofRM2oo4YiTiLz5dC8s3RT/h6O7ORVgRNyXUgGdEXsQmwt9RkEt3YC/CrZ4SO3e7qYGGg06Aiydh4C/S2AoAiQKqCYfeibJhEaQpSBBnp6mmEx3FUsNHoSA1lGW0uJcqYAM24= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788988141532317.7667867946617; Wed, 9 Sep 2026 14:09:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x4PWi-0000yD-Lt; Wed, 09 Sep 2026 17:08:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x4PWg-0000xM-KN for qemu-devel@nongnu.org; Wed, 09 Sep 2026 17:08:14 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x4PWe-0000WU-8j for qemu-devel@nongnu.org; Wed, 09 Sep 2026 17:08:13 -0400 Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 689JI4fq1686922 for ; Wed, 9 Sep 2026 21:08:11 GMT Received: from mail-qv1-f69.google.com (mail-qv1-f69.google.com [209.85.219.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gkcyg0jys-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 09 Sep 2026 21:08:10 +0000 (GMT) Received: by mail-qv1-f69.google.com with SMTP id 6a1803df08f44-91043af01d9so98859516d6.2 for ; Wed, 09 Sep 2026 14:08:10 -0700 (PDT) Received: from QCOM-UWl2o8bcGT.qualcomm.com ([177.18.66.131]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-91040646d59sm151811336d6.8.2026.09.09.14.08.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 14:08:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=S1lXxqviL5/ yxkT8bRuVehG/I464kIAL8gID/sBy0xc=; b=epg+rKeuj1VVd2W/I8UNGMsg4P1 cVCbLLKMP1cDX45IBsWN4YmmOhzY/t0wcU+PqOaavhn11kbaGko5/L3a5PCsuXE/ HRMaItuOaH/gipPdhpX59k3RUUnA3ap0zguCovgGcjNSav36xfDJofBBy8mgt3Ai Iygtf8x5Gabt0Smm24E9Pid+EbUJmEsl58IU6be4aPm89PXOVvPgBsK6IlVaOjL8 0YtWL0XbkLcSDQ1mdF3VBQLOoBvMxysEycjgLQdhcgpbxVRmAjj4WXeObcksvw8d 3MWnOng7v3DNv1GOgW3v+QqIOcwgaPdQR482duj1fawpKbKAvElAs4lA7GQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1788988090; x=1789592890; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=S1lXxqviL5/yxkT8bRuVehG/I464kIAL8gID/sBy0xc=; b=j8DpMMclukC6aqKPk+WQCL8Rix0kclskmD1IMMUibE1OMNIemFsxaeXybeCKOilQqz mofnvXJqXvbz4sezj52hWY1y6BaHMzRCDHd3Bc0tlnwM48nsdu6LUsUpSM2Yt2CMw7Ov YI1wjCtRsg0RoQbP8cv/88PjQHlyn7gcj8bEdb1y4lLEfV2NJwXMgLa3wx/ZPX3kLOBf oGevtaevlY4InP4dcG8ohk6D6l8XDWwBPF9Vh5vyUsoOU0pd19KADIm26RuD1oDQgbIN 9S/0tlMDo2Cwu3w9sWTtSmpEfRcs6Xj8QeiJECyqK9rO4BglLg3lcOemBarRtGZQTJka kBfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788988090; x=1789592890; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=S1lXxqviL5/yxkT8bRuVehG/I464kIAL8gID/sBy0xc=; b=rbSbu8IEUFSMCLtLaKH4dmDyBjDamYd1m58natwUvL/xVFuPasVp5oiRhYAgVS3jX7 TDK6yS08gl437dA8ge2Bu1XfPZJk3TENqfoAQoXOxS05mBTcGGqEOyKWcBS5kxqK4NrY Ymyn6CdmWqLDT0iDqWgKpiY+aewrLcJw0qpKZwWVYjUfdz6EwjFhF02fyILt5hkiLOp6 URRBBHJqc2t1aldbSLPb9YqQn1B+gZJmgCroEoBAYkA19VJhZBJDTn1J5DrG8x14s9vR seK9xI/jjnWNekcFualgXSD8HkD4834W4SakbLClM9lWMd3PhOh7H7j2uMjZKnaeGQ9n RMjQ== X-Gm-Message-State: AFuF++nkRW4dSdiwOqSz4YQ1SjdHiKcLBvqWTnqr7WcQJMpDb7hQ1r59 y5QRjjM4o9OE4tzfx3Iyf8eaHdGVItQyFPRLV6nIzxp2gFrEw7iRHa6JKevUPYzXUGAaXu2Fz4h h69GHPMKT/PWRn/O4yo6aRmZQ4ghXlkt9mC/Oe1e8W2YF2jpRb7ADV3KX5+mxxoN7iQ== X-Gm-Gg: AYBFou3ySW2unYmVavLsvEthm5pyrBEkh1vmLtLklPaTrCXCKgAY6IK4zp2BYGAhrE/ wB73yDcW46ZKOVBmLObL9I3W0cExrvkJ/WqAlLdaDwTi7StZQFZQJRwiV4/jY0ayH/G6nMwY49A ShTUMVbydeQOQO8P60sC/3vhaispPx/H07ztgZspuu+YjBQ5W4049D/hYbGhJHTzoxSyoRRl/Sm fT7uakbbpMTtGyBZfrMKy18PXg9IaEGIgwibopet7Ik/X5Iu/n2dtlHm1jPegqToyJlIgmy+aFT pdUgoNoCW+XVm4o/qOqeYvEPlFrEk7BKsVhcPie6vY5KXqHxwZp0uc9e2OkNDhkEy5AceyNWF2M v4sLwwjSIfWSn8kDoLGvJDwLZuUuCnnwScIzJ X-Received: by 2002:a05:6214:d88:b0:910:6f9c:5b8 with SMTP id 6a1803df08f44-9106f9c072emr67009366d6.9.1788988089502; Wed, 09 Sep 2026 14:08:09 -0700 (PDT) X-Received: by 2002:a05:6214:d88:b0:910:6f9c:5b8 with SMTP id 6a1803df08f44-9106f9c072emr67008836d6.9.1788988089032; Wed, 09 Sep 2026 14:08:09 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, Daniel Henrique Barboza , Icenowy Zheng , Matheus Ferst , Sunil V L , Palmer Dabbelt Subject: [PATCH v11 2/5] target/riscv: add riscv-server-ref CPU Date: Wed, 9 Sep 2026 18:07:52 -0300 Message-ID: <20260909210756.1767711-3-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260909210756.1767711-1-daniel.barboza@oss.qualcomm.com> References: <20260909210756.1767711-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=bMqDs/+Z c=1 sm=1 tr=0 ts=6aa1caba cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=CQQxcbsX5Byh3TlVSSGwig==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=V1jnuoLLAAAA:20 a=EUspDBNiAAAA:8 a=JF9118EUAAAA:8 a=PXcuKL70AAAA:8 a=FRSEYCzRAAAA:8 a=zLUtPzHEVTZWnbMtJKMA:9 a=OIgjcC2v60KrkQgK7BGD:22 a=xVlTc564ipvMDusKsbsT:22 a=1qLaeP4TCVy2vqIEy19U:22 a=H4N_Y-AU75W7NKDNhZlT:22 a=bA3UWDv6hWIuX7UZL3qL:22 X-Proofpoint-GUID: S9tPfpyl7LCbuVn9FpJmmaMBXLmKQyAP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDIzNyBTYWx0ZWRfX7qhdyOlwbl8L ogo1FxMx+sFCzhs9o49STa4mS3FxQeHxdTFIYjmbwjtmNGIhLZXdpHLMyClRkwjXq7f5Am48I6g QA86nGYeyAsgBcVrWLRP1ueN0PkBkYlZXkTy1MqdNpvkT6WMmKL2WxNrGWC4zBbRscFGKQ/Jzab NfdBdRLtm1fiHYGfggKFU9NBQnxTJp2raqgcShszeZV2dEXSSWAFmYDbYewKdVR7rdjo4maaXMA QzGAgM5igCZa0gqpvmn5446qd6+7IM5ZidDnEEVEKC4ih0TjIaEqQ7v5sk0vLrnSNqt/FpGhvkm rV/Smiypqae4019FutVCRYfD9VatfP8pKHdW7wYJTrBN6Hzo/V1ylFX0tqkK8FLeTMEFwkXxRhi 842K/gTU14evMbIf2gxrPXd/M1kyeVyXd9LSw9oPXWJ6Cx+QkzliCGZhqj6sZaJ/YqjVPnEBXWB QD+0yGv1sEZxrrWw4Lg== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDIzNyBTYWx0ZWRfX66wVoSPwXisb MOHuaUaVKucPNbiVzZirL2nxAalwJxyj0dtdnEOP1SEOwENJDiEoNJ/ZbbaWhxVdCexTUpveJ5F CBAV31SF5AZsMHkLx5On5DIsNtBPMDk= X-Proofpoint-ORIG-GUID: S9tPfpyl7LCbuVn9FpJmmaMBXLmKQyAP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-09_01,2026-09-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 malwarescore=0 adultscore=0 suspectscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609090237 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788988143793158500 Content-Type: text/plain; charset="utf-8" The harts requirements of RISC-V server platform [1] require RVA23 ISA profile support and others. We're going for a profile-based implementation, instead of a regular CPU that can inherit RVA23, to allow future CPUs to use it internally as a starting base for their own extension sets. There's also a new 'rvserver-ref-1.0' flag that can be used to set the extensions in the command line for other CPUs, which can be used for testing/debugging purposes. Note that for all intents and purposes "riscv-server-ref" is a regular CPU and no, we're not trying to set a precedent of calling the riscv server platform spec a profile. [1] defines in rule SEE_020 that we must support at least 11 debug triggers (4 for insn address, 4 for insn load/store, 1 for icount, one for int, one for excp). We're going for the minimum. If more triggers are needed users can set any trigger amount with: -cpu riscv-server-ref,trigger-count=3DN Note that N must be <=3D 128. [1] https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server= _platform_requirements.adoc Suggested-by: Icenowy Zheng Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Matheus Ferst Reviewed-by: Chao Liu Reviewed-by: Sunil V L Reviewed-by: Andrew Jones --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 1a28f1369c..61234842e3 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -42,6 +42,7 @@ #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") #define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64") #define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64") +#define TYPE_RISCV_CPU_RVSERVER_REF RISCV_CPU_TYPE_NAME("riscv-server-= ref") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 773aeba8da..0b0b8e0a99 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2424,11 +2424,36 @@ static RISCVCPUProfile RVA23S64 =3D { } }; =20 +/* + * This riscv-server-ref entry isn't a profile per se but its + * CPU definition can be modelled as a profile that extends + * RVA23, with additional things on top of it, and allowing + * future CPUs to derive from it via + * ".profile =3D &RVServerRef1_0;". + */ +static RISCVCPUProfile RVServerRef1_0 =3D { + .s_parent =3D &RVA23S64, + .name =3D "riscv-server-ref-1.0", + .satp_mode =3D VM_1_10_SV48, + .ext_offsets =3D { + CPU_CFG_OFFSET(ext_zkr), + CPU_CFG_OFFSET(ext_sdext), + CPU_CFG_OFFSET(ext_sdtrig), + CPU_CFG_OFFSET(ext_ssaia), + CPU_CFG_OFFSET(ext_ssccfg), + /* ssstrict is always enabled for PRIV_VER_1_12 */ + + RISCV_PROFILE_EXT_LIST_END + } +}; + + RISCVCPUProfile *riscv_profiles[] =3D { &RVA22U64, &RVA22S64, &RVA23U64, &RVA23S64, + &RVServerRef1_0, NULL, }; =20 @@ -3766,6 +3791,13 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif ), =20 + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSERVER_REF, TYPE_RISCV_BARE_CPU, + .profile =3D &RVServerRef1_0, + .misa_mxl_max =3D MXL_RV64, + .cfg.max_satp_mode =3D VM_1_10_SV57, + .num_triggers =3D 11, + ), + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, .cfg.max_satp_mode =3D VM_1_10_SV57, --=20 2.43.0 From nobody Sat Sep 26 20:01:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788988148; cv=none; d=zohomail.com; s=zohoarc; b=exggmbZMFdYX7K6p9RWdQGwhKfFE4mnTTH+BeCpXUpnhy8hpfuYzlxciQE+RSMw6nD2hkwDIZzvnkuUXJDjyZ4jIfy0mtxrjC6Di8SSlmu3wysmPEpnCI4OIQ/6TPY+XUHMEQmS82kfdDELqqYQbOEFm1PWUGIKzM2C3j4k65c0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788988148; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=tte2nRlzGxWUqO12ksBuvU9I+oOWeNatFnn+t4eh9/0=; b=kMRsmRGtLtOpXNhc0i6GsYvSFuTP+9azO3+RQxgpR6RvYKgdi88dpbtUK97mOTQMsriY5pUxxI6+63z6LcikvcfeYEtInkUiWkp8CeYN0ZwKD+Bu9yhEIiBPbd0FpsQNflXTAWu3szAnw/e0Cr89G9QdHWaf8X3VSGbGhs1lWo8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788988148016724.7317396100252; Wed, 9 Sep 2026 14:09:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x4PX4-00013j-K8; Wed, 09 Sep 2026 17:08:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x4PWm-0000yM-Km for qemu-devel@nongnu.org; Wed, 09 Sep 2026 17:08:21 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x4PWi-0000XH-Ss for qemu-devel@nongnu.org; Wed, 09 Sep 2026 17:08:20 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 689JI6bc2363667 for ; Wed, 9 Sep 2026 21:08:15 GMT Received: from mail-qv1-f72.google.com (mail-qv1-f72.google.com [209.85.219.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gkcydrmkw-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 09 Sep 2026 21:08:15 +0000 (GMT) Received: by mail-qv1-f72.google.com with SMTP id 6a1803df08f44-90e8dd8be81so74836316d6.0 for ; Wed, 09 Sep 2026 14:08:15 -0700 (PDT) Received: from QCOM-UWl2o8bcGT.qualcomm.com ([177.18.66.131]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-91040646d59sm151811336d6.8.2026.09.09.14.08.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 14:08:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=tte2nRlzGxW UqO12ksBuvU9I+oOWeNatFnn+t4eh9/0=; b=hO1oqxrgHX1o2kkNO1PI8/nIafd 277X+LYjMdggs3kYK1KyC59vzCrTERGp5D7qdxhipHoLpC5cLvLTrIT/QcfIUTGs TN0JZhlC5zHTtyjykg3xpQzw6LsxK4mTqBq3kq8pUvy/99bevW4SJyTTLilhr8dB Jj7hdQE2FbRhT2kM5VIu3Z8J4jFmaspJkwLGGo3eXhK5pXO9p4ctmkZmDfuuCwAs eVv8qLf1g+CpdW59pMYp1HOI0wNd4a4LToF1kWOFXFCuSKNAXeWq0JLutjoqRCx6 UdfD2/kYFQHRZvgTnZ/efGyjeFCudPYnMhvfkuzJxYks2Lf1uhqcQdZtD9g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1788988094; x=1789592894; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=tte2nRlzGxWUqO12ksBuvU9I+oOWeNatFnn+t4eh9/0=; b=bbazNIjEwz0deMMqekNRluRIzIPH8pYb/BiMmXBt0pEVJnTLyejMbMHjN9AxilxBGD u1Tq+h7QvQGN3PzzpFE1Kf+Ukxpydil2Jjix9FzqlJsIpfa2ItFA++vlOTIEDbtf5okp VSBRjIUeb1+lZN2u2hKrqliuwxftkCw+aMPHcVfTpQ/llo07TlBsh4V8NNKqed+zuKGV +ej56m5SY83Wmuu00BQRB2n3V7w7Uq59wTDqlcBOGlEEeyetpNPyMjN2P9BkAml66+ol k74lUKNFMShmlX114Vf6wDMYMifUO4ZwaLpzWwmBanLQM2PMv3maZOt4S8/HOGFGx+mL VQlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788988094; x=1789592894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=tte2nRlzGxWUqO12ksBuvU9I+oOWeNatFnn+t4eh9/0=; b=jHF9XD+o2s7xDpxm5FUZrNBwxJ1TIDxToBkZDArnBpFUKkQ4K96YNj4CO5A9ZmMYk0 qa63ccpLqJ/K8Lhz2nTKsTH4zARbZKcV/q59nm7IiLxtKUwVq/hiFai5fR3f8rBIn33h F/Wh5svXuPhWzhj3euHsc6HjPepem0lEO+UTZlvFOu1NJZlmpM82tN+67ND9i3a2SHrg v/sGbQEV+EgWbPeEdEHAFguA4wrr3jCiJZnGy1gIBkUwR5lf/GXw+OA65rjBc+p/U/Iw UZUjxF2p+OWAK0D0FoUF3xYKpdan1njPZeGsGva122yUE6Ufc7fpXHH7McqvvDdMQbwL r+rQ== X-Gm-Message-State: AFuF++m3Gwxj0nosjXUn/SFcmNzHbimVIgodlhvDxOIs2A3OaQVqssaz 54WBbFJ0+nt+zuaoYxeT17tCubtAb8XYSsyWh0INcAgj6Np3BAhkYDPmMGkunQ5/CRrbEAboz+T z0tcwFBKl/DCzvHoIVaK3+TLc5SO+3NpgA8lb9Sjg9ZSDQuVjm7PYDCxbYLb/KcfnNw== X-Gm-Gg: AYBFou0ijvbMg9ybTnnc/Fs8YNxaOJ5GEbOpuSDAdJrAC9Owb7YWJgk9/pK8mgeoONf 8svpYP6IPkyYJSye0Q6tFbXAMpucnjTcM/oiOJ36gWwDk83oLlNN5PeaKwVUl5f/7U+xZ41Y2uw B12FMTLNGzfwvPC3f4Mdo3+y8jeROVt0y0ZTG4B0NcmLI5tZvGjUD03NJEBeAzUimDI5OfgBMU6 kvYmvX5HvxzllTtk94gyNs2XQwFOYpgLd0bIxKkARoZokIOqp3NRgIhtmOSmXh5Qa54WknUBPWw odctAWCeMJzLcO+Rz5f5pXy5ryYy0kAafPezr0vEbPp4QZdpQTNZj43GUl3W7BGL8Y/wEdqpSjo 6RhoE3Cui6cBp9PHn8FIikckzy/5uhADhXglO X-Received: by 2002:a05:6214:202b:b0:910:cd4:23a with SMTP id 6a1803df08f44-9103ef980c2mr494408266d6.20.1788988093349; Wed, 09 Sep 2026 14:08:13 -0700 (PDT) X-Received: by 2002:a05:6214:202b:b0:910:cd4:23a with SMTP id 6a1803df08f44-9103ef980c2mr494406906d6.20.1788988092404; Wed, 09 Sep 2026 14:08:12 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, Daniel Henrique Barboza , Nutty Liu , Sunil V L , Paolo Bonzini , Palmer Dabbelt Subject: [PATCH v11 3/5] hw/riscv: server platform reference machine Date: Wed, 9 Sep 2026 18:07:53 -0300 Message-ID: <20260909210756.1767711-4-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260909210756.1767711-1-daniel.barboza@oss.qualcomm.com> References: <20260909210756.1767711-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=IfsSymqa c=1 sm=1 tr=0 ts=6aa1cabf cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=CQQxcbsX5Byh3TlVSSGwig==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=NEAV23lmAAAA:8 a=NLiCwHATAAAA:8 a=EUspDBNiAAAA:8 a=69EAbJreAAAA:8 a=FRSEYCzRAAAA:8 a=9kP_nYF4JKOc7euzSxIA:9 a=2KoRbIiLB8rUyhBb:21 a=pJ04lnu7RYOZP9TFuWaZ:22 a=F9tHCgz3TLBaZgltkx5D:22 a=H4N_Y-AU75W7NKDNhZlT:22 X-Proofpoint-GUID: 0erzGOsNqx-fe9RuVSeB0pTo4Mn1DIgU X-Proofpoint-ORIG-GUID: 0erzGOsNqx-fe9RuVSeB0pTo4Mn1DIgU X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDIzNyBTYWx0ZWRfX6SoaIsckXQJd +79cMa85RNOlTrcu7St11t14FKOnrQ4vMsBrP2iqL3fGgzIjldk1LPoL1KioLYup7xgTs1n5HFN 0IdqBgiUK6gn9/THrczVUDjtkVfybQk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDIzNyBTYWx0ZWRfX35s/fCwasCAD QUBc4WW95jSGdvkkqiITn2dhLLS0E6DbTCRygIUOjKKWJ0ikRuVPYQunLxi0ycZPUn3FWaEuqyp ZSXWWMe5BXLnE4M/TXfeYEVqjGb53lbJMENaoGoAUfC+xWLSfrMZxMxudo/Elmr7fsiIEPYpO24 4GsM7mI6Mho+IIHwQDIe/NZ7s03bnknWNWt4aLgGSUR3gtnRE/AQVrDWAun8DglQzMa1VTVy1T5 Jb9ml4gKpS9zB1WQ0tnMgqDtIbZfJAKNgOrIgHhl/l/pTt8WhLLARtxeiTz2dMCis5s0boyblAj WVTMxlPjP+2mcjze4akkBL5rLBifTxMIOUK/jRi+Aw5xsI720Lc5KaViDFGJMkGnflYGAfYCNqi XcGD/Ef7o3Ltns1XySdX1TvreG6Mut4Th+iTG9J7ANGRoWfWD0a24YVWEAEDras3aTag1FEZHAt iI+yoUJ3tZ9o2maQgSQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-09_01,2026-09-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 spamscore=0 adultscore=0 suspectscore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609090237 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788988150000158501 Content-Type: text/plain; charset="utf-8" The RISC-V Server Platform specification [1] defines a standardized set of hardware and software capabilities, that portable system software, such as OS and hypervisors can rely on being present in a RISC-V server platform. The main features included in this emulation are: - Based on riscv virt machine type; - A new memory map as close as virt machine as possible; - An always present IOMMU platform device (riscv-iommu-sys) that uses IRQs 36 to 39, one IRQ for queue, similar to the 'virt' board; - AIA; - PCIe AHCI; - PCIe NIC; - No virtio device; - No fw_cfg device; - No ACPI table provided; - Only minimal device tree nodes; - a platform bus for TPM support. A note about TPM support: TPM devices in QEMU comes usually in two flavors - emulated or passthrough. A passthrough device requires a host TPM device that the QEMU process can borrow and it's usually coupled with KVM acceleration. To use the TPM emulator we'll need help from an external TPM emulator called swtpm. More info can be found in [2]. For our purposes this is a process that, if running Ubuntu, can be installed via 'swtpm' package. We'll go back to it shortly. For now, adding support for the emulated TPM device 'tpm-tis' (other TPM flavors might work as well, 'tpm-tis' is the one tested with this work) requires a platform bus. Adding a platform bus will open the door for more devices to be added in the board. This is ok - a reference board isn't a restricted board and users are free to add devices at their leisure. Here's how to use tpm-tis with the riscv-server-ref board: - in a separated shell/term run 'swtpm' (--log is optional): $ mkdir /tmp/mytpm1 $ swtpm socket --tpmstate dir=3D/tmp/mytpm1 \ --ctrl type=3Dunixio,path=3D/tmp/mytpm1/swtpm-sock \ --tpm2 \ --log level=3D20 Then start QEMU with: $ qemu-system-riscv64 -M riscv-server-ref (...) \ -chardev socket,id=3Dchrtpm,path=3D/tmp/mytpm1/swtpm-sock \ -tpmdev emulator,id=3Dtpm0,chardev=3Dchrtpm\ -device tpm-tis-device,tpmdev=3Dtpm0 [1] https://github.com/riscv-non-isa/riscv-server-platform [2] https://qemu-project.gitlab.io/qemu/specs/tpm.html Signed-off-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Reviewed-by: Chao Liu Reviewed-by: Sunil V L --- configs/devices/riscv64-softmmu/default.mak | 1 + hw/riscv/Kconfig | 16 + hw/riscv/meson.build | 1 + hw/riscv/server_platform_ref.c | 790 ++++++++++++++++++++ 4 files changed, 808 insertions(+) create mode 100644 hw/riscv/server_platform_ref.c diff --git a/configs/devices/riscv64-softmmu/default.mak b/configs/devices/= riscv64-softmmu/default.mak index a8e4d0ab33..ae3f62e2d4 100644 --- a/configs/devices/riscv64-softmmu/default.mak +++ b/configs/devices/riscv64-softmmu/default.mak @@ -9,6 +9,7 @@ # CONFIG_SIFIVE_E=3Dn # CONFIG_SIFIVE_U=3Dn # CONFIG_RISCV_VIRT=3Dn +# CONFIG_RISCV_SERVER_PLATFORM_REF=3Dn # CONFIG_MICROCHIP_PFSOC=3Dn # CONFIG_SHAKTI_C=3Dn # CONFIG_XIANGSHAN_KUNMINGHU=3Dn diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index d06ac26648..da59eb2155 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -69,6 +69,22 @@ config RISCV_VIRT select ACPI select ACPI_PCI =20 +config RISCV_SERVER_PLATFORM_REF + bool + default y + depends on RISCV64 + imply TPM_TIS_SYSBUS + select RISCV_NUMA + select GOLDFISH_RTC + select PCI + select PCI_EXPRESS_GENERIC_BRIDGE + select PFLASH_CFI01 + select SERIAL + select RISCV_ACLINT + select RISCV_APLIC + select RISCV_IMSIC + select RISCV_IOMMU + config SHAKTI_C bool default y diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 7aa3c1578d..cc5a019f7c 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -7,6 +7,7 @@ riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('num= a.c')) riscv_ss.add(files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) +riscv_ss.add(when: 'CONFIG_RISCV_SERVER_PLATFORM_REF', if_true: files('ser= ver_platform_ref.c')) riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) diff --git a/hw/riscv/server_platform_ref.c b/hw/riscv/server_platform_ref.c new file mode 100644 index 0000000000..8ee87b2159 --- /dev/null +++ b/hw/riscv/server_platform_ref.c @@ -0,0 +1,790 @@ +/* + * QEMU RISC-V Server Platform Reference Board (riscv-server-ref) + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/error-report.h" +#include "qemu/guest-random.h" +#include "qapi/error.h" +#include "qapi/qapi-visit-common.h" +#include "hw/core/boards.h" +#include "hw/core/platform-bus.h" +#include "hw/core/loader.h" +#include "hw/core/sysbus.h" +#include "hw/core/qdev-properties.h" +#include "hw/char/serial.h" +#include "hw/block/flash.h" +#include "hw/ide/pci.h" +#include "hw/ide/ahci-pci.h" +#include "hw/pci/pci.h" +#include "hw/pci-host/gpex.h" +#include "hw/core/sysbus-fdt.h" +#include "hw/riscv/riscv_hart.h" +#include "hw/riscv/boot.h" +#include "hw/riscv/device-common.h" +#include "hw/riscv/fdt-common.h" +#include "hw/riscv/numa.h" +#include "hw/riscv/iommu.h" +#include "hw/riscv/riscv-iommu.h" +#include "hw/riscv/riscv-iommu-bits.h" +#include "hw/intc/riscv_aclint.h" +#include "hw/intc/riscv_aplic.h" +#include "hw/intc/riscv_imsic.h" +#include "chardev/char.h" +#include "hw/char/serial-mm.h" +#include "system/device_tree.h" +#include "system/runstate.h" +#include "system/system.h" +#include "system/kvm.h" +#include "system/qtest.h" +#include "system/tcg.h" +#include "kvm/kvm_riscv.h" +#include "system/tpm.h" +#include "system/qtest.h" +#include "target/riscv/cpu.h" +#include "net/net.h" + +#include "aia.h" + +#define RVSERVER_CPUS_MAX_BITS 9 +#define RVSERVER_CPUS_MAX (1 << RVSERVER_CPUS_MAX_BITS) +#define RVSERVER_SOCKETS_MAX_BITS 2 +#define RVSERVER_SOCKETS_MAX (1 << RVSERVER_SOCKETS_MAX_BITS) + +#define RVSERVER_IRQCHIP_NUM_MSIS 255 +#define RVSERVER_IRQCHIP_NUM_SOURCES 96 +#define RVSERVER_IRQCHIP_NUM_PRIO_BITS 3 +#define RVSERVER_IRQCHIP_MAX_GUESTS_BITS 3 +#define RVSERVER_IRQCHIP_MAX_GUESTS \ + ((1U << RVSERVER_IRQCHIP_MAX_GUESTS_BITS) - 1U) +#define RVSERVER_IRQCHIP_DEFAULT_AIA_GUESTS 5 + +#define NUM_SATA_PORTS 6 + +#define SYSCON_RESET 0x1 +#define SYSCON_POWEROFF 0x2 + +#define RVSERVER_PLATFORM_BUS_NUM_IRQS 8 + +#define TYPE_RISCV_SERVER_REF_MACHINE MACHINE_TYPE_NAME("riscv-server-ref") +OBJECT_DECLARE_SIMPLE_TYPE(RISCVServerRefMachineState, RISCV_SERVER_REF_MA= CHINE) + +struct RISCVServerRefMachineState { + /*< private >*/ + MachineState parent; + + /*< public >*/ + Notifier machine_done; + RISCVHartArrayState soc[RVSERVER_SOCKETS_MAX]; + DeviceState *irqchip[RVSERVER_SOCKETS_MAX]; + PFlashCFI01 *flash[2]; + + int fdt_size; + int aia_guests; + const MemMapEntry *memmap; + + DeviceState *platform_bus_dev; +}; + +enum { + RVSERVER_DEBUG, + RVSERVER_MROM, + RVSERVER_RESET_SYSCON, + RVSERVER_RTC, + RVSERVER_IOMMU_SYS, + RVSERVER_ACLINT, + RVSERVER_APLIC_M, + RVSERVER_APLIC_S, + RVSERVER_UART0, + RVSERVER_IMSIC_M, + RVSERVER_IMSIC_S, + RVSERVER_FLASH, + RVSERVER_DRAM, + RVSERVER_PCIE_MMIO, + RVSERVER_PCIE_PIO, + RVSERVER_PLATFORM_BUS, + RVSERVER_PCIE_ECAM, + RVSERVER_PCIE_MMIO_HIGH +}; + +enum { + RVSERVER_UART0_IRQ =3D 10, + RVSERVER_RTC_IRQ =3D 11, + RVSERVER_PCIE_IRQ =3D 32, /* 32 to 35 */ + IOMMU_SYS_IRQ =3D 36, /* 36 to 39 */ + RVSERVER_PLATFORM_BUS_IRQ =3D 40, /* 40 to 48 */ +}; + +/* + * The server soc reference machine physical address space used by some of= the + * devices namely ACLINT, APLIC and IMSIC depend on number of Sockets, num= ber + * of CPUs, and number of IMSIC guest files. + * + * Various limits defined by RVSERVER_SOCKETS_MAX_BITS, RVSERVER_CPUS_MAX_= BITS, + * and RVSERVER_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization = of + * server reference machine physical address space. + */ + +#define RVSERVER_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHI= FT) +#if RVSERVER_IMSIC_GROUP_MAX_SIZE < \ + IMSIC_GROUP_SIZE(RVSERVER_CPUS_MAX_BITS, RVSERVER_IRQCHIP_MAX_GUESTS_B= ITS) +#error "Can't accomodate single IMSIC group in address space" +#endif + +#define RVSERVER_IMSIC_MAX_SIZE (RVSERVER_SOCKETS_MAX * \ + RVSERVER_IMSIC_GROUP_MAX_SIZE) +#if 0x4000000 < RVSERVER_IMSIC_MAX_SIZE +#error "Can't accomodate all IMSIC groups in address space" +#endif + +static const MemMapEntry rvserver_ref_memmap[] =3D { + [RVSERVER_DEBUG] =3D { 0x0, 0x100 }, + [RVSERVER_MROM] =3D { 0x1000, 0xf000 }, + [RVSERVER_RESET_SYSCON] =3D { 0x100000, 0x1000 }, + [RVSERVER_RTC] =3D { 0x101000, 0x1000 }, + [RVSERVER_IOMMU_SYS] =3D { 0x102000, 0x1000 }, + [RVSERVER_ACLINT] =3D { 0x2000000, 0x10000 }, + [RVSERVER_PCIE_PIO] =3D { 0x3000000, 0x10000 }, + [RVSERVER_PLATFORM_BUS] =3D { 0x4000000, 0x2000000 }, + [RVSERVER_APLIC_M] =3D { 0xc000000, APLIC_SIZE(RVSERVER_CPUS_M= AX) }, + [RVSERVER_APLIC_S] =3D { 0xd000000, APLIC_SIZE(RVSERVER_CPUS_M= AX) }, + [RVSERVER_UART0] =3D { 0x10000000, 0x100 }, + [RVSERVER_FLASH] =3D { 0x20000000, 0x4000000 }, + [RVSERVER_IMSIC_M] =3D { 0x24000000, RVSERVER_IMSIC_MAX_SIZE }, + [RVSERVER_IMSIC_S] =3D { 0x28000000, RVSERVER_IMSIC_MAX_SIZE }, + [RVSERVER_PCIE_ECAM] =3D { 0x30000000, 0x10000000 }, + [RVSERVER_PCIE_MMIO] =3D { 0x40000000, 0x40000000 }, + [RVSERVER_DRAM] =3D { 0x80000000, 0xff80000000ull }, + [RVSERVER_PCIE_MMIO_HIGH] =3D { 0x10000000000ull, 0x10000000000ull }, +}; + +#define RVSERVER_FLASH_SECTOR_SIZE (256 * KiB) + +static void rvserver_flash_maps(RISCVServerRefMachineState *s, + MemoryRegion *sysmem) +{ + hwaddr flashsize =3D rvserver_ref_memmap[RVSERVER_FLASH].size / 2; + hwaddr flashbase =3D rvserver_ref_memmap[RVSERVER_FLASH].base; + + riscv_init_flash_map(s->flash[0], flashbase, flashsize, + sysmem, RVSERVER_FLASH_SECTOR_SIZE); + riscv_init_flash_map(s->flash[1], flashbase + flashsize, flashsize, + sysmem, RVSERVER_FLASH_SECTOR_SIZE); +} + +static void create_fdt_pmu(RISCVServerRefMachineState *s) +{ + g_autofree char *pmu_name =3D g_strdup_printf("/pmu"); + MachineState *ms =3D MACHINE(s); + RISCVCPU *hart =3D &s->soc[0].harts[0]; + + qemu_fdt_add_subnode(ms->fdt, pmu_name); + qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(ms->fdt, hart->pmu_avail_ctrs, pmu_name); +} + +static void create_fdt_sockets(RISCVServerRefMachineState *s, + const MemMapEntry *memmap, + uint32_t *phandle, + uint32_t *irq_mmio_phandle, + uint32_t *irq_pcie_phandle, + uint32_t *msi_pcie_phandle) +{ + int socket, phandle_pos; + MachineState *ms =3D MACHINE(s); + uint32_t msi_m_phandle =3D 0, msi_s_phandle =3D 0; + uint32_t xplic_phandles[MAX_NODES]; + g_autofree uint32_t *intc_phandles =3D NULL; + int socket_count =3D riscv_socket_count(ms); + bool numa_enabled =3D riscv_numa_enabled(ms); + bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); + IMSICFdtProps imsic_fdt_props; + APLICFdtProps aplic_fdt_props; + ACLINTFdtProps aclint_props; + + riscv_fdt_create_cpu_socket_subnode(ms->fdt, + kvm_enabled() ? kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) + : RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); + + intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); + + aclint_props.clint =3D &memmap[RVSERVER_ACLINT]; + aclint_props.aia_type =3D AIA_TYPE_APLIC_IMSIC; + aclint_props.numa_enabled =3D numa_enabled; + + phandle_pos =3D ms->smp.cpus; + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { + hwaddr memaddr =3D s->memmap[RVSERVER_DRAM].base + + riscv_socket_mem_offset(ms, socket); + uint64_t memsize =3D riscv_socket_mem_size(ms, socket); + + phandle_pos -=3D s->soc[socket].num_harts; + + riscv_create_fdt_socket_cpus(ms->fdt, (&s->soc[socket])->harts, so= cket, + s->soc[socket].num_harts, + s->soc[socket].hartid_base, + phandle, &intc_phandles[phandle_pos], + numa_enabled, is_32_bit); + + riscv_create_fdt_socket_memory(ms->fdt, memaddr, memsize, + socket, riscv_numa_enabled(ms)); + + aclint_props.socket =3D socket; + aclint_props.num_harts =3D s->soc[socket].num_harts; + riscv_create_fdt_socket_aclint(ms->fdt, &aclint_props, + &intc_phandles[phandle_pos]); + } + + imsic_fdt_props.soc =3D &s->soc; + imsic_fdt_props.socket_count =3D socket_count; + imsic_fdt_props.smp_cpus =3D ms->smp.cpus; + imsic_fdt_props.imsic_m_base =3D memmap[RVSERVER_IMSIC_M].base; + imsic_fdt_props.imsic_s_base =3D memmap[RVSERVER_IMSIC_S].base; + imsic_fdt_props.imsic_group_max_size =3D RVSERVER_IMSIC_GROUP_MAX_SIZE; + imsic_fdt_props.irqchip_num_msis =3D RVSERVER_IRQCHIP_NUM_MSIS; + imsic_fdt_props.aia_guests =3D s->aia_guests; + + riscv_create_fdt_imsic(ms->fdt, &imsic_fdt_props, phandle, intc_phandl= es, + &msi_m_phandle, &msi_s_phandle); + *msi_pcie_phandle =3D msi_s_phandle; + + aplic_fdt_props.aplic_m =3D !kvm_enabled() + ? &memmap[RVSERVER_APLIC_M] : NULL; + aplic_fdt_props.aplic_s =3D &memmap[RVSERVER_APLIC_S]; + aplic_fdt_props.platform_bus =3D &memmap[RVSERVER_PLATFORM_BUS]; + aplic_fdt_props.platform_bus_irq =3D RVSERVER_PLATFORM_BUS_IRQ; + aplic_fdt_props.num_harts =3D ms->smp.cpus; + aplic_fdt_props.numa_enabled =3D numa_enabled; + aplic_fdt_props.irqchip_num_sources =3D RVSERVER_IRQCHIP_NUM_SOURCES; + aplic_fdt_props.aia_type =3D AIA_TYPE_APLIC_IMSIC; + + phandle_pos =3D ms->smp.cpus; + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { + phandle_pos -=3D s->soc[socket].num_harts; + + aplic_fdt_props.socket =3D socket; + aplic_fdt_props.num_harts =3D s->soc[socket].num_harts; + riscv_create_fdt_socket_aplic(ms->fdt, &aplic_fdt_props, + msi_m_phandle, msi_s_phandle, phandl= e, + &intc_phandles[phandle_pos], + xplic_phandles); + } + + for (socket =3D 0; socket < socket_count; socket++) { + if (socket =3D=3D 0) { + *irq_mmio_phandle =3D xplic_phandles[socket]; + *irq_pcie_phandle =3D xplic_phandles[socket]; + } + if (socket =3D=3D 1) { + *irq_pcie_phandle =3D xplic_phandles[socket]; + } + } + + riscv_socket_fdt_write_distance_matrix(ms); +} + +static void finalize_fdt(RISCVServerRefMachineState *s) +{ + uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; + uint32_t irq_pcie_phandle =3D 1, iommu_sys_phandle; + g_autofree char *name =3D NULL; + MachineState *ms =3D MACHINE(s); + + create_fdt_sockets(s, rvserver_ref_memmap, &phandle, &irq_mmio_phandle, + &irq_pcie_phandle, &msi_pcie_phandle); + + iommu_sys_phandle =3D riscv_create_fdt_riscv_iommu_sys(ms->fdt, + s->memmap[RVSERVER_IOMMU_SYS].bas= e, + s->memmap[RVSERVER_IOMMU_SYS].siz= e, + &phandle, irq_mmio_phandle, + msi_pcie_phandle, IOMMU_SYS_IRQ); + + riscv_create_fdt_pcie(ms->fdt, AIA_TYPE_APLIC_IMSIC, true, + &s->memmap[RVSERVER_PCIE_ECAM], + &s->memmap[RVSERVER_PCIE_PIO], + &s->memmap[RVSERVER_PCIE_MMIO], + &s->memmap[RVSERVER_PCIE_MMIO_HIGH], + irq_pcie_phandle, msi_pcie_phandle, + iommu_sys_phandle, RVSERVER_PCIE_IRQ); + + riscv_create_fdt_syscon(ms->fdt, &phandle, + rvserver_ref_memmap[RVSERVER_RESET_SYSCON].bas= e, + rvserver_ref_memmap[RVSERVER_RESET_SYSCON].siz= e, + SYSCON_RESET, SYSCON_POWEROFF, false); + + riscv_create_fdt_uart(ms->fdt, &rvserver_ref_memmap[RVSERVER_UART0], + RVSERVER_UART0_IRQ, AIA_TYPE_APLIC_IMSIC, + irq_mmio_phandle); + name =3D riscv_fdt_get_uart_nodename(rvserver_ref_memmap[RVSERVER_UART= 0].base); + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); + qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); + + riscv_create_fdt_rtc(ms->fdt, &rvserver_ref_memmap[RVSERVER_RTC], + RVSERVER_RTC_IRQ, AIA_TYPE_APLIC_IMSIC, + irq_mmio_phandle); +} + +static void create_fdt(RISCVServerRefMachineState *s, + const MemMapEntry *memmap) +{ + MachineState *ms =3D MACHINE(s); + uint8_t rng_seed[32]; + g_autofree char *name =3D NULL; + + ms->fdt =3D riscv_create_board_device_tree(MACHINE_GET_CLASS(s)->desc, + "qemu,riscv-server-ref", + &s->fdt_size); + + /* + * This versioning scheme is for informing platform fw only. It is nei= ther: + * - A QEMU versioned machine type; a given version of QEMU will emula= te + * a given version of the platform. + * - A reflection of level of server platform support provided. + * + * machine-version-major: updated when changes breaking fw compatibili= ty + * are introduced. + * machine-version-minor: updated when features are added that don't b= reak + * fw compatibility. + * + * It's the same as the scheme in arm sbsa-ref. + */ + qemu_fdt_setprop_cell(ms->fdt, "/", "machine-version-major", 0); + qemu_fdt_setprop_cell(ms->fdt, "/", "machine-version-minor", 0); + + /* + * The "/soc/pci@..." node is needed for PCIE hotplugs + * that might happen before finalize_fdt(). + */ + name =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIx, + s->memmap[RVSERVER_PCIE_ECAM].base); + qemu_fdt_add_subnode(ms->fdt, name); + + qemu_fdt_add_subnode(ms->fdt, "/chosen"); + qemu_fdt_add_subnode(ms->fdt, "/aliases"); + + /* Pass seed to RNG */ + qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); + qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", + rng_seed, sizeof(rng_seed)); + + riscv_create_fdt_flash(ms->fdt, rvserver_ref_memmap[RVSERVER_FLASH].ba= se, + rvserver_ref_memmap[RVSERVER_FLASH].size / 2); + create_fdt_pmu(s); + +} + +static void rvserver_init_pci_devices(RISCVServerRefMachineState *s, + DeviceState *gpex_host) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(s); + PCIHostState *pci =3D PCI_HOST_BRIDGE(gpex_host); + PCIDevice *pdev_ahci; + AHCIPCIState *ich9; + DriveInfo *hd[NUM_SATA_PORTS]; + + pci_init_nic_devices(pci->bus, mc->default_nic); + + /* IDE disk setup. */ + pdev_ahci =3D pci_create_simple(pci->bus, -1, TYPE_ICH9_AHCI); + ich9 =3D ICH9_AHCI(pdev_ahci); + g_assert(ARRAY_SIZE(hd) =3D=3D ich9->ahci.ports); + ide_drive_get(hd, ich9->ahci.ports); + ahci_ide_create_devs(&ich9->ahci, hd); +} + +static uint64_t rvserver_reset_syscon_read(void *opaque, hwaddr addr, + unsigned size) +{ + return 0; +} + +static void rvserver_reset_syscon_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + switch (val64) { + case SYSCON_POWEROFF: + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + return; + case SYSCON_RESET: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; + default: + break; + } +} + +static const MemoryRegionOps rvserver_reset_syscon_ops =3D { + .read =3D rvserver_reset_syscon_read, + .write =3D rvserver_reset_syscon_write, + .endianness =3D DEVICE_LITTLE_ENDIAN +}; + +static void rvserver_ref_machine_done(Notifier *notifier, void *data) +{ + RISCVServerRefMachineState *s =3D container_of( + notifier, RISCVServerRefMachineState, machine_done); + const MemMapEntry *memmap =3D rvserver_ref_memmap; + MachineState *machine =3D MACHINE(s); + hwaddr start_addr =3D memmap[RVSERVER_DRAM].base; + target_ulong firmware_end_addr, kernel_start_addr; + const char *firmware_name =3D riscv_default_firmware_name(&s->soc[0]); + uint64_t fdt_load_addr; + uint64_t kernel_entry =3D 0; + BlockBackend *pflash_blk0; + RISCVBootInfo boot_info; + + /* + * An user provided dtb must include everything, including + * dynamic sysbus devices. Our FDT needs to be finalized. + */ + if (machine->dtb =3D=3D NULL) { + finalize_fdt(s); + } + + riscv_boot_info_init(&boot_info, &s->soc[0]); + + firmware_end_addr =3D riscv_find_and_load_firmware(machine, &boot_info, + firmware_name, + &start_addr, NULL); + + pflash_blk0 =3D pflash_cfi01_get_blk(s->flash[0]); + if (pflash_blk0) { + if (machine->firmware && !strcmp(machine->firmware, "none")) { + /* + * Pflash was supplied but bios is none and not KVM guest, + * let's overwrite the address we jump to after reset to + * the base of the flash. + */ + start_addr =3D rvserver_ref_memmap[RVSERVER_FLASH].base; + } else { + /* + * Pflash was supplied but either KVM guest or bios is not non= e. + * In this case, base of the flash would contain S-mode payloa= d. + */ + riscv_setup_firmware_boot(machine); + kernel_entry =3D rvserver_ref_memmap[RVSERVER_FLASH].base; + } + } + + if (machine->kernel_filename && !kernel_entry) { + kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info, + firmware_end_addr= ); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, true, NU= LL); + kernel_entry =3D boot_info.image_low_addr; + } + + fdt_load_addr =3D riscv_compute_fdt_addr(memmap[RVSERVER_DRAM].base, + memmap[RVSERVER_DRAM].size, + machine, &boot_info); + + riscv_load_fdt(fdt_load_addr, machine->fdt); + + /* load the reset vector */ + riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, + rvserver_ref_memmap[RVSERVER_MROM].base, + rvserver_ref_memmap[RVSERVER_MROM].size, + kernel_entry, + fdt_load_addr); +} + +static bool rvserver_aclint_allowed(void) +{ + return tcg_enabled() || qtest_enabled(); +} + +static void rvserver_ref_machine_init(MachineState *machine) +{ + const MemMapEntry *memmap =3D rvserver_ref_memmap; + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(machine); + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *reset_syscon_io =3D g_new(MemoryRegion, 1); + DeviceState *mmio_irqchip, *pcie_irqchip, *gpex_host; + int i, base_hartid, hart_count; + int socket_count =3D riscv_socket_count(machine); + int imsic_bits; + + /* Check socket count limit */ + if (RVSERVER_SOCKETS_MAX < socket_count) { + error_report("number of sockets/nodes should be less than %d", + RVSERVER_SOCKETS_MAX); + exit(1); + } + + if (!rvserver_aclint_allowed()) { + error_report("'aclint' is only available with TCG acceleration"); + exit(1); + } + + s->memmap =3D rvserver_ref_memmap; + + /* + * We can't set aia_guests with 'qtest' because it'll skip the + * TCG exclusive init code, setting a blank CPU without RVH + * (among other things). If aia_guests is not zero we'll + * enter riscv_imsic_reset_enter(), which will reset its + * external irqs via qemu_irq_lower(), and qtest will hit an + * assert in riscv_cpu_set_irq() because we don't have RVH + * for handling guest local interrupts. + * + * qtest just want to inspect realized devices using QOM and + * HMP, so do not set aia_guests in that case. + */ + if (qtest_enabled()) { + s->aia_guests =3D 0; + } + + imsic_bits =3D imsic_num_bits(s->aia_guests + 1); + + /* Initialize sockets */ + mmio_irqchip =3D pcie_irqchip =3D NULL; + for (i =3D 0; i < socket_count; i++) { + g_autofree char *soc_name =3D g_strdup_printf("soc%d", i); + + if (!riscv_socket_check_hartids(machine, i)) { + error_report("discontinuous hartids in socket%d", i); + exit(1); + } + + base_hartid =3D riscv_socket_first_hartid(machine, i); + if (base_hartid < 0) { + error_report("can't find hartid base for socket%d", i); + exit(1); + } + + hart_count =3D riscv_socket_hart_count(machine, i); + if (hart_count < 0) { + error_report("can't find hart count for socket%d", i); + exit(1); + } + + object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], + TYPE_RISCV_HART_ARRAY); + object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", + machine->cpu_type, &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", + base_hartid, &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), "num-harts", + hart_count, &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); + + /* Per-socket ACLINT MTIMER */ + riscv_aclint_mtimer_create(system_memory, + memmap[RVSERVER_ACLINT].base + i * RISCV_ACLINT_DEFAULT_MT= IMER_SIZE, + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, + base_hartid, hart_count, + RISCV_ACLINT_DEFAULT_MTIMECMP, + RISCV_ACLINT_DEFAULT_MTIME, + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); + + /* Per-socket interrupt controller */ + s->irqchip[i] =3D riscv_create_aia(system_memory, true, s->aia_gue= sts, + IMSIC_HART_SIZE(0), + IMSIC_HART_SIZE(imsic_bits), + RVSERVER_IRQCHIP_NUM_SOURCES, + &s->memmap[RVSERVER_APLIC_M], + &s->memmap[RVSERVER_APLIC_S], + &s->memmap[RVSERVER_IMSIC_M], + &s->memmap[RVSERVER_IMSIC_S], + i, base_hartid, hart_count, + RVSERVER_IRQCHIP_NUM_MSIS, + RVSERVER_IRQCHIP_NUM_PRIO_BITS); + + /* Try to use different IRQCHIP instance based device type */ + if (i =3D=3D 0) { + mmio_irqchip =3D s->irqchip[i]; + pcie_irqchip =3D s->irqchip[i]; + } + if (i =3D=3D 1) { + pcie_irqchip =3D s->irqchip[i]; + } + } + + /* register system main memory (actual RAM) */ + memory_region_add_subregion(system_memory, memmap[RVSERVER_DRAM].base, + machine->ram); + + /* boot rom */ + memory_region_init_rom(mask_rom, NULL, "riscv_rvserver_ref_board.mrom", + memmap[RVSERVER_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[RVSERVER_MROM].base, + mask_rom); + + memory_region_init_io(reset_syscon_io, NULL, &rvserver_reset_syscon_op= s, + NULL, "reset_syscon_io", + memmap[RVSERVER_RESET_SYSCON].size); + memory_region_add_subregion(system_memory, + memmap[RVSERVER_RESET_SYSCON].base, + reset_syscon_io); + + gpex_host =3D riscv_gpex_pcie_init(system_memory, pcie_irqchip, + &rvserver_ref_memmap[RVSERVER_PCIE_EC= AM], + &rvserver_ref_memmap[RVSERVER_PCIE_MM= IO], + &rvserver_ref_memmap[RVSERVER_PCIE_MM= IO_HIGH], + &rvserver_ref_memmap[RVSERVER_PCIE_PI= O], + RVSERVER_PCIE_IRQ); + + /* Init nic devices and ICH9 AHCI */ + rvserver_init_pci_devices(s, gpex_host); + + s->platform_bus_dev =3D riscv_create_platform_bus(mmio_irqchip, + &s->memmap[RVSERVER_PL= ATFORM_BUS], + RVSERVER_PLATFORM_BUS_= IRQ, + RVSERVER_PLATFORM_BUS_= NUM_IRQS); + + serial_mm_init(system_memory, memmap[RVSERVER_UART0].base, + 0, qdev_get_gpio_in(mmio_irqchip, RVSERVER_UART0_IRQ), 399193, + serial_hd(0), DEVICE_LITTLE_ENDIAN); + + sysbus_create_simple("goldfish_rtc", memmap[RVSERVER_RTC].base, + qdev_get_gpio_in(mmio_irqchip, RVSERVER_RTC_IRQ)); + + for (i =3D 0; i < ARRAY_SIZE(s->flash); i++) { + /* Map legacy -drive if=3Dpflash to machine properties */ + pflash_cfi01_legacy_drive(s->flash[i], + drive_get(IF_PFLASH, 0, i)); + } + rvserver_flash_maps(s, system_memory); + + /* load/create device tree */ + if (machine->dtb) { + machine->fdt =3D load_device_tree(machine->dtb, &s->fdt_size); + if (!machine->fdt) { + error_report("load_device_tree() failed"); + exit(1); + } + } else { + create_fdt(s, memmap); + } + + riscv_create_iommu_sys(mmio_irqchip, s->memmap[RVSERVER_IOMMU_SYS].bas= e, + IOMMU_SYS_IRQ, false); + + s->machine_done.notify =3D rvserver_ref_machine_done; + qemu_add_machine_init_done_notifier(&s->machine_done); +} + +static void rvserver_ref_machine_instance_init(Object *obj) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(obj); + + s->flash[0] =3D riscv_flash_create(OBJECT(s), "riscv-server-ref.flash0= ", + "pflash0", RVSERVER_FLASH_SECTOR_SIZE= ); + s->flash[1] =3D riscv_flash_create(OBJECT(s), "riscv-server-ref.flash1= ", + "pflash1", RVSERVER_FLASH_SECTOR_SIZE= ); + + s->aia_guests =3D RVSERVER_IRQCHIP_DEFAULT_AIA_GUESTS; +} + +static char *rvserver_ref_get_aia_guests(Object *obj, Error **errp) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(obj); + char val[32]; + + sprintf(val, "%d", s->aia_guests); + return g_strdup(val); +} + +static void rvserver_ref_set_aia_guests(Object *obj, const char *val, + Error **errp) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(obj); + + s->aia_guests =3D atoi(val); + if (s->aia_guests < 0 || s->aia_guests > RVSERVER_IRQCHIP_MAX_GUESTS) { + error_setg(errp, "Invalid number of AIA IMSIC guests"); + error_append_hint(errp, "Valid values be between 0 and %d.\n", + RVSERVER_IRQCHIP_MAX_GUESTS); + } +} + +static HotplugHandler *rvserver_machine_get_hotplug_handler(MachineState *= ms, + DeviceState *d= ev) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + + if (device_is_dynamic_sysbus(mc, dev)) { + return HOTPLUG_HANDLER(ms); + } + + return NULL; +} + +static void rvserver_machine_device_plug_cb(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(hotplug_dev= ); + + if (s->platform_bus_dev) { + MachineClass *mc =3D MACHINE_GET_CLASS(s); + + if (device_is_dynamic_sysbus(mc, dev)) { + platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_d= ev), + SYS_BUS_DEVICE(dev)); + } + } +} + +static void rvserver_ref_machine_class_init(ObjectClass *oc, const void *d= ata) +{ + char str[128]; + MachineClass *mc =3D MACHINE_CLASS(oc); + HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + TYPE_RISCV_CPU_RVSERVER_REF, + }; + + /* Note: this is used as /model in the FDT. */ + mc->desc =3D "RISC-V Server Platform Reference Board v1.0"; + mc->init =3D rvserver_ref_machine_init; + mc->max_cpus =3D RVSERVER_CPUS_MAX; + mc->default_cpu_type =3D TYPE_RISCV_CPU_RVSERVER_REF; + mc->valid_cpu_types =3D valid_cpu_types; + mc->pci_allow_0_address =3D true; + mc->default_nic =3D "e1000e"; + mc->possible_cpu_arch_ids =3D riscv_numa_possible_cpu_arch_ids; + mc->cpu_index_to_instance_props =3D riscv_numa_cpu_index_to_props; + mc->get_default_cpu_node_id =3D riscv_numa_get_default_cpu_node_id; + mc->numa_mem_supported =3D true; + /* platform instead of architectural choice */ + mc->cpu_cluster_has_numa_boundary =3D true; + mc->default_ram_id =3D "riscv_rvserver_ref_board.ram"; + + object_class_property_add_str(oc, "aia-guests", + rvserver_ref_get_aia_guests, + rvserver_ref_set_aia_guests); + sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid valu= e " + "should be between 0 and %d.", RVSERVER_IRQCHIP_MAX_GUEST= S); + object_class_property_set_description(oc, "aia-guests", str); + + assert(!mc->get_hotplug_handler); + mc->get_hotplug_handler =3D rvserver_machine_get_hotplug_handler; + hc->plug =3D rvserver_machine_device_plug_cb; +#ifdef CONFIG_TPM + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); +#endif +} + +static const TypeInfo rvserver_ref_typeinfo =3D { + .name =3D TYPE_RISCV_SERVER_REF_MACHINE, + .parent =3D TYPE_MACHINE, + .class_init =3D rvserver_ref_machine_class_init, + .instance_init =3D rvserver_ref_machine_instance_init, + .instance_size =3D sizeof(RISCVServerRefMachineState), + .interfaces =3D (const InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { } + }, +}; + +static void rvserver_ref_init_register_types(void) +{ + type_register_static(&rvserver_ref_typeinfo); +} + +type_init(rvserver_ref_init_register_types) --=20 2.43.0 From nobody Sat Sep 26 20:01:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788988160; cv=none; d=zohomail.com; s=zohoarc; b=WN6EcYZ1VXV32NJvQ8nl2RarytNzNUm3Z6p3D1VywTKm8NL9kSS84yQlUob+G8rcNV6KTkesFuY6voF7MSMEf/5wYrK00vMMnUj3sZ03zC9Tic4rpZja9HD2oYMFm5BGK9EvpKjc9kpuCS2dxsZjlzsnhCCinmMEonjAlgNTlKE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788988160; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EZqQ5JYYnmdJ85rMgpUXB3OQ7aPO0YYpI5JTE9zBSaU=; b=bdoxPrUCNQ/BGtRRTFNvZhvRACxpfeLOnV1Cso9RYdCfEUlUiP3P2cWXx2S5qooQuadnMrM+TYrrBbUricDhTiXEyjGDudgUYMaBu/AHYe7buxi6A6KlNzST8+hKPSs8NAxFDAXHzSRSs2e2f2nWDG9kK1JP0UT2jNa1CkSM8tw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788988160732434.5420084340012; Wed, 9 Sep 2026 14:09:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x4PX1-0000zn-KJ; Wed, 09 Sep 2026 17:08:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x4PWo-0000ya-5K for qemu-devel@nongnu.org; Wed, 09 Sep 2026 17:08:23 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x4PWk-0000XU-Fr for qemu-devel@nongnu.org; Wed, 09 Sep 2026 17:08:21 -0400 Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 689JI3Bl4013481 for ; Wed, 9 Sep 2026 21:08:17 GMT Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gkcyh8k0a-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 09 Sep 2026 21:08:17 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-939d677af5dso54809985a.1 for ; Wed, 09 Sep 2026 14:08:16 -0700 (PDT) Received: from QCOM-UWl2o8bcGT.qualcomm.com ([177.18.66.131]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-91040646d59sm151811336d6.8.2026.09.09.14.08.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 14:08:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=EZqQ5JYYnmd J85rMgpUXB3OQ7aPO0YYpI5JTE9zBSaU=; b=eZLl7c+duvqOfF2hcOyiXSuJip9 vZqBNrfJV3vx65d3U2NwXX1ssHDzJAPKnBEVIjGSq3uVn/KKuqK4M4jmmeT6KoSx VRw7K4Zr23adYYEvuHG8K69WGHJUueBHF3393AlVfaedvj0t+McmeUvv2aXq4X/j JbisTziqNmO0OPu67O/WS5d0K6PK2TpfVw8pSVHdzUYN58ERt9UT5/lEjMkpObUd FMIBrF517PoyDEjdj/AUTg3X3SQsa+SZ9aMUeBisYMAsTdnGEInBOaD5odx9KdZN O/Wnz8bVrrkYUeEmNR5j09kXlZFZhbtuG5JC1DUJjanZVzdO0TDUWjPmeMQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1788988096; x=1789592896; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=EZqQ5JYYnmdJ85rMgpUXB3OQ7aPO0YYpI5JTE9zBSaU=; b=J8A1q2ZBzGr3q1FVrSJyd/zEdz9paYmVN9orGdj3HJKniuuEXB3R+TCCT0EY8q6lhQ I0NhE3ml7O4hE74kQy8xdJ5VX5a1PHeEthyz51gC/dHlTkg9E9CMuW0sX7hY0+/XIHPu cDyJOdLTTtRnqRkBmqIVOhNUpwSRn6eK0tbpkh0tOmrbLGWgHeM/W2bTrp/fHC2T32YS w061qrqoHsW1doc6+cR+KqL9rF5sRA3k0MT5fV1ihPx31w1hsZBoDRFuRO+NUZC9Xz8i V4jAYZh+nTkRwf9Z394YUwEE/ZqiLMEvIYIBiI0BtkH2KdbD8tmz0NIPduoRNL8DpHrU sPOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788988096; x=1789592896; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=EZqQ5JYYnmdJ85rMgpUXB3OQ7aPO0YYpI5JTE9zBSaU=; b=OjUigX3AfUg5rUdxjArDLwQCraxgCmFANM8XrtaEtXzQctEvRhAqnHjuzGyLMgnJsS lgVC/an9lsCW30SFzTw2eSVFarlQtA1i4K2ca2v6bNS94WU6WBZqZ8+cZXrNJE+dcOr3 BvKqZe5b7jmsP2pjsaWYUZ5wEdFNTRsRLrLY8AYQT8Tq1lgH+VyVuZQualyPHOe/kGDb c+vUrBdyq7KvFXItkJmFOKU5nec9k7JoIoZleBsYvXeAr5au+m93NXoldO5ziYrEhz5P A5TadCQHOg8mrsRJQEhgFMDemf/4YNqpTj0RqihbSGsk3+TgCS9Nk/U2C+2X0Qsr77ys 6zxg== X-Gm-Message-State: AFuF++l1de1ihEGy2VSAZOVJZUBQVDZBqcbGYN/KTGIEKMnIn9KM4tuz KaaGOkSYkBoNPQhQjBwW+Wpk+cYoN9bFBEzLuarpeMM9Y1lc68OSMShxvuxIGYXwrsbAJ6YMyhO h2iTcWrUwQsW3kO121U/D1EEOzlADrsnyhlZfGbEO+LfQq974GncXT45PfKGpA8fWWQ== X-Gm-Gg: AYBFou1tBROWADmxWkUTzWSBw2qkm272iqOlYeepa8eS64jSFer1vSxuXQ/Kr2hTCjh 40nYsnszYyHcljeB1hXsGfi66wdCAbovG+18vaJkFC2O9SjE5nxqkmZIvfxjR37j2ShEM0Oo3J6 n/RKxgbER1pm0sb8xTLOW8VgWrz6XinagQAzUMOwBiJHcN3T1lUdgvZzRGlIUFE9caz0xWAFTne sI8OrtkDNcglhiGMbN6D/w/f5/7KM7wZemJg4/eKySdHWcLrquJNsCVCCAzV1ZcwtdMrAp7OpAf Xzjx22IX+Y4hFNUCeotFooWcIju/lqk8MS15zzfAayDIzS73yHPXQy9r3cu4w4wJllCS5vaadn3 UpVmve7VBtJWpUBjIrWVtUB6anmFz+1sLgJ0G X-Received: by 2002:a05:620a:2809:b0:939:72cb:bae5 with SMTP id af79cd13be357-939d7f8c7aamr173913385a.28.1788988095860; Wed, 09 Sep 2026 14:08:15 -0700 (PDT) X-Received: by 2002:a05:620a:2809:b0:939:72cb:bae5 with SMTP id af79cd13be357-939d7f8c7aamr173908685a.28.1788988095410; Wed, 09 Sep 2026 14:08:15 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, Daniel Henrique Barboza , Chao Liu , Nutty Liu , Sunil V L , Palmer Dabbelt Subject: [PATCH v11 4/5] tests/functional/riscv64: add riscv-server-ref tests Date: Wed, 9 Sep 2026 18:07:54 -0300 Message-ID: <20260909210756.1767711-5-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260909210756.1767711-1-daniel.barboza@oss.qualcomm.com> References: <20260909210756.1767711-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDIzNyBTYWx0ZWRfXzgDc0mGSndc0 J8AZOtq7Gxmyv5BM/mmiRbLT8xmVs9tF5feQaPtoDe6klHZ0NeYGP7WOXdW1bQfsr3ocJoURJ7d MM2jXREIBGMzYMwUYUVvCZFZ8Wi5IZvHZPdJXY9oldeawTYIKOtx34flxHuN/iyB1Zfj+ijhN0n GdK5eyAQ+pBEXv/lNlsQk/8whOHHv59m/l886mzDq/L+5608o7OooT9F/Hm3npankvvYZXc/D+L KbhbXSV6lQxG0xwNAqHiof58hZ5scf0swgyr2psKFoWWUb8NzW1/y/mmj+iVeBOABY2khiIleJU TaqgxUa6Z5kFYfiP6ks+hd8Y8eKiAJWd6wqtAFmmLLw9ZMB6O+paWjzZ4e1BWxlmCMFPXGkuJ6D HiAKxJGXMH6ac7ivYmBN1t5qlvIvQk8Ae8fPyFEpWXMPnBuJWX1o8A1KRzk0YPG4KxdfaF19C/l njG/M5h0lAxs2hWSjLQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDIzNyBTYWx0ZWRfX6rBKwRm4iCy8 YPstuXbIeoBPvfgOKVQ7rdc0Q+dzHMD0Kooeh8QAM55p06kIEyCupkLsj1n4NN1uEskHqaY2erK GxL5UybAceaLN4KhjEv+MlGFMeW2xH4= X-Authority-Analysis: v=2.4 cv=YKgKWhGx c=1 sm=1 tr=0 ts=6aa1cac1 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=CQQxcbsX5Byh3TlVSSGwig==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=NEAV23lmAAAA:8 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=69EAbJreAAAA:8 a=JF9118EUAAAA:8 a=QOu4sXKRH9_VvCpQA3IA:9 a=bTQJ7kPSJx9SKPbeHEYW:22 a=xVlTc564ipvMDusKsbsT:22 X-Proofpoint-ORIG-GUID: sg8DpF5FB-na39PROvFk6_BUAAzbLAMl X-Proofpoint-GUID: sg8DpF5FB-na39PROvFk6_BUAAzbLAMl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-09_01,2026-09-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 adultscore=0 malwarescore=0 phishscore=0 impostorscore=0 spamscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609090237 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788988161888158500 Content-Type: text/plain; charset="utf-8" Add tests for the recently added riscv-server-ref machine: - a new test_opensbi.py test. The idea is to have a quick test that can catch trivial regressions that would prevent OpenSBI to finish; - a new Linux boot "thorough" test that will boot the machine up to the buildroot prompt. - a TPM specific selftest for the riscv-server-ref board. The test will be skipped if there's no 'swtpm' in the host. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Reviewed-by: Nutty Liu Reviewed-by: Alistair Francis Reviewed-by: Sunil V L --- tests/functional/riscv64/meson.build | 2 + tests/functional/riscv64/test_opensbi.py | 4 + tests/functional/riscv64/test_server_ref.py | 88 +++++++++++++++++++++ 3 files changed, 94 insertions(+) create mode 100755 tests/functional/riscv64/test_server_ref.py diff --git a/tests/functional/riscv64/meson.build b/tests/functional/riscv6= 4/meson.build index d1a3e6c2bf..2d22e49efd 100644 --- a/tests/functional/riscv64/meson.build +++ b/tests/functional/riscv64/meson.build @@ -3,6 +3,7 @@ test_riscv64_timeouts =3D { 'boston' : 120, 'k230' : 120, + 'server_ref' : 120, 'tuxrun' : 120, } =20 @@ -15,6 +16,7 @@ tests_riscv64_system_thorough =3D [ 'endianness', 'boston', 'k230', + 'server_ref', 'sifive_u', 'tt_atlantis', 'tuxrun', diff --git a/tests/functional/riscv64/test_opensbi.py b/tests/functional/ri= scv64/test_opensbi.py index 0f8beb7e7a..367e131164 100755 --- a/tests/functional/riscv64/test_opensbi.py +++ b/tests/functional/riscv64/test_opensbi.py @@ -36,5 +36,9 @@ def test_riscv_virt(self): self.set_machine('virt') self.boot_opensbi() =20 + def test_riscv_server_ref(self): + self.set_machine('riscv-server-ref') + self.boot_opensbi() + if __name__ =3D=3D '__main__': QemuSystemTest.main() diff --git a/tests/functional/riscv64/test_server_ref.py b/tests/functional= /riscv64/test_server_ref.py new file mode 100755 index 0000000000..db3371fafd --- /dev/null +++ b/tests/functional/riscv64/test_server_ref.py @@ -0,0 +1,88 @@ +#!/usr/bin/env python3 +# +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +""" +riscv-server-ref board test +""" + +import os +import tempfile +import subprocess + +from qemu_test import QemuSystemTest, Asset +from qemu_test import wait_for_console_pattern +from qemu_test import skipIfMissingCommands + +class RiscvServerRefTest(QemuSystemTest): + """ + Test the riscv-server-ref board + """ + + ASSET_KERNEL =3D Asset( + ('https://github.com/danielhb/qemu-machine-boot/raw/refs/heads/' + 'master/riscv/images/virt64/buildroot/Image'), + '6bacc876c769c1bb6057d2bf549eba67fbe83916e8223f9fe21c8e8fff665a36') + + ASSET_ROOTFS =3D Asset( + ('https://github.com/danielhb/qemu-machine-boot/raw/refs/heads/' + 'master/riscv/images/virt64/buildroot/rootfs.ext2'), + 'f00bb88749f945d80675540a1338bd1ccb226574685a5b6c65ab44027d0411a8') + + def do_test_boot_linux_test(self, tpmstate_dir=3DNone): + self.set_machine('riscv-server-ref') + kernel_path =3D self.ASSET_KERNEL.fetch() + rootfs_path =3D self.ASSET_ROOTFS.fetch() + + self.vm.add_args('-kernel', kernel_path) + self.vm.add_args('-append', 'rw rootwait root=3D/dev/sda') + self.vm.add_args('-drive', + f'file=3D{rootfs_path},format=3Draw,id=3Dhd0,snapshot=3Don,if= =3Dnone') + self.vm.add_args('-device', 'ahci,id=3Dahci') + self.vm.add_args('-device', 'ide-hd,drive=3Dhd0,bus=3Dahci.0') + + if tpmstate_dir is not None: + # Note: code taken verbatim from + # tests/functional/arm/test_aspeed_ast2600_buildroot_tpm.py + + # We must put the TPM state dir in /tmp/, not the build dir, + # because some distros use AppArmor to lock down swtpm and + # restrict the set of locations it can access files in. + socket =3D os.path.join(tpmstate_dir, 'swtpm-socket') + subprocess.run(['swtpm', 'socket', '-d', '--tpm2', + '--tpmstate', f'dir=3D{tpmstate_dir}', + '--ctrl', f'type=3Dunixio,path=3D{socket}'], + check=3DTrue) + self.vm.add_args('-chardev', f'socket,id=3Dchrtpm,path=3D{sock= et}') + self.vm.add_args('-tpmdev', 'emulator,id=3Dtpm0,chardev=3Dchrt= pm') + self.vm.add_args('-device', 'tpm-tis-device,tpmdev=3Dtpm0') + + self.vm.set_console() + self.vm.launch() + + # Wait for OpenSBI + wait_for_console_pattern(self, 'OpenSBI') + + # Wait for Linux kernel boot + wait_for_console_pattern(self, 'Linux version') + wait_for_console_pattern(self, 'Machine model: RISC-V Server Platf= orm') + + # Test e1000e network card functionality + wait_for_console_pattern(self, 'e1000e') + wait_for_console_pattern(self, 'Network Connection') + + # Wait for boot to complete - system reaches login prompt + wait_for_console_pattern(self, 'Run /sbin/init as init process') + + def test_boot_linux_test(self): + self.do_test_boot_linux_test() + + @skipIfMissingCommands('swtpm') + def test_boot_linux_test_tpm(self): + with tempfile.TemporaryDirectory(prefix=3D"qemu_") as tpmstate_dir: + self.do_test_boot_linux_test(tpmstate_dir) + +if __name__ =3D=3D '__main__': + QemuSystemTest.main() --=20 2.43.0 From nobody Sat Sep 26 20:01:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788988169; cv=none; d=zohomail.com; s=zohoarc; b=ihcCgxheDa2bRiG1kfeoeQldVPHULGwrgAt5N7Lv3q9H+U0MjeEkihSZops/H++l7nOFFe/hdiU0D0voHFSKUCqEUZHUmh61JuLt0l5zFi3Z/xPLEQvR86qn9D/26dTtTlZ1GW2nebBWutY465qzS/PzaC22XhZUxjaBzrQ4/+Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788988169; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SWCz14HQJsIqff4DEAUggFZfm8sDK/aoUCeI73tDq1k=; b=X4E/w2HydHJusAO/QZUBmYHfweHciDaBPo7TWovNbKPdeSdTxZ/K8YIA8Cv++trwQHc3cEuyg6DjycQWBJCShoZZX6O7cV8FwgBhOQsJ6CzULkqPaxeK/tBsNSC3BrBTtFlXTJsWn5M5Eed4ypNVAFg4VJRCStzaMMGUms9mESQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788988169125517.0866840138164; Wed, 9 Sep 2026 14:09:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x4PX5-00014j-7A; Wed, 09 Sep 2026 17:08:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x4PWq-0000z4-3k for qemu-devel@nongnu.org; Wed, 09 Sep 2026 17:08:25 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x4PWn-0000Xx-J1 for qemu-devel@nongnu.org; Wed, 09 Sep 2026 17:08:23 -0400 Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 689JIRLE2851462 for ; Wed, 9 Sep 2026 21:08:20 GMT Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gkcyd0k4k-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 09 Sep 2026 21:08:20 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-5308a3825deso61730661cf.2 for ; Wed, 09 Sep 2026 14:08:20 -0700 (PDT) Received: from QCOM-UWl2o8bcGT.qualcomm.com ([177.18.66.131]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-91040646d59sm151811336d6.8.2026.09.09.14.08.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 14:08:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=SWCz14HQJsI qff4DEAUggFZfm8sDK/aoUCeI73tDq1k=; b=nHCU8l4U/TBmDXosKW9gvduqbev 6iyyJDxmQO4V4baKHehllebHPIAoI7SScVnV5QLivOsPR36uarmlK5D2x1HTDtEx uQkAHzjzPvRUQlnljsqoQZR/H8RpWU6KCcNl0+d8Ur3yn1vtsFU8nFij1RiaqjIm HObqTgiiIeH0Nb4sbpwShOcwVkNCBO0Ykjc4Es0guJ40E+f5Wm4W7yLSRRxgMXtm JN/Dn77rlcm+ickj3TB7mZf2UA+rmMqvSRbry23eWmExC/+H99KetNow2t48OC+e cLJA7caIWUVNkRU+kzw/lUMCZ9mV8g14w4WIT02dsvx1LySblJtyMahEgPg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1788988100; x=1789592900; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=SWCz14HQJsIqff4DEAUggFZfm8sDK/aoUCeI73tDq1k=; b=eufgAu3OfkHtgcFVRg8PIQxb7CGtWayox9Auvhv/VUvZ54nO3iknUt0zlJ4drWmyO1 fhPcsNwqtDyt95c1pa8UEUR/OCubTQvN0diTIGfnrosyjAPN44x/qE8jFX2n0zV15hlN KtCa5jcA2/LOPFczuEKz2J4IFCsEBfFlJLol+2XXz6ysrOToVIpuUNzxoH4RyIVON8vu chyAEqxILDszE4RxJdkHpyyAtrd/UOJjQugXayDhgprd7UblvZ2oVvEpj8HrW6Ook9kt +2P56rsOtOjS6+g+HFhVJw5wBkKTkg9DoYPNFW599mhQqe04OPM+WFDwHxRRmnyBKJwB euKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788988100; x=1789592900; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=SWCz14HQJsIqff4DEAUggFZfm8sDK/aoUCeI73tDq1k=; b=YnjmMCjx6hp/cOa3bL0H7F9sE83v513ZcgjRheH10LYNaCB4EeG/agxHns3yl8Eqdl NH33BmDKwTSh/9/0/3d9wzrfe+lJKG+o36i8ymsI0FwWUCFWLb/bFiSFcMkikz5zCm+q r0FYs2CQUFf+KNv13+4pGdjkSY8WoqtEJDeSkBS5CcjRxXHeUIiKLyaOojnmALusSTI1 tcxdb/77A1y/8FhIxkgssQFut39TbpixSmY2uh2OEKbLmhUFfjy1L7PHRozx5Kx9lKsl s0txmb6kutWmhY56b7EtxHwoW5UJlMmel8OpkhP4xEO8bUB4okkd5jXJH74KJW4Z+ph/ mpIg== X-Gm-Message-State: AFuF++lyfSF9SlqJIJoTp/pMKW03v5FCjcexr9MSDVO4FiFUkr037LbF b62F8Dc2zJlbSb22DHv0Bt+827/zfpNKG1AXxqWgIL5W+k22mWuzDkPlgCZZQdh6FwcLS6ELYKv au5+hhAkmDY5GxuUDEFxFfagse3WxaU6dFzFFFLAITcjP4i9qR602eVpTJI6TRKinHQ== X-Gm-Gg: AYBFou28p14TyQd4a/479aa25QRapM6GpTkyo5EyXy97w6NTlRGXdUZ0oF4FaT53NQi 3AAyDN2tHY10CcoRyHbYz6TpWqbDztngN64188k1Ecu8kEZeQ6ywvRIkOVIEOAGSsqQFMAKpF5H QW5LWeAKOfUUl9J2QAbpMjrlotdfvbPwJZ3O15dSjk67CfVFTjaj+SfGNYgs+omTJlXBXhhwKiT z4dFDVGwtSHUQRO4WLQ4+fRTFf+Vipyqcum4NJws0aY04IvVMKrmaB8RR+WwncZfOc81CGHEwfX HQI/QDs/KT2NX+6QQebxu2bdV2bD3cBtskjudM2bvsv6edP3uU76J6NhDssI29TvrxzF3XsuIVw 8mX2IDIpTfzpEdbZGsoTGaDrgXZHhJFaftgrd X-Received: by 2002:a05:622a:110c:b0:52d:28f8:578c with SMTP id d75a77b69052e-530a2d12553mr122186121cf.31.1788988099528; Wed, 09 Sep 2026 14:08:19 -0700 (PDT) X-Received: by 2002:a05:622a:110c:b0:52d:28f8:578c with SMTP id d75a77b69052e-530a2d12553mr122185371cf.31.1788988098987; Wed, 09 Sep 2026 14:08:18 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, Daniel Henrique Barboza , Sunil V L , Pierrick Bouvier , Palmer Dabbelt Subject: [PATCH v11 5/5] docs: add riscv-server-ref.rst Date: Wed, 9 Sep 2026 18:07:55 -0300 Message-ID: <20260909210756.1767711-6-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260909210756.1767711-1-daniel.barboza@oss.qualcomm.com> References: <20260909210756.1767711-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: WfUJJQm4wxlRu-luh_Pc61ZRn8vewfGr X-Authority-Analysis: v=2.4 cv=ef+o7LEH c=1 sm=1 tr=0 ts=6aa1cac4 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=CQQxcbsX5Byh3TlVSSGwig==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=NEAV23lmAAAA:8 a=NLiCwHATAAAA:8 a=EUspDBNiAAAA:8 a=JF9118EUAAAA:8 a=FRSEYCzRAAAA:8 a=vlmih187C6Ts2ntwv5oA:9 a=dawVfQjAaf238kedN5IG:22 a=F9tHCgz3TLBaZgltkx5D:22 a=xVlTc564ipvMDusKsbsT:22 a=H4N_Y-AU75W7NKDNhZlT:22 X-Proofpoint-ORIG-GUID: WfUJJQm4wxlRu-luh_Pc61ZRn8vewfGr X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDIzNiBTYWx0ZWRfXybWlqM7cIcca TIr9xsAA5xXqv4LPYJd4Ns9AxPdw+1jjTDJ8vZ4UeTrYUxOMw/4VETItQQ5OsT1LelBXzG6/cYn 3rKQ13AJ45rWyOEMV+7wHC62ddfZzVk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDIzNiBTYWx0ZWRfX78j6ZcZkDiTr uJ1u71cQQolG370B0Bs5HeYKuStfnu8hfawZ0gqzFG8SaXWxn8yD7xwZZpZxtX0M1ou7PXKxHLm ksf1DX3lvyKSqROxwvobm/vdbVhtcOKI6MBBtVmSUTrjbZYHlVlojRmwzZOb21aSgWUeWT95k2z Pdg8VURqiQi1Q8EoTdBFWOk0ARQe8afkDgxsrncWVruRqIkQpSxyneu6pAF6YGKHEMj4UyjoJvW GuaSDSINqI+RmSdpH9fBaI7UKSUfiWDaZUt+omlSvSoBbIRrHBffpzr4Z+Gf/emW5lO9HXN/ohd plKkQhWwVtNie1legaawpoFXawE5JvX7gejR47YBL6RJw36KAOcjAzlK7P91/k5HVbNyKif5Qfv xjTUo8vnfAKRBIlkxL0BcNG3MNGtF5R9EKDHGIWfCrQ95bJnnf1vB7n4/+KxQmjFF4B3rsFBYvs fZQECT0Fj5hbUbhhnaA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-09_01,2026-09-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 phishscore=0 impostorscore=0 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609090236 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788988169848158500 Content-Type: text/plain; charset="utf-8" Add documentation for the new riscv-server-ref board. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Chao Liu Reviewed-by: Sunil V L --- docs/system/riscv/riscv-server-ref.rst | 65 ++++++++++++++++++++++++++ docs/system/target-riscv.rst | 1 + 2 files changed, 66 insertions(+) create mode 100644 docs/system/riscv/riscv-server-ref.rst diff --git a/docs/system/riscv/riscv-server-ref.rst b/docs/system/riscv/ris= cv-server-ref.rst new file mode 100644 index 0000000000..5e9d237b14 --- /dev/null +++ b/docs/system/riscv/riscv-server-ref.rst @@ -0,0 +1,65 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +RISC-V Server Platform Reference board (``riscv-server-ref``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The RISC-V Server Platform specification `spec`_ defines a standardized +set of hardware and software capabilities that portable system software, +such as OS and hypervisors, can rely on being present in a RISC-V server +platform. This machine aims to emulate this specification, providing +an environment for firmware/OS development and testing. + +`spec`_ is version 1.0 at the introduction of this board. For each new +supported spec version a new versioned board will be added, keeping +"riscv-server-ref" as an alias for the newest version supported. E.g. +for spec version 2.0: + +* riscv-server-ref-1.0 - board that complies with spec version 1.0 +* riscv-server-ref-2.0 - board that complies with spec version 2.0 +* riscv-server-ref - alias for riscv-server-ref-2.0 + +The main features included in the riscv-server-ref board are: + +* IOMMU platform device (riscv-iommu-sys) +* AIA +* PCIe AHCI +* PCIe NIC +* No virtio mmio bus +* No fw_cfg device +* No ACPI table +* Minimal device tree nodes + +There are multiple ways of using this reference board. The spec compliant= way +is using an EDK2 image and a TPM device. The board was tested with the TPM +device ``tpm-tis`` that uses the external ``swtpm`` emulator. More info o= n how +to use this device can be found in `tpm`_. + +To use this board coupled with the tpm-tis device, first start the ``swtpm= `` +process in a shell (the ``log`` parameter is optional): + +.. code-block:: bash + + $ mkdir /tmp/mytpm1 + $ swtpm socket --tpmstate dir=3D/tmp/mytpm1 \ + --ctrl type=3Dunixio,path=3D/tmp/mytpm1/swtpm-sock \ + --tpm2 \ + --log level=3D20 + +And then start QEMU with: + +.. code-block:: bash + + qemu-system-riscv64 -M riscv-server-ref \ + -bios fw_dynamic.bin \ + -kernel EDK2.fd \ + -drive file=3Dnvme_disk.ext2,format=3Draw,id=3Dhd0,if=3Dnone \ + -device ahci,id=3Dahci \ + -device ide-hd,drive=3Dhd0,bus=3Dahci.0 \ + -chardev socket,id=3Dchrtpm,path=3D/tmp/mytpm1/swtpm-sock \ + -tpmdev emulator,id=3Dtpm0,chardev=3Dchrtpm \ + -device tpm-tis-device,tpmdev=3Dtpm0 \ + -nographic + + +.. _spec: https://github.com/riscv-non-isa/riscv-server-platform +.. _tpm: https://qemu-project.gitlab.io/qemu/specs/tpm.html diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 2639866a3e..74e23fa64c 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -70,6 +70,7 @@ undocumented; you can get a complete list by running riscv/microblaze-v-generic riscv/microchip-icicle-kit riscv/mips + riscv/riscv-server-ref riscv/shakti-c riscv/sifive_u riscv/tt_atlantis --=20 2.43.0