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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788926614776158500 v73 is currently the newest core this target implements. Add the v75, v79, v81 CPUs. New instructions to follow in subsequent commits. Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- target/hexagon/cpu-qom.h | 6 ++++++ linux-user/hexagon/elfload.c | 6 ++++++ target/hexagon/cpu.c | 3 +++ 3 files changed, 15 insertions(+) diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h index 6e1bb040704..2bfa4d5d0fc 100644 --- a/target/hexagon/cpu-qom.h +++ b/target/hexagon/cpu-qom.h @@ -25,6 +25,9 @@ typedef enum { HEX_VER_V69 =3D 0x69, HEX_VER_V71 =3D 0x71, HEX_VER_V73 =3D 0x73, + HEX_VER_V75 =3D 0x75, + HEX_VER_V79 =3D 0x79, + HEX_VER_V81 =3D 0x81, HEX_VER_ANY =3D 0xff, } HexagonVersion; =20 @@ -49,6 +52,9 @@ typedef struct { #define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") #define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") #define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") +#define TYPE_HEXAGON_CPU_V75 HEXAGON_CPU_TYPE_NAME("v75") +#define TYPE_HEXAGON_CPU_V79 HEXAGON_CPU_TYPE_NAME("v79") +#define TYPE_HEXAGON_CPU_V81 HEXAGON_CPU_TYPE_NAME("v81") =20 OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) =20 diff --git a/linux-user/hexagon/elfload.c b/linux-user/hexagon/elfload.c index 39b02018145..2fd45f7e38a 100644 --- a/linux-user/hexagon/elfload.c +++ b/linux-user/hexagon/elfload.c @@ -37,6 +37,12 @@ const char *get_elf_cpu_model(uint32_t eflags) return "v71"; case 0x73: return "v73"; + case 0x75: + return "v75"; + case 0x79: + return "v79"; + case 0x81: + return "v81"; } =20 err =3D snprintf(buf, sizeof(buf), "unknown (0x%x)", eflags); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 4a7b76e3bcc..fb0e3caa481 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -874,6 +874,9 @@ static const TypeInfo hexagon_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_HEXAGON_CPU_V69, HEX_VER_V69), DEFINE_CPU(TYPE_HEXAGON_CPU_V71, HEX_VER_V71), DEFINE_CPU(TYPE_HEXAGON_CPU_V73, HEX_VER_V73), + DEFINE_CPU(TYPE_HEXAGON_CPU_V75, HEX_VER_V75), + DEFINE_CPU(TYPE_HEXAGON_CPU_V79, HEX_VER_V79), + DEFINE_CPU(TYPE_HEXAGON_CPU_V81, HEX_VER_V81), }; =20 DEFINE_TYPES(hexagon_cpu_type_infos) --=20 2.34.1 From nobody Sat Sep 26 20:01:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788926579; cv=none; d=zohomail.com; s=zohoarc; b=hRZ04YXIYdPXQYK7rj85k9qYSm3CLTxajb+kUWln8ynbZ0BP2b0qIHUQOwOcWPcgGp77w8iphICe+gwARvZhmb2Da1pw1RDM830fSU63+50j0ggnn2fe0pz3LoDXHnpFTUeshPMtAGDQZO9YEAVqRi9OU3yo5GiP+llyqFhAxlU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788926579; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fdwDXcs4SfI3UaOq8SilTZCLtIfPZsAl3o0N2Mz0v3o=; b=EXvGCy+0Pkybp72VMLPFe5x1WxdQfwPYzWYQ/yJxu3Csj8xLlJvViegUf74HmfJCogJ+3gQvUOUTHjEgTrtA7U/MYfdt9g0XvjI+EjHKY5tJRyz3lY1CLOUPSLSMCLJmd5iNVqP34qJQ5boEZKPWEjUsVVQcwW4zV8DduJVO6Xo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788926579379443.8737260734422; Tue, 8 Sep 2026 21:02:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x49VP-0006xU-7Q; Wed, 09 Sep 2026 00:01:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x49VN-0006wx-5Y for qemu-devel@nongnu.org; Wed, 09 Sep 2026 00:01:49 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x49VK-0003rz-NX for qemu-devel@nongnu.org; Wed, 09 Sep 2026 00:01:48 -0400 Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 688MgGo5336395 for ; Wed, 9 Sep 2026 04:01:45 GMT Received: from mail-ot1-f69.google.com (mail-ot1-f69.google.com [209.85.210.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gjqe7hxn4-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 09 Sep 2026 04:01:45 +0000 (GMT) Received: by mail-ot1-f69.google.com with SMTP id 46e09a7af769-7f1da5e5b06so6536551a34.2 for ; Tue, 08 Sep 2026 21:01:45 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788926580677158500 v73 already added J2_callrh and J2_jumprh but unintentionally omitted `unpause`. Its effect is to cause other threads' pause instructions to cease pausing, but we treat `pause` as a nop or a yield in RR, so unpause can safely be a nop. While here, spell the other two v73 entries' version as HEX_VER_V73 instead of the literal 0x73, matching every other entry in the table. Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- tests/tcg/hexagon/check_rev_gating.c | 12 +++++++++--- tests/tcg/hexagon/v73_scalar.c | 7 +++++++ target/hexagon/tag_rev_info.c.inc | 5 +++-- target/hexagon/imported/encode_pp.def | 1 + target/hexagon/imported/system.idef | 3 +++ 5 files changed, 23 insertions(+), 5 deletions(-) diff --git a/tests/tcg/hexagon/check_rev_gating.c b/tests/tcg/hexagon/check= _rev_gating.c index 26b66f54552..d5295bf24ab 100644 --- a/tests/tcg/hexagon/check_rev_gating.c +++ b/tests/tcg/hexagon/check_rev_gating.c @@ -3,9 +3,12 @@ * are rejected with SIGILL. * * Compiled with -mv66 so that e_flags selects CPU v66. The test embeds - * a v68 instruction (L2_loadw_aq: "r0 =3D memw_aq(r0)") via .word - * encoding. The revision-gated decoder must reject it, and linux-user - * must deliver SIGILL. + * instructions from v68 through v73 via .word encoding: the assembler + * enforces the selected CPU's own minimum version, so none of these -- + * including ones it otherwise knows how to assemble at their own + * target, such as callrh or unpause -- can be written as themselves in + * a file built for v66. The revision-gated decoder must reject every + * one of them, and linux-user must deliver SIGILL. * * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * SPDX-License-Identifier: GPL-2.0-or-later @@ -102,6 +105,8 @@ TRY_FUNC(v73_callrh, ".word 0x50c5c000 /* callrh r5 */\n") TRY_FUNC(v73_jumprh, ".word 0x52c0c000 /* jumprh r0 */\n") +TRY_FUNC(v73_unpause, + ".word 0x57e0d000 /* unpause */\n") =20 int main(void) { @@ -133,6 +138,7 @@ int main(void) =20 assert(try_v73_callrh() =3D=3D SIGILL); assert(try_v73_jumprh() =3D=3D SIGILL); + assert(try_v73_unpause() =3D=3D SIGILL); =20 assert(signals_handled =3D=3D expected_signals); =20 diff --git a/tests/tcg/hexagon/v73_scalar.c b/tests/tcg/hexagon/v73_scalar.c index fee67fc5311..2b5f3aa2149 100644 --- a/tests/tcg/hexagon/v73_scalar.c +++ b/tests/tcg/hexagon/v73_scalar.c @@ -86,10 +86,17 @@ static void test_jumprh(void) check32(res, 1); } =20 +static void test_unpause(void) +{ + /* Nothing is paused, so this just needs to execute without faulting. = */ + asm volatile("unpause\n\t"); +} + int main() { test_callrh(); test_jumprh(); + test_unpause(); =20 puts(err ? "FAIL" : "PASS"); return err ? 1 : 0; diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_inf= o.c.inc index a91b91a23e6..44513f46809 100644 --- a/target/hexagon/tag_rev_info.c.inc +++ b/target/hexagon/tag_rev_info.c.inc @@ -571,8 +571,9 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_O= PCODE] =3D { [F2_dfmpyhh] =3D { .introduced =3D HEX_VER_V67, .removed =3D HEX_VER_N= ONE }, [F2_dfmpylh] =3D { .introduced =3D HEX_VER_V67, .removed =3D HEX_VER_N= ONE }, [F2_dfmpyll] =3D { .introduced =3D HEX_VER_V67, .removed =3D HEX_VER_N= ONE }, - [J2_callrh] =3D { .introduced =3D 0x73, .removed =3D HEX_VER_NONE }, - [J2_jumprh] =3D { .introduced =3D 0x73, .removed =3D HEX_VER_NONE }, + [J2_callrh] =3D { .introduced =3D HEX_VER_V73, .removed =3D HEX_VER_NO= NE }, + [J2_jumprh] =3D { .introduced =3D HEX_VER_V73, .removed =3D HEX_VER_NO= NE }, + [J2_unpause] =3D { .introduced =3D HEX_VER_V73, .removed =3D HEX_VER_N= ONE }, [L2_loadw_aq] =3D { .introduced =3D HEX_VER_V68, .removed =3D HEX_VER_= NONE }, [L4_loadd_aq] =3D { .introduced =3D HEX_VER_V68, .removed =3D HEX_VER_= NONE }, [Y6_dmcfgrd] =3D { .introduced =3D HEX_VER_V68, .removed =3D HEX_VER_N= ONE }, diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index d9e8ea2aebd..1fce318b2bb 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -585,6 +585,7 @@ DEF_FIELDROW_DESC32(ICLASS_J" 0100 -------- PP------ --= ------","[#4] (#u8) ") DEF_ENC32(J2_trap0, ICLASS_J" 0100 00------ PP-iiiii ---iii--") DEF_ENC32(J2_trap1, ICLASS_J" 0100 10-xxxxx PP-iiiii ---iii--") DEF_ENC32(J2_pause, ICLASS_J" 0100 01----ii PP-iiiii ---iii--") +DEF_ENC32(J2_unpause,"01010111111-----PP01----000-----") =20 DEF_FIELDROW_DESC32(ICLASS_J" 0101 -------- PP------ --------","[#5] Rd=3D= (Rs) ") DEF_ENC32(Y2_icdatar, ICLASS_J" 0101 101sssss PP------ ---ddddd") diff --git a/target/hexagon/imported/system.idef b/target/hexagon/imported/= system.idef index 02aee8ce8ee..b44e87565c3 100644 --- a/target/hexagon/imported/system.idef +++ b/target/hexagon/imported/system.idef @@ -51,6 +51,9 @@ Q6INSN(J2_trap1,"trap1(Rx32,#u8)",ATTRIBS(A_COF,A_NOTE_NO= PACKET,A_RESTRICT_NOPAC Q6INSN(J2_pause,"pause(#u8)",ATTRIBS(A_COF,A_NOTE_NOPACKET,A_RESTRICT_NOPA= CKET), "Enter low-power state for #u8 cycles",{fPAUSE(uiV);}) =20 +Q6INSN(J2_unpause,"unpause",ATTRIBS(A_COF,A_NOTE_NOPACKET,A_RESTRICT_NOPAC= KET), +"Resume paused threads",{fUNPAUSE();}) + Q6INSN(J2_rte, "rte", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NO_TIMING_LOG), "Return from Exception", { --=20 2.34.1 From nobody Sat Sep 26 20:01:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788926557291158500 v79 adds a ":nt" non-temporal cache-locality hint to the post-increment store family and to dcfetch/dczeroa. None of the ":nt" mnemonics are accepted by the assembler yet, so the new test embeds them via .word. Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- target/hexagon/attribs_def.h.inc | 2 + tests/tcg/hexagon/check_rev_gating.c | 32 +++++- tests/tcg/hexagon/v79_scalar.c | 157 ++++++++++++++++++++++++++ target/hexagon/tag_rev_info.c.inc | 23 ++++ target/hexagon/imported/encode_pp.def | 19 ++++ target/hexagon/imported/ldst.idef | 21 ++++ target/hexagon/imported/system.idef | 2 + tests/tcg/hexagon/meson.build | 1 + 8 files changed, 251 insertions(+), 6 deletions(-) create mode 100644 tests/tcg/hexagon/v79_scalar.c diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.= h.inc index d12f6ac4b1a..8b4eb27d682 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -21,6 +21,8 @@ DEF_ATTRIB(AA_DUMMY, "Dummy Zeroth Attribute", "", "") /* Misc */ DEF_ATTRIB(EXTENSION, "Extension instruction", "", "") =20 +DEF_ATTRIB(NA_NT, "Non-Allocating Non-Temporal instruction", "", "") + DEF_ATTRIB(PRIV, "Not available in user or guest mode", "", "") DEF_ATTRIB(GUEST, "Not available in user mode", "", "") =20 diff --git a/tests/tcg/hexagon/check_rev_gating.c b/tests/tcg/hexagon/check= _rev_gating.c index d5295bf24ab..3f48ab9cd35 100644 --- a/tests/tcg/hexagon/check_rev_gating.c +++ b/tests/tcg/hexagon/check_rev_gating.c @@ -3,12 +3,15 @@ * are rejected with SIGILL. * * Compiled with -mv66 so that e_flags selects CPU v66. The test embeds - * instructions from v68 through v73 via .word encoding: the assembler - * enforces the selected CPU's own minimum version, so none of these -- - * including ones it otherwise knows how to assemble at their own - * target, such as callrh or unpause -- can be written as themselves in - * a file built for v66. The revision-gated decoder must reject every - * one of them, and linux-user must deliver SIGILL. + * instructions from v68 up through v79 via .word encoding: the + * assembler enforces the selected CPU's own minimum version, so none + * of these -- including ones it otherwise knows how to assemble at + * their own target, such as callrh or unpause -- can be written as + * themselves in a file built for v66. The v79 non-temporal hints + * (":nt") aren't known to the assembler at any target yet, so those + * would need .word regardless. The revision-gated decoder must reject + * representative instructions from each family, and linux-user must + * deliver SIGILL. * * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * SPDX-License-Identifier: GPL-2.0-or-later @@ -108,6 +111,17 @@ TRY_FUNC(v73_jumprh, TRY_FUNC(v73_unpause, ".word 0x57e0d000 /* unpause */\n") =20 +TRY_FUNC(v79_storeri_pi_nt, + ".word 0xaa82c308 /* memw(r2++#4):nt =3D r3 */\n") +TRY_FUNC(v79_pstorerit_pi_nt, + ".word 0xaa82e308 /* if (p0) memw(r2++#4):nt =3D r3 */\n") +TRY_FUNC(v79_pstorerif_pi_nt, + ".word 0xaa82e30c /* if (!p0) memw(r2++#4):nt =3D r3 */\n") +TRY_FUNC(v79_dczeroa_nt, + ".word 0xa0c2e000 /* dczeroa(r2):nt */\n") +TRY_FUNC(v79_dcfetchbo_nt, + ".word 0x9402e000 /* dcfetch(r2+#0):nt */\n") + int main(void) { struct sigaction act; @@ -140,6 +154,12 @@ int main(void) assert(try_v73_jumprh() =3D=3D SIGILL); assert(try_v73_unpause() =3D=3D SIGILL); =20 + assert(try_v79_storeri_pi_nt() =3D=3D SIGILL); + assert(try_v79_pstorerit_pi_nt() =3D=3D SIGILL); + assert(try_v79_pstorerif_pi_nt() =3D=3D SIGILL); + assert(try_v79_dczeroa_nt() =3D=3D SIGILL); + assert(try_v79_dcfetchbo_nt() =3D=3D SIGILL); + assert(signals_handled =3D=3D expected_signals); =20 puts("PASS"); diff --git a/tests/tcg/hexagon/v79_scalar.c b/tests/tcg/hexagon/v79_scalar.c new file mode 100644 index 00000000000..81eb277b739 --- /dev/null +++ b/tests/tcg/hexagon/v79_scalar.c @@ -0,0 +1,157 @@ +/* + * Test the scalar core instructions that are new in v79. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include + +int err; + +static void __check32(int line, uint32_t result, uint32_t expect) +{ + if (result !=3D expect) { + printf("ERROR at line %d: 0x%08x !=3D 0x%08x\n", line, result, exp= ect); + err++; + } +} + +#define check32(RES, EXP) __check32(__LINE__, RES, EXP) + +static uint32_t sbuf[4]; +static uint32_t newp; + +/* S2_storeri_pi_nt: memw(Rx32++#4):nt =3D Rt32 */ +static void test_storeri_pi_nt(void) +{ + uint32_t *p =3D sbuf; + + memset(sbuf, 0xff, sizeof(sbuf)); + asm volatile( + "r2 =3D %1\n\t" + "r3 =3D #0x12345678\n\t" + ".word 0xaa82c308\n\t" /* memw(r2++#4):nt =3D r3 */ + "r5 =3D ##newp\n\t" + "memw(r5 + #0) =3D r2\n\t" + : "+m"(newp) + : "r"(p) + : "r2", "r3", "r5", "memory"); + check32(sbuf[0], 0x12345678); + check32(newp, (uint32_t)(uintptr_t)(sbuf + 1)); +} + +static uint8_t bbuf[4]; + +/* S2_storerb_pi_nt: memb(Rx32++#1):nt =3D Rt32 */ +static void test_storerb_pi_nt(void) +{ + uint32_t *p =3D (uint32_t *)bbuf; + + memset(bbuf, 0xff, sizeof(bbuf)); + asm volatile( + "r2 =3D %1\n\t" + "r3 =3D #0x42\n\t" + ".word 0xaa02c308\n\t" /* memb(r2++#1):nt =3D r3 */ + "r5 =3D ##newp\n\t" + "memw(r5 + #0) =3D r2\n\t" + : "+m"(newp) + : "r"(p) + : "r2", "r3", "r5", "memory"); + check32(bbuf[0], 0x42); + check32(newp, (uint32_t)(uintptr_t)(bbuf + 1)); +} + +/* S2_pstorerit_pi_nt: if (Pv4) memw(Rx32++#4):nt =3D Rt32, predicate true= */ +static void test_pstorerit_pi_nt(void) +{ + uint32_t *p =3D sbuf; + + memset(sbuf, 0xff, sizeof(sbuf)); + asm volatile( + "p0 =3D cmp.eq(r0, r0)\n\t" /* P0 =3D true */ + "r2 =3D %1\n\t" + "r3 =3D #0x11223344\n\t" + ".word 0xaa82e308\n\t" /* if (p0) memw(r2++#4):nt =3D r3 */ + "r5 =3D ##newp\n\t" + "memw(r5 + #0) =3D r2\n\t" + : "+m"(newp) + : "r"(p) + : "r0", "r2", "r3", "r5", "p0", "memory"); + check32(sbuf[0], 0x11223344); + check32(newp, (uint32_t)(uintptr_t)(sbuf + 1)); +} + +/* S2_pstorerif_pi_nt: if (!Pv4) memw(Rx32++#4):nt =3D Rt32, predicate fal= se */ +static void test_pstorerif_pi_nt(void) +{ + uint32_t *p =3D sbuf; + + memset(sbuf, 0xff, sizeof(sbuf)); + asm volatile( + "r0 =3D #1\n\t" + "r1 =3D #2\n\t" + "p0 =3D cmp.eq(r0, r1)\n\t" /* P0 =3D false */ + "r2 =3D %1\n\t" + "r3 =3D #0x99887766\n\t" + ".word 0xaa82e30c\n\t" /* if (!p0) memw(r2++#4):nt =3D r3 */ + "r5 =3D ##newp\n\t" + "memw(r5 + #0) =3D r2\n\t" + : "+m"(newp) + : "r"(p) + : "r0", "r1", "r2", "r3", "r5", "p0", "memory"); + check32(sbuf[0], 0x99887766); + check32(newp, (uint32_t)(uintptr_t)(sbuf + 1)); +} + +/* Y2_dczeroa_nt: dczeroa(Rs32):nt -- zeroes a 32-byte cacheline */ +static uint8_t cz[64] __attribute__((aligned(32))); + +static void test_dczeroa_nt(void) +{ + memset(cz, 0xaa, sizeof(cz)); + asm volatile( + "r2 =3D %1\n\t" + ".word 0xa0c2e000\n\t" /* dczeroa(r2):nt */ + : "+m"(cz) + : "r"(cz) + : "r2", "memory"); + for (int i =3D 0; i < 32; i++) { + check32(cz[i], 0); + } + for (int i =3D 32; i < 64; i++) { + check32(cz[i], 0xaa); + } +} + +/* Y2_dcfetchbo_nt: dcfetch(Rs32+#0):nt -- a hint, must not fault or store= */ +static uint8_t df[32] __attribute__((aligned(8))); + +static void test_dcfetchbo_nt(void) +{ + memset(df, 0x55, sizeof(df)); + asm volatile( + "r2 =3D %1\n\t" + ".word 0x9402e000\n\t" /* dcfetch(r2+#0):nt */ + : "+m"(df) + : "r"(df) + : "r2", "memory"); + for (int i =3D 0; i < 32; i++) { + check32(df[i], 0x55); + } +} + +int main() +{ + test_storeri_pi_nt(); + test_storerb_pi_nt(); + test_pstorerit_pi_nt(); + test_pstorerif_pi_nt(); + test_dczeroa_nt(); + test_dcfetchbo_nt(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_inf= o.c.inc index 44513f46809..48bdc52bfdb 100644 --- a/target/hexagon/tag_rev_info.c.inc +++ b/target/hexagon/tag_rev_info.c.inc @@ -619,6 +619,29 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_= OPCODE] =3D { [V6_vassign_tmp] =3D { .introduced =3D HEX_VER_V69, .removed =3D HEX_V= ER_NONE }, [V6_vcombine_tmp] =3D { .introduced =3D HEX_VER_V69, .removed =3D HEX_= VER_NONE }, [V6_vmpyuhvs] =3D { .introduced =3D HEX_VER_V69, .removed =3D HEX_VER_= NONE }, + + [S2_pstorerbf_pi_nt] =3D { .introduced =3D HEX_VER_V79, + .removed =3D HEX_VER_NONE }, + [S2_pstorerbt_pi_nt] =3D { .introduced =3D HEX_VER_V79, + .removed =3D HEX_VER_NONE }, + [S2_pstorerdf_pi_nt] =3D { .introduced =3D HEX_VER_V79, + .removed =3D HEX_VER_NONE }, + [S2_pstorerdt_pi_nt] =3D { .introduced =3D HEX_VER_V79, + .removed =3D HEX_VER_NONE }, + [S2_pstorerhf_pi_nt] =3D { .introduced =3D HEX_VER_V79, + .removed =3D HEX_VER_NONE }, + [S2_pstorerht_pi_nt] =3D { .introduced =3D HEX_VER_V79, + .removed =3D HEX_VER_NONE }, + [S2_pstorerif_pi_nt] =3D { .introduced =3D HEX_VER_V79, + .removed =3D HEX_VER_NONE }, + [S2_pstorerit_pi_nt] =3D { .introduced =3D HEX_VER_V79, + .removed =3D HEX_VER_NONE }, + [S2_storerb_pi_nt] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX= _VER_NONE }, + [S2_storerd_pi_nt] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX= _VER_NONE }, + [S2_storerh_pi_nt] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX= _VER_NONE }, + [S2_storeri_pi_nt] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX= _VER_NONE }, + [Y2_dcfetchbo_nt] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_= VER_NONE }, + [Y2_dczeroa_nt] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VE= R_NONE }, }; =20 #endif /* HEXAGON_TAG_ARCH_TABLE_H */ diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index 1fce318b2bb..fca8f8aeb1a 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -407,6 +407,7 @@ DEF_ENC32(R6_release_st_vi, ICLASS_ST" 000 01 11sssss= PP0ttttt --1011dd") =20 DEF_EXT_SPACE(EXTRACTW, ICLASS_LD" 001 0 000 iiiii PP0iiiii 001iiiii") DEF_ENC32(Y2_dcfetchbo, ICLASS_LD" 010 0 000 sssss PP0--iii iiiiiiii") +DEF_ENC32(Y2_dcfetchbo_nt,"10010100000sssssPP10-iiiiiiiiiii") =20 =20 =20 @@ -473,6 +474,13 @@ STD_ST_ENC(rbnew, "1 101","00ttt") STD_ST_ENC(rhnew, "1 101","01ttt") STD_ST_ENC(rinew, "1 101","10ttt") =20 +/* Non-temporal post-increment stores: the OPC nibble's high bit, always + * 1 above, is repurposed as the "nt" hint for this addressing mode only. = */ +DEF_ENC32(S2_storerb_pi_nt,"10101010000xxxxxPP0ttttt0iiii-0-") +DEF_ENC32(S2_storerh_pi_nt,"10101010010xxxxxPP0ttttt0iiii-0-") +DEF_ENC32(S2_storeri_pi_nt,"10101010100xxxxxPP0ttttt0iiii-0-") +DEF_ENC32(S2_storerd_pi_nt,"10101010110xxxxxPP0ttttt0iiii-00") + STD_PST_ENC(rb, "1 000","ttttt") STD_PST_ENC(rh, "1 010","ttttt") STD_PST_ENC(rf, "1 011","ttttt") @@ -482,6 +490,16 @@ STD_PST_ENC(rbnew, "1 101","00ttt") STD_PST_ENC(rhnew, "1 101","01ttt") STD_PST_ENC(rinew, "1 101","10ttt") =20 +/* Predicated forms of the non-temporal post-increment stores above. */ +DEF_ENC32(S2_pstorerbt_pi_nt,"10101010000xxxxxPP1ttttt0iiii0vv") +DEF_ENC32(S2_pstorerbf_pi_nt,"10101010000xxxxxPP1ttttt0iiii1vv") +DEF_ENC32(S2_pstorerht_pi_nt,"10101010010xxxxxPP1ttttt0iiii0vv") +DEF_ENC32(S2_pstorerhf_pi_nt,"10101010010xxxxxPP1ttttt0iiii1vv") +DEF_ENC32(S2_pstorerit_pi_nt,"10101010100xxxxxPP1ttttt0iiii0vv") +DEF_ENC32(S2_pstorerif_pi_nt,"10101010100xxxxxPP1ttttt0iiii1vv") +DEF_ENC32(S2_pstorerdt_pi_nt,"10101010110xxxxxPP1ttttt0iiii0vv") +DEF_ENC32(S2_pstorerdf_pi_nt,"10101010110xxxxxPP1ttttt0iiii1vv") + =20 =20 /* User */ @@ -492,6 +510,7 @@ STD_PST_ENC(rinew, "1 101","10ttt") DEF_ENC32(S2_allocframe, ICLASS_ST" 000 01 00xxxxx PP000iii iiiiiiii") DEF_ENC32(Y5_l2locka, ICLASS_ST" 000 01 11sssss PP1----- ------dd") DEF_ENC32(Y2_dczeroa, ICLASS_ST" 000 01 10sssss PP0----- --------") +DEF_ENC32(Y2_dczeroa_nt,"10100000110sssssPP1-------------") =20 =20 DEF_ENC32(Y2_barrier, ICLASS_ST" 100 00 00----- PP------ 000-----") diff --git a/target/hexagon/imported/ldst.idef b/target/hexagon/imported/ld= st.idef index 4e1e5d5326d..7106a0c572c 100644 --- a/target/hexagon/imported/ldst.idef +++ b/target/hexagon/imported/ldst.idef @@ -118,6 +118,16 @@ STD_ST_AMODES(storerh, "Rt32", "memh","Store Half inte= ger",ATTRIBS(A_REGWRSIZE_2 STD_ST_AMODES(storerf, "Rt.H32", "memh","Store Upper Half integer",ATTRIBS= (A_REGWRSIZE_2B,A_MEMSIZE_2B,A_STORE),"1",fSTORE(1,2,EA,fGETHALF(1,RtV)),1) STD_ST_AMODES(storeri, "Rt32", "memw","Store Word",ATTRIBS(A_REGWRSIZE_4B,= A_MEMSIZE_4B,A_STORE),"2",fSTORE(1,4,EA,RtV),2) STD_ST_AMODES(storerd, "Rtt32","memd","Store Double integer",ATTRIBS(A_REG= WRSIZE_8B,A_MEMSIZE_8B,A_STORE),"3",fSTORE(1,8,EA,RttV),3) + +/* + * Non-temporal post-increment stores: same store, with a cache-locality + * hint that a normal-priority cache line is unlikely to be reused soon. + */ +Q6INSN(S2_storerb_pi_nt,"memb(Rx32++#s4:0):nt=3DRt32",ATTRIBS(A_ARCHV2,A_M= EMSIZE_1B,A_STORE,A_NA_NT),"Store Byte",{fEA_REG(RxV); fPM_I(RxV,siV); fSTO= RE(1,1,EA,fGETBYTE(0,RtV)); }) +Q6INSN(S2_storerh_pi_nt,"memh(Rx32++#s4:1):nt=3DRt32",ATTRIBS(A_REGWRSIZE_= 2B,A_ARCHV2,A_MEMSIZE_2B,A_STORE,A_NA_NT),"Store Half integer",{fEA_REG(RxV= ); fPM_I(RxV,siV); fSTORE(1,2,EA,fGETHALF(0,RtV)); }) +Q6INSN(S2_storeri_pi_nt,"memw(Rx32++#s4:2):nt=3DRt32",ATTRIBS(A_REGWRSIZE_= 4B,A_ARCHV2,A_MEMSIZE_4B,A_STORE,A_NA_NT),"Store Word",{fEA_REG(RxV); fPM_I= (RxV,siV); fSTORE(1,4,EA,RtV); }) +Q6INSN(S2_storerd_pi_nt,"memd(Rx32++#s4:3):nt=3DRtt32",ATTRIBS(A_REGWRSIZE= _8B,A_ARCHV2,A_MEMSIZE_8B,A_STORE,A_NA_NT),"Store Double integer",{fEA_REG(= RxV); fPM_I(RxV,siV); fSTORE(1,8,EA,RttV); }) + STD_ST_AMODES(storerinew, "Nt8.new", "memw","Store Word",ATTRIBS(A_REGWRSI= ZE_4B,A_NOTE_NEWVAL_SLOT0,A_NVSTORE,A_NOTE_NVSLOT0,A_MEMSIZE_4B,A_STORE,A_R= ESTRICT_NOSLOT1_STORE),"2",fSTORE(1,4,EA,fNEWREG_ST(NtN)),2) STD_ST_AMODES(storerbnew, "Nt8.new", "memb","Store Byte",ATTRIBS(A_NOTE_NE= WVAL_SLOT0,A_NVSTORE,A_NOTE_NVSLOT0,A_MEMSIZE_1B,A_STORE,A_RESTRICT_NOSLOT1= _STORE),"0",fSTORE(1,1,EA,fGETBYTE(0,fNEWREG_ST(NtN))),0) STD_ST_AMODES(storerhnew, "Nt8.new", "memh","Store Half integer",ATTRIBS(A= _REGWRSIZE_2B,A_NOTE_NEWVAL_SLOT0,A_NVSTORE,A_NOTE_NVSLOT0,A_MEMSIZE_2B,A_S= TORE,A_RESTRICT_NOSLOT1_STORE),"1",fSTORE(1,2,EA,fGETHALF(0,fNEWREG_ST(NtN)= )),1) @@ -277,6 +287,17 @@ STD_PST_AMODES(storerh,"Rt32","memh","Store Half integ= er",ATTRIBS(A_REGWRSIZE_2B STD_PST_AMODES(storerf,"Rt.H32","memh","Store Upper Half integer",ATTRIBS(= A_REGWRSIZE_2B,A_ARCHV2,A_MEMSIZE_2B,A_STORE),"1",1,fSTORE(1,2,EA,fGETHALF(= 1,RtV))) STD_PST_AMODES(storeri,"Rt32","memw","Store Word",ATTRIBS(A_REGWRSIZE_4B,A= _ARCHV2,A_MEMSIZE_4B,A_STORE),"2",2,fSTORE(1,4,EA,RtV)) STD_PST_AMODES(storerd,"Rtt32","memd","Store Double integer",ATTRIBS(A_REG= WRSIZE_8B,A_ARCHV2,A_MEMSIZE_8B,A_STORE),"3",3,fSTORE(1,8,EA,RttV)) + +/* Predicated forms of the non-temporal post-increment stores above. */ +Q6INSN(S2_pstorerbt_pi_nt,"if (Pv4) memb(Rx32++#s4:0):nt=3DRt32",ATTRIBS(A= _ARCHV2,A_MEMSIZE_1B,A_STORE,A_NA_NT),"Store Byte",{fEA_REG(RxV); if (fLSBO= LD(PvV)){ fPM_I(RxV,siV); fSTORE(1,1,EA,fGETBYTE(0,RtV));} else {STORE_CANC= EL(EA);}}) +Q6INSN(S2_pstorerbf_pi_nt,"if (!Pv4) memb(Rx32++#s4:0):nt=3DRt32",ATTRIBS(= A_ARCHV2,A_MEMSIZE_1B,A_STORE,A_NA_NT),"Store Byte",{fEA_REG(RxV); if (fLSB= OLDNOT(PvV)){ fPM_I(RxV,siV); fSTORE(1,1,EA,fGETBYTE(0,RtV));} else {STORE_= CANCEL(EA);}}) +Q6INSN(S2_pstorerht_pi_nt,"if (Pv4) memh(Rx32++#s4:1):nt=3DRt32",ATTRIBS(A= _REGWRSIZE_2B,A_ARCHV2,A_MEMSIZE_2B,A_STORE,A_NA_NT),"Store Half integer",{= fEA_REG(RxV); if (fLSBOLD(PvV)){ fPM_I(RxV,siV); fSTORE(1,2,EA,fGETHALF(0,R= tV));} else {STORE_CANCEL(EA);}}) +Q6INSN(S2_pstorerhf_pi_nt,"if (!Pv4) memh(Rx32++#s4:1):nt=3DRt32",ATTRIBS(= A_REGWRSIZE_2B,A_ARCHV2,A_MEMSIZE_2B,A_STORE,A_NA_NT),"Store Half integer",= {fEA_REG(RxV); if (fLSBOLDNOT(PvV)){ fPM_I(RxV,siV); fSTORE(1,2,EA,fGETHALF= (0,RtV));} else {STORE_CANCEL(EA);}}) +Q6INSN(S2_pstorerit_pi_nt,"if (Pv4) memw(Rx32++#s4:2):nt=3DRt32",ATTRIBS(A= _REGWRSIZE_4B,A_ARCHV2,A_MEMSIZE_4B,A_STORE,A_NA_NT),"Store Word",{fEA_REG(= RxV); if (fLSBOLD(PvV)){ fPM_I(RxV,siV); fSTORE(1,4,EA,RtV);} else {STORE_C= ANCEL(EA);}}) +Q6INSN(S2_pstorerif_pi_nt,"if (!Pv4) memw(Rx32++#s4:2):nt=3DRt32",ATTRIBS(= A_REGWRSIZE_4B,A_ARCHV2,A_MEMSIZE_4B,A_STORE,A_NA_NT),"Store Word",{fEA_REG= (RxV); if (fLSBOLDNOT(PvV)){ fPM_I(RxV,siV); fSTORE(1,4,EA,RtV);} else {STO= RE_CANCEL(EA);}}) +Q6INSN(S2_pstorerdt_pi_nt,"if (Pv4) memd(Rx32++#s4:3):nt=3DRtt32",ATTRIBS(= A_REGWRSIZE_8B,A_ARCHV2,A_MEMSIZE_8B,A_STORE,A_NA_NT),"Store Double integer= ",{fEA_REG(RxV); if (fLSBOLD(PvV)){ fPM_I(RxV,siV); fSTORE(1,8,EA,RttV);} e= lse {STORE_CANCEL(EA);}}) +Q6INSN(S2_pstorerdf_pi_nt,"if (!Pv4) memd(Rx32++#s4:3):nt=3DRtt32",ATTRIBS= (A_REGWRSIZE_8B,A_ARCHV2,A_MEMSIZE_8B,A_STORE,A_NA_NT),"Store Double intege= r",{fEA_REG(RxV); if (fLSBOLDNOT(PvV)){ fPM_I(RxV,siV); fSTORE(1,8,EA,RttV)= ;} else {STORE_CANCEL(EA);}}) + STD_PST_AMODES(storerinew,"Nt8.new","memw","Store Word",ATTRIBS(A_REGWRSIZ= E_4B,A_ARCHV2,A_NOTE_NEWVAL_SLOT0,A_NVSTORE,A_NOTE_NVSLOT0,A_MEMSIZE_4B,A_S= TORE,A_RESTRICT_NOSLOT1_STORE),"2",2,fSTORE(1,4,EA,fNEWREG_ST(NtN))) STD_PST_AMODES(storerbnew,"Nt8.new","memb","Store Byte",ATTRIBS(A_ARCHV2,A= _NOTE_NEWVAL_SLOT0,A_NVSTORE,A_NOTE_NVSLOT0,A_MEMSIZE_1B,A_STORE,A_RESTRICT= _NOSLOT1_STORE),"0",0,fSTORE(1,1,EA,fGETBYTE(0,fNEWREG_ST(NtN)))) STD_PST_AMODES(storerhnew,"Nt8.new","memh","Store Half integer",ATTRIBS(A_= REGWRSIZE_2B,A_ARCHV2,A_NOTE_NEWVAL_SLOT0,A_NVSTORE,A_NOTE_NVSLOT0,A_MEMSIZ= E_2B,A_STORE,A_RESTRICT_NOSLOT1_STORE),"1",1,fSTORE(1,2,EA,fGETHALF(0,fNEWR= EG_ST(NtN)))) diff --git a/target/hexagon/imported/system.idef b/target/hexagon/imported/= system.idef index b44e87565c3..6187ada5abb 100644 --- a/target/hexagon/imported/system.idef +++ b/target/hexagon/imported/system.idef @@ -238,10 +238,12 @@ Q6INSN(Y6_dmresume,"dmresume(Rs32)",ATTRIBS(A_NOTE_NO= PACKET,A_RESTRICT_NOPACKET, =20 =20 Q6INSN(Y2_dcfetchbo,"dcfetch(Rs32+#u11:3)",ATTRIBS(A_RESTRICT_PREFERSLOT0,= A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fEA_RI(RsV,uiV);= fDCFETCH(EA);}) +Q6INSN(Y2_dcfetchbo_nt,"dcfetch(Rs32+#u11:3):nt",ATTRIBS(A_NA_NT,A_RESTRIC= T_PREFERSLOT0,A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fE= A_RI(RsV,uiV); fDCFETCH(EA);}) Q6INSN(Y2_dckill,"dckill",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RES= TRICT_SLOT0ONLY,A_RESTRICT_NOPACKET,A_CACHEOP,A_DCFLUSHOP),"Data Cache Inva= lidate",{fDCKILL();}) =20 =20 Q6INSN(Y2_dczeroa,"dczeroa(Rs32)",ATTRIBS(A_STORE,A_RESTRICT_SLOT1_AOK,A_N= OTE_SLOT1_AOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYADDRESS,A_DCZEROA),"Zer= o an aligned 32-byte cacheline",{fEA_REG(RsV); fDCZEROA(EA);}) +Q6INSN(Y2_dczeroa_nt,"dczeroa(Rs32):nt",ATTRIBS(A_STORE,A_RESTRICT_SLOT1_A= OK,A_NOTE_SLOT1_AOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYADDRESS,A_DCZEROA= ,A_NA_NT),"Zero an aligned 32-byte cacheline",{fEA_REG(RsV); fDCZEROA(EA);}) Q6INSN(Y2_dccleana,"dccleana(Rs32)",ATTRIBS(A_RESTRICT_SLOT1_AOK,A_NOTE_SL= OT1_AOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYADDRESS,A_DCFLUSHOP),"Data Ca= che Clean Address",{fEA_REG(RsV); fDCCLEANA(EA);}) Q6INSN(Y2_dccleanidx,"dccleanidx(Rs32)",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_RESTR= ICT_PACKET_AXOK,A_NOTE_AXOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYIDX,A_DCF= LUSHOP),"Data Cache Clean Index",{fDCCLEANIDX(RsV);}) Q6INSN(Y2_dccleaninva,"dccleaninva(Rs32)",ATTRIBS(A_RESTRICT_SLOT1_AOK,A_N= OTE_SLOT1_AOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYADDRESS,A_DCFLUSHOP),"D= ata Cache Clean and Invalidate Address",{fEA_REG(RsV); fDCCLEANINVA(EA);}) diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build index 4a2826c4276..6e36a9a1220 100644 --- a/tests/tcg/hexagon/meson.build +++ b/tests/tcg/hexagon/meson.build @@ -101,6 +101,7 @@ tests +=3D { 'v68_hvx.c': {'cflags': [cflags, '-mhvx', '-Wno-unused-function', '-mv68= ']}, 'v69_hvx.c': {'cflags': [cflags, '-mhvx', '-Wno-unused-function', '-mv69= ']}, 'v73_scalar.c': {'cflags': [cflags, '-Wno-unused-function', '-mv73']}, + 'v79_scalar.c': {'cflags': [cflags, '-Wno-unused-function', '-mv79']}, 'valid-slots.c': {'cflags': cflags}, 'vector_add_int.c': {'cflags': [cflags, '-mhvx', '-fvectorize']}, } --=20 2.34.1 From nobody Sat Sep 26 20:01:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788926557365158500 Y2_tlbpp is mostly associated with the not-yet-implemented DMA engine. Let's decode it as unimpl for now. Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- target/hexagon/sys_macros.h | 3 +++ target/hexagon/attribs_def.h.inc | 1 + target/hexagon/tag_rev_info.c.inc | 2 ++ target/hexagon/imported/encode_pp.def | 1 + target/hexagon/imported/system.idef | 2 ++ 5 files changed, 9 insertions(+) diff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h index a49c72715dc..2e13ba00c8a 100644 --- a/target/hexagon/sys_macros.h +++ b/target/hexagon/sys_macros.h @@ -177,6 +177,9 @@ fTLB_NONPOW2WRAP(fTLB_IDXMASK(INDEX))) #define fTLBP(TLBHI) \ hex_tlb_lookup(env, ((TLBHI) >> 12), ((TLBHI) << 12)) +#define fTLBPP(TLBHI) ({ \ + qemu_log_mask(LOG_UNIMP, "tlbpp is not implemented\n"); \ + 0; }) #define iic_flush_cache(p) =20 #define fIN_DEBUG_MODE(TNUM) ({ \ diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.= h.inc index 8b4eb27d682..5a98ea33139 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -25,6 +25,7 @@ DEF_ATTRIB(NA_NT, "Non-Allocating Non-Temporal instructio= n", "", "") =20 DEF_ATTRIB(PRIV, "Not available in user or guest mode", "", "") DEF_ATTRIB(GUEST, "Not available in user mode", "", "") +DEF_ATTRIB(TLBPP_INSN, "Extended (64-bit VA) TLB probe instruction", "", "= ") =20 DEF_ATTRIB(FPOP, "Floating Point Operation", "", "") =20 diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_inf= o.c.inc index 48bdc52bfdb..68be8cbafb2 100644 --- a/target/hexagon/tag_rev_info.c.inc +++ b/target/hexagon/tag_rev_info.c.inc @@ -642,6 +642,8 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_O= PCODE] =3D { [S2_storeri_pi_nt] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX= _VER_NONE }, [Y2_dcfetchbo_nt] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_= VER_NONE }, [Y2_dczeroa_nt] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VE= R_NONE }, + + [Y2_tlbpp] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NON= E }, }; =20 #endif /* HEXAGON_TAG_ARCH_TABLE_H */ diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index fca8f8aeb1a..4b307b97b30 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -890,6 +890,7 @@ DEF_ENC32(Y2_tlbunlock,ICLASS_CR" 1100 001----- PP-----= - 010-----") DEF_ENC32(Y2_k0lock, ICLASS_CR" 1100 001----- PP------ 011-----") DEF_ENC32(Y2_k0unlock, ICLASS_CR" 1100 001----- PP------ 100-----") DEF_ENC32(Y2_tlbp, ICLASS_CR" 1100 100sssss PP------ ---ddddd") +DEF_ENC32(Y2_tlbpp,"01101100011sssssPP---------ddddd") DEF_ENC32(Y5_tlboc, ICLASS_CR" 1100 111sssss PP------ ---ddddd") DEF_ENC32(Y5_tlbasidi, ICLASS_CR" 1100 101sssss PP------ --------") DEF_ENC32(Y2_tlbr, ICLASS_CR" 1100 010sssss PP------ ---ddddd") diff --git a/target/hexagon/imported/system.idef b/target/hexagon/imported/= system.idef index 6187ada5abb..a58da8f8269 100644 --- a/target/hexagon/imported/system.idef +++ b/target/hexagon/imported/system.idef @@ -118,6 +118,8 @@ Q6INSN(Y2_tlbr,"Rdd32=3Dtlbr(Rs32)", ATTRIBS(A_PRIV,A_N= OTE_PRIV,A_NOTE_NOPACKET,A_ =20 Q6INSN(Y2_tlbp,"Rd32=3Dtlbp(Rs32)", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPA= CKET,A_RESTRICT_NOPACKET), "Probe TLB", {RdV=3DfTLBP(RsV);}) =20 +Q6INSN(Y2_tlbpp,"Rd32=3Dtlbp(Rss32)", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NO= PACKET,A_RESTRICT_NOPACKET,A_TLBPP_INSN), "Probe TLB64", {RdV=3DfTLBPP(RssV= );}) + Q6INSN(Y5_tlbasidi,"tlbinvasid(Rs32)",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NO= PACKET,A_RESTRICT_NOPACKET), "Invalidate ASID", { fHIDE(int i;) --=20 2.34.1 From nobody Sat Sep 26 20:01:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788926570808158500 Add these new machines that correspond to the hexagon-sim machine types. Signed-off-by: Brian Cain Reviewed-by: Marco Liebel --- include/hw/hexagon/hexagon.h | 11 ++++ target/hexagon/cpu.h | 2 +- hw/hexagon/machine_cfg_v81dgb_1.h.inc | 73 +++++++++++++++++++++++++++ hw/hexagon/machine_cfg_v81qa_1.h.inc | 73 +++++++++++++++++++++++++++ hw/hexagon/hexagon_dsp.c | 46 +++++++++++++++++ 5 files changed, 204 insertions(+), 1 deletion(-) create mode 100644 hw/hexagon/machine_cfg_v81dgb_1.h.inc create mode 100644 hw/hexagon/machine_cfg_v81qa_1.h.inc diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index 3d7b3cb12dc..62398eeb359 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -27,6 +27,8 @@ typedef enum { v71_rev =3D 0x8c71, v73_rev =3D 0x8c73, v73m_rev =3D 0xcc73, + v81_rev =3D 0x8781, + v81dgb_1_rev =3D 0xcc81, } Rev_t; #define HEXAGON_LATEST_REV v73 #define HEXAGON_LATEST_REV_UPPER V73 @@ -129,6 +131,15 @@ union hexagon_config_table { uint32_t corecfg_present; uint32_t coproc2_fp16_acc_exp; uint32_t AXIM2_secondary_base; + uint32_t AXIM_data_width; + /* Number of L1 data cache ways */ + uint32_t l1d_ways; + /* Number of L1 instruction cache ways */ + uint32_t l1i_ways; + /* Number of L2 cache ways */ + uint32_t l2way_num; + /* Number of DMA JTLB entries */ + uint32_t dma_jtlb_entries; }; uint32_t raw[HEXAGON_CFGSPACE_ENTRIES]; }; diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 8a4a81dc26c..719979d6c31 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -50,7 +50,7 @@ typedef struct HexagonGlobalRegState HexagonGlobalRegStat= e; #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ #define VSTORES_MAX 2 #define MAX_TLB_ENTRIES 1024 -#define THREADS_MAX 8 +#define THREADS_MAX 16 =20 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU #ifndef CONFIG_USER_ONLY diff --git a/hw/hexagon/machine_cfg_v81dgb_1.h.inc b/hw/hexagon/machine_cfg= _v81dgb_1.h.inc new file mode 100644 index 00000000000..c7d9e7e1927 --- /dev/null +++ b/hw/hexagon/machine_cfg_v81dgb_1.h.inc @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +static const struct hexagon_machine_config v81dgb_1 =3D { + .cfgbase =3D 0xd8380000, + .l2tcm_size =3D 0x00000000, + .l2vic_base =3D 0xfc910000, + .l2vic_size =3D 0x00001000, + .csr_base =3D 0xfc900000, + .qtmr_region =3D 0xfc921000, + .cfgtable =3D { + .l2tcm_base =3D 0x0000d800, + .reserved0 =3D 0x00000000, + .subsystem_base =3D 0x0000fc90, + .etm_base =3D 0x0000d839, + .l2cfg_base =3D 0x0000d83a, + .reserved1 =3D 0x0000d83b, + .l1s0_base =3D 0x0000d840, + .axi2_lowaddr =3D 0x00000000, + .streamer_base =3D 0x00000000, + .reserved2 =3D 0x00000000, + .fastl2vic_base =3D 0x0000d83e, + .jtlb_size_entries =3D 0x000000c0, + .coproc_present =3D 0x00000005, + .ext_contexts =3D 0x00000004, + .vtcm_base =3D 0x0000d840, + .vtcm_size_kb =3D 0x00000800, + .l2tag_size =3D 0x00000800, + .l2ecomem_size =3D 0x00000800, + .thread_enable_mask =3D 0x00000fff, + .eccreg_base =3D 0x00000000, + .l2line_size =3D 0x00000080, + .tiny_core =3D 0x00000000, + .l2itcm_size =3D 0x00000000, + .l2itcm_base =3D 0x0000d800, + .reserved3 =3D 0x00000000, + .dtm_present =3D 0x00000000, + .dma_version =3D 0x00000000, + .hvx_vec_log_length =3D 0x00000007, + .core_id =3D 0x00000000, + .core_count =3D 0x00000000, + .coproc2_reg0 =3D 0x00000001, + .coproc2_reg1 =3D 0x00000000, + .v2x_mode =3D 0x00000000, + .coproc2_reg2 =3D 0x00000000, + .coproc2_reg3 =3D 0x00000000, + .coproc2_reg4 =3D 0x00000000, + .coproc2_reg5 =3D 0x00000000, + .coproc2_reg6 =3D 0x00000000, + .coproc2_reg7 =3D 0x00000000, + .acd_preset =3D 0x00000000, + .mnd_preset =3D 0x00000000, + .l1d_size_kb =3D 0x00000040, + .l1i_size_kb =3D 0x00000040, + .l1d_write_policy =3D 0x00000002, + .vtcm_bank_width =3D 0x00000080, + .reserved4 =3D 0x00000000, + .reserved5 =3D 0x00000000, + .reserved6 =3D 0x00000000, + .coproc2_cvt_mpy_size =3D 0x00000000, + .consistency_domain =3D 0x000000e0, + .capacity_domain =3D 0x00000080, + .axi3_lowaddr =3D 0x00004000, + .coproc2_int8_subcolumns =3D 0x00000000, + .corecfg_present =3D 0x0000000d, + .coproc2_fp16_acc_exp =3D 0x00000000, + .AXIM2_secondary_base =3D 0x00000000, + .AXIM_data_width =3D 0x00000000, + .l1d_ways =3D 0x00000008, + .l1i_ways =3D 0x00000004, + .l2way_num =3D 0x00000008, + .dma_jtlb_entries =3D 0x00000040, + }, +}; diff --git a/hw/hexagon/machine_cfg_v81qa_1.h.inc b/hw/hexagon/machine_cfg_= v81qa_1.h.inc new file mode 100644 index 00000000000..8fb9bcb174c --- /dev/null +++ b/hw/hexagon/machine_cfg_v81qa_1.h.inc @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +static const struct hexagon_machine_config v81qa_1 =3D { + .cfgbase =3D 0xd8380000, + .l2tcm_size =3D 0x00000000, + .l2vic_base =3D 0xfc910000, + .l2vic_size =3D 0x00001000, + .csr_base =3D 0xfc900000, + .qtmr_region =3D 0xfc921000, + .cfgtable =3D { + .l2tcm_base =3D 0x0000d800, + .reserved0 =3D 0x00000000, + .subsystem_base =3D 0x00002000, + .etm_base =3D 0x0000d819, + .l2cfg_base =3D 0x0000d81a, + .reserved1 =3D 0x0000d81b, + .l1s0_base =3D 0x0000d900, + .axi2_lowaddr =3D 0x00000000, + .streamer_base =3D 0x00000000, + .reserved2 =3D 0x00000000, + .fastl2vic_base =3D 0x0000d81e, + .jtlb_size_entries =3D 0x00000080, + .coproc_present =3D 0x0000000d, + .ext_contexts =3D 0x00000008, + .vtcm_base =3D 0x0000d900, + .vtcm_size_kb =3D 0x00004000, + .l2tag_size =3D 0x00000400, + .l2ecomem_size =3D 0x00000400, + .thread_enable_mask =3D 0x00000fff, + .eccreg_base =3D 0x0000d81f, + .l2line_size =3D 0x00000080, + .tiny_core =3D 0x00000000, + .l2itcm_size =3D 0x00000000, + .l2itcm_base =3D 0x0000d800, + .reserved3 =3D 0x00000000, + .dtm_present =3D 0x00000000, + .dma_version =3D 0x00000008, + .hvx_vec_log_length =3D 0x00000007, + .core_id =3D 0x00000000, + .core_count =3D 0x00000000, + .coproc2_reg0 =3D 0x00000010, + .coproc2_reg1 =3D 0x00000008, + .v2x_mode =3D 0x00000001, + .coproc2_reg2 =3D 0x00000000, + .coproc2_reg3 =3D 0x00000000, + .coproc2_reg4 =3D 0x00000000, + .coproc2_reg5 =3D 0x00000000, + .coproc2_reg6 =3D 0x00000000, + .coproc2_reg7 =3D 0x00000000, + .acd_preset =3D 0x00000001, + .mnd_preset =3D 0x00000001, + .l1d_size_kb =3D 0x00000040, + .l1i_size_kb =3D 0x00000040, + .l1d_write_policy =3D 0x00000002, + .vtcm_bank_width =3D 0x00000080, + .reserved4 =3D 0x00000001, + .reserved5 =3D 0x00000000, + .reserved6 =3D 0x00000000, + .coproc2_cvt_mpy_size =3D 0x00000000, + .consistency_domain =3D 0x000000e0, + .capacity_domain =3D 0x00000080, + .axi3_lowaddr =3D 0x00004000, + .coproc2_int8_subcolumns =3D 0x00000000, + .corecfg_present =3D 0x0000000d, + .coproc2_fp16_acc_exp =3D 0x00000001, + .AXIM2_secondary_base =3D 0x00000000, + .AXIM_data_width =3D 0x00000100, + .l1d_ways =3D 0x00000008, + .l1i_ways =3D 0x00000004, + .l2way_num =3D 0x00000008, + .dma_jtlb_entries =3D 0x00000040, + }, +}; diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c index ff110234b09..be17a32ee12 100644 --- a/hw/hexagon/hexagon_dsp.c +++ b/hw/hexagon/hexagon_dsp.c @@ -30,6 +30,8 @@ =20 #include "machine_cfg_v66g_1024.h.inc" #include "machine_cfg_v68n_1024.h.inc" +#include "machine_cfg_v81dgb_1.h.inc" +#include "machine_cfg_v81qa_1.h.inc" =20 #define TYPE_HEXAGON_DSP_MACHINE "hexagon-dsp-machine" OBJECT_DECLARE_SIMPLE_TYPE(HexagonDspMachineState, HEXAGON_DSP_MACHINE) @@ -199,6 +201,40 @@ static void v68n_1024_init(ObjectClass *oc, const void= *data) mc->default_cpus =3D 6; } =20 +static void v81dgb_1_config_init(MachineState *machine) +{ + hexagon_common_init(machine, v81dgb_1_rev, &v81dgb_1); +} + +static void v81dgb_1_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Hexagon V81DGB_1"; + mc->init =3D v81dgb_1_config_init; + init_mc(mc); + mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V81; + mc->max_cpus =3D 12; + mc->default_cpus =3D 12; +} + +static void v81qa_1_config_init(MachineState *machine) +{ + hexagon_common_init(machine, v81_rev, &v81qa_1); +} + +static void v81qa_1_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Hexagon V81QA_1"; + mc->init =3D v81qa_1_config_init; + init_mc(mc); + mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V81; + mc->max_cpus =3D 12; + mc->default_cpus =3D 12; +} + static const TypeInfo hexagon_machine_types[] =3D { { .name =3D TYPE_HEXAGON_COMMON_MACHINE, @@ -222,6 +258,16 @@ static const TypeInfo hexagon_machine_types[] =3D { .parent =3D TYPE_HEXAGON_DSP_MACHINE, .class_init =3D v68n_1024_init, }, + { + .name =3D MACHINE_TYPE_NAME("V81DGB_1"), + .parent =3D TYPE_HEXAGON_DSP_MACHINE, + .class_init =3D v81dgb_1_init, + }, + { + .name =3D MACHINE_TYPE_NAME("V81QA_1"), + .parent =3D TYPE_HEXAGON_DSP_MACHINE, + .class_init =3D v81qa_1_init, + }, }; =20 DEFINE_TYPES(hexagon_machine_types) --=20 2.34.1 From nobody Sat Sep 26 20:01:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 08 Sep 2026 21:01:55 -0700 (PDT) X-Received: by 2002:a05:6a21:3b89:b0:3da:421e:40f3 with SMTP id adf61e73a8af0-3dabb1d5fcfmr5466156637.17.1788926510286; Tue, 08 Sep 2026 21:01:50 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: marco.liebel@oss.qualcomm.com, Pierrick Bouvier , Laurent Vivier , Helge Deller , Brian Cain Subject: [PATCH v2 6/9] hw/hexagon: move "sim" alias to "V81QA_1" Date: Tue, 8 Sep 2026 21:01:34 -0700 Message-Id: <20260909040137.3414132-7-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260909040137.3414132-1-brian.cain@oss.qualcomm.com> References: <20260909040137.3414132-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: jAn3CJB1a4aqy9nHDkOc7lnpPaICPijX X-Proofpoint-ORIG-GUID: jAn3CJB1a4aqy9nHDkOc7lnpPaICPijX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDA0MyBTYWx0ZWRfXxbfgc4DPmJGd y4Cget5m0YN9VE4Q6NKO8hvEPVgeGGwsextseqGiNCKpHYd/rZ6chpaWt46BbswdUyh4Bt0vhls lbtM70Q8LG1kqrft9wbLG0BNcv0f8Qgwcg08f2yT9tbbvyKnZtDgutTJmE/lkKjWU/xA8JjlclC Q2IPnOoYMRiopph6qO/cUlu3oGeAATpXDeZDQDrT1wr1G3jSGiPtiFEHKhSmte5qDuzqM515Ljp 2Mqi6eXy7ckDV/ktb46XbAVV1H962BiQVAkf841bp+W+YhgM7Yf5jLzs00bam+2QhTArqspzDKI k99GqIA8+1kTKe8d//kIELB3O3veUTwZ2fKzaCet4zm9nLPge4pA5QgmJSE3tcfL7EoXF4o3rlh IvdXcxnGuVXW2dEVaKV5jU0raSUfWv16WC//gwg4aHOh9cyaqnjnXaleh3HrYFV6Rg+lSdjXVuO Pg//tfsde2wz/YK5trg== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDA0MyBTYWx0ZWRfX0RUW5ZX+GSW1 E9WrF8Bfr1scCvCRF9h7KscOcRwdq8RYYddSPbOSwWj0PjFLRfMe4j8hhyVzC+t3hF1xEwXkZjd 8G1KOi/NR2rhmBzj5tRFlbCoTMw1tPY= X-Authority-Analysis: v=2.4 cv=DcInbPtW c=1 sm=1 tr=0 ts=6aa0da34 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=kk5yy-eOBfP67cS8hnMA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-08_03,2026-09-08_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 suspectscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 spamscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609090043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788926588643158500 The 'sim' machine name is an alias for 'most up-to-date/capable hexagon-sim-style-memory-map machine', so with new v81 machines available, we'll update the alias. Signed-off-by: Brian Cain Reviewed-by: Marco Liebel --- hw/hexagon/hexagon_dsp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c index be17a32ee12..8824fe10a59 100644 --- a/hw/hexagon/hexagon_dsp.c +++ b/hw/hexagon/hexagon_dsp.c @@ -194,7 +194,6 @@ static void v68n_1024_init(ObjectClass *oc, const void = *data) MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "Hexagon V68N_1024"; - mc->alias =3D "sim"; mc->init =3D v68n_1024_config_init; init_mc(mc); mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V68; @@ -228,6 +227,7 @@ static void v81qa_1_init(ObjectClass *oc, const void *d= ata) MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "Hexagon V81QA_1"; + mc->alias =3D "sim"; mc->init =3D v81qa_1_config_init; init_mc(mc); mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V81; --=20 2.34.1 From nobody Sat Sep 26 20:01:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788926610; cv=none; d=zohomail.com; s=zohoarc; b=HGUkX0Qwlug4aaU9KW2Xa44Xxbhgw/zo1E/Tl8yjLd1XZUego+/mU4MCVqSXxImIHZr4UBkqb3myMZv9AS0/M7GmR8RrRX0rh1WoGJsfkrQpp5QcrMY/hr/MIws+nWmB57B576BI6JOQbhBx3gGxkdAbeLrrQ66L1DzsXxYgkco= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788926610; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8E4Ymq8STrxDCYX6ChWdHbC8ym/xjtdtnv8X50h5ink=; b=EAlgj2lLBc7v0KyOcmK0jFwfwP5N0W0S7JO30zoSly0U50BUmFRlgviWIprGK9yw8l88vZq8NmEqs2VUdhqujMk9EnBtQulTwjaI+xdAvctCsgTfvFhOxWynTtcvPVRr6CS6XrE0IJI/wEVHURSZKwa0TPWxyMTslxQS5/6938k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788926610609832.0996671465294; Tue, 8 Sep 2026 21:03:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x49VV-00070L-Qt; Wed, 09 Sep 2026 00:01:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x49VU-0006zx-1c for qemu-devel@nongnu.org; Wed, 09 Sep 2026 00:01:56 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x49VS-0003u6-Gf for qemu-devel@nongnu.org; Wed, 09 Sep 2026 00:01:55 -0400 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 688MgWbb045619 for ; Wed, 9 Sep 2026 04:01:53 GMT Received: from mail-oo1-f72.google.com (mail-oo1-f72.google.com [209.85.161.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gjqewhyvp-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 09 Sep 2026 04:01:53 +0000 (GMT) Received: by mail-oo1-f72.google.com with SMTP id 006d021491bc7-6b1b6df25efso5692112eaf.3 for ; Tue, 08 Sep 2026 21:01:53 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788926612607158500 Signed-off-by: Brian Cain Reviewed-by: Marco Liebel --- target/hexagon/reg_fields_def.h.inc | 9 ++++----- target/hexagon/genptr.c | 8 ++++++-- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/target/hexagon/reg_fields_def.h.inc b/target/hexagon/reg_field= s_def.h.inc index 29497fbcc4d..a6b17011d82 100644 --- a/target/hexagon/reg_fields_def.h.inc +++ b/target/hexagon/reg_fields_def.h.inc @@ -44,7 +44,7 @@ DEF_REG_FIELD(IPENDAD_IAD, 16, 16) DEF_REG_FIELD(IPENDAD_IPEND, 0, 16) =20 DEF_REG_FIELD(SCHEDCFG_EN, 8, 1) -DEF_REG_FIELD(SCHEDCFG_INTNO, 0, 4) +DEF_REG_FIELD(SCHEDCFG_INTNO, 0, 5) DEF_REG_FIELD(BESTWAIT_PRIO, 0, 9) =20 =20 @@ -109,14 +109,13 @@ DEF_REG_FIELD(SSR_SS, 30, 1) DEF_REG_FIELD(SSR_XE, 31, 1) =20 /* misc registers */ -DEF_REG_FIELD(IMASK_MASK, 0, 16) +DEF_REG_FIELD(IMASK_MASK, 0, 32) =20 DEF_REG_FIELD(STID_PRIO, 16, 8) DEF_REG_FIELD(STID_STID, 0, 8) =20 -/* MODECTL fields */ -DEF_REG_FIELD(MODECTL_E, 0, 8) -DEF_REG_FIELD(MODECTL_W, 16, 8) +DEF_REG_FIELD(MODECTL_E, 0, 16) +DEF_REG_FIELD(MODECTL_W, 16, 16) =20 DEF_REG_FIELD(CCR_L1ICP, 0, 2) DEF_REG_FIELD(CCR_L1DCP, 3, 2) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 9f53fcb6b95..4e9a9670d54 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -269,14 +269,18 @@ static const uint32_t sreg_immut_masks[NUM_SREGS] =3D= { [HEX_SREG_SSR] =3D 0x00008000, [HEX_SREG_CCR] =3D 0x10e0ff24, [HEX_SREG_HTID] =3D IMMUTABLE, - [HEX_SREG_IMASK] =3D 0xffff0000, [HEX_SREG_GEVB] =3D 0x000000ff, }; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788926602735158500 Signed-off-by: Brian Cain Reviewed-by: Marco Liebel --- target/hexagon/cpu.h | 2 +- target/hexagon/hex_regs.h | 42 +++++++++ target/hexagon/sys_macros.h | 8 +- target/hexagon/reg_fields_def.h.inc | 1 + hw/hexagon/hexagon_globalreg.c | 10 ++ target/hexagon/cpu.c | 11 ++- target/hexagon/cpu_helper.c | 15 ++- target/hexagon/hex_interrupts.c | 141 +++++++++++++++++++--------- target/hexagon/op_helper.c | 58 ++++++++---- target/hexagon/translate.c | 8 +- 10 files changed, 224 insertions(+), 72 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 719979d6c31..b1533680bd7 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -23,7 +23,7 @@ #ifndef CONFIG_USER_ONLY #define NUM_GREGS 32 #define GREG_WRITES_MAX 2 -#define NUM_SREGS 64 +#define NUM_SREGS 106 #define SREG_WRITES_MAX 2 #endif =20 diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h index 214b7b8fde8..1f6bf9f88a0 100644 --- a/target/hexagon/hex_regs.h +++ b/target/hexagon/hex_regs.h @@ -195,6 +195,48 @@ enum { HEX_SREG_S61 =3D 61, HEX_SREG_S62 =3D 62, HEX_SREG_S63 =3D 63, + HEX_SREG_COMMIT1T =3D 64, + HEX_SREG_COMMIT2T =3D 65, + HEX_SREG_COMMIT3T =3D 66, + HEX_SREG_COMMIT4T =3D 67, + HEX_SREG_COMMIT5T =3D 68, + HEX_SREG_COMMIT6T =3D 69, + HEX_SREG_PCYCLE1T =3D 70, + HEX_SREG_PCYCLE2T =3D 71, + HEX_SREG_PCYCLE3T =3D 72, + HEX_SREG_PCYCLE4T =3D 73, + HEX_SREG_PCYCLE5T =3D 74, + HEX_SREG_PCYCLE6T =3D 75, + HEX_SREG_STFINST =3D 76, + HEX_SREG_ISDBCMD =3D 77, + HEX_SREG_ISDBVER =3D 78, + HEX_SREG_BRKPTINFO =3D 79, + HEX_SREG_S80 =3D 80, + HEX_SREG_COMMIT7T =3D 81, + HEX_SREG_COMMIT8T =3D 82, + HEX_SREG_PCYCLE7T =3D 83, + HEX_SREG_PCYCLE8T =3D 84, + HEX_SREG_COMMIT9T =3D 85, + HEX_SREG_COMMIT10T =3D 86, + HEX_SREG_COMMIT11T =3D 87, + HEX_SREG_COMMIT12T =3D 88, + HEX_SREG_COMMIT13T =3D 89, + HEX_SREG_COMMIT14T =3D 90, + HEX_SREG_COMMIT15T =3D 91, + HEX_SREG_COMMIT16T =3D 92, + HEX_SREG_PCYCLE9T =3D 93, + HEX_SREG_PCYCLE10T =3D 94, + HEX_SREG_PCYCLE11T =3D 95, + HEX_SREG_PCYCLE12T =3D 96, + HEX_SREG_PCYCLE13T =3D 97, + HEX_SREG_PCYCLE14T =3D 98, + HEX_SREG_PCYCLE15T =3D 99, + HEX_SREG_PCYCLE16T =3D 100, + HEX_SREG_IPEND =3D 101, + HEX_SREG_IAD =3D 102, + HEX_SREG_ISDBST1 =3D 103, + HEX_SREG_ISDBST2 =3D 104, + HEX_SREG_BRKPTINFO1 =3D 105, }; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h index 2e13ba00c8a..a5b9b7f2592 100644 --- a/target/hexagon/sys_macros.h +++ b/target/hexagon/sys_macros.h @@ -184,10 +184,14 @@ =20 #define fIN_DEBUG_MODE(TNUM) ({ \ HexagonCPU *_cpu =3D env_archcpu(env); \ + bool _is_v81 =3D _cpu->cfg.hex_def->hex_version >=3D HEX_VER_V81; \ uint32_t _isdbst =3D _cpu->globalregs ? \ hexagon_globalreg_read(_cpu->globalregs, \ - HEX_SREG_ISDBST, env->threadId) : 0; \ - (GET_FIELD(ISDBST_DEBUGMODE, _isdbst) \ + _is_v81 ? HEX_SREG_ISDBST2 : HEX_SREG_ISDB= ST, \ + env->threadId) : 0; \ + ((_is_v81 ? \ + GET_FIELD(ISDBST2_DEBUGMODE, _isdbst) : \ + GET_FIELD(ISDBST_DEBUGMODE, _isdbst)) \ & (0x1 << (TNUM))) !=3D 0; }) =20 #define fIN_DEBUG_MODE_NO_ISDB(TNUM) false diff --git a/target/hexagon/reg_fields_def.h.inc b/target/hexagon/reg_field= s_def.h.inc index a6b17011d82..c06e14fe24a 100644 --- a/target/hexagon/reg_fields_def.h.inc +++ b/target/hexagon/reg_fields_def.h.inc @@ -152,3 +152,4 @@ DEF_REG_FIELD(ISDBST_PROCMODE, 3, 1) DEF_REG_FIELD(ISDBST_MBXINSTATUS, 2, 1) DEF_REG_FIELD(ISDBST_MBXOUTSTATUS, 1, 1) DEF_REG_FIELD(ISDBST_READY, 0, 1) +DEF_REG_FIELD(ISDBST2_DEBUGMODE, 16, 16) diff --git a/hw/hexagon/hexagon_globalreg.c b/hw/hexagon/hexagon_globalreg.c index 61621cf2b8f..616cddf3048 100644 --- a/hw/hexagon/hexagon_globalreg.c +++ b/hw/hexagon/hexagon_globalreg.c @@ -84,6 +84,11 @@ static const char *hex_sreg_names[] =3D { [HEX_SREG_S61] =3D "s61", [HEX_SREG_S62] =3D "s62", [HEX_SREG_S63] =3D "s63", + [HEX_SREG_IPEND] =3D "ipend", + [HEX_SREG_IAD] =3D "iad", + [HEX_SREG_ISDBST1] =3D "isdbst1", + [HEX_SREG_ISDBST2] =3D "isdbst2", + [HEX_SREG_BRKPTINFO1] =3D "brkptinfo1", }; =20 static const char *get_sreg_name(uint32_t reg) @@ -100,6 +105,8 @@ static const uint32_t global_sreg_immut_masks[NUM_SREGS= ] =3D { [HEX_SREG_MODECTL] =3D IMMUTABLE, [HEX_SREG_SYSCFG] =3D 0x80001c00, [HEX_SREG_IPENDAD] =3D IMMUTABLE, + [HEX_SREG_IPEND] =3D IMMUTABLE, + [HEX_SREG_IAD] =3D IMMUTABLE, [HEX_SREG_VID] =3D 0xfc00fc00, [HEX_SREG_VID1] =3D 0xfc00fc00, [HEX_SREG_BESTWAIT] =3D 0xfffffe00, @@ -109,6 +116,9 @@ static const uint32_t global_sreg_immut_masks[NUM_SREGS= ] =3D { [HEX_SREG_DIAG] =3D 0x00000000, [HEX_SREG_REV] =3D IMMUTABLE, [HEX_SREG_ISDBST] =3D IMMUTABLE, + [HEX_SREG_ISDBST1] =3D IMMUTABLE, + [HEX_SREG_ISDBST2] =3D IMMUTABLE, + [HEX_SREG_BRKPTINFO1] =3D IMMUTABLE, [HEX_SREG_ISDBCFG0] =3D 0xe0000000, [HEX_SREG_BRKPTPC0] =3D 0x00000003, [HEX_SREG_BRKPTCFG0] =3D 0xfc007000, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index fb0e3caa481..fad526ccfb5 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -103,7 +103,16 @@ const char * const hexagon_sregnames[] =3D { "pmucnt5", "pmucnt6", "pmucnt7", "pmucnt0", "pmucnt1", "pmucnt2", "pmucnt3", "pmuevtcfg", "pmustid0", "pmuevtcfg1", "pmustid1", "timerlo", "timerhi", "pmucfg", "s59", - "s60", "s61", "s62", "s63", + "s60", "s61", "s62", "s63", "commit1t", + "commit2t", "commit3t", "commit4t", "commit5t", "commit6t", + "pcycle1t", "pcycle2t", "pcycle3t", "pcycle4t", "pcycle5t", + "pcycle6t", "stfinst", "isdbcmd", "isdbver", "brkptinfo", + "s80", "commit7t", "commit8t", "pcycle7t", "pcycle8t", + "commit9t", "commit10t", "commit11t", "commit12t", "commit13t", + "commit14t", "commit15t", "commit16t", "pcycle9t", "pcycle10t", + "pcycle11t", "pcycle12t", "pcycle13t", "pcycle14t", "pcycle15t", + "pcycle16t", "ipend", "iad", "isdbst1", "isdbst2", + "brkptinfo1", }; =20 G_STATIC_ASSERT(NUM_SREGS =3D=3D ARRAY_SIZE(hexagon_sregnames)); diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index 9ce260d7448..eea5f60b46c 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -333,10 +333,17 @@ int get_exe_mode(const CPUHexagonState *env) E_bit =3D thread_enabled_mask & (0x1 << env->threadId); thread_wait_mask =3D GET_FIELD(MODECTL_W, modectl); W_bit =3D thread_wait_mask & (0x1 << env->threadId); - isdbst =3D cpu->globalregs ? - hexagon_globalreg_read(cpu->globalregs, HEX_SREG_ISDBST, - env->threadId) : 0; - debugmode =3D GET_FIELD(ISDBST_DEBUGMODE, isdbst); + if (cpu->cfg.hex_def->hex_version >=3D HEX_VER_V81) { + isdbst =3D cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_ISDBST2, + env->threadId) : 0; + debugmode =3D GET_FIELD(ISDBST2_DEBUGMODE, isdbst); + } else { + isdbst =3D cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_ISDBST, + env->threadId) : 0; + debugmode =3D GET_FIELD(ISDBST_DEBUGMODE, isdbst); + } D_bit =3D debugmode & (0x1 << env->threadId); =20 if (!D_bit && !W_bit && !E_bit) { diff --git a/target/hexagon/hex_interrupts.c b/target/hexagon/hex_interrupt= s.c index 2b2834af95f..0b714b73831 100644 --- a/target/hexagon/hex_interrupts.c +++ b/target/hexagon/hex_interrupts.c @@ -21,7 +21,7 @@ static bool hex_is_qualified_for_int(CPUHexagonState *env= , int int_num); =20 static bool get_syscfg_gie(CPUHexagonState *env) { - HexagonCPU *cpu =3D env_archcpu(env); + const HexagonCPU *cpu =3D env_archcpu(env); uint32_t syscfg =3D hexagon_globalreg_read(cpu->globalregs, HEX_SREG_SYSCFG, env->threadId); @@ -52,85 +52,138 @@ static void set_ssr_ex_cause(CPUHexagonState *env, int= ex, uint32_t cause) hexagon_modify_ssr(env, new, old); } =20 +static bool has_split_ipend_iad(const CPUHexagonState *env) +{ + const HexagonCPU *cpu =3D env_archcpu(env); + + return cpu->cfg.hex_def->hex_version >=3D HEX_VER_V81; +} + +static uint32_t get_iad(CPUHexagonState *env) +{ + HexagonCPU *cpu =3D env_archcpu(env); + + if (has_split_ipend_iad(env)) { + return hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IAD, + env->threadId); + } + return GET_FIELD(IPENDAD_IAD, + hexagon_globalreg_read(cpu->globalregs, + HEX_SREG_IPENDAD, + env->threadId)); +} + +static void set_iad(CPUHexagonState *env, uint32_t iad) +{ + HexagonCPU *cpu =3D env_archcpu(env); + + if (has_split_ipend_iad(env)) { + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IAD, iad, + env->threadId); + } else { + uint32_t ipendad =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId); + + fSET_FIELD(ipendad, IPENDAD_IAD, iad); + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, + ipendad, env->threadId); + } +} + static bool get_iad_bit(CPUHexagonState *env, int int_num) { - HexagonCPU *cpu =3D env_archcpu(env); - uint32_t ipendad =3D - hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, - env->threadId); - uint32_t iad =3D GET_FIELD(IPENDAD_IAD, ipendad); + uint32_t iad =3D get_iad(env); + return extract32(iad, int_num, 1); } =20 static void set_iad_bit(CPUHexagonState *env, int int_num, int val) { - HexagonCPU *cpu =3D env_archcpu(env); - uint32_t ipendad =3D - hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, - env->threadId); - uint32_t iad =3D GET_FIELD(IPENDAD_IAD, ipendad); + uint32_t iad =3D get_iad(env); + iad =3D deposit32(iad, int_num, 1, val); - fSET_FIELD(ipendad, IPENDAD_IAD, iad); - hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, - ipendad, env->threadId); + set_iad(env, iad); } =20 static uint32_t get_ipend(CPUHexagonState *env) { HexagonCPU *cpu =3D env_archcpu(env); - uint32_t ipendad =3D - hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, - env->threadId); - return GET_FIELD(IPENDAD_IPEND, ipendad); + + if (has_split_ipend_iad(env)) { + return hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPEND, + env->threadId); + } + return GET_FIELD(IPENDAD_IPEND, + hexagon_globalreg_read(cpu->globalregs, + HEX_SREG_IPENDAD, + env->threadId)); } =20 static inline bool get_ipend_bit(CPUHexagonState *env, int int_num) { - HexagonCPU *cpu =3D env_archcpu(env); - uint32_t ipendad =3D - hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, - env->threadId); - uint32_t ipend =3D GET_FIELD(IPENDAD_IPEND, ipendad); + uint32_t ipend =3D get_ipend(env); return extract32(ipend, int_num, 1); } =20 static void clear_ipend(CPUHexagonState *env, uint32_t mask) { HexagonCPU *cpu =3D env_archcpu(env); - uint32_t ipendad =3D - hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, - env->threadId); - uint32_t ipend =3D GET_FIELD(IPENDAD_IPEND, ipendad); + uint32_t ipend =3D get_ipend(env); + ipend &=3D ~mask; - fSET_FIELD(ipendad, IPENDAD_IPEND, ipend); - hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, - ipendad, env->threadId); + if (has_split_ipend_iad(env)) { + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPEND, ipend, + env->threadId); + } else { + uint32_t ipendad =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId); + + fSET_FIELD(ipendad, IPENDAD_IPEND, ipend); + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, + ipendad, env->threadId); + } } =20 static void set_ipend(CPUHexagonState *env, uint32_t mask) { HexagonCPU *cpu =3D env_archcpu(env); - uint32_t ipendad =3D - hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, - env->threadId); - uint32_t ipend =3D GET_FIELD(IPENDAD_IPEND, ipendad); + uint32_t ipend =3D get_ipend(env); + ipend |=3D mask; - fSET_FIELD(ipendad, IPENDAD_IPEND, ipend); - hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, - ipendad, env->threadId); + if (has_split_ipend_iad(env)) { + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPEND, ipend, + env->threadId); + } else { + uint32_t ipendad =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId); + + fSET_FIELD(ipendad, IPENDAD_IPEND, ipend); + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, + ipendad, env->threadId); + } } =20 static void set_ipend_bit(CPUHexagonState *env, int int_num, int val) { HexagonCPU *cpu =3D env_archcpu(env); - uint32_t ipendad =3D - hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, - env->threadId); - uint32_t ipend =3D GET_FIELD(IPENDAD_IPEND, ipendad); + uint32_t ipend =3D get_ipend(env); + ipend =3D deposit32(ipend, int_num, 1, val); - fSET_FIELD(ipendad, IPENDAD_IPEND, ipend); - hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, - ipendad, env->threadId); + if (has_split_ipend_iad(env)) { + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPEND, ipend, + env->threadId); + } else { + uint32_t ipendad =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId); + + fSET_FIELD(ipendad, IPENDAD_IPEND, ipend); + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, + ipendad, env->threadId); + } } =20 static bool get_imask_bit(CPUHexagonState *env, int int_num) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 7ad99ced7ab..0d08ac77361 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1600,38 +1600,53 @@ void HELPER(raise_stack_overflow)(CPUHexagonState *= env, uint32_t slot, =20 void HELPER(ciad)(CPUHexagonState *env, uint32_t mask) { - uint32_t ipendad; uint32_t iad; HexagonCPU *cpu; =20 BQL_LOCK_GUARD(); cpu =3D env_archcpu(env); - ipendad =3D hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, - env->threadId); - iad =3D fGET_FIELD(ipendad, IPENDAD_IAD); - fSET_FIELD(ipendad, IPENDAD_IAD, iad & ~(mask)); - hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, - ipendad, env->threadId); + if (cpu->cfg.hex_def->hex_version >=3D HEX_VER_V81) { + iad =3D hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IAD, + env->threadId) & ~mask; + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IAD, iad, + env->threadId); + } else { + uint32_t ipendad =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId); + + fSET_FIELD(ipendad, IPENDAD_IAD, + fGET_FIELD(ipendad, IPENDAD_IAD) & ~mask); + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, + ipendad, env->threadId); + } l2vic_clear_interrupt(cpu->l2vic); hex_interrupt_update(env); } =20 void HELPER(siad)(CPUHexagonState *env, uint32_t mask) { - uint32_t ipendad; uint32_t iad; HexagonCPU *cpu; =20 BQL_LOCK_GUARD(); cpu =3D env_archcpu(env); - ipendad =3D cpu->globalregs ? - hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, - env->threadId) : 0; - iad =3D fGET_FIELD(ipendad, IPENDAD_IAD); - fSET_FIELD(ipendad, IPENDAD_IAD, iad | mask); if (cpu->globalregs) { - hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, - ipendad, env->threadId); + if (cpu->cfg.hex_def->hex_version >=3D HEX_VER_V81) { + iad =3D hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IAD, + env->threadId) | mask; + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IAD, iad, + env->threadId); + } else { + uint32_t ipendad =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId); + + fSET_FIELD(ipendad, IPENDAD_IAD, + fGET_FIELD(ipendad, IPENDAD_IAD) | mask); + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, + ipendad, env->threadId); + } } hex_interrupt_update(env); } @@ -1657,7 +1672,7 @@ void HELPER(iassignw)(CPUHexagonState *env, uint32_t = src) CPU_FOREACH(cpu) { CPUHexagonState *thread_env =3D &(HEXAGON_CPU(cpu)->env); uint32_t imask =3D thread_env->t_sreg[HEX_SREG_IMASK]; - uint32_t intbitpos =3D (src >> 16) & 0xF; + uint32_t intbitpos =3D extract32(src, 16, 5); uint32_t val =3D (src >> thread_env->threadId) & 0x1; imask =3D deposit32(imask, intbitpos, 1, val); thread_env->t_sreg[HEX_SREG_IMASK] =3D imask; @@ -1677,7 +1692,7 @@ uint32_t HELPER(iassignr)(CPUHexagonState *env, uint3= 2_t src) =20 BQL_LOCK_GUARD(); /* src fields are in same position as modectl, but mean different thin= gs */ - intbitpos =3D GET_FIELD(MODECTL_W, src); + intbitpos =3D extract32(src, 16, 5); dest_reg =3D 0; CPU_FOREACH(cpu) { CPUHexagonState *thread_env =3D &(HEXAGON_CPU(cpu)->env); @@ -1896,10 +1911,17 @@ static inline QEMU_ALWAYS_INLINE uint32_t sreg_read= (CPUHexagonState *env, } return env->t_sreg[HEX_SREG_BADVA0]; } + cpu =3D env_archcpu(env); + if (reg =3D=3D HEX_SREG_IPENDAD && + cpu->cfg.hex_def->hex_version >=3D HEX_VER_V81) { + return (hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPEND, + env->threadId) & 0xffff) | + ((hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IAD, + env->threadId) & 0xffff) << 16); + } if (reg < HEX_SREG_GLB_START) { return env->t_sreg[reg]; } - cpu =3D env_archcpu(env); return cpu->globalregs ? hexagon_globalreg_read(cpu->globalregs, reg, env->threadId) : 0; } diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 5d3d67e5d3e..fd1de87405c 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -319,6 +319,8 @@ static bool sreg_write_ends_tb(int reg_num) reg_num =3D=3D HEX_SREG_STID || reg_num =3D=3D HEX_SREG_IMASK || reg_num =3D=3D HEX_SREG_IPENDAD || + reg_num =3D=3D HEX_SREG_IPEND || + reg_num =3D=3D HEX_SREG_IAD || reg_num =3D=3D HEX_SREG_BESTWAIT || reg_num =3D=3D HEX_SREG_SCHEDCFG; } @@ -830,8 +832,10 @@ static void gen_sreg_writes(DisasContext *ctx) gen_helper_modify_ssr(tcg_env, ctx->t_sreg_new_value[reg_num], old_reg); } else if ((reg_num =3D=3D HEX_SREG_STID) || - (reg_num =3D=3D HEX_SREG_IMASK) || - (reg_num =3D=3D HEX_SREG_IPENDAD)) { + (reg_num =3D=3D HEX_SREG_IMASK) || + (reg_num =3D=3D HEX_SREG_IPENDAD) || + (reg_num =3D=3D HEX_SREG_IPEND) || + (reg_num =3D=3D HEX_SREG_IAD)) { if (ctx->need_commit && reg_num < HEX_SREG_GLB_START) { tcg_gen_mov_tl(hex_t_sreg[reg_num], ctx->t_sreg_new_value[reg_num]); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788926557073158500 Signed-off-by: Brian Cain --- tests/functional/hexagon/test_arch_tests.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/tests/functional/hexagon/test_arch_tests.py b/tests/functional= /hexagon/test_arch_tests.py index 5d7ce487436..40f76e25ae6 100755 --- a/tests/functional/hexagon/test_arch_tests.py +++ b/tests/functional/hexagon/test_arch_tests.py @@ -24,6 +24,11 @@ class ArchTestsUart(QemuSystemTest): "download/v0.2.14/arch_tests_uart.tar.gz", "ce93cb90b9d757c1946dfe8fe6abcec8292b08a66546ac51b2dd48650b05fa91", ) + ASSET_SEMIHOSTING_TARBALL =3D Asset( + "https://github.com/qualcomm/qemu-hexagon-testing/releases/" + "download/v0.2.9/arch_tests_semihosting.tar.gz", + "f0ce731dc8dc2b861792b8bd60808cb714fd1922c0dc793af65090c0ba525bb0", + ) =20 def run_uart_test(self, test_name: str, machine: str =3D "virt") -> None: @@ -40,6 +45,18 @@ def run_uart_test(self, test_name: str, self.vm.launch() wait_for_console_pattern(self, "PASS") =20 + def run_semihosting_test(self, test_name: str, + machine: str =3D "V81QA_1") -> None: + self.set_machine(machine) + self.archive_extract(self.ASSET_SEMIHOSTING_TARBALL) + target_bin =3D self.scratch_file('arch_tests_semihosting_package', + 'bin', test_name) + self.vm.set_console(semihosting=3DTrue) + self.set_vm_arg("-display", "none") + self.set_vm_arg("-kernel", target_bin) + self.vm.launch() + wait_for_console_pattern(self, "PASS") + def test_exceptions(self) -> None: """Tests exception delivery for trap instructions, privilege violations, and verifies SSR cause codes and ELR values. @@ -78,6 +95,10 @@ def test_sys_regs(self) -> None: """Tests system registers.""" self.run_uart_test("test_sys_regs") =20 + def test_sys_regs_v81(self) -> None: + """Tests V81-specific system register masks.""" + self.run_semihosting_test("test_sys_regs") + def test_threads(self) -> None: """Tests hardware thread management: start/stop, MODECTL state, per-thread HTID, shared memory, wait/resume, STID priority, and --=20 2.34.1