From nobody Sat Sep 26 20:02:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788852901262513.3022805148468; Tue, 8 Sep 2026 00:35:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3qLy-0002CH-4n; Tue, 08 Sep 2026 03:34:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3qLv-0002Aj-5z for qemu-devel@nongnu.org; Tue, 08 Sep 2026 03:34:47 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3qLr-000073-AG for qemu-devel@nongnu.org; Tue, 08 Sep 2026 03:34:46 -0400 Received: from loongson.cn (unknown [10.40.46.54]) by gateway (Coremail) with SMTP id _____8DxztKKup9qrrcJAA--.27763S3; Tue, 08 Sep 2026 15:34:34 +0800 (CST) Received: from fedora.loongson.cn (unknown [10.40.46.54]) by front1 (Coremail) with SMTP id qMiowJDxDc+Eup9qSQ0dAA--.29522S3; Tue, 08 Sep 2026 15:34:33 +0800 (CST) From: Bibo Mao To: qemu-devel@nongnu.org Cc: Xianglai Li , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 1/5] target/loongarch: clear the registers when cpu is reset Date: Tue, 8 Sep 2026 15:35:44 +0800 Message-ID: <20260908073548.3249551-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260908073548.3249551-1-maobibo@loongson.cn> References: <20260908073548.3249551-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxDc+Eup9qSQ0dAA--.29522S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBj93XoW3Xr15Zr4fWF4UGFyfuw4Dtrc_yoWxAr1Upr 43KF9Fkw48KF43Crn5X398AFn8Zw1xGw1xt3sxKr1Fkayvgr93ZFWvqr1SkFWDZry5ur4x XrnrJrW2gF47Z3XCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE 14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU1wL05UUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1788852905870154100 From: Xianglai Li Use virt-manager to start a virtual machine, and then use the following command to manually trigger the crash of the virtual machine: echo c > /proc/sysrq-trigger After the VM is abnormal, the ESTAT register has a certain probability of remaining interrupted. Then the VM is forced to restart and the VM is suspended in the interrupt handling function during startup. In order to clear the remaining interrupt information in the ESTAT register, we performed this operation during the reset process, while also checking and optimizing the status of other CSR registers. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Xianglai Li Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 54 +++++++----------------------------------- target/loongarch/cpu.h | 34 ++++++++++++++++---------- 2 files changed, 29 insertions(+), 59 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 84a130956d..18d73ebc1b 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -623,6 +623,13 @@ static void loongarch_cpu_reset_hold(Object *obj, Rese= tType type) lacc->parent_phases.hold(obj, type); } =20 + /* + * Workaround for edk2-stable202408, CSR PGD register is set only if + * its value is equal to zero for boot cpu, it causes reboot issue. + */ + memset(env, 0, offsetof(CPULoongArchState, end_reset_fields)); + memset(sys, 0, offsetof(CPUSysState, end_reset_fields)); + #ifdef CONFIG_TCG env->fcsr0_mask =3D FCSR0_M1 | FCSR0_M2 | FCSR0_M3; =20 @@ -637,47 +644,11 @@ static void loongarch_cpu_reset_hold(Object *obj, Res= etType type) R_TLBENTRY_32_PPN_MASK; } #endif - env->fcsr0 =3D 0x0; =20 - int n; - /* Set csr registers value after reset, see the manual 6.4. */ - sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, PLV, 0); - sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, IE, 0); sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, DA, 1); - sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, PG, 0); - sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, DATF, 0); - sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, DATM, 0); - - sys->CSR_EUEN =3D FIELD_DP64(sys->CSR_EUEN, CSR_EUEN, FPE, 0); - sys->CSR_EUEN =3D FIELD_DP64(sys->CSR_EUEN, CSR_EUEN, SXE, 0); - sys->CSR_EUEN =3D FIELD_DP64(sys->CSR_EUEN, CSR_EUEN, ASXE, 0); - sys->CSR_EUEN =3D FIELD_DP64(sys->CSR_EUEN, CSR_EUEN, BTE, 0); - - sys->CSR_MISC =3D 0; - - sys->CSR_ECFG =3D FIELD_DP64(sys->CSR_ECFG, CSR_ECFG, VS, 0); - sys->CSR_ECFG =3D FIELD_DP64(sys->CSR_ECFG, CSR_ECFG, LIE, 0); - - sys->CSR_ESTAT =3D sys->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); - sys->CSR_RVACFG =3D FIELD_DP64(sys->CSR_RVACFG, CSR_RVACFG, RBITS, 0); sys->CSR_CPUID =3D cs->cpu_index; - sys->CSR_TCFG =3D FIELD_DP64(sys->CSR_TCFG, CSR_TCFG, EN, 0); - sys->CSR_LLBCTL =3D FIELD_DP64(sys->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); - sys->CSR_TLBRERA =3D FIELD_DP64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR,= 0); - sys->CSR_MERRCTL =3D FIELD_DP64(sys->CSR_MERRCTL, CSR_MERRCTL, ISMERR,= 0); sys->CSR_TID =3D cs->cpu_index; - /* - * Workaround for edk2-stable202408, CSR PGD register is set only if - * its value is equal to zero for boot cpu, it causes reboot issue. - * - * Here clear CSR registers relative with TLB. - */ - sys->CSR_PGDH =3D 0; - sys->CSR_PGDL =3D 0; - sys->CSR_PWCH =3D 0; - sys->CSR_EENTRY =3D 0; - sys->CSR_TLBRENTRY =3D 0; - sys->CSR_MERRENTRY =3D 0; + /* set CSR_PWCL.PTBASE and CSR_STLBPS.PS bits from CSR_PRCFG2 */ if (sys->CSR_PRCFG2 =3D=3D 0) { sys->CSR_PRCFG2 =3D 0x3fffff000; @@ -685,18 +656,9 @@ static void loongarch_cpu_reset_hold(Object *obj, Rese= tType type) tlb_ps =3D ctz32(sys->CSR_PRCFG2); sys->CSR_STLBPS =3D FIELD_DP64(sys->CSR_STLBPS, CSR_STLBPS, PS, tlb_ps= ); sys->CSR_PWCL =3D FIELD_DP64(sys->CSR_PWCL, CSR_PWCL, PTBASE, tlb_ps); - for (n =3D 0; n < 4; n++) { - sys->CSR_DMW[n] =3D FIELD_DP64(sys->CSR_DMW[n], CSR_DMW, PLV0, 0); - sys->CSR_DMW[n] =3D FIELD_DP64(sys->CSR_DMW[n], CSR_DMW, PLV1, 0); - sys->CSR_DMW[n] =3D FIELD_DP64(sys->CSR_DMW[n], CSR_DMW, PLV2, 0); - sys->CSR_DMW[n] =3D FIELD_DP64(sys->CSR_DMW[n], CSR_DMW, PLV3, 0); - } =20 #ifndef CONFIG_USER_ONLY env->pc =3D 0x1c000000; -#ifdef CONFIG_TCG - memset(env->tlb, 0, sizeof(env->tlb)); -#endif if (kvm_enabled()) { kvm_arch_reset_vcpu(cs); } diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 97db3b453f..d83dcef6f8 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -334,7 +334,6 @@ typedef struct CPUSysState { uint64_t CSR_TLBEHI; uint64_t CSR_TLBELO0; uint64_t CSR_TLBELO1; - uint64_t CSR_ASID; uint64_t CSR_PGDL; uint64_t CSR_PGDH; uint64_t CSR_PGD; @@ -343,9 +342,6 @@ typedef struct CPUSysState { uint64_t CSR_STLBPS; uint64_t CSR_RVACFG; uint64_t CSR_CPUID; - uint64_t CSR_PRCFG1; - uint64_t CSR_PRCFG2; - uint64_t CSR_PRCFG3; uint64_t CSR_SAVE[16]; uint64_t CSR_TID; uint64_t CSR_TCFG; @@ -380,6 +376,14 @@ typedef struct CPUSysState { uint64_t CSR_MSGIS[N_MSGIS]; uint64_t CSR_MSGIR; uint64_t CSR_MSGIE; + + /* Fields up to this point are cleared by a CPU reset */ + struct {} end_reset_fields; + + uint64_t CSR_ASID; + uint64_t CSR_PRCFG1; + uint64_t CSR_PRCFG2; + uint64_t CSR_PRCFG3; } CPUSysState; =20 typedef struct CPUArchState { @@ -391,16 +395,9 @@ typedef struct CPUArchState { uint32_t fcsr0; lbt_t lbt; =20 - uint32_t cpucfg[21]; - uint32_t pv_features; - uint64_t vendor_id; - uint64_t cpu_id; - CPUSysState sys_states[1]; - struct { uint64_t guest_addr; } stealtime; - uint32_t perf_event_num; =20 #ifdef CONFIG_TCG float_status fp_status; @@ -410,12 +407,23 @@ typedef struct CPUArchState { uint64_t llval_high; /* For 128-bit atomic SC.Q */ uint64_t llbit_scq; /* Potential LL.D+LD.D+SC.Q sequence in effect */ uint64_t hw_pte_mask; /* Mask of architecturally-defined (hardware) PT= E bits. */ -#endif + #ifndef CONFIG_USER_ONLY -#ifdef CONFIG_TCG LoongArchTLB tlb[LOONGARCH_TLB_MAX]; +#endif #endif =20 + /* Fields up to this point are cleared by a CPU reset */ + struct {} end_reset_fields; + + CPUSysState sys_states[1]; + uint32_t cpucfg[21]; + uint32_t pv_features; + uint64_t vendor_id; + uint64_t cpu_id; + uint32_t perf_event_num; + +#ifndef CONFIG_USER_ONLY AddressSpace *address_space_iocsr; uint32_t mp_state; #endif --=20 2.54.0 From nobody Sat Sep 26 20:02:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178885294738957.660950574201934; Tue, 8 Sep 2026 00:35:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3qLx-0002CE-53; Tue, 08 Sep 2026 03:34:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3qLv-0002Af-3K for qemu-devel@nongnu.org; Tue, 08 Sep 2026 03:34:47 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3qLr-00006o-Mi for qemu-devel@nongnu.org; Tue, 08 Sep 2026 03:34:46 -0400 Received: from loongson.cn (unknown [10.40.46.54]) by gateway (Coremail) with SMTP id _____8CxKvCLup9qsrcJAA--.27845S3; Tue, 08 Sep 2026 15:34:35 +0800 (CST) Received: from fedora.loongson.cn (unknown [10.40.46.54]) by front1 (Coremail) with SMTP id qMiowJDxDc+Eup9qSQ0dAA--.29522S4; Tue, 08 Sep 2026 15:34:34 +0800 (CST) From: Bibo Mao To: qemu-devel@nongnu.org Cc: Song Gao <17746591750@163.com> Subject: [PULL 2/5] hw/intc/loongarch_dintc: Add loongarch_dintc_cpu_by_arch_id() function Date: Tue, 8 Sep 2026 15:35:45 +0800 Message-ID: <20260908073548.3249551-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260908073548.3249551-1-maobibo@loongson.cn> References: <20260908073548.3249551-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxDc+Eup9qSQ0dAA--.29522S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBj93XoWxAFW5JFyDKryxGFyfKw4xKrX_yoW5AF1Dpr Wxurn0gr1UAanrX39xJa4rZr4fCrn3u3W2q3WakF92kF4kXr15Xr48GryDXF9Fka4UWr1j qwn7J3WUWF13JFbCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_JF0_Jw1lYx0Ex4A2jsIE 14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU82g43UUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1788852949208154100 Content-Type: text/plain; charset="utf-8" Similar with IPI, add function loongarch_dintc_cpu_by_arch_id() for dintc driver. It searches dintc device from physical CPUID, also it used binary search method, rather than one by one with common API cpu_by_arch_id(). And use this newly added API in loongarch_dintc_get_cpu() and loongarch_dintc_mem_write(). Signed-off-by: Bibo Mao Reviewed-by: Song Gao <17746591750@163.com> --- hw/intc/loongarch_dintc.c | 49 +++++++++++++++++++++++---------------- 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/hw/intc/loongarch_dintc.c b/hw/intc/loongarch_dintc.c index 94d418261c..c01f1fe07e 100644 --- a/hw/intc/loongarch_dintc.c +++ b/hw/intc/loongarch_dintc.c @@ -26,6 +26,25 @@ FIELD(MSG_ADDR, IRQ_NUM, 4, 8) FIELD(MSG_ADDR, CPU_NUM, 12, 8) FIELD(MSG_ADDR, FIX, 28, 12) =20 +static int loongarch_dintc_cmp(const void *a, const void *b) +{ + DINTCCore *dintc_a =3D (DINTCCore *)a; + DINTCCore *dintc_b =3D (DINTCCore *)b; + + return dintc_a->arch_id - dintc_b->arch_id; +} + +static DINTCCore *loongarch_dintc_cpu_by_arch_id(LoongArchDINTCState *s, + int64_t arch_id) +{ + DINTCCore dintc, *found; + + dintc.arch_id =3D arch_id; + found =3D bsearch(&dintc, s->cpu, s->num_cpu, sizeof(DINTCCore), + loongarch_dintc_cmp); + return found; +} + static uint64_t loongarch_dintc_mem_read(void *opaque, hwaddr addr, unsigned size) { @@ -49,23 +68,20 @@ static void loongarch_dintc_mem_write(void *opaque, hwa= ddr addr, { int irq_num, cpu_num =3D 0; LoongArchDINTCState *s =3D LOONGARCH_DINTC(opaque); - uint64_t msg_addr =3D addr + VIRT_DINTC_BASE; + uint64_t msg_addr =3D addr + VIRT_DINTC_BASE, arch_id; + DINTCCore *core; CPUState *cs; =20 - cpu_num =3D FIELD_EX64(msg_addr, MSG_ADDR, CPU_NUM); - - /* Validate cpu_num against the configured number of CPUs */ - if (cpu_num >=3D s->num_cpu) { - qemu_log_mask(LOG_GUEST_ERROR, - "loongarch-dintc: invalid cpu number%d\n", cpu_num); - return; - } - cs =3D cpu_by_arch_id(cpu_num); - if (!cs) { + arch_id =3D FIELD_EX64(msg_addr, MSG_ADDR, CPU_NUM); + core =3D loongarch_dintc_cpu_by_arch_id(s, arch_id); + if (!core || !core->cpu) { qemu_log_mask(LOG_GUEST_ERROR, - "loongarch-dintc: no CPU for arch_id %d\n", cpu_num); + "loongarch-dintc: no CPU for arch_id %"PRId64"\n", + arch_id); return; } + cpu_num =3D core - s->cpu; + cs =3D core->cpu; irq_num =3D FIELD_EX64(msg_addr, MSG_ADDR, IRQ_NUM); =20 if (kvm_irqchip_in_kernel()) { @@ -148,15 +164,8 @@ static DINTCCore *loongarch_dintc_get_cpu(LoongArchDIN= TCState *s, { CPUClass *k =3D CPU_GET_CLASS(dev); uint64_t arch_id =3D k->get_arch_id(CPU(dev)); - int i; - - for (i =3D 0; i < s->num_cpu; i++) { - if (s->cpu[i].arch_id =3D=3D arch_id) { - return &s->cpu[i]; - } - } =20 - return NULL; + return loongarch_dintc_cpu_by_arch_id(s, arch_id); } =20 static void loongarch_dintc_cpu_plug(HotplugHandler *hotplug_dev, --=20 2.54.0 From nobody Sat Sep 26 20:02:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788852926826473.4632732022949; Tue, 8 Sep 2026 00:35:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3qLw-0002Ay-8F; Tue, 08 Sep 2026 03:34:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3qLt-0002A7-Ee for qemu-devel@nongnu.org; Tue, 08 Sep 2026 03:34:45 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3qLr-00006n-9h for qemu-devel@nongnu.org; Tue, 08 Sep 2026 03:34:45 -0400 Received: from loongson.cn (unknown [10.40.46.54]) by gateway (Coremail) with SMTP id _____8Bx69GLup9qs7cJAA--.27945S3; Tue, 08 Sep 2026 15:34:35 +0800 (CST) Received: from fedora.loongson.cn (unknown [10.40.46.54]) by front1 (Coremail) with SMTP id qMiowJDxDc+Eup9qSQ0dAA--.29522S5; Tue, 08 Sep 2026 15:34:35 +0800 (CST) From: Bibo Mao To: qemu-devel@nongnu.org Cc: Xianglai Li Subject: [PULL 3/5] hw/intc/loongarch_ipi: Add ipi interrupt status display Date: Tue, 8 Sep 2026 15:35:46 +0800 Message-ID: <20260908073548.3249551-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260908073548.3249551-1-maobibo@loongson.cn> References: <20260908073548.3249551-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxDc+Eup9qSQ0dAA--.29522S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBj93XoWxWF13Zw47Kry8Xr15ArWDGFX_yoW5WrWkpF W3uF4Ykr48AFsrGrZxAasIqFn8Gw1xuFy7uFs7C348AFWDJrn0q3yIyr9xXFyUC3y8GF1Y qw4fJa4q9a1UCrcCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_JF0_Jw1lYx0Ex4A2jsIE 14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU8wNVDUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1788852930473158500 Content-Type: text/plain; charset="utf-8" When irqchip in kernel is enabled, the register status of ipi irqchip is in KVM kernel. Here add interrupt status display in user side in order to debug irqchip driver. Signed-off-by: Bibo Mao Reviewed-by: Xianglai Li --- hw/intc/loongarch_ipi.c | 42 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 5d8b8c96df..28d816e3f5 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -9,6 +9,7 @@ #include "qemu/error-report.h" #include "hw/core/boards.h" #include "qapi/error.h" +#include "hw/intc/intc.h" #include "hw/intc/loongarch_ipi.h" #include "hw/core/qdev-properties.h" #include "system/kvm.h" @@ -193,8 +194,47 @@ static int loongarch_ipi_post_load(void *opaque, int v= ersion_id) return 0; } =20 +static void loongarch_ipi_print_info(InterruptStatsProvider *obj, GString = *buf) +{ + LoongsonIPICommonState *lics =3D LOONGSON_IPI_COMMON(obj); + int i, j; + IPICore *core; + uint64_t mbx; + unsigned long pos; + + loongarch_ipi_pre_save(lics); + + g_string_append_printf(buf, "%s:\n", object_get_typename(OBJECT(obj))); + for (i =3D 0; i < lics->num_cpu; i++) { + core =3D lics->cpu + i; + /* IPI with targeted CPU available however not present */ + if (!core->cpu) { + continue; + } + + g_string_append_printf(buf, " CPU %-3u status=3D0x%x en=3D0x%x\n", + i, core->status, core->en); + + pos =3D find_first_bit((unsigned long *)core->buf, IPI_MBX_NUM * 6= 4); + /* All zero in mailbox */ + if (pos =3D=3D (IPI_MBX_NUM * 64)) { + continue; + } + + for (j =3D 0; j < IPI_MBX_NUM; j++) { + mbx =3D *(uint64_t *)&core->buf[2 * j]; + if (mbx) { + g_string_append_printf(buf, " MBX[%-1u] 0x%016"PRIx64, j,= mbx); + } + } + + g_string_append_c(buf, '\n'); + } +} + static void loongarch_ipi_class_init(ObjectClass *klass, const void *data) { + InterruptStatsProviderClass *ic =3D INTERRUPT_STATS_PROVIDER_CLASS(kla= ss); LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_CLASS(klass); HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); LoongarchIPIClass *lic =3D LOONGARCH_IPI_CLASS(klass); @@ -211,6 +251,7 @@ static void loongarch_ipi_class_init(ObjectClass *klass= , const void *data) hc->unplug =3D loongarch_ipi_cpu_unplug; licc->pre_save =3D loongarch_ipi_pre_save; licc->post_load =3D loongarch_ipi_post_load; + ic->print_info =3D loongarch_ipi_print_info; } =20 static const TypeInfo loongarch_ipi_types[] =3D { @@ -222,6 +263,7 @@ static const TypeInfo loongarch_ipi_types[] =3D { .class_init =3D loongarch_ipi_class_init, .interfaces =3D (const InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, + { TYPE_INTERRUPT_STATS_PROVIDER }, { } }, } --=20 2.54.0 From nobody Sat Sep 26 20:02:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178885293368123.702234354121515; Tue, 8 Sep 2026 00:35:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3qLw-0002Bk-M4; Tue, 08 Sep 2026 03:34:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3qLu-0002AG-Pe for qemu-devel@nongnu.org; Tue, 08 Sep 2026 03:34:46 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3qLr-00006t-Hb for qemu-devel@nongnu.org; Tue, 08 Sep 2026 03:34:46 -0400 Received: from loongson.cn (unknown [10.40.46.54]) by gateway (Coremail) with SMTP id _____8DxpvCOup9qtLcJAA--.28125S3; Tue, 08 Sep 2026 15:34:38 +0800 (CST) Received: from fedora.loongson.cn (unknown [10.40.46.54]) by front1 (Coremail) with SMTP id qMiowJBxrM6Nup9qVA0dAA--.29211S2; Tue, 08 Sep 2026 15:34:37 +0800 (CST) From: Bibo Mao To: qemu-devel@nongnu.org Cc: Xianglai Li Subject: [PULL 4/5] hw/intc/loongarch_pch_pic: Add pic interrupt status display Date: Tue, 8 Sep 2026 15:35:47 +0800 Message-ID: <20260908073548.3249551-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260908073548.3249551-1-maobibo@loongson.cn> References: <20260908073548.3249551-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxrM6Nup9qVA0dAA--.29211S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBj93XoWxWF1xWr4kGr47Aw4fZw1DJwc_yoW5Zr15pF W7uFnxJr4DGFsrXr93Z345ZF1FqFyxur13KFsxA340krZ8Gr1DXa48tryj9F1UK393Cr12 gws5tF1Yga1UCrbCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_JF0_Jw1lYx0Ex4A2jsIE 14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU1LiSJUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1788852935825158500 Content-Type: text/plain; charset="utf-8" When irqchip in kernel is enabled, the register status of pch_pic irqchip is in KVM kernel. Here add interrupt status display in user side in order to debug pch_pic irqchip driver. Signed-off-by: Bibo Mao Reviewed-by: Xianglai Li --- hw/intc/loongarch_pch_pic.c | 38 +++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index e87c7497c1..34090514ec 100644 --- a/hw/intc/loongarch_pch_pic.c +++ b/hw/intc/loongarch_pch_pic.c @@ -9,6 +9,7 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "hw/core/irq.h" +#include "hw/intc/intc.h" #include "hw/intc/loongarch_pch_pic.h" #include "system/kvm.h" #include "trace.h" @@ -331,11 +332,43 @@ static int loongarch_pic_post_load(LoongArchPICCommon= State *opaque, return 0; } =20 +static void loongarch_pic_print_info(InterruptStatsProvider *obj, GString = *buf) +{ + LoongArchPICCommonState *s =3D LOONGARCH_PIC_COMMON(obj); + uint64_t *vector; + + loongarch_pic_pre_save(s); + g_string_append_printf(buf, "%s:\n", object_get_typename(OBJECT(obj))); + + g_string_append_printf(buf, " mask 0x%016"PRIx64" msi_en 0x%016"P= RIx64 + " edge 0x%016"PRIx64" clr 0x%016"PRIx64= "\n", + s->int_mask, s->htmsi_en, s->intedge, + s->intclr); + + g_string_append_printf(buf, " last_irr 0x%016"PRIx64" irr 0x%016"P= RIx64 + " isr 0x%016"PRIx64" polary 0x%016"PRIx64= "\n", + s->last_intirr, s->intirr, s->intisr, + s->int_polarity); + + vector =3D (uint64_t *)s->htmsi_vector; + g_string_append_printf(buf, " MSI map 0x%016"PRIx64" 0x%016"PRIx64 + " 0x%016"PRIx64" 0x%016"PRIx64"\n", + *vector, *(vector + 1), *(vector + 2), + *(vector + 3)); + + vector +=3D 4; + g_string_append_printf(buf, " 0x%016"PRIx64" 0x%016"PRIx64 + " 0x%016"PRIx64" 0x%016"PRIx64"\n", + *vector, *(vector + 1), *(vector + 2), + *(vector + 3)); +} + static void loongarch_pic_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); LoongarchPICClass *lpc =3D LOONGARCH_PIC_CLASS(klass); LoongArchPICCommonClass *lpcc =3D LOONGARCH_PIC_COMMON_CLASS(klass); + InterruptStatsProviderClass *ic =3D INTERRUPT_STATS_PROVIDER_CLASS(kla= ss); ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 resettable_class_set_parent_phases(rc, NULL, loongarch_pic_reset_hold, @@ -344,6 +377,7 @@ static void loongarch_pic_class_init(ObjectClass *klass= , const void *data) &lpc->parent_realize); lpcc->pre_save =3D loongarch_pic_pre_save; lpcc->post_load =3D loongarch_pic_post_load; + ic->print_info =3D loongarch_pic_print_info; } =20 static const TypeInfo loongarch_pic_types[] =3D { @@ -353,6 +387,10 @@ static const TypeInfo loongarch_pic_types[] =3D { .instance_size =3D sizeof(LoongarchPICState), .class_size =3D sizeof(LoongarchPICClass), .class_init =3D loongarch_pic_class_init, + .interfaces =3D (const InterfaceInfo[]) { + { TYPE_INTERRUPT_STATS_PROVIDER }, + { } + }, } }; =20 --=20 2.54.0 From nobody Sat Sep 26 20:02:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788852953593400.7862381004692; Tue, 8 Sep 2026 00:35:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3qLx-0002CG-HR; Tue, 08 Sep 2026 03:34:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3qLu-0002AF-O5 for qemu-devel@nongnu.org; Tue, 08 Sep 2026 03:34:46 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3qLr-000070-9K for qemu-devel@nongnu.org; Tue, 08 Sep 2026 03:34:46 -0400 Received: from loongson.cn (unknown [10.40.46.54]) by gateway (Coremail) with SMTP id _____8Bxn9GOup9qtbcJAA--.27746S3; Tue, 08 Sep 2026 15:34:38 +0800 (CST) Received: from fedora.loongson.cn (unknown [10.40.46.54]) by front1 (Coremail) with SMTP id qMiowJBxrM6Nup9qVA0dAA--.29211S3; Tue, 08 Sep 2026 15:34:38 +0800 (CST) From: Bibo Mao To: qemu-devel@nongnu.org Cc: Xianglai Li Subject: [PULL 5/5] hw/intc/loongarch_extioi: Add extioi interrupt status display Date: Tue, 8 Sep 2026 15:35:48 +0800 Message-ID: <20260908073548.3249551-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260908073548.3249551-1-maobibo@loongson.cn> References: <20260908073548.3249551-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxrM6Nup9qVA0dAA--.29211S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBj93XoWxWF1fAFyrGFy5GF48ZrWfCrX_yoW5Kw1rpF 43uFW3Wr4UGanxJr9xWayDuF1rtws3ur12qFZFv348uayUGryDuas2qry7XF4UCws7t3Wv kwn5tryYgF1DArcCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_JF0_Jw1lYx0Ex4A2jsIE 14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU1LiSJUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1788852955929158500 Content-Type: text/plain; charset="utf-8" When irqchip in kernel is enabled, the register status of extioi irqchip is in KVM kernel. Here add interrupt status display in user side in order to debug extioi irqchip driver. Signed-off-by: Bibo Mao Reviewed-by: Xianglai Li --- hw/intc/loongarch_extioi.c | 58 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c index 2999740269..06f2aa7b14 100644 --- a/hw/intc/loongarch_extioi.c +++ b/hw/intc/loongarch_extioi.c @@ -10,6 +10,7 @@ #include "qemu/log.h" #include "qapi/error.h" #include "hw/core/irq.h" +#include "hw/intc/intc.h" #include "hw/loongarch/virt.h" #include "system/address-spaces.h" #include "system/kvm.h" @@ -420,11 +421,63 @@ static int vmstate_extioi_post_load(void *opaque, int= version_id) return 0; } =20 +static void loongarch_extioi_print_info(InterruptStatsProvider *obj, + GString *buf) +{ + LoongArchExtIOICommonState *s =3D LOONGARCH_EXTIOI_COMMON(obj); + uint64_t *val; + unsigned long irq; + ExtIOICore *core; + int i; + + vmstate_extioi_pre_save(s); + g_string_append_printf(buf, "%s:\n", object_get_typename(OBJECT(obj))); + + val =3D (uint64_t *)s->isr; + g_string_append_printf(buf, " ISR 0x%016"PRIx64" 0x%016"PRIx64 + " 0x%016"PRIx64" 0x%016"PRIx64"\n", + *val, *(val + 1), *(val + 2), *(val + 3)); + val =3D (uint64_t *)s->enable; + g_string_append_printf(buf, " ENABLE 0x%016"PRIx64" 0x%016"PRIx64 + " 0x%016"PRIx64" 0x%016"PRIx64"\n", + *val, *(val + 1), *(val + 2), *(val + 3)); + val =3D (uint64_t *)s->ipmap; + g_string_append_printf(buf, " IPMAP 0x%016"PRIx64"\n", *val); + + val =3D (uint64_t *)s->coremap; + for (i =3D 0; i < EXTIOI_IRQS; i +=3D 32) { + g_string_append_printf(buf, " COREMAP 0x%016"PRIx64" 0x%016"PRIx64 + " 0x%016"PRIx64" 0x%016"PRIx64"\n", + *val, *(val + 1), *(val + 2), *(val + = 3)); + val +=3D 4; + } + + core =3D s->cpu; + for (i =3D 0; i < s->num_cpu; i++, core++) { + if (!core->cpu) { + continue; + } + + irq =3D find_first_bit((unsigned long *)core->coreisr, EXTIOI_IRQS= ); + /* No pending IRQ */ + if (irq =3D=3D EXTIOI_IRQS) { + continue; + } + + val =3D (uint64_t *)core->coreisr; + g_string_append_printf(buf, " CPU[%d] ISR 0x%016"PRIx64" 0x%016"P= RIx64 + " 0x%016"PRIx64" 0x%016"PRIx64"\n", + i, *val, *(val + 1), *(val + 2), + *(val + 3)); + } +} + static void loongarch_extioi_class_init(ObjectClass *klass, const void *da= ta) { DeviceClass *dc =3D DEVICE_CLASS(klass); LoongArchExtIOIClass *lec =3D LOONGARCH_EXTIOI_CLASS(klass); LoongArchExtIOICommonClass *lecc =3D LOONGARCH_EXTIOI_COMMON_CLASS(kla= ss); + InterruptStatsProviderClass *ic =3D INTERRUPT_STATS_PROVIDER_CLASS(kla= ss); ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 device_class_set_parent_realize(dc, loongarch_extioi_realize, @@ -433,6 +486,7 @@ static void loongarch_extioi_class_init(ObjectClass *kl= ass, const void *data) NULL, &lec->parent_phases); lecc->pre_save =3D vmstate_extioi_pre_save; lecc->post_load =3D vmstate_extioi_post_load; + ic->print_info =3D loongarch_extioi_print_info; } =20 static const TypeInfo loongarch_extioi_types[] =3D { @@ -442,6 +496,10 @@ static const TypeInfo loongarch_extioi_types[] =3D { .instance_size =3D sizeof(LoongArchExtIOIState), .class_size =3D sizeof(LoongArchExtIOIClass), .class_init =3D loongarch_extioi_class_init, + .interfaces =3D (const InterfaceInfo[]) { + { TYPE_INTERRUPT_STATS_PROVIDER }, + { } + }, } }; =20 --=20 2.54.0