From nobody Sat Sep 26 19:59:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1788791094; cv=none; d=zohomail.com; s=zohoarc; b=EOv0ym7djotWdyJAHfubkdL78AuEjYo0rtYoSAa5CeFnRYbnD7j4kwcfqBp1YYh6JzBDDcQSPT+i1fDkXX0D0OH/cw5dZtY3cRqY4VJcU5G7tfKh5FY0fQOe8YAy5VUyCKdPWnhRH2nAQFs76KDQd1WXsuIIqXk3lW4WEUWyM7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788791094; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=J1brsl71IEXD02jTIvt6amMa7SMls9Qs5ZHUMqIyFqM=; b=JNZfJ263WUJk0cRi548h5Azr1RxokB4KqAtpmRck6hgTsr8dycBNMPWtuqcgzIbGSjMBdY8alU9OVmvmjMsockXLKM0gB3/niLMTFXo8WjolYC8S2xP/P8HJVn/Vfd3qs7Zt7Z9+tSdXENlFL5xSvCPMaYlHkrZrR4Q68KtAMlw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788791094700490.15600914511083; Mon, 7 Sep 2026 07:24:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3aGU-0004Wj-Bd; Mon, 07 Sep 2026 10:24:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3aGT-0004WW-A9 for qemu-devel@nongnu.org; Mon, 07 Sep 2026 10:24:05 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3aGR-0006Ye-EN for qemu-devel@nongnu.org; Mon, 07 Sep 2026 10:24:05 -0400 Received: from laptop.localdomain (unknown [81.196.141.93]) by linux.microsoft.com (Postfix) with ESMTPSA id 6F58520B712B; Mon, 7 Sep 2026 07:23:21 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 6F58520B712B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1788791003; bh=J1brsl71IEXD02jTIvt6amMa7SMls9Qs5ZHUMqIyFqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pvJX2ZR1Np77wT+geR7t5dQDL+qN++dcT94Zfec8yzWS3aPB96GP12mCYxj5R2F1C Cny9/BzKPhCsYiiraKl2e5IQzfoUdyySsNEnbOYuK4Z9pN70Qw1Q3zi1peEUDrwt7L hSDCblPnrx/YdcICX1N8oTMO7zBdNqH6lHFCALd4= From: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= To: qemu-devel@nongnu.org Cc: Wei Liu , Magnus Kulke , Wei Liu , Magnus Kulke , =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= , =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= Subject: [PATCH 1/2] accel/mshv: size XSAVE buffers from the hypervisor Date: Mon, 7 Sep 2026 17:23:54 +0300 Message-ID: <20260907142355.141033-2-dblanzeanu@linux.microsoft.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260907142355.141033-1-dblanzeanu@linux.microsoft.com> References: <20260907142355.141033-1-dblanzeanu@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1788791096585154100 Query MAX_XSAVE_DATA_SIZE at vcpu creation and cache it in MshvState. Introduce a new trace event for the xsave area size reported by the hypervisor. Also fixes a leak of xsavec_buf on the get error path and switches qemu_memalign() buffers to qemu_vfree(). No functional change on hosts reporting under 4 KiB. Signed-off-by: Doru Bl=C3=A2nzeanu --- accel/mshv/mshv-all.c | 21 +++++++++++++++++++++ accel/mshv/trace-events | 2 ++ include/system/mshv_int.h | 3 +++ target/i386/mshv/mshv-cpu.c | 34 +++++++++++++++++++++++++--------- 4 files changed, 51 insertions(+), 9 deletions(-) diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c index 5921ce693e..725ccd0511 100644 --- a/accel/mshv/mshv-all.c +++ b/accel/mshv/mshv-all.c @@ -162,6 +162,27 @@ static int get_proc_features(int vm_fd, return 0; } =20 +int mshv_get_max_xsave_size(int vm_fd, uint32_t *size) +{ + uint64_t value =3D 0; + int ret; + + ret =3D get_partition_property(vm_fd, + HV_PARTITION_PROPERTY_MAX_XSAVE_DATA_SIZE, + &value); + if (ret < 0) { + error_report("Failed to get partition property MAX_XSAVE_DATA_SIZE= "); + return -1; + } + + /* round up to page size */ + *size =3D ROUND_UP(value, HV_HYP_PAGE_SIZE); + + trace_mshv_xsave_data_size(value, *size); + + return 0; +} + static int create_partition(int mshv_fd, int *vm_fd) { int ret; diff --git a/accel/mshv/trace-events b/accel/mshv/trace-events index 859e8bfb0f..9473530140 100644 --- a/accel/mshv/trace-events +++ b/accel/mshv/trace-events @@ -12,6 +12,8 @@ mshv_mem_ioeventfd_del(uint64_t addr, uint32_t size, uint= 32_t data) "addr=3D0x%" P =20 mshv_hvcall_args(const char* hvcall, uint16_t code, uint16_t in_sz) "built= args for '%s' code: %d in_sz: %d" =20 +mshv_xsave_data_size(uint64_t required, uint32_t allocated) "required=3D%"= PRIu64 " allocated=3D%u" + mshv_handle_interrupt(uint32_t cpu, int mask) "cpu_index=3D%d mask=3D0x%x" mshv_set_msi_routing(uint32_t gsi, uint64_t addr, uint32_t data) "gsi=3D%d= addr=3D0x%" PRIx64 " data=3D0x%x" mshv_remove_msi_routing(uint32_t gsi) "gsi=3D%d" diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h index 3dffe3c5fb..9d0957a65b 100644 --- a/include/system/mshv_int.h +++ b/include/system/mshv_int.h @@ -70,6 +70,8 @@ struct MshvState { unsigned long *used_gsi_bitmap; unsigned int gsi_count; union hv_partition_processor_features processor_features; + /* compacted xsave area size rounded up to the page size */ + uint32_t xsave_data_size; }; =20 typedef struct MshvMsiControl { @@ -107,6 +109,7 @@ void mshv_arch_amend_proc_features( void mshv_arch_disable_partition_proc_features( union hv_partition_processor_features *disabled_features); int mshv_arch_post_init_vm(int vm_fd); +int mshv_get_max_xsave_size(int vm_fd, uint32_t *size); int mshv_get_vp_state(int cpu_fd, struct mshv_get_set_vp_state *state); int mshv_set_vp_state(int cpu_fd, const struct mshv_get_set_vp_state *stat= e); typedef struct mshv_root_hvcall mshv_root_hvcall; diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index f528dd2b9a..7ce05bfb17 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -157,9 +157,8 @@ static int get_xsave_state(CPUState *cpu) int ret; void *xsavec_buf; const size_t page =3D HV_HYP_PAGE_SIZE; - size_t xsavec_buf_len =3D page; + size_t xsavec_buf_len =3D mshv_state->xsave_data_size; =20 - /* TODO: should properly determine xsavec size based on CPUID */ xsavec_buf =3D qemu_memalign(page, xsavec_buf_len); memset(xsavec_buf, 0, xsavec_buf_len); =20 @@ -172,11 +171,12 @@ static int get_xsave_state(CPUState *cpu) ret =3D ioctl(cpu_fd, MSHV_GET_VP_STATE, &args); if (ret < 0) { error_report("failed to get xsave state: %s", strerror(errno)); + qemu_vfree(xsavec_buf); return -errno; } =20 ret =3D decompact_xsave_area(xsavec_buf, xsavec_buf_len, env); - g_free(xsavec_buf); + qemu_vfree(xsavec_buf); if (ret < 0) { error_report("failed to decompact xsave area"); return ret; @@ -196,8 +196,8 @@ static int set_xsave_state(const CPUState *cpu) size_t page =3D HV_HYP_PAGE_SIZE, xsavec_buf_len; =20 /* allocate and populate compacted buffer */ - xsavec_buf =3D qemu_memalign(page, page); - xsavec_buf_len =3D page; + xsavec_buf_len =3D mshv_state->xsave_data_size; + xsavec_buf =3D qemu_memalign(page, xsavec_buf_len); =20 /* save registers to standard format buffer */ x86_cpu_xsave_all_areas(x86cpu, env->xsave_buf, env->xsave_buf_len); @@ -212,7 +212,7 @@ static int set_xsave_state(const CPUState *cpu) }; =20 ret =3D ioctl(cpu_fd, MSHV_SET_VP_STATE, &args); - g_free(xsavec_buf); + qemu_vfree(xsavec_buf); if (ret < 0) { error_report("failed to set xsave state: %s", strerror(errno)); return -errno; @@ -2125,6 +2125,24 @@ void mshv_arch_init_vcpu(CPUState *cpu) int ret; X86XSaveHeader *header; =20 + /* get the xsave data size */ + if (!mshv_state->xsave_data_size) { + ret =3D mshv_get_max_xsave_size(mshv_state->vm, + &mshv_state->xsave_data_size); + if (ret < 0) { + warn_report("failed to get the max xsave area size: %s", + strerror(errno)); + /* + * Use the maximum size for xsave because the partition is + * provisioned with every XSAVE component supported + */ + mshv_state->xsave_data_size =3D + ROUND_UP(mshv_get_supported_cpuid(0xD, 0, R_ECX), page); + } + /* never allow a zero-sized xsave area */ + mshv_state->xsave_data_size =3D MAX(mshv_state->xsave_data_size, p= age); + } + /* sanity check, to make sure we don't overflow the page */ QEMU_BUILD_BUG_ON((MAX_REGISTER_COUNT * sizeof(hv_register_assoc) @@ -2149,9 +2167,7 @@ void mshv_arch_init_vcpu(CPUState *cpu) =20 env->emu_mmio_buf =3D g_new(char, 4096); =20 - /* Initialize XSAVE buffer page-aligned */ - /* TODO: pick proper size based on CPUID */ - xsave_len =3D page; + xsave_len =3D mshv_state->xsave_data_size; env->xsave_buf =3D qemu_memalign(page, xsave_len); env->xsave_buf_len =3D xsave_len; memset(env->xsave_buf, 0, env->xsave_buf_len); --=20 2.53.0 From nobody Sat Sep 26 19:59:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1788791094; cv=none; d=zohomail.com; s=zohoarc; b=KVSyY0pizzTfmd9aKjG9vCj1fAc7MdnJXjF/CvvVDdlB8NsSc6JGTVOam1qLzD9UckFgYnGezCqjv2f6afEsC8Ewt2f4vktVx7KYqFbpT6a9jJakw2D9pDrgFwFuftUFMFO7n4Zlo/DA6himM8MJJZgjgHhmZ+aoOw7l3KKGTr4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788791094; 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Mon, 07 Sep 2026 10:24:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3aGW-0004Wv-Bv for qemu-devel@nongnu.org; Mon, 07 Sep 2026 10:24:08 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3aGU-0006Z7-C4 for qemu-devel@nongnu.org; Mon, 07 Sep 2026 10:24:08 -0400 Received: from laptop.localdomain (unknown [81.196.141.93]) by linux.microsoft.com (Postfix) with ESMTPSA id D991A20B7128; Mon, 7 Sep 2026 07:23:23 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com D991A20B7128 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1788791005; bh=erpSLdPysRVjCLcWr1f1pDlnO3o6Z1Ax+t4JTLQHMQ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JQOPzAjcgh91Fgyc7fFuQBeisQdOIY6ZhVJuHQHE09dmhjBCgyOiN+IFTCst+yXXV Dww0jOvtHkVGjd//wwPQxqsf1l4YDkvaBU01usoxrAcjpNLGvHYa2Eq2oZWkyKyj4f to9+eNdWvgb1Me+pVH8nVQI0rl6YOOfuILDLvc2s= From: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= To: qemu-devel@nongnu.org Cc: Wei Liu , Magnus Kulke , Wei Liu , Magnus Kulke , =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= , =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= Subject: [PATCH 2/2] accel/mshv: enable amx tiles support for guests Date: Mon, 7 Sep 2026 17:23:55 +0300 Message-ID: <20260907142355.141033-3-dblanzeanu@linux.microsoft.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260907142355.141033-1-dblanzeanu@linux.microsoft.com> References: <20260907142355.141033-1-dblanzeanu@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1788791097058158500 The AMX tiles feature uses a larger than 4kB area in xsave. This fix removes the code that disables AMX tiles in the partition and it adjusts the supported CPUID to advertise AMX tiles. Signed-off-by: Doru Bl=C3=A2nzeanu --- accel/mshv/mshv-all.c | 18 +++++------------- target/i386/mshv/mshv-cpu.c | 16 ---------------- 2 files changed, 5 insertions(+), 29 deletions(-) diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c index 725ccd0511..99b2b3362a 100644 --- a/accel/mshv/mshv-all.c +++ b/accel/mshv/mshv-all.c @@ -187,7 +187,6 @@ static int create_partition(int mshv_fd, int *vm_fd) { int ret; uint64_t pt_flags, host_proc_features; - union hv_partition_processor_xsave_features disabled_xsave_features; union hv_partition_processor_features disabled_partition_features =3D = {0}; =20 struct mshv_create_partition_v2 args =3D {0}; @@ -200,17 +199,6 @@ static int create_partition(int mshv_fd, int *vm_fd) (1ULL << MSHV_PT_BIT_GPA_SUPER_PAGES) | (1ULL << MSHV_PT_BIT_CPU_AND_XSAVE_FEATURES); =20 - /* enable all */ - disabled_xsave_features.as_uint64 =3D 0; - /* - * AMX TILE XSAVE state (XTILE_DATA) is 8KB, which exceeds the - * current fixed 4KB XSAVE buffer size. - */ - disabled_xsave_features.amx_tile_support =3D 1; - disabled_xsave_features.amx_bf16_support =3D 1; - disabled_xsave_features.amx_int8_support =3D 1; - disabled_xsave_features.amx_fp16_support =3D 1; - /* * query host for supported processor features and disable unsupported * features: (0 means supported, 1 means disabled, hence the negation) @@ -238,10 +226,14 @@ static int create_partition(int mshv_fd, int *vm_fd) args.pt_cpu_fbanks[0] |=3D disabled_partition_features.as_uint64[0]; args.pt_cpu_fbanks[1] |=3D disabled_partition_features.as_uint64[1]; =20 + /* + * for now, all the xsave features are enabled, the filtering is only = done + * at the CPUID level + * TODO: filter the xsave features based on the CPUID derived from Cpu= model + */ /* populate args structure */ args.pt_flags =3D pt_flags; args.pt_isolation =3D MSHV_PT_ISOLATION_NONE; - args.pt_disabled_xsave =3D disabled_xsave_features.as_uint64; args.pt_num_cpu_fbanks =3D MSHV_NUM_CPU_FEATURES_BANKS; =20 ret =3D ioctl(mshv_fd, MSHV_CREATE_PARTITION, &args); diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 7ce05bfb17..6a6b9ccd02 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -2244,22 +2244,6 @@ uint32_t mshv_get_supported_cpuid(uint32_t func, uin= t32_t idx, int reg) */ ret &=3D ~CPUID_7_0_ECX_LA57; } - if (func =3D=3D 0x07 && idx =3D=3D 0 && reg =3D=3D R_EDX) { - /* - * AMX TILE XSAVE state (XTILE_DATA) is 8KB, which exceeds the - * current fixed 4KB XSAVE buffer size. Filter until buffer - * sizing is computed dynamically from CPUID. - */ - ret &=3D ~CPUID_7_0_EDX_AMX_TILE; - ret &=3D ~CPUID_7_0_EDX_AMX_BF16; - ret &=3D ~CPUID_7_0_EDX_AMX_INT8; - } - if (func =3D=3D 0x07 && idx =3D=3D 1 && reg =3D=3D R_EAX) { - ret &=3D ~CPUID_7_1_EAX_AMX_FP16; - } - if (func =3D=3D 0x07 && idx =3D=3D 1 && reg =3D=3D R_EDX) { - ret &=3D ~CPUID_7_1_EDX_AMX_COMPLEX; - } =20 return ret; } --=20 2.53.0