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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cee60bae6sm468589935e9.9.2026.09.07.06.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 06:02:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788786147; x=1789390947; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=2SIbkR3zLUPorTsZ3CZUe6Kq3hBul8d9QZlsky3KnOQ=; b=ZbWuwJr3Etvxu0tlbpsTJD/SLppictoQELzFLJER87ZN0v0+svc9ReV3kSID6ZqE8W LUPPyVemd1MsT4oMOYIEGv9KbscZNkfXBfzHPgbIA3JJUbLUipBRWsEONCpFwH3gPEyi oQwh1yLeUo4qeH4fEGqWTGnEruvlqCN5uEwunZ8aJjXGkBeIO+c/ZanVZW7cc7t5/24o KTSBJCI7zK6MdKAoKnpPJz38kX0tzpoBpQcPoViku1EnSYrs0ZrbVHy02WxAoLyn7sCv PQQ4EJFq7KrIqu+/tUcIDAkFd63MUQbQPB8WDS4XMJTjQOnQUKNBpRmywHH+A+COqq8e xl0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788786147; x=1789390947; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=2SIbkR3zLUPorTsZ3CZUe6Kq3hBul8d9QZlsky3KnOQ=; b=P2IIJ8iWc8sKe6Y7JZHYtmIdz5FVQVGU+H1i0j2WACfl1ZHygDo/c/nb8MvdU0ovUC CCgI/GjH6T+4BzfSa15IHhJ5rL1/JVOWKLCoKa8lXOPtL6Zlp38btprHq3Q+S2H0kL1J RyCMeHhK+WCbU6SPZvS2w3Zx/OhkuP9MtbEC/IwKKgFsV45DIiH7k1KtUl6AgQBp2dWb /h/0a9vfPTUpusgFSiBTVShvpkLwK2ynB8TuDGczZb4Z92znC7dgO4Myce2Keh5UExmI M/8Qq7nZg9jA5Mqs7hjbjaAULVxMCEjY0UlgNpPBBJRGg++Hpgx12cYx8coWrlkPg0cU AJRQ== X-Forwarded-Encrypted: i=1; AKwUvBx6EbOrPhX7GzclOkuDJIaxjGOBuHjaCDLCaDOqr3tUOqDmdvoahw0KU7qzomdlARtxK7NC7XTAcGCg@nongnu.org X-Gm-Message-State: AFuF++l276eMF6C52AU2167HAsCRR5rD+ZRu3v+0IBgu3wslTDe9jtd8 rCybGSnwIuMk4R8HljOEHC2xg6ZtuOKtmZBYbsrof5mHsIEoCKVRk8LKWrhqfPtdRIY= X-Gm-Gg: AYBFou0TfdQmmLRTkouGznjBbQV57w5jE0JffMiB1VYF3ZH4VQ6a9vbTsICps8JJpOi ynxOWrFE/G1/ng/ZDVY/sbKsue/+WRYxYad0lgzHCUoj5BQvXI1vXM8btA2Z59ld2+G22F75olg PZh/nccXL16of4sKap4LG7GfXSvNPYsS4z4QN+0+uJUE4aX0GTcRg7+rGMh5HiaNEdQ39SRxqkh plTjVkRJm8wB3sPPcCSwBqKTVs6XVP/LAYyWOCsnA9eMDfpGc8sGlOOhZMf6t1UOJKX2rvqVxjm rF2wdnb/V/0Viaw2jdkz7BY+hzjkpR+mJCwU7ecL4+s3zT8DKC6T7hKF6oo1oV373LN11vNt06Q 7R9yWZc5pFfles9mSII2kuwcxWSNyBW/PNniplVxkuoELx0+7oryM5QnPoxYd4bVUJcB0ZR+lpC 4sbJfC9Xw4i4c3Qdkxi8kvswI9YH7txgg+gePZkel2QywNmMur6qHByb8Mgg174BXnJz/3ilkfA 8qlxmD2UFLZQwn0WEtlM8tmlkjQM5ozfEVnR5WSRRG3i1bO9wuNe/OYUie3RCxqdndgLg== X-Received: by 2002:a05:600c:8b88:b0:49c:fc6e:a3d8 with SMTP id 5b1f17b1804b1-49cffde8d95mr176142925e9.23.1788786146554; Mon, 07 Sep 2026 06:02:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Tao Ding Subject: [PATCH 1/8] target/arm: Keep the S/NS bit in migration data Date: Mon, 7 Sep 2026 14:02:16 +0100 Message-ID: <20260907130223.3148989-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260907130223.3148989-1-peter.maydell@linaro.org> References: <20260907130223.3148989-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788786238892158500 Content-Type: text/plain; charset="utf-8" For Arm, the format we use on the wire for migration of sysregs (cpregs on AArch32) is a set of arrays, where cpreg_indexes[] holds the register IDs and cpreg_values[] holds the corresponding values. The ID format we use is KVM's ID format, which is 64 bits. This is not quite the same as the 32-bit ID format QEMU uses internally for things like the coprocessor register hashtable keys, and so we have conversion functions kvm_to_cpreg_id() and cpreg_to_kvm_id() to swap between them. This conversion has never handled AArch32 Secure coprocessor registers correctly: the KVM ID format has no way to indicate a Secure register, because KVM VMs on AArch32 were always NonSecure. The current code doesn't touch the CP_REG_AA32_NS_MASK bit when converting from the 32-bit ID format to a KVM ID, and it forces the NS bit to 1 when converting from a KVM ID to a cpreg. The effect of this on migration is that the indexes in cpreg_indexes[] have NS =3D 0 for the Secure banked registers and NS =3D 1 for the NS banked registers, but when we read and write the values into the CPUState by finding the register using kvm_to_cpreg_id(cpreg_indexes[i]) we always find the NS register, and so the S register values aren't actually migrated. This went unnoticed most of the time because a typical Linux guest is running only in NS and doesn't really care about the S register state, but it breaks migration of a guest which is running in S, such as Linux on the imx boards. This would be more awkward to fix if KVM still supported AArch32 hosts, but luckily that was dropped some years ago, and AArch32 guests on an AArch64 host expose the sysregs as CP_REG_ARM64, not CP_REG_ARM32. So the only place where we use a CP_REG_ARM32 KVM register ID is for TCG migrations. We can therefore (continue to) steal a bit in the KVM format for the NS bit, with the semantics we've given it on the wire in the past. We just need to let kvm_to_cpreg_id() pass it through rather than forcing it to 1. To retain compatibility with migration from older QEMU versions without this fix, we need to add a subsection to the migration data that tells the destination that it can trust the values for Secure banked registers. For incoming migrations, if we don't see this then we ignore all the values for Secure banked registers, giving the same behaviour as before. This means we continue to work for migrations where the Secure world exists but the guest is basically not using it, such as a direct kernel boot on boards which don't set arm_boot_info::secure_boot to true; this includes the cubieboard, bananapi and orangepi. Attempting migration from a new QEMU to an older QEMU version will now fail cleanly (because the destination doesn't recognize the new subsection) rather than silently corrupting the Secure banked registers. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/467 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpregs.h | 21 ++++++++---- target/arm/cpu.h | 6 ++++ target/arm/machine.c | 80 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+), 7 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 9f2532fe667..ce651a4faa6 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -215,7 +215,20 @@ enum { =20 /* * Convert a full 64 bit KVM register ID to the truncated 32 bit - * version used as a key for the coprocessor register hashtable + * version used as a key for the coprocessor register hashtable. + * + * Note that we deviate slightly from the KVM register ID format as + * used by the kernel for AArch32 cpregs, by using bit 29 as "1 + * for NonSecure, 0 for Secure". (When KVM still supported AArch32 + * hosts it didn't set this bit; all sysregs for KVM guests are + * NonSecure anyway.) This shouldn't cause any issues as KVM no longer + * supports AArch32 hosts (and other accelerators never did), so the + * only thing that generates KVM regids for AArch32 cpregs is QEMU + * TCG. + * + * The NS bit being in the KVM ID is implicit in the fact that we + * don't mask out CP_REG_AA32_NS_MASK in the conversions to and from + * the QEMU hashtable key ID format. */ static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) { @@ -226,12 +239,6 @@ static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) if ((kvmid & CP_REG_SIZE_MASK) =3D=3D CP_REG_SIZE_U64) { cpregid |=3D CP_REG_AA32_64BIT_MASK; } - - /* - * KVM is always non-secure so add the NS flag on AArch32 register - * entries. - */ - cpregid |=3D CP_REG_AA32_NS_MASK; } return cpregid; } diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e3f931dba26..231fdf710b7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1128,6 +1128,12 @@ struct ArchCPU { bool prop_pauth_qarma5; bool prop_lpa2; =20 + /* + * Used only during migration, to handle back-compat with older QEMU + * that mishandled migration of AArch32 banked cpregs. + */ + bool secure_banked_regs_ok; + /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ uint8_t gm_blocksize; =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index 89127e5d83c..1fc3acc31ca 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -979,6 +979,39 @@ static const VMStateDescription vmstate_fpmr =3D { }, }; =20 +static bool secure_banked_regs_ok_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + /* + * We must send this subsection if this is an AArch32 CPU with + * banked coprocessor registers. Older QEMU mishandled migration + * of these by listing both Secure and NonSecure banked registers + * in the cpreg_vmstate_indexes but reading and writing the + * NonSecure register for both indexes. Providing this subsection + * tells the destination that we do not have this bug and it + * should not ignore the Secure banked register values. + * + * We don't need the subsection for CPUs without banked registers + * (notably AArch64 ones and M-profile ones), and don't send + * it to avoid breaking migration compat for them. + */ + return !arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && + !arm_feature(&cpu->env, ARM_FEATURE_M) && + arm_feature(&cpu->env, ARM_FEATURE_EL3); +} + +static const VMStateDescription vmstate_secure_banked_regs_ok =3D { + .name =3D "cpu/secure-banked-regs-ok", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D secure_banked_regs_ok_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_BOOL(secure_banked_regs_ok, ARMCPU), + VMSTATE_END_OF_LIST() + }, +}; + static int cpu_pre_save(void *opaque) { ARMCPU *cpu =3D opaque; @@ -1014,6 +1047,9 @@ static int cpu_pre_save(void *opaque) cpu->cpreg_vmstate_values =3D cpu->cpreg_values; cpu->cpreg_vmstate_array_len =3D cpu->cpreg_array_len; =20 + /* We don't have the bug where we send wrong data for Secure regs */ + cpu->secure_banked_regs_ok =3D true; + return 0; } =20 @@ -1062,6 +1098,9 @@ static int cpu_pre_load(void *opaque) g_assert(!cpu->cpreg_vmstate_indexes); g_assert(!cpu->cpreg_vmstate_values); =20 + /* So cpu_post_load() can see if we saw secure-banked-regs-ok */ + cpu->secure_banked_regs_ok =3D false; + return 0; } =20 @@ -1120,6 +1159,7 @@ static int cpu_post_load(void *opaque, int version_id) ARMCPU *cpu =3D opaque; CPUARMState *env =3D &cpu->env; bool fail =3D false; + bool ignore_s_regs; int i, v; =20 trace_cpu_post_load(cpu->cpreg_vmstate_array_len, @@ -1142,6 +1182,21 @@ static int cpu_post_load(void *opaque, int version_i= d) CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VFIQ); } =20 + /* + * Handle migration compatibility from an old QEMU which didn't get + * AArch32 Secure banked cpregs right. That QEMU will not have sent + * us the secure-banked-regs-ok subsection, and although its + * vmstate_indexes will include the S banked regs, the values in + * vmstate_values will be duplicates of the values of the NS banked + * regs. Ignore the S banked registers, which is the same effective + * behaviour of an old->old migration. (That is, the S regs will + * be at their reset values, which is usually good enough for the + * case of "guest is actually executing in NS and doesn't care + * about the S state".) + */ + ignore_s_regs =3D secure_banked_regs_ok_needed(cpu) && + !cpu->secure_banked_regs_ok; + /* Update the values list from the incoming migration data. * Anything in the incoming data which we don't know about is * a migration failure; anything we know about but the incoming @@ -1165,6 +1220,30 @@ static int cpu_post_load(void *opaque, int version_i= d) continue; } /* matching register, copy the value over */ + + if (ignore_s_regs) { + /* + * If this is an AArch32 Secure cpreg, read the current (reset) + * value instead of using the migration state value. That way + * write_list_to_cpustate() will effectively be a NOP. + */ + uint64_t kvmidx =3D cpu->cpreg_vmstate_indexes[v]; + + if ((kvmidx & CP_REG_ARCH_MASK) =3D=3D CP_REG_ARM && + (kvmidx & CP_REG_AA32_NS_MASK) =3D=3D 0) { + uint32_t regidx =3D kvm_to_cpreg_id(kvmidx); + const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(cpu->cp_regs, + regidx); + /* + * Missing ri or NO_RAW ri will be ignored or errored in + * write_list_to_cpustate() later, so safe to skip. + */ + if (ri && !(ri->type & ARM_CP_NO_RAW)) { + cpu->cpreg_vmstate_values[v] =3D read_raw_cp_reg(env, = ri); + } + } + } + cpu->cpreg_values[i] =3D cpu->cpreg_vmstate_values[v]; i++; v++; @@ -1343,6 +1422,7 @@ const VMStateDescription vmstate_arm_cpu =3D { &vmstate_pstate64, &vmstate_event, &vmstate_fpmr, + &vmstate_secure_banked_regs_ok, NULL } }; --=20 2.43.0 From nobody Sat Sep 26 20:01:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788786222; cv=none; d=zohomail.com; s=zohoarc; b=PDPKnmc7o/c5kgUSu3fzrHTLy1VD6D33RShnWWOj1uOiGTfgsn8Qlbyy6B4Pe/Via+SCoIlTaPn8MH5cuFWEVY9Qaaz2Q86Ms+uALZwB1xx6oAJXhScMVLvCibu6D940eV3pEJMi8+fekGHJhqNDtOzVjJlBxAOikXKJkOqcinw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788786222; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BjmanBQ6cdorW9qdGQW5sVUyC1W6a6RSIT+PlHeq248=; b=UwCb6U6wXSrmYYWKLEsYCn2MfwI8NgGbpfGTGlORO98YmK3xvuYn9r+p5r9tVWHqt6K3DWQUJZFKkuhdHBQjOkdWCqXQTdyHV9jBHjB6ctDCmUuQcvOFToCrkb6SwJ1HxfzOYk1jbJcD2YfSzfu2j5LN2rWkObSr9gZnByAIk0M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788786222500691.0831903865193; Mon, 7 Sep 2026 06:03:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3Yzd-0006A1-5t; Mon, 07 Sep 2026 09:02:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3YzX-00067r-BT for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:32 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x3YzV-0004zz-A0 for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:31 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4956869750eso30824205e9.2 for ; Mon, 07 Sep 2026 06:02:28 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cee60bae6sm468589935e9.9.2026.09.07.06.02.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 06:02:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788786148; x=1789390948; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=BjmanBQ6cdorW9qdGQW5sVUyC1W6a6RSIT+PlHeq248=; b=XBTYi+cDx8T1qaduZQJqvI5nNO2AlilAAZED0LuKI3NqptyqcOJVJq8C7zkRSW7bxz zZMmo2YixJsJ8VRUBvgk5ZvYOkVVHs0avuZaH05XAKIThfAVr3tXBGJxbxtjjQGuPiQc OpAvEU2rgP3BlDDao8RiWapkx4wqPbRDBdTIMT1bS7rFk8EvEevVjQoKw6wKZtIm3Dei Gqfxa2YUBz+XaECx2OezKbXW4CpW6XbOiWuruzmR5OKd21EvfabWJSdBZCtApLu7xBVx pgk0A/pSwNKo2rWeJt5xFkSecpUt4TSyHmj8FB9UnyzjXDBvPdMBqcTUP+JXf7eHW2Mj b08w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788786148; x=1789390948; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=BjmanBQ6cdorW9qdGQW5sVUyC1W6a6RSIT+PlHeq248=; b=sln7Zh/ghUICIjAqWbRn5RgaCk/Y/RCfNOSpuMvHMrGq46AQ0d6MdiwGcr4tiJNrnI gGBDc1KGtYRehGc8jWlIczKEOHh+iOIIc1thKe9VgsHsnipKvH8m4VT0jNkRKfjVrDMU elz8yEgj3D6pUNgTCvL6vxu2++ZGnC5kyubSCruRZIYsYj4JghBkKw32XOrkCZtWqlcn +BruNyzlx54zOEk/xSJ9diSg8tsRg41je3G97wGl7k8dSQcaOecsyjmsfOBmgMRpphEe eR7D1aPJWxsD7LYyFWT7JPV+vbMSPsR7q4t0yfnwtngDZFpEHiYQnoPUlba9wLlj8VK1 3t7g== X-Forwarded-Encrypted: i=1; AKwUvBwMbFTEOFimBv5dNnpmTfjS+WJaDs+nFZgelPUFG3sNe4bTlawcu4W1zLsJ7TH4bGuvnuOHPdQh11E9@nongnu.org X-Gm-Message-State: AFuF++ncVd26Qw/wbBIxepFka3NHhxGGnbIE0LclXqHnbWQtnQnsSEjw eyKmGjY8wh8QMm8F6UR6+f3QucXQeSFk8yjeHIl3p7DOPto4bwC8rGe7OD8AC5xu7vQ= X-Gm-Gg: AYBFou011DVydmrNtI9ujwJdFxHJFt+W4FF5TVo/xz1rNZRy9c6uL4rUWBHGoKdomrR Xb0ekBhE6pc5eWUfu15KaGtHshTwZnKnzYG8g9Ibf1dVHpGlIAim41mBm9xHby8rYTHEj/cPrzX Ilj0SHL0JC5jvNuWV85dnlmY8dK7EBYY70Ila5Gh9Z9IVKOZ+xLCuehx0Hw5P3j2YTd7l1Xez5K fNw2Oe0sXwiAgiNnH1L0qrhNFT7juyW3Lhw4x12UJ9mxZKbCL6bc6cR75/Si4V5ljRqrP+cLwE4 /j4rlarwgzZjjIPNo77kiZCiOw39XH7fGhcz+XWcfXhCCgfpGG9q1nbJvk8AWB773TLPBh5NzYH TbIvpPTNMYKxSsxdDWO8Q/dtrSqZo++0gg+Jdjw62brQ8dnf4W8nlOgQ5fpK2sskE9r57Tzbb10 W+on0931witVL2v/SbVKV45N7pzTqI485icoXQfS9PyghtYcbIylTCjcL4XF94FyDSArfR8uVh1 D+vS734je1Bq9J9e8gFkB/gSOnmw7USxuRQe6eVvim7fsUqREQFp8ZxPaAaeg3hAjUG+A== X-Received: by 2002:a05:600c:3495:b0:49c:dadb:18a7 with SMTP id 5b1f17b1804b1-49cf8244260mr225172095e9.10.1788786147628; Mon, 07 Sep 2026 06:02:27 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Tao Ding Subject: [PATCH 2/8] target/arm: Don't assume secure-banked registers are migrated by 64-bit regs Date: Mon, 7 Sep 2026 14:02:17 +0100 Message-ID: <20260907130223.3148989-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260907130223.3148989-1-peter.maydell@linaro.org> References: <20260907130223.3148989-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788786224705158500 Content-Type: text/plain; charset="utf-8" In add_cpreg_to_hashtable() we have some code that automatically marks the secure version of an AArch32 banked cpreg as ARM_CP_ALIAS under two conditions: 1) If the register has both 32-bit and 64-bit instances then we can count on the 64-bit instance taking care of the non-secure bank. 2) If ARMv8 is enabled then we can count on a 64-bit version taking care of the secure bank. This requires that separate 32 and 64-bit definitions are provided. Item 1 is correct: if the ARMCPRegInfo has ARM_CP_STATE_BOTH then we will always add it as an AA32 entry (which then splits into an S entry with bank_fieldoffsets[0] and an NS entry with bank_fieldoffsets[1]) and as an AA64 entry (which uses bank_fieldoffsets[1]), so the AA64 entry will always be present to cover the NS banked AA32 entry. Item 2 is not correct: the idea was that because typically AArch32 Secure banked registers are (non-architecturally) mapped to EL3 AArch64 registers, the AArch64 EL3 register would handle things (and that we would be adding the AArch64 register to the hashtable even if the CPU didn't have AArch64). However, this fails in several cases: (a) registers like CSSELR, where there is only a CSSELR_EL1, and no _EL3 version. CSSELR_S's underlying state isn't migrated (b) registers like TPIDRURW, where the secure banked register isn't mapped to any AArch64 register, so the state isn't migrated (c) IFAR_S and DFAR_S are odd special cases, because they map to AArch32 HIFAR and HDFAR, which in turn map to AArch64 FAR_EL2. If the CPU doesn't have EL2, we don't register FAR_EL2 and the IFAR_S and DFAR_S registers don't get migrated. More generally, the architecture dropped the concept of documenting secure AArch32 registers as being "non-architecturally mapped" to EL3 AArch64 registers and relegated it to an implementation detail, which is why TPIDRURW and friends got mishandled. It also conflates "has 64-bit registers" with "is ARMv8", which is wrong for the qemu-system-arm "max" type and for any AArch64 CPU started with "aarch64=3Doff". Instead of marking the S-banked register as an alias if ARM_FEATURE_V8, don't put it into the hashtable at all if ARM_FEATURE_AARCH64 is present. There are not all that many banked registers, and they're easy to find by searching for regdefs that set bank_fieldoffsets: DACR, IFAR, DFAR, IFSR, DFSR, CSSELR, MAIR0, MAIR1, TPIDRURW, TPIDRURO, TPIDRPRW, TTBR0, TTBR1, TTBCR, TTBCR2, PAR, VBAR, SCTLR None of these do complicated things on reset, so having both an AArch64 view and an AArch32 view reset the same register state to the same value and migrate the same data twice is harmless. This is better than sometimes not migrating or resetting it at all. This changes the set of cpregs we will try to migrate for CPUs with ARM_FEATURE_V8 but not ARM_FEATURE_AARCH64, and is a migration break there. However, the only such CPUs are the qemu-system-aarch32 "max" CPU and AArch64 CPUs with "aarch64=3Doff". In an ideal world we would also not bother putting the S cpreg into the hashtable if the CPU is AArch32 without EL3 (i.e. it doesn't implement Secure state at all), because nothing will ever look up the S version of the register (access_secure_reg() always returns false). But that would be a migration compat break for those CPUs. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c3f607e6d6b..1b024adc703 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7787,18 +7787,33 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARM= CPRegInfo *r, if (state =3D=3D ARM_CP_STATE_AA32) { if (isbanked) { /* - * If the register is banked then we don't need to migrate= or - * reset the 32-bit instance in certain cases: + * If this is an AArch64 CPU then AArch32 cpregs are never + * banked, and if we put an NS version into the hash table + * it would never be accessed (compare the condition we te= st + * in access_secure_reg()). So drop it rather than adding = it. * - * 1) If the register has both 32-bit and 64-bit instances - * then we can count on the 64-bit instance taking care - * of the non-secure bank. - * 2) If ARMv8 is enabled then we can count on a 64-bit - * version taking care of the secure bank. This requir= es - * that separate 32 and 64-bit definitions are provided. + * Ideally we would also ignore the S banked register here + * for an AArch32 register without EL3; however, that would + * be a migration compatibility break for those CPUs, so we + * continue with having the cpregs in the hashtable. */ - if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || - (arm_feature(env, ARM_FEATURE_V8) && !ns)) { + if (!ns && arm_feature(env, ARM_FEATURE_AARCH64)) { + g_free(r); + return; + } + /* + * If the register is banked then we don't need to migrate= or + * reset the 32-bit instance if this is a STATE_BOTH regde= f. + * This is because we can know for certain that there's a + * 64-bit regdef that's using bank_fieldoffsets[1] as its + * fieldoffset, because the code that handles STATE_BOTH + * always registers it. In other situations either the NS + * or the S banked register might be aliased (architectura= lly + * or non-architecturally) to a 64-bit register, but it mi= ght + * not be. For those we must manually mark the alias in the + * regdef struct if we care. + */ + if (r->state =3D=3D ARM_CP_STATE_BOTH && ns) { r->type |=3D ARM_CP_ALIAS; } } else if ((secstate !=3D r->secure) && !ns) { --=20 2.43.0 From nobody Sat Sep 26 20:01:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788786256; cv=none; d=zohomail.com; s=zohoarc; b=nWGYNaqg0W0iD/oOIS0iUgltTeYYSEbnnllIkmkn0kSvVmlB/W0iGVJ0Es6eek9DJ15/1/n2/xpLlYYSSRxfR4AmfT1L21AYJLFwv0vzaYzPxZquwX4/9hTzDDnKVq6US5BQ1+q99HFMzmqVQaKLRFhYOYJvy4bIae7LNKPv0AQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788786256; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=MCXaA9JKSbsLcHED56ZOmYfMXgeBVruvAR+utYnVKl4=; b=nCrCE6bWUH8ktAxi3rojzzeX+Dmsvg3fwt4v6W6kHOfKzxWD2C5HoKp/L5bEx+hplOVxnokWG2fY6C4LWpACAmMTFUC6XPZW21xYqrcs0MHWGfkqAomgF3PCRjclX7fzvyDUubNU86zGarocyq7HvqccYJN4qBRXMixNhA27T0I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788786256028345.7268360255232; Mon, 7 Sep 2026 06:04:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3Yzj-0006Ci-VN; Mon, 07 Sep 2026 09:02:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3YzZ-00068L-18 for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:34 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x3YzW-000509-5R for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:32 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-49d0da752ffso13868555e9.3 for ; Mon, 07 Sep 2026 06:02:29 -0700 (PDT) Received: from lanath.. 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This is presumably in an expectation that some other AArch64 register will handle resetting the underlying state. However this isn't true for some of them: * TPIDRURO's S bank is in cp15.tpidruro_s and this isn't shared with any AArch64 register * TPIDRURW's S bank similarly is in cp15.tpidrurw_s, not shared with any AArch64 register Remove the use of arm_cp_reset_ignore here; this means that the state for the NS versions of these registers will be reset twice, but that is fine because it will always be to the same value (and the cp_reg_check_reset() code will assert if we introduce a bug where the AArch64 and AArch32 regs disagree about the reset value). For the MAIR0 and MAIR1 banked registers, doing nothing on reset is OK because they are backed by state that is always covered by the MAIR_EL1 and MAIR_EL3 AArch64 registers that will always be present if the AArch32 registers are. But it's not consistent with how we handle all the other banked regs, so drop it here too. Again, the cp_reg_check_reset() checks will catch any mismatches in what the reset value should be. The lack of reset-to-zero for the S banked versions of TPIDRURO and TPIDRURW is very unlikely to have had any guest visible consquences, because these registers are architecturally UNKNOWN at reset and so guest code should be initializing them itself regardless. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1b024adc703..f8185b201be 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1072,14 +1072,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair0_s), - offsetof(CPUARMState, cp15.mair0_ns) }, - .resetfn =3D arm_cp_reset_ignore }, + offsetof(CPUARMState, cp15.mair0_ns) }, }, { .name =3D "MAIR1", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair1_s), - offsetof(CPUARMState, cp15.mair1_ns) }, - .resetfn =3D arm_cp_reset_ignore }, + offsetof(CPUARMState, cp15.mair1_ns) }, }, { .name =3D "ISR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 0, .fgt =3D FGT_ISR_EL1, @@ -1136,8 +1134,7 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { .access =3D PL0_RW, .fgt =3D FGT_TPIDR_EL0, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrurw_s), - offsetoflow32(CPUARMState, cp15.tpidrurw_ns) = }, - .resetfn =3D arm_cp_reset_ignore }, + offsetoflow32(CPUARMState, cp15.tpidrurw_ns) = }, }, { .name =3D "TPIDRRO_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 3, .crn =3D 13, .crm =3D 0, .access =3D PL0_R | PL1_W, @@ -1148,8 +1145,7 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { .access =3D PL0_R | PL1_W, .fgt =3D FGT_TPIDRRO_EL0, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidruro_s), - offsetoflow32(CPUARMState, cp15.tpidruro_ns) = }, - .resetfn =3D arm_cp_reset_ignore }, + offsetoflow32(CPUARMState, cp15.tpidruro_ns) = }, }, { .name =3D "TPIDR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 4, .crn =3D 13, .crm =3D 0, .access =3D PL1_RW, --=20 2.43.0 From nobody Sat Sep 26 20:01:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788786255; cv=none; d=zohomail.com; s=zohoarc; b=lXaAmVy5l6+sQXCuR9lk0CX9hwfbm9IFLsHxQWWlwhTkzmPJFDoVUQP/HcMGnI5k1hCGsoGPH1aurBKq0o6YQUluiz9Zah6njXTxvNVT7hxbTzirBCaJE2aPXp2K3UHzc/AK0GaPy1eTYHcev2ToU467hBMIFqC17NUGZRq4XTQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788786255; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=V5GTzXoa5Bc18T0mL4aBCRmcSOeg2+fjb2ceHf6mrW4=; b=MhTaN7lgbIGy19QOHKFyla6nphesOp/MRRSNBUbJPUivHpROv649mwEGmBHjoU1DEyI0HPfZMHecpR+2HC7NWcnEtVCHqfVsyRn04n0B6FGLY9WClQoHa21GurpSeCzJEdnralXsrQRRvT94L2Ru9nhDuApGsgpaTanVi0ogtW8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788786255123985.6342317059338; Mon, 7 Sep 2026 06:04:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3Yzf-0006AP-7T; Mon, 07 Sep 2026 09:02:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3Yza-00068Q-Bq for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:34 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x3YzY-00050W-Nd for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:34 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-49cf4f81d86so27746325e9.2 for ; Mon, 07 Sep 2026 06:02:31 -0700 (PDT) Received: from lanath.. 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So we don't need to explicitly set ri->resetfn to arm_cp_reset_ignore() when we haven't defined a fieldoffset in the cpreg struct. Remove the setting of resetfn to arm_cp_reset_ignore in the handful of places where we were doing this unnecessarily. These are all timer registers, and doing this brings them in to line with the other timer registers (e.g. CNTPCT_EL0 has no resetfn, and now CNTPCT doesn't either). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f8185b201be..9d8f09f13b4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2209,7 +2209,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { { .name =3D "CNTPCT", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, .accessfn =3D gt_pct_access, - .readfn =3D gt_cnt_read, .resetfn =3D arm_cp_reset_ignore, + .readfn =3D gt_cnt_read, }, { .name =3D "CNTPCT_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 1, @@ -2219,7 +2219,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { { .name =3D "CNTVCT", .cp =3D 15, .crm =3D 14, .opc1 =3D 1, .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, .accessfn =3D gt_vct_access, - .readfn =3D gt_virt_cnt_read, .resetfn =3D arm_cp_reset_ignore, + .readfn =3D gt_virt_cnt_read, }, { .name =3D "CNTVCT_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 2, @@ -2310,7 +2310,7 @@ static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = =3D { { .name =3D "CNTVCTSS", .cp =3D 15, .crm =3D 14, .opc1 =3D 9, .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, .accessfn =3D gt_vct_access, - .readfn =3D gt_virt_cnt_read, .resetfn =3D arm_cp_reset_ignore, + .readfn =3D gt_virt_cnt_read, }, { .name =3D "CNTVCTSS_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 6, @@ -2320,7 +2320,7 @@ static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = =3D { { .name =3D "CNTPCTSS", .cp =3D 15, .crm =3D 14, .opc1 =3D 8, .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, .accessfn =3D gt_pct_access, - .readfn =3D gt_cnt_read, .resetfn =3D arm_cp_reset_ignore, + .readfn =3D gt_cnt_read, }, { .name =3D "CNTPCTSS_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 5, --=20 2.43.0 From nobody Sat Sep 26 20:01:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788786260; cv=none; d=zohomail.com; s=zohoarc; b=CTFRb4sNSdWih2ABdSZ1gxe5dtKZcI+6LUzpcX6yBWk2snNsKwzwUsFWC73cufdAck+imiGHvbYivw3Nk3uhFkjUFRAzBfEiMn8JLkDis7pKtu5ec59cBZzCpWUET+69hG0hbMYgLNFTaFuR9ucCSHHsPZ/CnDCkDfhz/CeDaio= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788786260; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xHOpqk1d77YmC+yqfEv/L5VjmCn6NlRjjzjSXGyDKdg=; b=PmxP9zEXRZEtFDQRoVjnRzm7U/FAUfn2g75N1u8UbjqstewnqeRT7JF6MAYWeFCLf+/oj/Zg1ZxTVfoa91OXhPlZP2XQCxe/8YL9b3OLZ+xBCHxfeJ/pKq+tpUT2E4gy+73UFLvopKtd4e5mqPrS2Dwc4/JoMxqU7gaHzf1P9r0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788786260941156.28539929164197; Mon, 7 Sep 2026 06:04:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3Yzu-0006FR-8U; Mon, 07 Sep 2026 09:02:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3Yzd-0006AB-9I for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:38 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x3YzY-00050u-OR for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:35 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-49b965570d7so41908705e9.0 for ; Mon, 07 Sep 2026 06:02:32 -0700 (PDT) Received: from lanath.. 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This doesn't matter for "is the register visible when it should be?", because currently all our AArch64 CPUs are VMSA. But it does matter for migration, because the DFSR definition in vmsa_pmsa_cp_reginfo[] is marked ARM_CP_ALIAS on the assumption that the migration of cp15.dfsr_ns will be handled by migrating esr_el[1], which is the same underlying field in the CPU state. Move ESR_EL1 to vmsa_pmsa_cp_reginfo[]; this will fix the lack of migration of DFSR for R-profile CPUs. This is a migration break for those CPUs, but none of them are used in versioned machine types. (The S banked DFSR is already migrated, because we register ESR_EL3 in el3_cp_reginfo[] if EL3 exists, regardless of whether we have VMSA or PMSA.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9d8f09f13b4..e4028e0eba6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2894,6 +2894,14 @@ static void vttbr_write(CPUARMState *env, const ARMC= PRegInfo *ri, } =20 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { + { .name =3D "ESR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .crn =3D 5, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_ESR_EL1, + .nv2_redirect_offset =3D 0x138 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 2, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 2, 0), + .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_= ALIAS, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dfsr_s), @@ -2918,14 +2926,6 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D= { }; =20 static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { - { .name =3D "ESR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .crn =3D 5, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .fgt =3D FGT_ESR_EL1, - .nv2_redirect_offset =3D 0x138 | NV2_REDIR_NV1, - .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 2, 0), - .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 2, 0), - .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, --=20 2.43.0 From nobody Sat Sep 26 20:01:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788786203; cv=none; d=zohomail.com; s=zohoarc; b=mSIu6nDiPNnoD+hDbtq7DS4acqrkH9Xjrmy5cQ/N6RmdiI0ZBy0GoiJFKZxAWtSxishY5Ek3wik1VSG5GRDTyVwWnjBNZyeDdPXdJcONh4kyWAFikIQjT2vEoz8Qncw63KSI8qNG1Gl/6dCnxAjGG+ZIp5I3dagC2dhdnQwnAkI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788786203; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xFia9cX6lxhGTb677k1n/vSwEH8f4LK/rrumre5hJP0=; b=N1w9TqwV9Yp/Qd2PRIg4co9Hd2rIwITVobBRwVGqayjS0yxmEVMWxRhfBhbF3v+yR/vRyaTWTdtC17+yRviXIZCYIfoDmjK/1tn5THgXwML3Du89xQmCcjhHlVm9phLVVkupTLMgwF+P91K7c7ettCUErEbprPePYyxn0KAor28= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788786203142564.9756322473336; Mon, 7 Sep 2026 06:03:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3Yzp-0006E8-VB; Mon, 07 Sep 2026 09:02:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3Yzd-0006A6-8y for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:38 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x3YzZ-00051N-TT for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:35 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-49d036e0e99so11417865e9.1 for ; Mon, 07 Sep 2026 06:02:33 -0700 (PDT) Received: from lanath.. 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For v8, the ATS insns and PAR are added to R-profile; although there are no page table descriptors to be long or short, the v8R PAR format is always long-descriptor style, so it makes more sense to set ARM_FEATURE_LPAE than not (and matches how we already return true from regime_using_lpae_format() for v8R PMSA). Our "feature X implies feature Y" code was only taking account of A-profile; adjust it so that for PMSA: * V8 implies V7VE, LPAE, V7, and VAPA (no change from currently) * V7 does not imply VAPA (new) (v8R wants V7VE because this implies things like the existence of ERET and the PMOVSSET insns.) This will stop us incorrectly exposing the PAR and ATS insns for v7R CPUs (and it will be a migration break on those CPUs, which is fine as none of them are usable with versioned machine types). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 77aa78f00e2..0432888ae34 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1501,7 +1501,11 @@ static void arm_cpu_propagate_feature_implications(A= RMCPU *cpu) set_feature(env, ARM_FEATURE_V7); } if (arm_feature(env, ARM_FEATURE_V7)) { - set_feature(env, ARM_FEATURE_VAPA); + /* VAPA appears in v7A, but not in R profile until v8R */ + if (arm_feature(env, ARM_FEATURE_V8) || + !arm_feature(env, ARM_FEATURE_PMSA)) { + set_feature(env, ARM_FEATURE_VAPA); + } set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_MPIDR); if (!arm_feature(env, ARM_FEATURE_M)) { --=20 2.43.0 From nobody Sat Sep 26 20:01:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788786207; cv=none; d=zohomail.com; s=zohoarc; b=DEcFxoiBgn1uwwsOF5cTZI2EwnUajxmkk6rkKgqZsIbxuE7TzwRRoVRSOKRGNvepGAgae1qjd4qAvwxrnVqzzRhpx8ySkn840fOTk8fqrPzDqkwc9vGlPymYT5hJxdHTRqVpufuwPqR/2LtoUG7hZSN6ZsGoTzR6YwIS+38PVFk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788786207; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PECZI3QBNqqLr6ePRzJzDKHA0mATh/ie5d5BiyY28gQ=; b=FDl8jtxuEVUlbHAO68OHFS3hWNSSodCyJgmFACUscJ2Zb5k87BPxheZ1q/jmC7Zx4uuk+8zl/typ8ZIFA2ZjS0K/6DlIBoNr0gPHCbJ+iKXKf5Gw8H9NrzeMWUbMqbQqVeSoV8eN8qR4i1dLfZhJ5ci32qFV6l98KDhpWZwsb98= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788786206960353.55992383897353; Mon, 7 Sep 2026 06:03:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3Yzz-0006Hg-CY; Mon, 07 Sep 2026 09:02:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3Yze-0006AU-DV for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:39 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x3Yzb-00051i-8r for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:38 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4998b5a63e2so42414515e9.1 for ; Mon, 07 Sep 2026 06:02:34 -0700 (PDT) Received: from lanath.. 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However, this means that we are also defining these registers as present in the Cortex-R52, which is a v8R PMSA CPU. v8R does define AMAIR0, AMAIR1 and the PAR, but does not have TTBR0 or TTBR1. Split the TTBR0 and TTBR1 definitions into a new lpae_vmsa_cp_reginfo which we only register when we have both LPAE and VMSA. This is a migration break for Cortex-R52 CPUs (which we don't use in any versioned machine type). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Detected because we ended up with the CP_ALIAS TTBR[01] registered but not the TTBR[01]_EL1 cpregs that handled the migration. --- target/arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index e4028e0eba6..b41e07e84b4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3098,6 +3098,9 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_64BIT, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.par_s), offsetof(CPUARMState, cp15.par_ns)} }, +}; + +static const ARMCPRegInfo lpae_vmsa_cp_reginfo[] =3D { { .name =3D "TTBR0", .cp =3D 15, .crm =3D 2, .opc1 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, @@ -7226,6 +7229,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, lpae_cp_reginfo); + if (!arm_feature(env, ARM_FEATURE_PMSA)) { + define_arm_cp_regs(cpu, lpae_vmsa_cp_reginfo); + } } if (cpu_isar_feature(aa32_jazelle, cpu)) { define_arm_cp_regs(cpu, jazelle_regs); --=20 2.43.0 From nobody Sat Sep 26 20:01:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788786243; cv=none; d=zohomail.com; s=zohoarc; b=V8zsg0K53KqMb+sx9qAMEFl4DN/uDVTlAXDbWf490BgRFfpH8dgY52f0PDAfYovKyWWb4m3ogPjvOikjnRH9Ll0dfgbcLVq+xEekWxElZpAuCdJKMgTTi13NDdCoFAJwx9SHwcA05uWFRX5HnhfoQDea4Bt/NwHfA1hf6HFmG+M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788786243; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iotEmPiMiYZmi7r+LxWWGWJQuCRVXl+ELdBcaukh1a8=; b=ho2PEjszQXRo0k2aP1+1T3//DZ4u3pu+16bH0vs3FCvd36G2poiEFXthJJ7T52D8R+v9ANkeA/AFfqEkzwObOk+138h1tN4MXfQE/SnKBilFPcrHh5/1yEd9Y3uccxXoE9kIlkkDu+5smtf66x1PZIzhoCtyVfBsVnhHn69GGVI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788786243049132.97233368689183; Mon, 7 Sep 2026 06:04:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x3Yzy-0006HA-PM; Mon, 07 Sep 2026 09:02:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x3Yzg-0006Bj-0f for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:41 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x3Yzc-000523-TX for qemu-devel@nongnu.org; Mon, 07 Sep 2026 09:02:39 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-49ccfae359fso31382085e9.3 for ; Mon, 07 Sep 2026 06:02:36 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cee60bae6sm468589935e9.9.2026.09.07.06.02.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 06:02:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788786155; x=1789390955; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=iotEmPiMiYZmi7r+LxWWGWJQuCRVXl+ELdBcaukh1a8=; b=WT2vBRizlVP3A8qU/PqNmC3jhDqigCwjOuMLlNDgwjNosrOnnv/0LG2JCf9eJ1kLO3 GyDV10KwKCQ1dYOVZ5Rcb0eeYQgjpOTBda48l6n/l3HCjHJk3mXww+/yT1dapB/zC0Km Y58njGQ5dhtW0sij6leicw3ooXW4UXLMXhYbDJPssvYRqTnsObv8tXi+Xo2HNP7CR0Os kCp5U4TmSYixSnMF0nuXbilMxCw2QvlarZoWn0hBMM2NrZGiFGrlFn801N6hvB0IQh0J tnTTndvyfs+8EFQ68dTdbHoV85JW3r9RXQNfjsFkp7VSyRcsLGkxwz1axSQDlAdVPoUE qulQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788786155; x=1789390955; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=iotEmPiMiYZmi7r+LxWWGWJQuCRVXl+ELdBcaukh1a8=; b=gFMnRi8BWmnPuIIsthRTGHBRL2GJVBnObFomr605CTxBbBgoKcXS/WZaYRnFW9ihS/ /w97V82Uupbp/lTImWUm4ksZCWi0HTXLup17xs8wd5HlAHw+o2n4guHwW2TBMpvPLtmV mrbn2iZ5B1rzoU6BgFeH9ERc8OMI4R0YZMFtv+6OfURg7DjuUl/atqc43eGLaJG9L2e+ oeHE5ejfBS22cvlsjRbRrQVXSEaIpKdE0wLbl8oe4nJBoLR8QPw07lPybvmz45+BXQoc oMkTAGBiR3TVSynhssUkhrDxWQ1WE+ol6ZfziDdSClgAw87Q5si+vM2F3wfLWTCfrunO bsMg== X-Forwarded-Encrypted: i=1; AKwUvBwSp6woocviNUR80vVfX+oTShvCUfNBjDqS0uCxOQJ5wvFKrrDvqJcjbz+RHt3AwG9DLBu+xTaFEeTI@nongnu.org X-Gm-Message-State: AFuF++mzxKbSYbvcOAZjKHUC/vJAG2ih0OEuiYgv6LqYYI8XFXm2o/vp jhK4jPS48fLWliYNx1zvFHGhHMLLYPIpeGf5F1OdNl8K4y9PxDBtwN6CppOHrb5D8zHmP8qmBRC y/N6Vagw= X-Gm-Gg: AYBFou1etJs1ItxQ9iWlkRUKu/L9nlXjzIsdFoTh2w2//GZn0NaqKUx5vWh7R/Uz43J Y5dETS/aEe19v8u3+pq1Mq22O0qWsbaHnuV4lAKJTS35ayblitl4vz2fJJ4HWO62NSgnqQ1M7Aq ucAcNk7UordCO2bPK3A0Ek+cRzMRL9MmmLWnkqvNp4u4zK3qyB30j06RDykThCjrK3/kMrI5grt qWANy4pR9119qjl81UzL+Fv+1Ua2jxxuN6dtcONCG+1N8lX6dHt8k5GE7rwwe0AK1EAFT1/eDjB hya3HBk/uBYl6+E0sDTmODSzmzdN4FsyWCPmDQuU3/6F2tfopJTx0B1B5DXNLaGfGCYJfu0Vly3 i2WWb0IvHSk/isUPujwcg/TI0yx7rxq24US4gEVw3bHVfPM9raNbenPNpFKOHfrN5+8SmxNQmHp g7VnX82krsDyi4bn5IdFAha7T/MDftsQ97Ar4HkSIvXLS1STWnrWGacMuLlh4JfNlqkHl7yqVzF 4U7wtFnWLSZ1/AzNAUecA+x5KgP1+AYMHdq5+Af3tgcRlb5TqvVh83i6o2C3NdEoBY/TIWqfh+P 9HzI X-Received: by 2002:a05:600c:6088:b0:49c:fc6c:be15 with SMTP id 5b1f17b1804b1-49cfc6cc100mr200291415e9.27.1788786154889; Mon, 07 Sep 2026 06:02:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Tao Ding Subject: [PATCH 8/8] target/arm: Add a debug check that all sysregs are migrated Date: Mon, 7 Sep 2026 14:02:23 +0100 Message-ID: <20260907130223.3148989-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260907130223.3148989-1-peter.maydell@linaro.org> References: <20260907130223.3148989-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788786246941154100 Content-Type: text/plain; charset="utf-8" We mark some sysregs with ARM_CP_ALIAS (either manually or automatically) to indicate that they are accessing underlying guest CPU state whose migration and reset is handled by some other register. (For example, typically we make the 32-bit view of a register an alias and handle migration for the 64-bit view.) Add a debug check that we actually do handle the migration elsewhere: for every sysreg in the hashtable (i.e. which might be visible to the guest), check that some register in the migration list has a field offset that matches. This isn't perfect but it can catch some bugs. In particular it did fire for the various secure banked registers that we were not migrating before the fixes in the previous patches. Because the check is more of a debugging aid than something I'm confident will never produce a false-positive report for some niche combination of CPU and machine options, we only do it for debug builds, and make it a warning printed to the user rather than an assertion failure. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 121 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index b41e07e84b4..82e7a20bdb6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -230,6 +230,125 @@ bool write_list_to_cpustate(ARMCPU *cpu) return ok; } =20 +#ifdef CONFIG_DEBUG_TCG +/* Data to pass through to check_cpreg() */ +typedef struct CheckCPRegData { + ARMCPU *cpu; + bool warned; +} CheckCPRegData; + +static void check_cpreg(gpointer key, gpointer value, gpointer opaque) +{ + CheckCPRegData *data =3D opaque; + ARMCPU *cpu =3D data->cpu; + CPUARMState *env =3D &cpu->env; + bool match =3D false; + const ARMCPRegInfo *ri =3D value; + + if ((ri->type & (ARM_CP_NO_RAW | ARM_CP_CONST)) || + ri->fieldoffset =3D=3D 0) { + return; + } + + /* + * If we don't have EL3 then the guest can't get at S-only + * registers even if they're in the hashtable. This avoids + * false-positive complaints about e.g. TTBCR_S and DFSR_S: they + * are migrated via ESR_EL3 and TCR_EL3, but we only register those + * _EL3 regs if ARM_FEATURE_EL3. + */ + if (ri->secure =3D=3D ARM_CP_SECSTATE_S && !arm_feature(env, ARM_FEATU= RE_EL3)) { + return; + } + + /* + * Some special cases for sysregs that are backed by fields that we + * migrate in the main vmstate, not the cpregs array. + */ + if (ri->fieldoffset >=3D offsetof(CPUARMState, banked_spsr[BANK_USRSYS= ]) && + ri->fieldoffset <=3D offsetof(CPUARMState, banked_spsr[BANK_MON]))= { + return; + } + if (ri->fieldoffset >=3D offsetof(CPUARMState, elr_el[0]) && + ri->fieldoffset <=3D offsetof(CPUARMState, elr_el[3])) { + return; + } + if (ri->fieldoffset >=3D offsetof(CPUARMState, sp_el[0]) && + ri->fieldoffset <=3D offsetof(CPUARMState, sp_el[3])) { + return; + } + if (ri->fieldoffset =3D=3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPE= XC])) { + return; + } + + for (int i =3D 0; i < cpu->cpreg_array_len; i++) { + uint32_t other_regidx =3D kvm_to_cpreg_id(cpu->cpreg_indexes[i]); + const ARMCPRegInfo *other_ri =3D get_arm_cp_reginfo(cpu->cp_regs, + other_regidx); + + if (!other_ri || (other_ri->type & (ARM_CP_NO_RAW | ARM_CP_CONST))= || + other_ri->fieldoffset =3D=3D 0) { + continue; + } + + /* + * If the field offsets match exactly, or this 32-bit cpreg + * is in the second half of a 64-bit field, consider it to + * be handled. + */ + if (ri->fieldoffset =3D=3D other_ri->fieldoffset || + (cpreg_field_type(ri) =3D=3D MO_32 && + cpreg_field_type(other_ri) =3D=3D MO_64 && + ri->fieldoffset =3D=3D other_ri->fieldoffset + 4)) { + match =3D true; + break; + } + } + if (!match) { + warn_report("check_cpreg: no migration entry found for %s", ri->na= me); + data->warned =3D true; + } +} +#endif /* CONFIG_DEBUG_TCG */ + +static void arm_check_cpreg_coverage(ARMCPU *cpu) +{ + /* + * Try to catch bugs where we don't actually migrate a cpreg. + * Specifically, here we check that every cpreg in the hash table + * (and thus potentially visible to the guest) which specifies + * a fieldoffset has some entry in the cpreg_indexes[] array that + * handles that same fieldoffset. + * The typical bug that will be flagged up here is if a register + * is marked as an alias of something else, but there isn't actually + * anything else that handles the field. + * + * Note that the checks are more of a best-effort, are somewhat + * expensive at O(n^2) in the number of sysregs, and need some + * cases to be excluded where the sysreg data isn't migrated via + * the cpreg arrays. So we only do them in --enable-debug builds, + * to avoid potentially causing problems for users. + */ +#ifdef CONFIG_DEBUG_TCG + CheckCPRegData data =3D { + .cpu =3D cpu, + .warned =3D false, + }; + + /* We'll only use the cpregs for migration with TCG */ + if (!tcg_enabled()) { + return; + } + g_hash_table_foreach(cpu->cp_regs, check_cpreg, &data); + + if (data.warned) { + error_printf("check_cpreg errors are a QEMU bug that may cause " + "migration to fail. Please report this with the full " + "QEMU command line and version.\n"); + } +#endif +} + static void add_cpreg_to_list(gpointer key, gpointer value, gpointer opaqu= e) { ARMCPU *cpu =3D opaque; @@ -281,6 +400,8 @@ void arm_init_cpreg_list(ARMCPU *cpu) if (arraylen) { qsort(cpu->cpreg_indexes, arraylen, sizeof(uint64_t), compare_u64); } + + arm_check_cpreg_coverage(cpu); } =20 bool arm_pan_enabled(CPUARMState *env) --=20 2.43.0