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Mon, 07 Sep 2026 17:37:45 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1788773867; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=vIgHjORxejL1Lv+F0GBsY0ihEjHzMkne0LldY+ERvUE=; b=Px4Ktf9LnurPblhX9B3HzExetGAOStDUYDc5u57S4V08Frbw1Yfr1CKU14XJR6TP5Nl23NHCo1rOvJlzJFmPjS+nL2/fwDkZsnTmSvSNsVSrJxrGM0bMu9Ssyt+MXncbiL5mxpqmrUWbcSxs4TBhMjXPQ49eTM5E76Dl10VkZcg= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R131e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037026112; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=19; SR=0; TI=SMTPD_---0XATXGy1_1788773865; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH v6 1/6] hw/riscv/virt: Add CXL support to the RISC-V virt machine Date: Mon, 7 Sep 2026 17:37:28 +0800 Message-ID: <20260907093735.2753-2-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260907093735.2753-1-cp0613@linux.alibaba.com> References: <20260907093735.2753-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.113 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Enable CXL support on the RISC-V virt machine following the same approach used by the ARM virt machine: - Add PXB and ACPI_CXL Kconfig selections - Add CXLState and PCIBus pointer to RISCVVirtState - Register CXL machine properties via cxl_machine_init() - Create CXL host register region above the PCIe high MMIO region - Call cxl_hook_up_pxb_registers() and cxl_fmws_link_targets() at machine_done time - Map Fixed Memory Windows above the CXL host register region - Add ACPI0017 device in DSDT and build CEDT table in virt-acpi-build.c Reviewed-by: Junjie Cao Tested-by: Junjie Cao Signed-off-by: Chen Pei Reviewed-by: Chao Liu Reviewed-by: Jonathan Cameron Reviewed-by: Michael S. Tsirkin Reviewed-by: Nutty Liu --- hw/riscv/Kconfig | 2 ++ hw/riscv/virt-acpi-build.c | 20 ++++++++++++++++ hw/riscv/virt.c | 47 ++++++++++++++++++++++++++++++++++---- include/hw/riscv/virt.h | 3 +++ 4 files changed, 68 insertions(+), 4 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index d06ac26648..c2f8c5d2da 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -66,8 +66,10 @@ config RISCV_VIRT select VIRTIO_MMIO select FW_CFG_DMA select PLATFORM_BUS + select PXB select ACPI select ACPI_PCI + select ACPI_CXL =20 config SHAKTI_C bool diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 8e516ec114..2be8c6d572 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -29,12 +29,16 @@ #include "hw/acpi/aml-build.h" #include "hw/acpi/pci.h" #include "hw/acpi/utils.h" +#include "hw/acpi/cxl.h" #include "hw/intc/riscv_aclint.h" #include "hw/nvram/fw_cfg_acpi.h" #include "hw/pci-host/gpex.h" +#include "hw/pci/pci_bus.h" #include "hw/riscv/virt.h" #include "hw/riscv/numa.h" #include "hw/virtio/virtio-acpi.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "kvm/kvm_riscv.h" #include "migration/vmstate.h" #include "qapi/error.h" @@ -518,6 +522,17 @@ static void build_dsdt(GArray *table_data, acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + s->num_sources * 2); } =20 + if (s->cxl_devices_state.is_enabled) { + Aml *cxl_dev =3D aml_device("CXLM"); + aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + Aml *method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0x0B))); + aml_append(cxl_dev, method); + build_cxl_dsm_method(cxl_dev); + + aml_append(scope, cxl_dev); + } + aml_append(dsdt, scope); =20 /* copy AML table into ACPI tables blob and patch header there */ @@ -925,6 +940,11 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBui= ldTables *tables) s->oem_table_id); } =20 + if (s->cxl_devices_state.is_enabled) { + cxl_build_cedt(table_offsets, tables_blob, tables->linker, + s->oem_id, s->oem_table_id, &s->cxl_devices_state); + } + if (ms->numa_state->num_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, s); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f3a1cc5ba3..70090ca70a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -56,6 +56,8 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "hw/acpi/aml-build.h" #include "qapi/qapi-visit-common.h" #include "hw/virtio/virtio-iommu.h" @@ -540,6 +542,29 @@ static void create_fdt(RISCVVirtState *s) create_fdt_pmu(s); } =20 +static void cxl_host_state_init(RISCVVirtState *s) +{ + MemoryRegion *sysmem =3D get_system_memory(); + MemoryRegion *mr =3D &s->cxl_devices_state.host_mr; + hwaddr base; + + if (!s->cxl_devices_state.is_enabled) { + return; + } + + base =3D virt_high_pcie_memmap.base + virt_high_pcie_memmap.size; + base =3D ROUND_UP(base, 64 * KiB); + + memory_region_init(mr, OBJECT(s), "cxl_host_reg", 64 * KiB * 16); + memory_region_add_subregion(sysmem, base, mr); + + /* Map the Fixed Memory Windows above the CXL host register region. */ + base +=3D memory_region_size(mr); + base =3D ROUND_UP(base, 256 * MiB); + cxl_fmws_set_memmap(base, UINT64_MAX); + cxl_fmws_update_mmio(); +} + static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) { FWCfgState *fw_cfg; @@ -625,6 +650,13 @@ static void virt_machine_done(Notifier *notifier, void= *data) BlockBackend *pflash_blk0; RISCVBootInfo boot_info; =20 + cxl_hook_up_pxb_registers(s->pci_bus, &s->cxl_devices_state, + &error_fatal); + + if (s->cxl_devices_state.is_enabled) { + cxl_fmws_link_targets(&error_fatal); + } + /* * An user provided dtb must include everything, including * dynamic sysbus devices. Our FDT needs to be finalized. @@ -716,6 +748,7 @@ static void virt_machine_init(MachineState *machine) MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; + DeviceState *gpex_dev; int i, base_hartid, hart_count; int socket_count =3D riscv_socket_count(machine); =20 @@ -871,6 +904,8 @@ static void virt_machine_init(MachineState *machine) ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.siz= e); } =20 + cxl_host_state_init(s); + /* register system main memory (actual RAM) */ memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base, machine->ram); @@ -898,10 +933,12 @@ static void virt_machine_init(MachineState *machine) qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); } =20 - riscv_gpex_pcie_init(system_memory, pcie_irqchip, - &s->memmap[VIRT_PCIE_ECAM], &s->memmap[VIRT_PCIE_MMIO], - &virt_high_pcie_memmap, &s->memmap[VIRT_PCIE_PIO], - PCIE_IRQ); + gpex_dev =3D riscv_gpex_pcie_init(system_memory, pcie_irqchip, + &s->memmap[VIRT_PCIE_ECAM], + &s->memmap[VIRT_PCIE_MMIO], + &virt_high_pcie_memmap, + &s->memmap[VIRT_PCIE_PIO], PCIE_IRQ); + s->pci_bus =3D PCI_HOST_BRIDGE(gpex_dev)->bus; =20 s->platform_bus_dev =3D riscv_create_platform_bus(mmio_irqchip, &s->memmap[VIRT_PLATFORM_BUS], VIRT_PLATFORM_BUS_IRQ, @@ -972,6 +1009,8 @@ static void virt_machine_instance_init(Object *obj) s->acpi =3D ON_OFF_AUTO_AUTO; s->iommu_sys =3D ON_OFF_AUTO_AUTO; s->num_sources =3D VIRT_IRQCHIP_NUM_SOURCES; + + cxl_machine_init(obj, &s->cxl_devices_state); } =20 static char *virt_get_aia_guests(Object *obj, Error **errp) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index e516898f9a..a7b74d10c6 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -24,6 +24,7 @@ #include "hw/core/sysbus.h" #include "hw/block/flash.h" #include "hw/intc/riscv_imsic.h" +#include "hw/cxl/cxl.h" =20 #define VIRT_CPUS_MAX_BITS 9 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) @@ -66,6 +67,8 @@ struct RISCVVirtState { OnOffAuto iommu_sys; uint16_t pci_iommu_bdf; uint16_t num_sources; + CXLState cxl_devices_state; + PCIBus *pci_bus; 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Mon, 07 Sep 2026 17:37:46 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1788773867; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=zYZIRnVm4EVgjOeiEy+OXbDkRrDL+s/FNTgJFXZLnu0=; b=O0w+lK8YUhmL6O2USdQkNoBipP/uman2Bs/oe9n5ralju+xKnvdUs2Dxq0StdcqcMkB0whZCEB2lGXEKhD2+Q29mGC4fUS4vnGtfP9EliPI8CYfmB/wHBKd7ovT1/zGNgBNFjcVE6z83vQCHiK47Em4TkOV5WAp6a1E4B+yKDBA= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R181e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam011083073210; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=20; SR=0; TI=SMTPD_---0XATXGyA_1788773866; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, Sunil V L Subject: [PATCH v6 2/6] hw/riscv/virt-acpi-build: Add _DEP to ACPI0017 for CXL host bridge dependency Date: Mon, 7 Sep 2026 17:37:29 +0800 Message-ID: <20260907093735.2753-3-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260907093735.2753-1-cp0613@linux.alibaba.com> References: <20260907093735.2753-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.97 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" On RISC-V QEMU virt platform with CXL enabled, the probe ordering of acpi_pci_root (ACPI0016) and cxl_acpi (ACPI0017) is not guaranteed. If cxl_acpi probes before acpi_pci_root has attached the CXL host bridges, the CXL port topology will be incomplete because to_cxl_host_bridge() silently skips devices whose PCI root is not yet ready. Add a _DEP object to the ACPI0017 device in the DSDT, declaring its dependency on the ACPI0016 CXL host bridge devices. This tells the OS to defer ACPI0017 enumeration until all ACPI0016 devices have been attached by acpi_pci_root. This pairs with two kernel commits, both merged in v7.2: bf5418a5fe63 ("ACPI: scan: Honor _DEP for ACPI0016 PCI/CXL host bridge") makes the ACPI core defer ACPI0017 enumeration while its _DEP targets are unattached, and 3a59c3b772e5 ("ACPI: PCI: Clear _DEP dependencies after PCI root bridge attach") clears the dependency from acpi_pci_root_add() once the host bridge is attached. Note on kernel compatibility: this is a "new QEMU feature requires a sufficiently new kernel" situation. Kernels that process _DEP but lack the acpi_dev_clear_dependencies() call will leave the CXLM device deferred, so CXL memory is unusable there; kernels old enough to ignore _DEP entirely behave exactly as before this change. In neither case is existing (non-CXL) PCIe affected. The resulting DSDT fragment (iasl -d output) for a single CXL host bridge at bus 0x0C looks like: Device (CXLM) { Name (_HID, "ACPI0017") Name (_DEP, Package (0x01) { \_SB.PC0C }) Method (_STA, 0, NotSerialized) { Return (0x0B) } ... } Reviewed-by: Sunil V L Reviewed-by: Junjie Cao Signed-off-by: Chen Pei Reviewed-by: Jonathan Cameron Reviewed-by: Michael S. Tsirkin --- hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 2be8c6d572..e1beb2068d 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -525,6 +525,38 @@ static void build_dsdt(GArray *table_data, if (s->cxl_devices_state.is_enabled) { Aml *cxl_dev =3D aml_device("CXLM"); aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + + /* + * Declare a _DEP on every ACPI0016 CXL host bridge so the OS + * defers ACPI0017 enumeration until acpi_pci_root has attached + * the CXL host bridges. Without this, cxl_acpi may probe before + * to_cxl_host_bridge() can resolve the PCI root and the CXL + * port topology comes up empty. + */ + if (s->pci_bus) { + PCIBus *bus; + uint32_t num_cxl_hbs =3D 0; + + QLIST_FOREACH(bus, &s->pci_bus->child, sibling) { + if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) { + num_cxl_hbs++; + } + } + + if (num_cxl_hbs > 0) { + Aml *dep_pkg =3D aml_package(num_cxl_hbs); + + QLIST_FOREACH(bus, &s->pci_bus->child, sibling) { + if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) { + aml_append(dep_pkg, + aml_name("\\_SB.PC%.02X", + pci_bus_num(bus))); + } + } + aml_append(cxl_dev, aml_name_decl("_DEP", dep_pkg)); + } + } + Aml *method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); aml_append(method, aml_return(aml_int(0x0B))); aml_append(cxl_dev, method); --=20 2.50.1 From nobody Sat Sep 26 20:00:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1788773868; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=yc5KhGVgl+0DuLZrt8gjwOQ2YjB/WdP3UupIKvk84hk=; b=XK1swFaiA4Bqd9F0URePupAZwuTPPJul/PzWxDTuJEcdWcwrIEycYKUZ7o5jR8y4WfvzGZNVVCK2eMzEsWPlFucPyAUrftwQVPcY7BMoR95u6GUvpAoittRNvza9d0nvGTxIymols/9vdlAOXzAK3ylFwSOktWjEvRcO8e6Shb8= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R251e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045133197; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=19; SR=0; TI=SMTPD_---0XATXGyL_1788773867; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH v6 3/6] hw/riscv/virt: Advertise the CXL host bridge to firmware via extra-pci-roots Date: Mon, 7 Sep 2026 17:37:30 +0800 Message-ID: <20260907093735.2753-4-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260907093735.2753-1-cp0613@linux.alibaba.com> References: <20260907093735.2753-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.111 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The pxb-cxl expander bridge presents as a class 0x0600 host bridge with a type-0 header, so EDK2's PciBusDxe never recurses into it and never assigns the CXL root port a memory window or bus numbers. As a result build_crs() produces an empty _CRS for the ACPI0016 host bridge and the CXL devices behind it are not enumerated by the OS. Advertise the pxb-cxl expander root buses to firmware via the etc/extra-pci-roots fw_cfg file, the same way arm/virt and x86 do, by calling pci_bus_add_fw_cfg_extra_pci_roots() from virt_machine_done(). EDK2's PciBusDxe then enumerates behind the CXL host bridge and assigns the root-port window and bus numbers. The ACPI tables are rebuilt when the guest reads them (after that firmware enumeration), so build_crs() then emits a correct _CRS for the ACPI0016 host bridge. The call is made unconditionally, in line with arm/virt, pc and hppa, so plain pxb-pcie expander bridges, which likewise depend on etc/extra-pci-roots, are advertised as well; the generator simply returns nothing when there is no expander root bus. This approach also scales to multiple pxb-cxl host bridges (each gets its own window from the shared aperture) and lets firmware size the window to what is actually behind the bridge, rather than reserving a fixed carve-out. Verified by booting an RVA22 guest: the CXL root port and Type3 device enumerate, and 'cxl enable-memdev' / 'cxl create-region' / 'daxctl online-memory' bring the CXL memory online as system RAM. Reviewed-by: Junjie Cao Tested-by: Junjie Cao Signed-off-by: Chen Pei Reviewed-by: Jonathan Cameron Reviewed-by: Michael S. Tsirkin --- hw/riscv/virt.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 70090ca70a..885020af83 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -657,6 +657,15 @@ static void virt_machine_done(Notifier *notifier, void= *data) cxl_fmws_link_targets(&error_fatal); } =20 + /* + * Advertise the pxb/pxb-cxl expander root buses to firmware so that + * it enumerates behind them and assigns bus numbers and windows. For + * the CXL host bridges, build_crs() then builds the ACPI0016 _CRS + * from the resulting state when the guest reads the ACPI tables. + * This is a no-op without any expander root bus. + */ + pci_bus_add_fw_cfg_extra_pci_roots(s->fw_cfg, s->pci_bus, &error_abort= ); + /* * An user provided dtb must include everything, including * dynamic sysbus devices. Our FDT needs to be finalized. --=20 2.50.1 From nobody Sat Sep 26 20:00:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1788773980; cv=none; d=zohomail.com; s=zohoarc; b=cJdYNaJ3aKpt8mwhAxcTZDyCAkOlYino5IJGPbBI7osM0WNe4tgZpkma+zA//k5mUtoo70W2LzRU+Sz1L5h/HNhdEwWlB2lSYDpWaPqxmt2enhh1SZtqfpHlYWJIQuE9DwMBjUM/zZsBLcc2XJdUc5qsfHV1ReFh2SBEyucvHJc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788773980; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WmhvmGPUNy77AIuahmD4mTp3kq8V1wWxZtZ1BZHb17w=; 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Mon, 07 Sep 2026 05:38:07 -0400 Received: from DESKTOP-S9E58SO.localdomain(mailfrom:cp0613@linux.alibaba.com fp:SMTPD_---0XATXGyV_1788773868 cluster:ay36) by smtp.aliyun-inc.com; Mon, 07 Sep 2026 17:37:48 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1788773869; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=WmhvmGPUNy77AIuahmD4mTp3kq8V1wWxZtZ1BZHb17w=; b=fj73P8VCeWdMKFczN+RGsI14f12xXulEzBpZWQPreamgfwNaQN56aHM6wJlw51zsIANnuW5kivISn7vR7ZrYwFL8NYC9F5trpczJrDcDdbNJfy/jsUimiHTBMfy4QK4JocyzPx2G+alDTb0h8VCiyV7XqCO4e0004qrnhV33bk0= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R501e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033032089153; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=19; SR=0; TI=SMTPD_---0XATXGyV_1788773868; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH v6 4/6] tests/qtest: Prepare golden files for the RISC-V CXL ACPI test Date: Mon, 7 Sep 2026 17:37:31 +0800 Message-ID: <20260907093735.2753-5-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260907093735.2753-1-cp0613@linux.alibaba.com> References: <20260907093735.2753-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.124 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Add empty DSDT.cxl and CEDT.cxl golden files and list them in bios-tables-test-allowed-diff.h, in preparation for the RISC-V CXL bios-tables test added in the following patch. The populated golden master binaries are committed separately in a final patch, following the bios-tables-test update process. Reviewed-by: Junjie Cao Signed-off-by: Chen Pei Reviewed-by: Jonathan Cameron Reviewed-by: Michael S. Tsirkin --- tests/data/acpi/riscv64/virt/CEDT.cxl | 0 tests/data/acpi/riscv64/virt/DSDT.cxl | 0 tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 3 files changed, 2 insertions(+) create mode 100644 tests/data/acpi/riscv64/virt/CEDT.cxl create mode 100644 tests/data/acpi/riscv64/virt/DSDT.cxl diff --git a/tests/data/acpi/riscv64/virt/CEDT.cxl b/tests/data/acpi/riscv6= 4/virt/CEDT.cxl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/riscv64/virt/DSDT.cxl b/tests/data/acpi/riscv6= 4/virt/DSDT.cxl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..c05fb697a5 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"riscv64/virt/DSDT.cxl", +"riscv64/virt/CEDT.cxl", --=20 2.50.1 From nobody Sat Sep 26 20:00:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Add test_acpi_riscv64_virt_tcg_cxl() to verify that enabling CXL on the RISC-V virt machine produces correct ACPI tables, including the ACPI0017 CXLM device with _DEP in the DSDT and the CEDT table. The test boots with cxl=3Don, one pxb-cxl bus (bus_nr=3D12), a CXL root port, a cxl-type3 device and a fixed memory window, mirroring the existing x86 q35 CXL test pattern. Since pxb-cxl is a root bus, using -cdrom causes QEMU to auto-plug the cdrom drive into pxb-cxl, triggering "Only PCI/PCIe bridges can be plugged into pxb-cxl". The ISO is instead attached explicitly via a virtio-scsi-pci controller on pcie.0, following the same approach as test_acpi_aarch64_virt_tcg_pxb(). Acked-by: Alistair Francis Reviewed-by: Junjie Cao Tested-by: Junjie Cao Signed-off-by: Chen Pei Reviewed-by: Jonathan Cameron Reviewed-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test.c | 54 ++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index f6dfa4131b..41c0d6a295 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -2214,6 +2214,56 @@ static void test_acpi_riscv64_virt_tcg(void) free_test_data(&data); } =20 +#ifdef CONFIG_POSIX +static void test_acpi_riscv64_virt_tcg_cxl(void) +{ + gchar *tmp_path =3D g_dir_make_tmp("qemu-test-cxl.XXXXXX", NULL); + gchar *params; + + test_data data =3D { + .machine =3D "virt", + .arch =3D "riscv64", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-riscv64-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-riscv64-vars.fd", + .ram_start =3D 0x80000000ULL, + .scan_len =3D 128ULL * MiB, + .variant =3D ".cxl", + }; + + /* + * While using -cdrom, the cdrom would auto-plug into pxb-cxl because + * its bus is also a root bus, triggering "Only PCI/PCIe bridges can be + * plugged into pxb-cxl". Attach the ISO explicitly to a scsi control= ler + * on pcie.0 instead, following the same pattern as + * test_acpi_aarch64_virt_tcg_pxb(). + */ + params =3D g_strdup_printf("-cpu rva22s64" + " -machine cxl=3Don" + " -device pcie-root-port,chassis=3D1,id=3Dpci= .1,bus=3Dpcie.0" + " -device virtio-scsi-pci,id=3Dscsi0,bus=3Dpc= i.1" + " -drive file=3Dtests/data/uefi-boot-images/" + "bios-tables-test.riscv64.iso.qcow2," + "if=3Dnone,media=3Dcdrom,id=3Ddrive-scsi0-0-0= -1,readonly=3Don" + " -device scsi-cd,bus=3Dscsi0.0,scsi-id=3D0," + "drive=3Ddrive-scsi0-0-0-1,id=3Dscsi0-0-0-1,b= ootindex=3D1" + " -object memory-backend-file,id=3Dcxl-mem1,m= em-path=3D%s,size=3D256M" + " -object memory-backend-file,id=3Dlsa1,mem-p= ath=3D%s,size=3D256M" + " -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id= =3Dcxl.1" + " -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Drp= 1,chassis=3D0,slot=3D2" + " -device cxl-type3,bus=3Drp1,persistent-memd= ev=3Dcxl-mem1,lsa=3Dlsa1" + " -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.si= ze=3D4G," + "cxl-fmw.0.interleave-granularity=3D8k", + tmp_path, tmp_path); + test_acpi_one(params, &data); + + g_free(params); + g_assert(g_rmdir(tmp_path) =3D=3D 0); + g_free(tmp_path); + free_test_data(&data); +} +#endif /* CONFIG_POSIX */ + static void test_acpi_aarch64_virt_tcg(void) { test_data data =3D { @@ -2971,6 +3021,10 @@ int main(int argc, char *argv[]) test_acpi_riscv64_virt_tcg_numamem); qtest_add_func("acpi/virt/acpispcr", test_acpi_riscv64_virt_tcg_acpi_spcr); +#ifdef CONFIG_POSIX + qtest_add_func("acpi/virt/cxl", + test_acpi_riscv64_virt_tcg_cxl); +#endif } } else if (strcmp(arch, "loongarch64") =3D=3D 0) { if (has_tcg && qtest_has_machine("virt")) { --=20 2.50.1 From nobody Sat Sep 26 20:00:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1788773941; cv=none; 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charset="utf-8" Populate the DSDT.cxl and CEDT.cxl golden master binaries for the RISC-V CXL bios-tables test and empty bios-tables-test-allowed-diff.h, following the bios-tables-test update process. The expected AML added by this series is: DSDT.cxl: Device (PC0C) // ACPI0016 CXL host bridge (pxb-cxl, bus 0x0C) Name (_CRS, ResourceTemplate () { DWordMemory (... 0x40400000 .. 0x405FFFFF ...) // 32-bit MMIO QWordMemory (... 0x400100000 .. 0x40010FFFF ...) // 64-bit MMIO WordBusNumber (... 0x000C .. 0x000D ...) }) Method (_OSC, ...) // PCI host bridge + CXL UUIDs Device (CXLM) // ACPI0017 CXL memory controller Name (_HID, "ACPI0017") Name (_DEP, Package () { \_SB.PC0C }) Method (_STA, ...) / Method (_DSM, ...) CEDT.cxl: CHBS : CXL Host Bridge Structure, Register base 0x800000000 CFMWS: CXL Fixed Memory Window, base 0x810000000, size 4G Reviewed-by: Junjie Cao Tested-by: Junjie Cao Signed-off-by: Chen Pei Reviewed-by: Michael S. Tsirkin --- tests/data/acpi/riscv64/virt/CEDT.cxl | Bin 0 -> 108 bytes tests/data/acpi/riscv64/virt/DSDT.cxl | Bin 0 -> 6331 bytes tests/qtest/bios-tables-test-allowed-diff.h | 2 -- 3 files changed, 2 deletions(-) diff --git a/tests/data/acpi/riscv64/virt/CEDT.cxl b/tests/data/acpi/riscv6= 4/virt/CEDT.cxl index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..81d746dfb09ccb147e26bb64060= 404ca3191d097 100644 GIT binary patch literal 108 zc-nJzbqUE~U|?VjaPoKd2v%^42yj*a0!E-1hz+6{7!(+IKx!BefCEf2LP-snumA^? O0aMEg#QH!C(hmS*@&^F` literal 0 Hc-jL100001 diff --git a/tests/data/acpi/riscv64/virt/DSDT.cxl b/tests/data/acpi/riscv6= 4/virt/DSDT.cxl index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c3d68cf3a080ab66160f6847267= fe4b9f8a8c6fc 100644 GIT binary patch literal 6331 zc-pO*%WoS+9LHzv^&{)GV>{0K;q)PKKt*52P18#i+v~J-6(`1)3XKq=3D4eEu9E28obaDpO`;KHpELLiX1ap8gl2ZV%VW_E37zv))$A&#^=3DsjyJZGJBgPxzOF3X@P8DTFKjaal{ zSw&55>vk$-ByRPn@?=3Du3Qe2mnGZm||gt~2=3Dm6f^f5>DAAv8Pa&LaaK4R>WGYa%H|- zscJ@y!FEkjZEuH#rWwwx(MH)Wr>6p`J|mg=3Dx%JBzS3jt3-Ff)Q*JnP}(xX~>C=3Dg$J z>E*SJBNty;zxMk2)wSz#+QM-;X;D90?<{wIp}r_5o!*_a%h{Pa>HN7m-^;kHEyJ1daTtF>fa*Vwx-UjNSmr{1k{=3D7bb<;^q~p3NM+xDMYxgvFV8ZP=3D zb@|>$1&KPmVh%?5VG3GRh(>Q3Fho2&R*i| zWzJsaOcH03IFrnoWX=3D?Erie4eoGIo^6K9$@)6AJ>&OYMoBhEhN>|@Rhab}1!!<-rB z>?h8C;_PS6e&!q?&H>^aV9o*N93;*`;v8hoLFODH&LQF)V$LDv945|T;v8nqVdfkm z&Jp4qVa^fe93{?C;v8kpQRW;Y&N1Q~W6m+=3D94F3k;v8qraps&L&I#h2V9p8V%o1mo zIJ3-|?Qpsu+zTP&h4&pjw&A2m{v$CeOgnS zosIhmcP_QY+|Gt;de}c{#QsSm_E8$KPtv$>uVz&|XRCMNiPk=3DDCzyE!Y5 zXlAgZmGZ+`J%UOw_o}F9t7z{Y6-_$Zy`xj@(ar~q=3DkaIDy;+)>kFb!2{C)I^<~i|{ z=3DIMCmeUk(+bEHwWt9tW*JLjXB?|-+a->Tjj{G&SjtyOLIY+n&Osi5X=3DR&G}H`kYNV z*|GV&fyd4h+%wsl-E&9ZIZ@6n&9HTTzDhUg)K3KExmw!PEM`?t@o6&_sq+>9-LSnsY^YbLg@Xgld>KuhaVcK!!2ury2n literal 0 Hc-jL100001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index c05fb697a5..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,3 +1 @@ /* List of comma-separated changed AML files to ignore */ -"riscv64/virt/DSDT.cxl", -"riscv64/virt/CEDT.cxl", --=20 2.50.1