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Sun, 06 Sep 2026 23:51:22 -0700 (PDT) From: Mayuresh Chitale To: Palmer Dabbelt , Alistair Francis Cc: Mayuresh Chitale , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Gong Shuai , TianCheng TANG , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2] target/riscv: Fix LCOFI interrupt masking in sie/sip/mvip Date: Mon, 7 Sep 2026 12:21:10 +0530 Message-ID: <20260907065112.2287127-1-mayuresh.chitale@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 1exjIkZ3omrPQ82ALe7UcbWddqI2Tare X-Proofpoint-ORIG-GUID: 1exjIkZ3omrPQ82ALe7UcbWddqI2Tare X-Authority-Analysis: v=2.4 cv=CbQ4Irrl c=1 sm=1 tr=0 ts=6a9e5eec cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=pGLkceISAAAA:8 a=SRrdq9N9AAAA:8 a=EUspDBNiAAAA:8 a=pY6yUR2m6-QEIg0VTF4A:9 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA3MDA3MCBTYWx0ZWRfX883QrFUGxEHd iYPxtE1QgrpjWVIK4Lg9qQpT3BkW56+AduXIVg/0UnInJjlez+bG7rzH3cIHmhGwmL4QQ8xgsYb CvMYSLGgIN+JXgfkP4i5cw3yjf1P/Lw= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA3MDA3MCBTYWx0ZWRfXwqdem9ED5QgA fIpF9+ZXuZkBBDeWqO93UnrSS9UDLxMD8+HU5K8zxbvcW0QvNuS+vPVvSwrJyz4XUwpcDvjR9k7 YAUqnLUhlLZ+wc4+4B1u5nFRrP5Bu+g9e/GDPZspEtwQt/XBPUpnNsKvMHb7B9/blydvKTBNg3g xFMQ+uzvcqJVnnITYHbHJQ/BMEBywYAwTG6peOb9lB2IGSfiiySG2PA3eOjusi1weyWEwjeV7zE 35FZ/mXWnM9ggBq0rLMPuhMLt7W33wi/DNPK1ko0Rh4X2xalBBJyRxdEYW3tF5kuHTvV7d6U/K5 4uwKh1wGUJHxzyILw7ezeLtO4c5h5SEgl6B5e4WcXQvTaDKfEkF9PpKPXnVRSpqGeKNVWHJk0K9 cLgauuMEXjVMUpSOzKOOsv8gG2EGERqEsy0bVcymIp9MRXmS601UZW0So2mWppmQSSLYOyD3Dnl ceJzny0YEdruYhn5mEQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-07_01,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 bulkscore=0 suspectscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609070070 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=mayuresh.chitale@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788763930871158500 Content-Type: text/plain; charset="utf-8" Commit 27f9566dcd98 dropped bit 13 (MIP_LCOFIP) from the LOCAL_INTERRUPTS macro and hence also from individual masks such as all_ints, sip_writable_mask etc. As a result, with Sscofpmf enabled and LCOFIP delegated to S-mode, the overflow interrupt was raised in mip but was not visible in sip and it never got delivered to the PMU driver. For the same reason, sie.LCOFIE also became read-only 0. Add back bit 13 in the affected masks, but gate it on Sscofpmf being implemented. In addition, for the virtual interrupt path, mvip/mvien LCOFI also requires Smcdeleg and Smaia to be implemented. Also make LCOFI delegable only if Sscofpmf is implemented. Fixes: 27f9566dcd98 ("target/riscv: Update the local interrupt mask") Suggested-by: Gong Shuai Suggested-by: TianCheng TANG Signed-off-by: Mayuresh Chitale Reviewed-by: Daniel Henrique Barboza --- v2: - Fix the sip.LCOFIP read-back mask in rmw_sip64() so that it matches the write path. - Gate LCOFI on the Sscofpmf, Smcdeleg and Smaia extensions, depending on the register being accessed and on whether it is the virtual interrupt path. target/riscv/tcg/csr.c | 59 +++++++++++++++++++++++++++++++++++------- 1 file changed, 50 insertions(+), 9 deletions(-) diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 002f7e69c1..966a0897bb 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -1812,7 +1812,7 @@ static RISCVException write_stimecmph(CPURISCVState *= env, int csrno, #define LOCAL_INTERRUPTS (~0xFFFFULL) =20 static const uint64_t delegable_ints =3D - S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP; + S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; static const uint64_t vs_delegable_ints =3D (VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & ~MIP_LCOFIP; static const uint64_t all_ints =3D M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | @@ -1874,6 +1874,25 @@ static const uint64_t hvien_writable_mask =3D LOCAL_= INTERRUPTS; =20 static const uint64_t vsip_writable_mask =3D MIP_VSSIP | LOCAL_INTERRUPTS; =20 +static bool lcofi_present(CPURISCVState *env, bool virt_int) +{ + const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); + + if (!cfg->ext_sscofpmf) { + return false; + } + + /* + * For the virtual interrupts path, we also need to check if smcdeleg = and + * smaia are both implemented. + */ + if (virt_int && !(cfg->ext_smcdeleg && cfg->ext_smaia)) { + return false; + } + + return true; +} + /* Machine Information Registers */ static RISCVException read_zero(CPURISCVState *env, int csrno, target_ulong *val) @@ -2248,6 +2267,10 @@ static RISCVException rmw_mideleg64(CPURISCVState *e= nv, int csrno, { uint64_t mask =3D wr_mask & delegable_ints; =20 + if (lcofi_present(env, false)) { + mask |=3D wr_mask & MIP_LCOFIP; + } + if (ret_val) { *ret_val =3D env->mideleg; } @@ -2299,6 +2322,10 @@ static RISCVException rmw_mie64(CPURISCVState *env, = int csrno, { uint64_t mask =3D wr_mask & all_ints; =20 + if (lcofi_present(env, false)) { + mask |=3D wr_mask & MIP_LCOFIP; + } + if (ret_val) { *ret_val =3D env->mie; } @@ -2349,6 +2376,10 @@ static RISCVException rmw_mvien64(CPURISCVState *env= , int csrno, { uint64_t mask =3D wr_mask & mvien_writable_mask; =20 + if (lcofi_present(env, true)) { + mask |=3D wr_mask & MIP_LCOFIP; + } + if (ret_val) { *ret_val =3D env->mvien; } @@ -3784,6 +3815,10 @@ static RISCVException rmw_mip64(CPURISCVState *env, = int csrno, uint64_t old_mip, mask =3D wr_mask & delegable_ints; uint32_t gin; =20 + if (lcofi_present(env, false)) { + mask |=3D wr_mask & MIP_LCOFIP; + } + /* * When mvien[9]=3D1, mip.SEIP is read-only and reflects only * the external interrupt signal from the interrupt controller. @@ -3897,9 +3932,11 @@ static RISCVException rmw_mvip64(CPURISCVState *env,= int csrno, * alias_mask denotes the bits that come from mip nalias_mask denotes= bits * that come from hvip. */ - uint64_t alias_mask =3D ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & + bool virt_int =3D (csrno =3D=3D CSR_MVIP) || (csrno =3D=3D CSR_MVIPH); + uint64_t lcofi_mask =3D lcofi_present(env, virt_int) ? MIP_LCOFIP : 0; + uint64_t alias_mask =3D ((S_MODE_INTERRUPTS | lcofi_mask | LOCAL_INTER= RUPTS) & (env->mideleg | ~env->mvien)) | MIP_STIP; - uint64_t nalias_mask =3D (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & + uint64_t nalias_mask =3D (S_MODE_INTERRUPTS | lcofi_mask | LOCAL_INTER= RUPTS) & (~env->mideleg & env->mvien); uint64_t wr_mask_mvip; uint64_t wr_mask_mip; @@ -3928,8 +3965,8 @@ static RISCVException rmw_mvip64(CPURISCVState *env, = int csrno, alias_mask &=3D ~MIP_STIP; } =20 - wr_mask_mip =3D wr_mask & alias_mask & mvip_writable_mask; - wr_mask_mvip =3D wr_mask & nalias_mask & mvip_writable_mask; + wr_mask_mip =3D wr_mask & alias_mask & (mvip_writable_mask | lcofi_mas= k); + wr_mask_mvip =3D wr_mask & nalias_mask & (mvip_writable_mask | lcofi_m= ask); =20 /* * For bits set in alias_mask, mvip needs to be alias of mip, so forwa= rd @@ -4132,9 +4169,11 @@ static RISCVException rmw_sie64(CPURISCVState *env, = int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { - uint64_t nalias_mask =3D (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & + uint64_t lcofi_mask =3D lcofi_present(env, false) ? MIP_LCOFIP : 0; + uint64_t nalias_mask =3D (S_MODE_INTERRUPTS | lcofi_mask | LOCAL_INTER= RUPTS) & (~env->mideleg & env->mvien); - uint64_t alias_mask =3D (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & env->= mideleg; + uint64_t alias_mask =3D (S_MODE_INTERRUPTS | lcofi_mask | LOCAL_INTERR= UPTS) & + env->mideleg; uint64_t sie_mask =3D wr_mask & nalias_mask; RISCVException ret; =20 @@ -4379,7 +4418,9 @@ static RISCVException rmw_sip64(CPURISCVState *env, i= nt csrno, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; - uint64_t mask =3D (env->mideleg | env->mvien) & sip_writable_mask; + uint64_t lcofi_mask =3D lcofi_present(env, false) ? MIP_LCOFIP : 0; + uint64_t mask =3D (env->mideleg | env->mvien) & + (sip_writable_mask | lcofi_mask); =20 if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { @@ -4392,7 +4433,7 @@ static RISCVException rmw_sip64(CPURISCVState *env, i= nt csrno, =20 if (ret_val) { *ret_val &=3D (env->mideleg | env->mvien) & - (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS); + (S_MODE_INTERRUPTS | lcofi_mask | LOCAL_INTERRUPTS); } =20 return ret; base-commit: a925240509d1b4b656cc480f1cc79ba4d7c8bc08 --=20 2.43.0