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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631865633154100 Cast operands to uint32_t before left-shifting in build_mreg() to avoid undefined behavior when the shift result overflows int32_t. Found with UBSan. Signed-off-by: Brian Cain --- tests/tcg/hexagon/circ.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/tcg/hexagon/circ.c b/tests/tcg/hexagon/circ.c index ab949ebef1c..2a15c324242 100644 --- a/tests/tcg/hexagon/circ.c +++ b/tests/tcg/hexagon/circ.c @@ -97,9 +97,9 @@ INIT(dbuf, NDOBLS) */ static int32_t build_mreg(int32_t inc, int32_t K, int32_t len) { - return ((inc & 0x780) << 21) | - ((K & 0xf) << 24) | - ((inc & 0x7f) << 17) | + return ((uint32_t)(inc & 0x780) << 21) | + ((uint32_t)(K & 0xf) << 24) | + ((uint32_t)(inc & 0x7f) << 17) | (len & 0x1ffff); } =20 --=20 2.34.1 From nobody Sat Sep 26 20:00:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788631913; cv=none; d=zohomail.com; s=zohoarc; b=e9McupcC53KzurYIr8ZEsWUoZ7wvI69ckIONxxywstwn0fFk4ubL3yxe2gwh4pNFJMsdcwSPZVibPWogRKy8/1LQ8LcGEuXWwNxGhEgl0Q89vVXHoC735+F70yMgayQRbf7NuCfwx0nfm57RFapjk+o2g8rFe7QW5vq/7HRHx84= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788631913; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Xaxst8wdMWsPo9+AMmjwvV4s5Q17/pJQfAEVLaoAtuA=; b=SFTdO3ysSxKf30bkeZqdw/PTlSIR3rsiav+cI9eqBXtgpE99NObuTMLNwALzvEas842yvBzTn2jO9OuxJycmzWFzsGyYj/oQkZf2eg13nBkj7u/0xMSRsoDcrCl1M1ypPYBkTDCkjaeyMn9yNlgh2Kc5SRo1xokaQgOrH0jVyXY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788631910095740.8760464767624; Sat, 5 Sep 2026 11:11:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x2uqQ-0002sZ-3m; Sat, 05 Sep 2026 14:10:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uq8-0002lh-OS for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:10 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uq6-0001P4-Ms for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:08 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 685HcCe02452017 for ; Sat, 5 Sep 2026 18:09:59 GMT Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ggbuehxfm-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Sat, 05 Sep 2026 18:09:58 +0000 (GMT) Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-cc435388657so2725056a12.3 for ; Sat, 05 Sep 2026 11:09:58 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631914295158500 Cast to uint32_t before left-shifting in sext8() to avoid undefined behavior when shifting a negative value. The subsequent arithmetic right shift on the int32_t cast correctly sign-extends the result. Found with UBSan. Signed-off-by: Brian Cain Reviewed-by:Sid Manning sid.manning@oss.qualcomm.com --- tests/tcg/hexagon/brev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/tcg/hexagon/brev.c b/tests/tcg/hexagon/brev.c index 6c7b1340849..1473e309ee0 100644 --- a/tests/tcg/hexagon/brev.c +++ b/tests/tcg/hexagon/brev.c @@ -106,7 +106,7 @@ uint32_t bitreverse(uint32_t x) =20 int32_t sext8(int32_t x) { - return (x << 24) >> 24; + return (int32_t)((uint32_t)x << 24) >> 24; } =20 #define TEST_BREV_LOAD(SZ, TYPE, BUF, SHIFT, EXP) \ --=20 2.34.1 From nobody Sat Sep 26 20:00:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788631924; cv=none; d=zohomail.com; s=zohoarc; b=KGnZp7mcA/ftBx+klz+cz1TYmEjPBG+a0Lmhvt2KORj6/9W9nXQtE5m6+gIsEc+JtR7GPbdlJFZ2INIyASasNVSt5yRDlQDKUIJZ3x//PFp7aJMwZOywRIUIpqtEannBXoYizQ+83oeRR3Q/cizv3oFwL9gRMNTXbPOyPwukwYc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788631924; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zoMJ8ubNugqDYoJRWFaRKxHdSYdWnZjnKAd139odpbM=; b=MvjcR01N6L3aUjcA6wijV2dIh9pT3+hD/z5G/8LrnrzNwAKUlGKfPEf5puoWiX3WIkl3COt+GWPvuh0p27rxXEhNC9r2vuZVjTRLzs8kXWtlSSPIJLO5cO3VxReMmfbptmCbyWhNZIP4nj/PYRe/bKLUuX/kie4kttacvgT1DhU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788631924647526.9655712827858; Sat, 5 Sep 2026 11:12:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x2uqK-0002rp-54; Sat, 05 Sep 2026 14:10:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uq9-0002mE-17 for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:10 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uq6-0001P8-Bq for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:08 -0400 Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 685HbmOk3520150 for ; Sat, 5 Sep 2026 18:09:59 GMT Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ggany1xc0-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Sat, 05 Sep 2026 18:09:58 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-cc1eb205d31so2734912a12.2 for ; Sat, 05 Sep 2026 11:09:58 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631926542158500 Use unsigned (.uw) instead of signed (.w) array members for vector addition and subtraction reference calculations to avoid signed integer overflow. Wrapping arithmetic is well-defined for unsigned types. Add CHECK_OUTPUT_FUNC(uw, 4) to support unsigned word comparisons in the TEST_VEC_OP2 macro. Found with UBSan. Signed-off-by: Brian Cain Reviewed-by:Sid Manning sid.manning@oss.qualcomm.com --- tests/tcg/hexagon/hvx_misc.h | 1 + tests/tcg/hexagon/hvx_misc.c | 18 +++++++++--------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/tests/tcg/hexagon/hvx_misc.h b/tests/tcg/hexagon/hvx_misc.h index c21ea975c16..e32715ed11d 100644 --- a/tests/tcg/hexagon/hvx_misc.h +++ b/tests/tcg/hexagon/hvx_misc.h @@ -69,6 +69,7 @@ static inline void check_output_##FIELD(int line, size_t = num_vectors) \ CHECK_OUTPUT_FUNC(d, 8) CHECK_OUTPUT_FUNC(w, 4) CHECK_OUTPUT_FUNC(sf, 4) +CHECK_OUTPUT_FUNC(uw, 4) CHECK_OUTPUT_FUNC(h, 2) CHECK_OUTPUT_FUNC(uh, 2) CHECK_OUTPUT_FUNC(hf, 2) diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c index 32a3661a86f..f20afc8e670 100644 --- a/tests/tcg/hexagon/hvx_misc.c +++ b/tests/tcg/hexagon/hvx_misc.c @@ -55,7 +55,7 @@ static void test_load_tmp(void) pout +=3D sizeof(MMVector); =20 for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 4; j++) { - expect[i].w[j] =3D buffer0[i].w[j] + buffer1[i].w[j] + 1; + expect[i].uw[j] =3D buffer0[i].uw[j] + buffer1[i].uw[j] + 1; } } =20 @@ -285,8 +285,8 @@ static void test_max_temps() =20 /* The first two vectors come from the vadd-pair instruction */ for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { - expect[0].w[i] =3D buffer0[0].w[i] + buffer0[2].w[i]; - expect[1].w[i] =3D buffer0[1].w[i] + buffer0[3].w[i]; + expect[0].uw[i] =3D buffer0[0].uw[i] + buffer0[2].uw[i]; + expect[1].uw[i] =3D buffer0[1].uw[i] + buffer0[3].uw[i]; } /* The third vector comes from the vshuffe instruction */ for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { @@ -295,7 +295,7 @@ static void test_max_temps() } /* The fourth vector comes from the vadd-single instruction */ for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { - expect[3].w[i] =3D buffer0[1].w[i] + buffer0[5].w[i]; + expect[3].uw[i] =3D buffer0[1].uw[i] + buffer0[5].uw[i]; } /* * The fifth vector comes from the load to v4 @@ -306,10 +306,10 @@ static void test_max_temps() check_output_b(__LINE__, 5); } =20 -TEST_VEC_OP2(vadd_w, vadd, .w, w, 4, +) +TEST_VEC_OP2(vadd_w, vadd, .w, uw, 4, +) TEST_VEC_OP2(vadd_h, vadd, .h, h, 2, +) TEST_VEC_OP2(vadd_b, vadd, .b, b, 1, +) -TEST_VEC_OP2(vsub_w, vsub, .w, w, 4, -) +TEST_VEC_OP2(vsub_w, vsub, .w, uw, 4, -) TEST_VEC_OP2(vsub_h, vsub, .h, h, 2, -) TEST_VEC_OP2(vsub_b, vsub, .b, b, 1, -) TEST_VEC_OP2(vxor, vxor, , d, 8, ^) @@ -489,9 +489,9 @@ static void test_load_tmp_predicated(void) pout +=3D sizeof(MMVector); =20 for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 4; j++) { - expect[i].w[j] =3D - pred ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631948426158500 Cast to uint32_t before multiplying uint16_t values to prevent signed integer overflow. Without the cast, the uint16_t operands are promoted to int, and the product can overflow the int range. Found with UBSan. Signed-off-by: Brian Cain Reviewed-by:Sid Manning sid.manning@oss.qualcomm.com --- tests/tcg/hexagon/v69_hvx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/tcg/hexagon/v69_hvx.c b/tests/tcg/hexagon/v69_hvx.c index a0d567d142f..eff936064a0 100644 --- a/tests/tcg/hexagon/v69_hvx.c +++ b/tests/tcg/hexagon/v69_hvx.c @@ -292,7 +292,8 @@ static void test_vmpyuhvs(void) pout +=3D sizeof(MMVector); =20 for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 2; j++) { - expect[i].uh[j] =3D (buffer0[i].uh[j] * buffer1[i].uh[j]) >> 1= 6; + expect[i].uh[j] =3D + ((uint32_t)buffer0[i].uh[j] * buffer1[i].uh[j]) >> 16; } } =20 --=20 2.34.1 From nobody Sat Sep 26 20:00:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788631925; cv=none; d=zohomail.com; s=zohoarc; b=gtzKJ/wqzPHl4h1JP/oGqNxbCU3d1wsQ8AXsnPKpNsx+FmJ4SaFe8otKdBFkE3k5rROprOedOzkBbXx/KsNjK/KrrhcLj9JVSUGQ9T0uIZeZUkbyP87U/GXlRUsPOSDTAcNRWXfc5Ih+K2vT2RZPeXHjNAhZ3EJGpwVv/JAUHM4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788631925; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0jznzsrL2c1cMANKS+KMYcmou2PNLYP6+Qmd0n2zxjY=; b=T7kMTQlzxctkYhS1XI0zhXGo7uSpDWV+N4YPEPuxLJ2Ys4XEftx+fFrM9UbF9+Ky9041auAT8lxf/z4BhEjCkdXgnCoklEyDPbekAOSgghAyQsc7vE6RZ+QZvr9DLij5K/W8b/mfe5WxQRvX4QSkOM+K1UjI32rcPzBPm5jYTls= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788631925305280.484314638834; Sat, 5 Sep 2026 11:12:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x2uqI-0002rK-Dv; Sat, 05 Sep 2026 14:10:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uq9-0002mu-PM for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:10 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uq8-0001Qq-3F for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:09 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 685Hb4Wc2449911 for ; Sat, 5 Sep 2026 18:10:04 GMT Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ggbuehxfs-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Sat, 05 Sep 2026 18:10:04 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-cc132709c76so2789885a12.3 for ; Sat, 05 Sep 2026 11:10:03 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631926374154100 Add __attribute__((no_sanitize("undefined"))) to the float/double to integer conversion functions. C17 6.3.1.4p1 only defines float-to-integer conversion for finite values whose integral part fits in the destination type; it discards the fractional part and explicitly makes it UB if the integral part doesn't fit. These tests intentionally exercise both of those UB cases, so we'll suppress it to get a clean ubsan run on the TCG test suite. Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- tests/tcg/multiarch/float_convd.c | 1 + tests/tcg/multiarch/float_convs.c | 1 + 2 files changed, 2 insertions(+) diff --git a/tests/tcg/multiarch/float_convd.c b/tests/tcg/multiarch/float_= convd.c index 58d7f8b4c58..cb3884df974 100644 --- a/tests/tcg/multiarch/float_convd.c +++ b/tests/tcg/multiarch/float_convd.c @@ -62,6 +62,7 @@ static void convert_double_to_single(double input) #define str(a) #a =20 #define CONVERT_DOUBLE_TO_INT(TYPE, FMT) \ + __attribute__((no_sanitize("undefined"))) \ static void convert_double_to_ ## TYPE(double input) \ { \ TYPE ## _t output; \ diff --git a/tests/tcg/multiarch/float_convs.c b/tests/tcg/multiarch/float_= convs.c index cb1fdd439e3..584ce89aa17 100644 --- a/tests/tcg/multiarch/float_convs.c +++ b/tests/tcg/multiarch/float_convs.c @@ -62,6 +62,7 @@ static void convert_single_to_double(float input) #define str(a) #a =20 #define CONVERT_SINGLE_TO_INT(TYPE, FMT) \ + __attribute__((no_sanitize("undefined"))) \ static void convert_single_to_ ## TYPE(float input) \ { \ TYPE ## _t output; \ --=20 2.34.1 From nobody Sat Sep 26 20:00:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788631857; cv=none; d=zohomail.com; s=zohoarc; b=ahZWT57w4XYQL2NvvSAURWmBgqYzgCQ27OhyV/b3D2M9k9mURoLeg5gIZpVcvlnjEb2iX5VdAY0DWLE8VBLKSH4N4xyIPqMZ3SsYjOMMqF7/vUSRHQTBq55DZl1xC0WqFbZf+zO3D1TyYF7u0q97Nn5xiFbhhrL5m28Gdn9KcCM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788631857; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hQAp/rIDMa1sYGRkoRCgkVwiNEWZvL9ZQuXRJCszO/k=; b=QpkXGq7jUI8M9rkmi8uUHhOPk0YGSR5IWElCyqTfZzksbYNKeBkETcg3AWV1ut6S5XZx4x43xLl1YuNPkn4Lxpxo2dHnPkW66lilwrYExIQ2RFuuUfh/SroCppgo1Gr85QxjzPhu/czniXTUtwEAc8dlbQoBYfSdokc+XYWsxI8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788631857405916.2335856613644; Sat, 5 Sep 2026 11:10:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x2uqJ-0002rm-F7; Sat, 05 Sep 2026 14:10:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uqA-0002qj-WD for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:12 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uq9-0001RB-26 for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:10 -0400 Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 685HcU8f4117451 for ; Sat, 5 Sep 2026 18:10:06 GMT Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gg8sd2d0q-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Sat, 05 Sep 2026 18:10:06 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-ca8aee88725so3517476a12.3 for ; Sat, 05 Sep 2026 11:10:06 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631861535154100 Add sfclass/dfclass FP classification tests, unsigned-to-double conversions, and dfmpyfix denormal fixup tests. Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- tests/tcg/hexagon/fpstuff.c | 175 ++++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c index 6aadaccabdf..7561f31cdc3 100644 --- a/tests/tcg/hexagon/fpstuff.c +++ b/tests/tcg/hexagon/fpstuff.c @@ -711,6 +711,176 @@ static void check_dfmpyxx(void) check64(res64, 0x7fefffffffffffffULL); } =20 +/* + * sfclass mask bits: + * bit 0: positive/negative zero + * bit 1: positive/negative normal + * bit 2: positive/negative denormal + * bit 3: positive/negative infinity + * bit 4: positive/negative NaN + */ +#define TEST_SFCLASS(VAL, MASK, EXPECT) \ + do { \ + uint32_t res; \ + asm("%[res] =3D #0\n\t" \ + "p0 =3D sfclass(%[val], #" #MASK ")\n\t" \ + "if (p0) %[res] =3D #1\n\t" \ + : [res] "=3D&r"(res) \ + : [val] "r"(VAL) \ + : "p0"); \ + check32(res, EXPECT); \ + } while (0) + +static void check_sfclass(void) +{ + /* Zero: mask bit 0 */ + TEST_SFCLASS(SF_zero, 0x01, 1); + TEST_SFCLASS(SF_zero_neg, 0x01, 1); + TEST_SFCLASS(SF_zero, 0x02, 0); + + /* Normal: mask bit 1 */ + TEST_SFCLASS(SF_one, 0x02, 1); + TEST_SFCLASS(SF_one, 0x01, 0); + + /* Denormal: mask bit 2 */ + TEST_SFCLASS(SF_denorm, 0x04, 1); + TEST_SFCLASS(SF_denorm, 0x01, 0); + + /* Infinity: mask bit 3 */ + TEST_SFCLASS(SF_INF, 0x08, 1); + TEST_SFCLASS(SF_INF, 0x01, 0); + + /* NaN: mask bit 4 */ + TEST_SFCLASS(SF_QNaN, 0x10, 1); + TEST_SFCLASS(SF_SNaN, 0x10, 1); + TEST_SFCLASS(SF_QNaN, 0x01, 0); + + /* Combined: any class (all bits set) */ + TEST_SFCLASS(SF_one, 0x1f, 1); +} + +/* + * dfclass mask bits are the same as sfclass. + */ +static const uint64_t DF_INF =3D 0x7ff0000000000000ULL; +static const uint64_t DF_denorm =3D 0x0000000000000001ULL; +static const uint64_t DF_neg_one =3D 0xbff0000000000000ULL; + +#define TEST_DFCLASS(VAL, MASK, EXPECT) \ + do { \ + uint32_t res; \ + asm("%[res] =3D #0\n\t" \ + "p0 =3D dfclass(%[val], #" #MASK ")\n\t" \ + "if (p0) %[res] =3D #1\n\t" \ + : [res] "=3D&r"(res) \ + : [val] "r"(VAL) \ + : "p0"); \ + check32(res, EXPECT); \ + } while (0) + +static void check_dfclass(void) +{ + /* Zero: mask bit 0 */ + TEST_DFCLASS(DF_zero, 0x01, 1); + TEST_DFCLASS(DF_zero_neg, 0x01, 1); + TEST_DFCLASS(DF_zero, 0x02, 0); + + /* Normal: mask bit 1 */ + TEST_DFCLASS(DF_one, 0x02, 1); + TEST_DFCLASS(DF_neg_one, 0x02, 1); + TEST_DFCLASS(DF_one, 0x01, 0); + + /* Denormal: mask bit 2 */ + TEST_DFCLASS(DF_denorm, 0x04, 1); + TEST_DFCLASS(DF_denorm, 0x01, 0); + + /* Infinity: mask bit 3 */ + TEST_DFCLASS(DF_INF, 0x08, 1); + TEST_DFCLASS(DF_INF, 0x01, 0); + + /* NaN: mask bit 4 */ + TEST_DFCLASS(DF_QNaN, 0x10, 1); + TEST_DFCLASS(DF_SNaN, 0x10, 1); + TEST_DFCLASS(DF_QNaN, 0x01, 0); +} + +/* Rdd =3D convert_uw2df(Rs) */ +static uint64_t conv_uw2df(uint32_t val) +{ + uint64_t result; + + asm("%[res] =3D convert_uw2df(%[val])\n\t" + : [res] "=3Dr"(result) + : [val] "r"(val)); + return result; +} + +static void check_conv_uw2df(void) +{ + check64(conv_uw2df(0), DF_zero); + check64(conv_uw2df(1), DF_one); + /* 100 -> 0x4059000000000000 */ + check64(conv_uw2df(100), 0x4059000000000000ULL); + /* 0xFFFFFFFF -> 4294967295.0 =3D 0x41EFFFFFFFE00000 */ + check64(conv_uw2df(0xFFFFFFFF), 0x41EFFFFFFFE00000ULL); +} + +/* Rdd =3D convert_ud2df(Rss) */ +static uint64_t conv_ud2df(uint64_t val) +{ + uint64_t result; + + asm("%[res] =3D convert_ud2df(%[val])\n\t" + : [res] "=3Dr"(result) + : [val] "r"(val)); + return result; +} + +static void check_conv_ud2df(void) +{ + check64(conv_ud2df(0ULL), DF_zero); + check64(conv_ud2df(1ULL), DF_one); + /* 1000000 -> 0x412E848000000000 */ + check64(conv_ud2df(1000000ULL), 0x412E848000000000ULL); +} + +/* Rdd =3D dfmpyfix(Rss,Rtt) -- DF multiply denormal fixup */ +static uint64_t do_dfmpyfix(uint64_t a, uint64_t b) +{ + uint64_t result; + + asm("%[res] =3D dfmpyfix(%[a], %[b])\n\t" + : [res] "=3Dr"(result) + : [a] "r"(a), [b] "r"(b)); + return result; +} + +static void check_dfmpyfix(void) +{ + /* + * With two normal values (neither denormal, exps < 512), + * the result should be the first operand unchanged. + */ + check64(do_dfmpyfix(DF_one, DF_one), DF_one); + + /* + * Case: b is denormal AND a is normal with exp >=3D 512. + * a gets multiplied by 2^-52 (0x3cb0000000000000). + * a =3D 1.0, result =3D 1.0 * 2^-52 =3D 0x3cb0000000000000 + */ + check64(do_dfmpyfix(DF_one, DF_denorm), 0x3CB0000000000000ULL); + + /* + * Case: a is denormal AND b is normal with exp >=3D 512. + * a gets multiplied by 2^52 (0x4330000000000000). + * a =3D smallest denorm =3D 2^-1074, b =3D 2^512 (biased exp 0x5ff). + * Result =3D 2^-1074 * 2^52 =3D 2^-1022 =3D smallest normal + * =3D 0x0010000000000000 + */ + check64(do_dfmpyfix(DF_denorm, 0x5FF0000000000000ULL), + 0x0010000000000000ULL); +} + int main() { check_compare_exception(); @@ -725,6 +895,11 @@ int main() check_float2int_convs(); check_float_consts(); check_dfmpyxx(); + check_sfclass(); + check_dfclass(); + check_conv_uw2df(); + check_conv_ud2df(); + check_dfmpyfix(); =20 puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631922347154100 Test the interleave/deinterleave 64-bit bit-manipulation instructions and the cround instruction. Signed-off-by: Brian Cain Reviewed-by:Sid Manning --- tests/tcg/hexagon/test_bitops.c | 98 +++++++++++++++++++++++++++++++++ tests/tcg/hexagon/meson.build | 1 + 2 files changed, 99 insertions(+) create mode 100644 tests/tcg/hexagon/test_bitops.c diff --git a/tests/tcg/hexagon/test_bitops.c b/tests/tcg/hexagon/test_bitop= s.c new file mode 100644 index 00000000000..3e9274ddddd --- /dev/null +++ b/tests/tcg/hexagon/test_bitops.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * Test bit interleave/deinterleave and convergent rounding. + */ + +#include +#include +#include + +int err; + +#include "hex_test.h" + +static void check_interleave(void) +{ + uint64_t input; + uint64_t inter; + uint64_t deinter; + + /* + * interleave takes the 32 even bits and 32 odd bits of Rss and + * interleaves them: even[0] goes to bit 0, odd[0] to bit 1, + * even[1] to bit 2, odd[1] to bit 3, etc. + * + * Input: low 32 bits (even half), high 32 bits (odd half) + * If low =3D 0xFFFFFFFF, high =3D 0x00000000: + * result has every even bit set, every odd bit clear + * =3D 0x5555555555555555 + */ + input =3D 0x00000000FFFFFFFFULL; + inter =3D Q6_P_interleave_P(input); + check64(inter, 0x5555555555555555ULL); + + /* All ones should stay all ones */ + input =3D 0xFFFFFFFFFFFFFFFFULL; + inter =3D Q6_P_interleave_P(input); + check64(inter, 0xFFFFFFFFFFFFFFFFULL); + + /* All zeros should stay all zeros */ + input =3D 0x0000000000000000ULL; + inter =3D Q6_P_interleave_P(input); + check64(inter, 0x0000000000000000ULL); + + /* + * deinterleave is the inverse of interleave. + * deinterleave(interleave(x)) should equal x. + */ + input =3D 0xDEADBEEFCAFEBABEULL; + inter =3D Q6_P_interleave_P(input); + deinter =3D Q6_P_deinterleave_P(inter); + check64(deinter, input); + + /* deinterleave of 0x5555...5555 -> low half all 1s, high half all 0s = */ + deinter =3D Q6_P_deinterleave_P(0x5555555555555555ULL); + check64(deinter, 0x00000000FFFFFFFFULL); +} + +static void check_cround(void) +{ + /* + * cround(0x300, #8) -> 3 (exact shift, no rounding needed). + * 0x300 >> 8 =3D 3 + */ + check32(Q6_R_cround_RI(0x300, 8), 3); + + /* + * cround(0x380, #8) -> 4 (0x380 >> 8 =3D 3.5, rounds to even =3D 4) + */ + check32(Q6_R_cround_RI(0x380, 8), 4); + + /* + * cround(0x280, #8) -> 2 (0x280 >> 8 =3D 2.5, rounds to even =3D 2) + */ + check32(Q6_R_cround_RI(0x280, 8), 2); + + /* + * cround(0x3C0, #8) -> 4 (0x3C0 >> 8 =3D 3.75, rounds up to 4) + */ + check32(Q6_R_cround_RI(0x3C0, 8), 4); + + /* + * Shift by 0 -> return the input unchanged. + */ + check32(Q6_R_cround_RI(42, 0), 42); +} + +int main(void) +{ + check_interleave(); + check_cround(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build index 4a2826c4276..6c8e26876af 100644 --- a/tests/tcg/hexagon/meson.build +++ b/tests/tcg/hexagon/meson.build @@ -69,6 +69,7 @@ tests +=3D { 'test_abs.S': {'cflags': asmflags}, 'test_bitcnt.S': {'cflags': asmflags}, 'test_bitsplit.S': {'cflags': asmflags}, + 'test_bitops.c': {'cflags': cflags}, 'test_call.S': {'cflags': asmflags}, 'test_clobber.S': {'cflags': asmflags}, 'test_cmp.S': {'cflags': asmflags}, --=20 2.34.1 From nobody Sat Sep 26 20:00:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788631913; cv=none; d=zohomail.com; s=zohoarc; b=Jeu5ora8xp0QZcGHwv0mKkCkcd/nYPi6Bltr2rA3XnLYUqflSm0V8Zc3dKMlgvSpbsLpFWJ1uVeU2UzsbF5r09pxdKrDHqDdVgyN03uLIqRcv0HSJ2QnffD/txYWydCzt1bquGV2XxNkF17Mtr15S2wtKAH96mgmFd2W/2fZ3Po= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788631913; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Yrqh62pzVyNW02N+VwF8wglTlx2ZXqgjxuu+4LlRKEc=; b=nFttdiOGeEFkES89/tBzd8tNa1M18/Kvu0oEakfo4yxNxrED8qtcU2tl8kPWbvPdbil5y+lRdSzfSiZqLBoZoXdJ3lSr81fKtus/1lf9sV3RNrM5g7DMGbuFck9fqSo4YnKPFhep7sfhkSuG94gPktmXTMUB4yZeqj5H2E6pBuE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788631913071834.8838270701231; Sat, 5 Sep 2026 11:11:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x2uqc-0002we-Cn; Sat, 05 Sep 2026 14:10:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uqE-0002rC-D9 for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:16 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uqB-0001cr-D1 for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:13 -0400 Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 685HcWxx3521421 for ; Sat, 5 Sep 2026 18:10:10 GMT Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ggany1xc9-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Sat, 05 Sep 2026 18:10:10 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-38ea32e57e2so4206602a91.1 for ; Sat, 05 Sep 2026 11:10:09 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631914248154100 Test conditional callr, compound tstbit0-and-jump instructions and endloop01. These exercise previously uncovered branch paths in translate.c. Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- tests/tcg/hexagon/test_cond_branch.c | 162 +++++++++++++++++++++++++++ tests/tcg/hexagon/meson.build | 1 + 2 files changed, 163 insertions(+) create mode 100644 tests/tcg/hexagon/test_cond_branch.c diff --git a/tests/tcg/hexagon/test_cond_branch.c b/tests/tcg/hexagon/test_= cond_branch.c new file mode 100644 index 00000000000..73be8fbb43c --- /dev/null +++ b/tests/tcg/hexagon/test_cond_branch.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * Test conditional calls, compound testbit0-and-jump instructions, + * and endloop01 (dual hardware loop end). + */ + +#include +#include + +int err; + +#include "hex_test.h" + +/* Target function for conditional calls */ +static int call_target_val; + +__attribute__((noinline)) +static void call_target(void) +{ + call_target_val =3D 42; +} + +/* + * Test conditional call: if (Pu) callr Rs / if (!Pu) callr Rs + */ +static void check_cond_call(void) +{ + void (*fn)(void) =3D call_target; + + /* + * callr clobbers all caller-saved registers. + * Hexagon caller-saved: r0-r5, r14-r15, r28, p0-p3. + */ + + /* if (p0) callr Rs -- predicate true */ + call_target_val =3D 0; + asm volatile("p0 =3D cmp.eq(%[one], %[one])\n\t" /* p0 =3D true */ + "if (p0) callr %[fn]\n\t" + : + : [one] "r"(1), [fn] "r"(fn) + : "r0", "r1", "r2", "r3", "r4", "r5", + "r14", "r15", "r28", "r31", + "p0", "p1", "p2", "p3", "memory"); + check32(call_target_val, 42); + + /* if (!p0) callr Rs -- predicate true, so !p0 is false */ + call_target_val =3D 0; + asm volatile("p0 =3D cmp.eq(%[one], %[one])\n\t" /* p0 =3D true */ + "if (!p0) callr %[fn]\n\t" + : + : [one] "r"(1), [fn] "r"(fn) + : "r0", "r1", "r2", "r3", "r4", "r5", + "r14", "r15", "r28", "r31", + "p0", "p1", "p2", "p3", "memory"); + check32(call_target_val, 0); + + /* if (!p0) callr Rs -- predicate false, so !p0 is true */ + call_target_val =3D 0; + asm volatile("p0 =3D cmp.eq(%[a], %[b])\n\t" /* p0 =3D false (1 !=3D = 2) */ + "if (!p0) callr %[fn]\n\t" + : + : [a] "r"(1), [b] "r"(2), [fn] "r"(fn) + : "r0", "r1", "r2", "r3", "r4", "r5", + "r14", "r15", "r28", "r31", + "p0", "p1", "p2", "p3", "memory"); + check32(call_target_val, 42); +} + +/* + * Test compound testbit0-and-jump. + * p0 =3D tstbit(Rs, #0); if ([!]p0.new) jump:t/nt target + */ +static void check_tstbit0_jump(void) +{ + uint32_t result; + + /* Rs has bit0 =3D 1, test "if (p0.new) jump" -> should jump */ + result =3D 0; + asm volatile( + "{\n\t" + " p0 =3D tstbit(%[val], #0)\n\t" + " if (p0.new) jump:t 1f\n\t" + "}\n\t" + "%[res] =3D #0\n\t" + "jump 2f\n\t" + "1:\n\t" + "%[res] =3D #1\n\t" + "2:\n\t" + : [res] "=3Dr"(result) + : [val] "r"(0x5) /* bit 0 is set */ + : "p0"); + check32(result, 1); + + /* Rs has bit0 =3D 0, test "if (p0.new) jump" -> should NOT jump */ + result =3D 0; + asm volatile( + "{\n\t" + " p0 =3D tstbit(%[val], #0)\n\t" + " if (p0.new) jump:t 1f\n\t" + "}\n\t" + "%[res] =3D #0\n\t" + "jump 2f\n\t" + "1:\n\t" + "%[res] =3D #1\n\t" + "2:\n\t" + : [res] "=3Dr"(result) + : [val] "r"(0x4) /* bit 0 is clear */ + : "p0"); + check32(result, 0); + + /* Rs has bit0 =3D 0, test "if (!p0.new) jump" -> should jump */ + result =3D 0; + asm volatile( + "{\n\t" + " p0 =3D tstbit(%[val], #0)\n\t" + " if (!p0.new) jump:t 1f\n\t" + "}\n\t" + "%[res] =3D #0\n\t" + "jump 2f\n\t" + "1:\n\t" + "%[res] =3D #1\n\t" + "2:\n\t" + : [res] "=3Dr"(result) + : [val] "r"(0x4) /* bit 0 is clear */ + : "p0"); + check32(result, 1); +} + +/* + * Test endloop01: a packet that terminates both loop0 and loop1. + * Outer loop runs 3 iterations, inner loop runs 4. + */ +static void check_endloop01(void) +{ + uint32_t count; + + asm volatile( + "%[cnt] =3D #0\n\t" + "loop1(1f, #3)\n\t" /* outer loop: 3 iterations */ + "1:\n\t" + "loop0(2f, #4)\n\t" /* inner loop: 4 iterations */ + "2:\n\t" + "{ %[cnt] =3D add(%[cnt], #1) }:endloop01\n\t" + : [cnt] "=3Dr"(count)); + + /* 3 outer * 4 inner =3D 12 total iterations */ + check32(count, 12); +} + +int main(void) +{ + check_cond_call(); + check_tstbit0_jump(); + check_endloop01(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build index 6c8e26876af..aa176e56883 100644 --- a/tests/tcg/hexagon/meson.build +++ b/tests/tcg/hexagon/meson.build @@ -73,6 +73,7 @@ tests +=3D { 'test_call.S': {'cflags': asmflags}, 'test_clobber.S': {'cflags': asmflags}, 'test_cmp.S': {'cflags': asmflags}, + 'test_cond_branch.c': {'cflags': cflags}, 'test_dotnew.S': {'cflags': asmflags}, 'test_ext.S': {'cflags': asmflags}, 'test_fibonacci.S': {'cflags': asmflags}, --=20 2.34.1 From nobody Sat Sep 26 20:00:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788631904; cv=none; d=zohomail.com; s=zohoarc; b=SmE+3G5rdJfm4OnvZoOGzphI+Vmc4QmCv+eRWYbguBuUzKCkwldrMDmY7tlBD7gNQCnK/G+vgOZtoPgcXOgXmQlYwGzYTG4WxprM1/XVaXncK4yA9ovfPQRBVwHjzBMa/cF5Cvy75UU8g+fCqsTOSuiGS958UjLOtpToSo/W7aI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788631904; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4DvtK8S5TJotU1fvpxHTlfk3iWSuq+07sN+ZNPnFJFw=; b=WUBnSbRZ5f71UOFUhf7Bc44bAH+U67HdBLKcbZQfLD9fZRsdJTSjhd2HlBi2Mp2efAeMNU5u8+xvLbHD1lPj0oq5WGWYoWimA1nQoS46cL54dpqU1mghBmwZ/xNpfC9lKXJzqlfHcmQsrkIayAJ+KxG1+nHrZmCmWZTsgeA6tJE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178863190426116.87070465915326; Sat, 5 Sep 2026 11:11:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x2uqV-0002sr-Ry; Sat, 05 Sep 2026 14:10:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uqI-0002rb-K3 for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:18 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uqG-0001dQ-SY for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:18 -0400 Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 685HcGw53521237 for ; Sat, 5 Sep 2026 18:10:15 GMT Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ggany1xcb-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Sat, 05 Sep 2026 18:10:15 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2d7293f13c6so27202585ad.2 for ; Sat, 05 Sep 2026 11:10:15 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631906268154100 Test the dczeroa instruction which zeroes a cache line. Verifies aligned, unaligned, and buffer-start addresses. Signed-off-by: Brian Cain Reviewed-by:Sid Manning --- tests/tcg/hexagon/test_dczeroa.c | 88 ++++++++++++++++++++++++++++++++ tests/tcg/hexagon/meson.build | 1 + 2 files changed, 89 insertions(+) create mode 100644 tests/tcg/hexagon/test_dczeroa.c diff --git a/tests/tcg/hexagon/test_dczeroa.c b/tests/tcg/hexagon/test_dcze= roa.c new file mode 100644 index 00000000000..8cdcdd6a3b5 --- /dev/null +++ b/tests/tcg/hexagon/test_dczeroa.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * Test the dczeroa instruction, which zeroes a 32-byte cache line. + * The address is rounded down to a 32-byte boundary: (addr & ~0x1f). + */ + +#include +#include +#include +#include + +int err; + +#include "hex_test.h" + +static uint8_t buf[128] __attribute__((aligned(32))); + +/* dczeroa with an aligned address */ +static void test_dczeroa_aligned(void) +{ + int i; + + memset(buf, 0xff, sizeof(buf)); + + Q6_dczeroa_A(&buf[32]); + + for (i =3D 0; i < 32; i++) { + check32(buf[i], 0xff); + } + for (i =3D 32; i < 64; i++) { + check32(buf[i], 0x00); + } + for (i =3D 64; i < 96; i++) { + check32(buf[i], 0xff); + } +} + +/* dczeroa with an unaligned address (should round down) */ +static void test_dczeroa_unaligned(void) +{ + int i; + + memset(buf, 0xff, sizeof(buf)); + + /* Address buf+40 rounds down to buf+32 */ + Q6_dczeroa_A(&buf[40]); + + for (i =3D 0; i < 32; i++) { + check32(buf[i], 0xff); + } + for (i =3D 32; i < 64; i++) { + check32(buf[i], 0x00); + } + for (i =3D 64; i < 96; i++) { + check32(buf[i], 0xff); + } +} + +/* dczeroa at the start of the buffer */ +static void test_dczeroa_start(void) +{ + int i; + + memset(buf, 0xff, sizeof(buf)); + + Q6_dczeroa_A(&buf[0]); + + for (i =3D 0; i < 32; i++) { + check32(buf[i], 0x00); + } + for (i =3D 32; i < 64; i++) { + check32(buf[i], 0xff); + } +} + +int main(void) +{ + test_dczeroa_aligned(); + test_dczeroa_unaligned(); + test_dczeroa_start(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build index aa176e56883..fcf0bd38f26 100644 --- a/tests/tcg/hexagon/meson.build +++ b/tests/tcg/hexagon/meson.build @@ -74,6 +74,7 @@ tests +=3D { 'test_clobber.S': {'cflags': asmflags}, 'test_cmp.S': {'cflags': asmflags}, 'test_cond_branch.c': {'cflags': cflags}, + 'test_dczeroa.c': {'cflags': cflags}, 'test_dotnew.S': {'cflags': asmflags}, 'test_ext.S': {'cflags': asmflags}, 'test_fibonacci.S': {'cflags': asmflags}, --=20 2.34.1 From nobody Sat Sep 26 20:00:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788631921; cv=none; d=zohomail.com; s=zohoarc; b=bRH7j8wzywgHeLkV3o0WMe70LddqIuD7m9/FzGauY1iO3tPGjFiSzmE1Oqr2Oybuk1uh9gNzbbXYG+laPvhV6Y1hyx9RS3g/1JZwTa4o5jtZDC8JhCJmAsDl8o/cwyofrmhJu+IRQW4xFGXAIqckC3KHvKrQDfrSLNYY2eO3BMQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788631921; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LpTLBTasF+5RS+EpSk3QCx962PeXHI2vn2JaNnRbKLs=; b=PzaTz6mZLg5Ll3AIUO50jW+9qHeEJqkcyG7THSok84zfDJYivRki17hRGRGOKVfPW4dwFtPGASArjUbxm9ndkVxRuUapHGv4HW6O2/k0xXZM9sP9qIBSsmE2pR1EeJFwopmzj0HdOsx2X/7PTstwhCPOO7KsG39+2f7a374h4mE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788631921110719.4714347037707; Sat, 5 Sep 2026 11:12:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x2uqc-0002x1-Jt; Sat, 05 Sep 2026 14:10:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uqN-0002sL-Ef for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:25 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uqI-0001da-FC for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:20 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 685Hb0GR2295054 for ; Sat, 5 Sep 2026 18:10:17 GMT Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ggcca1rh1-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Sat, 05 Sep 2026 18:10:16 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2d7443e0f0bso31810125ad.1 for ; Sat, 05 Sep 2026 11:10:16 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631924415154100 Test all eight vwhist instruction variants and the four Q-masked forms. Signed-off-by: Brian Cain --- tests/tcg/hexagon/test_vwhist.c | 361 ++++++++++++++++++++++++++++++++ tests/tcg/hexagon/meson.build | 1 + 2 files changed, 362 insertions(+) create mode 100644 tests/tcg/hexagon/test_vwhist.c diff --git a/tests/tcg/hexagon/test_vwhist.c b/tests/tcg/hexagon/test_vwhis= t.c new file mode 100644 index 00000000000..5e143f79a43 --- /dev/null +++ b/tests/tcg/hexagon/test_vwhist.c @@ -0,0 +1,361 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * Test HVX weighted histogram instructions (vwhist128/vwhist256 variants). + * + * Each halfword in the input vector (loaded via Vx.tmp) contains a bucket + * index (low byte) and a weight (high byte). The instruction accumulates + * the weight into the appropriate element of the destination vector. + */ + +#include +#include +#include + +int err; + +#define MAX_VEC_SIZE_BYTES 128 + +typedef union { + uint32_t uw[MAX_VEC_SIZE_BYTES / 4]; + uint16_t uh[MAX_VEC_SIZE_BYTES / 2]; + uint8_t ub[MAX_VEC_SIZE_BYTES]; +} MMVector; + +/* + * Build input vector for vwhist256: each halfword is (weight << 8 | bucke= t). + * We put bucket=3D0, weight=3D1 in every slot so that v0.uh[0] gets incre= mented + * by 1 for each of the 64 halfwords -> v0.uh[0] should equal 64. + */ +static MMVector input __attribute__((aligned(MAX_VEC_SIZE_BYTES))); +static MMVector zero_vec __attribute__((aligned(MAX_VEC_SIZE_BYTES))); +static MMVector result __attribute__((aligned(MAX_VEC_SIZE_BYTES))); + +static void check_uint32(int line, int idx, uint32_t val, uint32_t expect) +{ + if (val !=3D expect) { + printf("ERROR at line %d: [%d] 0x%08x !=3D 0x%08x\n", + line, idx, val, expect); + err++; + } +} + +static void check_uint16(int line, int idx, uint16_t val, uint16_t expect) +{ + if (val !=3D expect) { + printf("ERROR at line %d: [%d] 0x%04x !=3D 0x%04x\n", + line, idx, val, expect); + err++; + } +} + +/* + * Test vwhist256: 256-bin histogram with 16-bit accumulation. + * Each halfword of the input: low byte =3D bucket, high byte =3D weight. + * bucket bits [7:3] -> vindex (which vector register), [2:0] + lane -> el= ement. + * All entries have bucket=3D0 weight=3D1, so v0.uh[0..7] get incremented. + */ +static void test_vwhist256(void) +{ + int i; + + /* Set all input halfwords to bucket=3D0, weight=3D1 */ + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0x0100; /* weight=3D1, bucket=3D0 */ + } + + asm volatile( + /* Zero out v0 (the target for bucket 0) */ + "v0 =3D vmem(%[zero] + #0)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist256\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result) + : "v0", "v12", "memory"); + + /* + * 64 input halfwords all targeting bucket 0. + * elindex =3D (i & ~7) | (bucket & 7) =3D i & ~7 (since bucket=3D0). + * So elements 0,8,16,24,32,40,48,56 each get 8 increments. + */ + for (i =3D 0; i < 64; i++) { + uint16_t expected =3D ((i & 7) =3D=3D 0) ? 8 : 0; + check_uint16(__LINE__, i, result.uh[i], expected); + } +} + +/* + * Test vwhist256:sat -- saturating variant. + * Use weight=3D0xFF to test that saturation to 0xFFFF works. + */ +static void test_vwhist256_sat(void) +{ + int i; + + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0xFF00; /* weight=3D0xFF, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist256:sat\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result) + : "v0", "v12", "memory"); + + /* + * Same distribution as vwhist256: elements 0,8,16,...,56. + * Each gets 8 * 0xFF =3D 2040 =3D 0x7F8 (within uint16 range). + */ + for (i =3D 0; i < 64; i++) { + uint16_t expected =3D ((i & 7) =3D=3D 0) ? 8 * 0xFF : 0; + check_uint16(__LINE__, i, result.uh[i], expected); + } +} + +/* + * Test vwhist128: 128-bin histogram with 32-bit accumulation. + * bucket bits [7:3] -> vindex, [2:1] + lane -> element (word granularity). + */ +static void test_vwhist128(void) +{ + int i; + + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0x0100; /* weight=3D1, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist128\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result) + : "v0", "v12", "memory"); + + /* + * 128-bin: 64 halfwords all targeting bucket 0. + * bucket 0 -> vindex=3D0, elindex based on (i>>1)&(~3) | (bucket>>1)&= 3. + * With bucket=3D0, elindex =3D (i>>1)&(~3). + * For i=3D0,1: elindex=3D0; i=3D2,3: elindex=3D0; ... up to i=3D6,7: = elindex=3D0 + * i ranges 0..63. (i>>1) ranges 0..31. + * (i>>1)&(~3) =3D 0,0,0,0,4,4,4,4,8,... + * So elements 0,4,8,12,16,20,24,28 each get 8 increments. + */ + for (i =3D 0; i < 32; i++) { + uint32_t expected =3D ((i & 3) =3D=3D 0) ? 8 : 0; + check_uint32(__LINE__, i, result.uw[i], expected); + } +} + +/* + * Test vwhist128(#0) -- masked variant. + * Only processes elements where (bucket & 1) =3D=3D mode. + */ +static void test_vwhist128m(void) +{ + int i; + + /* All bucket=3D0, weight=3D1. bucket&1=3D=3D0, so mode=3D0 matches a= ll. */ + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0x0100; /* weight=3D1, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist128(#0)\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result) + : "v0", "v12", "memory"); + + /* Same distribution as vwhist128 since all buckets have bit0=3D0 */ + for (i =3D 0; i < 32; i++) { + uint32_t expected =3D ((i & 3) =3D=3D 0) ? 8 : 0; + check_uint32(__LINE__, i, result.uw[i], expected); + } + + /* Now test with mode=3D1: bucket=3D0 has bit0=3D0, so nothing should = match */ + memset(&result, 0, sizeof(result)); + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist128(#1)\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result) + : "v0", "v12", "memory"); + + for (i =3D 0; i < 32; i++) { + check_uint32(__LINE__, i, result.uw[i], 0); + } +} + +static MMVector ones_vec __attribute__((aligned(MAX_VEC_SIZE_BYTES))); + +/* + * Test vwhist256(Qv4) -- Q-masked vwhist256. + * Set Q0 to all-ones so all elements pass the mask -> same as vwhist256. + */ +static void test_vwhist256q(void) +{ + int i; + + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0x0100; /* weight=3D1, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "v1 =3D vmem(%[ones] + #0)\n\t" + "q0 =3D vcmp.eq(v1.b, v1.b)\n\t" /* all-ones Q0 */ + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist256(q0)\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result), [ones] "r"(&ones_vec) + : "v0", "v1", "v12", "q0", "memory"); + + for (i =3D 0; i < 64; i++) { + uint16_t expected =3D ((i & 7) =3D=3D 0) ? 8 : 0; + check_uint16(__LINE__, i, result.uh[i], expected); + } +} + +/* + * Test vwhist256(Qv4):sat -- Q-masked saturating vwhist256. + */ +static void test_vwhist256q_sat(void) +{ + int i; + + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0xFF00; /* weight=3D0xFF, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "v1 =3D vmem(%[ones] + #0)\n\t" + "q0 =3D vcmp.eq(v1.b, v1.b)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist256(q0):sat\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result), [ones] "r"(&ones_vec) + : "v0", "v1", "v12", "q0", "memory"); + + for (i =3D 0; i < 64; i++) { + uint16_t expected =3D ((i & 7) =3D=3D 0) ? 8 * 0xFF : 0; + check_uint16(__LINE__, i, result.uh[i], expected); + } +} + +/* + * Test vwhist128(Qv4) -- Q-masked vwhist128. + */ +static void test_vwhist128q(void) +{ + int i; + + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0x0100; /* weight=3D1, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "v1 =3D vmem(%[ones] + #0)\n\t" + "q0 =3D vcmp.eq(v1.b, v1.b)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist128(q0)\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result), [ones] "r"(&ones_vec) + : "v0", "v1", "v12", "q0", "memory"); + + for (i =3D 0; i < 32; i++) { + uint32_t expected =3D ((i & 3) =3D=3D 0) ? 8 : 0; + check_uint32(__LINE__, i, result.uw[i], expected); + } +} + +/* + * Test vwhist128(Qv4,#0) -- Q-masked mode vwhist128. + */ +static void test_vwhist128qm(void) +{ + int i; + + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0x0100; /* weight=3D1, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "v1 =3D vmem(%[ones] + #0)\n\t" + "q0 =3D vcmp.eq(v1.b, v1.b)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist128(q0,#0)\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result), [ones] "r"(&ones_vec) + : "v0", "v1", "v12", "q0", "memory"); + + /* bucket=3D0, bit0=3D0, mode=3D0 matches -> same as vwhist128 */ + for (i =3D 0; i < 32; i++) { + uint32_t expected =3D ((i & 3) =3D=3D 0) ? 8 : 0; + check_uint32(__LINE__, i, result.uw[i], expected); + } +} + +int main(void) +{ + memset(&zero_vec, 0, sizeof(zero_vec)); + memset(&ones_vec, 0xff, sizeof(ones_vec)); + + test_vwhist256(); + test_vwhist256_sat(); + test_vwhist128(); + test_vwhist128m(); + test_vwhist256q(); + test_vwhist256q_sat(); + test_vwhist128q(); + test_vwhist128qm(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build index fcf0bd38f26..4c70875034d 100644 --- a/tests/tcg/hexagon/meson.build +++ b/tests/tcg/hexagon/meson.build @@ -94,6 +94,7 @@ tests +=3D { 'test_vminh.S': {'cflags': asmflags}, 'test_vpmpyh.S': {'cflags': asmflags}, 'test_vspliceb.S': {'cflags': asmflags}, + 'test_vwhist.c': {'cflags': [cflags, '-mhvx']}, 'unaligned_pc.c': {'cflags': cflags}, 'unaligned_data.c': {'cflags': cflags}, 'usr.c': { --=20 2.34.1 From nobody Sat Sep 26 20:00:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788631909; cv=none; d=zohomail.com; s=zohoarc; b=PkLtRTdzN2ItZy8wfJmTsQlrmG3rUE7Q0lTXiaKqqvkgLQetwlq/cWSjP2hZZYWwDvo86t1XDs8juRndKYkYxGqWJOKwVtMTD1JLzMiktPyGO8D1mE1KUQUHHceBspZEt/TT9ptldjVJZz86IaXp4hXPXeTjazNiOrm49BrtLNQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788631909; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JDD8jh7duwunX0oSZc151pc7fMyJr/NjP+j+FOXU82g=; b=f96AfUnlfv94eMxSzoL/kSA+R49ffw8IVeJbVMEJHmQFSW3RIyATfOCgbtDmBncbbZwYy8nwTgbH8lHGJzpqI4bNrN7h8HLvwqYVikT/5ALK0nc4+tv3ehU268eQHOXzfvigb0jO4HR6GUHyqHoYwMQwP7zjooIlUghpDYNDkpE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788631908386746.3737977688711; Sat, 5 Sep 2026 11:11:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x2uqd-0002xr-Jt; Sat, 05 Sep 2026 14:10:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uqQ-0002sc-4L for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:27 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x2uqM-0001e3-2g for qemu-devel@nongnu.org; Sat, 05 Sep 2026 14:10:24 -0400 Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 685HbelI1775030 for ; Sat, 5 Sep 2026 18:10:20 GMT Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ggc8j9u40-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Sat, 05 Sep 2026 18:10:19 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2d52734fc41so38022075ad.1 for ; Sat, 05 Sep 2026 11:10:19 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631910382158500 Add edge case tests for the sfrecipa instruction Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- tests/tcg/hexagon/fpstuff.c | 81 +++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c index 7561f31cdc3..f82262ab4ac 100644 --- a/tests/tcg/hexagon/fpstuff.c +++ b/tests/tcg/hexagon/fpstuff.c @@ -345,6 +345,86 @@ static void check_sfrecipa(void) check32(pred, 0x80); } =20 +/* + * Helper to run sfrecipa and capture result + USR. + */ +static void do_sfrecipa(uint32_t Rs, uint32_t Rt, + uint32_t *Rd, uint32_t *usr_out) +{ + uint32_t rd, usr; + + asm volatile(CLEAR_FPSTATUS + "%[rd],p0 =3D sfrecipa(%[Rs], %[Rt])\n\t" + "%[usr] =3D usr\n\t" + : [rd] "=3Dr"(rd), [usr] "=3Dr"(usr) + : [Rs] "r"(Rs), [Rt] "r"(Rt) + : "p0", "r2", "usr"); + *Rd =3D rd; + *usr_out =3D usr; +} + +/* + * Additional sfrecipa edge cases: + * - inf/inf, 0/0 -> NaN + invalid + * - normal/inf, 0/normal, inf/normal + * - denominator with extreme biased exponents + */ +static void check_sfrecipa_edges(void) +{ + uint32_t rd, usr; + + /* inf / inf -> invalid */ + do_sfrecipa(SF_INF, SF_INF, &rd, &usr); + check_fpstatus(usr, USR_FPINVF); + + /* -inf / +inf -> invalid */ + do_sfrecipa(0xff800000, SF_INF, &rd, &usr); + check_fpstatus(usr, USR_FPINVF); + + /* 0 / 0 -> invalid */ + do_sfrecipa(SF_zero, SF_zero, &rd, &usr); + check_fpstatus(usr, USR_FPINVF); + + /* -0 / +0 -> invalid */ + do_sfrecipa(SF_zero_neg, SF_zero, &rd, &usr); + check_fpstatus(usr, USR_FPINVF); + + /* normal / inf -> fixup (Rd =3D 1.0) */ + do_sfrecipa(SF_one, SF_INF, &rd, &usr); + check32(rd, SF_one); + + do_sfrecipa(SF_two, SF_INF, &rd, &usr); + check32(rd, SF_one); + + /* 0 / normal -> fixup (Rd =3D 1.0) */ + do_sfrecipa(SF_zero, SF_one, &rd, &usr); + check32(rd, SF_one); + + do_sfrecipa(SF_zero_neg, SF_two, &rd, &usr); + check32(rd, SF_one); + + /* inf / normal -> fixup (Rd =3D 1.0) */ + do_sfrecipa(SF_INF, SF_one, &rd, &usr); + check32(rd, SF_one); + + do_sfrecipa(0xff800000, SF_two, &rd, &usr); + check32(rd, SF_one); + + /* + * Denominator with biased exponent <=3D 1. + * Rs: biased exp 26, Rt: biased exp 1. + */ + do_sfrecipa(26U << 23, 1U << 23, &rd, &usr); + check32_ne(rd, 0); + + /* + * Denominator with biased exponent > 252. + * Both: biased exp 253. + */ + do_sfrecipa(253U << 23, 253U << 23, &rd, &usr); + check32_ne(rd, 0); +} + static void check_canonical_NaN(void) { uint32_t sf_result; @@ -887,6 +967,7 @@ int main() check_sfminmax(); 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Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- tests/tcg/hexagon/fpstuff.c | 57 +++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c index f82262ab4ac..0f28a218d84 100644 --- a/tests/tcg/hexagon/fpstuff.c +++ b/tests/tcg/hexagon/fpstuff.c @@ -935,6 +935,16 @@ static uint64_t do_dfmpyfix(uint64_t a, uint64_t b) return result; } =20 +static uint64_t do_dfmpyhh(uint64_t a, uint64_t b, uint64_t acc) +{ + uint64_t result =3D acc; + + asm("%[res] +=3D dfmpyhh(%[a], %[b])\n\t" + : [res] "+r"(result) + : [a] "r"(a), [b] "r"(b)); + return result; +} + static void check_dfmpyfix(void) { /* @@ -961,6 +971,52 @@ static void check_dfmpyfix(void) 0x0010000000000000ULL); } =20 +/* + * Test dfmpyhh (double-precision FP multiply high*high and accumulate): + * - normal inputs + * - denormal inputs (crushed to inexact zero) + * - zero/NaN/infinity inputs + * - nonzero accumulator + */ +static inline uint64_t df_abs(uint64_t v) { return v & 0x7FFFFFFFFFFFFFFFU= LL; } +static inline uint64_t df_exp(uint64_t v) { return v & 0x7FF0000000000000U= LL; } +static inline uint64_t df_mant(uint64_t v) { return v & 0x000FFFFFFFFFFFFF= ULL; } + +static void check_dfmpyhh(void) +{ + uint64_t result; + + /* Normal * normal: 1.0 * 1.0 + 0 -> nonzero finite */ + result =3D do_dfmpyhh(DF_one, DF_one, 0ULL); + check64_ne(df_abs(result), 0ULL); + + /* Denormal input a: crushed to zero */ + result =3D do_dfmpyhh(0x0008000000000000ULL, DF_one, 0ULL); + check64(df_abs(result), 0ULL); + + /* Denormal input b: crushed to zero */ + result =3D do_dfmpyhh(DF_one, 0x0008000000000000ULL, 0ULL); + check64(df_abs(result), 0ULL); + + /* Zero input: early exit */ + result =3D do_dfmpyhh(DF_zero, DF_one, 0ULL); + check64(df_abs(result), 0ULL); + + /* Infinity input: early exit, result contains inf */ + result =3D do_dfmpyhh(0x7FF0000000000000ULL, DF_one, 0ULL); + check64(df_exp(result), 0x7FF0000000000000ULL); + + /* NaN input: early exit, result is NaN */ + result =3D do_dfmpyhh(DF_QNaN, DF_one, 0ULL); + check64(df_exp(result), 0x7FF0000000000000ULL); + check64_ne(df_mant(result), 0ULL); + + /* Nonzero accumulator: nonzero finite result */ + result =3D do_dfmpyhh(DF_one, DF_one, DF_one); + check64_ne(df_abs(result), 0ULL); + check64_ne(df_exp(result), 0x7FF0000000000000ULL); +} + int main() { check_compare_exception(); @@ -981,6 +1037,7 @@ int main() check_conv_uw2df(); check_conv_ud2df(); check_dfmpyfix(); + check_dfmpyhh(); =20 puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631922351158500 Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- tests/tcg/hexagon/misc.c | 44 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c index ca22bb79f7b..c07547b6f68 100644 --- a/tests/tcg/hexagon/misc.c +++ b/tests/tcg/hexagon/misc.c @@ -404,6 +404,48 @@ void test_dpmpyss_rnd_s0(void) check32(dpmpyss_rnd_s0(0x7fffffff, 0x7fffffff), 0x3fffffff); } =20 +static uint8_t storeimm_byte_array[16]; +static uint16_t storeimm_half_array[16]; +static uint32_t storeimm_word_array[16]; + +/* + * Unconditional store-immediate instructions (S4_storeir*_io). + * The predicated forms are tested above; these exercise the base encoding + * with positive and negative #S8 immediate values. + */ +static void check_store_imm(void) +{ + /* memb(Rs+#u6:0) =3D #S8 */ + memset(storeimm_byte_array, 0, sizeof(storeimm_byte_array)); + asm volatile("memb(%[ptr] + #0) =3D #0x12\n\t" + : : [ptr] "r"(storeimm_byte_array) : "memory"); + check32(storeimm_byte_array[0], 0x12); + + asm volatile("memb(%[ptr] + #3) =3D #-1\n\t" + : : [ptr] "r"(storeimm_byte_array) : "memory"); + check32(storeimm_byte_array[3], 0xff); + + /* memh(Rs+#u6:1) =3D #S8 */ + memset(storeimm_half_array, 0, sizeof(storeimm_half_array)); + asm volatile("memh(%[ptr] + #0) =3D #0x34\n\t" + : : [ptr] "r"(storeimm_half_array) : "memory"); + check32(storeimm_half_array[0], 0x34); + + asm volatile("memh(%[ptr] + #4) =3D #-1\n\t" + : : [ptr] "r"(storeimm_half_array) : "memory"); + check32(storeimm_half_array[2], 0xffff); + + /* memw(Rs+#u6:2) =3D #S8 */ + memset(storeimm_word_array, 0, sizeof(storeimm_word_array)); + asm volatile("memw(%[ptr] + #0) =3D #0x56\n\t" + : : [ptr] "r"(storeimm_word_array) : "memory"); + check32(storeimm_word_array[0], 0x56); + + asm volatile("memw(%[ptr] + #8) =3D #-1\n\t" + : : [ptr] "r"(storeimm_word_array) : "memory"); + check32(storeimm_word_array[2], 0xffffffff); +} + int main() { int32_t res; @@ -547,6 +589,8 @@ int main() =20 test_dpmpyss_rnd_s0(); =20 + check_store_imm(); + puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631861414154100 Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- tests/tcg/hexagon/misc.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c index c07547b6f68..abb34ab6a65 100644 --- a/tests/tcg/hexagon/misc.c +++ b/tests/tcg/hexagon/misc.c @@ -446,6 +446,31 @@ static void check_store_imm(void) check32(storeimm_word_array[2], 0xffffffff); } =20 +/* + * Rd =3D Ps -- transfer predicate register to general register. + * The result is 0x00 or 0xff depending on the predicate value. + */ +static void check_preg_transfer(void) +{ + uint32_t result; + + /* Set p0 =3D true, then Rd =3D p0 should give 0xff */ + asm volatile("p0 =3D cmp.eq(%[val], %[val])\n\t" + "%[res] =3D p0\n\t" + : [res] "=3Dr"(result) + : [val] "r"(1) + : "p0"); + check32(result, 0xff); + + /* Set p0 =3D false, then Rd =3D p0 should give 0x00 */ + asm volatile("p0 =3D cmp.eq(%[a], %[b])\n\t" + "%[res] =3D p0\n\t" + : [res] "=3Dr"(result) + : [a] "r"(1), [b] "r"(2) + : "p0"); + check32(result, 0x00); +} + int main() { int32_t res; @@ -590,6 +615,7 @@ int main() test_dpmpyss_rnd_s0(); =20 check_store_imm(); + check_preg_transfer(); =20 puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631864676158500 Add round-to-nearest float-to-int conversion tests for the non-:chop varian= ts, sfmpy:lib with Inf-Inf to verify exception suppression, and sfinvsqrta with a denormal input. Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- tests/tcg/hexagon/fpstuff.c | 99 +++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c index 0f28a218d84..9ea79c617d9 100644 --- a/tests/tcg/hexagon/fpstuff.c +++ b/tests/tcg/hexagon/fpstuff.c @@ -1017,6 +1017,102 @@ static void check_dfmpyhh(void) check64_ne(df_exp(result), 0x7FF0000000000000ULL); } =20 +/* + * Round-to-nearest float-to-int conversions with normal values. + * These test the non-:chop variants which use the USR rounding mode. + */ +static void check_conv_rnd(void) +{ + uint32_t res32; + uint64_t res64; + + /* convert_sf2w(1.5) rounds to nearest-even =3D 2 */ + asm(CLEAR_FPSTATUS + "%[res] =3D convert_sf2w(%[val])\n\t" + : [res] "=3Dr"(res32) + : [val] "r"(0x3fc00000) /* 1.5f */ + : "r2", "usr"); + check32(res32, 2); + + /* convert_sf2d(1.5) =3D 2 */ + asm(CLEAR_FPSTATUS + "%[res] =3D convert_sf2d(%[val])\n\t" + : [res] "=3Dr"(res64) + : [val] "r"(0x3fc00000) /* 1.5f */ + : "r2", "usr"); + check64(res64, 2ULL); + + /* convert_df2w(1.5) =3D 2 */ + asm(CLEAR_FPSTATUS + "%[res] =3D convert_df2w(%[val])\n\t" + : [res] "=3Dr"(res32) + : [val] "r"(0x3FF8000000000000ULL) /* 1.5 */ + : "r2", "usr"); + check32(res32, 2); + + /* convert_df2d(1.5) =3D 2 */ + asm(CLEAR_FPSTATUS + "%[res] =3D convert_df2d(%[val])\n\t" + : [res] "=3Dr"(res64) + : [val] "r"(0x3FF8000000000000ULL) /* 1.5 */ + : "r2", "usr"); + check64(res64, 2ULL); +} + +/* + * Test sfmpy:lib with Inf-Inf. + * + * Rx +=3D sfmpy(Rs, Rt):lib with Rx =3D -Inf, Rs*Rt -> +Inf + * Inf - Inf is invalid, but the :lib variant suppresses the + * exception and returns zero. + */ +static void check_sffma_lib_inf(void) +{ + uint32_t result; + + /* +Inf +=3D sfmpy(+Inf, 1.0):lib -> Inf (no exception, normal) */ + result =3D SF_INF; + asm(CLEAR_FPSTATUS + "%[res] +=3D sfmpy(%[a], %[b]):lib\n\t" + : [res] "+r"(result) + : [a] "r"(SF_INF), [b] "r"(SF_one) + : "r2", "usr"); + check32(result, SF_INF); + + /* + * -Inf +=3D sfmpy(+Inf, 1.0):lib -> Inf - Inf =3D invalid + * The :lib variant should return zero for Inf - Inf. + */ + result =3D SF_INF | (1u << 31); /* -Inf */ + asm(CLEAR_FPSTATUS + "%[res] +=3D sfmpy(%[a], %[b]):lib\n\t" + : [res] "+r"(result) + : [a] "r"(SF_INF), [b] "r"(SF_one) + : "r2", "usr"); + check32(result, 0); +} + +/* + * Test sfinvsqrta with a denormal input. + */ +static void check_invsqrta_denorm(void) +{ + uint32_t result; + uint32_t predval; + uint32_t exp_bits; + + /* Denormal positive float: 0x00400000 (small denorm) */ + asm volatile("%[res],p0 =3D sfinvsqrta(%[val])\n\t" + "%[pred] =3D p0\n\t" + : [res] "=3Dr"(result), [pred] "=3Dr"(predval) + : [val] "r"(SF_denorm) + : "p0"); + /* Result should be a valid float (not NaN/zero) */ + check32_ne(result, 0); + exp_bits =3D (result >> 23) & 0xff; + check32_ne(exp_bits, 0xff); /* not Inf/NaN */ +} + int main() { check_compare_exception(); @@ -1038,6 +1134,9 @@ int main() check_conv_ud2df(); check_dfmpyfix(); check_dfmpyhh(); + check_conv_rnd(); + check_sffma_lib_inf(); + check_invsqrta_denorm(); =20 puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631922352158500 Test a packet with both a scalar store and an HVX store, and test a non-inverted masked store (if (q0) vmem) to verify the invert=3Dfalse path in masked store generation. Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- tests/tcg/hexagon/hvx_misc.c | 66 ++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c index f20afc8e670..0285886c2a5 100644 --- a/tests/tcg/hexagon/hvx_misc.c +++ b/tests/tcg/hexagon/hvx_misc.c @@ -566,6 +566,69 @@ void test_store_new() check_output_w(__LINE__, 1); } =20 +/* + * Test a packet with both a scalar store and an HVX store. + */ +static uint32_t scalar_store_dst; + +static void test_scalar_hvx_store(void) +{ + scalar_store_dst =3D 0; + memset(&expect[0], 0, sizeof(MMVector)); + + /* Fill v0 with 0xABCD pattern */ + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + expect[0].uw[i] =3D 0xABCDABCD; + } + + asm("r0 =3D #0xABCDABCD\n\t" + "v0 =3D vsplat(r0)\n\t" + "r1 =3D #42\n\t" + "{\n\t" + " memw(%[scalar]) =3D r1\n\t" + " vmem(%[hvx]) =3D v0\n\t" + "}\n\t" + : + : [scalar] "r"(&scalar_store_dst), + [hvx] "r"(&output[0]) + : "r0", "r1", "v0", "memory"); + + check_output_w(__LINE__, 1); + if (scalar_store_dst !=3D 42) { + printf("ERROR at line %d: scalar_store_dst =3D %d, expected 42\n", + __LINE__, scalar_store_dst); + err++; + } +} + +/* + * Test non-inverted masked store: if (Qv) vmem(Rt) =3D Vs. + * Existing tests only cover the inverted form (!Qv). + * Use an all-true Q predicate to unconditionally store. + */ +static void test_masked_store_noninvert(void) +{ + void *p0 =3D buffer0; + void *pout =3D output; + + memset(&output[0], 0xff, sizeof(MMVector)); + + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + expect[0].uw[i] =3D buffer0[0].uw[i]; + } + + asm("v5 =3D vmem(%[src] + #0)\n\t" + "r0 =3D #-1\n\t" + "v6 =3D vsplat(r0)\n\t" + "q0 =3D vand(v6, r0)\n\t" + "if (q0) vmem(%[dst]) =3D v5\n\t" + : + : [src] "r"(p0), [dst] "r"(pout) + : "r0", "v5", "v6", "q0", "memory"); + + check_output_w(__LINE__, 1); +} + int main() { init_buffers(); @@ -615,6 +678,9 @@ int main() =20 test_store_new(); =20 + test_scalar_hvx_store(); + test_masked_store_noninvert(); + puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788631869914154100 Add a decbin test vector exercising the MPS case Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- tests/tcg/hexagon/misc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c index abb34ab6a65..08845201b59 100644 --- a/tests/tcg/hexagon/misc.c +++ b/tests/tcg/hexagon/misc.c @@ -599,6 +599,15 @@ int main() res64 =3D decbin(0xfLL, 0x1bLL, &pred); check64(res64, 0x78000100LL); check32(pred, true); + + /* + * Test the MPS (most-probable symbol) case in decbin. + * Rss: word0=3Drange=3D0xFF800000, word1=3Doffset=3D0x00000000 + * Rtt: word0=3Dbitpos=3D0, word1=3Dstate=3D0|valMPS=3D1(bit8) + */ + res64 =3D decbin(0x00000000FF800000LL, 0x0000010000000000LL, &pred); + check64(res64, 0x0000000087800101LL); + check32(pred, true); #else puts("Skipping cabac tests"); #endif --=20 2.34.1