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Sat, 05 Sep 2026 02:28:38 -0700 (PDT) From: Zephyr Li To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Zephyr Li Subject: [PATCH] target/riscv: fix RV32 fixed counter accesses Date: Sat, 5 Sep 2026 17:28:10 +0800 Message-ID: <20260905092810.660-1-fritchleybohrer@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::b; envelope-from=fritchleybohrer@gmail.com; helo=mail-pj2-x0b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788600580190158500 Content-Type: text/plain; charset="utf-8" Since commit cfc96df65e01, riscv_pmu_ctr_get_fixed_counters_val() returns the complete 64-bit fixed-counter value. The RV32 counter access paths, however, still perform parts of the offset calculation on separately extracted 32-bit halves. In particular, riscv_pmu_write_ctrh() deposits the low 32 bits of the complete fixed-counter value into the high half of mhpmcounter_prev. riscv_pmu_read_ctr() also subtracts a 32-bit half of the previous value from the complete 64-bit fixed-counter value. Consequently, writes to mcycleh can be lost and carries between the low and high halves are not handled correctly. Keep the fixed-counter offset calculation entirely in 64 bits. Before a running counter is partially written, materialize its current architectural value and reset the fixed-counter baseline. On reads, calculate the complete 64-bit counter value before extracting the half requested by RV32. Add an RV32 system TCG test for high-half writes, low-to-high carry, and preserving the carried high half across a subsequent low-half write. Fixes: cfc96df65e01 ("target/riscv: Remove upper_half from riscv_pmu_ctr_ge= t_fixed_counters_val") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4219 Signed-off-by: Zephyr Li Reviewed-by: Daniel Henrique Barboza --- target/riscv/tcg/csr.c | 32 ++++++++-------- tests/tcg/riscv64/Makefile.softmmu-target | 12 ++++++ tests/tcg/riscv64/test-mcycle-rv32.S | 45 +++++++++++++++++++++++ 3 files changed, 74 insertions(+), 15 deletions(-) create mode 100644 tests/tcg/riscv64/test-mcycle-rv32.S diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 002f7e69c1..ffdd5c4aa6 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -1337,23 +1337,23 @@ static RISCVException riscv_pmu_write_ctr(CPURISCVS= tate *env, target_ulong val, int deposit_size =3D rv32 ? 32 : 64; uint64_t ctr; =20 - counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, - 0, deposit_size, val); - if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { ctr =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx); - counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, - 0, deposit_size, ctr); + counter->mhpmcounter_val +=3D ctr - counter->mhpmcounter_prev; + counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, + 0, deposit_size, val); + counter->mhpmcounter_prev =3D ctr; if (ctr_idx > 2) { riscv_pmu_setup_timer(env, counter->mhpmcounter_val, ctr_idx); } } else { + counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, + 0, deposit_size, val); /* Other counters can keep incrementing from the given value */ counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, 0, deposit_size, val); - } =20 return RISCV_EXCP_NONE; @@ -1363,20 +1363,22 @@ static RISCVException riscv_pmu_write_ctrh(CPURISCV= State *env, target_ulong val, uint32_t ctr_idx) { PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - uint64_t ctrh; + uint64_t ctr; =20 - counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, - 32, 32, val); if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { - ctrh =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx); - counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, - 32, 32, ctrh); + ctr =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx); + counter->mhpmcounter_val +=3D ctr - counter->mhpmcounter_prev; + counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, + 32, 32, val); + counter->mhpmcounter_prev =3D ctr; if (ctr_idx > 2) { riscv_pmu_setup_timer(env, counter->mhpmcounter_val, ctr_idx); } } else { + counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, + 32, 32, val); counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, 32, 32, val); } @@ -1407,12 +1409,11 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState *en= v, target_ulong *val, bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32; int start =3D upper_half ? 32 : 0; int length =3D rv32 ? 32 : 64; - uint64_t ctr_prev, ctr_val; + uint64_t ctr_val; =20 /* Ensure upper_half is only set for XLEN =3D=3D 32 */ g_assert(rv32 || !upper_half); =20 - ctr_prev =3D extract64(counter->mhpmcounter_prev, start, length); ctr_val =3D extract64(counter->mhpmcounter_val, start, length); =20 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { @@ -1431,7 +1432,8 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState *env,= target_ulong *val, if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { uint64_t cntr =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_id= x) - - ctr_prev + ct= r_val; + counter->mhpmcounter_prev + + counter->mhpmcounter_val; *val =3D extract64(cntr, start, length); } else { *val =3D ctr_val; diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/= Makefile.softmmu-target index 6a219c306c..15c7371acd 100644 --- a/tests/tcg/riscv64/Makefile.softmmu-target +++ b/tests/tcg/riscv64/Makefile.softmmu-target @@ -28,6 +28,18 @@ EXTRA_RUNS +=3D run-test-minstret-ecall run-test-minstret-ecall: test-minstret-ecall $(call run-test, $<, $(QEMU) -icount shift=3D1 $(QEMU_OPTS)$<) =20 +RV32_CFLAGS =3D -march=3Drv32im_zicsr -mabi=3Dilp32 +CLEANFILES +=3D test-mcycle-rv32 + +test-mcycle-rv32: test-mcycle-rv32.S $(LINK_SCRIPT) + $(CC) $(CFLAGS) $(RV32_CFLAGS) $< -Wa,--noexecstack -c -o $@.o + $(LD) -m elf32lriscv $(LDFLAGS) $@.o -o $@ + +EXTRA_RUNS +=3D run-test-mcycle-rv32 +run-test-mcycle-rv32: test-mcycle-rv32 + $(call run-test, $<, \ + $(QEMU) -cpu rv32 -icount shift=3D1 $(QEMU_OPTS)$<) + EXTRA_RUNS +=3D run-plugin-doubletrap run-plugin-doubletrap: doubletrap $(call run-test, $<, \ diff --git a/tests/tcg/riscv64/test-mcycle-rv32.S b/tests/tcg/riscv64/test-= mcycle-rv32.S new file mode 100644 index 0000000000..189d1e13a2 --- /dev/null +++ b/tests/tcg/riscv64/test-mcycle-rv32.S @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + + .option norvc + + .text + .global _start +_start: + /* Exercise writes while mcycle is running. */ + csrw mcountinhibit, zero + csrw mcycle, zero + + /* A write to the high half must be immediately observable. */ + li s0, 0x1234ffff + csrw mcycleh, s0 + csrr t0, mcycleh + bne t0, s0, fail + + /* Check carry from the low half into the high half. */ + li s0, 0x12345678 + csrw mcycleh, s0 + li t0, 0xfffffff0 + csrw mcycle, t0 + .rept 32 + nop + .endr + csrr t0, mcycleh + addi s0, s0, 1 + bne t0, s0, fail + + /* A low-half write must preserve the carried high half. */ + li t0, 0x22222222 + csrw mcycle, t0 + csrr t0, mcycleh + bne t0, s0, fail + + li t0, 0x100000 + li t1, 0x5555 /* FINISHER_PASS */ + sw t1, 0(t0) + j . + +fail: + li t0, 0x100000 + li t1, 0x13333 /* status =3D FINISHER_FAIL, code =3D 1 */ + sw t1, 0(t0) + j . --=20 2.43.0