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Thu, 03 Sep 2026 22:19:56 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis Subject: [PULL 01/47] target/riscv: split 'debug' and 'sdtrig' flags Date: Fri, 4 Sep 2026 15:18:57 +1000 Message-ID: <20260904051943.799041-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=alistair23@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499459148158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We need to support modern debug extensions that happens to be dependencies of other things that we want to support (e.g. a riscv server spec board). These extensions, namely sdext, depends on Debug 1.0. At this moment we support Debug 0.13, and so it happens that 0.13 and 1.0 aren't backwards compatible, i.e. we need design changes to support both. The easier way is to deprecate the Debug 0.13 support, together with its legacy 'debug' flag and call it a day. But there's a demand to keep the 0.13 support around and this idea got scrapped. We're going to support both 0.13 and 1.0, where the 'debug' flag will refer to 0.13 and 'sdtrig' to 1.0. We need to split both in distinct flags first to handle the backend changes, so: - add a new cpu->cfg.ext_sdtrig flag; - all code that checks "if debug enabled" now checks for both debug and ext_sdtrig; - amend riscv_isa_string_ext() to keep adding 'sdtrig' in riscv,isa if we have just the 'debug' flag enabled. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20260805182506.2943757-2-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/cpu.c | 21 ++++++++++++++++----- target/riscv/machine.c | 2 +- target/riscv/tcg/csr.c | 2 +- target/riscv/tcg/tcg-cpu.c | 3 ++- 5 files changed, 21 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index f8c27a574f..f91c780299 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -105,6 +105,7 @@ BOOL_FIELD(ext_zvfbfmin) BOOL_FIELD(ext_zvfbfwma) BOOL_FIELD(ext_zvfh) BOOL_FIELD(ext_zvfhmin) +BOOL_FIELD(ext_sdtrig) BOOL_FIELD(ext_smaia) BOOL_FIELD(ext_ssaia) BOOL_FIELD(ext_smctr) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fd1afbc7fe..a760ba3a52 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -248,7 +248,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), - ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug), + ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig), ISA_INTERNAL_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_INTERNAL_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha), @@ -1091,7 +1091,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTy= pe type) =20 #ifndef CONFIG_USER_ONLY #ifdef CONFIG_TCG - if (cpu->cfg.debug) { + if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) { riscv_trigger_reset_hold(env); } #endif @@ -1331,7 +1331,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) riscv_cpu_register_gdb_regs_for_features(cs); =20 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - if (cpu->cfg.debug) { + if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) { riscv_trigger_realize(&cpu->env); } #endif @@ -1348,7 +1348,7 @@ static void riscv_cpu_unrealize(DeviceState *dev) #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) RISCVCPU *cpu =3D RISCV_CPU(dev); =20 - if (cpu->cfg.debug) { + if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) { riscv_trigger_unrealize(&cpu->env); } #endif @@ -2925,6 +2925,11 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rul= es[] =3D { }; =20 static const Property riscv_cpu_properties[] =3D { + /* + * The 'debug' flag enables support for the legacy Debug + * 0.13 spec. In case cpu->ext.ext_sdtrig is also enabled + * the CPU will enable Debug 1.0 instead. + */ DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), DEFINE_PROP_BOOL("big-endian", RISCVCPU, cfg.big_endian, false), =20 @@ -3146,7 +3151,13 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char= **isa_str, char *new =3D *isa_str; =20 for (edata =3D isa_edata_arr; edata && edata->name; edata++) { - if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) + /* + * We've been adding 'sdtrig' in riscv,isa for + * Debug 0.13 for awhile. Until we decide to + * move away from it we'll keep doing it. + */ + || (!g_strcmp0(edata->name, "sdtrig") && cpu->cfg.debug)) { new =3D g_strconcat(old, "_", edata->name, NULL); g_free(old); old =3D new; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c3f5a25509..bf203bffce 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -268,7 +268,7 @@ static bool debug_needed(void *opaque) { RISCVCPU *cpu =3D opaque; =20 - return cpu->cfg.debug; + return cpu->cfg.debug || cpu->cfg.ext_sdtrig; } =20 static int debug_post_load(void *opaque, int version_id) diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 002f7e69c1..bd4b6dc114 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -804,7 +804,7 @@ static RISCVException have_mseccfg(CPURISCVState *env, = int csrno) =20 static RISCVException debug(CPURISCVState *env, int csrno) { - if (riscv_cpu_cfg(env)->debug) { + if (riscv_cpu_cfg(env)->debug || riscv_cpu_cfg(env)->ext_sdtrig) { return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 9e3cc87f8a..54f1b66216 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -182,7 +182,8 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *c= s) ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; } =20 - if (cpu->cfg.debug && !icount_enabled()) { + if ((cpu->cfg.debug || cpu->cfg.ext_sdtrig) + && !icount_enabled()) { flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); } #endif --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499446; cv=none; d=zohomail.com; s=zohoarc; b=JlcMXtXMjIx6iqVtN9QyuLpMKSO9o00nKMb6Y8WWJJFf/dql+IIeK3lVlLuoSo2ucGd5FwQAPMAlnebhhVca2NT8+X8f+hhIgal/nW27yAtlyMa0CMbqQpNxtBsoqDVMd6acHn4p1aa/7mLbiteKzyq8fj1c5v2+yTiYgR7Xklc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788499446; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 03 Sep 2026 22:19:59 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis Subject: [PULL 02/47] target/riscv/tcg/debug.c: add Debug 1.0 'pending' bit Date: Fri, 4 Sep 2026 15:18:58 +1000 Message-ID: <20260904051943.799041-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=alistair23@gmail.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499446997158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We need to set the 'pending' bit when 'count' reaches 0, clearing it right after the trigger fires. This is 1.0 exclusive behavior so no changes are needed when running Debug 0.13. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20260805182506.2943757-3-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/debug.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c index 5ab29f6945..d40db381e6 100644 --- a/target/riscv/tcg/debug.c +++ b/target/riscv/tcg/debug.c @@ -77,6 +77,11 @@ static int access_size[SIZE_NUM] =3D { [6 ... 15] =3D -1, }; =20 +static bool debug_trigger_version_1_0(CPURISCVState *env) +{ + return riscv_cpu_cfg(env)->ext_sdtrig; +} + static inline target_ulong extract_trigger_type(CPURISCVState *env, target_ulong tdata1) { @@ -684,6 +689,17 @@ itrigger_set_count(CPURISCVState *env, int index, int = value) ITRIGGER_COUNT, value); } =20 +static inline void +itrigger_set_pending(CPURISCVState *env, int index, int val) +{ + if (!debug_trigger_version_1_0(env)) { + return; + } + + env->tdata1[index] =3D set_field(env->tdata1[index], + ITRIGGER_PENDING, val); +} + static bool check_itrigger_priv(CPURISCVState *env, int index) { target_ulong tdata1 =3D env->tdata1[index]; @@ -735,8 +751,25 @@ void helper_itrigger_match(CPURISCVState *env) } itrigger_set_count(env, i, count--); if (!count) { + /* + * From the 1.0 spec: "When pending is set, the trigger + * fires just before any further instructions are executed + * in a mode where the trigger is enabled. As the trigger + * fires, pending is cleared." + * + * And: "This bit becomes set when count is decremented + * from 1 to 0. It is cleared when the trigger fires, + * which will happen just before executing the next + * instruction in one of the enabled modes". + * + * Note that itrigger_set_pending() is a no-op if we're + * running debug 0.13. + */ + itrigger_set_pending(env, i, 1); + env->itrigger_enabled =3D riscv_itrigger_enabled(env); do_trigger_action(env, i); + itrigger_set_pending(env, i, 0); } } } --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499447; cv=none; d=zohomail.com; s=zohoarc; b=mjZ7ugK1KQT3ONm2cfyLR85habMg09FeavD5OZQx7Y6XipGJaESDGapTWgIHtB/GXmHV4wkEeIpQ0tvA8QvkooEz0eurTI0OjPHSoeXSvtNk9nO1lEwRO1Uaf70E4qndvxUfvRrXFGRwNVp7fYeKnu5VMxwCPK6nb79cLpiEaGw= ARC-Message-Signature: i=1; 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Thu, 03 Sep 2026 22:20:02 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis Subject: [PULL 03/47] target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0 Date: Fri, 4 Sep 2026 15:18:59 +1000 Message-ID: <20260904051943.799041-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499449026158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Version 1.0 changed the 'timing' bit. It is now bit 18. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20260805182506.2943757-4-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/debug.h | 3 ++- target/riscv/tcg/debug.c | 7 ++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/target/riscv/tcg/debug.h b/target/riscv/tcg/debug.h index a25d099b37..eb635bc277 100644 --- a/target/riscv/tcg/debug.h +++ b/target/riscv/tcg/debug.h @@ -98,7 +98,8 @@ typedef enum { #define TYPE6_CHAIN BIT(11) #define TYPE6_ACTION (0xf << 12) #define TYPE6_SIZE (0xf << 16) -#define TYPE6_TIMING BIT(20) +#define TYPE6_TIMING BIT(18) +#define TYPE6_TIMING_0_13 BIT(20) #define TYPE6_SELECT BIT(21) #define TYPE6_HIT BIT(22) #define TYPE6_VU BIT(23) diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c index d40db381e6..9b2e5b19d8 100644 --- a/target/riscv/tcg/debug.c +++ b/target/riscv/tcg/debug.c @@ -584,10 +584,15 @@ static target_ulong type6_mcontrol6_validate(CPURISCV= State *env, warn_always_zero_bit(ctrl, TYPE6_MATCH, "match"); warn_always_zero_bit(ctrl, TYPE6_CHAIN, "chain"); warn_always_zero_bit(ctrl, TYPE6_ACTION, "action"); - warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing"); warn_always_zero_bit(ctrl, TYPE6_SELECT, "select"); warn_always_zero_bit(ctrl, TYPE6_HIT, "hit"); =20 + if (debug_trigger_version_1_0(env)) { + warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing"); + } else { + warn_always_zero_bit(ctrl, TYPE6_TIMING_0_13, "timing"); + } + /* validate size encoding */ size =3D extract32(ctrl, 16, 4); if (access_size[size] =3D=3D -1) { --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499222; cv=none; d=zohomail.com; s=zohoarc; b=dNSY7mtjVVIYyXLIAJny8lJCQy/a/yvZUg1bUBtA/gCsZUbHduKKIvrkzg2+LpD8eEa5QCv2z54X/HHnMEJ+TM61bJqMGzhgRUh1iHwU2lGv4YZsxl2rqXZVdNteFmrd8LH3zDPN3Ma1TFaUDoFTErt1RB2G1a7fy2wM37Baneo= ARC-Message-Signature: i=1; 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Thu, 03 Sep 2026 22:20:04 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis Subject: [PULL 04/47] target/riscv/tcg/debug: set tinfo version if sdtrig enabled Date: Fri, 4 Sep 2026 15:19:00 +1000 Message-ID: <20260904051943.799041-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=alistair23@gmail.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499224859158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Set 'version' to 1 if we're running Debug 1.0. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20260805182506.2943757-5-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/debug.h | 3 +++ target/riscv/tcg/debug.c | 11 ++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/target/riscv/tcg/debug.h b/target/riscv/tcg/debug.h index eb635bc277..fcd92b768c 100644 --- a/target/riscv/tcg/debug.h +++ b/target/riscv/tcg/debug.h @@ -45,6 +45,9 @@ typedef enum { TRIGGER_TYPE_NUM } trigger_type_t; =20 +#define TINFO_VERSION_OFFSET 24 +#define TINFO_VERSION_LEN 8 + /* actions */ typedef enum { DBG_ACTION_NONE =3D -1, /* sentinel value */ diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c index 9b2e5b19d8..148201f3cb 100644 --- a/target/riscv/tcg/debug.c +++ b/target/riscv/tcg/debug.c @@ -957,9 +957,14 @@ void tdata_csr_write(CPURISCVState *env, int tdata_ind= ex, target_ulong val) =20 target_ulong tinfo_csr_read(CPURISCVState *env) { - /* assume all triggers support the same types of triggers */ - return BIT(TRIGGER_TYPE_AD_MATCH) | - BIT(TRIGGER_TYPE_AD_MATCH6); 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Thu, 03 Sep 2026 22:20:07 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis Subject: [PULL 05/47] docs/specs: add RISC-V CPU Debug support info Date: Fri, 4 Sep 2026 15:19:01 +1000 Message-ID: <20260904051943.799041-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=alistair23@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499242374158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Add documentation regarding how QEMU handles Debug versions 0.13 and 1.0. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20260805182506.2943757-6-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- docs/specs/index.rst | 1 + docs/specs/riscv-debug.rst | 68 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 docs/specs/riscv-debug.rst diff --git a/docs/specs/index.rst b/docs/specs/index.rst index 7c7282b425..44e108db02 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -39,6 +39,7 @@ guest hardware that is specific to QEMU. rocker riscv-iommu riscv-aia + riscv-debug aspeed-intc iommu-testdev s390x-secure-ipl diff --git a/docs/specs/riscv-debug.rst b/docs/specs/riscv-debug.rst new file mode 100644 index 0000000000..e6dcad7d38 --- /dev/null +++ b/docs/specs/riscv-debug.rst @@ -0,0 +1,68 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +.. _riscv-debug: + +RISC-V Debug support for RISC-V CPUs +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Up until QEMU version 11.1 RISC-V CPUs historically supports Debug version +0.13 via a "debug" flag that is enabled by default in the default rv64 +CPU. + +Starting on QEMU 11.2, RISC-V CPUs supports also Debug version 1.0, enabled +via the "sdtrig" flag like a regular extension. The default setting for r= v64 +is still Debug 0.13 (debug =3D on, sdtrig =3D off), + +The "sdtrig" flag precedes "debug", i.e. if both are enabled the CPU will +implement Debug 1.0. In short: + +.. list-table:: "debug" and "sdtrig" flags and enabled Debug version + :widths: 25 25 25 + :header-rows: 1 + + * - debug + - sdtrig + - Enabled Debug version + * - on + - off + - 0.13 + * - on + - on + - 1.0 + * - off + - on + - 1.0 + * - off + - off + - All Debug versions disabled + + +Debug 0.13 to 1.0 code/design changes +------------------------------------- + +The effort done in QEMU version 11.2 to support Debug versions 0.13 and +1.0 together was based in section 1.2.1.2 "Incompatible Changes from 0.13 +to 1.0" from the ratified `1.0 spec`_. Here's how the proposed changes in +that section were implemented in QEMU 11.2: + +Changes that aren't applicable due to either being SBI related or not pres= ent/supported in QEMU: + * "Make haltsum0 optional if there is only one hart." + * "System bus autoincrement only happens if an access actually takes p= lace (sbdata0)." + * "Require debugger to poll dmactive after lowering it." + +Already implemented in the legacy Debug 0.13 base code: + * "When a selected trigger is disabled, tdata2 and tdata3 can be writt= en with any value supported by any of the types this trigger supports." + * "tcontrol fields only apply to breakpoint traps, not any trap." + +All "hitN" fields are hardwired 0 thus no changes made: + * "If version is greater than 0, then hit0 (previously called mcontrol= 6.hit) now contains 0 when a trigger fires more than one instruction after = the instruction that matched. (This information is now reflected in hit1.)" + +QEMU doesn't support encoding sizes greater than 64 bit so no change made: + * "If version is greater than 0, then the encodings of size for sizes = greater than 64 bit have changed." + +Changes made in the 0.13 codebase to support Debug 1.0: + * "Add pending to icount." + * "If version is greater than 0, then bit 20 of mcontrol6 is no longer= used for timing information. (Previously the bit was called mcontrol6.timi= ng.)" + + +.. _1.0 spec: https://docs.riscv.org/reference/debug/v1.0/_attachments/ris= cv-debug-specification.pdf --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499298; cv=none; d=zohomail.com; s=zohoarc; b=l76cp5dwI1H6XnkgvhvxaCVLfwo2IeLStce62kMvoDOVp0aE22I7KitGU1yn88d6twp9Md9pdfLKJeMbycjlRv98vLovzzMIOIKwDbsSGn6QqTl0Aq4ehHnXb9b3Ryw9Q3dfRrMhHmiRE7HhRm+laZJB/dFaPjBqilXS2N6XY6w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788499298; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 03 Sep 2026 22:20:11 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Portia Stephens Subject: [PULL 06/47] hw/riscv/boot: Make RISCVBootInfo const where possible Date: Fri, 4 Sep 2026 15:19:02 +1000 Message-ID: <20260904051943.799041-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=alistair23@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499298729158500 From: Joel Stanley As with riscv_load_firmware, take a const pointer in functions that reads the structure without writing. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Portia Stephens Message-ID: <20260824055642.41098-2-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h | 6 +++--- hw/riscv/boot.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 4e7bd9a225..d23f45d780 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -50,10 +50,10 @@ void riscv_boot_info_init(RISCVBootInfo *info, RISCVHar= tArrayState *harts); void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info, RISCVHartArrayState *harts, hwaddr low_start, hwaddr low_size); -vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, +vaddr riscv_calc_kernel_start_addr(const RISCVBootInfo *info, hwaddr firmware_end_addr); hwaddr riscv_find_and_load_firmware(MachineState *machine, - RISCVBootInfo *info, + const RISCVBootInfo *info, const char *default_machine_firmware, hwaddr *firmware_load_addr, symbol_fn_t sym_cb); @@ -71,7 +71,7 @@ void riscv_load_kernel(MachineState *machine, bool load_initrd, symbol_fn_t sym_cb); uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, - MachineState *ms, RISCVBootInfo *info); + MachineState *ms, const RISCVBootInfo *inf= o); void riscv_load_fdt(hwaddr fdt_addr, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr saddr, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 5e2dfa091a..4ac0b8ef65 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -91,7 +91,7 @@ void riscv_boot_info_init_discontig_mem(RISCVBootInfo *in= fo, info->ram_low_size =3D low_size; } =20 -vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, +vaddr riscv_calc_kernel_start_addr(const RISCVBootInfo *info, hwaddr firmware_end_addr) { if (info->is_32bit) { return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); @@ -151,7 +151,7 @@ char *riscv_find_firmware(const char *firmware_filename, } =20 hwaddr riscv_find_and_load_firmware(MachineState *machine, - RISCVBootInfo *info, + const RISCVBootInfo *info, const char *default_machine_firmware, hwaddr *firmware_load_addr, symbol_fn_t sym_cb) @@ -348,7 +348,7 @@ out: * The FDT is fdt_packed() during the calculation. */ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, - MachineState *ms, RISCVBootInfo *info) + MachineState *ms, const RISCVBootInfo *inf= o) { int ret =3D fdt_pack(ms->fdt); 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Thu, 03 Sep 2026 22:20:14 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Portia Stephens Subject: [PULL 07/47] hw/riscv/virt: Use hwaddr for IMSIC device tree address Date: Fri, 4 Sep 2026 15:19:03 +1000 Message-ID: <20260904051943.799041-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=alistair23@gmail.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499268637158500 From: Joel Stanley create_fdt_one_imsic() hard codes the top 32 bits to zero. Instead take a hwaddr and populate both the high and low cell. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Portia Stephens Message-ID: <20260824055642.41098-3-joel@jms.id.au> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index dd39641017..a5d2452d97 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -382,7 +382,8 @@ static void create_fdt_one_imsic(RISCVVirtState *s, hwa= ddr base_addr, g_autofree char *imsic_name =3D NULL; MachineState *ms =3D MACHINE(s); int socket_count =3D riscv_socket_count(ms); - uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; + uint32_t imsic_max_hart_per_socket, imsic_size; + hwaddr imsic_addr; g_autofree uint32_t *imsic_cells =3D NULL; g_autofree uint32_t *imsic_regs =3D NULL; static const char * const imsic_compat[2] =3D { @@ -402,7 +403,7 @@ static void create_fdt_one_imsic(RISCVVirtState *s, hwa= ddr base_addr, imsic_addr =3D base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size =3D IMSIC_HART_SIZE(imsic_guest_bits) * s->soc[socket].num_harts; - imsic_regs[socket * 4 + 0] =3D 0; + imsic_regs[socket * 4 + 0] =3D cpu_to_be32(imsic_addr >> 32); imsic_regs[socket * 4 + 1] =3D cpu_to_be32(imsic_addr); imsic_regs[socket * 4 + 2] =3D 0; imsic_regs[socket * 4 + 3] =3D cpu_to_be32(imsic_size); --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499241; cv=none; d=zohomail.com; s=zohoarc; b=Vof7pwuZvRlg/EtIia3tDMYiP5ViVtJGI0g46h7KZ73LO7ix3b9a50K5Pxh/4y8cGfzEz9Ztp/5MZwWcuxkUBqxC5nV/Xz20VSHwNEy/5OF+MGQPmNCanlj2bmLVAzowOMJGfgAF5b7eYYjib0oiv/m6sUhgQ51AneYOOQAnHy8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Thu, 03 Sep 2026 22:20:18 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 08/47] tests/functional: Avoid unnecessary removal of scratch files Date: Fri, 4 Sep 2026 15:19:04 +1000 Message-ID: <20260904051943.799041-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=alistair23@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499242378158500 From: Joel Stanley Files written by uncompress() and archive_extract() are placed in a temporary directory that is cleaned up when the test exits, making os.remove() redundant. Drop it and the unused os import. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20260824055642.41098-4-joel@jms.id.au> Signed-off-by: Alistair Francis --- tests/functional/arm/test_bpim2u.py | 11 ----------- tests/functional/arm/test_orangepi.py | 9 --------- tests/functional/riscv64/test_sifive_u.py | 4 ---- 3 files changed, 24 deletions(-) diff --git a/tests/functional/arm/test_bpim2u.py b/tests/functional/arm/tes= t_bpim2u.py index 8bed64b702..9192a2fbec 100755 --- a/tests/functional/arm/test_bpim2u.py +++ b/tests/functional/arm/test_bpim2u.py @@ -5,8 +5,6 @@ # # SPDX-License-Identifier: GPL-2.0-or-later =20 -import os - from qemu_test import LinuxKernelTest, exec_command_and_wait_for_pattern from qemu_test import Asset, interrupt_interactive_console_until_pattern from qemu_test import skipBigDataTest @@ -54,8 +52,6 @@ def test_arm_bpim2u(self): self.vm.launch() console_pattern =3D 'Kernel command line: %s' % kernel_command_line self.wait_for_console_pattern(console_pattern) - os.remove(kernel_path) - os.remove(dtb_path) =20 def test_arm_bpim2u_initrd(self): self.set_machine('bpim2u') @@ -86,9 +82,6 @@ def test_arm_bpim2u_initrd(self): 'reboot: Restarting system= ') # Wait for VM to shut down gracefully self.vm.wait() - os.remove(kernel_path) - os.remove(dtb_path) - os.remove(initrd_path) =20 def test_arm_bpim2u_gmac(self): self.set_machine('bpim2u') @@ -133,9 +126,6 @@ def test_arm_bpim2u_gmac(self): 'reboot: Restarting system= ') # Wait for VM to shut down gracefully self.vm.wait() - os.remove(kernel_path) - os.remove(dtb_path) - os.remove(rootfs_path) =20 @skipBigDataTest() def test_arm_bpim2u_openwrt_22_03_3(self): @@ -174,7 +164,6 @@ def test_arm_bpim2u_openwrt_22_03_3(self): 'Allwinner sun8i Family') exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', 'system-control@1c00000') - os.remove(image_path) =20 if __name__ =3D=3D '__main__': LinuxKernelTest.main() diff --git a/tests/functional/arm/test_orangepi.py b/tests/functional/arm/t= est_orangepi.py index f9bfa8c78d..0978023655 100755 --- a/tests/functional/arm/test_orangepi.py +++ b/tests/functional/arm/test_orangepi.py @@ -5,7 +5,6 @@ # # SPDX-License-Identifier: GPL-2.0-or-later =20 -import os import shutil =20 from qemu_test import LinuxKernelTest, exec_command_and_wait_for_pattern @@ -65,8 +64,6 @@ def test_arm_orangepi(self): self.vm.launch() console_pattern =3D 'Kernel command line: %s' % kernel_command_line self.wait_for_console_pattern(console_pattern) - os.remove(kernel_path) - os.remove(dtb_path) =20 def test_arm_orangepi_initrd(self): self.set_machine('orangepi-pc') @@ -97,9 +94,6 @@ def test_arm_orangepi_initrd(self): 'reboot: Restarting system= ') # Wait for VM to shut down gracefully self.vm.wait() - os.remove(kernel_path) - os.remove(dtb_path) - os.remove(initrd_path) =20 def test_arm_orangepi_sd(self): self.set_machine('orangepi-pc') @@ -140,9 +134,6 @@ def test_arm_orangepi_sd(self): 'reboot: Restarting system= ') # Wait for VM to shut down gracefully self.vm.wait() - os.remove(kernel_path) - os.remove(dtb_path) - os.remove(rootfs_path) =20 @skipBigDataTest() def test_arm_orangepi_armbian(self): diff --git a/tests/functional/riscv64/test_sifive_u.py b/tests/functional/r= iscv64/test_sifive_u.py index 54a0f9c648..6bf5be15f9 100755 --- a/tests/functional/riscv64/test_sifive_u.py +++ b/tests/functional/riscv64/test_sifive_u.py @@ -10,8 +10,6 @@ # # SPDX-License-Identifier: GPL-2.0-or-later =20 -import os - from qemu_test import Asset, LinuxKernelTest =20 =20 @@ -49,8 +47,6 @@ def do_test_riscv64_sifive_u_mmc_spi(self, connect_card): self.vm.launch() self.wait_for_console_pattern(pattern) =20 - os.remove(rootfs_path) - def test_riscv64_sifive_u_nommc_spi(self): self.do_test_riscv64_sifive_u_mmc_spi(False) =20 --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 03 Sep 2026 22:20:22 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 09/47] hw/riscv/atlantis: Document QEMU-only I2C device tree nodes Date: Fri, 4 Sep 2026 15:19:05 +1000 Message-ID: <20260904051943.799041-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499346623158500 From: Joel Stanley The QEMU only I2C devices have a comment next to them, do the same for the corresponding device tree entries. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20260824055642.41098-5-joel@jms.id.au> Signed-off-by: Alistair Francis --- hw/riscv/tt_atlantis.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 7d02868b22..4fd8679ae1 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -355,6 +355,7 @@ static void finalize_fdt(TTAtlantisState *s) aplic_s_phandle, periph_clk_phandle); } =20 + /* I2C peripherals: qemu specific */ create_fdt_i2c_device(s, 0, "dallas,ds1338", 0x6f); create_fdt_i2c_device(s, 4, "ti,tmp105", 0x48); } --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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Thu, 03 Sep 2026 22:20:25 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Alistair Francis , Portia Stephens Subject: [PULL 10/47] hw/riscv: Make s-mode IMSIC stride explicit Date: Fri, 4 Sep 2026 15:19:06 +1000 Message-ID: <20260904051943.799041-11-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499447152158500 Content-Type: text/plain; charset="utf-8" From: Joel Stanley Existing machines tightly coupled s-mode IMSIC stride with the guest bits value. There need to be enough bits to describe the guest in GEILEN, but that's a minimum bound and machines may choose to use a larger stride. This change decouples the two and updates Atlantis and Virt to use the new API. AIA guest count used by the Atlantis machine was not correct. It looks like a placeholder value was chosen in order to size the stride to 0x40000, but this gives the wrong guest count. From the (currently internal) docs, the guest count is 5: > |NUM_GEILEN|5 (0 - 64)|Number of supported guest index from the S-mode in= terrupt domain| Add that value to a define, and add a separate define for the stride, to reduce the opportunity for future confusion. Fixes: 7778f4b27bb1 ("hw/riscv: Add Tenstorrent Atlantis machine") Signed-off-by: Joel Stanley Acked-by: Alistair Francis Reviewed-by: Portia Stephens Message-ID: <20260824030509.18078-2-joel@jms.id.au> Signed-off-by: Alistair Francis --- hw/riscv/aia.h | 1 + hw/riscv/aia.c | 5 ++--- hw/riscv/tt_atlantis.c | 19 +++++++++++-------- hw/riscv/virt.c | 2 ++ 4 files changed, 16 insertions(+), 11 deletions(-) diff --git a/hw/riscv/aia.h b/hw/riscv/aia.h index 565f91accc..3b6d7f9625 100644 --- a/hw/riscv/aia.h +++ b/hw/riscv/aia.h @@ -15,6 +15,7 @@ uint32_t imsic_num_bits(uint32_t count); =20 DeviceState *riscv_create_aia(bool msimode, int aia_guests, uint32_t m_imsic_stride, + uint32_t s_imsic_stride, uint16_t num_sources, const MemMapEntry *aplic_m, const MemMapEntry *aplic_s, diff --git a/hw/riscv/aia.c b/hw/riscv/aia.c index ed89160029..c33a3b32bd 100644 --- a/hw/riscv/aia.c +++ b/hw/riscv/aia.c @@ -26,6 +26,7 @@ uint32_t imsic_num_bits(uint32_t count) =20 DeviceState *riscv_create_aia(bool msimode, int aia_guests, uint32_t m_imsic_stride, + uint32_t s_imsic_stride, uint16_t num_sources, const MemMapEntry *aplic_m, const MemMapEntry *aplic_s, @@ -36,7 +37,6 @@ DeviceState *riscv_create_aia(bool msimode, int aia_guest= s, { int i; hwaddr addr =3D 0; - uint32_t guest_bits; DeviceState *aplic_s_dev =3D NULL; DeviceState *aplic_m_dev =3D NULL; =20 @@ -55,10 +55,9 @@ DeviceState *riscv_create_aia(bool msimode, int aia_gues= ts, } =20 /* Per-socket S-level IMSICs */ - guest_bits =3D imsic_num_bits(aia_guests + 1); addr =3D imsic_s->base + socket * (1U << IMSIC_MMIO_GROUP_MIN_SHIF= T); for (i =3D 0; i < hart_count; i++) { - riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), + riscv_imsic_create(addr + i * s_imsic_stride, base_hartid + i, false, 1 + aia_guests, num_msis); } diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 4fd8679ae1..fda848c3a6 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -36,8 +36,12 @@ #define TT_IRQCHIP_NUM_MSIS 255 #define TT_IRQCHIP_NUM_SOURCES 128 #define TT_IRQCHIP_NUM_PRIO_BITS 3 -#define TT_IRQCHIP_GUESTS 63 /* aia_guests, gives guest_index_bits= =3D6 */ -#define TT_IRQCHIP_MIMSIC_STRIDE 0x40000 +#define TT_IMSIC_GUESTS 5 +#define TT_IMSIC_STRIDE 0x40000 /* Same stride for M and S */ +#define TT_IMSIC_GUEST_BITS 6 + +/* Stride is fixed by hardware, check it's consistent with guest bits. */ +QEMU_BUILD_BUG_ON(TT_IMSIC_STRIDE !=3D (0x1000 << TT_IMSIC_GUEST_BITS)); =20 #define TT_ACLINT_MTIME_SIZE 0x8050 #define TT_ACLINT_MTIME 0x0 @@ -230,18 +234,16 @@ static void create_fdt_cpu(TTAtlantisState *s, const = MemMapEntry *memmap, =20 create_fdt_aclint(s, intc_phandles); =20 - uint32_t imsic_guest_bits =3D imsic_num_bits(TT_IRQCHIP_GUESTS + 1); - /* M-level IMSIC node */ uint32_t msi_m_phandle =3D next_phandle(); create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_MIMSIC], ms->smp.cpus, intc_phandles, msi_m_phandle, - IRQ_M_EXT, imsic_guest_bits); + IRQ_M_EXT, TT_IMSIC_GUEST_BITS); =20 /* S-level IMSIC node */ create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_SIMSIC], ms->smp.cpus, intc_phandles, imsic_s_phandle, - IRQ_S_EXT, imsic_guest_bits); + IRQ_S_EXT, TT_IMSIC_GUEST_BITS); =20 uint32_t aplic_m_phandle =3D next_phandle(); =20 @@ -493,8 +495,9 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); =20 - s->irqchip =3D riscv_create_aia(true, TT_IRQCHIP_GUESTS, - TT_IRQCHIP_MIMSIC_STRIDE, + s->irqchip =3D riscv_create_aia(true, TT_IMSIC_GUESTS, + TT_IMSIC_STRIDE, + TT_IMSIC_STRIDE, TT_IRQCHIP_NUM_SOURCES, &s->memmap[TT_ATL_MAPLIC], &s->memmap[TT_ATL_SAPLIC], diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a5d2452d97..c43a23af02 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1410,9 +1410,11 @@ static void virt_machine_init(MachineState *machine) s->irqchip[i] =3D virt_create_plic(s->memmap, i, base_hartid, hart_count); } else { + int imsic_bits =3D imsic_num_bits(s->aia_guests + 1); s->irqchip[i] =3D riscv_create_aia(s->aia_type =3D=3D VIRT_AIA= _TYPE_APLIC_IMSIC, s->aia_guests, IMSIC_HART_SIZE(0), + IMSIC_HART_SIZE(imsic_bits), s->num_sources, &s->memmap[VIRT_APLIC_M], &s->memmap[VIRT_APLIC_S], --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499326; cv=none; d=zohomail.com; s=zohoarc; b=eJeeB14rIv0CBvXsGD+ppkwzE0qOfEFHL2Kt0yX2Bq7MSCmsb4g6ojlhJsMcAYwPPEtJ9RpuaaakpDs5XfWrEVn0hSn6FdCftk4cXntC2ouDqmXz4JaHlJLlGdhY9l9UXBXiq2qkkq6anap5BrZ/zfDpw/Dv+k7zyy/7bhPspYQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788499326; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 03 Sep 2026 22:20:28 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Alistair Francis , Portia Stephens Subject: [PULL 11/47] hw/riscv/aia: Check for invalid IMSIC configs Date: Fri, 4 Sep 2026 15:19:07 +1000 Message-ID: <20260904051943.799041-12-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=alistair23@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499326519158500 Content-Type: text/plain; charset="utf-8" From: Joel Stanley Assert that the IMSIC layout will be valid before creating the devices. aia_guests is a command line parameter but the machines that allows it to be set (currently only virt) should be passing the correct stride for a given number of guests. The assert helps catch bugs in future changes and shouldn't be triggerable by an invalid user config. Signed-off-by: Joel Stanley Acked-by: Alistair Francis Reviewed-by: Portia Stephens Message-ID: <20260824030509.18078-3-joel@jms.id.au> Signed-off-by: Alistair Francis --- hw/riscv/aia.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/riscv/aia.c b/hw/riscv/aia.c index c33a3b32bd..c1a5982856 100644 --- a/hw/riscv/aia.c +++ b/hw/riscv/aia.c @@ -43,6 +43,10 @@ DeviceState *riscv_create_aia(bool msimode, int aia_gues= ts, /* The RISC-V Advanced Interrupt Architecture, Chapter 1.2. Limits */ g_assert(num_sources <=3D 1023); =20 + /* Prevent IMSIC MMIO regions from silently overlapping */ + g_assert(s_imsic_stride >=3D IMSIC_HART_SIZE(imsic_num_bits(1 + aia_gu= ests))); + g_assert(m_imsic_stride >=3D IMSIC_HART_SIZE(0)); + if (msimode) { if (!kvm_enabled()) { /* Per-socket M-level IMSICs */ --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499320; cv=none; d=zohomail.com; s=zohoarc; b=Fce4PytSBfTTjjdZz+xWmfuqSm2YLUfgHOGT/3/DvDNDnkRbf7s7NbmwuHU0LJAMw+GLmhU4n3w9Zf5Bf4K7Rt63C+vyeWzM2JBf8TrKVVq/Xs8RCD08UJKPIlpxqQ6jGCgXvlswgDBlESD83n3eMs605CFkhqPdUcA8w1g4r5I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788499320; 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Thu, 03 Sep 2026 22:20:31 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , Julien Thillard , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 12/47] disas/riscv.c: Correct dasm for cbo and lq Date: Fri, 4 Sep 2026 15:19:08 +1000 Message-ID: <20260904051943.799041-13-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=alistair23@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499323196158500 From: Fr=C3=A9d=C3=A9ric P=C3=A9trot Lq shares the cmo opcode space, but the cbos must have rd =3D 0. Now ensure that they are matched only in that case. This implies that lq can be recognized as such only when rd !=3D 0. Update the decoder file accordingly. Fixes: 9273cda722 ("disas/riscv.c: add 'cbo' insns to disassembler") Reported-by: Julien Thillard Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Reviewed-by: Daniel Henrique Barboza Message-ID: <20260825100922.387919-2-frederic.petrot@univ-grenoble-alpes.fr> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 ++ disas/riscv.c | 20 +++++++++++--------- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 21272fdb50..aa02dae3c9 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -216,6 +216,8 @@ ldu ............ ..... 111 ..... 0000011 @i ] =20 # *** RVI128 lq *** + # *** Catches an lq with rd =3D 0, which we disallow + illegal ------------ ----- 010 00000 0001111 lq ............ ..... 010 ..... 0001111 @i } sq ............ ..... 100 ..... 0100011 @s diff --git a/disas/riscv.c b/disas/riscv.c index b8099cbdf8..e85dbac035 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -1281,22 +1281,24 @@ static const rv_opcode_data *decode_inst_opcode(rv_= decode *dec, rv_isa isa) case 2: /* * 'lq' shares the "(...) 010 ..... 0001111" opcode space - * with 'cbo' insns. Check the next 5 bits to select - * what we want: + * with 'cbo' insns. * * cbo_inval 0000000 00000 ..... 010 00000 0001111 * cbo_clean 0000000 00001 ..... 010 00000 0001111 * cbo_flush 0000000 00010 ..... 010 00000 0001111 * cbo_zero 0000000 00100 ..... 010 00000 0001111 * - * Anything that doesn't match these will default to 'lq'. + * lq matches when rd !=3D 0 */ - switch ((inst >> 17) & 0b11111) { - case 0: return &op_cbo_inval; - case 1: return &op_cbo_clean; - case 2: return &op_cbo_flush; - case 4: return &op_cbo_zero; - default: return &op_lq; + if ((inst >> 7) & 0b11111) { + return &op_lq; + } else { + switch (inst >> 20) { + case 0: return &op_cbo_inval; + case 1: return &op_cbo_clean; + case 2: return &op_cbo_flush; + case 4: return &op_cbo_zero; + } } } break; --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 03 Sep 2026 22:20:34 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 13/47] tests/tcg/riscv64: Add tests for rv128 [ms]status Date: Fri, 4 Sep 2026 15:19:09 +1000 Message-ID: <20260904051943.799041-14-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=alistair23@gmail.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499403161158500 From: Fr=C3=A9d=C3=A9ric P=C3=A9trot Adding asm tests to check that mstatus and sstatus are updated as expected in an rv128 cpu. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Reviewed-by: Daniel Henrique Barboza Message-ID: <20260824174246.202150-1-frederic.petrot@univ-grenoble-alpes.fr> Signed-off-by: Alistair Francis --- tests/tcg/riscv64/Makefile.softmmu-target | 9 ++ tests/tcg/riscv64/test-rv128-mstatus.S | 67 ++++++++++++++ tests/tcg/riscv64/test-rv128-sstatus.S | 108 ++++++++++++++++++++++ 3 files changed, 184 insertions(+) create mode 100644 tests/tcg/riscv64/test-rv128-mstatus.S create mode 100644 tests/tcg/riscv64/test-rv128-sstatus.S diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/= Makefile.softmmu-target index 6a219c306c..575571de90 100644 --- a/tests/tcg/riscv64/Makefile.softmmu-target +++ b/tests/tcg/riscv64/Makefile.softmmu-target @@ -71,5 +71,14 @@ EXTRA_RUNS +=3D run-test-misa-w run-test-misa-w: test-misa-w $(call run-test, $<, $(QEMU) -cpu rv64$(comma)x-misa-w=3Dtrue$(comma)c=3D= true$(comma)v=3Dtrue $(QEMU_OPTS)$<) =20 +# Test for rv128 +EXTRA_RUNS +=3D run-test-rv128-mstatus +run-test-rv128-mstatus: test-rv128-mstatus + $(call run-test, $<, $(QEMU) -cpu x-rv128 $(QEMU_OPTS)$<) + +EXTRA_RUNS +=3D run-test-rv128-sstatus +run-test-rv128-sstatus: test-rv128-sstatus + $(call run-test, $<, $(QEMU) -cpu x-rv128 $(QEMU_OPTS)$<) + # We don't currently support the multiarch system tests undefine MULTIARCH_TESTS diff --git a/tests/tcg/riscv64/test-rv128-mstatus.S b/tests/tcg/riscv64/tes= t-rv128-mstatus.S new file mode 100644 index 0000000000..323f65ef90 --- /dev/null +++ b/tests/tcg/riscv64/test-rv128-mstatus.S @@ -0,0 +1,67 @@ +/* + * Test rv128 mstatus update and access + * Author: Fr=C3=A9d=C3=A9ric P=C3=A9trot + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#define srli(rd, rs1, imm) .insn i 0b0010011, 0b101, rd, r= s1, imm & 0b1111111 + + .option norvc + + .text + .globl _start +_start: + csrr s0, misa + srli (s1, s0, 126) + li s0, 3 + bne s1, s0, fail + + # Check UXL and SXL are set to RV128 too + csrr s0, mstatus + srli (s1, s0, 32) + andi s1, s1, 0xf + li s0, 0xf + bne s1, s0, fail + + # Mark FPU dirty to check for SD + .equiv MSTATUS_FS, 0x00006000 + li s0, MSTATUS_FS + csrs mstatus, s0 + # Do some useless computation + fmadd.s f3, f2, f1, f0 + fmax.s f0, f1, f2 + # Check SD has changed where expected + csrr s0, mstatus + srli (s1, s0, 127) + li s0, 1 + bne s1, s0, fail + # Mark FPU clean (2 in FS place) + li s0, ~0x00004000 + csrc mstatus, s0 + csrr s0, mstatus + srli (s1, s0, 13) + andi s1, s1, 3 + li s0, 2 + bne s1, s0, fail + li a0, 0 + j _exit +fail: + li a0, 1 +_exit: + lla a1, semiargs + li t0, 0x20026 # ADP_Stopped_ApplicationExit + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 # TARGET_SYS_EXIT_EXTENDED + + # Semihosting call sequence + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + .data + .balign 16 +semiargs: + .space 16 diff --git a/tests/tcg/riscv64/test-rv128-sstatus.S b/tests/tcg/riscv64/tes= t-rv128-sstatus.S new file mode 100644 index 0000000000..af118e355a --- /dev/null +++ b/tests/tcg/riscv64/test-rv128-sstatus.S @@ -0,0 +1,108 @@ +/* + * Test rv128 sstatus update and access + * Author: Fr=C3=A9d=C3=A9ric P=C3=A9trot + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#define srli(rd, rs1, imm) .insn i 0b0010011, 0b101, rd, r= s1, imm & 0b1111111 + + .option norvc + + .text + .globl _start +_start: + // Check RV128 is running + csrr s0, misa + srli (s1, s0, 126) + li s0, 3 + bne s1, s0, fail + + // Minimal pmp settings +#define PMP_NAPOT 0x18 +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 + + li s0, -1 + csrw pmpaddr0, s0 + li s0, PMP_NAPOT | PMP_R | PMP_W | PMP_X + csrw pmpcfg0, s0 + + la s0, backm + csrw mtvec, s0 + + // Set MPP to supervisor + csrr s0, mstatus + li s1, ~0x1800 // mask + and s1, s1, s0 + li s0, 0x0800 // supervisor + or s1, s1, s0 + csrw mstatus, s1 + // Change to supervisor mode + la s0, 1f + csrw mepc, s0 + mret +1: + // Check UXL is set to RV128 + csrr s0, sstatus + srli (s1, s0, 32) + andi s1, s1, 0x3 + li s0, 3 + bne s1, s0, fail + // Check SPP if is set to 1, since we + // come from machine mode + srli (s1, s0, 8) + andi s1, s1, 0x1 + // Actually this check fails, so test 0 + li s0, 0 + bne s1, s0, fail + + // Mark FPU dirty to check for SD + .equiv MSTATUS_FS, 0x00006000 + li s0, MSTATUS_FS + csrs sstatus, s0 + // Do some fun useless computation + fmadd.s f3, f2, f1, f0 + fmax.s f0, f1, f2 + // Check SD has changed where expected + csrr s0, sstatus + srli (s1, s0, 127) + li s0, 1 + bne s1, s0, fail + // Mark FPU clean (2 in FS place) + li s0, ~0x00004000 + csrc sstatus, s0 + csrr s0, sstatus + srli (s1, s0, 127) + li s0, 0 + bne s1, s0, fail + + // Let's go back to machine mode to exit + ecall + + // mtvec bit 1:0 indicate mode, 00 is Direct, what + // we want in this simple test + .align 4 +backm: + li a0, 0 + j _exit +fail: + li a0, 1 +_exit: + lla a1, semiargs + li t0, 0x20026 # ADP_Stopped_ApplicationExit + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 # TARGET_SYS_EXIT_EXTENDED + + # Semihosting call sequence + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + .data + .balign 16 +semiargs: + .space 16 --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499276; cv=none; d=zohomail.com; s=zohoarc; b=AaxEnnGrpv1bUzjfE0WDXyQR3BX4JZCoUgHbfqGY+9e5Xs7kwXEeYTJoh1hZZ0LH6LrWGz0KExMTwgUK6Bh6Xh2CvXjHyG2L89iTxFnT+FDTArSam05375QAxDdS0fykkSqsYBbLDjBZ7QA9m1v6qu6yJhR5Dn/MZTHKY8Z1abU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788499276; 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client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499276677158500 From: Daniel Henrique Barboza Given that the helpers are public API we should prefix them with "riscv_" to avoid conflicts when linking with different targets in the future, i.e. we should not use generic names like "create_fdt_socket_memory". Despite the amount of lines this is a mechanical change and no real FDT changes are intended. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260828203918.350131-2-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/fdt-common.h | 48 ++++++++++++++++++----------------- hw/riscv/fdt-common.c | 45 ++++++++++++++++---------------- hw/riscv/sifive_u.c | 34 +++++++++++++------------ hw/riscv/spike.c | 30 ++++++++++++---------- hw/riscv/tt_atlantis.c | 22 ++++++++-------- hw/riscv/virt.c | 42 +++++++++++++++--------------- 6 files changed, 117 insertions(+), 104 deletions(-) diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index 1729a6abc6..371971d79d 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -11,29 +11,31 @@ =20 #include "target/riscv/cpu.h" =20 -void *create_board_device_tree(const char *model, const char *compatible, - int *fdt_size); -void create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, - int socket_id, bool numa_enabled); -void create_fdt_clint(void *fdt, hwaddr addr, uint64_t size, - uint32_t *intc_phandles, int num_harts); -void create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, - int socket_id, uint32_t *intc_phandles, - int num_harts, bool numa_enabled); -void fdt_create_cpu_socket_subnode(void *fdt, uint64_t timebase_frequency); -void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, - int socket_id, int num_harts_socket, - int socket_hartid_base, uint32_t *phandle, - uint32_t *intc_phandles, bool numa_enabled, - bool is_32_bit); -void create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, - int cpu_id, int socket_id, +void *riscv_create_board_device_tree(const char *model, const char *compat= ible, + int *fdt_size); +void riscv_create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, + int socket_id, bool numa_enabled); +void riscv_create_fdt_clint(void *fdt, hwaddr addr, uint64_t size, + uint32_t *intc_phandles, int num_harts); +void riscv_create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, + int socket_id, uint32_t *intc_phandles, + int num_harts, bool numa_enabled); +void riscv_fdt_create_cpu_socket_subnode(void *fdt, + uint64_t timebase_frequency); +void riscv_create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, + int socket_id, int num_harts_socket, int socket_hartid_base, uint32_t *phandl= e, - uint32_t *intc_phandles); -void create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, - uint32_t plic_phandle, uint32_t int_cells, - uint32_t addr_cells, uint32_t *plic_cells, - uint32_t cells_size, uint32_t ndev_sources, - bool numa_enabled, int socket); + uint32_t *intc_phandles, bool numa_enabl= ed, + bool is_32_bit); +void riscv_create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, + int cpu_id, int socket_id, + int socket_hartid_base, + uint32_t *phandle, + uint32_t *intc_phandles); +void riscv_create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, + uint32_t plic_phandle, uint32_t int_cells, + uint32_t addr_cells, uint32_t *plic_cells, + uint32_t cells_size, uint32_t ndev_sources, + bool numa_enabled, int socket); void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name= ); #endif diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index aa143a618b..3a8da03cfb 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -14,8 +14,8 @@ #include "hw/riscv/fdt-common.h" #include "target/riscv/cpu_bits.h" =20 -void *create_board_device_tree(const char *model, const char *compatible, - int *fdt_size) +void *riscv_create_board_device_tree(const char *model, const char *compat= ible, + int *fdt_size) { void *fdt =3D create_device_tree(fdt_size); =20 @@ -38,8 +38,8 @@ void *create_board_device_tree(const char *model, const c= har *compatible, return fdt; } =20 -void create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, - int socket_id, bool numa_enabled) +void riscv_create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, + int socket_id, bool numa_enabled) { g_autofree char *mem_name =3D g_strdup_printf("/memory@%"HWADDR_PRIx, = addr); =20 @@ -52,9 +52,9 @@ void create_fdt_socket_memory(void *fdt, hwaddr addr, uin= t64_t size, } } =20 -void create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, - int socket_id, uint32_t *intc_phandles, - int num_harts, bool numa_enabled) +void riscv_create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, + int socket_id, uint32_t *intc_phandles, + int num_harts, bool numa_enabled) { g_autofree uint32_t *clint_cells =3D g_new0(uint32_t, num_harts * 4); g_autofree char *clint_name =3D NULL; @@ -84,7 +84,8 @@ void create_fdt_socket_clint(void *fdt, hwaddr addr, uint= 64_t size, } } =20 -void fdt_create_cpu_socket_subnode(void *fdt, uint64_t timebase_frequency) +void riscv_fdt_create_cpu_socket_subnode(void *fdt, + uint64_t timebase_frequency) { qemu_fdt_add_subnode(fdt, "/cpus"); qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", @@ -169,11 +170,11 @@ create_fdt_socket_cpu_internal(void *fdt, char *clust= _name, RISCVCPU *cpu_ptr, qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); } =20 -void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, - int socket_id, int num_harts_socket, - int socket_hartid_base, uint32_t *phandle, - uint32_t *intc_phandles, bool numa_enabled, - bool is_32_bit) +void riscv_create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, + int socket_id, int num_harts_socket, + int socket_hartid_base, uint32_t *phandl= e, + uint32_t *intc_phandles, bool numa_enabl= ed, + bool is_32_bit) { g_autofree char *clust_name =3D NULL; =20 @@ -191,21 +192,21 @@ void create_fdt_socket_cpus(void *fdt, RISCVCPU *sock= et_harts, } =20 void -create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, - int cpu_id, int socket_id, - int socket_hartid_base, uint32_t *phandle, - uint32_t *intc_phandles) +riscv_create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, + int cpu_id, int socket_id, + int socket_hartid_base, uint32_t *phand= le, + uint32_t *intc_phandles) { create_fdt_socket_cpu_internal(fdt, clust_name, NULL, cpu_id, socket_id, socket_hartid_base, phandle, intc_phandles, false, false); } =20 -void create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, - uint32_t plic_phandle, uint32_t int_cells, - uint32_t addr_cells, uint32_t *plic_cells, - uint32_t cells_size, uint32_t ndev_sources, - bool numa_enabled, int socket_id) +void riscv_create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, + uint32_t plic_phandle, uint32_t int_cells, + uint32_t addr_cells, uint32_t *plic_cells, + uint32_t cells_size, uint32_t ndev_sources, + bool numa_enabled, int socket_id) { g_autofree char *nodename =3D NULL; static const char * const plic_compat[2] =3D { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 997ee91aa0..a40f82e7a5 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -107,8 +107,10 @@ static void create_fdt(SiFiveUState *s, const MemMapEn= try *memmap, g_autofree uint32_t *intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); g_autofree char *clust_name =3D NULL; =20 - fdt =3D ms->fdt =3D create_board_device_tree("SiFive HiFive Unleashed = A00", - "sifive,hifive-unleashed-a00", &s->fdt_size); + fdt =3D ms->fdt =3D riscv_create_board_device_tree( + "SiFive HiFive Unleashed A00", + "sifive,hifive-unleashed-a00", + &s->fdt_size); =20 hfclk_phandle =3D phandle++; nodename =3D g_strdup_printf("/hfclk"); @@ -132,10 +134,10 @@ static void create_fdt(SiFiveUState *s, const MemMapE= ntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); g_free(nodename); =20 - create_fdt_socket_memory(fdt, memmap[SIFIVE_U_DEV_DRAM].base, - ms->ram_size, 0, false); + riscv_create_fdt_socket_memory(fdt, memmap[SIFIVE_U_DEV_DRAM].base, + ms->ram_size, 0, false); =20 - fdt_create_cpu_socket_subnode(fdt, CLINT_TIMEBASE_FREQ); + riscv_fdt_create_cpu_socket_subnode(fdt, CLINT_TIMEBASE_FREQ); =20 clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", 0); qemu_fdt_add_subnode(fdt, clust_name); @@ -156,15 +158,15 @@ static void create_fdt(SiFiveUState *s, const MemMapE= ntry *memmap, riscv_isa_write_fdt(&s->soc.e_cpus.harts[0], fdt, nodename); } =20 - create_fdt_socket_cpu_sifive(fdt, clust_name, cpu, 0, 0, - &phandle, intc_phandles); + riscv_create_fdt_socket_cpu_sifive(fdt, clust_name, cpu, 0, 0, + &phandle, intc_phandles); =20 g_free(nodename); } =20 - create_fdt_socket_clint(fdt, memmap[SIFIVE_U_DEV_CLINT].base, - memmap[SIFIVE_U_DEV_CLINT].size, 0, - intc_phandles, ms->smp.cpus, false); + riscv_create_fdt_socket_clint(fdt, memmap[SIFIVE_U_DEV_CLINT].base, + memmap[SIFIVE_U_DEV_CLINT].size, 0, + intc_phandles, ms->smp.cpus, false); =20 nodename =3D g_strdup_printf("/soc/otp@%lx", (long)memmap[SIFIVE_U_DEV_OTP].base); @@ -208,12 +210,12 @@ static void create_fdt(SiFiveUState *s, const MemMapE= ntry *memmap, } } =20 - create_fdt_plic(fdt, memmap[SIFIVE_U_DEV_PLIC].base, - memmap[SIFIVE_U_DEV_PLIC].size, - plic_phandle, SIFIVE_U_PLIC_INT_CELLS, - SIFIVE_U_PLIC_ADDR_CELLS, cells, - cells_length * sizeof(uint32_t), - SIFIVE_U_PLIC_NUM_SOURCES - 1, false, 0); + riscv_create_fdt_plic(fdt, memmap[SIFIVE_U_DEV_PLIC].base, + memmap[SIFIVE_U_DEV_PLIC].size, + plic_phandle, SIFIVE_U_PLIC_INT_CELLS, + SIFIVE_U_PLIC_ADDR_CELLS, cells, + cells_length * sizeof(uint32_t), + SIFIVE_U_PLIC_NUM_SOURCES - 1, false, 0); g_free(cells); =20 gpio_phandle =3D phandle++; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index e36fe996b0..5fd4109d29 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -60,8 +60,10 @@ static void create_fdt(SpikeState *s, const MemMapEntry = *memmap, uint32_t phandle =3D 1; bool numa_enabled =3D riscv_numa_enabled(ms); =20 - fdt =3D ms->fdt =3D create_board_device_tree("ucbbar,spike-bare,qemu", - "ucbbar,spike-bare-dev", &fdt_size); + fdt =3D ms->fdt =3D riscv_create_board_device_tree( + "ucbbar,spike-bare,qemu", + "ucbbar,spike-bare-dev", + &fdt_size); =20 qemu_fdt_add_subnode(fdt, "/htif"); qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); @@ -70,7 +72,8 @@ static void create_fdt(SpikeState *s, const MemMapEntry *= memmap, 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); } =20 - fdt_create_cpu_socket_subnode(fdt, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); + riscv_fdt_create_cpu_socket_subnode(fdt, + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ= ); =20 for (socket =3D (riscv_socket_count(ms) - 1); socket >=3D 0; socket--)= { g_autofree uint32_t *intc_phandles =3D g_new0(uint32_t, @@ -79,20 +82,21 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, riscv_socket_mem_offset(ms, socket); uint64_t memsize =3D riscv_socket_mem_size(ms, socket); =20 - create_fdt_socket_cpus(fdt, (&s->soc[socket])->harts, socket, - s->soc[socket].num_harts, - s->soc[socket].hartid_base, - &phandle, intc_phandles, numa_enabled, - is_32_bit); + riscv_create_fdt_socket_cpus(fdt, (&s->soc[socket])->harts, socket, + s->soc[socket].num_harts, + s->soc[socket].hartid_base, + &phandle, intc_phandles, numa_enabled, + is_32_bit); =20 - create_fdt_socket_memory(fdt, memaddr, memsize, socket, - riscv_numa_enabled(ms)); + riscv_create_fdt_socket_memory(fdt, memaddr, memsize, socket, + riscv_numa_enabled(ms)); =20 clint_addr =3D memmap[SPIKE_CLINT].base + (memmap[SPIKE_CLINT].size * socket); - create_fdt_socket_clint(fdt, clint_addr, memmap[SPIKE_CLINT].size, - socket, intc_phandles, - s->soc[socket].num_harts, numa_enabled); + riscv_create_fdt_socket_clint(fdt, clint_addr, + memmap[SPIKE_CLINT].size, socket, + intc_phandles, s->soc[socket].num_ha= rts, + numa_enabled); } =20 riscv_socket_fdt_write_distance_matrix(ms); diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index fda848c3a6..db8a1805d7 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -90,16 +90,17 @@ static void create_fdt_memory(TTAtlantisState *s) size_hi =3D MACHINE(s)->ram_size - size_lo; } =20 - create_fdt_socket_memory(fdt, s->memmap[TT_ATL_DDR_LO].base, size_lo, - 0, false); + riscv_create_fdt_socket_memory(fdt, s->memmap[TT_ATL_DDR_LO].base, + size_lo, 0, false); if (size_hi) { /* * The first part of the HI address is aliased at the LO address * so do not include that as usable memory. Is there any way * (or good reason) to describe that aliasing 2GB with DT? */ - create_fdt_socket_memory(fdt, s->memmap[TT_ATL_DDR_HI].base + size= _lo, - size_hi, 0, false); + riscv_create_fdt_socket_memory(fdt, + s->memmap[TT_ATL_DDR_HI].base + siz= e_lo, + size_hi, 0, false); } } =20 @@ -224,11 +225,11 @@ static void create_fdt_cpu(TTAtlantisState *s, const = MemMapEntry *memmap, void *fdt =3D MACHINE(s)->fdt; g_autofree uint32_t *intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); =20 - fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); + riscv_fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); =20 - create_fdt_socket_cpus(fdt, s->soc.harts, 0, s->soc.num_harts, - s->soc.hartid_base, &fdt_phandle, intc_phandles, - false, false); + riscv_create_fdt_socket_cpus(fdt, s->soc.harts, 0, s->soc.num_harts, + s->soc.hartid_base, &fdt_phandle, + intc_phandles, false, false); =20 create_fdt_memory(s); =20 @@ -366,8 +367,9 @@ static void create_fdt(TTAtlantisState *s) { MachineState *ms =3D MACHINE(s); =20 - ms->fdt =3D create_board_device_tree("Tenstorrent Atlantis RISC-V Mach= ine", - "tenstorrent,atlantis", &s->fdt_siz= e); + ms->fdt =3D riscv_create_board_device_tree( + "Tenstorrent Atlantis RISC-V Machine", + "tenstorrent,atlantis", &s->fdt_size); =20 qemu_fdt_add_subnode(ms->fdt, "/chosen"); =20 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c43a23af02..ef97d04031 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -359,12 +359,12 @@ static void create_fdt_socket_plic(RISCVVirtState *s, =20 plic_phandles[socket] =3D (*phandle)++; =20 - create_fdt_plic(ms->fdt, plic_addr, s->memmap[VIRT_PLIC].size, - plic_phandles[socket], FDT_PLIC_INT_CELLS, - FDT_PLIC_ADDR_CELLS, plic_cells, - cells_length * sizeof(uint32_t), - VIRT_IRQCHIP_NUM_SOURCES - 1, - numa_enabled, socket); + riscv_create_fdt_plic(ms->fdt, plic_addr, s->memmap[VIRT_PLIC].size, + plic_phandles[socket], FDT_PLIC_INT_CELLS, + FDT_PLIC_ADDR_CELLS, plic_cells, + cells_length * sizeof(uint32_t), + VIRT_IRQCHIP_NUM_SOURCES - 1, + numa_enabled, socket); =20 if (!socket) { platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, @@ -600,7 +600,7 @@ static void create_fdt_sockets(RISCVVirtState *s, bool numa_enabled =3D riscv_numa_enabled(ms); bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); =20 - fdt_create_cpu_socket_subnode(ms->fdt, + riscv_fdt_create_cpu_socket_subnode(ms->fdt, kvm_enabled() ? kvm_riscv_get_timebase_frequency(&s->soc->harts[0]= ) : RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); =20 @@ -614,14 +614,14 @@ static void create_fdt_sockets(RISCVVirtState *s, =20 phandle_pos -=3D s->soc[socket].num_harts; =20 - create_fdt_socket_cpus(ms->fdt, (&s->soc[socket])->harts, socket, - s->soc[socket].num_harts, - s->soc[socket].hartid_base, - phandle, &intc_phandles[phandle_pos], - numa_enabled, is_32_bit); + riscv_create_fdt_socket_cpus(ms->fdt, (&s->soc[socket])->harts, so= cket, + s->soc[socket].num_harts, + s->soc[socket].hartid_base, + phandle, &intc_phandles[phandle_pos], + numa_enabled, is_32_bit); =20 - create_fdt_socket_memory(ms->fdt, memaddr, memsize, - socket, riscv_numa_enabled(ms)); + riscv_create_fdt_socket_memory(ms->fdt, memaddr, memsize, + socket, riscv_numa_enabled(ms)); =20 if (virt_aclint_allowed() && s->have_aclint) { create_fdt_socket_aclint(s, socket, @@ -630,10 +630,11 @@ static void create_fdt_sockets(RISCVVirtState *s, hwaddr clintaddr =3D s->memmap[VIRT_CLINT].base + s->memmap[VIRT_CLINT].size * socket; =20 - create_fdt_socket_clint(ms->fdt, clintaddr, - s->memmap[VIRT_CLINT].size, - socket, &intc_phandles[phandle_pos], - s->soc[socket].num_harts, numa_enabled= ); + riscv_create_fdt_socket_clint(ms->fdt, clintaddr, + s->memmap[VIRT_CLINT].size, + socket, &intc_phandles[phandle_p= os], + s->soc[socket].num_harts, + numa_enabled); } } =20 @@ -1020,8 +1021,9 @@ static void create_fdt(RISCVVirtState *s) uint8_t rng_seed[32]; g_autofree char *name =3D NULL; =20 - ms->fdt =3D create_board_device_tree("riscv-virtio,qemu", "riscv-virti= o", - &s->fdt_size); + ms->fdt =3D riscv_create_board_device_tree("riscv-virtio,qemu", + "riscv-virtio", + &s->fdt_size); =20 /* * The "/soc/pci@..." node is needed for PCIE hotplugs --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 03 Sep 2026 22:20:40 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Chao Liu , Alistair Francis Subject: [PULL 15/47] hw/riscv/fdt-common, virt.c: add riscv_create_fdt_flash() Date: Fri, 4 Sep 2026 15:19:11 +1000 Message-ID: <20260904051943.799041-16-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=alistair23@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499310464158500 From: Daniel Henrique Barboza Add a common helper to create a cfi-flash compatible flash subnode. This change only affects the existing 'virt' board for now but it will be used by the future 'riscv-server-ref' board in the future. No FDT changes intended. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Chao Liu Reviewed-by: Alistair Francis Message-ID: <20260828203918.350131-3-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/fdt-common.h | 1 + hw/riscv/fdt-common.c | 12 ++++++++++++ hw/riscv/virt.c | 18 ++---------------- 3 files changed, 15 insertions(+), 16 deletions(-) diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index 371971d79d..b422da6aef 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -38,4 +38,5 @@ void riscv_create_fdt_plic(void *fdt, hwaddr addr, uint64= _t size, uint32_t cells_size, uint32_t ndev_sources, bool numa_enabled, int socket); void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name= ); +void riscv_create_fdt_flash(void *fdt, hwaddr flashbase, hwaddr flashsize); #endif diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index 3a8da03cfb..6fcc1ce21f 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -283,3 +283,15 @@ void riscv_pmu_generate_fdt_node(void *fdt, uint32_t c= mask, char *pmu_name) qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); } + +void riscv_create_fdt_flash(void *fdt, hwaddr flashbase, hwaddr flashsize) +{ + g_autofree char *name =3D g_strdup_printf("/flash@%" PRIx64, flashbase= ); + + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 2, flashbase, 2, flashsize, + 2, flashbase + flashsize, 2, flashsize); + qemu_fdt_setprop_cell(fdt, name, "bank-width", 4); +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ef97d04031..fec5f6d17a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -866,21 +866,6 @@ static void create_fdt_rtc(RISCVVirtState *s, } } =20 -static void create_fdt_flash(RISCVVirtState *s) -{ - MachineState *ms =3D MACHINE(s); - hwaddr flashsize =3D s->memmap[VIRT_FLASH].size / 2; - hwaddr flashbase =3D s->memmap[VIRT_FLASH].base; - g_autofree char *name =3D g_strdup_printf("/flash@%" PRIx64, flashbase= ); - - qemu_fdt_add_subnode(ms->fdt, name); - qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); - qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", - 2, flashbase, 2, flashsize, - 2, flashbase + flashsize, 2, flashsize); - qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); -} - static void create_fdt_fw_cfg(RISCVVirtState *s) { MachineState *ms =3D MACHINE(s); @@ -1042,7 +1027,8 @@ static void create_fdt(RISCVVirtState *s) =20 qemu_fdt_add_subnode(ms->fdt, "/aliases"); =20 - create_fdt_flash(s); + riscv_create_fdt_flash(ms->fdt, s->memmap[VIRT_FLASH].base, + s->memmap[VIRT_FLASH].size / 2); create_fdt_fw_cfg(s); create_fdt_pmu(s); } --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499291; cv=none; d=zohomail.com; s=zohoarc; b=EgEYMa4ef3zmHJANYViKH2Sc1IT3i8z482BpGwIkih3Fo4fNtMUhr0sJ6yUMT6PrCaCbdW1ZC/ZyWvVaEntfRNNqbKgmLe7g1vg9zuDjxMGAan5rXNb8Ikbo9n0ydGl43Vh/WYDS3yxlQ/xBJ9Gz1BkmeqtLNGnudbea23YsZmc= ARC-Message-Signature: i=1; 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Thu, 03 Sep 2026 22:20:44 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Chao Liu , Alistair Francis Subject: [PULL 16/47] hw/riscv/fdt-common, virt.c: add riscv_create_fdt_syscon() Date: Fri, 4 Sep 2026 15:19:12 +1000 Message-ID: <20260904051943.799041-17-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=alistair23@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499292563158500 From: Daniel Henrique Barboza The soon to be added riscv-server-ref board will declare a syscon FDT similar to what the 'virt' board already does. It won't have a 'sifive,test0' and 'sifive,test1' compat string though, hence we'll add a flag to enable/disable these additional properties. The FDT is slightly changed: the subnode is now named 'soc/syscon' instead of 'soc/test' to be compatible with the latest device-tree docs. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Chao Liu Reviewed-by: Alistair Francis Message-ID: <20260828203918.350131-4-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/fdt-common.h | 4 +++ hw/riscv/fdt-common.c | 54 +++++++++++++++++++++++++++++++++++ hw/riscv/virt.c | 46 +++-------------------------- 3 files changed, 62 insertions(+), 42 deletions(-) diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index b422da6aef..e377682b32 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -39,4 +39,8 @@ void riscv_create_fdt_plic(void *fdt, hwaddr addr, uint64= _t size, bool numa_enabled, int socket); void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name= ); void riscv_create_fdt_flash(void *fdt, hwaddr flashbase, hwaddr flashsize); +void riscv_create_fdt_syscon(void *fdt, uint32_t *next_phandle, + hwaddr addr, hwaddr size, + uint32_t reboot, uint32_t poweroff, + bool sifive_test_compat); #endif diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index 6fcc1ce21f..eac5ca9322 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -295,3 +295,57 @@ void riscv_create_fdt_flash(void *fdt, hwaddr flashbas= e, hwaddr flashsize) 2, flashbase + flashsize, 2, flashsize); qemu_fdt_setprop_cell(fdt, name, "bank-width", 4); } + +/* + * @sifive_test_compat is used to create a FDT that declares + * compat with "sifive,test1" and "sifive,test0". This happens + * to be the case for the 'virt' machine that also creates a + * 'sifive_test' syscon device. + */ +void riscv_create_fdt_syscon(void *fdt, uint32_t *next_phandle, + hwaddr addr, hwaddr size, + uint32_t reboot, uint32_t poweroff, + bool sifive_test_compat) +{ + uint32_t syscon_phandle; + char *name; + + name =3D g_strdup_printf("/soc/syscon@%"HWADDR_PRIx, addr); + qemu_fdt_add_subnode(fdt, name); + + if (sifive_test_compat) { + static const char * const compat[3] =3D { + "sifive,test1", "sifive,test0", "syscon" + }; + + qemu_fdt_setprop_string_array(fdt, name, "compatible", + (char **)&compat, ARRAY_SIZE(compat)= ); + } else { + qemu_fdt_setprop_string(fdt, name, "compatible", "syscon"); + } + + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 2, addr, + 2, size); + + syscon_phandle =3D next_phandle ? (*next_phandle)++ : qemu_fdt_alloc_p= handle(fdt); + qemu_fdt_setprop_cell(fdt, name, "phandle", syscon_phandle); + + g_free(name); + + name =3D g_strdup_printf("/reboot"); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); + qemu_fdt_setprop_cell(fdt, name, "regmap", syscon_phandle); + qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(fdt, name, "value", reboot); + g_free(name); + + name =3D g_strdup_printf("/poweroff"); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); + qemu_fdt_setprop_cell(fdt, name, "regmap", syscon_phandle); + qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(fdt, name, "value", poweroff); + g_free(name); +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index fec5f6d17a..1f7b4343d3 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -767,47 +767,6 @@ static void create_fdt_pcie(RISCVVirtState *s, create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); } =20 -static void create_fdt_reset(RISCVVirtState *s, uint32_t *phandle) -{ - char *name; - uint32_t test_phandle; - MachineState *ms =3D MACHINE(s); - - test_phandle =3D (*phandle)++; - name =3D g_strdup_printf("/soc/test@%"HWADDR_PRIx, - s->memmap[VIRT_TEST].base); - qemu_fdt_add_subnode(ms->fdt, name); - { - static const char * const compat[3] =3D { - "sifive,test1", "sifive,test0", "syscon" - }; - qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", - (char **)&compat, ARRAY_SIZE(compat)= ); - } - qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", - 2, s->memmap[VIRT_TEST].base, - 2, s->memmap[VIRT_TEST].size); - qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); - test_phandle =3D qemu_fdt_get_phandle(ms->fdt, name); - g_free(name); - - name =3D g_strdup_printf("/reboot"); - qemu_fdt_add_subnode(ms->fdt, name); - qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); - qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); - g_free(name); - - name =3D g_strdup_printf("/poweroff"); - qemu_fdt_add_subnode(ms->fdt, name); - qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"= ); - qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); - g_free(name); -} - static void create_fdt_uart(RISCVVirtState *s, uint32_t irq_mmio_phandle, int memId, int irqN= o) { @@ -993,7 +952,10 @@ static void finalize_fdt(RISCVVirtState *s) create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle, iommu_sys_phandle); =20 - create_fdt_reset(s, &phandle); + riscv_create_fdt_syscon(MACHINE(s)->fdt, &phandle, + s->memmap[VIRT_TEST].base, + s->memmap[VIRT_TEST].size, + FINISHER_RESET, FINISHER_PASS, true); =20 create_fdt_uarts(s, irq_mmio_phandle); =20 --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 03 Sep 2026 22:20:47 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Chao Liu , Alistair Francis Subject: [PULL 17/47] hw/riscv/fdt-common, virt.c: add riscv_create_fdt_riscv_iommu_sys() Date: Fri, 4 Sep 2026 15:19:13 +1000 Message-ID: <20260904051943.799041-18-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=alistair23@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499304606158500 From: Daniel Henrique Barboza Both the 'virt' board and the future 'riscv-server-ref' boards uses an iommu-sys device that is declared in the DT. Create a helper to encapsulate the logic and avoid copy/pasting stuff between boards. The helper will return the iommu phandle value instead of returning void and writing the used phandle in an extra argument. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Chao Liu Reviewed-by: Alistair Francis Message-ID: <20260828203918.350131-5-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/fdt-common.h | 5 ++++ hw/riscv/fdt-common.c | 35 ++++++++++++++++++++++++ hw/riscv/virt.c | 50 ++++++----------------------------- 3 files changed, 48 insertions(+), 42 deletions(-) diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index e377682b32..65711468b8 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -43,4 +43,9 @@ void riscv_create_fdt_syscon(void *fdt, uint32_t *next_ph= andle, hwaddr addr, hwaddr size, uint32_t reboot, uint32_t poweroff, bool sifive_test_compat); +uint32_t riscv_create_fdt_riscv_iommu_sys(void *fdt, hwaddr addr, hwaddr s= ize, + uint32_t *next_phandle, + uint32_t irq_chip, + uint32_t msi_phandle, + uint32_t iommu_sys_irq); #endif diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index eac5ca9322..88589330fb 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -13,6 +13,8 @@ #include "hw/core/boards.h" #include "hw/riscv/fdt-common.h" #include "target/riscv/cpu_bits.h" +#include "hw/riscv/riscv-iommu-bits.h" +#include "hw/riscv/iommu.h" =20 void *riscv_create_board_device_tree(const char *model, const char *compat= ible, int *fdt_size) @@ -349,3 +351,36 @@ void riscv_create_fdt_syscon(void *fdt, uint32_t *next= _phandle, qemu_fdt_setprop_cell(fdt, name, "value", poweroff); g_free(name); } + +uint32_t riscv_create_fdt_riscv_iommu_sys(void *fdt, hwaddr addr, hwaddr s= ize, + uint32_t *next_phandle, + uint32_t irq_chip, + uint32_t msi_phandle, + uint32_t iommu_sys_irq) +{ + const char comp[] =3D "riscv,iommu"; + g_autofree char *iommu_node =3D NULL; + uint32_t iommu_phandle; + + iommu_node =3D g_strdup_printf("/soc/iommu@%"HWADDR_PRIx, addr); + qemu_fdt_add_subnode(fdt, iommu_node); + + qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); + qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); + + iommu_phandle =3D next_phandle ? (*next_phandle)++ : qemu_fdt_alloc_ph= andle(fdt); + qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); + + qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 2, addr, 2, size); + qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); + + qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", + iommu_sys_irq + RISCV_IOMMU_INTR_CQ, FDT_IRQ_TYPE_EDGE_LOW, + iommu_sys_irq + RISCV_IOMMU_INTR_FQ, FDT_IRQ_TYPE_EDGE_LOW, + iommu_sys_irq + RISCV_IOMMU_INTR_PM, FDT_IRQ_TYPE_EDGE_LOW, + iommu_sys_irq + RISCV_IOMMU_INTR_PQ, FDT_IRQ_TYPE_EDGE_LOW); + + qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); + + return iommu_phandle; +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 1f7b4343d3..b0b94af4a3 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -868,46 +868,6 @@ static void create_fdt_virtio_iommu(RISCVVirtState *s,= uint16_t bdf) bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); } =20 -static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip, - uint32_t msi_phandle, - uint32_t *iommu_sys_phandle) -{ - const char comp[] =3D "riscv,iommu"; - void *fdt =3D MACHINE(s)->fdt; - uint32_t iommu_phandle; - g_autofree char *iommu_node =3D NULL; - hwaddr addr =3D s->memmap[VIRT_IOMMU_SYS].base; - hwaddr size =3D s->memmap[VIRT_IOMMU_SYS].size; - uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] =3D { - IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ, - IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ, - IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM, - IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ, - }; - - iommu_node =3D g_strdup_printf("/soc/iommu@%x", - (unsigned int) s->memmap[VIRT_IOMMU_SYS].ba= se); - iommu_phandle =3D qemu_fdt_alloc_phandle(fdt); - qemu_fdt_add_subnode(fdt, iommu_node); - - qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); - qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); - qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); - - qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 2, addr, 2, size); - qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); - - qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", - iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW, - iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW, - iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW, - iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW); - - qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); - - *iommu_sys_phandle =3D iommu_phandle; -} - static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf) { const char comp[] =3D "riscv,pci-iommu"; @@ -946,8 +906,14 @@ static void finalize_fdt(RISCVVirtState *s) create_fdt_virtio(s, irq_virtio_phandle); =20 if (virt_is_iommu_sys_enabled(s)) { - create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, - &iommu_sys_phandle); + iommu_sys_phandle =3D + riscv_create_fdt_riscv_iommu_sys(MACHINE(s)->fdt, + s->memmap[VIRT_IOMMU_SYS].bas= e, + s->memmap[VIRT_IOMMU_SYS].siz= e, + &phandle, + irq_mmio_phandle, + msi_pcie_phandle, + IOMMU_SYS_IRQ); } create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle, iommu_sys_phandle); --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 03 Sep 2026 22:20:50 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Chao Liu Subject: [PULL 18/47] hw/riscv/fdt_common, virt.c: add riscv_create_fdt_pcie() Date: Fri, 4 Sep 2026 15:19:14 +1000 Message-ID: <20260904051943.799041-19-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=alistair23@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499260307158501 From: Daniel Henrique Barboza The pcie FDT is quite tedious but can be parametrized into a helper. This is going to benefit only the 'virt' board for now but it will be used by the 'riscv-server-ref' board in the near future too. Some other changes made: - FDT related macros are moved to fdt-common.h. Only a couple are being used by the helper ATM but more will be added in the next patches; - an RISCVAIAType enum is created. There are several FDTs that depends on the active AIA type being used, and we want a way to represent the different AIA modes that doesn't re-use the 'virt' specific VIRT_AIA_* macros. The enum vals are equivalent by design - we want "s->aia_type" to be used by 'virt' when calling the fdt helpers, and other boards will use "AIA_*" macros in their code. No FDT changes made. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260828203918.350131-6-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/fdt-common.h | 29 +++++++++ include/hw/riscv/virt.h | 15 ----- hw/riscv/fdt-common.c | 111 ++++++++++++++++++++++++++++++++++ hw/riscv/virt.c | 111 +++------------------------------- 4 files changed, 149 insertions(+), 117 deletions(-) diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index 65711468b8..3750230865 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -11,6 +11,27 @@ =20 #include "target/riscv/cpu.h" =20 +#define FDT_PCI_ADDR_CELLS 3 +#define FDT_PCI_INT_CELLS 1 +#define FDT_PLIC_ADDR_CELLS 0 +#define FDT_PLIC_INT_CELLS 1 +#define FDT_APLIC_INT_CELLS 2 +#define FDT_APLIC_ADDR_CELLS 0 +#define FDT_IMSIC_INT_CELLS 0 +#define FDT_MAX_INT_CELLS 2 +#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ + 1 + FDT_MAX_INT_CELLS) +#define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ + 1 + FDT_PLIC_INT_CELLS) +#define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ + 1 + FDT_APLIC_INT_CELLS) + +typedef enum RISCVAIAType { + AIA_TYPE_NONE =3D 0, + AIA_TYPE_APLIC, + AIA_TYPE_APLIC_IMSIC, +} RISCVAIAType; + void *riscv_create_board_device_tree(const char *model, const char *compat= ible, int *fdt_size); void riscv_create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, @@ -48,4 +69,12 @@ uint32_t riscv_create_fdt_riscv_iommu_sys(void *fdt, hwa= ddr addr, hwaddr size, uint32_t irq_chip, uint32_t msi_phandle, uint32_t iommu_sys_irq); +void riscv_create_fdt_pcie(void *fdt, int aia_type, bool has_iommu_sys, + const MemMapEntry *pcie_ecam, + const MemMapEntry *pcie_pio, + const MemMapEntry *pcie_mmio, + const MemMapEntry *high_pcie, + uint32_t irq_pcie_phandle, + uint32_t msi_pcie_phandle, + uint32_t iommu_sys_phandle, uint32_t pcie_irq); #endif diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 7c862b0da2..e516898f9a 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -121,21 +121,6 @@ enum { #define VIRT_PLIC_SIZE(__num_context) \ (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) =20 -#define FDT_PCI_ADDR_CELLS 3 -#define FDT_PCI_INT_CELLS 1 -#define FDT_PLIC_ADDR_CELLS 0 -#define FDT_PLIC_INT_CELLS 1 -#define FDT_APLIC_INT_CELLS 2 -#define FDT_APLIC_ADDR_CELLS 0 -#define FDT_IMSIC_INT_CELLS 0 -#define FDT_MAX_INT_CELLS 2 -#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ - 1 + FDT_MAX_INT_CELLS) -#define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ - 1 + FDT_PLIC_INT_CELLS) -#define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ - 1 + FDT_APLIC_INT_CELLS) - bool virt_is_acpi_enabled(RISCVVirtState *s); bool virt_is_iommu_sys_enabled(RISCVVirtState *s); void virt_acpi_setup(RISCVVirtState *vms); diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index 88589330fb..38813b6aa7 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -15,6 +15,8 @@ #include "target/riscv/cpu_bits.h" #include "hw/riscv/riscv-iommu-bits.h" #include "hw/riscv/iommu.h" +#include "hw/pci/pci.h" +#include "hw/pci/pcie_host.h" =20 void *riscv_create_board_device_tree(const char *model, const char *compat= ible, int *fdt_size) @@ -384,3 +386,112 @@ uint32_t riscv_create_fdt_riscv_iommu_sys(void *fdt, = hwaddr addr, hwaddr size, =20 return iommu_phandle; } + +static void create_pcie_irq_map(void *fdt, char *nodename, + uint32_t irqchip_phandle, + RISCVAIAType aia_type, uint32_t pcie_irq) +{ + int pin, dev; + uint32_t irq_map_stride =3D 0; + uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * + FDT_MAX_INT_MAP_WIDTH] =3D {}; + uint32_t *irq_map =3D full_irq_map; + + /* + * This code creates a standard swizzle of interrupts such that + * each device's first interrupt is based on it's PCI_SLOT number. + * (See pci_swizzle_map_irq_fn()) + * + * We only need one entry per interrupt in the table (not one per + * possible slot) seeing the interrupt-map-mask will allow the table + * to wrap to any number of devices. + */ + for (dev =3D 0; dev < PCI_NUM_PINS; dev++) { + int devfn =3D dev * 0x8; + + for (pin =3D 0; pin < PCI_NUM_PINS; pin++) { + int irq_nr =3D pcie_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_P= INS); + int i =3D 0; + + /* Fill PCI address cells */ + irq_map[i] =3D cpu_to_be32(devfn << 8); + i +=3D FDT_PCI_ADDR_CELLS; + + /* Fill PCI Interrupt cells */ + irq_map[i] =3D cpu_to_be32(pin + 1); + i +=3D FDT_PCI_INT_CELLS; + + /* Fill interrupt controller phandle and cells */ + irq_map[i++] =3D cpu_to_be32(irqchip_phandle); + irq_map[i++] =3D cpu_to_be32(irq_nr); + + if (aia_type !=3D AIA_TYPE_NONE) { + irq_map[i++] =3D cpu_to_be32(0x4); + } + + if (!irq_map_stride) { + irq_map_stride =3D i; + } + irq_map +=3D irq_map_stride; + } + } + + qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, + PCI_NUM_PINS * PCI_NUM_PINS * + irq_map_stride * sizeof(uint32_t)); + + qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", + 0x1800, 0, 0, 0x7); +} + +/* + * NOTE: this function uses a "/soc/pci@..." FDT subnode that + * should be created beforehand. + */ +void riscv_create_fdt_pcie(void *fdt, int aia_type, bool has_iommu_sys, + const MemMapEntry *pcie_ecam, + const MemMapEntry *pcie_pio, + const MemMapEntry *pcie_mmio, + const MemMapEntry *high_pcie, + uint32_t irq_pcie_phandle, + uint32_t msi_pcie_phandle, + uint32_t iommu_sys_phandle, uint32_t pcie_irq) +{ + g_autofree char *name =3D NULL; + + name =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIx, pcie_ecam->base); + qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS= ); + qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); + qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generi= c"); + qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); + qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); + + qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, + pcie_ecam->size / PCIE_MMCFG_SIZE_MIN - 1); + qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); + + if (aia_type =3D=3D AIA_TYPE_APLIC_IMSIC) { + qemu_fdt_setprop_cell(fdt, name, "msi-parent", msi_pcie_phandle); + } + + qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, + pcie_ecam->base, 2, pcie_ecam->size); + + qemu_fdt_setprop_sized_cells(fdt, name, "ranges", + 1, FDT_PCI_RANGE_IOPORT, 2, 0, + 2, pcie_pio->base, 2, pcie_pio->size, + 1, FDT_PCI_RANGE_MMIO, + 2, pcie_mmio->base, + 2, pcie_mmio->base, 2, pcie_mmio->size, + 1, FDT_PCI_RANGE_MMIO_64BIT, + 2, high_pcie->base, + 2, high_pcie->base, 2, high_pcie->size); + + if (has_iommu_sys) { + qemu_fdt_setprop_cells(fdt, name, "iommu-map", + 0, iommu_sys_phandle, 0, 0x10000); + } + + create_pcie_irq_map(fdt, name, irq_pcie_phandle, aia_type, pcie_irq); +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index b0b94af4a3..cc81def8d4 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -179,61 +179,6 @@ static void virt_flash_map(RISCVVirtState *s, sysmem); } =20 -static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodena= me, - uint32_t irqchip_phandle) -{ - int pin, dev; - uint32_t irq_map_stride =3D 0; - uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * - FDT_MAX_INT_MAP_WIDTH] =3D {}; - uint32_t *irq_map =3D full_irq_map; - - /* - * This code creates a standard swizzle of interrupts such that - * each device's first interrupt is based on it's PCI_SLOT number. - * (See pci_swizzle_map_irq_fn()) - * - * We only need one entry per interrupt in the table (not one per - * possible slot) seeing the interrupt-map-mask will allow the table - * to wrap to any number of devices. - */ - for (dev =3D 0; dev < PCI_NUM_PINS; dev++) { - int devfn =3D dev * 0x8; - - for (pin =3D 0; pin < PCI_NUM_PINS; pin++) { - int irq_nr =3D PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % PCI_NUM_P= INS); - int i =3D 0; - - /* Fill PCI address cells */ - irq_map[i] =3D cpu_to_be32(devfn << 8); - i +=3D FDT_PCI_ADDR_CELLS; - - /* Fill PCI Interrupt cells */ - irq_map[i] =3D cpu_to_be32(pin + 1); - i +=3D FDT_PCI_INT_CELLS; - - /* Fill interrupt controller phandle and cells */ - irq_map[i++] =3D cpu_to_be32(irqchip_phandle); - irq_map[i++] =3D cpu_to_be32(irq_nr); - if (s->aia_type !=3D VIRT_AIA_TYPE_NONE) { - irq_map[i++] =3D cpu_to_be32(0x4); - } - - if (!irq_map_stride) { - irq_map_stride =3D i; - } - irq_map +=3D irq_map_stride; - } - } - - qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, - PCI_NUM_PINS * PCI_NUM_PINS * - irq_map_stride * sizeof(uint32_t)); - - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", - 0x1800, 0, 0, 0x7); -} - static void create_fdt_socket_aclint(RISCVVirtState *s, int socket, uint32_t *intc_phandles) @@ -722,51 +667,6 @@ static void create_fdt_virtio(RISCVVirtState *s, uint3= 2_t irq_virtio_phandle) } } =20 -static void create_fdt_pcie(RISCVVirtState *s, - uint32_t irq_pcie_phandle, - uint32_t msi_pcie_phandle, - uint32_t iommu_sys_phandle) -{ - g_autofree char *name =3D NULL; - MachineState *ms =3D MACHINE(s); - - name =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIx, - s->memmap[VIRT_PCIE_ECAM].base); - qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", - FDT_PCI_ADDR_CELLS); - qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", - FDT_PCI_INT_CELLS); - qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); - qemu_fdt_setprop_string(ms->fdt, name, "compatible", - "pci-host-ecam-generic"); - qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); - qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); - qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, - s->memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); - qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); - if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { - qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandl= e); - } - qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, - s->memmap[VIRT_PCIE_ECAM].base, 2, s->memmap[VIRT_PCIE_ECAM].size); - qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", - 1, FDT_PCI_RANGE_IOPORT, 2, 0, - 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size, - 1, FDT_PCI_RANGE_MMIO, - 2, s->memmap[VIRT_PCIE_MMIO].base, - 2, s->memmap[VIRT_PCIE_MMIO].base, 2, s->memmap[VIRT_PCIE_MMIO].si= ze, - 1, FDT_PCI_RANGE_MMIO_64BIT, - 2, virt_high_pcie_memmap.base, - 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); - - if (virt_is_iommu_sys_enabled(s)) { - qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map", - 0, iommu_sys_phandle, 0, 0x10000); - } - - create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); -} - static void create_fdt_uart(RISCVVirtState *s, uint32_t irq_mmio_phandle, int memId, int irqN= o) { @@ -915,8 +815,15 @@ static void finalize_fdt(RISCVVirtState *s) msi_pcie_phandle, IOMMU_SYS_IRQ); } - create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle, - iommu_sys_phandle); + + riscv_create_fdt_pcie(MACHINE(s)->fdt, s->aia_type, + virt_is_iommu_sys_enabled(s), + &s->memmap[VIRT_PCIE_ECAM], + &s->memmap[VIRT_PCIE_PIO], + &s->memmap[VIRT_PCIE_MMIO], + &virt_high_pcie_memmap, + irq_pcie_phandle, msi_pcie_phandle, + iommu_sys_phandle, PCIE_IRQ); =20 riscv_create_fdt_syscon(MACHINE(s)->fdt, &phandle, s->memmap[VIRT_TEST].base, --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 03 Sep 2026 22:20:53 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Chao Liu Subject: [PULL 19/47] hw/riscv/fdt_common, virt.c: add riscv_create_fdt_imsic() Date: Fri, 4 Sep 2026 15:19:15 +1000 Message-ID: <20260904051943.799041-20-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499284614158500 From: Daniel Henrique Barboza The FDT related to interrupt controllers should definitely be put into helpers, even if only 'virt' benefits from it, due to the amount of code that is relieved from the board alone. We'll start with 'imsic'. For this endeavor we're going to use a helper struct that will carry all the extra FDT arguments in a human format. The alternative would be to add 8 more function arguments, on top of 4 phandle arguments that we're passing around in all these controllers, and that's not only a poor reading experience but it's quite error prone too. We do not want to crowd the fdt-helper with non-FDT logic, hence we're handling the !kvm_enabled() cond in virt.c using the imsic_m_base argument. This is a pattern that we'll fall back on in the next patches too. No FDT changes made. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260828203918.350131-7-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/fdt-common.h | 21 +++++++ hw/riscv/fdt-common.c | 98 ++++++++++++++++++++++++++++++ hw/riscv/virt.c | 108 +++++----------------------------- 3 files changed, 133 insertions(+), 94 deletions(-) diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index 3750230865..182c03d8ce 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -10,6 +10,8 @@ #define RISCV_VIRT_FDT_H =20 #include "target/riscv/cpu.h" +#include "hw/core/boards.h" +#include "hw/riscv/riscv_hart.h" =20 #define FDT_PCI_ADDR_CELLS 3 #define FDT_PCI_INT_CELLS 1 @@ -32,6 +34,22 @@ typedef enum RISCVAIAType { AIA_TYPE_APLIC_IMSIC, } RISCVAIAType; =20 +typedef struct IMSICFdtProps { + /* + * Machines will statically allocate RISCVHartArrayState[] pointer, + * e.g. "RISCVHartArrayState soc[VIRT_SOCKETS_MAX]". We'll have + * to use a void* pointer to handle a soc with variable sizes. + */ + void *soc; + hwaddr imsic_m_base; + hwaddr imsic_s_base; + int socket_count; + int smp_cpus; + int imsic_group_max_size; + int irqchip_num_msis; + int aia_guests; +} IMSICFdtProps; + void *riscv_create_board_device_tree(const char *model, const char *compat= ible, int *fdt_size); void riscv_create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, @@ -77,4 +95,7 @@ void riscv_create_fdt_pcie(void *fdt, int aia_type, bool = has_iommu_sys, uint32_t irq_pcie_phandle, uint32_t msi_pcie_phandle, uint32_t iommu_sys_phandle, uint32_t pcie_irq); +void riscv_create_fdt_imsic(void *fdt, IMSICFdtProps *fdt_props, + uint32_t *next_phandle, uint32_t *intc_phandle= s, + uint32_t *msi_m_phandle, uint32_t *msi_s_phand= le); #endif diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index 38813b6aa7..ae24ad0011 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -15,8 +15,10 @@ #include "target/riscv/cpu_bits.h" #include "hw/riscv/riscv-iommu-bits.h" #include "hw/riscv/iommu.h" +#include "hw/intc/riscv_imsic.h" #include "hw/pci/pci.h" #include "hw/pci/pcie_host.h" +#include "hw/riscv/aia.h" =20 void *riscv_create_board_device_tree(const char *model, const char *compat= ible, int *fdt_size) @@ -495,3 +497,99 @@ void riscv_create_fdt_pcie(void *fdt, int aia_type, bo= ol has_iommu_sys, =20 create_pcie_irq_map(fdt, name, irq_pcie_phandle, aia_type, pcie_irq); } + +static void create_fdt_one_imsic(void *fdt, IMSICFdtProps *props, + hwaddr base_addr, + uint32_t *intc_phandles, uint32_t msi_pha= ndle, + bool m_mode, uint32_t imsic_guest_bits) +{ + RISCVHartArrayState *soc =3D (RISCVHartArrayState *)props->soc; + g_autofree char *imsic_name =3D NULL; + g_autofree uint32_t *imsic_cells =3D NULL; + g_autofree uint32_t *imsic_regs =3D NULL; + uint32_t imsic_max_hart_per_socket =3D 0; + static const char * const imsic_compat[2] =3D { + "qemu,imsics", "riscv,imsics" + }; + + imsic_cells =3D g_new0(uint32_t, props->smp_cpus * 2); + imsic_regs =3D g_new0(uint32_t, props->socket_count * 4); + + for (int cpu =3D 0; cpu < props->smp_cpus; cpu++) { + imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_= S_EXT); + } + + for (int socket =3D 0; socket < props->socket_count; socket++) { + hwaddr imsic_addr =3D base_addr + socket * props->imsic_group_max_= size; + uint32_t imsic_size =3D IMSIC_HART_SIZE(imsic_guest_bits) * + soc[socket].num_harts; + + imsic_regs[socket * 4 + 0] =3D cpu_to_be32(imsic_addr >> 32); + imsic_regs[socket * 4 + 1] =3D cpu_to_be32(imsic_addr); + imsic_regs[socket * 4 + 2] =3D 0; + imsic_regs[socket * 4 + 3] =3D cpu_to_be32(imsic_size); + if (imsic_max_hart_per_socket < soc[socket].num_harts) { + imsic_max_hart_per_socket =3D soc[socket].num_harts; + } + } + + imsic_name =3D g_strdup_printf("/soc/interrupt-controller@%"HWADDR_PRI= x, + base_addr); + qemu_fdt_add_subnode(fdt, imsic_name); + + qemu_fdt_setprop_string_array(fdt, imsic_name, "compatible", + (char **)&imsic_compat, + ARRAY_SIZE(imsic_compat)); + + qemu_fdt_setprop_cell(fdt, imsic_name, "#interrupt-cells", + FDT_IMSIC_INT_CELLS); + qemu_fdt_setprop(fdt, imsic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(fdt, imsic_name, "msi-controller", NULL, 0); + qemu_fdt_setprop(fdt, imsic_name, "interrupts-extended", + imsic_cells, props->smp_cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(fdt, imsic_name, "reg", imsic_regs, + props->socket_count * sizeof(uint32_t) * 4); + qemu_fdt_setprop_cell(fdt, imsic_name, "riscv,num-ids", + props->irqchip_num_msis); + + if (imsic_guest_bits) { + qemu_fdt_setprop_cell(fdt, imsic_name, "riscv,guest-index-bits", + imsic_guest_bits); + } + + if (props->socket_count > 1) { + qemu_fdt_setprop_cell(fdt, imsic_name, "riscv,hart-index-bits", + imsic_num_bits(imsic_max_hart_per_socket)); + qemu_fdt_setprop_cell(fdt, imsic_name, "riscv,group-index-bits", + imsic_num_bits(props->socket_count)); + qemu_fdt_setprop_cell(fdt, imsic_name, "riscv,group-index-shift", + IMSIC_MMIO_GROUP_MIN_SHIFT); + } + qemu_fdt_setprop_cell(fdt, imsic_name, "phandle", msi_phandle); +} + +void riscv_create_fdt_imsic(void *fdt, IMSICFdtProps *props, + uint32_t *next_phandle, uint32_t *intc_phandle= s, + uint32_t *msi_m_phandle, uint32_t *msi_s_phand= le) +{ + if (next_phandle) { + *msi_m_phandle =3D (*next_phandle)++; + *msi_s_phandle =3D (*next_phandle)++; + } else { + *msi_m_phandle =3D qemu_fdt_alloc_phandle(fdt); + *msi_s_phandle =3D qemu_fdt_alloc_phandle(fdt); + } + + if (props->imsic_m_base) { + /* M-level IMSIC node */ + create_fdt_one_imsic(fdt, props, props->imsic_m_base, + intc_phandles, *msi_m_phandle, true, 0); + } + + /* S-level IMSIC node */ + create_fdt_one_imsic(fdt, props, props->imsic_s_base, + intc_phandles, *msi_s_phandle, false, + imsic_num_bits(props->aia_guests + 1)); + +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index cc81def8d4..cb6cd8f030 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -319,98 +319,6 @@ static void create_fdt_socket_plic(RISCVVirtState *s, } } =20 -static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, - uint32_t *intc_phandles, uint32_t msi_pha= ndle, - bool m_mode, uint32_t imsic_guest_bits) -{ - int cpu, socket; - g_autofree char *imsic_name =3D NULL; - MachineState *ms =3D MACHINE(s); - int socket_count =3D riscv_socket_count(ms); - uint32_t imsic_max_hart_per_socket, imsic_size; - hwaddr imsic_addr; - g_autofree uint32_t *imsic_cells =3D NULL; - g_autofree uint32_t *imsic_regs =3D NULL; - static const char * const imsic_compat[2] =3D { - "qemu,imsics", "riscv,imsics" - }; - - imsic_cells =3D g_new0(uint32_t, ms->smp.cpus * 2); - imsic_regs =3D g_new0(uint32_t, socket_count * 4); - - for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { - imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_= S_EXT); - } - - imsic_max_hart_per_socket =3D 0; - for (socket =3D 0; socket < socket_count; socket++) { - imsic_addr =3D base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; - imsic_size =3D IMSIC_HART_SIZE(imsic_guest_bits) * - s->soc[socket].num_harts; - imsic_regs[socket * 4 + 0] =3D cpu_to_be32(imsic_addr >> 32); - imsic_regs[socket * 4 + 1] =3D cpu_to_be32(imsic_addr); - imsic_regs[socket * 4 + 2] =3D 0; - imsic_regs[socket * 4 + 3] =3D cpu_to_be32(imsic_size); - if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { - imsic_max_hart_per_socket =3D s->soc[socket].num_harts; - } - } - - imsic_name =3D g_strdup_printf("/soc/interrupt-controller@%lx", - (unsigned long)base_addr); - qemu_fdt_add_subnode(ms->fdt, imsic_name); - qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible", - (char **)&imsic_compat, - ARRAY_SIZE(imsic_compat)); - - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", - FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); - qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", - imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, - socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", - VIRT_IRQCHIP_NUM_MSIS); - - if (imsic_guest_bits) { - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits= ", - imsic_guest_bits); - } - - if (socket_count > 1) { - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", - imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits= ", - imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shif= t", - IMSIC_MMIO_GROUP_MIN_SHIFT); - } - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); -} - -static void create_fdt_imsic(RISCVVirtState *s, - uint32_t *phandle, uint32_t *intc_phandles, - uint32_t *msi_m_phandle, uint32_t *msi_s_phan= dle) -{ - *msi_m_phandle =3D (*phandle)++; - *msi_s_phandle =3D (*phandle)++; - - if (!kvm_enabled()) { - /* M-level IMSIC node */ - create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_M].base, intc_phandle= s, - *msi_m_phandle, true, 0); - } - - /* S-level IMSIC node */ - create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_S].base, intc_phandles, - *msi_s_phandle, false, - imsic_num_bits(s->aia_guests + 1)); - -} - /* Caller must free string after use */ static char *fdt_get_aplic_nodename(unsigned long aplic_addr) { @@ -584,8 +492,20 @@ static void create_fdt_sockets(RISCVVirtState *s, } =20 if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { - create_fdt_imsic(s, phandle, intc_phandles, - &msi_m_phandle, &msi_s_phandle); + IMSICFdtProps props =3D { + .soc =3D &s->soc, + .socket_count =3D riscv_socket_count(ms), + .smp_cpus =3D ms->smp.cpus, + .imsic_m_base =3D !kvm_enabled() ? s->memmap[VIRT_IMSIC_M].bas= e : 0, + .imsic_s_base =3D s->memmap[VIRT_IMSIC_S].base, + .imsic_group_max_size =3D VIRT_IMSIC_GROUP_MAX_SIZE, + .irqchip_num_msis =3D VIRT_IRQCHIP_NUM_MSIS, + .aia_guests =3D s->aia_guests + }; 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Thu, 03 Sep 2026 22:20:57 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Chao Liu Subject: [PULL 20/47] hw/riscv/fdt_common, virt.c: add riscv_create_fdt_socket_aplic() Date: Fri, 4 Sep 2026 15:19:16 +1000 Message-ID: <20260904051943.799041-21-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=alistair23@gmail.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499292489158500 From: Daniel Henrique Barboza Similar to what we did with 'imsic' in the previous patch, including creating a helper struct to encapsulate the extra arguments required to create the FDT. TODO: I believe the tt-atlantis board can use this same helper too. We just need to verify how to map the phandles used by it and what the helper is using (which was inherited by the 'virt' board). No FDT changes intended. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260828203918.350131-8-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/fdt-common.h | 19 +++++ hw/riscv/fdt-common.c | 109 ++++++++++++++++++++++++++ hw/riscv/virt.c | 139 ++++++---------------------------- 3 files changed, 151 insertions(+), 116 deletions(-) diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index 182c03d8ce..8207cfee7b 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -12,6 +12,7 @@ #include "target/riscv/cpu.h" #include "hw/core/boards.h" #include "hw/riscv/riscv_hart.h" +#include "exec/hwaddr.h" =20 #define FDT_PCI_ADDR_CELLS 3 #define FDT_PCI_INT_CELLS 1 @@ -50,6 +51,18 @@ typedef struct IMSICFdtProps { int aia_guests; } IMSICFdtProps; =20 +typedef struct APLICFdtProps { + const MemMapEntry *aplic_m; + const MemMapEntry *aplic_s; + const MemMapEntry *platform_bus; + int platform_bus_irq; + int socket; + int num_harts; + bool numa_enabled; + int irqchip_num_sources; + int aia_type; +} APLICFdtProps; + void *riscv_create_board_device_tree(const char *model, const char *compat= ible, int *fdt_size); void riscv_create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, @@ -98,4 +111,10 @@ void riscv_create_fdt_pcie(void *fdt, int aia_type, boo= l has_iommu_sys, void riscv_create_fdt_imsic(void *fdt, IMSICFdtProps *fdt_props, uint32_t *next_phandle, uint32_t *intc_phandle= s, uint32_t *msi_m_phandle, uint32_t *msi_s_phand= le); +void riscv_create_fdt_socket_aplic(void *fdt, APLICFdtProps *props, + uint32_t msi_m_phandle, + uint32_t msi_s_phandle, + uint32_t *next_phandle, + uint32_t *intc_phandles, + uint32_t *aplic_phandles); #endif diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index ae24ad0011..d815c5adff 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -11,6 +11,7 @@ #include "qemu/error-report.h" #include "system/device_tree.h" #include "hw/core/boards.h" +#include "hw/core/sysbus-fdt.h" #include "hw/riscv/fdt-common.h" #include "target/riscv/cpu_bits.h" #include "hw/riscv/riscv-iommu-bits.h" @@ -593,3 +594,111 @@ void riscv_create_fdt_imsic(void *fdt, IMSICFdtProps = *props, imsic_num_bits(props->aia_guests + 1)); =20 } + +/* Caller must free string after use */ +static char *fdt_get_aplic_nodename(hwaddr aplic_addr) +{ + return g_strdup_printf("/soc/interrupt-controller@%"HWADDR_PRIx, + aplic_addr); +} + +static void create_fdt_one_aplic(void *fdt, APLICFdtProps *props, + hwaddr aplic_addr, uint32_t aplic_size, + uint32_t msi_phandle, + uint32_t *intc_phandles, + uint32_t aplic_phandle, + uint32_t aplic_child_phandle, + bool m_mode) +{ + g_autofree char *aplic_name =3D fdt_get_aplic_nodename(aplic_addr); + g_autofree uint32_t *aplic_cells =3D g_new0(uint32_t, props->num_harts= * 2); + static const char * const aplic_compat[2] =3D { + "qemu,aplic", "riscv,aplic" + }; + + for (int cpu =3D 0; cpu < props->num_harts; cpu++) { + aplic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_= S_EXT); + } + + qemu_fdt_add_subnode(fdt, aplic_name); + qemu_fdt_setprop_string_array(fdt, aplic_name, "compatible", + (char **)&aplic_compat, + ARRAY_SIZE(aplic_compat)); + qemu_fdt_setprop_cell(fdt, aplic_name, "#address-cells", + FDT_APLIC_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, aplic_name, + "#interrupt-cells", FDT_APLIC_INT_CELLS); + qemu_fdt_setprop(fdt, aplic_name, "interrupt-controller", NULL, 0); + + if (props->aia_type =3D=3D AIA_TYPE_APLIC) { + qemu_fdt_setprop(fdt, aplic_name, "interrupts-extended", + aplic_cells, props->num_harts * sizeof(uint32_t) = * 2); + } else { + qemu_fdt_setprop_cell(fdt, aplic_name, "msi-parent", msi_phandle); + } + + qemu_fdt_setprop_sized_cells(fdt, aplic_name, "reg", + 2, aplic_addr, 2, aplic_size); + qemu_fdt_setprop_cell(fdt, aplic_name, "riscv,num-sources", + props->irqchip_num_sources); + + if (aplic_child_phandle) { + qemu_fdt_setprop_cell(fdt, aplic_name, "riscv,children", + aplic_child_phandle); + qemu_fdt_setprop_cells(fdt, aplic_name, "riscv,delegation", + aplic_child_phandle, 0x1, + props->irqchip_num_sources); + } + + if (props->numa_enabled) { + qemu_fdt_setprop_cell(fdt, aplic_name, "numa-node-id", props->sock= et); + } + + qemu_fdt_setprop_cell(fdt, aplic_name, "phandle", aplic_phandle); +} + +void riscv_create_fdt_socket_aplic(void *fdt, APLICFdtProps *props, + uint32_t msi_m_phandle, + uint32_t msi_s_phandle, + uint32_t *next_phandle, + uint32_t *intc_phandles, + uint32_t *aplic_phandles) +{ + uint32_t aplic_m_phandle, aplic_s_phandle; + hwaddr aplic_addr; + + if (next_phandle) { + aplic_m_phandle =3D (*next_phandle)++; + aplic_s_phandle =3D (*next_phandle)++; + } else { + aplic_m_phandle =3D qemu_fdt_alloc_phandle(fdt); + aplic_s_phandle =3D qemu_fdt_alloc_phandle(fdt); + } + + if (props->aplic_m) { + /* M-level APLIC node */ + aplic_addr =3D props->aplic_m->base + (props->aplic_m->size * prop= s->socket); + create_fdt_one_aplic(fdt, props, aplic_addr, props->aplic_m->size, + msi_m_phandle, intc_phandles, + aplic_m_phandle, aplic_s_phandle, + true); + } + + /* S-level APLIC node */ + aplic_addr =3D props->aplic_s->base + (props->aplic_s->size * props->s= ocket); + create_fdt_one_aplic(fdt, props, aplic_addr, props->aplic_s->size, + msi_s_phandle, intc_phandles, + aplic_s_phandle, 0, + false); + + if (!props->socket && props->platform_bus_irq) { + g_autofree char *aplic_name =3D fdt_get_aplic_nodename(aplic_addr); + platform_bus_add_all_fdt_nodes(fdt, aplic_name, + props->platform_bus->base, + props->platform_bus->size, + props->platform_bus_irq); + } + + aplic_phandles[props->socket] =3D aplic_s_phandle; +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index cb6cd8f030..63a32de3b4 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -319,113 +319,6 @@ static void create_fdt_socket_plic(RISCVVirtState *s, } } =20 -/* Caller must free string after use */ -static char *fdt_get_aplic_nodename(unsigned long aplic_addr) -{ - return g_strdup_printf("/soc/interrupt-controller@%lx", aplic_addr); -} - -static void create_fdt_one_aplic(RISCVVirtState *s, int socket, - unsigned long aplic_addr, uint32_t aplic_= size, - uint32_t msi_phandle, - uint32_t *intc_phandles, - uint32_t aplic_phandle, - uint32_t aplic_child_phandle, - bool m_mode, int num_harts) -{ - int cpu; - g_autofree char *aplic_name =3D fdt_get_aplic_nodename(aplic_addr); - g_autofree uint32_t *aplic_cells =3D g_new0(uint32_t, num_harts * 2); - MachineState *ms =3D MACHINE(s); - static const char * const aplic_compat[2] =3D { - "qemu,aplic", "riscv,aplic" - }; - - for (cpu =3D 0; cpu < num_harts; cpu++) { - aplic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_= S_EXT); - } - - qemu_fdt_add_subnode(ms->fdt, aplic_name); - qemu_fdt_setprop_string_array(ms->fdt, aplic_name, "compatible", - (char **)&aplic_compat, - ARRAY_SIZE(aplic_compat)); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#address-cells", - FDT_APLIC_ADDR_CELLS); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, - "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); - - if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", - aplic_cells, num_harts * sizeof(uint32_t) * 2); - } else { - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phand= le); - } - - qemu_fdt_setprop_sized_cells(ms->fdt, aplic_name, "reg", - 2, aplic_addr, 2, aplic_size); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", - VIRT_IRQCHIP_NUM_SOURCES); - - if (aplic_child_phandle) { - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", - aplic_child_phandle); - qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegation", - aplic_child_phandle, 0x1, - VIRT_IRQCHIP_NUM_SOURCES); - } - - riscv_socket_fdt_write_id(ms, aplic_name, socket); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); -} - -static void create_fdt_socket_aplic(RISCVVirtState *s, - int socket, - uint32_t msi_m_phandle, - uint32_t msi_s_phandle, - uint32_t *phandle, - uint32_t *intc_phandles, - uint32_t *aplic_phandles, - int num_harts) -{ - unsigned long aplic_addr; - MachineState *ms =3D MACHINE(s); - uint32_t aplic_m_phandle, aplic_s_phandle; - - aplic_m_phandle =3D (*phandle)++; - aplic_s_phandle =3D (*phandle)++; - - if (!kvm_enabled()) { - /* M-level APLIC node */ - aplic_addr =3D s->memmap[VIRT_APLIC_M].base + - (s->memmap[VIRT_APLIC_M].size * socket); - create_fdt_one_aplic(s, socket, aplic_addr, - s->memmap[VIRT_APLIC_M].size, - msi_m_phandle, intc_phandles, - aplic_m_phandle, aplic_s_phandle, - true, num_harts); - } - - /* S-level APLIC node */ - aplic_addr =3D s->memmap[VIRT_APLIC_S].base + - (s->memmap[VIRT_APLIC_S].size * socket); - create_fdt_one_aplic(s, socket, aplic_addr, s->memmap[VIRT_APLIC_S].si= ze, - msi_s_phandle, intc_phandles, - aplic_s_phandle, 0, - false, num_harts); - - if (!socket) { - g_autofree char *aplic_name =3D fdt_get_aplic_nodename(aplic_addr); - platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, - s->memmap[VIRT_PLATFORM_BUS].base, - s->memmap[VIRT_PLATFORM_BUS].size, - VIRT_PLATFORM_BUS_IRQ); - } - - aplic_phandles[socket] =3D aplic_s_phandle; -} - static void create_fdt_pmu(RISCVVirtState *s) { g_autofree char *pmu_name =3D g_strdup_printf("/pmu"); @@ -452,6 +345,7 @@ static void create_fdt_sockets(RISCVVirtState *s, int socket_count =3D riscv_socket_count(ms); bool numa_enabled =3D riscv_numa_enabled(ms); bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); + APLICFdtProps aplic_props; =20 riscv_fdt_create_cpu_socket_subnode(ms->fdt, kvm_enabled() ? kvm_riscv_get_timebase_frequency(&s->soc->harts[0]= ) : @@ -509,15 +403,26 @@ static void create_fdt_sockets(RISCVVirtState *s, *msi_pcie_phandle =3D msi_s_phandle; } =20 + if (s->aia_type !=3D VIRT_AIA_TYPE_NONE) { + aplic_props.aplic_m =3D !kvm_enabled() ? &s->memmap[VIRT_APLIC_M] = : NULL; + aplic_props.aplic_s =3D &s->memmap[VIRT_APLIC_S]; + aplic_props.platform_bus =3D &s->memmap[VIRT_PLATFORM_BUS]; + aplic_props.platform_bus_irq =3D VIRT_PLATFORM_BUS_IRQ; + aplic_props.socket =3D 0; + aplic_props.num_harts =3D ms->smp.cpus; + aplic_props.numa_enabled =3D numa_enabled; + aplic_props.irqchip_num_sources =3D VIRT_IRQCHIP_NUM_SOURCES; + aplic_props.aia_type =3D s->aia_type; + } + /* * With KVM AIA aplic-imsic, using an irqchip without split * mode, we'll use only one APLIC instance. */ if (!virt_use_emulated_aplic(s->aia_type)) { - create_fdt_socket_aplic(s, 0, - msi_m_phandle, msi_s_phandle, phandle, - &intc_phandles[0], xplic_phandles, - ms->smp.cpus); + riscv_create_fdt_socket_aplic(ms->fdt, &aplic_props, + msi_m_phandle, msi_s_phandle, phandl= e, + &intc_phandles[0], xplic_phandles); =20 *irq_mmio_phandle =3D xplic_phandles[0]; *irq_virtio_phandle =3D xplic_phandles[0]; @@ -532,11 +437,13 @@ static void create_fdt_sockets(RISCVVirtState *s, &intc_phandles[phandle_pos], xplic_phandles); } else { - create_fdt_socket_aplic(s, socket, - msi_m_phandle, msi_s_phandle, phan= dle, - &intc_phandles[phandle_pos], - xplic_phandles, - s->soc[socket].num_harts); + aplic_props.socket =3D socket; + aplic_props.num_harts =3D s->soc[socket].num_harts; + riscv_create_fdt_socket_aplic(ms->fdt, &aplic_props, + msi_m_phandle, msi_s_phandle, + phandle, + &intc_phandles[phandle_pos], + xplic_phandles); } } =20 --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499417; cv=none; d=zohomail.com; s=zohoarc; b=aHEQGGA/Uj+OfjuCP0SgB76aWDsXJSyyiRALIuB+YNZBeEO5yh8eFdg7xP2u7cgNKK1AzUmfb323MqPMhwek6Ke2YafR4hoi4XpXpnldINKIPtZeIOm1XgqpgrQ+fi5LUXKKKVhAqP+Qsn5lgwlneSfE41gkYCVQ9ZnOmrxg45U= ARC-Message-Signature: i=1; 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Thu, 03 Sep 2026 22:21:00 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , qemu-stable@nongnu.org, Chao Liu , Alistair Francis Subject: [PULL 21/47] hw/riscv/virt.c: fix aclint soc/mtimer nodename Date: Fri, 4 Sep 2026 15:19:17 +1000 Message-ID: <20260904051943.799041-22-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=alistair23@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499418928158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Running 'dtc' to generate a readable fdt for the virt machine produce warnings: $ dtc -I dtb -O dts virt.dtb > virt.dts : Warning (simple_bus_reg): /soc/mtimer@2000000: simple-bus unit ad= dress format error, expected "2007ff8" : Warning (simple_bus_reg): /soc/mtimer@2008000: simple-bus unit ad= dress format error, expected "200fff8" This happens because the 'reg' field does not match the address in the nodename. The right fix, pointed out by Chao in [1], is to make the nodename match the reg value: "In the current QEMU implement, `addr` is the MTIMECMP base address, while the MTIME register is located at addr + RISCV_ACLINT_DEFAULT_MTIME." In other words, the 'reg' value is correct but the nodename isn't. We'll make the fix now, allowing the next patch to move the fixed version of aclint FDT to fdt-common. [1] https://lore.kernel.org/qemu-devel/apHH1upnh8udUUT-@ChaodeMacBook-Pro.l= ocal/ Cc: qemu-stable@nongnu.org Suggested-by: Chao Liu Fixes: 954886ea6d ("hw/riscv: virt: Add optional ACLINT support to virt mac= hine") Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260828203918.350131-9-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 63a32de3b4..840dd0e075 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -233,7 +233,8 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, (s->memmap[VIRT_CLINT].size * socket); size =3D s->memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; } - name =3D g_strdup_printf("/soc/mtimer@%lx", addr); + name =3D g_strdup_printf("/soc/mtimer@%"HWADDR_PRIx, + addr + RISCV_ACLINT_DEFAULT_MTIME); qemu_fdt_add_subnode(ms->fdt, name); qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mtimer"); 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Thu, 03 Sep 2026 22:21:03 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Chao Liu Subject: [PULL 22/47] hw/riscv/fdt-common, virt.c: add riscv_create_fdt_socket_aclint() Date: Fri, 4 Sep 2026 15:19:18 +1000 Message-ID: <20260904051943.799041-23-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499459181158500 From: Daniel Henrique Barboza Yet another FDT that we want to move to a helper to avoid copy/pasting code to other boards that will use a mtimer. In particular the future 'riscv-server-ref' board. No FDT changes made. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260828203918.350131-10-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/fdt-common.h | 11 ++++ hw/riscv/fdt-common.c | 97 ++++++++++++++++++++++++++++++++ hw/riscv/virt.c | 102 ++++------------------------------ 3 files changed, 120 insertions(+), 90 deletions(-) diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index 8207cfee7b..a45b063f66 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -63,6 +63,15 @@ typedef struct APLICFdtProps { int aia_type; } APLICFdtProps; =20 +typedef struct ACLINTFdtProps { + const MemMapEntry *clint; + const MemMapEntry *aclint_sswi; + int socket; + int num_harts; + int aia_type; + bool numa_enabled; +} ACLINTFdtProps; + void *riscv_create_board_device_tree(const char *model, const char *compat= ible, int *fdt_size); void riscv_create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, @@ -117,4 +126,6 @@ void riscv_create_fdt_socket_aplic(void *fdt, APLICFdtP= rops *props, uint32_t *next_phandle, uint32_t *intc_phandles, uint32_t *aplic_phandles); +void riscv_create_fdt_socket_aclint(void *fdt, ACLINTFdtProps *props, + uint32_t *intc_phandles); #endif diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index d815c5adff..d2ce93ad28 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -16,6 +16,7 @@ #include "target/riscv/cpu_bits.h" #include "hw/riscv/riscv-iommu-bits.h" #include "hw/riscv/iommu.h" +#include "hw/intc/riscv_aclint.h" #include "hw/intc/riscv_imsic.h" #include "hw/pci/pci.h" #include "hw/pci/pcie_host.h" @@ -702,3 +703,99 @@ void riscv_create_fdt_socket_aplic(void *fdt, APLICFdt= Props *props, =20 aplic_phandles[props->socket] =3D aplic_s_phandle; } + +void riscv_create_fdt_socket_aclint(void *fdt, ACLINTFdtProps *props, + uint32_t *intc_phandles) +{ + uint32_t aclint_cells_size =3D props->num_harts * sizeof(uint32_t) * 2; + g_autofree uint32_t *aclint_mswi_cells =3D NULL; + g_autofree uint32_t *aclint_sswi_cells =3D NULL; + g_autofree uint32_t *aclint_mtimer_cells =3D NULL; + hwaddr addr, size; + char *name; + int cpu; + + aclint_mswi_cells =3D g_new0(uint32_t, props->num_harts * 2); + aclint_mtimer_cells =3D g_new0(uint32_t, props->num_harts * 2); + aclint_sswi_cells =3D g_new0(uint32_t, props->num_harts * 2); + + for (cpu =3D 0; cpu < props->num_harts; cpu++) { + aclint_mswi_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + aclint_mswi_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_SOFT); + aclint_mtimer_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu= ]); + aclint_mtimer_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_TIMER); + aclint_sswi_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + aclint_sswi_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_S_SOFT); + } + + if (props->aia_type !=3D AIA_TYPE_APLIC_IMSIC) { + addr =3D props->clint->base + (props->clint->size * props->socket); + name =3D g_strdup_printf("/soc/mswi@%"HWADDR_PRIx, addr); + + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "riscv,aclint-msw= i"); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 2, addr, 2, RISCV_ACLINT_SWI_SIZE); + qemu_fdt_setprop(fdt, name, "interrupts-extended", + aclint_mswi_cells, aclint_cells_size); + qemu_fdt_setprop(fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", 0); + + if (props->numa_enabled) { + qemu_fdt_setprop_cell(fdt, name, "numa-node-id", props->socket= ); + } + + g_free(name); + } + + if (props->aia_type =3D=3D AIA_TYPE_APLIC_IMSIC) { + addr =3D props->clint->base + + (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * props->socket); + size =3D RISCV_ACLINT_DEFAULT_MTIMER_SIZE; + } else { + addr =3D props->clint->base + RISCV_ACLINT_SWI_SIZE + + (props->clint->size * props->socket); + size =3D props->clint->size - RISCV_ACLINT_SWI_SIZE; + } + + name =3D g_strdup_printf("/soc/mtimer@%"HWADDR_PRIx, + addr + RISCV_ACLINT_DEFAULT_MTIME); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", + "riscv,aclint-mtimer"); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 2, addr + RISCV_ACLINT_DEFAULT_MTIME, + 2, size - RISCV_ACLINT_DEFAULT_MTIME, + 2, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, + 2, RISCV_ACLINT_DEFAULT_MTIME); + qemu_fdt_setprop(fdt, name, "interrupts-extended", + aclint_mtimer_cells, aclint_cells_size); + + if (props->numa_enabled) { + qemu_fdt_setprop_cell(fdt, name, "numa-node-id", props->socket); + } + + g_free(name); + + if (props->aia_type !=3D AIA_TYPE_APLIC_IMSIC) { + addr =3D props->aclint_sswi->base + + (props->aclint_sswi->size * props->socket); + + name =3D g_strdup_printf("/soc/sswi@%"HWADDR_PRIx, addr); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", + "riscv,aclint-sswi"); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 2, addr, 2, props->aclint_sswi->size); + qemu_fdt_setprop(fdt, name, "interrupts-extended", + aclint_sswi_cells, aclint_cells_size); + qemu_fdt_setprop(fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", 0); + + if (props->numa_enabled) { + qemu_fdt_setprop_cell(fdt, name, "numa-node-id", props->socket= ); + } + + g_free(name); + } +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 840dd0e075..c9b1a669a5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -179,94 +179,6 @@ static void virt_flash_map(RISCVVirtState *s, sysmem); } =20 -static void create_fdt_socket_aclint(RISCVVirtState *s, - int socket, - uint32_t *intc_phandles) -{ - int cpu; - char *name; - unsigned long addr, size; - uint32_t aclint_cells_size; - g_autofree uint32_t *aclint_mswi_cells =3D NULL; - g_autofree uint32_t *aclint_sswi_cells =3D NULL; - g_autofree uint32_t *aclint_mtimer_cells =3D NULL; - MachineState *ms =3D MACHINE(s); - - aclint_mswi_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2); - aclint_mtimer_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2); - aclint_sswi_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2); - - for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { - aclint_mswi_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - aclint_mswi_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_SOFT); - aclint_mtimer_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu= ]); - aclint_mtimer_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_TIMER); - aclint_sswi_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - aclint_sswi_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_S_SOFT); - } - aclint_cells_size =3D s->soc[socket].num_harts * sizeof(uint32_t) * 2; - - if (s->aia_type !=3D VIRT_AIA_TYPE_APLIC_IMSIC) { - addr =3D s->memmap[VIRT_CLINT].base + - (s->memmap[VIRT_CLINT].size * socket); - name =3D g_strdup_printf("/soc/mswi@%lx", addr); - - qemu_fdt_add_subnode(ms->fdt, name); - qemu_fdt_setprop_string(ms->fdt, name, "compatible", - "riscv,aclint-mswi"); - qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", - 2, addr, 2, RISCV_ACLINT_SWI_SIZE); - qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", - aclint_mswi_cells, aclint_cells_size); - qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(ms, name, socket); - g_free(name); - } - - if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { - addr =3D s->memmap[VIRT_CLINT].base + - (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); - size =3D RISCV_ACLINT_DEFAULT_MTIMER_SIZE; - } else { - addr =3D s->memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + - (s->memmap[VIRT_CLINT].size * socket); - size =3D s->memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; - } - name =3D g_strdup_printf("/soc/mtimer@%"HWADDR_PRIx, - addr + RISCV_ACLINT_DEFAULT_MTIME); - qemu_fdt_add_subnode(ms->fdt, name); - qemu_fdt_setprop_string(ms->fdt, name, "compatible", - "riscv,aclint-mtimer"); - qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", - 2, addr + RISCV_ACLINT_DEFAULT_MTIME, - 2, size - RISCV_ACLINT_DEFAULT_MTIME, - 2, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, - 2, RISCV_ACLINT_DEFAULT_MTIME); - qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", - aclint_mtimer_cells, aclint_cells_size); - riscv_socket_fdt_write_id(ms, name, socket); - g_free(name); - - if (s->aia_type !=3D VIRT_AIA_TYPE_APLIC_IMSIC) { - addr =3D s->memmap[VIRT_ACLINT_SSWI].base + - (s->memmap[VIRT_ACLINT_SSWI].size * socket); - - name =3D g_strdup_printf("/soc/sswi@%lx", addr); - qemu_fdt_add_subnode(ms->fdt, name); - qemu_fdt_setprop_string(ms->fdt, name, "compatible", - "riscv,aclint-sswi"); - qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", - 2, addr, 2, s->memmap[VIRT_ACLINT_SSWI].size); - qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", - aclint_sswi_cells, aclint_cells_size); - qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(ms, name, socket); - g_free(name); - } -} - static void create_fdt_socket_plic(RISCVVirtState *s, int socket, uint32_t *phandle, uint32_t *intc_phand= les, @@ -347,6 +259,7 @@ static void create_fdt_sockets(RISCVVirtState *s, bool numa_enabled =3D riscv_numa_enabled(ms); bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); APLICFdtProps aplic_props; + ACLINTFdtProps aclint_props; =20 riscv_fdt_create_cpu_socket_subnode(ms->fdt, kvm_enabled() ? kvm_riscv_get_timebase_frequency(&s->soc->harts[0]= ) : @@ -354,6 +267,13 @@ static void create_fdt_sockets(RISCVVirtState *s, =20 intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); =20 + if (virt_aclint_allowed() && s->have_aclint) { + aclint_props.clint =3D &s->memmap[VIRT_CLINT]; + aclint_props.aclint_sswi =3D &s->memmap[VIRT_ACLINT_SSWI]; + aclint_props.aia_type =3D s->aia_type; + aclint_props.numa_enabled =3D numa_enabled; + } + phandle_pos =3D ms->smp.cpus; for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { hwaddr memaddr =3D s->memmap[VIRT_DRAM].base + @@ -372,8 +292,10 @@ static void create_fdt_sockets(RISCVVirtState *s, socket, riscv_numa_enabled(ms)); =20 if (virt_aclint_allowed() && s->have_aclint) { - create_fdt_socket_aclint(s, socket, - &intc_phandles[phandle_pos]); + aclint_props.socket =3D socket; + aclint_props.num_harts =3D s->soc[socket].num_harts; + riscv_create_fdt_socket_aclint(ms->fdt, &aclint_props, + &intc_phandles[phandle_pos]); } else if (tcg_enabled()) { hwaddr clintaddr =3D s->memmap[VIRT_CLINT].base + s->memmap[VIRT_CLINT].size * socket; --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 03 Sep 2026 22:21:06 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Chao Liu Subject: [PULL 23/47] hw/riscv/fdt-common, virt.c: add riscv_create_fdt_uart() Date: Fri, 4 Sep 2026 15:19:19 +1000 Message-ID: <20260904051943.799041-24-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499447175158500 From: Daniel Henrique Barboza Add a common uart FDT helper to be used by 'virt' and the future 'riscv-server-ref' board. The 'tt-atlantis' board is left out of this patch because it's going through UART related changes and its FDT might change soon, thus it's better to wait for the final DT to be determined and then we can evaluate whether it can share a common helper. The "/chosen" and "/alias" changes are UART0 only so we're keeping them out of the common helper. The board can set both manually as appropriate. No FDT changes intended. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260828203918.350131-11-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/fdt-common.h | 5 +++++ hw/riscv/fdt-common.c | 29 +++++++++++++++++++++++++++++ hw/riscv/virt.c | 35 +++++++++-------------------------- 3 files changed, 43 insertions(+), 26 deletions(-) diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index a45b063f66..c8b25348bd 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -128,4 +128,9 @@ void riscv_create_fdt_socket_aplic(void *fdt, APLICFdtP= rops *props, uint32_t *aplic_phandles); void riscv_create_fdt_socket_aclint(void *fdt, ACLINTFdtProps *props, uint32_t *intc_phandles); +/* Caller must free the returned string. */ +char *riscv_fdt_get_uart_nodename(hwaddr addr); +void riscv_create_fdt_uart(void *fdt, const MemMapEntry *uart_mem, + int uart_irq, int aia_type, + uint32_t irq_phandle); #endif diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index d2ce93ad28..0107aadaad 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -22,6 +22,8 @@ #include "hw/pci/pcie_host.h" #include "hw/riscv/aia.h" =20 +#define UART_STD_CLOCK_FREQ 3686400 /* 3.6864 MHz */ + void *riscv_create_board_device_tree(const char *model, const char *compat= ible, int *fdt_size) { @@ -799,3 +801,30 @@ void riscv_create_fdt_socket_aclint(void *fdt, ACLINTF= dtProps *props, g_free(name); } } + +char *riscv_fdt_get_uart_nodename(hwaddr addr) +{ + return g_strdup_printf("/soc/serial@%"HWADDR_PRIx, addr); +} + +void riscv_create_fdt_uart(void *fdt, const MemMapEntry *uart_mem, + int uart_irq, int aia_type, + uint32_t irq_phandle) +{ + g_autofree char *name =3D riscv_fdt_get_uart_nodename(uart_mem->base); + + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 2, uart_mem->base, + 2, uart_mem->size); + + qemu_fdt_setprop_cell(fdt, name, "clock-frequency", UART_STD_CLOCK_FRE= Q); + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", irq_phandle); + + if (aia_type =3D=3D AIA_TYPE_NONE) { + qemu_fdt_setprop_cell(fdt, name, "interrupts", uart_irq); + } else { + qemu_fdt_setprop_cells(fdt, name, "interrupts", uart_irq, 0x4); + } +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c9b1a669a5..ae809ecb5f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -417,39 +417,22 @@ static void create_fdt_virtio(RISCVVirtState *s, uint= 32_t irq_virtio_phandle) } } =20 -static void create_fdt_uart(RISCVVirtState *s, - uint32_t irq_mmio_phandle, int memId, int irqN= o) +static void create_fdt_uarts(RISCVVirtState *s, uint32_t irq_mmio_phandle) { g_autofree char *name =3D NULL; MachineState *ms =3D MACHINE(s); =20 - name =3D g_strdup_printf("/soc/serial@%"HWADDR_PRIx, - s->memmap[memId].base); - qemu_fdt_add_subnode(ms->fdt, name); - qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); - qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", - 2, s->memmap[memId].base, - 2, s->memmap[memId].size); - qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phan= dle); - if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", irqNo); - } else { - qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", irqNo, 0x4); + if (s->uart1_present) { + riscv_create_fdt_uart(ms->fdt, &s->memmap[VIRT_UART1], + UART1_IRQ, s->aia_type, irq_mmio_phandle); } =20 - if (VIRT_UART0 =3D=3D memId) { - qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); - qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); - } -} + riscv_create_fdt_uart(ms->fdt, &s->memmap[VIRT_UART0], UART0_IRQ, + s->aia_type, irq_mmio_phandle); =20 -static void create_fdt_uarts(RISCVVirtState *s, uint32_t irq_mmio_phandle) -{ - if (s->uart1_present) { - create_fdt_uart(s, irq_mmio_phandle, VIRT_UART1, UART1_IRQ); - } - create_fdt_uart(s, irq_mmio_phandle, VIRT_UART0, UART0_IRQ); + name =3D riscv_fdt_get_uart_nodename(s->memmap[VIRT_UART0].base); + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); + qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); } =20 static void create_fdt_rtc(RISCVVirtState *s, --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499436; cv=none; d=zohomail.com; s=zohoarc; b=LpETAk7y9ZidnX9Arjfgdm28Q4yxbhBwlP11JDqT/ZnSodaFBcIV+p+iYHDs5jrf9mEZpsmpgpzJFBh3oaAJW4VWOu8d/IkaMFy3PkvWIIzniGimLX9ZTAXZ37vwOzcJug5ll+GUYFJ1vF5uEUgoAvYGs3b2nZA3l5TPvVwfExg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Thu, 03 Sep 2026 22:21:09 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Chao Liu Subject: [PULL 24/47] hw/riscv/fdt-common, virt.c: add riscv_create_fdt_rtc() Date: Fri, 4 Sep 2026 15:19:20 +1000 Message-ID: <20260904051943.799041-25-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499437022158500 From: Daniel Henrique Barboza The soon to be added 'riscv-server-ref' board will add a rtc FDT subnode that is similar to what the 'virt' board users. Put it into a helper to avoid copy/pasting code. No FDT changes intended. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260828203918.350131-12-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/fdt-common.h | 3 +++ hw/riscv/fdt-common.c | 21 +++++++++++++++++++++ hw/riscv/virt.c | 26 ++------------------------ 3 files changed, 26 insertions(+), 24 deletions(-) diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index c8b25348bd..eb9db8278d 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -133,4 +133,7 @@ char *riscv_fdt_get_uart_nodename(hwaddr addr); void riscv_create_fdt_uart(void *fdt, const MemMapEntry *uart_mem, int uart_irq, int aia_type, uint32_t irq_phandle); +void riscv_create_fdt_rtc(void *fdt, const MemMapEntry *rtc_mem, + int rtc_irq, int aia_type, + uint32_t irq_phandle); #endif diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index 0107aadaad..ce2dcb43b4 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -828,3 +828,24 @@ void riscv_create_fdt_uart(void *fdt, const MemMapEntr= y *uart_mem, qemu_fdt_setprop_cells(fdt, name, "interrupts", uart_irq, 0x4); } } + +void riscv_create_fdt_rtc(void *fdt, const MemMapEntry *rtc_mem, + int rtc_irq, int aia_type, + uint32_t irq_phandle) +{ + g_autofree char *name =3D NULL; + + name =3D g_strdup_printf("/soc/rtc@%"HWADDR_PRIx, + rtc_mem->base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"= ); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 2, rtc_mem->base, + 2, rtc_mem->size); + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", irq_phandle); + if (aia_type =3D=3D AIA_TYPE_NONE) { + qemu_fdt_setprop_cell(fdt, name, "interrupts", rtc_irq); + } else { + qemu_fdt_setprop_cells(fdt, name, "interrupts", rtc_irq, 0x4); + } +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ae809ecb5f..3a9d1e0a13 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -435,29 +435,6 @@ static void create_fdt_uarts(RISCVVirtState *s, uint32= _t irq_mmio_phandle) qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); } =20 -static void create_fdt_rtc(RISCVVirtState *s, - uint32_t irq_mmio_phandle) -{ - g_autofree char *name =3D NULL; - MachineState *ms =3D MACHINE(s); - - name =3D g_strdup_printf("/soc/rtc@%"HWADDR_PRIx, - s->memmap[VIRT_RTC].base); - qemu_fdt_add_subnode(ms->fdt, name); - qemu_fdt_setprop_string(ms->fdt, name, "compatible", - "google,goldfish-rtc"); - qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", - 2, s->memmap[VIRT_RTC].base, - 2, s->memmap[VIRT_RTC].size); - qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", - irq_mmio_phandle); - if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); - } else { - qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); - } -} - static void create_fdt_fw_cfg(RISCVVirtState *s) { MachineState *ms =3D MACHINE(s); @@ -565,7 +542,8 @@ static void finalize_fdt(RISCVVirtState *s) =20 create_fdt_uarts(s, irq_mmio_phandle); =20 - create_fdt_rtc(s, irq_mmio_phandle); + riscv_create_fdt_rtc(MACHINE(s)->fdt, &s->memmap[VIRT_RTC], RTC_IRQ, + s->aia_type, irq_mmio_phandle); } =20 static void create_fdt(RISCVVirtState *s) --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 03 Sep 2026 22:21:13 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Chao Liu Subject: [PULL 25/47] hw/riscv/device-common, virt.c: add riscv_create_platform_bus() Date: Fri, 4 Sep 2026 15:19:21 +1000 Message-ID: <20260904051943.799041-26-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=alistair23@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499330594158500 From: Daniel Henrique Barboza There will be code repetition instances added by the 'riscv-server-ref' board w.r.t device creation and initialization. Instead of waiting for that code to land we're adding helpers beforehand. The idea is to make the new board code shorter and more palatable for reviewers. A new 'device-common' file is created for such helpers. We'll start with the platform bus, a nice piece of software that only the 'virt' board uses so far, and the 'riscv-server-ref' will use to support TPM devices. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260828203918.350131-13-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/device-common.h | 19 +++++++++++++ hw/riscv/device-common.c | 48 ++++++++++++++++++++++++++++++++ hw/riscv/virt.c | 30 +++----------------- hw/riscv/meson.build | 1 + 4 files changed, 72 insertions(+), 26 deletions(-) create mode 100644 include/hw/riscv/device-common.h create mode 100644 hw/riscv/device-common.c diff --git a/include/hw/riscv/device-common.h b/include/hw/riscv/device-com= mon.h new file mode 100644 index 0000000000..12af031bbf --- /dev/null +++ b/include/hw/riscv/device-common.h @@ -0,0 +1,19 @@ +/* + * RISC-V board helpers for FDT generation. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef RISCV_DEVICE_COMMON_H +#define RISCV_DEVICE_COMMON_H + +#include "exec/hwaddr.h" +#include "hw/core/qdev.h" + +DeviceState *riscv_create_platform_bus(DeviceState *irqchip, + const MemMapEntry *platform_bus_mem, + int platform_bus_base_irq, + int platform_bus_num_irqs); +#endif diff --git a/hw/riscv/device-common.c b/hw/riscv/device-common.c new file mode 100644 index 0000000000..d3c68a9e71 --- /dev/null +++ b/hw/riscv/device-common.c @@ -0,0 +1,48 @@ +/* + * RISC-V board helpers for FDT generation. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "hw/riscv/device-common.h" + +#include "hw/core/platform-bus.h" +#include "hw/core/qdev.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/sysbus.h" +#include "qapi/error.h" +#include "system/address-spaces.h" +#include "system/memory.h" + + +DeviceState *riscv_create_platform_bus(DeviceState *irqchip, + const MemMapEntry *platform_bus_mem, + int platform_bus_base_irq, + int platform_bus_num_irqs) +{ + MemoryRegion *sysmem =3D get_system_memory(); + DeviceState *dev; + SysBusDevice *sysbus; + + dev =3D qdev_new(TYPE_PLATFORM_BUS_DEVICE); + dev->id =3D g_strdup(TYPE_PLATFORM_BUS_DEVICE); + qdev_prop_set_uint32(dev, "num_irqs", platform_bus_num_irqs); + qdev_prop_set_uint32(dev, "mmio_size", platform_bus_mem->size); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + sysbus =3D SYS_BUS_DEVICE(dev); + for (int i =3D 0; i < platform_bus_num_irqs; i++) { + int irq =3D platform_bus_base_irq + i; + sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); + } + + memory_region_add_subregion(sysmem, + platform_bus_mem->base, + sysbus_mmio_get_region(sysbus, 0)); + + return dev; +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 3a9d1e0a13..64f75646d0 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -35,6 +35,7 @@ #include "hw/riscv/riscv-iommu-bits.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" +#include "hw/riscv/device-common.h" #include "hw/riscv/fdt-common.h" #include "hw/riscv/numa.h" #include "kvm/kvm_riscv.h" @@ -682,31 +683,6 @@ static DeviceState *virt_create_plic(const MemMapEntry= *memmap, int socket, memmap[VIRT_PLIC].size); } =20 -static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) -{ - DeviceState *dev; - SysBusDevice *sysbus; - int i; - MemoryRegion *sysmem =3D get_system_memory(); - - dev =3D qdev_new(TYPE_PLATFORM_BUS_DEVICE); - dev->id =3D g_strdup(TYPE_PLATFORM_BUS_DEVICE); - qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); - qdev_prop_set_uint32(dev, "mmio_size", s->memmap[VIRT_PLATFORM_BUS].si= ze); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - s->platform_bus_dev =3D dev; - - sysbus =3D SYS_BUS_DEVICE(dev); - for (i =3D 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { - int irq =3D VIRT_PLATFORM_BUS_IRQ + i; - sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); - } - - memory_region_add_subregion(sysmem, - s->memmap[VIRT_PLATFORM_BUS].base, - sysbus_mmio_get_region(sysbus, 0)); -} - static void virt_build_smbios(RISCVVirtState *s) { MachineClass *mc =3D MACHINE_GET_CLASS(s); @@ -1029,7 +1005,9 @@ static void virt_machine_init(MachineState *machine) =20 gpex_pcie_init(system_memory, pcie_irqchip, s); =20 - create_platform_bus(s, mmio_irqchip); + s->platform_bus_dev =3D riscv_create_platform_bus(mmio_irqchip, + &s->memmap[VIRT_PLATFORM_BUS], VIRT_PLATFORM_BUS_IRQ, + VIRT_PLATFORM_BUS_NUM_IRQS); =20 serial_mm_init(system_memory, s->memmap[VIRT_UART0].base, 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 0d82ceacc4..7aa3c1578d 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -1,6 +1,7 @@ riscv_ss =3D ss.source_set() riscv_ss.add(files('aia.c')) riscv_ss.add(files('boot.c')) +riscv_ss.add(files('device-common.c')) riscv_ss.add(files('fdt-common.c')) riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) riscv_ss.add(files('riscv_hart.c')) --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 03 Sep 2026 22:21:16 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Chao Liu Subject: [PULL 26/47] hw/riscv/device-common, virt.c: add flash helpers Date: Fri, 4 Sep 2026 15:19:22 +1000 Message-ID: <20260904051943.799041-27-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=alistair23@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499358890158500 From: Daniel Henrique Barboza Move the flash device creating and flash map initialization to device-common.c. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260828203918.350131-14-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/device-common.h | 6 ++++ hw/riscv/device-common.c | 44 ++++++++++++++++++++++++ hw/riscv/virt.c | 57 +++++--------------------------- 3 files changed, 58 insertions(+), 49 deletions(-) diff --git a/include/hw/riscv/device-common.h b/include/hw/riscv/device-com= mon.h index 12af031bbf..9f8bc67a1d 100644 --- a/include/hw/riscv/device-common.h +++ b/include/hw/riscv/device-common.h @@ -10,10 +10,16 @@ #define RISCV_DEVICE_COMMON_H =20 #include "exec/hwaddr.h" +#include "hw/block/flash.h" #include "hw/core/qdev.h" =20 DeviceState *riscv_create_platform_bus(DeviceState *irqchip, const MemMapEntry *platform_bus_mem, int platform_bus_base_irq, int platform_bus_num_irqs); +PFlashCFI01 *riscv_flash_create(Object *parent, const char *name, + const char *alias_prop_name, + int flash_sector_size); +void riscv_init_flash_map(PFlashCFI01 *flash, hwaddr base, hwaddr size, + MemoryRegion *sysmem, int flash_sector_size); #endif diff --git a/hw/riscv/device-common.c b/hw/riscv/device-common.c index d3c68a9e71..a054cd7114 100644 --- a/hw/riscv/device-common.c +++ b/hw/riscv/device-common.c @@ -10,11 +10,13 @@ =20 #include "hw/riscv/device-common.h" =20 +#include "hw/block/flash.h" #include "hw/core/platform-bus.h" #include "hw/core/qdev.h" #include "hw/core/qdev-properties.h" #include "hw/core/sysbus.h" #include "qapi/error.h" +#include "qom/object.h" #include "system/address-spaces.h" #include "system/memory.h" =20 @@ -46,3 +48,45 @@ DeviceState *riscv_create_platform_bus(DeviceState *irqc= hip, =20 return dev; } + +PFlashCFI01 *riscv_flash_create(Object *parent, const char *name, + const char *alias_prop_name, + int flash_sector_size) +{ + /* + * Create a single flash device. We use the same parameters as + * the flash devices on the ARM virt board. + */ + DeviceState *dev =3D qdev_new(TYPE_PFLASH_CFI01); + + qdev_prop_set_uint64(dev, "sector-length", flash_sector_size); + qdev_prop_set_uint8(dev, "width", 4); + qdev_prop_set_uint8(dev, "device-width", 2); + qdev_prop_set_bit(dev, "big-endian", false); + qdev_prop_set_uint16(dev, "id0", 0x89); + qdev_prop_set_uint16(dev, "id1", 0x18); + qdev_prop_set_uint16(dev, "id2", 0x00); + qdev_prop_set_uint16(dev, "id3", 0x00); + qdev_prop_set_string(dev, "name", name); + + object_property_add_child(parent, name, OBJECT(dev)); + object_property_add_alias(parent, alias_prop_name, + OBJECT(dev), "drive"); + + return PFLASH_CFI01(dev); +} + +void riscv_init_flash_map(PFlashCFI01 *flash, hwaddr base, hwaddr size, + MemoryRegion *sysmem, int flash_sector_size) +{ + DeviceState *dev =3D DEVICE(flash); + + assert(QEMU_IS_ALIGNED(size, flash_sector_size)); + assert(size / flash_sector_size <=3D UINT32_MAX); + + qdev_prop_set_uint32(dev, "num-blocks", size / flash_sector_size); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + memory_region_add_subregion(sysmem, base, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)= ); +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 64f75646d0..255d5ca3b3 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -119,53 +119,12 @@ static MemMapEntry virt_high_pcie_memmap; =20 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) =20 -static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, - const char *name, - const char *alias_prop_name) -{ - /* - * Create a single flash device. We use the same parameters as - * the flash devices on the ARM virt board. - */ - DeviceState *dev =3D qdev_new(TYPE_PFLASH_CFI01); - - qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); - qdev_prop_set_uint8(dev, "width", 4); - qdev_prop_set_uint8(dev, "device-width", 2); - qdev_prop_set_bit(dev, "big-endian", false); - qdev_prop_set_uint16(dev, "id0", 0x89); - qdev_prop_set_uint16(dev, "id1", 0x18); - qdev_prop_set_uint16(dev, "id2", 0x00); - qdev_prop_set_uint16(dev, "id3", 0x00); - qdev_prop_set_string(dev, "name", name); - - object_property_add_child(OBJECT(s), name, OBJECT(dev)); - object_property_add_alias(OBJECT(s), alias_prop_name, - OBJECT(dev), "drive"); - - return PFLASH_CFI01(dev); -} - static void virt_flash_create(RISCVVirtState *s) { - s->flash[0] =3D virt_flash_create1(s, "virt.flash0", "pflash0"); - s->flash[1] =3D virt_flash_create1(s, "virt.flash1", "pflash1"); -} - -static void virt_flash_map1(PFlashCFI01 *flash, - hwaddr base, hwaddr size, - MemoryRegion *sysmem) -{ - DeviceState *dev =3D DEVICE(flash); - - assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); - assert(size / VIRT_FLASH_SECTOR_SIZE <=3D UINT32_MAX); - qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - - memory_region_add_subregion(sysmem, base, - sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), - 0)); + s->flash[0] =3D riscv_flash_create(OBJECT(s), "virt.flash0", "pflash0", + VIRT_FLASH_SECTOR_SIZE); + s->flash[1] =3D riscv_flash_create(OBJECT(s), "virt.flash1", "pflash1", + VIRT_FLASH_SECTOR_SIZE); } =20 static void virt_flash_map(RISCVVirtState *s, @@ -174,10 +133,10 @@ static void virt_flash_map(RISCVVirtState *s, hwaddr flashsize =3D s->memmap[VIRT_FLASH].size / 2; hwaddr flashbase =3D s->memmap[VIRT_FLASH].base; =20 - virt_flash_map1(s->flash[0], flashbase, flashsize, - sysmem); - virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, - sysmem); + riscv_init_flash_map(s->flash[0], flashbase, flashsize, + sysmem, VIRT_FLASH_SECTOR_SIZE); + riscv_init_flash_map(s->flash[1], flashbase + flashsize, flashsize, + sysmem, VIRT_FLASH_SECTOR_SIZE); } =20 static void create_fdt_socket_plic(RISCVVirtState *s, --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499400; cv=none; d=zohomail.com; s=zohoarc; b=kjMW9Yt3XKISgBavrhuzHYULYSpwXRt4T1yi3l0pd8CLsNt7jdh/oIiA+75rIf/Af6XiXNnQfxt7tDpW+Y0ogOf2i46dcaYQCzEySkN3aIXGbOp3xBhFkbB9bvl/E4pfK/N/KAcVHLa2CnSxEu9s+cHmNL8XIPn3trARpoUCAwE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788499400; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 03 Sep 2026 22:21:19 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Chao Liu Subject: [PULL 27/47] hw/riscv/device-common, virt.c: add riscv_gpex_pcie_init() Date: Fri, 4 Sep 2026 15:19:23 +1000 Message-ID: <20260904051943.799041-28-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499400936158500 From: Daniel Henrique Barboza The GPEX_HOST initialization in 'virt' can be moved to device-common.c and be re-used later for other boards, namely the future 'riscv-server-ref' emulation. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260828203918.350131-15-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/device-common.h | 7 +++ hw/riscv/device-common.c | 76 +++++++++++++++++++++++++++++++ hw/riscv/virt.c | 77 ++------------------------------ 3 files changed, 87 insertions(+), 73 deletions(-) diff --git a/include/hw/riscv/device-common.h b/include/hw/riscv/device-com= mon.h index 9f8bc67a1d..572912ec36 100644 --- a/include/hw/riscv/device-common.h +++ b/include/hw/riscv/device-common.h @@ -22,4 +22,11 @@ PFlashCFI01 *riscv_flash_create(Object *parent, const ch= ar *name, int flash_sector_size); void riscv_init_flash_map(PFlashCFI01 *flash, hwaddr base, hwaddr size, MemoryRegion *sysmem, int flash_sector_size); +DeviceState *riscv_gpex_pcie_init(MemoryRegion *sys_mem, + DeviceState *irqchip, + const MemMapEntry *pcie_ecam_mem, + const MemMapEntry *pcie_mmio_mem, + const MemMapEntry *high_pcie_mmio_mem, + const MemMapEntry *pcie_pio_mem, + int pcie_irq); #endif diff --git a/hw/riscv/device-common.c b/hw/riscv/device-common.c index a054cd7114..d1a6814f87 100644 --- a/hw/riscv/device-common.c +++ b/hw/riscv/device-common.c @@ -15,6 +15,8 @@ #include "hw/core/qdev.h" #include "hw/core/qdev-properties.h" #include "hw/core/sysbus.h" +#include "hw/pci/pci.h" +#include "hw/pci-host/gpex.h" #include "qapi/error.h" #include "qom/object.h" #include "system/address-spaces.h" @@ -90,3 +92,77 @@ void riscv_init_flash_map(PFlashCFI01 *flash, hwaddr bas= e, hwaddr size, memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)= ); } + +DeviceState *riscv_gpex_pcie_init(MemoryRegion *sys_mem, + DeviceState *irqchip, + const MemMapEntry *pcie_ecam_mem, + const MemMapEntry *pcie_mmio_mem, + const MemMapEntry *high_pcie_mmio_mem, + const MemMapEntry *pcie_pio_mem, + int pcie_irq) +{ + DeviceState *dev; + MemoryRegion *ecam_alias, *ecam_reg; + MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; + hwaddr ecam_base =3D pcie_ecam_mem->base; + hwaddr ecam_size =3D pcie_ecam_mem->size; + hwaddr mmio_base =3D pcie_mmio_mem->base; + hwaddr mmio_size =3D pcie_mmio_mem->size; + hwaddr high_mmio_base =3D high_pcie_mmio_mem->base; + hwaddr high_mmio_size =3D high_pcie_mmio_mem->size; + hwaddr pio_base =3D pcie_pio_mem->base; + hwaddr pio_size =3D pcie_pio_mem->size; + + dev =3D qdev_new(TYPE_GPEX_HOST); + + /* Set GPEX object properties for the virt machine */ + object_property_set_uint(OBJECT(dev), PCI_HOST_ECAM_BASE, + ecam_base, NULL); + object_property_set_int(OBJECT(dev), PCI_HOST_ECAM_SIZE, + ecam_size, NULL); + object_property_set_uint(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_BASE, + mmio_base, NULL); + object_property_set_int(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_SIZE, + mmio_size, NULL); + object_property_set_uint(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_BASE, + high_mmio_base, NULL); + object_property_set_int(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_SIZE, + high_mmio_size, NULL); + object_property_set_uint(OBJECT(dev), PCI_HOST_PIO_BASE, + pio_base, NULL); + object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, + pio_size, NULL); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + ecam_alias =3D g_new0(MemoryRegion, 1); + ecam_reg =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", + ecam_reg, 0, ecam_size); + memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias= ); + + mmio_alias =3D g_new0(MemoryRegion, 1); + mmio_reg =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", + mmio_reg, mmio_base, mmio_size); + memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias= ); + + /* Map high MMIO space */ + high_mmio_alias =3D g_new0(MemoryRegion, 1); + memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high= ", + mmio_reg, high_mmio_base, high_mmio_size); + memory_region_add_subregion(get_system_memory(), high_mmio_base, + high_mmio_alias); + + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); + + for (int i =3D 0; i < PCI_NUM_PINS; i++) { + qemu_irq irq =3D qdev_get_gpio_in(irqchip, pcie_irq + i); + + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); + gpex_set_irq_num(GPEX_HOST(dev), i, pcie_irq + i); + } + + GPEX_HOST(dev)->gpex_cfg.bus =3D PCI_HOST_BRIDGE(dev)->bus; + return dev; +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 255d5ca3b3..f725cb9110 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -539,78 +539,6 @@ static void create_fdt(RISCVVirtState *s) create_fdt_pmu(s); } =20 -static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, - DeviceState *irqchip, - RISCVVirtState *s) -{ - DeviceState *dev; - MemoryRegion *ecam_alias, *ecam_reg; - MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; - hwaddr ecam_base =3D s->memmap[VIRT_PCIE_ECAM].base; - hwaddr ecam_size =3D s->memmap[VIRT_PCIE_ECAM].size; - hwaddr mmio_base =3D s->memmap[VIRT_PCIE_MMIO].base; - hwaddr mmio_size =3D s->memmap[VIRT_PCIE_MMIO].size; - hwaddr high_mmio_base =3D virt_high_pcie_memmap.base; - hwaddr high_mmio_size =3D virt_high_pcie_memmap.size; - hwaddr pio_base =3D s->memmap[VIRT_PCIE_PIO].base; - hwaddr pio_size =3D s->memmap[VIRT_PCIE_PIO].size; - qemu_irq irq; - int i; - - dev =3D qdev_new(TYPE_GPEX_HOST); - - /* Set GPEX object properties for the virt machine */ - object_property_set_uint(OBJECT(dev), PCI_HOST_ECAM_BASE, - ecam_base, NULL); - object_property_set_int(OBJECT(dev), PCI_HOST_ECAM_SIZE, - ecam_size, NULL); - object_property_set_uint(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_BASE, - mmio_base, NULL); - object_property_set_int(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_SIZE, - mmio_size, NULL); - object_property_set_uint(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_BASE, - high_mmio_base, NULL); - object_property_set_int(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_SIZE, - high_mmio_size, NULL); - object_property_set_uint(OBJECT(dev), PCI_HOST_PIO_BASE, - pio_base, NULL); - object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, - pio_size, NULL); - - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - - ecam_alias =3D g_new0(MemoryRegion, 1); - ecam_reg =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); - memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", - ecam_reg, 0, ecam_size); - memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias= ); - - mmio_alias =3D g_new0(MemoryRegion, 1); - mmio_reg =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); - memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", - mmio_reg, mmio_base, mmio_size); - memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias= ); - - /* Map high MMIO space */ - high_mmio_alias =3D g_new0(MemoryRegion, 1); - memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high= ", - mmio_reg, high_mmio_base, high_mmio_size); - memory_region_add_subregion(get_system_memory(), high_mmio_base, - high_mmio_alias); - - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); - - for (i =3D 0; i < PCI_NUM_PINS; i++) { - irq =3D qdev_get_gpio_in(irqchip, PCIE_IRQ + i); - - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); - gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); - } - - GPEX_HOST(dev)->gpex_cfg.bus =3D PCI_HOST_BRIDGE(dev)->bus; - return dev; -} - static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) { FWCfgState *fw_cfg; @@ -962,7 +890,10 @@ static void virt_machine_init(MachineState *machine) qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); } =20 - gpex_pcie_init(system_memory, pcie_irqchip, s); + riscv_gpex_pcie_init(system_memory, pcie_irqchip, + &s->memmap[VIRT_PCIE_ECAM], &s->memmap[VIRT_PCIE_MMIO], + &virt_high_pcie_memmap, &s->memmap[VIRT_PCIE_PIO], + PCIE_IRQ); =20 s->platform_bus_dev =3D riscv_create_platform_bus(mmio_irqchip, &s->memmap[VIRT_PLATFORM_BUS], VIRT_PLATFORM_BUS_IRQ, --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 03 Sep 2026 22:21:22 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Chao Liu Subject: [PULL 28/47] hw/riscv/riscv-iommu-sys.c, virt.c: add riscv_create_iommu_sys() Date: Fri, 4 Sep 2026 15:19:24 +1000 Message-ID: <20260904051943.799041-29-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499391226158500 From: Daniel Henrique Barboza Move the creation of riscv-iommu-sys to its own file instead of open coding it in the 'virt' board. Other boards in the future might want to use this device and we want to avoid code duplication. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260828203918.350131-16-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.h | 3 +++ hw/riscv/riscv-iommu-sys.c | 25 +++++++++++++++++++++++++ hw/riscv/virt.c | 23 +++-------------------- 3 files changed, 31 insertions(+), 20 deletions(-) diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h index da70e8bfa8..7c470ba084 100644 --- a/hw/riscv/riscv-iommu.h +++ b/hw/riscv/riscv-iommu.h @@ -104,6 +104,9 @@ void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_= iommu_igs_mode mode); void riscv_iommu_reset(RISCVIOMMUState *s); void riscv_iommu_notify(RISCVIOMMUState *s, int vec_type); void riscv_iommu_fault(RISCVIOMMUState *s, struct riscv_iommu_fq_record *e= v); +DeviceState *riscv_create_iommu_sys(DeviceState *mmio_irqchip, + hwaddr addr, int base_irq, + bool is_32_bit); =20 typedef struct RISCVIOMMUContext RISCVIOMMUContext; /* Device translation context state. */ diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c index 3314adeed2..258c171efd 100644 --- a/hw/riscv/riscv-iommu-sys.c +++ b/hw/riscv/riscv-iommu-sys.c @@ -217,6 +217,31 @@ static void riscv_iommu_sys_init(Object *obj) riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_BOTH); } =20 +DeviceState *riscv_create_iommu_sys(DeviceState *mmio_irqchip, + hwaddr addr, int base_irq, + bool is_32_bit) +{ + DeviceState *iommu_sys =3D qdev_new(TYPE_RISCV_IOMMU_SYS); + + object_property_set_uint(OBJECT(iommu_sys), "addr", addr, &error_fatal= ); + object_property_set_uint(OBJECT(iommu_sys), "base-irq", + base_irq, &error_fatal); + object_property_set_link(OBJECT(iommu_sys), "irqchip", + OBJECT(mmio_irqchip), + &error_fatal); + /* + * For riscv64 use a physical address size of 56 bits (44 bit PPN), + * and for riscv32 use 34 bits (22 bit PPN). + */ + object_property_set_uint(OBJECT(iommu_sys), "pas-bits", + is_32_bit ? 34 : 56, + &error_fatal); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal); + + return iommu_sys; +} + static const Property riscv_iommu_sys_properties[] =3D { DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0), DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0), diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f725cb9110..a72f1a6e4c 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -32,6 +32,7 @@ #include "hw/core/sysbus-fdt.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/iommu.h" +#include "hw/riscv/riscv-iommu.h" #include "hw/riscv/riscv-iommu-bits.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" @@ -932,26 +933,8 @@ static void virt_machine_init(MachineState *machine) } =20 if (virt_is_iommu_sys_enabled(s)) { - DeviceState *iommu_sys =3D qdev_new(TYPE_RISCV_IOMMU_SYS); - - object_property_set_uint(OBJECT(iommu_sys), "addr", - s->memmap[VIRT_IOMMU_SYS].base, - &error_fatal); - object_property_set_uint(OBJECT(iommu_sys), "base-irq", - IOMMU_SYS_IRQ, - &error_fatal); - object_property_set_link(OBJECT(iommu_sys), "irqchip", - OBJECT(mmio_irqchip), - &error_fatal); - /* - * For riscv64 use a physical address size of 56 bits (44 bit PPN), - * and for riscv32 use 34 bits (22 bit PPN). - */ - object_property_set_uint(OBJECT(iommu_sys), "pas-bits", - riscv_is_32bit(&s->soc[0]) ? 34 : 56, - &error_fatal); - - sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal); + riscv_create_iommu_sys(mmio_irqchip, s->memmap[VIRT_IOMMU_SYS].bas= e, + IOMMU_SYS_IRQ, riscv_is_32bit(&s->soc[0])); } =20 s->machine_done.notify =3D virt_machine_done; --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499374; cv=none; d=zohomail.com; s=zohoarc; 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Thu, 03 Sep 2026 22:21:25 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: TANG Tiancheng , Alistair Francis Subject: [PULL 29/47] target/riscv/tcg: fix user option hash table leaks Date: Fri, 4 Sep 2026 15:19:25 +1000 Message-ID: <20260904051943.799041-30-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=alistair23@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499376942158500 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng The misa_ext_user_opts and multi_ext_user_opts hash tables are global, but riscv_tcg_cpu_instance_init() recreates both for every CPU instance. Creating a second CPU overwrites the only references to the first CPU's tables. LeakSanitizer reports two direct and four indirect leaks, 320 bytes in total, when a two-hart virt machine exits. The option state belongs to a CPU instance, like user_options. Move both tables into RISCVCPU, pass the CPU to their access helpers, and free them from the existing instance finalizer. Keep the implied-rule tables global because those are initialized once and shared. Fixes: 549cbf789ef8 ("target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig") Fixes: 21915d16c6fb ("target/riscv/tcg: add MISA user options hash") Signed-off-by: TANG Tiancheng Reviewed-by: Alistair Francis Message-ID: <20260831-b4-riscv-cpu-user-option-leak-v1-1-6b020c8b6964@linux= .alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 2 ++ target/riscv/tcg/tcg-cpu.c | 54 ++++++++++++++++++-------------------- 3 files changed, 30 insertions(+), 28 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b974c2f4b4..c2138dbd4b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -582,6 +582,8 @@ struct ArchCPU { /* Mapping of events to counters */ GHashTable *pmu_event_ctr_map; GHashTable *user_options; + GHashTable *misa_ext_user_opts; + GHashTable *multi_ext_user_opts; const GPtrArray *decoders; }; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a760ba3a52..652311ddef 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3279,6 +3279,8 @@ static void riscv_cpu_instance_finalize(Object *obj) g_clear_pointer(&cpu->pmu_event_ctr_map, g_hash_table_destroy); #endif g_clear_pointer(&cpu->user_options, g_hash_table_destroy); + g_clear_pointer(&cpu->misa_ext_user_opts, g_hash_table_destroy); + g_clear_pointer(&cpu->multi_ext_user_opts, g_hash_table_destroy); } =20 static const TypeInfo riscv_cpu_type_infos[] =3D { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 54f1b66216..b68160af83 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -41,34 +41,32 @@ #include "target/riscv/tcg/csr.h" #endif =20 -/* Hash that stores user set extensions */ -static GHashTable *multi_ext_user_opts; -static GHashTable *misa_ext_user_opts; - static GHashTable *multi_ext_implied_rules; static GHashTable *misa_ext_implied_rules; =20 -static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) +static bool cpu_cfg_ext_is_user_set(RISCVCPU *cpu, uint32_t ext_offset) { - return g_hash_table_contains(multi_ext_user_opts, + return g_hash_table_contains(cpu->multi_ext_user_opts, GUINT_TO_POINTER(ext_offset)); } =20 -static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) +static bool cpu_misa_ext_is_user_set(RISCVCPU *cpu, uint32_t misa_bit) { - return g_hash_table_contains(misa_ext_user_opts, + return g_hash_table_contains(cpu->misa_ext_user_opts, GUINT_TO_POINTER(misa_bit)); } =20 -static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) +static void cpu_cfg_ext_add_user_opt(RISCVCPU *cpu, uint32_t ext_offset, + bool value) { - g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), + g_hash_table_insert(cpu->multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset), (gpointer)value); } =20 -static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) +static void cpu_misa_ext_add_user_opt(RISCVCPU *cpu, uint32_t bit, bool va= lue) { - g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), + g_hash_table_insert(cpu->misa_ext_user_opts, GUINT_TO_POINTER(bit), (gpointer)value); } =20 @@ -358,7 +356,7 @@ static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint= 32_t ext_offset, return; } =20 - if (cpu_cfg_ext_is_user_set(ext_offset)) { + if (cpu_cfg_ext_is_user_set(cpu, ext_offset)) { return; } =20 @@ -491,7 +489,7 @@ static void riscv_cpu_validate_g(RISCVCPU *cpu) { const char *warn_msg =3D "RVG mandates disabled extension %s"; uint32_t g_misa_bits[] =3D {RVI, RVM, RVA, RVF, RVD}; - bool send_warn =3D cpu_misa_ext_is_user_set(RVG); + bool send_warn =3D cpu_misa_ext_is_user_set(cpu, RVG); =20 for (int i =3D 0; i < ARRAY_SIZE(g_misa_bits); i++) { uint32_t bit =3D g_misa_bits[i]; @@ -734,7 +732,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) } =20 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { + if (cpu_cfg_ext_is_user_set(cpu, CPU_CFG_OFFSET(ext_zicntr))) { error_setg(errp, "zicntr requires zicsr"); return; } @@ -742,7 +740,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) } =20 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { + if (cpu_cfg_ext_is_user_set(cpu, CPU_CFG_OFFSET(ext_zihpm))) { error_setg(errp, "zihpm requires zicsr"); return; } @@ -802,8 +800,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) =20 if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) && (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) { - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_smctr)) || - cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ssctr))) { + if (cpu_cfg_ext_is_user_set(cpu, CPU_CFG_OFFSET(ext_smctr)) || + cpu_cfg_ext_is_user_set(cpu, CPU_CFG_OFFSET(ext_ssctr))) { error_setg(errp, "Smctr and Ssctr require S-mode and Sscsrind"= ); return; } @@ -820,7 +818,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) #ifndef CONFIG_USER_ONLY if (cpu->cfg.ext_svpbmt && cpu->cfg.max_satp_mode < VM_1_10_SV39) { cpu->cfg.ext_svpbmt =3D false; - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_svpbmt))) { + if (cpu_cfg_ext_is_user_set(cpu, CPU_CFG_OFFSET(ext_svpbmt))) { warn_report("svpbmt requires at least satp sv39, " "current satp mode: %s", satp_mode_str(cpu->cfg.max_satp_mode, @@ -830,7 +828,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) =20 if (cpu->cfg.ext_svnapot && cpu->cfg.max_satp_mode < VM_1_10_SV39) { cpu->cfg.ext_svnapot =3D false; - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_svnapot))) { + if (cpu_cfg_ext_is_user_set(cpu, CPU_CFG_OFFSET(ext_svnapot))) { warn_report("svnapot requires at least satp sv39, " "current satp mode: %s", satp_mode_str(cpu->cfg.max_satp_mode, @@ -1007,7 +1005,7 @@ static void cpu_enable_implied_rule(RISCVCPU *cpu, * If the user disabled the misa_bit do not re-enable = it * and do not apply any implied rules related to it. */ - if (cpu_misa_ext_is_user_set(misa_bits[i]) && + if (cpu_misa_ext_is_user_set(cpu, misa_bits[i]) && !(env->misa_ext & misa_bits[i])) { continue; } @@ -1143,7 +1141,7 @@ static void riscv_cpu_update_misa_c(RISCVCPU *cpu) } =20 if (set_misa_c) { - if (cpu_misa_ext_is_user_set(RVC)) { + if (cpu_misa_ext_is_user_set(cpu, RVC)) { warn_report("RVC mandated by Zca/Zcf/Zcd extensions"); return; } @@ -1285,7 +1283,7 @@ static void riscv_cpu_set_profile(RISCVCPU *cpu, continue; } =20 - cpu_misa_ext_add_user_opt(bit, profile->enabled); + cpu_misa_ext_add_user_opt(cpu, bit, profile->enabled); riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); } =20 @@ -1296,7 +1294,7 @@ static void riscv_cpu_set_profile(RISCVCPU *cpu, cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); } =20 - cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); + cpu_cfg_ext_add_user_opt(cpu, ext_offset, profile->enabled); isa_ext_update_enabled(cpu, ext_offset, profile->enabled); } } @@ -1356,7 +1354,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor= *v, const char *name, return; } =20 - cpu_misa_ext_add_user_opt(misa_bit, value); + cpu_misa_ext_add_user_opt(cpu, misa_bit, value); =20 prev_val =3D env->misa_ext & misa_bit; =20 @@ -1520,7 +1518,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visito= r *v, const char *name, return; } =20 - cpu_cfg_ext_add_user_opt(cfg_offset, value); + cpu_cfg_ext_add_user_opt(cpu, cfg_offset, value); =20 prev_val =3D isa_ext_is_enabled(cpu, cfg_offset); =20 @@ -1684,8 +1682,8 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs) "riscv.cpu.rnmi", RNMI_MAX); #endif =20 - misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); - multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); + cpu->misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); + cpu->multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); =20 if (!misa_ext_implied_rules) { misa_ext_implied_rules =3D g_hash_table_new(NULL, g_direct_equal); --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 03 Sep 2026 22:21:28 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Zephyr Li , Chao Liu , Max Chou , Alistair Francis Subject: [PULL 30/47] target/riscv: preserve vl on element-zero fault Date: Fri, 4 Sep 2026 15:19:26 +1000 Message-ID: <20260904051943.799041-31-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499475213158500 Content-Type: text/plain; charset="utf-8" From: Zephyr Li A unit-stride fault-only-first load must leave vl unchanged when element zero raises a synchronous exception. The current implementation updates vl after probing the accesses but before performing the actual loads. For unassigned MMIO, the probe can succeed even though the subsequent device transaction raises an exception. If this happens for element zero, the trap handler observes a prematurely shortened vl. Keep the shortened value in a local bound until all loads complete, and only then update the architectural vl. Add a bare-metal RVV regression test using an unassigned MMIO address and check that vl remains unchanged in the trap handler. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3544 Reviewed-by: Chao Liu Reviewed-by: Max Chou Signed-off-by: Zephyr Li Acked-by: Alistair Francis Message-ID: <20260813025959.583-1-fritchleybohrer@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/vector_helper.c | 23 +++++---- tests/tcg/riscv64/Makefile.softmmu-target | 5 ++ tests/tcg/riscv64/test-vle32ff.S | 58 +++++++++++++++++++++++ 3 files changed, 77 insertions(+), 9 deletions(-) create mode 100644 tests/tcg/riscv64/test-vle32ff.S diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_hel= per.c index e28d8a3d9f..0d1e4e0964 100644 --- a/target/riscv/tcg/vector_helper.c +++ b/target/riscv/tcg/vector_helper.c @@ -721,7 +721,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, CPURIS= CVState *env, uint32_t desc, vext_ldst_elem_fn_tlb *ldst_tlb, vext_ldst_elem_fn_host *ldst_host, uint32_t log2_esz, uintptr_t = ra) { - uint32_t i, k, vl =3D 0; + uint32_t i, k, vl =3D 0, load_vl; uint32_t nf =3D vext_nf(desc); uint32_t vm =3D vext_vm(desc); uint32_t max_elems =3D vext_max_elems(desc, log2_esz); @@ -787,22 +787,24 @@ vext_ldff(void *vd, void *v0, target_ulong base, CPUR= ISCVState *env, } } ProbeSuccess: - /* load bytes from guest memory */ - if (vl !=3D 0) { - env->vl =3D vl; - } + /* + * Keep a shortened vl local until all loads complete. In particular, + * an exception from element zero must leave the architectural vl alon= e. + */ + load_vl =3D vl ? vl : env->vl; =20 - if (env->vstart < env->vl) { + if (env->vstart < load_vl) { if (vm) { /* Load/store elements in the first page */ if (likely(elems)) { + elems =3D MIN(elems, load_vl - env->vstart); vext_page_ldst_us(env, vd, addr, elems, nf, max_elems, log2_esz, true, mmu_index, ldst_tlb, ldst_host, ra); } =20 /* Load/store elements in the second page */ - if (unlikely(env->vstart < env->vl)) { + if (unlikely(env->vstart < load_vl)) { /* Cross page element */ if (unlikely(page_split % msize)) { for (k =3D 0; k < nf; k++) { @@ -815,7 +817,7 @@ ProbeSuccess: =20 addr =3D base + ((env->vstart * nf) << log2_esz); /* Get number of elements of second page */ - elems =3D env->vl - env->vstart; + elems =3D load_vl - env->vstart; =20 /* Load/store elements in the second page */ vext_page_ldst_us(env, vd, addr, elems, nf, max_elems, @@ -823,7 +825,7 @@ ProbeSuccess: ldst_host, ra); } } else { - for (i =3D env->vstart; i < env->vl; i++) { + for (i =3D env->vstart; i < load_vl; i++) { k =3D 0; while (k < nf) { if (!vext_elem_mask(v0, i)) { @@ -841,6 +843,9 @@ ProbeSuccess: } } } + if (vl !=3D 0) { + env->vl =3D vl; + } env->vstart =3D 0; =20 vext_set_tail_elems_1s(env->vl, vd, desc, nf, esz, max_elems); diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/= Makefile.softmmu-target index 575571de90..f2c75abd57 100644 --- a/tests/tcg/riscv64/Makefile.softmmu-target +++ b/tests/tcg/riscv64/Makefile.softmmu-target @@ -80,5 +80,10 @@ EXTRA_RUNS +=3D run-test-rv128-sstatus run-test-rv128-sstatus: test-rv128-sstatus $(call run-test, $<, $(QEMU) -cpu x-rv128 $(QEMU_OPTS)$<) =20 +EXTRA_RUNS +=3D run-test-vle32ff +run-test-vle32ff: test-vle32ff + $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=3Dtrue $(QEMU_OPTS)$<) +test-vle32ff: CFLAGS +=3D -march=3Drv64gcv + # We don't currently support the multiarch system tests undefine MULTIARCH_TESTS diff --git a/tests/tcg/riscv64/test-vle32ff.S b/tests/tcg/riscv64/test-vle3= 2ff.S new file mode 100644 index 0000000000..2cffe8659c --- /dev/null +++ b/tests/tcg/riscv64/test-vle32ff.S @@ -0,0 +1,58 @@ +/* + * Verify that a fault-only-first load keeps vl unchanged when element zero + * raises a synchronous exception. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + + .option norvc + + .text + .globl _start +_start: + lla t0, trap + csrw mtvec, t0 + + li t0, (1 << 9) /* Set mstatus.VS to Initial. */ + csrs mstatus, t0 + li t1, 4 + vsetvli t2, t1, e32, m1, ta, ma + /* Unassigned MMIO: probe succeeds, load faults. */ + li t0, 0x18000000 + vle32ff.v v1, (t0) + + /* Element zero did not trap. */ + li a0, 1 + j _exit + +trap: + csrr t0, mcause + li t1, 5 /* Load access fault. */ + bne t0, t1, trap_fail + + csrr t0, vl + bne t0, t2, trap_fail + + li a0, 0 + j _exit + +trap_fail: + li a0, 1 + +_exit: + lla a1, semiargs + li t0, 0x20026 /* ADP_Stopped_ApplicationExit */ + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 /* TARGET_SYS_EXIT_EXTENDED */ + + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + .data + .balign 8 +semiargs: + .space 16 --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 03 Sep 2026 22:21:31 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Abhigyan Kumar <314abh@gmail.com>, Alistair Francis Subject: [PULL 31/47] target/riscv: prevent abrupt abortion on unassigned value write to tdata Date: Fri, 4 Sep 2026 15:19:27 +1000 Message-ID: <20260904051943.799041-32-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499334615158500 Content-Type: text/plain; charset="utf-8" From: Abhigyan Kumar <314abh@gmail.com> tdata_csr_write is approachable by guest programs. In case of unassigned values written to a tdata CSR in debug mode, the switch-case falls through straight to default causing an immediate abort. The risc-v spec says: All tdata registers follow write-any-read-legal semantics. If a debugger writes an unsupported configuration, the register will read back a value that is supported (which may simply be a disabled trigger). This means that a debugger must always read back values it writes to tdata registers, unless it already knows what is supported. This fix correctly ensures that the WARL behaviour of tdata CSRs. Fixes: a42bd001 ("target/riscv: debug: Determine the trigger type from tdata1.type") Signed-off-by: Abhigyan Kumar <314abh@gmail.com> Reviewed-by: Alistair Francis Message-ID: <20260729230028.1797355-1-314abh@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/debug.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c index 148201f3cb..e4d719a1da 100644 --- a/target/riscv/tcg/debug.c +++ b/target/riscv/tcg/debug.c @@ -951,7 +951,8 @@ void tdata_csr_write(CPURISCVState *env, int tdata_inde= x, target_ulong val) trigger_type); break; default: - g_assert_not_reached(); + qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d is unassigned\n", + trigger_type); } } =20 --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 03 Sep 2026 22:21:34 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Chao Liu Subject: [PULL 32/47] hw/riscv/aia: Take a MemoryRegion for the created devices Date: Fri, 4 Sep 2026 15:19:28 +1000 Message-ID: <20260904051943.799041-33-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=alistair23@gmail.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499314628158500 From: Joel Stanley Add a MemoryRegion parameter to riscv_create_aia(), to be passed on to the IMSIC and APLIC helpers so a SoC can have the controllers mapped into its own memory container. Both callers pass system_memory, so there is no change in behaviour. As the controllers don't yet take a MemoryRegion the parameter is not yet passed on. Changing riscv_create_aia first avoids churn in the intermediate commits. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley Reviewed-by: Chao Liu Message-ID: <20260903055131.257903-2-joel@jms.id.au> Signed-off-by: Alistair Francis --- hw/riscv/aia.h | 3 ++- hw/riscv/aia.c | 3 ++- hw/riscv/tt_atlantis.c | 3 ++- hw/riscv/virt.c | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/riscv/aia.h b/hw/riscv/aia.h index 3b6d7f9625..5df3292610 100644 --- a/hw/riscv/aia.h +++ b/hw/riscv/aia.h @@ -13,7 +13,8 @@ =20 uint32_t imsic_num_bits(uint32_t count); =20 -DeviceState *riscv_create_aia(bool msimode, int aia_guests, +DeviceState *riscv_create_aia(MemoryRegion *container, + bool msimode, int aia_guests, uint32_t m_imsic_stride, uint32_t s_imsic_stride, uint16_t num_sources, diff --git a/hw/riscv/aia.c b/hw/riscv/aia.c index c1a5982856..e11382e512 100644 --- a/hw/riscv/aia.c +++ b/hw/riscv/aia.c @@ -24,7 +24,8 @@ uint32_t imsic_num_bits(uint32_t count) return ret; } =20 -DeviceState *riscv_create_aia(bool msimode, int aia_guests, +DeviceState *riscv_create_aia(MemoryRegion *container, + bool msimode, int aia_guests, uint32_t m_imsic_stride, uint32_t s_imsic_stride, uint16_t num_sources, diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index db8a1805d7..e40aacbb6c 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -497,7 +497,8 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); =20 - s->irqchip =3D riscv_create_aia(true, TT_IMSIC_GUESTS, + s->irqchip =3D riscv_create_aia(system_memory, + true, TT_IMSIC_GUESTS, TT_IMSIC_STRIDE, TT_IMSIC_STRIDE, TT_IRQCHIP_NUM_SOURCES, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a72f1a6e4c..def46c1ec6 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -808,8 +808,9 @@ static void virt_machine_init(MachineState *machine) s->irqchip[i] =3D virt_create_plic(s->memmap, i, base_hartid, hart_count); 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Thu, 03 Sep 2026 22:21:37 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 33/47] hw/intc/riscv_aclint: Take a MemoryRegion for the created devices Date: Fri, 4 Sep 2026 15:19:29 +1000 Message-ID: <20260904051943.799041-34-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=alistair23@gmail.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499477296158500 From: Joel Stanley The riscv_aclint_mtimer_create() and riscv_aclint_swi_create() helpers map the device they create into system_memory, which prevents their use by SoCs that map devices into a memory container of their own. Add a MemoryRegion parameter and map the device into it instead of calling sysbus_mmio_map(). All callers pass system_memory, so there is no change in behaviour. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-3-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/intc/riscv_aclint.h | 7 ++++--- hw/intc/riscv_aclint.c | 12 ++++++++---- hw/riscv/cps.c | 6 ++++-- hw/riscv/k230.c | 6 ++++-- hw/riscv/microchip_pfsoc.c | 5 +++-- hw/riscv/shakti_c.c | 7 ++++--- hw/riscv/sifive_e.c | 4 ++-- hw/riscv/sifive_u.c | 7 ++++--- hw/riscv/spike.c | 4 ++-- hw/riscv/tt_atlantis.c | 3 ++- hw/riscv/virt.c | 17 +++++++++++------ hw/riscv/xiangshan_kmh.c | 6 ++++-- 12 files changed, 52 insertions(+), 32 deletions(-) diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h index 0e0b98acb0..71d1b551a1 100644 --- a/include/hw/intc/riscv_aclint.h +++ b/include/hw/intc/riscv_aclint.h @@ -46,7 +46,8 @@ typedef struct RISCVAclintMTimerState { qemu_irq *timer_irqs; } RISCVAclintMTimerState; =20 -DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, +DeviceState *riscv_aclint_mtimer_create(MemoryRegion *container, + hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq, bool provide_rdtime); @@ -68,8 +69,8 @@ typedef struct RISCVAclintSwiState { qemu_irq *soft_irqs; } RISCVAclintSwiState; =20 -DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base, - uint32_t num_harts, bool sswi); +DeviceState *riscv_aclint_swi_create(MemoryRegion *container, + hwaddr addr, uint32_t hartid_base, uint32_t num_harts, bool sswi); =20 enum { RISCV_ACLINT_DEFAULT_MTIMECMP =3D 0x0, diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 361a8d1bcb..2d133d0dcf 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -371,7 +371,8 @@ static const TypeInfo riscv_aclint_mtimer_info =3D { /* * Create ACLINT MTIMER device. */ -DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, +DeviceState *riscv_aclint_mtimer_create(MemoryRegion *container, + hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq, bool provide_rdtime) @@ -392,7 +393,8 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hw= addr size, qdev_prop_set_uint32(dev, "aperture-size", size); qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(container, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); @@ -556,7 +558,8 @@ static const TypeInfo riscv_aclint_swi_info =3D { /* * Create ACLINT [M|S]SWI device. */ -DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base, +DeviceState *riscv_aclint_swi_create(MemoryRegion *container, + hwaddr addr, uint32_t hartid_base, uint32_t num_harts, bool sswi) { int i; @@ -569,7 +572,8 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint3= 2_t hartid_base, qdev_prop_set_uint32(dev, "num-harts", num_harts); qdev_prop_set_uint32(dev, "sswi", sswi ? true : false); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(container, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); diff --git a/hw/riscv/cps.c b/hw/riscv/cps.c index 86172be5b3..5cfb54aa27 100644 --- a/hw/riscv/cps.c +++ b/hw/riscv/cps.c @@ -151,9 +151,11 @@ static void riscv_cps_realize(DeviceState *dev, Error = **errp) false, false, s->aplic); /* PLIC changes msi_nonbroken to ture. We revert the change. */ msi_nonbroken =3D false; - riscv_aclint_swi_create(cm_base + AIA_CLINT_OFFSET, + riscv_aclint_swi_create(get_system_memory(), + cm_base + AIA_CLINT_OFFSET, hartid_base, MAX_HARTS, false); - riscv_aclint_mtimer_create(cm_base + AIA_CLINT_OFFSET + + riscv_aclint_mtimer_create(get_system_memory(), + cm_base + AIA_CLINT_OFFSET + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, hartid_base, diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c index 34905bb170..309619dabf 100644 --- a/hw/riscv/k230.c +++ b/hw/riscv/k230.c @@ -195,9 +195,11 @@ static void k230_soc_realize(DeviceState *dev, Error *= *errp) s->c908_plic =3D k230_create_plic(C908_CPU_HARTID, c908_cpus); =20 /* CLINT */ - riscv_aclint_swi_create(memmap[K230_DEV_CLINT].base, + riscv_aclint_swi_create(sys_mem, + memmap[K230_DEV_CLINT].base, C908_CPU_HARTID, c908_cpus, false); - riscv_aclint_mtimer_create(memmap[K230_DEV_CLINT].base + 0x4000, + riscv_aclint_mtimer_create(sys_mem, + memmap[K230_DEV_CLINT].base + 0x4000, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, C908_CPU_HARTID, c908_cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 60bb96da01..d34d8182b1 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -249,9 +249,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *d= ev, Error **errp) memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); =20 /* CLINT */ - riscv_aclint_swi_create(memmap[MICROCHIP_PFSOC_CLINT].base, + riscv_aclint_swi_create(system_memory, + memmap[MICROCHIP_PFSOC_CLINT].base, 0, ms->smp.cpus, false); - riscv_aclint_mtimer_create( + riscv_aclint_mtimer_create(system_memory, memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index a205a21332..4f99d78327 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -125,10 +125,11 @@ static void shakti_c_soc_state_realize(DeviceState *d= ev, Error **errp) SHAKTI_C_PLIC_CONTEXT_STRIDE, shakti_c_memmap[SHAKTI_C_PLIC].size); =20 - riscv_aclint_swi_create(shakti_c_memmap[SHAKTI_C_CLINT].base, + riscv_aclint_swi_create(system_memory, + shakti_c_memmap[SHAKTI_C_CLINT].base, 0, 1, false); - riscv_aclint_mtimer_create(shakti_c_memmap[SHAKTI_C_CLINT].base + - RISCV_ACLINT_SWI_SIZE, + riscv_aclint_mtimer_create(system_memory, + shakti_c_memmap[SHAKTI_C_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, 1, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 1acfea4966..fa77f28152 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -223,9 +223,9 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) SIFIVE_E_PLIC_CONTEXT_BASE, SIFIVE_E_PLIC_CONTEXT_STRIDE, memmap[SIFIVE_E_DEV_PLIC].size); - riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base, + riscv_aclint_swi_create(sys_mem, memmap[SIFIVE_E_DEV_CLINT].base, 0, ms->smp.cpus, false); - riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base + + riscv_aclint_mtimer_create(sys_mem, memmap[SIFIVE_E_DEV_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index a40f82e7a5..0f0370b8c5 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -788,10 +788,11 @@ static void sifive_u_soc_realize(DeviceState *dev, Er= ror **errp) serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ= )); sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ= )); - riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0, + riscv_aclint_swi_create(system_memory, + memmap[SIFIVE_U_DEV_CLINT].base, 0, ms->smp.cpus, false); - riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base + - RISCV_ACLINT_SWI_SIZE, + riscv_aclint_mtimer_create(system_memory, + memmap[SIFIVE_U_DEV_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, CLINT_TIMEBASE_FREQ, false); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 5fd4109d29..63cf77e1de 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -166,10 +166,10 @@ static void spike_board_init(MachineState *machine) sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); =20 /* Core Local Interruptor (timer and IPI) for each socket */ - riscv_aclint_swi_create( + riscv_aclint_swi_create(system_memory, memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, base_hartid, hart_count, false); - riscv_aclint_mtimer_create( + riscv_aclint_mtimer_create(system_memory, memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index e40aacbb6c..8b07218152 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -510,7 +510,8 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) TT_IRQCHIP_NUM_MSIS, TT_IRQCHIP_NUM_PRIO_BITS); =20 - riscv_aclint_mtimer_create(s->memmap[TT_ATL_ACLINT].base, + riscv_aclint_mtimer_create(system_memory, + s->memmap[TT_ATL_ACLINT].base, TT_ACLINT_MTIME_SIZE, 0, hart_count, TT_ACLINT_MTIMECMP, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index def46c1ec6..186d266b29 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -767,7 +767,8 @@ static void virt_machine_init(MachineState *machine) if (virt_aclint_allowed() && s->have_aclint) { if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { /* Per-socket ACLINT MTIMER */ - riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + + riscv_aclint_mtimer_create(system_memory, + s->memmap[VIRT_CLINT].base + i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, @@ -776,10 +777,12 @@ static void virt_machine_init(MachineState *machine) RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); } else { /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ - riscv_aclint_swi_create(s->memmap[VIRT_CLINT].base + + riscv_aclint_swi_create(system_memory, + s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size, base_hartid, hart_count, false); - riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + + riscv_aclint_mtimer_create(system_memory, + s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, @@ -787,16 +790,18 @@ static void virt_machine_init(MachineState *machine) RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); - riscv_aclint_swi_create(s->memmap[VIRT_ACLINT_SSWI].base + + riscv_aclint_swi_create(system_memory, + s->memmap[VIRT_ACLINT_SSWI].base + i * s->memmap[VIRT_ACLINT_SSWI].size, base_hartid, hart_count, true); } } else if (tcg_enabled()) { /* Per-socket SiFive CLINT */ - riscv_aclint_swi_create( + riscv_aclint_swi_create(system_memory, s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT]= .size, base_hartid, hart_count, false); - riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + + riscv_aclint_mtimer_create(system_memory, + s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_co= unt, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MT= IME, diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index 247a0b5d1f..7ebe422dfc 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -115,9 +115,11 @@ static void xiangshan_kmh_soc_realize(DeviceState *dev= , Error **errp) 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); =20 /* CLINT */ - riscv_aclint_swi_create(memmap[XIANGSHAN_KMH_CLINT].base, + riscv_aclint_swi_create(system_memory, + memmap[XIANGSHAN_KMH_CLINT].base, 0, num_harts, false); - riscv_aclint_mtimer_create(memmap[XIANGSHAN_KMH_CLINT].base + + riscv_aclint_mtimer_create(system_memory, + memmap[XIANGSHAN_KMH_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, num_harts, RISCV_ACLINT_DEFAULT_MTIMECMP, --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 03 Sep 2026 22:21:41 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 34/47] hw/intc/riscv_imsic: Take a MemoryRegion for the created device Date: Fri, 4 Sep 2026 15:19:30 +1000 Message-ID: <20260904051943.799041-35-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=alistair23@gmail.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499487200158500 From: Joel Stanley riscv_imsic_create() maps the device it creates into system_memory, which prevents its use by SoCs that map devices into their own memory container. Add a MemoryRegion parameter and map the device into it instead of calling sysbus_mmio_map(). All callers pass system_memory, so there is no change in behaviour. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-4-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/intc/riscv_imsic.h | 3 ++- hw/intc/riscv_imsic.c | 6 ++++-- hw/riscv/aia.c | 6 ++++-- hw/riscv/xiangshan_kmh.c | 5 +++-- 4 files changed, 13 insertions(+), 7 deletions(-) diff --git a/include/hw/intc/riscv_imsic.h b/include/hw/intc/riscv_imsic.h index fae999731d..0a1df1c2f8 100644 --- a/include/hw/intc/riscv_imsic.h +++ b/include/hw/intc/riscv_imsic.h @@ -62,7 +62,8 @@ struct RISCVIMSICState { uint32_t num_irqs; }; =20 -DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, +DeviceState *riscv_imsic_create(MemoryRegion *container, hwaddr addr, + uint32_t hartid, bool mmode, uint32_t num_pages, uint32_t num_ids); =20 #endif diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index d6b46cdca2..cb9ce9612c 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -495,7 +495,8 @@ type_init(riscv_imsic_register_types) /* * Create IMSIC device. */ -DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, +DeviceState *riscv_imsic_create(MemoryRegion *container, hwaddr addr, + uint32_t hartid, bool mmode, uint32_t num_pages, uint32_t num_ids) { DeviceState *dev =3D qdev_new(TYPE_RISCV_IMSIC); @@ -518,7 +519,8 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t h= artid, bool mmode, qdev_prop_set_uint32(dev, "num-irqs", num_ids + 1); =20 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(container, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 if (!kvm_irqchip_in_kernel()) { for (i =3D 0; i < num_pages; i++) { diff --git a/hw/riscv/aia.c b/hw/riscv/aia.c index e11382e512..eae7638f97 100644 --- a/hw/riscv/aia.c +++ b/hw/riscv/aia.c @@ -53,7 +53,8 @@ DeviceState *riscv_create_aia(MemoryRegion *container, /* Per-socket M-level IMSICs */ addr =3D imsic_m->base + socket * (1U << IMSIC_MMIO_GROUP_MIN_= SHIFT); for (i =3D 0; i < hart_count; i++) { - riscv_imsic_create(addr + i * m_imsic_stride, + riscv_imsic_create(container, + addr + i * m_imsic_stride, base_hartid + i, true, 1, num_msis); } @@ -62,7 +63,8 @@ DeviceState *riscv_create_aia(MemoryRegion *container, /* Per-socket S-level IMSICs */ addr =3D imsic_s->base + socket * (1U << IMSIC_MMIO_GROUP_MIN_SHIF= T); for (i =3D 0; i < hart_count; i++) { - riscv_imsic_create(addr + i * s_imsic_stride, + riscv_imsic_create(container, + addr + i * s_imsic_stride, base_hartid + i, false, 1 + aia_guests, num_msis); } diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index 7ebe422dfc..bb9b1e05ef 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -64,14 +64,15 @@ static DeviceState *xiangshan_kmh_create_aia(uint32_t n= um_harts) /* M-level IMSICs */ addr =3D memmap[XIANGSHAN_KMH_IMSIC_M].base; for (i =3D 0; i < num_harts; i++) { - riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), i, true, + riscv_imsic_create(get_system_memory(), + addr + i * IMSIC_HART_SIZE(0), i, true, 1, XIANGSHAN_KMH_IMSIC_NUM_IDS); } =20 /* S-level IMSICs */ addr =3D memmap[XIANGSHAN_KMH_IMSIC_S].base; for (i =3D 0; i < num_harts; i++) { - riscv_imsic_create(addr + + riscv_imsic_create(get_system_memory(), addr + i * IMSIC_HART_SIZE(XIANGSHAN_KMH_IMSIC_GUEST_B= ITS), i, false, 1 + XIANGSHAN_KMH_IMSIC_GUEST_BITS, XIANGSHAN_KMH_IMSIC_NUM_IDS); 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Thu, 03 Sep 2026 22:21:44 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 35/47] hw/intc/riscv_aplic: Take a MemoryRegion for the created device Date: Fri, 4 Sep 2026 15:19:31 +1000 Message-ID: <20260904051943.799041-36-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=alistair23@gmail.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499368783158500 From: Joel Stanley riscv_aplic_create() maps the device it creates into system_memory, which prevents its use by SoCs that map devices into their own memory container. Add a MemoryRegion parameter and map the device into it instead of calling sysbus_mmio_map(). The mapping still only happens when the APLIC is emulated. All callers pass system_memory, so there is no change in behaviour. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-5-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/intc/riscv_aplic.h | 7 ++++--- hw/intc/riscv_aplic.c | 10 ++++++---- hw/riscv/aia.c | 8 ++++---- hw/riscv/cps.c | 6 ++++-- hw/riscv/xiangshan_kmh.c | 6 ++++-- 5 files changed, 22 insertions(+), 15 deletions(-) diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h index c7a4d4ad01..62d2b33ade 100644 --- a/include/hw/intc/riscv_aplic.h +++ b/include/hw/intc/riscv_aplic.h @@ -80,8 +80,9 @@ bool riscv_is_kvm_aia_aplic_imsic(bool msimode); bool riscv_use_emulated_aplic(bool msimode); void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr); =20 -DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, - uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, - uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent); +DeviceState *riscv_aplic_create(MemoryRegion *container, + hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, + uint32_t num_sources, uint32_t iprio_bits, bool msimode, bool mmode, + DeviceState *parent); =20 #endif diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 84606e9f3d..d8e25bfda1 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -1109,9 +1109,10 @@ void riscv_aplic_add_child(DeviceState *parent, Devi= ceState *child) /* * Create APLIC device. */ -DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, - uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, - uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent) +DeviceState *riscv_aplic_create(MemoryRegion *container, + hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, + uint32_t num_sources, uint32_t iprio_bits, bool msimode, bool mmode, + DeviceState *parent) { DeviceState *dev =3D qdev_new(TYPE_RISCV_APLIC); uint32_t i; @@ -1137,7 +1138,8 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr s= ize, sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 if (riscv_use_emulated_aplic(msimode)) { - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(container, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 if (!msimode) { for (i =3D 0; i < num_harts; i++) { diff --git a/hw/riscv/aia.c b/hw/riscv/aia.c index eae7638f97..56fc064533 100644 --- a/hw/riscv/aia.c +++ b/hw/riscv/aia.c @@ -72,8 +72,8 @@ DeviceState *riscv_create_aia(MemoryRegion *container, =20 if (!kvm_enabled()) { /* Per-socket M-level APLIC */ - aplic_m_dev =3D riscv_aplic_create(aplic_m->base + - socket * aplic_m->size, + aplic_m_dev =3D riscv_aplic_create(container, + aplic_m->base + socket * aplic_m->siz= e, aplic_m->size, (msimode) ? 0 : base_hartid, (msimode) ? 0 : hart_count, @@ -83,8 +83,8 @@ DeviceState *riscv_create_aia(MemoryRegion *container, } =20 /* Per-socket S-level APLIC */ - aplic_s_dev =3D riscv_aplic_create(aplic_s->base + - socket * aplic_s->size, + aplic_s_dev =3D riscv_aplic_create(container, + aplic_s->base + socket * aplic_s->size, aplic_s->size, (msimode) ? 0 : base_hartid, (msimode) ? 0 : hart_count, diff --git a/hw/riscv/cps.c b/hw/riscv/cps.c index 5cfb54aa27..d2fd9638a0 100644 --- a/hw/riscv/cps.c +++ b/hw/riscv/cps.c @@ -135,14 +135,16 @@ static void riscv_cps_realize(DeviceState *dev, Error= **errp) for (i =3D 0; i < num_of_clusters; i++) { uint64_t cm_base =3D GLOBAL_CM_BASE + (CM_SIZE * i); uint32_t hartid_base =3D i << MHARTID_CLUSTER_SHIFT; - s->aplic =3D riscv_aplic_create(cm_base + AIA_PLIC_M_OFFSET, + s->aplic =3D riscv_aplic_create(get_system_memory(), + cm_base + AIA_PLIC_M_OFFSET, AIA_PLIC_M_SIZE, hartid_base, /* hartid_base */ MAX_HARTS, /* num_harts */ APLIC_NUM_SOURCES, APLIC_NUM_PRIO_BITS, false, true, NULL); - riscv_aplic_create(cm_base + AIA_PLIC_S_OFFSET, + riscv_aplic_create(get_system_memory(), + cm_base + AIA_PLIC_S_OFFSET, AIA_PLIC_S_SIZE, hartid_base, /* hartid_base */ MAX_HARTS, /* num_harts */ diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index bb9b1e05ef..a234c5f352 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -79,13 +79,15 @@ static DeviceState *xiangshan_kmh_create_aia(uint32_t n= um_harts) } =20 /* M-level APLIC */ - aplic_m =3D riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_M].base, + aplic_m =3D riscv_aplic_create(get_system_memory(), + memmap[XIANGSHAN_KMH_APLIC_M].base, memmap[XIANGSHAN_KMH_APLIC_M].size, 0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES, 1, true, true, NULL); =20 /* S-level APLIC */ - riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_S].base, + riscv_aplic_create(get_system_memory(), + memmap[XIANGSHAN_KMH_APLIC_S].base, memmap[XIANGSHAN_KMH_APLIC_S].size, 0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES, 1, true, false, aplic_m); --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499371; cv=none; d=zohomail.com; s=zohoarc; b=AcbpTzT4iGg7O5FEP9MKvBr/wWsdAYd1TbwTRqPtVJkHC/ZpA/bikZf+g3mU8eP3clUgIacJ8wSkrrKEE2tMjTZD7s0giBYkCMzMdfWrpOWquiXTg3XNjvKx82aIVD9F3Z5bDL/e9tHzAP7lO7D5ZOSaeanf5vcQgswrGG61UW8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788499371; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 03 Sep 2026 22:21:48 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Daniel Henrique Barboza , Alistair Francis , Chao Liu Subject: [PULL 36/47] hw/intc/sifive_plic: Take a MemoryRegion for the created device Date: Fri, 4 Sep 2026 15:19:32 +1000 Message-ID: <20260904051943.799041-37-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=alistair23@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499372775158500 From: Joel Stanley sifive_plic_create() maps the device it creates into system_memory, which prevents its use by SoCs that map devices into their own memory container. Add a MemoryRegion parameter and map the device into it instead of calling sysbus_mmio_map(). All callers pass system_memory, so there is no change in behaviour. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley Reviewed-by: Chao Liu Message-ID: <20260903055131.257903-6-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/intc/sifive_plic.h | 4 ++-- hw/intc/sifive_plic.c | 7 ++++--- hw/riscv/k230.c | 3 ++- hw/riscv/microchip_pfsoc.c | 3 ++- hw/riscv/shakti_c.c | 3 ++- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 3 ++- hw/riscv/virt.c | 1 + 8 files changed, 16 insertions(+), 10 deletions(-) diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h index 32973dbf28..064754c3f6 100644 --- a/include/hw/intc/sifive_plic.h +++ b/include/hw/intc/sifive_plic.h @@ -76,8 +76,8 @@ struct SiFivePLICState { qemu_irq *s_external_irqs; }; =20 -DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, - uint32_t num_harts, +DeviceState *sifive_plic_create(MemoryRegion *container, + hwaddr addr, char *hart_config, uint32_t num_harts, uint32_t hartid_base, uint32_t num_sources, uint32_t num_priorities, uint32_t priority_base, uint32_t pending_base, uint32_t enable_base, diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 9c84ff06a9..90f17e6ee7 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -473,8 +473,8 @@ type_init(sifive_plic_register_types) /* * Create PLIC device. */ -DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, - uint32_t num_harts, +DeviceState *sifive_plic_create(MemoryRegion *container, + hwaddr addr, char *hart_config, uint32_t num_harts, uint32_t hartid_base, uint32_t num_sources, uint32_t num_priorities, uint32_t priority_base, uint32_t pending_base, uint32_t enable_base, @@ -499,7 +499,8 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart= _config, qdev_prop_set_uint32(dev, "context-stride", context_stride); qdev_prop_set_uint32(dev, "aperture-size", aperture_size); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(container, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 plic =3D SIFIVE_PLIC(dev); =20 diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c index 309619dabf..1e4ca38579 100644 --- a/hw/riscv/k230.c +++ b/hw/riscv/k230.c @@ -133,7 +133,8 @@ static DeviceState *k230_create_plic(int base_hartid, i= nt hartid_count) plic_hart_config =3D riscv_plic_hart_config_string(hartid_count); =20 /* Per-socket PLIC */ - return sifive_plic_create(memmap[K230_DEV_PLIC].base, + return sifive_plic_create(get_system_memory(), + memmap[K230_DEV_PLIC].base, plic_hart_config, hartid_count, base_hartid, K230_PLIC_NUM_SOURCES, K230_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index d34d8182b1..edd29626fa 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -281,7 +281,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *de= v, Error **errp) plic_hart_config =3D riscv_plic_hart_config_string(ms->smp.cpus); =20 /* PLIC */ - s->plic =3D sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, + s->plic =3D sifive_plic_create(system_memory, + memmap[MICROCHIP_PFSOC_PLIC].base, plic_hart_config, ms->smp.cpus, 0, MICROCHIP_PFSOC_PLIC_NUM_SOURCES, MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 4f99d78327..3b6efd25be 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -113,7 +113,8 @@ static void shakti_c_soc_state_realize(DeviceState *dev= , Error **errp) =20 sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort); =20 - sss->plic =3D sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base, + sss->plic =3D sifive_plic_create(system_memory, + shakti_c_memmap[SHAKTI_C_PLIC].base, (char *)SHAKTI_C_PLIC_HART_CONFIG, ms->smp.cpus, 0, SHAKTI_C_PLIC_NUM_SOURCES, SHAKTI_C_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index fa77f28152..35ed7f42a4 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -212,7 +212,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom); =20 /* MMIO */ - s->plic =3D sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, + s->plic =3D sifive_plic_create(sys_mem, memmap[SIFIVE_E_DEV_PLIC].base, (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0, SIFIVE_E_PLIC_NUM_SOURCES, SIFIVE_E_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 0f0370b8c5..b7d5e7b4da 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -772,7 +772,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) plic_hart_config =3D riscv_plic_hart_config_string(ms->smp.cpus); =20 /* MMIO */ - s->plic =3D sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, + s->plic =3D sifive_plic_create(system_memory, + memmap[SIFIVE_U_DEV_PLIC].base, plic_hart_config, ms->smp.cpus, 0, SIFIVE_U_PLIC_NUM_SOURCES, SIFIVE_U_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 186d266b29..f3a1cc5ba3 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -560,6 +560,7 @@ static DeviceState *virt_create_plic(const MemMapEntry = *memmap, int socket, =20 /* Per-socket PLIC */ return sifive_plic_create( + get_system_memory(), memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, plic_hart_config, hart_count, base_hartid, VIRT_IRQCHIP_NUM_SOURCES, --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 03 Sep 2026 22:21:51 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 37/47] hw/riscv/cps: Map interrupt controllers in SoC container Date: Fri, 4 Sep 2026 15:19:33 +1000 Message-ID: <20260904051943.799041-38-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=alistair23@gmail.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499354667158500 From: Joel Stanley The CPS device maps some devices into a container region, but the ACLINT and APLIC were mapped directly to system_memory. Pass the container memory region to the interrupt controller helpers so all CPS devices live in the container. The location of devices in memory for the boston-aia machine is unchanged. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-7-joel@jms.id.au> Signed-off-by: Alistair Francis --- hw/riscv/cps.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/cps.c b/hw/riscv/cps.c index d2fd9638a0..21daaf4943 100644 --- a/hw/riscv/cps.c +++ b/hw/riscv/cps.c @@ -135,7 +135,7 @@ static void riscv_cps_realize(DeviceState *dev, Error *= *errp) for (i =3D 0; i < num_of_clusters; i++) { uint64_t cm_base =3D GLOBAL_CM_BASE + (CM_SIZE * i); uint32_t hartid_base =3D i << MHARTID_CLUSTER_SHIFT; - s->aplic =3D riscv_aplic_create(get_system_memory(), + s->aplic =3D riscv_aplic_create(&s->container, cm_base + AIA_PLIC_M_OFFSET, AIA_PLIC_M_SIZE, hartid_base, /* hartid_base */ @@ -143,7 +143,7 @@ static void riscv_cps_realize(DeviceState *dev, Error *= *errp) APLIC_NUM_SOURCES, APLIC_NUM_PRIO_BITS, false, true, NULL); - riscv_aplic_create(get_system_memory(), + riscv_aplic_create(&s->container, cm_base + AIA_PLIC_S_OFFSET, AIA_PLIC_S_SIZE, hartid_base, /* hartid_base */ @@ -153,10 +153,10 @@ static void riscv_cps_realize(DeviceState *dev, Error= **errp) false, false, s->aplic); /* PLIC changes msi_nonbroken to ture. We revert the change. */ msi_nonbroken =3D false; - riscv_aclint_swi_create(get_system_memory(), + riscv_aclint_swi_create(&s->container, cm_base + AIA_CLINT_OFFSET, hartid_base, MAX_HARTS, false); - riscv_aclint_mtimer_create(get_system_memory(), + riscv_aclint_mtimer_create(&s->container, cm_base + AIA_CLINT_OFFSET + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499439; cv=none; d=zohomail.com; s=zohoarc; b=k+Zt1PsHbDxuTNzDGoraBS01s0ZFzJvGRX7NbcYT8fYKQ4SkKuENGS8XBe6hQ3hmxqeLfXQuECfrxpwNcguDwfmxWjEs6k7cuk12Og4d4DImZTRW+QozQGOF1IsnRQejZFEbKWx8y2dr5b+LbvINanS48rRsITvk3dPPtpDz0wc= ARC-Message-Signature: i=1; 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Thu, 03 Sep 2026 22:21:55 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 38/47] hw/riscv/atlantis: Make UART unimp region a SoC device Date: Fri, 4 Sep 2026 15:19:34 +1000 Message-ID: <20260904051943.799041-39-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=alistair23@gmail.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499441028158500 From: Joel Stanley Make the unimplemented region covering the remainder of the console UART's register space a SoC child device, mapped using a helper. This makes it easier to map it into the SoC's memory container along with the other devices in the future. While here, rename the region from uart0 to uart1. The uart0 name was a leftover from an earlier revision that used a different device for the console. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-8-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/riscv/tt_atlantis.h | 2 ++ hw/riscv/tt_atlantis.c | 19 ++++++++++++++++--- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 7f7d4a5a59..c9308aa570 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -13,6 +13,7 @@ #include "hw/core/sysbus.h" #include "hw/i2c/designware_i2c.h" #include "hw/intc/riscv_imsic.h" +#include "hw/misc/unimp.h" #include "hw/riscv/riscv_hart.h" =20 #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") @@ -31,6 +32,7 @@ struct TTAtlantisState { RISCVHartArrayState soc; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; + UnimplementedDeviceState uart1; =20 int fdt_size; }; diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 8b07218152..6e1e50aaf6 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -410,6 +410,17 @@ static void load_fdt(TTAtlantisState *s) create_fdt_memory(s); } =20 +static void mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, + const char *name, hwaddr addr, uint64_t= size) +{ + qdev_prop_set_string(DEVICE(dev), "name", name); + qdev_prop_set_uint64(DEVICE(dev), "size", size); + sysbus_realize(dev, &error_abort); + + memory_region_add_subregion_overlap(memory, addr, + sysbus_mmio_get_region(dev, 0), -1= 000); +} + static void tt_atlantis_machine_done(Notifier *notifier, void *data) { TTAtlantisState *s =3D container_of(notifier, TTAtlantisState, machine= _done); @@ -561,9 +572,11 @@ static void tt_atlantis_machine_init(MachineState *mac= hine) * Create an unimplemented device region so writes don't fault * and reads return zero, which keeps Linux happy. */ - create_unimplemented_device("tt-atlantis.uart0", - s->memmap[TT_ATL_UART1].base, - s->memmap[TT_ATL_UART1].size); + object_initialize_child(OBJECT(s), "uart1", &s->uart1, + TYPE_UNIMPLEMENTED_DEVICE); + mmio_map_unimplemented(system_memory, SYS_BUS_DEVICE(&s->uart1), + "tt-atlantis.uart1", s->memmap[TT_ATL_UART1].ba= se, + s->memmap[TT_ATL_UART1].size); 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Thu, 03 Sep 2026 22:21:58 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 39/47] hw/riscv/atlantis: Remove unused fdt_size Date: Fri, 4 Sep 2026 15:19:35 +1000 Message-ID: <20260904051943.799041-40-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499483216158500 Content-Type: text/plain; charset="utf-8" From: Joel Stanley The machine state carries around the FDT size which isn't used by anything. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-9-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/riscv/tt_atlantis.h | 2 -- hw/riscv/tt_atlantis.c | 9 +++++---- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index c9308aa570..d0cca3b024 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -33,8 +33,6 @@ struct TTAtlantisState { DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; - - int fdt_size; }; =20 enum { diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 6e1e50aaf6..c682bb6848 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -366,10 +366,10 @@ static void finalize_fdt(TTAtlantisState *s) static void create_fdt(TTAtlantisState *s) { MachineState *ms =3D MACHINE(s); + int fdt_size =3D 0; =20 - ms->fdt =3D riscv_create_board_device_tree( - "Tenstorrent Atlantis RISC-V Machine", - "tenstorrent,atlantis", &s->fdt_size); + ms->fdt =3D riscv_create_board_device_tree("Tenstorrent Atlantis RISC-= V Machine", + "tenstorrent,atlantis", &fdt_= size); =20 qemu_fdt_add_subnode(ms->fdt, "/chosen"); =20 @@ -385,8 +385,9 @@ static void load_fdt(TTAtlantisState *s) MachineState *ms =3D MACHINE(s); char **node_path; Error *err =3D NULL; + int fdt_size =3D 0; =20 - ms->fdt =3D load_device_tree(ms->dtb, &s->fdt_size); + ms->fdt =3D load_device_tree(ms->dtb, &fdt_size); if (!ms->fdt) { error_report("load_device_tree() failed"); exit(1); --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499451; cv=none; d=zohomail.com; s=zohoarc; b=EoOva2RZE+I/+bjpcZR6i3TbFTxopqiN9DaJ/QK/SvFk4LYWrlJHfkEHcxLV3Qjud503yZqxyMwJ+v4x/rryWcC+PQBG/gvpGm1O0AJ6cyubCiD7OoVsGIGmTdparQHQCyUNjcl2i2Ced1kKqSOckDsaoaEATqRKiRDftoGZrf8= ARC-Message-Signature: i=1; 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Thu, 03 Sep 2026 22:22:01 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 40/47] hw/riscv/atlantis: Rename hart array 'soc' to 'cpus' Date: Fri, 4 Sep 2026 15:19:36 +1000 Message-ID: <20260904051943.799041-41-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499453097158500 From: Joel Stanley The RISCVHartArrayState member is named soc, but it's an array of cpus, not the entire SoC. Use cpus instead as an accurate description of the hart array. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-10-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/riscv/tt_atlantis.h | 2 +- hw/riscv/tt_atlantis.c | 34 +++++++++++++++++----------------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index d0cca3b024..642490d217 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -29,7 +29,7 @@ struct TTAtlantisState { Notifier machine_done; const MemMapEntry *memmap; =20 - RISCVHartArrayState soc; + RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index c682bb6848..62e902f930 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -112,13 +112,13 @@ static void create_fdt_aclint(TTAtlantisState *s, uin= t32_t *intc_phandles) uint32_t aclint_cells_size; hwaddr addr; =20 - aclint_mtimer_cells =3D g_new0(uint32_t, s->soc.num_harts * 2); + aclint_mtimer_cells =3D g_new0(uint32_t, s->cpus.num_harts * 2); =20 - for (int cpu =3D 0; cpu < s->soc.num_harts; cpu++) { + for (int cpu =3D 0; cpu < s->cpus.num_harts; cpu++) { aclint_mtimer_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu= ]); aclint_mtimer_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_TIMER); } - aclint_cells_size =3D s->soc.num_harts * sizeof(uint32_t) * 2; + aclint_cells_size =3D s->cpus.num_harts * sizeof(uint32_t) * 2; =20 addr =3D s->memmap[TT_ATL_ACLINT].base; =20 @@ -210,7 +210,7 @@ static void create_fdt_pmu(TTAtlantisState *s) { char pmu_name[] =3D "/pmu"; void *fdt =3D MACHINE(s)->fdt; - RISCVCPU *hart =3D &s->soc.harts[0]; + RISCVCPU *hart =3D &s->cpus.harts[0]; =20 qemu_fdt_add_subnode(fdt, pmu_name); qemu_fdt_setprop_string(fdt, pmu_name, "compatible", "riscv,pmu"); @@ -227,8 +227,8 @@ static void create_fdt_cpu(TTAtlantisState *s, const Me= mMapEntry *memmap, =20 riscv_fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); =20 - riscv_create_fdt_socket_cpus(fdt, s->soc.harts, 0, s->soc.num_harts, - s->soc.hartid_base, &fdt_phandle, + riscv_create_fdt_socket_cpus(fdt, s->cpus.harts, 0, s->cpus.num_harts, + s->cpus.hartid_base, &fdt_phandle, intc_phandles, false, false); =20 create_fdt_memory(s); @@ -252,13 +252,13 @@ static void create_fdt_cpu(TTAtlantisState *s, const = MemMapEntry *memmap, create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_MAPLIC], msi_m_phandle, intc_phandles, aplic_m_phandle, aplic_s_phandle, - IRQ_M_EXT, s->soc.num_harts); + IRQ_M_EXT, s->cpus.num_harts); =20 /* S-level APLIC node */ create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_SAPLIC], imsic_s_phandle, intc_phandles, aplic_s_phandle, 0, - IRQ_S_EXT, s->soc.num_harts); + IRQ_S_EXT, s->cpus.num_harts); } =20 static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, @@ -429,7 +429,7 @@ static void tt_atlantis_machine_done(Notifier *notifier= , void *data) hwaddr start_addr =3D s->memmap[TT_ATL_DDR_LO].base; hwaddr mem_size; target_ulong firmware_end_addr, kernel_start_addr; - const char *firmware_name =3D riscv_default_firmware_name(&s->soc); + const char *firmware_name =3D riscv_default_firmware_name(&s->cpus); uint64_t fdt_load_addr; uint64_t kernel_entry; RISCVBootInfo boot_info; @@ -446,7 +446,7 @@ static void tt_atlantis_machine_done(Notifier *notifier= , void *data) if (mem_size > s->memmap[TT_ATL_DDR_LO].size) { mem_size =3D s->memmap[TT_ATL_DDR_LO].size; } - riscv_boot_info_init_discontig_mem(&boot_info, &s->soc, + riscv_boot_info_init_discontig_mem(&boot_info, &s->cpus, s->memmap[TT_ATL_DDR_LO].base, mem_size); =20 @@ -476,7 +476,7 @@ static void tt_atlantis_machine_done(Notifier *notifier= , void *data) riscv_load_fdt(fdt_load_addr, machine->fdt); =20 /* load the reset vector */ - riscv_setup_rom_reset_vec(machine, &s->soc, start_addr, + riscv_setup_rom_reset_vec(machine, &s->cpus, start_addr, s->memmap[TT_ATL_BOOTROM].base, s->memmap[TT_ATL_BOOTROM].size, kernel_entry, @@ -496,18 +496,18 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) =20 s->memmap =3D tt_atlantis_memmap; =20 - object_initialize_child(OBJECT(machine), "soc", &s->soc, + object_initialize_child(OBJECT(machine), "soc", &s->cpus, TYPE_RISCV_HART_ARRAY); - object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, + object_property_set_str(OBJECT(&s->cpus), "cpu-type", machine->cpu_typ= e, &error_abort); - object_property_set_int(OBJECT(&s->soc), "hartid-base", 0, + object_property_set_int(OBJECT(&s->cpus), "hartid-base", 0, &error_abort); - object_property_set_int(OBJECT(&s->soc), "num-harts", hart_count, + object_property_set_int(OBJECT(&s->cpus), "num-harts", hart_count, &error_abort); - object_property_set_int(OBJECT(&s->soc), "resetvec", + object_property_set_int(OBJECT(&s->cpus), "resetvec", s->memmap[TT_ATL_BOOTROM].base, &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); =20 s->irqchip =3D riscv_create_aia(system_memory, true, TT_IMSIC_GUESTS, --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 03 Sep 2026 22:22:04 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 41/47] hw/riscv/atlantis: Rework device tree creation Date: Fri, 4 Sep 2026 15:19:37 +1000 Message-ID: <20260904051943.799041-42-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=alistair23@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499332621158500 From: Joel Stanley Remove the direct use of MachineState from the device tree creation to allow separation between the SoC (TTAtlantisState) and the QEMU MachineState. Fix this for the device tree pointer by passing it directly to the functions that use it, instead of casting the TTAtlantisState to a MachineState. MachineState::smp.cpus is replaced with TTAtlantisState::cpus.num_harts, as these are equivalent after tt_atlantis_machine_init. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-11-joel@jms.id.au> Signed-off-by: Alistair Francis --- hw/riscv/tt_atlantis.c | 51 +++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 62e902f930..940f982e6b 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -79,9 +79,8 @@ static uint32_t next_phandle(void) return fdt_phandle++; } =20 -static void create_fdt_memory(TTAtlantisState *s) +static void create_fdt_memory(void *fdt, TTAtlantisState *s) { - void *fdt =3D MACHINE(s)->fdt; hwaddr size_lo =3D MACHINE(s)->ram_size; hwaddr size_hi =3D 0; =20 @@ -104,9 +103,9 @@ static void create_fdt_memory(TTAtlantisState *s) } } =20 -static void create_fdt_aclint(TTAtlantisState *s, uint32_t *intc_phandles) +static void create_fdt_aclint(void *fdt, TTAtlantisState *s, + uint32_t *intc_phandles) { - void *fdt =3D MACHINE(s)->fdt; g_autofree char *name =3D NULL; g_autofree uint32_t *aclint_mtimer_cells =3D NULL; uint32_t aclint_cells_size; @@ -206,10 +205,9 @@ static void create_fdt_one_aplic(void *fdt, qemu_fdt_setprop_cell(fdt, name, "phandle", aplic_phandle); } =20 -static void create_fdt_pmu(TTAtlantisState *s) +static void create_fdt_pmu(void *fdt, TTAtlantisState *s) { char pmu_name[] =3D "/pmu"; - void *fdt =3D MACHINE(s)->fdt; RISCVCPU *hart =3D &s->cpus.harts[0]; =20 qemu_fdt_add_subnode(fdt, pmu_name); @@ -217,32 +215,29 @@ static void create_fdt_pmu(TTAtlantisState *s) riscv_pmu_generate_fdt_node(fdt, hart->pmu_avail_ctrs, pmu_name); } =20 -static void create_fdt_cpu(TTAtlantisState *s, const MemMapEntry *memmap, +static void create_fdt_cpu(void *fdt, TTAtlantisState *s, uint32_t aplic_s_phandle, uint32_t imsic_s_phandle) { - MachineState *ms =3D MACHINE(s); - void *fdt =3D MACHINE(s)->fdt; - g_autofree uint32_t *intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); + g_autofree uint32_t *intc_phandles =3D g_new0(uint32_t, s->cpus.num_ha= rts); + int num_harts =3D s->cpus.num_harts; =20 riscv_fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); =20 - riscv_create_fdt_socket_cpus(fdt, s->cpus.harts, 0, s->cpus.num_harts, + riscv_create_fdt_socket_cpus(fdt, s->cpus.harts, 0, num_harts, s->cpus.hartid_base, &fdt_phandle, intc_phandles, false, false); =20 - create_fdt_memory(s); - - create_fdt_aclint(s, intc_phandles); + create_fdt_aclint(fdt, s, intc_phandles); =20 /* M-level IMSIC node */ uint32_t msi_m_phandle =3D next_phandle(); - create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_MIMSIC], ms->smp.cpus, + create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_MIMSIC], num_harts, intc_phandles, msi_m_phandle, IRQ_M_EXT, TT_IMSIC_GUEST_BITS); =20 /* S-level IMSIC node */ - create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_SIMSIC], ms->smp.cpus, + create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_SIMSIC], num_harts, intc_phandles, imsic_s_phandle, IRQ_S_EXT, TT_IMSIC_GUEST_BITS); =20 @@ -252,13 +247,13 @@ static void create_fdt_cpu(TTAtlantisState *s, const = MemMapEntry *memmap, create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_MAPLIC], msi_m_phandle, intc_phandles, aplic_m_phandle, aplic_s_phandle, - IRQ_M_EXT, s->cpus.num_harts); + IRQ_M_EXT, num_harts); =20 /* S-level APLIC node */ create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_SAPLIC], imsic_s_phandle, intc_phandles, aplic_s_phandle, 0, - IRQ_S_EXT, s->cpus.num_harts); + IRQ_S_EXT, num_harts); } =20 static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, @@ -317,10 +312,9 @@ static void create_fdt_i2c(void *fdt, const MemMapEntr= y *mem, uint32_t irq, qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0); } =20 -static void create_fdt_i2c_device(TTAtlantisState *s, int bus, +static void create_fdt_i2c_device(void *fdt, TTAtlantisState *s, int bus, const char *compat, int addr) { - void *fdt =3D MACHINE(s)->fdt; hwaddr base =3D s->memmap[TT_ATL_I2C0 + bus].base; g_autofree char *name =3D g_strdup_printf("/soc/i2c@%"HWADDR_PRIX"/sen= sor@%x", base, addr); @@ -330,14 +324,15 @@ static void create_fdt_i2c_device(TTAtlantisState *s,= int bus, qemu_fdt_setprop_cell(fdt, name, "reg", addr); } =20 -static void finalize_fdt(TTAtlantisState *s) +static void finalize_fdt(void *fdt, TTAtlantisState *s) { uint32_t aplic_s_phandle =3D next_phandle(); uint32_t imsic_s_phandle =3D next_phandle(); uint32_t periph_clk_phandle =3D next_phandle(); - void *fdt =3D MACHINE(s)->fdt; =20 - create_fdt_cpu(s, s->memmap, aplic_s_phandle, imsic_s_phandle); + create_fdt_cpu(fdt, s, aplic_s_phandle, imsic_s_phandle); + + create_fdt_memory(fdt, s); =20 /* * We want to do this, but the Linux aplic driver was broken before v6= .16 @@ -359,8 +354,8 @@ static void finalize_fdt(TTAtlantisState *s) } =20 /* I2C peripherals: qemu specific */ - create_fdt_i2c_device(s, 0, "dallas,ds1338", 0x6f); - create_fdt_i2c_device(s, 4, "ti,tmp105", 0x48); + create_fdt_i2c_device(fdt, s, 0, "dallas,ds1338", 0x6f); + create_fdt_i2c_device(fdt, s, 4, "ti,tmp105", 0x48); } =20 static void create_fdt(TTAtlantisState *s) @@ -377,7 +372,7 @@ static void create_fdt(TTAtlantisState *s) =20 qemu_fdt_add_subnode(ms->fdt, "/aliases"); =20 - create_fdt_pmu(s); + create_fdt_pmu(ms->fdt, s); } =20 static void load_fdt(TTAtlantisState *s) @@ -408,7 +403,7 @@ static void load_fdt(TTAtlantisState *s) g_strfreev(node_path); } =20 - create_fdt_memory(s); + create_fdt_memory(ms->fdt, s); } =20 static void mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, @@ -439,7 +434,7 @@ static void tt_atlantis_machine_done(Notifier *notifier= , void *data) * dynamic sysbus devices. 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Thu, 03 Sep 2026 22:22:07 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 42/47] hw/riscv/atlantis: Use local reference for system memory Date: Fri, 4 Sep 2026 15:19:38 +1000 Message-ID: <20260904051943.799041-43-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499491252158500 Content-Type: text/plain; charset="utf-8" From: Joel Stanley Instead of system_memory, attach devices to TTAtlantisState::memory in preparation for the ->memory becoming a container. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-12-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/riscv/tt_atlantis.h | 1 + hw/riscv/tt_atlantis.c | 19 ++++++++++--------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 642490d217..a29c67c1cf 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -29,6 +29,7 @@ struct TTAtlantisState { Notifier machine_done; const MemMapEntry *memmap; =20 + MemoryRegion *memory; RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 940f982e6b..6555da02f0 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -482,13 +482,14 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) { TTAtlantisState *s =3D TT_ATLANTIS_MACHINE(machine); =20 - MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *ram_hi =3D g_new(MemoryRegion, 1); MemoryRegion *ram_lo =3D g_new(MemoryRegion, 1); MemoryRegion *bootrom =3D g_new(MemoryRegion, 1); ram_addr_t lo_ram_size; int hart_count =3D machine->smp.cpus; =20 + s->memory =3D get_system_memory(); + s->memmap =3D tt_atlantis_memmap; =20 object_initialize_child(OBJECT(machine), "soc", &s->cpus, @@ -504,7 +505,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); =20 - s->irqchip =3D riscv_create_aia(system_memory, + s->irqchip =3D riscv_create_aia(s->memory, true, TT_IMSIC_GUESTS, TT_IMSIC_STRIDE, TT_IMSIC_STRIDE, @@ -517,7 +518,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) TT_IRQCHIP_NUM_MSIS, TT_IRQCHIP_NUM_PRIO_BITS); =20 - riscv_aclint_mtimer_create(system_memory, + riscv_aclint_mtimer_create(s->memory, s->memmap[TT_ATL_ACLINT].base, TT_ACLINT_MTIME_SIZE, 0, hart_count, @@ -540,23 +541,23 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) =20 memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", machine-= >ram, 0, machine->ram_size); - memory_region_add_subregion(system_memory, + memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_HI].base, ram_hi); =20 lo_ram_size =3D MIN(machine->ram_size, s->memmap[TT_ATL_DDR_LO].size); memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", machine->= ram, 0, lo_ram_size); - memory_region_add_subregion(system_memory, + memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_LO].base, ram_lo); =20 /* Boot ROM */ memory_region_init_rom(bootrom, NULL, "tt-atlantis.bootrom", s->memmap[TT_ATL_BOOTROM].size, &error_fatal); - memory_region_add_subregion(system_memory, s->memmap[TT_ATL_BOOTROM].b= ase, + memory_region_add_subregion(s->memory, s->memmap[TT_ATL_BOOTROM].base, bootrom); =20 /* UART1, the soc console (UART0 is for the boot microcontroller) */ - serial_mm_init(system_memory, s->memmap[TT_ATL_UART1].base, 2, + serial_mm_init(s->memory, s->memmap[TT_ATL_UART1].base, 2, qdev_get_gpio_in(s->irqchip, TT_ATL_UART1_IRQ), 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); /* @@ -570,7 +571,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) */ object_initialize_child(OBJECT(s), "uart1", &s->uart1, TYPE_UNIMPLEMENTED_DEVICE); - mmio_map_unimplemented(system_memory, SYS_BUS_DEVICE(&s->uart1), + mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->uart1), "tt-atlantis.uart1", s->memmap[TT_ATL_UART1].ba= se, s->memmap[TT_ATL_UART1].size); =20 @@ -582,7 +583,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) TYPE_DESIGNWARE_I2C); sbd =3D SYS_BUS_DEVICE(&s->i2c[i]); sysbus_realize(sbd, &error_fatal); - memory_region_add_subregion(system_memory, + memory_region_add_subregion(s->memory, s->memmap[TT_ATL_I2C0 + i].base, sysbus_mmio_get_region(sbd, 0)); sysbus_connect_irq(sbd, 0, --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 03 Sep 2026 22:22:10 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 43/47] hw/riscv/atlantis: Decouple RAM size from MachineState Date: Fri, 4 Sep 2026 15:19:39 +1000 Message-ID: <20260904051943.799041-44-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499435048158500 From: Joel Stanley Keep a reference to the machine's RAM MemoryRegion in TTAtlantisState, and get the MemoryRegion's size where the configured RAM size is required. This allows reading the RAM size without needing a pointer to MachineState, decoupling the memory layout setup from the machine. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-13-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/riscv/tt_atlantis.h | 1 + hw/riscv/tt_atlantis.c | 20 ++++++++++++-------- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index a29c67c1cf..2ec283d0fd 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -30,6 +30,7 @@ struct TTAtlantisState { const MemMapEntry *memmap; =20 MemoryRegion *memory; + MemoryRegion *dram; RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 6555da02f0..4b4f5ff241 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -81,12 +81,13 @@ static uint32_t next_phandle(void) =20 static void create_fdt_memory(void *fdt, TTAtlantisState *s) { - hwaddr size_lo =3D MACHINE(s)->ram_size; + hwaddr ram_size =3D memory_region_size(s->dram); + hwaddr size_lo =3D ram_size; hwaddr size_hi =3D 0; =20 if (size_lo > s->memmap[TT_ATL_DDR_LO].size) { size_lo =3D s->memmap[TT_ATL_DDR_LO].size; - size_hi =3D MACHINE(s)->ram_size - size_lo; + size_hi =3D ram_size - size_lo; } =20 riscv_create_fdt_socket_memory(fdt, s->memmap[TT_ATL_DDR_LO].base, @@ -485,11 +486,14 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) MemoryRegion *ram_hi =3D g_new(MemoryRegion, 1); MemoryRegion *ram_lo =3D g_new(MemoryRegion, 1); MemoryRegion *bootrom =3D g_new(MemoryRegion, 1); - ram_addr_t lo_ram_size; + ram_addr_t lo_ram_size, ram_size; int hart_count =3D machine->smp.cpus; =20 s->memory =3D get_system_memory(); =20 + s->dram =3D machine->ram; + ram_size =3D memory_region_size(s->dram); + s->memmap =3D tt_atlantis_memmap; =20 object_initialize_child(OBJECT(machine), "soc", &s->cpus, @@ -532,20 +536,20 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) * The high address is where RAM lives. It is always present and may be * up to 64GB. The low address is an alias of the first 2GB of that RA= M. */ - if (machine->ram_size > s->memmap[TT_ATL_DDR_HI].size) { + if (ram_size > s->memmap[TT_ATL_DDR_HI].size) { char *sz =3D size_to_str(s->memmap[TT_ATL_DDR_HI].size); error_report("RAM size is too large, maximum is %s", sz); g_free(sz); exit(EXIT_FAILURE); } =20 - memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", machine-= >ram, - 0, machine->ram_size); + memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", s->dram, + 0, ram_size); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_HI].base, ram_hi); =20 - lo_ram_size =3D MIN(machine->ram_size, s->memmap[TT_ATL_DDR_LO].size); - memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", machine->= ram, + lo_ram_size =3D MIN(ram_size, s->memmap[TT_ATL_DDR_LO].size); + memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", s->dram, 0, lo_ram_size); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_LO].base, ram_lo); --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 03 Sep 2026 22:22:13 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 44/47] hw/riscv/atlantis: Make TTAtlantisState own memory containers Date: Fri, 4 Sep 2026 15:19:40 +1000 Message-ID: <20260904051943.799041-45-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499481189158500 From: Joel Stanley The DRAM hi, DRAM low and bootrom memory containers can be owned by the TTAtlantisState. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-14-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/riscv/tt_atlantis.h | 4 ++++ hw/riscv/tt_atlantis.c | 15 ++++++--------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 2ec283d0fd..9ca98bfb84 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -31,10 +31,14 @@ struct TTAtlantisState { =20 MemoryRegion *memory; MemoryRegion *dram; + MemoryRegion ram_hi; + MemoryRegion ram_lo; + RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; + MemoryRegion bootrom; }; =20 enum { diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 4b4f5ff241..2a46336674 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -483,9 +483,6 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) { TTAtlantisState *s =3D TT_ATLANTIS_MACHINE(machine); =20 - MemoryRegion *ram_hi =3D g_new(MemoryRegion, 1); - MemoryRegion *ram_lo =3D g_new(MemoryRegion, 1); - MemoryRegion *bootrom =3D g_new(MemoryRegion, 1); ram_addr_t lo_ram_size, ram_size; int hart_count =3D machine->smp.cpus; =20 @@ -543,22 +540,22 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) exit(EXIT_FAILURE); } =20 - memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", s->dram, + memory_region_init_alias(&s->ram_hi, OBJECT(machine), "ram.high", s->d= ram, 0, ram_size); memory_region_add_subregion(s->memory, - s->memmap[TT_ATL_DDR_HI].base, ram_hi); + s->memmap[TT_ATL_DDR_HI].base, &s->ram_hi); =20 lo_ram_size =3D MIN(ram_size, s->memmap[TT_ATL_DDR_LO].size); - memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", s->dram, + memory_region_init_alias(&s->ram_lo, OBJECT(machine), "ram.low", s->dr= am, 0, lo_ram_size); memory_region_add_subregion(s->memory, - s->memmap[TT_ATL_DDR_LO].base, ram_lo); + s->memmap[TT_ATL_DDR_LO].base, &s->ram_lo); =20 /* Boot ROM */ - memory_region_init_rom(bootrom, NULL, "tt-atlantis.bootrom", + memory_region_init_rom(&s->bootrom, NULL, "tt-atlantis.bootrom", s->memmap[TT_ATL_BOOTROM].size, &error_fatal); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_BOOTROM].base, - bootrom); + &s->bootrom); =20 /* UART1, the soc console (UART0 is for the boot microcontroller) */ serial_mm_init(s->memory, s->memmap[TT_ATL_UART1].base, 2, --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499476; cv=none; d=zohomail.com; s=zohoarc; b=k/lb/O9pk/eZsB9TD3XqZTq03BA1F5JGs0eFASj7DlnuwxcnhkLp2x/hiSqKVdG/Eqf9xrOW1IInPNF7EilC7+pn+CMDlsi26STQ4CqIAMeEOxR+K4MR0MbSRLM9QTsM61TRQxZ9olMCfnAVKGcG5iEAvBU6/wXE5XW/3bM9ffg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788499476; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 03 Sep 2026 22:22:16 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Portia Stephens , Daniel Henrique Barboza , Alistair Francis , Joel Stanley Subject: [PULL 45/47] hw/riscv: Add property to hart array to allow private memory Date: Fri, 4 Sep 2026 15:19:41 +1000 Message-ID: <20260904051943.799041-46-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499477220158500 Content-Type: text/plain; charset="utf-8" From: Portia Stephens There are platforms where CPUs have different mapping of system memory. The global system memory does not allow for this. This adds an optional property on the hart array to assign a specific memory region. The array passes the region to each hart it creates, so a machine can alias the harts' memory to system memory, while the harts view memory from their own memory region. Signed-off-by: Portia Stephens Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-15-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/riscv/riscv_hart.h | 2 ++ hw/riscv/riscv_hart.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 197fa16231..c3cd05a2c8 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -42,6 +42,8 @@ struct RISCVHartArrayState { uint64_t *rnmi_irqvec; uint32_t num_rnmi_excpvec; uint64_t *rnmi_excpvec; + /* Optional private memory region for use instead of system memory */ + MemoryRegion *memory; RISCVCPU *harts; }; =20 diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 747754be61..32fd39737f 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -53,6 +53,8 @@ static const Property riscv_harts_props[] =3D { DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState, num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64, uint64_t), + DEFINE_PROP_LINK("memory", RISCVHartArrayState, memory, + TYPE_MEMORY_REGION, MemoryRegion *), }; =20 static void riscv_harts_cpu_reset(void *opaque) @@ -117,6 +119,12 @@ static bool riscv_hart_realize(RISCVHartArrayState *s,= int idx, object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_typ= e); qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); =20 + /* Use private memory instead of system_memory if provided */ + if (s->memory) { + object_property_set_link(OBJECT(&s->harts[idx]), "memory", + OBJECT(s->memory), &error_abort); + } + if (s->harts[idx].cfg.ext_smrnmi) { if (idx < s->num_rnmi_irqvec) { qdev_prop_set_uint64(DEVICE(&s->harts[idx]), --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1788499457; cv=none; d=zohomail.com; s=zohoarc; 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Thu, 03 Sep 2026 22:22:19 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 46/47] hw/riscv/atlantis: Extract an Atlantis SoC device Date: Fri, 4 Sep 2026 15:19:42 +1000 Message-ID: <20260904051943.799041-47-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=alistair23@gmail.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499459064158500 Content-Type: text/plain; charset="utf-8" From: Joel Stanley Introduce TYPE_TT_ATLANTIS_SOC and move the hart array, AIA, ACLINT, boot ROM, UART and I2C controllers into the new TTAtlantisSoCState. The machine keeps ownership of RAM, device tree generation, firmware loading, and the board-level I2C slaves. This makes it easier to compose the SoC into a more complex machine in the future. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-16-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/riscv/tt_atlantis.h | 21 ++++- hw/riscv/tt_atlantis.c | 144 +++++++++++++++++++++++---------- 2 files changed, 119 insertions(+), 46 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 9ca98bfb84..5d4e4d133b 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -19,14 +19,16 @@ #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_MACHINE) =20 +#define TYPE_TT_ATLANTIS_SOC "tt-atlantis-soc" +OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisSoCState, TT_ATLANTIS_SOC) + #define TT_ATL_NUM_I2C 5 =20 -struct TTAtlantisState { +struct TTAtlantisSoCState { /*< private >*/ - MachineState parent; + DeviceState parent; =20 /*< public >*/ - Notifier machine_done; const MemMapEntry *memmap; =20 MemoryRegion *memory; @@ -39,6 +41,19 @@ struct TTAtlantisState { DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; MemoryRegion bootrom; + + uint32_t num_harts; + char *cpu_type; +}; + +struct TTAtlantisState { + /*< private >*/ + MachineState parent; + + /*< public >*/ + Notifier machine_done; + + TTAtlantisSoCState soc; }; =20 enum { diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 2a46336674..c44fd8d6d0 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -7,6 +7,7 @@ */ =20 #include "qemu/osdep.h" +#include "qapi/error.h" #include "qemu/cutils.h" #include "qemu/error-report.h" #include "qemu/guest-random.h" @@ -14,6 +15,7 @@ =20 #include "hw/core/boards.h" #include "hw/core/loader.h" +#include "hw/core/qdev-properties.h" #include "hw/core/sysbus.h" =20 #include "target/riscv/cpu.h" @@ -66,7 +68,7 @@ static const MemMapEntry tt_atlantis_memmap[] =3D { [TT_ATL_DDR_HI] =3D { 0x100000000, 0x1000000000 }, }; =20 -static I2CBus *i2c_get_bus(TTAtlantisState *s, unsigned busnr) +static I2CBus *i2c_get_bus(TTAtlantisSoCState *s, unsigned busnr) { assert(busnr < TT_ATL_NUM_I2C); =20 @@ -79,7 +81,7 @@ static uint32_t next_phandle(void) return fdt_phandle++; } =20 -static void create_fdt_memory(void *fdt, TTAtlantisState *s) +static void create_fdt_memory(void *fdt, TTAtlantisSoCState *s) { hwaddr ram_size =3D memory_region_size(s->dram); hwaddr size_lo =3D ram_size; @@ -104,7 +106,7 @@ static void create_fdt_memory(void *fdt, TTAtlantisStat= e *s) } } =20 -static void create_fdt_aclint(void *fdt, TTAtlantisState *s, +static void create_fdt_aclint(void *fdt, TTAtlantisSoCState *s, uint32_t *intc_phandles) { g_autofree char *name =3D NULL; @@ -206,7 +208,7 @@ static void create_fdt_one_aplic(void *fdt, qemu_fdt_setprop_cell(fdt, name, "phandle", aplic_phandle); } =20 -static void create_fdt_pmu(void *fdt, TTAtlantisState *s) +static void create_fdt_pmu(void *fdt, TTAtlantisSoCState *s) { char pmu_name[] =3D "/pmu"; RISCVCPU *hart =3D &s->cpus.harts[0]; @@ -216,7 +218,7 @@ static void create_fdt_pmu(void *fdt, TTAtlantisState *= s) riscv_pmu_generate_fdt_node(fdt, hart->pmu_avail_ctrs, pmu_name); } =20 -static void create_fdt_cpu(void *fdt, TTAtlantisState *s, +static void create_fdt_cpu(void *fdt, TTAtlantisSoCState *s, uint32_t aplic_s_phandle, uint32_t imsic_s_phandle) { @@ -313,7 +315,7 @@ static void create_fdt_i2c(void *fdt, const MemMapEntry= *mem, uint32_t irq, qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0); } =20 -static void create_fdt_i2c_device(void *fdt, TTAtlantisState *s, int bus, +static void create_fdt_i2c_device(void *fdt, TTAtlantisSoCState *s, int bu= s, const char *compat, int addr) { hwaddr base =3D s->memmap[TT_ATL_I2C0 + bus].base; @@ -325,7 +327,7 @@ static void create_fdt_i2c_device(void *fdt, TTAtlantis= State *s, int bus, qemu_fdt_setprop_cell(fdt, name, "reg", addr); } =20 -static void finalize_fdt(void *fdt, TTAtlantisState *s) +static void finalize_fdt(void *fdt, TTAtlantisSoCState *s) { uint32_t aplic_s_phandle =3D next_phandle(); uint32_t imsic_s_phandle =3D next_phandle(); @@ -359,9 +361,9 @@ static void finalize_fdt(void *fdt, TTAtlantisState *s) create_fdt_i2c_device(fdt, s, 4, "ti,tmp105", 0x48); } =20 -static void create_fdt(TTAtlantisState *s) +static void create_fdt(TTAtlantisState *ams) { - MachineState *ms =3D MACHINE(s); + MachineState *ms =3D MACHINE(ams); int fdt_size =3D 0; =20 ms->fdt =3D riscv_create_board_device_tree("Tenstorrent Atlantis RISC-= V Machine", @@ -373,12 +375,12 @@ static void create_fdt(TTAtlantisState *s) =20 qemu_fdt_add_subnode(ms->fdt, "/aliases"); =20 - create_fdt_pmu(ms->fdt, s); + create_fdt_pmu(ms->fdt, &ams->soc); } =20 -static void load_fdt(TTAtlantisState *s) +static void load_fdt(TTAtlantisState *ams) { - MachineState *ms =3D MACHINE(s); + MachineState *ms =3D MACHINE(ams); char **node_path; Error *err =3D NULL; int fdt_size =3D 0; @@ -404,7 +406,7 @@ static void load_fdt(TTAtlantisState *s) g_strfreev(node_path); } =20 - create_fdt_memory(ms->fdt, s); + create_fdt_memory(ms->fdt, &ams->soc); } =20 static void mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, @@ -418,10 +420,11 @@ static void mmio_map_unimplemented(MemoryRegion *memo= ry, SysBusDevice *dev, sysbus_mmio_get_region(dev, 0), -1= 000); } =20 -static void tt_atlantis_machine_done(Notifier *notifier, void *data) +static void tt_atlantis_machine_done(Notifier *n, void *data) { - TTAtlantisState *s =3D container_of(notifier, TTAtlantisState, machine= _done); - MachineState *machine =3D MACHINE(s); + TTAtlantisState *ams =3D container_of(n, TTAtlantisState, machine_done= ); + TTAtlantisSoCState *s =3D &ams->soc; + MachineState *machine =3D MACHINE(ams); hwaddr start_addr =3D s->memmap[TT_ATL_DDR_LO].base; hwaddr mem_size; target_ulong firmware_end_addr, kernel_start_addr; @@ -479,23 +482,39 @@ static void tt_atlantis_machine_done(Notifier *notifi= er, void *data) fdt_load_addr); } =20 -static void tt_atlantis_machine_init(MachineState *machine) +static void tt_atlantis_soc_init(Object *obj) { - TTAtlantisState *s =3D TT_ATLANTIS_MACHINE(machine); + TTAtlantisSoCState *s =3D TT_ATLANTIS_SOC(obj); + + object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); + + object_initialize_child(obj, "uart1", &s->uart1, + TYPE_UNIMPLEMENTED_DEVICE); =20 + for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { + object_initialize_child(obj, "i2c[*]", &s->i2c[i], + TYPE_DESIGNWARE_I2C); + } +} + +static void tt_atlantis_soc_realize(DeviceState *dev, Error **errp) +{ + TTAtlantisSoCState *s =3D TT_ATLANTIS_SOC(dev); ram_addr_t lo_ram_size, ram_size; - int hart_count =3D machine->smp.cpus; + int hart_count =3D s->num_harts; =20 s->memory =3D get_system_memory(); =20 - s->dram =3D machine->ram; + if (!s->dram) { + error_setg(errp, "'dram' link is not set"); + return; + } ram_size =3D memory_region_size(s->dram); =20 s->memmap =3D tt_atlantis_memmap; =20 - object_initialize_child(OBJECT(machine), "soc", &s->cpus, - TYPE_RISCV_HART_ARRAY); - object_property_set_str(OBJECT(&s->cpus), "cpu-type", machine->cpu_typ= e, + /* CPUs */ + object_property_set_str(OBJECT(&s->cpus), "cpu-type", s->cpu_type, &error_abort); object_property_set_int(OBJECT(&s->cpus), "hartid-base", 0, &error_abort); @@ -504,7 +523,9 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) object_property_set_int(OBJECT(&s->cpus), "resetvec", s->memmap[TT_ATL_BOOTROM].base, &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpus), errp)) { + return; + } =20 s->irqchip =3D riscv_create_aia(s->memory, true, TT_IMSIC_GUESTS, @@ -534,26 +555,27 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) * up to 64GB. The low address is an alias of the first 2GB of that RA= M. */ if (ram_size > s->memmap[TT_ATL_DDR_HI].size) { - char *sz =3D size_to_str(s->memmap[TT_ATL_DDR_HI].size); - error_report("RAM size is too large, maximum is %s", sz); - g_free(sz); - exit(EXIT_FAILURE); + g_autofree char *sz =3D size_to_str(s->memmap[TT_ATL_DDR_HI].size); + error_setg(errp, "RAM size is too large, maximum is %s", sz); + return; } =20 - memory_region_init_alias(&s->ram_hi, OBJECT(machine), "ram.high", s->d= ram, + memory_region_init_alias(&s->ram_hi, OBJECT(s), "ram.high", s->dram, 0, ram_size); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_HI].base, &s->ram_hi); =20 lo_ram_size =3D MIN(ram_size, s->memmap[TT_ATL_DDR_LO].size); - memory_region_init_alias(&s->ram_lo, OBJECT(machine), "ram.low", s->dr= am, + memory_region_init_alias(&s->ram_lo, OBJECT(s), "ram.low", s->dram, 0, lo_ram_size); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_LO].base, &s->ram_lo); =20 /* Boot ROM */ - memory_region_init_rom(&s->bootrom, NULL, "tt-atlantis.bootrom", - s->memmap[TT_ATL_BOOTROM].size, &error_fatal); + if (!memory_region_init_rom(&s->bootrom, OBJECT(s), "tt-atlantis.bootr= om", + s->memmap[TT_ATL_BOOTROM].size, errp)) { + return; + } memory_region_add_subregion(s->memory, s->memmap[TT_ATL_BOOTROM].base, &s->bootrom); =20 @@ -570,26 +592,56 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) * Create an unimplemented device region so writes don't fault * and reads return zero, which keeps Linux happy. */ - object_initialize_child(OBJECT(s), "uart1", &s->uart1, - TYPE_UNIMPLEMENTED_DEVICE); mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->uart1), "tt-atlantis.uart1", s->memmap[TT_ATL_UART1].ba= se, s->memmap[TT_ATL_UART1].size); =20 /* I2C */ for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { - SysBusDevice *sbd; + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->i2c[i]); =20 - object_initialize_child(OBJECT(s), "i2c[*]", &s->i2c[i], - TYPE_DESIGNWARE_I2C); - sbd =3D SYS_BUS_DEVICE(&s->i2c[i]); - sysbus_realize(sbd, &error_fatal); + if (!sysbus_realize(sbd, errp)) { + return; + } memory_region_add_subregion(s->memory, s->memmap[TT_ATL_I2C0 + i].base, sysbus_mmio_get_region(sbd, 0)); sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(s->irqchip, TT_ATL_I2C0_IRQ + = i)); } +} + +static const Property tt_atlantis_soc_props[] =3D { + DEFINE_PROP_STRING("cpu-type", TTAtlantisSoCState, cpu_type), + DEFINE_PROP_UINT32("num-harts", TTAtlantisSoCState, num_harts, 8), + DEFINE_PROP_LINK("dram", TTAtlantisSoCState, dram, + TYPE_MEMORY_REGION, MemoryRegion *), +}; + +static void tt_atlantis_soc_class_init(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D tt_atlantis_soc_realize; + device_class_set_props(dc, tt_atlantis_soc_props); + /* The SoC can only be instantiated from the machine */ + dc->user_creatable =3D false; +} + +static void tt_atlantis_machine_init(MachineState *machine) +{ + TTAtlantisState *ams =3D TT_ATLANTIS_MACHINE(machine); + TTAtlantisSoCState *s =3D &ams->soc; + + object_initialize_child(OBJECT(machine), "soc", &ams->soc, + TYPE_TT_ATLANTIS_SOC); + object_property_set_str(OBJECT(&ams->soc), "cpu-type", machine->cpu_ty= pe, + &error_abort); + object_property_set_int(OBJECT(&ams->soc), "num-harts", machine->smp.c= pus, + &error_abort); + object_property_set_link(OBJECT(&ams->soc), "dram", OBJECT(machine->ra= m), + &error_abort); + qdev_realize(DEVICE(&ams->soc), NULL, &error_fatal); =20 /* I2C peripherals: qemu specific */ i2c_slave_create_simple(i2c_get_bus(s, 0), "ds1338", 0x6f); @@ -597,13 +649,13 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) =20 /* Load or create device tree */ if (machine->dtb) { - load_fdt(s); + load_fdt(ams); } else { - create_fdt(s); + create_fdt(ams); } =20 - s->machine_done.notify =3D tt_atlantis_machine_done; - qemu_add_machine_init_done_notifier(&s->machine_done); + ams->machine_done.notify =3D tt_atlantis_machine_done; + qemu_add_machine_init_done_notifier(&ams->machine_done); } =20 static void tt_atlantis_machine_class_init(ObjectClass *oc, const void *da= ta) @@ -623,6 +675,12 @@ static void tt_atlantis_machine_class_init(ObjectClass= *oc, const void *data) =20 static const TypeInfo tt_atlantis_types[] =3D { { + .name =3D TYPE_TT_ATLANTIS_SOC, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(TTAtlantisSoCState), + .instance_init =3D tt_atlantis_soc_init, + .class_init =3D tt_atlantis_soc_class_init, + }, { .name =3D MACHINE_TYPE_NAME("tt-atlantis"), .parent =3D TYPE_MACHINE, .class_init =3D tt_atlantis_machine_class_init, --=20 2.55.0 From nobody Sat Sep 26 20:52:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 03 Sep 2026 22:22:22 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Joel Stanley , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 47/47] hw/riscv/atlantis: Map the SoC through a memory container Date: Fri, 4 Sep 2026 15:19:43 +1000 Message-ID: <20260904051943.799041-48-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904051943.799041-1-alistair.francis@wdc.com> References: <20260904051943.799041-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=alistair23@gmail.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1788499447126158500 Content-Type: text/plain; charset="utf-8" From: Joel Stanley Give the Atlantis SoC a 'memory' link property. The machine creates a container MemoryRegion, maps it at address 0 of system memory, and passes it to the SoC together with the machine RAM. The SoC maps devices into the 'memory' container instead of system memory, allowing TTAtlantisSoCState to be composed together with other SoCs in the future. This prepares the machine for adding other microcontrollers that share the memory bus with the Ascalon complex (aka the Atlantis SoC), but with their own view of the address map. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley Message-ID: <20260903055131.257903-17-joel@jms.id.au> Signed-off-by: Alistair Francis --- include/hw/riscv/tt_atlantis.h | 1 + hw/riscv/tt_atlantis.c | 17 +++++++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 5d4e4d133b..3923308b7c 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -53,6 +53,7 @@ struct TTAtlantisState { /*< public >*/ Notifier machine_done; =20 + MemoryRegion soc_memory; TTAtlantisSoCState soc; }; =20 diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index c44fd8d6d0..8a219afef7 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -503,8 +503,10 @@ static void tt_atlantis_soc_realize(DeviceState *dev, = Error **errp) ram_addr_t lo_ram_size, ram_size; int hart_count =3D s->num_harts; =20 - s->memory =3D get_system_memory(); - + if (!s->memory) { + error_setg(errp, "'memory' link is not set"); + return; + } if (!s->dram) { error_setg(errp, "'dram' link is not set"); return; @@ -523,6 +525,8 @@ static void tt_atlantis_soc_realize(DeviceState *dev, E= rror **errp) object_property_set_int(OBJECT(&s->cpus), "resetvec", s->memmap[TT_ATL_BOOTROM].base, &error_abort); + object_property_set_link(OBJECT(&s->cpus), "memory", OBJECT(s->memory), + &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpus), errp)) { return; } @@ -614,6 +618,8 @@ static void tt_atlantis_soc_realize(DeviceState *dev, E= rror **errp) static const Property tt_atlantis_soc_props[] =3D { DEFINE_PROP_STRING("cpu-type", TTAtlantisSoCState, cpu_type), DEFINE_PROP_UINT32("num-harts", TTAtlantisSoCState, num_harts, 8), + DEFINE_PROP_LINK("memory", TTAtlantisSoCState, memory, + TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_LINK("dram", TTAtlantisSoCState, dram, TYPE_MEMORY_REGION, MemoryRegion *), }; @@ -633,12 +639,19 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) TTAtlantisState *ams =3D TT_ATLANTIS_MACHINE(machine); TTAtlantisSoCState *s =3D &ams->soc; =20 + memory_region_init(&ams->soc_memory, OBJECT(machine), + "tt-atlantis.soc-memory", UINT64_MAX); + memory_region_add_subregion(get_system_memory(), 0, &ams->soc_memory); + object_initialize_child(OBJECT(machine), "soc", &ams->soc, TYPE_TT_ATLANTIS_SOC); object_property_set_str(OBJECT(&ams->soc), "cpu-type", machine->cpu_ty= pe, &error_abort); object_property_set_int(OBJECT(&ams->soc), "num-harts", machine->smp.c= pus, &error_abort); + + object_property_set_link(OBJECT(&ams->soc), "memory", + OBJECT(&ams->soc_memory), &error_abort); object_property_set_link(OBJECT(&ams->soc), "dram", OBJECT(machine->ra= m), &error_abort); qdev_realize(DEVICE(&ams->soc), NULL, &error_fatal); --=20 2.55.0