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Fri, 04 Sep 2026 11:43:08 -0700 (PDT) From: Trevor Gamblin Date: Fri, 04 Sep 2026 14:43:04 -0400 Subject: [PATCH v2 1/2] target/riscv: extract check_sfence_vma() from helper_tlb_flush() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-riscv_tlb_page_flush-v2-1-defec3f29312@baylibre.com> References: <20260904-riscv_tlb_page_flush-v2-0-defec3f29312@baylibre.com> In-Reply-To: <20260904-riscv_tlb_page_flush-v2-0-defec3f29312@baylibre.com> To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org, Trevor Gamblin X-Mailer: b4 0.16.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f35; envelope-from=tgamblin@baylibre.com; helo=mail-qv1-xf35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @baylibre.com) X-ZM-MESSAGEID: 1788547439321154100 Create a new function to encapsulate the privilege/hypervisor checks performed inside helper_tlb_flush(). The idea is to pass GETPC() as an argument directly to it inside the helper_tlb_flush() function. We'll use this function in the following patch for helper_tlb_flush_page(). Signed-off-by: Trevor Gamblin Reviewed-by: Daniel Henrique Barboza --- target/riscv/tcg/op_helper.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index 3e94005d2b..7f63f3ada5 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -588,21 +588,25 @@ void helper_wrs_nto(CPURISCVState *env) } } =20 -void helper_tlb_flush(CPURISCVState *env) +static void check_sfence_vma(CPURISCVState *env, uintptr_t ra) { - CPUState *cs =3D env_cpu(env); if (!env->virt_enabled && (env->priv =3D=3D PRV_U || (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)))= ) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } else if (env->virt_enabled && (env->priv =3D=3D PRV_U || get_field(env->hstatus, HSTATUS_= VTVM))) { - riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); - } else { - tlb_flush(cs); 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Fri, 04 Sep 2026 11:43:09 -0700 (PDT) From: Trevor Gamblin Date: Fri, 04 Sep 2026 14:43:05 -0400 Subject: [PATCH v2 2/2] target/riscv: add helper_tlb_flush_page(), use for sfence.vma with vaddr operand MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-riscv_tlb_page_flush-v2-2-defec3f29312@baylibre.com> References: <20260904-riscv_tlb_page_flush-v2-0-defec3f29312@baylibre.com> In-Reply-To: <20260904-riscv_tlb_page_flush-v2-0-defec3f29312@baylibre.com> To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org, Trevor Gamblin X-Mailer: b4 0.16.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=tgamblin@baylibre.com; helo=mail-qk1-x736.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @baylibre.com) X-ZM-MESSAGEID: 1788547454746154100 sfence.vma unconditionally called helper_tlb_flush(), regardless of the rs1 (vaddr) and rs2 (asid) operands, forcing a page-table walk on the next access. Create a page-level counterpart to helper_tlb_flush() called helper_tlb_flush_page(), and use it whenever rs1 !=3D 0, falling back to the existing full flush for rs1 =3D=3D 0. This makes RISC-V behaviour more similar to ARM's equivalent (tlbi_aa64_vae1_write), which already does tlb_flush_page_by_mmuidx() instead of a full flush. Pass get_address(ctx, a->rs1, 0) to gen_helper_tlb_flush_page() rather than get_gpr(), so that the address being passed matches the current addr_xl width regardless of '-cpu' input. Otherwise, the raw register value can carry garbage above that width and never match the address the TLB entry was actually filled under, so the flush silently misses and a stale mapping survives. Signed-off-by: Trevor Gamblin Reviewed-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson --- target/riscv/helper.h | 1 + target/riscv/tcg/insn_trans/trans_privileged.c.inc | 6 +++++- target/riscv/tcg/op_helper.c | 6 ++++++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 4fc2d3a155..652f85a5c7 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -137,6 +137,7 @@ DEF_HELPER_1(ctr_clear, void, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) +DEF_HELPER_2(tlb_flush_page, void, env, tl) DEF_HELPER_1(tlb_flush_all, void, env) DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl) /* Native Debug */ diff --git a/target/riscv/tcg/insn_trans/trans_privileged.c.inc b/target/ri= scv/tcg/insn_trans/trans_privileged.c.inc index a8eaccef67..8655fa332e 100644 --- a/target/riscv/tcg/insn_trans/trans_privileged.c.inc +++ b/target/riscv/tcg/insn_trans/trans_privileged.c.inc @@ -155,7 +155,11 @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sf= ence_vma *a) { #ifndef CONFIG_USER_ONLY decode_save_opc(ctx, 0); - gen_helper_tlb_flush(tcg_env); + if (a->rs1 =3D=3D 0) { + gen_helper_tlb_flush(tcg_env); + } else { + gen_helper_tlb_flush_page(tcg_env, get_address(ctx, a->rs1, 0)); + } return true; #endif return false; diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index 7f63f3ada5..178b4d271b 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -607,6 +607,12 @@ void helper_tlb_flush(CPURISCVState *env) tlb_flush(cs); } =20 +void helper_tlb_flush_page(CPURISCVState *env, target_ulong addr) +{ + check_sfence_vma(env, GETPC()); + tlb_flush_page(env_cpu(env), addr); +} + void helper_tlb_flush_all(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); --=20 2.55.0