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Fri, 04 Sep 2026 09:05:11 -0700 (PDT) From: Jim MacArthur Date: Fri, 04 Sep 2026 17:05:01 +0100 Subject: [PATCH v2 1/4] hw/pci: add IDE + TEE capability to PCIe root port MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-jmac-rme-da-prep-v2-1-fb461d78bbb2@linaro.org> References: <20260904-jmac-rme-da-prep-v2-0-fb461d78bbb2@linaro.org> In-Reply-To: <20260904-jmac-rme-da-prep-v2-0-fb461d78bbb2@linaro.org> To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , John Snow , "Denis V. Lunev" , qemu-block@nongnu.org, Jim MacArthur , Pierrick Bouvier , Pierrick Bouvier X-Mailer: b4 0.13.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=jim.macarthur@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788537962964154100 From: Pierrick Bouvier Signed-off-by: Pierrick Bouvier Signed-off-by: Jim MacArthur --- hw/pci-bridge/gen_pcie_root_port.c | 8 ++++++++ hw/pci/pcie.c | 15 +++++++++++++++ include/hw/pci/pcie.h | 3 +++ include/hw/pci/pcie_regs.h | 4 ++++ 4 files changed, 30 insertions(+) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index 5434d693d9..452ebf69b3 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -26,6 +26,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(GenPCIERootPort, GEN_PCIE_ROOT= _PORT) #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 #define GEN_PCIE_ROOT_PORT_ACS_OFFSET \ (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF) +#define GEN_PCIE_ROOT_PORT_ACS_END \ + (GEN_PCIE_ROOT_PORT_ACS_OFFSET + PCI_ACS_SIZEOF) =20 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1 #define GEN_PCIE_ROOT_DEFAULT_IO_RANGE 4096 @@ -100,6 +102,12 @@ static void gen_rp_realize(DeviceState *dev, Error **e= rrp) d->wmask[PCI_IO_BASE] =3D 0; d->wmask[PCI_IO_LIMIT] =3D 0; } + + uint32_t offset =3D GEN_PCIE_ROOT_PORT_ACS_END; + pcie_ide_init(d, offset); + offset +=3D PCI_IDE_SIZEOF; + + pcie_cap_tee_init(d); } =20 static const VMStateDescription vmstate_rp_dev =3D { diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 4622c75e48..b9ead826ed 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -968,6 +968,12 @@ void pcie_cap_flr_write_config(PCIDevice *dev, } } =20 +void pcie_cap_tee_init(PCIDevice *dev) +{ + pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DE= VCAP, + PCI_EXP_DEVCAP_TEE); +} + /* Alternative Routing-ID Interpretation (ARI) * forwarding support for root and downstream ports */ @@ -1371,6 +1377,15 @@ uint32_t pcie_pri_get_req_alloc(const PCIDevice *dev) return pci_get_long(dev->config + dev->exp.pri_cap + PCI_PRI_ALLOC_REQ= ); } =20 +/* IDE */ +void pcie_ide_init(PCIDevice *dev, uint16_t offset) +{ + pcie_add_capability(dev, PCI_EXT_CAP_ID_IDE, PCI_IDE_VER, + offset, PCI_IDE_SIZEOF); + uint32_t cap =3D PCI_IDE_CAP_SELECTIVE; + pci_set_byte(dev->config + offset + PCI_IDE_CAP, cap); +} + bool pcie_pri_enabled(const PCIDevice *dev) { if (!pci_is_express(dev) || !dev->exp.pri_cap) { diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 71ba94874b..db66678252 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -123,6 +123,8 @@ void pcie_cap_flr_init(PCIDevice *dev); void pcie_cap_flr_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len); =20 +void pcie_cap_tee_init(PCIDevice *dev); + /* ARI forwarding capability and control */ void pcie_cap_arifwd_init(PCIDevice *dev); void pcie_cap_arifwd_reset(PCIDevice *dev); @@ -161,6 +163,7 @@ void pcie_pasid_init(PCIDevice *dev, uint16_t offset, u= int8_t pasid_width, bool exec_perm, bool priv_mod); void pcie_pri_init(PCIDevice *dev, uint16_t offset, uint32_t outstanding_p= r_cap, bool prg_response_pasid_req); +void pcie_ide_init(PCIDevice *dev, uint16_t offset); =20 uint32_t pcie_pri_get_req_alloc(const PCIDevice *dev); bool pcie_pri_enabled(const PCIDevice *dev); diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 33a22229fe..aa21177411 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -182,4 +182,8 @@ typedef enum PCIExpLinkWidth { #define PCI_DOE_VER 0x1 #define PCI_DOE_SIZEOF 24 =20 +/* IDE */ +#define PCI_IDE_VER 0x1 +#define PCI_IDE_SIZEOF 12 + #endif /* QEMU_PCIE_REGS_H */ --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788537963; cv=none; d=zohomail.com; s=zohoarc; b=K80z3cIKQDPqi3UocG18WsaaKa/otNdffsF9F9LVpKAmecvSkyQjpSx4SEohLtETN3+o06beopEEX7EDFiEVdahPxZHcujP6gvgpI5QnX0svYh7Hbvb7JnZfOofrJGDtn7Syssehr0eMbXWo6l1yg5ARabg8M1QTkFM4IUVz8zw= ARC-Message-Signature: i=1; a=rsa-sha256; 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Fri, 04 Sep 2026 09:05:11 -0700 (PDT) From: Jim MacArthur Date: Fri, 04 Sep 2026 17:05:02 +0100 Subject: [PATCH v2 2/4] sata: add SPDM + IDE + TEE pci support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-jmac-rme-da-prep-v2-2-fb461d78bbb2@linaro.org> References: <20260904-jmac-rme-da-prep-v2-0-fb461d78bbb2@linaro.org> In-Reply-To: <20260904-jmac-rme-da-prep-v2-0-fb461d78bbb2@linaro.org> To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , John Snow , "Denis V. Lunev" , qemu-block@nongnu.org, Jim MacArthur , Pierrick Bouvier , Pierrick Bouvier X-Mailer: b4 0.13.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=jim.macarthur@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788537964917154100 From: Pierrick Bouvier Replaces the ICH9 config_write/config_read which versions which will use DOE to write/read config if we have an SPDM port and DOE capability. Signed-off-by: Pierrick Bouvier Signed-off-by: Jim MacArthur --- hw/ide/ich.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/hw/ide/ich.c b/hw/ide/ich.c index b00987f08d..d2731598ea 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -70,6 +70,7 @@ #include "hw/ide/pci.h" #include "hw/ide/ahci-pci.h" #include "ahci-internal.h" +#include "system/spdm-socket.h" =20 #define ICH9_MSI_CAP_OFFSET 0x80 #define ICH9_SATA_CAP_OFFSET 0xA8 @@ -90,6 +91,10 @@ static const VMStateDescription vmstate_ich9_ahci =3D { }, }; =20 +static const Property ich_props[] =3D { + DEFINE_PROP_UINT16("spdm_port", PCIDevice, spdm_port, 0), +}; + static void pci_ich9_ahci_update_irq(void *opaque, int irq_num, int level) { PCIDevice *pci_dev =3D opaque; @@ -120,6 +125,27 @@ static void pci_ich9_ahci_init(Object *obj) d->ahci.irq =3D &d->irq; } =20 +static bool pcie_doe_spdm_rsp(DOECap *doe_cap) +{ + void *req =3D pcie_doe_get_write_mbox_ptr(doe_cap); + uint32_t req_len =3D pcie_doe_get_obj_len(req) * 4; + void *rsp =3D doe_cap->read_mbox; + uint32_t rsp_len =3D SPDM_SOCKET_MAX_MESSAGE_BUFFER_SIZE; + + uint32_t recvd =3D spdm_socket_rsp(doe_cap->spdm_socket, + SPDM_SOCKET_TRANSPORT_TYPE_PCI_DOE, + req, req_len, rsp, rsp_len); + doe_cap->read_mbox_len +=3D DIV_ROUND_UP(recvd, 4); + + return recvd !=3D 0; +} + +static DOEProtocol doe_spdm_prot[] =3D { + { PCI_VENDOR_ID_PCI_SIG, PCI_SIG_DOE_CMA, pcie_doe_spdm_rsp }, + { PCI_VENDOR_ID_PCI_SIG, PCI_SIG_DOE_SECURED_CMA, pcie_doe_spdm_rsp }, + { } +}; + static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp) { AHCIPCIState *d; @@ -145,6 +171,8 @@ static void pci_ich9_ahci_realize(PCIDevice *dev, Error= **errp) pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->ahci.mem); =20 + pcie_endpoint_cap_init(dev, 0xa8 + 0x8); /* right after SATA */ + sata_cap_offset =3D pci_add_capability(dev, PCI_CAP_ID_SATA, ICH9_SATA_CAP_OFFSET, SATA_CAP_S= IZE, errp); @@ -165,6 +193,25 @@ static void pci_ich9_ahci_realize(PCIDevice *dev, Erro= r **errp) /* Any error other than -ENOTSUP(board's MSI support is broken) * is a programming error. Fall back to INTx silently on -ENOTSUP */ assert(!ret || ret =3D=3D -ENOTSUP); + + uint16_t cap_offset =3D PCI_CONFIG_SPACE_SIZE; + + if (dev->spdm_port) { + pcie_doe_init(dev, &dev->doe_spdm, cap_offset, + doe_spdm_prot, true, 0); + cap_offset +=3D PCI_DOE_SIZEOF; + + dev->doe_spdm.spdm_socket =3D spdm_socket_connect(dev->spdm_port, + errp); + assert(dev->doe_spdm.spdm_socket > 0); + } + + /* ide */ + pcie_ide_init(dev, cap_offset); + cap_offset +=3D PCI_IDE_SIZEOF; + + /* tee */ + pcie_cap_tee_init(dev); } =20 static void pci_ich9_uninit(PCIDevice *dev) @@ -176,18 +223,41 @@ static void pci_ich9_uninit(PCIDevice *dev) ahci_uninit(&d->ahci); } =20 +static uint32_t ich_read_config(PCIDevice *dev, uint32_t address, int len) +{ + uint32_t val; + if (dev->spdm_port && pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE)) { + if (pcie_doe_read_config(&dev->doe_spdm, address, len, &val)) { + return val; + } + } + return pci_default_read_config(dev, address, len); +} + +static void ich_write_config(PCIDevice *dev, uint32_t address, + uint32_t val, int len) +{ + if (pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE)) { + pcie_doe_write_config(&dev->doe_spdm, address, val, len); + } + pci_default_write_config(dev, address, val, len); +} + static void ich_ahci_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 k->realize =3D pci_ich9_ahci_realize; + k->config_write =3D ich_write_config; + k->config_read =3D ich_read_config; k->exit =3D pci_ich9_uninit; k->vendor_id =3D PCI_VENDOR_ID_INTEL; k->device_id =3D PCI_DEVICE_ID_INTEL_82801IR; k->revision =3D 0x02; k->class_id =3D PCI_CLASS_STORAGE_SATA; dc->vmsd =3D &vmstate_ich9_ahci; + device_class_set_props(dc, ich_props); device_class_set_legacy_reset(dc, pci_ich9_reset); set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } @@ -199,7 +269,7 @@ static const TypeInfo ich_ahci_info =3D { .instance_init =3D pci_ich9_ahci_init, .class_init =3D ich_ahci_class_init, .interfaces =3D (const InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { INTERFACE_PCIE_DEVICE }, { }, }, }; --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 04 Sep 2026 09:05:12 -0700 (PDT) From: Jim MacArthur Date: Fri, 04 Sep 2026 17:05:03 +0100 Subject: [PATCH v2 3/4] hw/pci: add DVSEC RMEDA capability to PCIe root port MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-jmac-rme-da-prep-v2-3-fb461d78bbb2@linaro.org> References: <20260904-jmac-rme-da-prep-v2-0-fb461d78bbb2@linaro.org> In-Reply-To: <20260904-jmac-rme-da-prep-v2-0-fb461d78bbb2@linaro.org> To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , John Snow , "Denis V. Lunev" , qemu-block@nongnu.org, Jim MacArthur , Pierrick Bouvier , Viresh Kumar , Pierrick Bouvier X-Mailer: b4 0.13.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=jim.macarthur@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788538001561154100 From: Pierrick Bouvier Signed-off-by: Pierrick Bouvier Signed-off-by: Viresh Kumar Signed-off-by: Jim MacArthur After this we can see all the capabilities listed for the PCIe bridge: 00:05.0 PCI bridge: Red Hat, Inc. QEMU PCIe Root port (prog-if 00 [Normal d= ecode]) ... Capabilities: [54] Express (v2) Root Port (Slot+), IntMsgNum 0 ... Capabilities: [48] MSI-X: Enable+ Count=3D1 Masked- Vector table: BAR=3D0 offset=3D00000000 PBA: BAR=3D0 offset=3D00000800 Capabilities: [40] Subsystem: Red Hat, Inc. Device 0000 Capabilities: [100 v2] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPB= lockedErr- PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXl= atBlocked- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UncorrIntErr+ BlockedTLP- AtomicOpBlocked- TLPB= lockedErr+ PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXl= atBlocked- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- UncorrIntErr+ BlockedTLP- AtomicOpBlocked- TLPB= lockedErr- PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXl= atBlocked- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- CorrInt= Err- HeaderOF- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ CorrInt= Err+ HeaderOF+ AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCC= hkEn- MultHdrRecCap+ MultHdrRecEn- TLPPfxPres- HdrLogCap- HeaderLog: 00000000 00000000 00000000 00000000 RootCmd: CERptEn+ NFERptEn+ FERptEn+ RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd- FirstFatal- NonFatalMsg- FatalMsg- IntMsgNum 0 ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000 Capabilities: [148 v1] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl= - DirectTrans+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl= - DirectTrans- Capabilities: [150 v1] Designated Vendor-Specific: Vendor=3D13b5 ID=3Dff01= Rev=3D0 Len=3D16 Capabilities: [164 v1] Integrity & Data Encryption IDECap: Lnk=3D0 Sel=3D1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM- Alg=3D'AES= -GCM-256-96b' TCs=3D1 TeeLim- IDECtl: FTEn- [170]SelectiveIDE#0 Cap: RID#=3D0 [174]SelectiveIDE#0 Ctl: En- NPR- PR- CPL- PCRC- CFG- HdrEnc=3Dno Alg=3D'= AES-GCM-256-96b' TC0 ID0 [178]SelectiveIDE#0 Sta: insecure RecvChkFail- [17c]SelectiveIDE#0 RID: Valid- Base=3D0 Limit=3D0 SegBase=3D0 Kernel driver in use: pcieport --- hw/pci-bridge/gen_pcie_root_port.c | 30 ++++++++++++++++++++++++++++++ include/hw/pci/pcie_regs.h | 4 ++++ 2 files changed, 34 insertions(+) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index 452ebf69b3..035212508d 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -104,6 +104,36 @@ static void gen_rp_realize(DeviceState *dev, Error **e= rrp) } =20 uint32_t offset =3D GEN_PCIE_ROOT_PORT_ACS_END; + /* + * dvsec rme-da + * https://developer.arm.com/documentation/den0129/latest/ + * Arm RME System Architecture + * 0x0000 RMEDA_ECH See B3.2.6.2.1 RME-DA Extended Capability Header + * 0x0004 RMEDA_HEAD1 See B3.2.6.2.2 RME-DA DVSEC Header 1 + * 0x0008 RMEDA_HEAD2 See B3.2.6.2.3 RME-DA DVSEC Header 2 + * 0x000C RMEDA_CTL1 See B3.2.6.2.4 RME-DA Control register 1 + * 0x0010 RMEDA_CTL2 See B3.2.6.2.5 RME-DA Control register 2 + */ + pcie_add_capability(d, PCI_EXT_CAP_ID_DVSEC, PCI_RMEDA_VER, offset, + PCI_RMEDA_SIZEOF); + const uint32_t header1 =3D 0x010013b5; + const uint32_t header2 =3D 0xFF01; + const uint32_t ctl1 =3D 0x1; /* support tdisp */ + const uint32_t ctl2 =3D 0x0; /* unlocked */ + pci_set_long(d->config + offset + 0x4, header1); + pci_set_long(d->config + offset + 0x8, header2); + pci_set_long(d->config + offset + 0xC, ctl1); + pci_set_long(d->config + offset + 0x10, ctl2); + d->wmask[offset + 0xC] =3D 0xff; + d->wmask[offset + 0xC + 1] =3D 0xff; + d->wmask[offset + 0xC + 2] =3D 0xff; + d->wmask[offset + 0xC + 3] =3D 0xff; + d->wmask[offset + 0x10] =3D 0xff; + d->wmask[offset + 0x10 + 1] =3D 0xff; + d->wmask[offset + 0x10 + 2] =3D 0xff; + d->wmask[offset + 0x10 + 3] =3D 0xff; + offset +=3D PCI_RMEDA_SIZEOF; + pcie_ide_init(d, offset); offset +=3D PCI_IDE_SIZEOF; =20 diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index aa21177411..233378fd79 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -186,4 +186,8 @@ typedef enum PCIExpLinkWidth { #define PCI_IDE_VER 0x1 #define PCI_IDE_SIZEOF 12 =20 +/* RME-DA */ +#define PCI_RMEDA_VER 0x1 +#define PCI_RMEDA_SIZEOF 20 + #endif /* QEMU_PCIE_REGS_H */ --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Fri, 04 Sep 2026 09:05:13 -0700 (PDT) From: Jim MacArthur Date: Fri, 04 Sep 2026 17:05:04 +0100 Subject: [PATCH v2 4/4] hw/pci/msi: extract msi_message_address_register MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-jmac-rme-da-prep-v2-4-fb461d78bbb2@linaro.org> References: <20260904-jmac-rme-da-prep-v2-0-fb461d78bbb2@linaro.org> In-Reply-To: <20260904-jmac-rme-da-prep-v2-0-fb461d78bbb2@linaro.org> To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , John Snow , "Denis V. Lunev" , qemu-block@nongnu.org, Jim MacArthur , Pierrick Bouvier , Pierrick Bouvier X-Mailer: b4 0.13.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=jim.macarthur@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788537951039154100 From: Pierrick Bouvier We need to access this address from smmu, to know if we are translating an MSI. Signed-off-by: Pierrick Bouvier Signed-off-by: Jim MacArthur Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci/msi.c | 19 +++++++++++++------ include/hw/pci/msi.h | 1 + 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/hw/pci/msi.c b/hw/pci/msi.c index b9f5b45920..7361776ace 100644 --- a/hw/pci/msi.c +++ b/hw/pci/msi.c @@ -137,6 +137,18 @@ void msi_set_message(PCIDevice *dev, MSIMessage msg) pci_set_word(dev->config + msi_data_off(dev, msi64bit), msg.data); } =20 +uint64_t msi_message_address_register(PCIDevice *dev) +{ + uint16_t flags =3D pci_get_word(dev->config + msi_flags_off(dev)); + bool msi64bit =3D flags & PCI_MSI_FLAGS_64BIT; + + if (msi64bit) { + return pci_get_quad(dev->config + msi_address_lo_off(dev)); + } else { + return pci_get_long(dev->config + msi_address_lo_off(dev)); + } +} + static MSIMessage msi_prepare_message(PCIDevice *dev, unsigned int vector) { uint16_t flags =3D pci_get_word(dev->config + msi_flags_off(dev)); @@ -146,12 +158,7 @@ static MSIMessage msi_prepare_message(PCIDevice *dev, = unsigned int vector) =20 assert(vector < nr_vectors); =20 - if (msi64bit) { - msg.address =3D pci_get_quad(dev->config + msi_address_lo_off(dev)= ); - } else { - msg.address =3D pci_get_long(dev->config + msi_address_lo_off(dev)= ); - } - + msg.address =3D msi_message_address_register(dev); /* upper bit 31:16 is zero */ msg.data =3D pci_get_word(dev->config + msi_data_off(dev, msi64bit)); if (nr_vectors > 1) { diff --git a/include/hw/pci/msi.h b/include/hw/pci/msi.h index abcfd13925..6f0e02c0fb 100644 --- a/include/hw/pci/msi.h +++ b/include/hw/pci/msi.h @@ -32,6 +32,7 @@ extern bool msi_nonbroken; =20 void msi_set_message(PCIDevice *dev, MSIMessage msg); MSIMessage msi_get_message(PCIDevice *dev, unsigned int vector); +uint64_t msi_message_address_register(PCIDevice *dev); bool msi_enabled(const PCIDevice *dev); void msi_set_enabled(PCIDevice *dev); int msi_init(struct PCIDevice *dev, uint8_t offset, --=20 2.43.0