From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788414814848306.5033902057942; Wed, 2 Sep 2026 22:53:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x20NM-0006Vs-Ru; Thu, 03 Sep 2026 01:52:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x20NK-0006UF-Kd for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:52:38 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x20NI-0006Fl-Lz for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:52:38 -0400 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-cc1bc88a20eso2610042a12.3 for ; Wed, 02 Sep 2026 22:52:28 -0700 (PDT) Received: from donnager-debian.. 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Both callers pass system_memory, so there is no change in behaviour. As the controllers don't yet take a MemoryRegion the parameter is not yet passed on. Changing riscv_create_aia first avoids churn in the intermediate commits. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley Reviewed-by: Chao Liu --- hw/riscv/aia.h | 3 ++- hw/riscv/aia.c | 3 ++- hw/riscv/tt_atlantis.c | 3 ++- hw/riscv/virt.c | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/riscv/aia.h b/hw/riscv/aia.h index 3b6d7f962506..5df3292610e9 100644 --- a/hw/riscv/aia.h +++ b/hw/riscv/aia.h @@ -13,7 +13,8 @@ =20 uint32_t imsic_num_bits(uint32_t count); =20 -DeviceState *riscv_create_aia(bool msimode, int aia_guests, +DeviceState *riscv_create_aia(MemoryRegion *container, + bool msimode, int aia_guests, uint32_t m_imsic_stride, uint32_t s_imsic_stride, uint16_t num_sources, diff --git a/hw/riscv/aia.c b/hw/riscv/aia.c index c1a5982856c5..e11382e512da 100644 --- a/hw/riscv/aia.c +++ b/hw/riscv/aia.c @@ -24,7 +24,8 @@ uint32_t imsic_num_bits(uint32_t count) return ret; } =20 -DeviceState *riscv_create_aia(bool msimode, int aia_guests, +DeviceState *riscv_create_aia(MemoryRegion *container, + bool msimode, int aia_guests, uint32_t m_imsic_stride, uint32_t s_imsic_stride, uint16_t num_sources, diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 812051a11fd4..f395236d88ab 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -498,7 +498,8 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); =20 - s->irqchip =3D riscv_create_aia(true, TT_IMSIC_GUESTS, + s->irqchip =3D riscv_create_aia(system_memory, + true, TT_IMSIC_GUESTS, TT_IMSIC_STRIDE, TT_IMSIC_STRIDE, TT_IRQCHIP_NUM_SOURCES, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index de7b99c6a51e..6480a3f0a9c0 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -809,8 +809,9 @@ static void virt_machine_init(MachineState *machine) s->irqchip[i] =3D virt_create_plic(s->memmap, i, base_hartid, hart_count); } else { + bool msimode =3D s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC; int imsic_bits =3D imsic_num_bits(s->aia_guests + 1); - s->irqchip[i] =3D riscv_create_aia(s->aia_type =3D=3D VIRT_AIA= _TYPE_APLIC_IMSIC, + s->irqchip[i] =3D riscv_create_aia(system_memory, msimode, s->aia_guests, IMSIC_HART_SIZE(0), IMSIC_HART_SIZE(imsic_bits), --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788414884096229.6869468802348; Wed, 2 Sep 2026 22:54:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x20NO-0006We-AT; Thu, 03 Sep 2026 01:52:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x20NM-0006VM-8F for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:52:40 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x20NI-0006Fw-Pd for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:52:39 -0400 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-398b3d66515so2518419a91.0 for ; Wed, 02 Sep 2026 22:52:34 -0700 (PDT) Received: from donnager-debian.. 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Add a MemoryRegion parameter and map the device into it instead of calling sysbus_mmio_map(). All callers pass system_memory, so there is no change in behaviour. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- include/hw/intc/riscv_aclint.h | 7 ++++--- hw/intc/riscv_aclint.c | 12 ++++++++---- hw/riscv/cps.c | 6 ++++-- hw/riscv/k230.c | 6 ++++-- hw/riscv/microchip_pfsoc.c | 5 +++-- hw/riscv/shakti_c.c | 7 ++++--- hw/riscv/sifive_e.c | 4 ++-- hw/riscv/sifive_u.c | 7 ++++--- hw/riscv/spike.c | 4 ++-- hw/riscv/tt_atlantis.c | 3 ++- hw/riscv/virt.c | 17 +++++++++++------ hw/riscv/xiangshan_kmh.c | 6 ++++-- 12 files changed, 52 insertions(+), 32 deletions(-) diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h index 0e0b98acb08a..71d1b551a1b2 100644 --- a/include/hw/intc/riscv_aclint.h +++ b/include/hw/intc/riscv_aclint.h @@ -46,7 +46,8 @@ typedef struct RISCVAclintMTimerState { qemu_irq *timer_irqs; } RISCVAclintMTimerState; =20 -DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, +DeviceState *riscv_aclint_mtimer_create(MemoryRegion *container, + hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq, bool provide_rdtime); @@ -68,8 +69,8 @@ typedef struct RISCVAclintSwiState { qemu_irq *soft_irqs; } RISCVAclintSwiState; =20 -DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base, - uint32_t num_harts, bool sswi); +DeviceState *riscv_aclint_swi_create(MemoryRegion *container, + hwaddr addr, uint32_t hartid_base, uint32_t num_harts, bool sswi); =20 enum { RISCV_ACLINT_DEFAULT_MTIMECMP =3D 0x0, diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 361a8d1bcb45..2d133d0dcf9b 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -371,7 +371,8 @@ static const TypeInfo riscv_aclint_mtimer_info =3D { /* * Create ACLINT MTIMER device. */ -DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, +DeviceState *riscv_aclint_mtimer_create(MemoryRegion *container, + hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq, bool provide_rdtime) @@ -392,7 +393,8 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hw= addr size, qdev_prop_set_uint32(dev, "aperture-size", size); qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(container, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); @@ -556,7 +558,8 @@ static const TypeInfo riscv_aclint_swi_info =3D { /* * Create ACLINT [M|S]SWI device. */ -DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base, +DeviceState *riscv_aclint_swi_create(MemoryRegion *container, + hwaddr addr, uint32_t hartid_base, uint32_t num_harts, bool sswi) { int i; @@ -569,7 +572,8 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint3= 2_t hartid_base, qdev_prop_set_uint32(dev, "num-harts", num_harts); qdev_prop_set_uint32(dev, "sswi", sswi ? true : false); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(container, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); diff --git a/hw/riscv/cps.c b/hw/riscv/cps.c index 86172be5b3ca..5cfb54aa27d2 100644 --- a/hw/riscv/cps.c +++ b/hw/riscv/cps.c @@ -151,9 +151,11 @@ static void riscv_cps_realize(DeviceState *dev, Error = **errp) false, false, s->aplic); /* PLIC changes msi_nonbroken to ture. We revert the change. */ msi_nonbroken =3D false; - riscv_aclint_swi_create(cm_base + AIA_CLINT_OFFSET, + riscv_aclint_swi_create(get_system_memory(), + cm_base + AIA_CLINT_OFFSET, hartid_base, MAX_HARTS, false); - riscv_aclint_mtimer_create(cm_base + AIA_CLINT_OFFSET + + riscv_aclint_mtimer_create(get_system_memory(), + cm_base + AIA_CLINT_OFFSET + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, hartid_base, diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c index 558f30b97e9d..1ef4260c5391 100644 --- a/hw/riscv/k230.c +++ b/hw/riscv/k230.c @@ -196,9 +196,11 @@ static void k230_soc_realize(DeviceState *dev, Error *= *errp) s->c908_plic =3D k230_create_plic(C908_CPU_HARTID, c908_cpus); =20 /* CLINT */ - riscv_aclint_swi_create(memmap[K230_DEV_CLINT].base, + riscv_aclint_swi_create(sys_mem, + memmap[K230_DEV_CLINT].base, C908_CPU_HARTID, c908_cpus, false); - riscv_aclint_mtimer_create(memmap[K230_DEV_CLINT].base + 0x4000, + riscv_aclint_mtimer_create(sys_mem, + memmap[K230_DEV_CLINT].base + 0x4000, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, C908_CPU_HARTID, c908_cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 4017129c8304..a6026776d4de 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -250,9 +250,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *d= ev, Error **errp) memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); =20 /* CLINT */ - riscv_aclint_swi_create(memmap[MICROCHIP_PFSOC_CLINT].base, + riscv_aclint_swi_create(system_memory, + memmap[MICROCHIP_PFSOC_CLINT].base, 0, ms->smp.cpus, false); - riscv_aclint_mtimer_create( + riscv_aclint_mtimer_create(system_memory, memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 835b1f879b7f..86ff8f8fcaab 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -127,10 +127,11 @@ static void shakti_c_soc_state_realize(DeviceState *d= ev, Error **errp) SHAKTI_C_PLIC_CONTEXT_STRIDE, shakti_c_memmap[SHAKTI_C_PLIC].size); =20 - riscv_aclint_swi_create(shakti_c_memmap[SHAKTI_C_CLINT].base, + riscv_aclint_swi_create(system_memory, + shakti_c_memmap[SHAKTI_C_CLINT].base, 0, 1, false); - riscv_aclint_mtimer_create(shakti_c_memmap[SHAKTI_C_CLINT].base + - RISCV_ACLINT_SWI_SIZE, + riscv_aclint_mtimer_create(system_memory, + shakti_c_memmap[SHAKTI_C_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, 1, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 71925583bd97..0ea444f43bc5 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -225,9 +225,9 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) SIFIVE_E_PLIC_CONTEXT_BASE, SIFIVE_E_PLIC_CONTEXT_STRIDE, memmap[SIFIVE_E_DEV_PLIC].size); - riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base, + riscv_aclint_swi_create(sys_mem, memmap[SIFIVE_E_DEV_CLINT].base, 0, ms->smp.cpus, false); - riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base + + riscv_aclint_mtimer_create(sys_mem, memmap[SIFIVE_E_DEV_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 852c48c056e9..6bbf2c4504d8 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -790,10 +790,11 @@ static void sifive_u_soc_realize(DeviceState *dev, Er= ror **errp) serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ= )); sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ= )); - riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0, + riscv_aclint_swi_create(system_memory, + memmap[SIFIVE_U_DEV_CLINT].base, 0, ms->smp.cpus, false); - riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base + - RISCV_ACLINT_SWI_SIZE, + riscv_aclint_mtimer_create(system_memory, + memmap[SIFIVE_U_DEV_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, CLINT_TIMEBASE_FREQ, false); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 8d7e93807c06..c0c22d639f17 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -167,10 +167,10 @@ static void spike_board_init(MachineState *machine) sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); =20 /* Core Local Interruptor (timer and IPI) for each socket */ - riscv_aclint_swi_create( + riscv_aclint_swi_create(system_memory, memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, base_hartid, hart_count, false); - riscv_aclint_mtimer_create( + riscv_aclint_mtimer_create(system_memory, memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index f395236d88ab..373d4dabf3a4 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -511,7 +511,8 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) TT_IRQCHIP_NUM_MSIS, TT_IRQCHIP_NUM_PRIO_BITS); =20 - riscv_aclint_mtimer_create(s->memmap[TT_ATL_ACLINT].base, + riscv_aclint_mtimer_create(system_memory, + s->memmap[TT_ATL_ACLINT].base, TT_ACLINT_MTIME_SIZE, 0, hart_count, TT_ACLINT_MTIMECMP, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6480a3f0a9c0..8fd742181e28 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -768,7 +768,8 @@ static void virt_machine_init(MachineState *machine) if (virt_aclint_allowed() && s->have_aclint) { if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { /* Per-socket ACLINT MTIMER */ - riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + + riscv_aclint_mtimer_create(system_memory, + s->memmap[VIRT_CLINT].base + i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, @@ -777,10 +778,12 @@ static void virt_machine_init(MachineState *machine) RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); } else { /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ - riscv_aclint_swi_create(s->memmap[VIRT_CLINT].base + + riscv_aclint_swi_create(system_memory, + s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size, base_hartid, hart_count, false); - riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + + riscv_aclint_mtimer_create(system_memory, + s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, @@ -788,16 +791,18 @@ static void virt_machine_init(MachineState *machine) RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); - riscv_aclint_swi_create(s->memmap[VIRT_ACLINT_SSWI].base + + riscv_aclint_swi_create(system_memory, + s->memmap[VIRT_ACLINT_SSWI].base + i * s->memmap[VIRT_ACLINT_SSWI].size, base_hartid, hart_count, true); } } else if (tcg_enabled()) { /* Per-socket SiFive CLINT */ - riscv_aclint_swi_create( + riscv_aclint_swi_create(system_memory, s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT]= .size, base_hartid, hart_count, false); - riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + + riscv_aclint_mtimer_create(system_memory, + s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_co= unt, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MT= IME, diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index 384624d69ad5..94f9d02a00b9 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -116,9 +116,11 @@ static void xiangshan_kmh_soc_realize(DeviceState *dev= , Error **errp) 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); =20 /* CLINT */ - riscv_aclint_swi_create(memmap[XIANGSHAN_KMH_CLINT].base, + riscv_aclint_swi_create(system_memory, + memmap[XIANGSHAN_KMH_CLINT].base, 0, num_harts, false); - riscv_aclint_mtimer_create(memmap[XIANGSHAN_KMH_CLINT].base + + riscv_aclint_mtimer_create(system_memory, + memmap[XIANGSHAN_KMH_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, num_harts, RISCV_ACLINT_DEFAULT_MTIMECMP, --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Add a MemoryRegion parameter and map the device into it instead of calling sysbus_mmio_map(). All callers pass system_memory, so there is no change in behaviour. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- include/hw/intc/riscv_imsic.h | 3 ++- hw/intc/riscv_imsic.c | 6 ++++-- hw/riscv/aia.c | 6 ++++-- hw/riscv/xiangshan_kmh.c | 5 +++-- 4 files changed, 13 insertions(+), 7 deletions(-) diff --git a/include/hw/intc/riscv_imsic.h b/include/hw/intc/riscv_imsic.h index fae999731dff..0a1df1c2f8d6 100644 --- a/include/hw/intc/riscv_imsic.h +++ b/include/hw/intc/riscv_imsic.h @@ -62,7 +62,8 @@ struct RISCVIMSICState { uint32_t num_irqs; }; =20 -DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, +DeviceState *riscv_imsic_create(MemoryRegion *container, hwaddr addr, + uint32_t hartid, bool mmode, uint32_t num_pages, uint32_t num_ids); =20 #endif diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index d6b46cdca220..cb9ce9612cff 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -495,7 +495,8 @@ type_init(riscv_imsic_register_types) /* * Create IMSIC device. */ -DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, +DeviceState *riscv_imsic_create(MemoryRegion *container, hwaddr addr, + uint32_t hartid, bool mmode, uint32_t num_pages, uint32_t num_ids) { DeviceState *dev =3D qdev_new(TYPE_RISCV_IMSIC); @@ -518,7 +519,8 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t h= artid, bool mmode, qdev_prop_set_uint32(dev, "num-irqs", num_ids + 1); =20 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(container, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 if (!kvm_irqchip_in_kernel()) { for (i =3D 0; i < num_pages; i++) { diff --git a/hw/riscv/aia.c b/hw/riscv/aia.c index e11382e512da..eae7638f972b 100644 --- a/hw/riscv/aia.c +++ b/hw/riscv/aia.c @@ -53,7 +53,8 @@ DeviceState *riscv_create_aia(MemoryRegion *container, /* Per-socket M-level IMSICs */ addr =3D imsic_m->base + socket * (1U << IMSIC_MMIO_GROUP_MIN_= SHIFT); for (i =3D 0; i < hart_count; i++) { - riscv_imsic_create(addr + i * m_imsic_stride, + riscv_imsic_create(container, + addr + i * m_imsic_stride, base_hartid + i, true, 1, num_msis); } @@ -62,7 +63,8 @@ DeviceState *riscv_create_aia(MemoryRegion *container, /* Per-socket S-level IMSICs */ addr =3D imsic_s->base + socket * (1U << IMSIC_MMIO_GROUP_MIN_SHIF= T); for (i =3D 0; i < hart_count; i++) { - riscv_imsic_create(addr + i * s_imsic_stride, + riscv_imsic_create(container, + addr + i * s_imsic_stride, base_hartid + i, false, 1 + aia_guests, num_msis); } diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index 94f9d02a00b9..9eb608f8c578 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -65,14 +65,15 @@ static DeviceState *xiangshan_kmh_create_aia(uint32_t n= um_harts) /* M-level IMSICs */ addr =3D memmap[XIANGSHAN_KMH_IMSIC_M].base; for (i =3D 0; i < num_harts; i++) { - riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), i, true, + riscv_imsic_create(get_system_memory(), + addr + i * IMSIC_HART_SIZE(0), i, true, 1, XIANGSHAN_KMH_IMSIC_NUM_IDS); } =20 /* S-level IMSICs */ addr =3D memmap[XIANGSHAN_KMH_IMSIC_S].base; for (i =3D 0; i < num_harts; i++) { - riscv_imsic_create(addr + + riscv_imsic_create(get_system_memory(), addr + i * IMSIC_HART_SIZE(XIANGSHAN_KMH_IMSIC_GUEST_B= ITS), i, false, 1 + XIANGSHAN_KMH_IMSIC_GUEST_BITS, XIANGSHAN_KMH_IMSIC_NUM_IDS); --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788414834845465.5971032286676; Wed, 2 Sep 2026 22:53:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x20NW-0006YA-3l; Thu, 03 Sep 2026 01:52:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x20NU-0006Xe-T1 for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:52:48 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x20NT-0006MO-02 for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:52:48 -0400 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-39927410578so3482459a91.1 for ; Wed, 02 Sep 2026 22:52:46 -0700 (PDT) Received: from donnager-debian.. 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Add a MemoryRegion parameter and map the device into it instead of calling sysbus_mmio_map(). The mapping still only happens when the APLIC is emulated. All callers pass system_memory, so there is no change in behaviour. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley --- include/hw/intc/riscv_aplic.h | 7 ++++--- hw/intc/riscv_aplic.c | 10 ++++++---- hw/riscv/aia.c | 8 ++++---- hw/riscv/cps.c | 6 ++++-- hw/riscv/xiangshan_kmh.c | 6 ++++-- 5 files changed, 22 insertions(+), 15 deletions(-) diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h index c7a4d4ad0172..62d2b33ade61 100644 --- a/include/hw/intc/riscv_aplic.h +++ b/include/hw/intc/riscv_aplic.h @@ -80,8 +80,9 @@ bool riscv_is_kvm_aia_aplic_imsic(bool msimode); bool riscv_use_emulated_aplic(bool msimode); void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr); =20 -DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, - uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, - uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent); +DeviceState *riscv_aplic_create(MemoryRegion *container, + hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, + uint32_t num_sources, uint32_t iprio_bits, bool msimode, bool mmode, + DeviceState *parent); =20 #endif diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 84606e9f3d88..d8e25bfda14b 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -1109,9 +1109,10 @@ void riscv_aplic_add_child(DeviceState *parent, Devi= ceState *child) /* * Create APLIC device. */ -DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, - uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, - uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent) +DeviceState *riscv_aplic_create(MemoryRegion *container, + hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, + uint32_t num_sources, uint32_t iprio_bits, bool msimode, bool mmode, + DeviceState *parent) { DeviceState *dev =3D qdev_new(TYPE_RISCV_APLIC); uint32_t i; @@ -1137,7 +1138,8 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr s= ize, sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 if (riscv_use_emulated_aplic(msimode)) { - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(container, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 if (!msimode) { for (i =3D 0; i < num_harts; i++) { diff --git a/hw/riscv/aia.c b/hw/riscv/aia.c index eae7638f972b..56fc06453321 100644 --- a/hw/riscv/aia.c +++ b/hw/riscv/aia.c @@ -72,8 +72,8 @@ DeviceState *riscv_create_aia(MemoryRegion *container, =20 if (!kvm_enabled()) { /* Per-socket M-level APLIC */ - aplic_m_dev =3D riscv_aplic_create(aplic_m->base + - socket * aplic_m->size, + aplic_m_dev =3D riscv_aplic_create(container, + aplic_m->base + socket * aplic_m->siz= e, aplic_m->size, (msimode) ? 0 : base_hartid, (msimode) ? 0 : hart_count, @@ -83,8 +83,8 @@ DeviceState *riscv_create_aia(MemoryRegion *container, } =20 /* Per-socket S-level APLIC */ - aplic_s_dev =3D riscv_aplic_create(aplic_s->base + - socket * aplic_s->size, + aplic_s_dev =3D riscv_aplic_create(container, + aplic_s->base + socket * aplic_s->size, aplic_s->size, (msimode) ? 0 : base_hartid, (msimode) ? 0 : hart_count, diff --git a/hw/riscv/cps.c b/hw/riscv/cps.c index 5cfb54aa27d2..d2fd9638a08d 100644 --- a/hw/riscv/cps.c +++ b/hw/riscv/cps.c @@ -135,14 +135,16 @@ static void riscv_cps_realize(DeviceState *dev, Error= **errp) for (i =3D 0; i < num_of_clusters; i++) { uint64_t cm_base =3D GLOBAL_CM_BASE + (CM_SIZE * i); uint32_t hartid_base =3D i << MHARTID_CLUSTER_SHIFT; - s->aplic =3D riscv_aplic_create(cm_base + AIA_PLIC_M_OFFSET, + s->aplic =3D riscv_aplic_create(get_system_memory(), + cm_base + AIA_PLIC_M_OFFSET, AIA_PLIC_M_SIZE, hartid_base, /* hartid_base */ MAX_HARTS, /* num_harts */ APLIC_NUM_SOURCES, APLIC_NUM_PRIO_BITS, false, true, NULL); - riscv_aplic_create(cm_base + AIA_PLIC_S_OFFSET, + riscv_aplic_create(get_system_memory(), + cm_base + AIA_PLIC_S_OFFSET, AIA_PLIC_S_SIZE, hartid_base, /* hartid_base */ MAX_HARTS, /* num_harts */ diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index 9eb608f8c578..c5a654ab417d 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -80,13 +80,15 @@ static DeviceState *xiangshan_kmh_create_aia(uint32_t n= um_harts) } =20 /* M-level APLIC */ - aplic_m =3D riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_M].base, + aplic_m =3D riscv_aplic_create(get_system_memory(), + memmap[XIANGSHAN_KMH_APLIC_M].base, memmap[XIANGSHAN_KMH_APLIC_M].size, 0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES, 1, true, true, NULL); =20 /* S-level APLIC */ - riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_S].base, + riscv_aplic_create(get_system_memory(), + memmap[XIANGSHAN_KMH_APLIC_S].base, memmap[XIANGSHAN_KMH_APLIC_S].size, 0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES, 1, true, false, aplic_m); --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788414810568484.6891556751126; Wed, 2 Sep 2026 22:53:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x20Ne-0006Zd-H1; Thu, 03 Sep 2026 01:52:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x20Nb-0006Yz-8j for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:52:55 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x20NZ-0006Mp-D4 for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:52:55 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-85377c8bc96so2203690b3a.3 for ; Wed, 02 Sep 2026 22:52:52 -0700 (PDT) Received: from donnager-debian.. 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Add a MemoryRegion parameter and map the device into it instead of calling sysbus_mmio_map(). All callers pass system_memory, so there is no change in behaviour. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley Reviewed-by: Chao Liu --- include/hw/intc/sifive_plic.h | 4 ++-- hw/intc/sifive_plic.c | 7 ++++--- hw/riscv/k230.c | 3 ++- hw/riscv/microchip_pfsoc.c | 3 ++- hw/riscv/shakti_c.c | 3 ++- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 3 ++- hw/riscv/virt.c | 1 + 8 files changed, 16 insertions(+), 10 deletions(-) diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h index 32973dbf281e..064754c3f628 100644 --- a/include/hw/intc/sifive_plic.h +++ b/include/hw/intc/sifive_plic.h @@ -76,8 +76,8 @@ struct SiFivePLICState { qemu_irq *s_external_irqs; }; =20 -DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, - uint32_t num_harts, +DeviceState *sifive_plic_create(MemoryRegion *container, + hwaddr addr, char *hart_config, uint32_t num_harts, uint32_t hartid_base, uint32_t num_sources, uint32_t num_priorities, uint32_t priority_base, uint32_t pending_base, uint32_t enable_base, diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 9c84ff06a9fd..90f17e6ee724 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -473,8 +473,8 @@ type_init(sifive_plic_register_types) /* * Create PLIC device. */ -DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, - uint32_t num_harts, +DeviceState *sifive_plic_create(MemoryRegion *container, + hwaddr addr, char *hart_config, uint32_t num_harts, uint32_t hartid_base, uint32_t num_sources, uint32_t num_priorities, uint32_t priority_base, uint32_t pending_base, uint32_t enable_base, @@ -499,7 +499,8 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart= _config, qdev_prop_set_uint32(dev, "context-stride", context_stride); qdev_prop_set_uint32(dev, "aperture-size", aperture_size); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(container, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 plic =3D SIFIVE_PLIC(dev); =20 diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c index 1ef4260c5391..6b0f0453c80b 100644 --- a/hw/riscv/k230.c +++ b/hw/riscv/k230.c @@ -134,7 +134,8 @@ static DeviceState *k230_create_plic(int base_hartid, i= nt hartid_count) plic_hart_config =3D riscv_plic_hart_config_string(hartid_count); =20 /* Per-socket PLIC */ - return sifive_plic_create(memmap[K230_DEV_PLIC].base, + return sifive_plic_create(get_system_memory(), + memmap[K230_DEV_PLIC].base, plic_hart_config, hartid_count, base_hartid, K230_PLIC_NUM_SOURCES, K230_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index a6026776d4de..1f6d9f5ae1ed 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -282,7 +282,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *de= v, Error **errp) plic_hart_config =3D riscv_plic_hart_config_string(ms->smp.cpus); =20 /* PLIC */ - s->plic =3D sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, + s->plic =3D sifive_plic_create(system_memory, + memmap[MICROCHIP_PFSOC_PLIC].base, plic_hart_config, ms->smp.cpus, 0, MICROCHIP_PFSOC_PLIC_NUM_SOURCES, MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 86ff8f8fcaab..62052bf7c61e 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -115,7 +115,8 @@ static void shakti_c_soc_state_realize(DeviceState *dev= , Error **errp) =20 sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort); =20 - sss->plic =3D sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base, + sss->plic =3D sifive_plic_create(system_memory, + shakti_c_memmap[SHAKTI_C_PLIC].base, (char *)SHAKTI_C_PLIC_HART_CONFIG, ms->smp.cpus, 0, SHAKTI_C_PLIC_NUM_SOURCES, SHAKTI_C_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 0ea444f43bc5..81d7995ddcfb 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -214,7 +214,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom); =20 /* MMIO */ - s->plic =3D sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, + s->plic =3D sifive_plic_create(sys_mem, memmap[SIFIVE_E_DEV_PLIC].base, (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0, SIFIVE_E_PLIC_NUM_SOURCES, SIFIVE_E_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6bbf2c4504d8..632194a06ea1 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -774,7 +774,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) plic_hart_config =3D riscv_plic_hart_config_string(ms->smp.cpus); =20 /* MMIO */ - s->plic =3D sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, + s->plic =3D sifive_plic_create(system_memory, + memmap[SIFIVE_U_DEV_PLIC].base, plic_hart_config, ms->smp.cpus, 0, SIFIVE_U_PLIC_NUM_SOURCES, SIFIVE_U_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 8fd742181e28..a7b5af4e4c88 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -561,6 +561,7 @@ static DeviceState *virt_create_plic(const MemMapEntry = *memmap, int socket, =20 /* Per-socket PLIC */ return sifive_plic_create( + get_system_memory(), memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, plic_hart_config, hart_count, base_hartid, VIRT_IRQCHIP_NUM_SOURCES, --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Pass the container memory region to the interrupt controller helpers so all CPS devices live in the container. The location of devices in memory for the boston-aia machine is unchanged. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley --- hw/riscv/cps.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/cps.c b/hw/riscv/cps.c index d2fd9638a08d..21daaf4943d8 100644 --- a/hw/riscv/cps.c +++ b/hw/riscv/cps.c @@ -135,7 +135,7 @@ static void riscv_cps_realize(DeviceState *dev, Error *= *errp) for (i =3D 0; i < num_of_clusters; i++) { uint64_t cm_base =3D GLOBAL_CM_BASE + (CM_SIZE * i); uint32_t hartid_base =3D i << MHARTID_CLUSTER_SHIFT; - s->aplic =3D riscv_aplic_create(get_system_memory(), + s->aplic =3D riscv_aplic_create(&s->container, cm_base + AIA_PLIC_M_OFFSET, AIA_PLIC_M_SIZE, hartid_base, /* hartid_base */ @@ -143,7 +143,7 @@ static void riscv_cps_realize(DeviceState *dev, Error *= *errp) APLIC_NUM_SOURCES, APLIC_NUM_PRIO_BITS, false, true, NULL); - riscv_aplic_create(get_system_memory(), + riscv_aplic_create(&s->container, cm_base + AIA_PLIC_S_OFFSET, AIA_PLIC_S_SIZE, hartid_base, /* hartid_base */ @@ -153,10 +153,10 @@ static void riscv_cps_realize(DeviceState *dev, Error= **errp) false, false, s->aplic); /* PLIC changes msi_nonbroken to ture. We revert the change. */ msi_nonbroken =3D false; - riscv_aclint_swi_create(get_system_memory(), + riscv_aclint_swi_create(&s->container, cm_base + AIA_CLINT_OFFSET, hartid_base, MAX_HARTS, false); - riscv_aclint_mtimer_create(get_system_memory(), + riscv_aclint_mtimer_create(&s->container, cm_base + AIA_CLINT_OFFSET + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788414902881770.6612846637806; Wed, 2 Sep 2026 22:55:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x20Nt-0006he-Qx; Thu, 03 Sep 2026 01:53:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x20Nl-0006ad-Oh for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:05 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x20Nk-0006Sg-7j for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:05 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-84e27035206so1789537b3a.3 for ; Wed, 02 Sep 2026 22:53:03 -0700 (PDT) Received: from donnager-debian.. ([180.150.112.50]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1431990a39bsm2770619c88.3.2026.09.02.22.52.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 22:53:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788414783; x=1789019583; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:sender:from:to:cc :subject:date:message-id:reply-to:content-type; bh=+s6fEopBsd7ppapT8KmLn2uzOdAaKJBsOus7rTyRoiQ=; b=BUwzsxNFQkASONZA9oUyKAChshn/LlUK8DdDaype+ejB9me3Ozv8Ve0j6wTyIAFyBW Ftu5uJx8POraCNlBpSOilitDlk21rMBMaIjRojZIYCifZbjZAPeD6pdeO573tpj2m0LZ OT88FuWH3Q+YOWf+k75S5X3VIRONRQVPCigZ+ZIyuyaQYbNfyIgxm80COq7mKb9DadUR 0uoedgdZMUShGCGiVpc8vBsrir78rlr42BvuUjJoP9RFQCmbSqc2gbtB4EXNDVyNyfH3 /TXKVLjp0MlTNF2g6CvwFdD4QlWGwJRltnxfqJdJeALLGNDGVeicKS0Lh2WdF/+kSQdC wLgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788414783; x=1789019583; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:sender:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=+s6fEopBsd7ppapT8KmLn2uzOdAaKJBsOus7rTyRoiQ=; b=cL+0v1Iq+qthVvwajlKeg/46XkUi7gojjhBVTkTY2NANihfWfQFimlSHPZijjEq0lI OXR3M1pfTfPGAffTxiOslakR4atESSLjoMSvUj0E9SLd2VpVnzrYwlHfiaRWfGv5oBs+ ICW8Bd3Lm2YKDAwr8iPLnylJQF/2oUV2TPmXIB9KJItUWMKhey2OVv0XH4IJh8mR3r6O knh8lUHvGn/UrlCPb1Z2z5EoKnCJqnbpfNxPyfkxGNFnSeAX4p8lrTGY8pxyAhg08JGJ 9XaPqKQMS42XJsX8K5Kv7pL/ewGePnJDn1Hx9hphfhW3wHIrrGAfhY0YiwSfZOwnYzD3 9eGQ== X-Forwarded-Encrypted: i=1; AKwUvBzSATbUgDBKva95Ige1hwuyi4kChkKn0KVp/qIH+/64PGdSt0GZi2SHR8w0+Ps+y7peL2TzSeX/4mst@nongnu.org X-Gm-Message-State: AFuF++mxqCNB7guQWS8faKdJyL11GR4UJ7qvq/mNCgTPzFSr1O+E3DFz CeSEqbS7IyiNjEHImQh2/Tgj0F3kt6JbcmX6Q7g9qLJxRf5ZbbCrbEC+ X-Gm-Gg: AYBFou0+X2V2gvfQXuNgGhssmSD/+VtWyGd16nDxthY4qIvf75DYP88U8Ey5Xjg4XM0 OT4CYf0ISJ4z2QPJAlNd1bqWZNaALrDzUgBGqZpzXOmwswmbsAWtf5mPP6EPkhDwOFBtkwdDITs fD6OPgKFXbaUpafgPsEzj/enAr3u4avJoFQcY9RE5i8SsZR+an1v23xYuEAQaldVRlci5dUAY9B Svn/0GKVI3BtvdcZU/6cV7ylHrMQjEWIbhhhYWFZeheBaSmnkFIPx5IfaSn2AgVgT4Mfdtyq2jC 01jXGQTY90Qwq+dqGSagXRnUvhC/HMdgFFrEfWZCLtk0Jp9gnMCXTFk49jvymhTf+4CE4eJKV4C 2VNPpm/Umd/0mpDyqaAISxuLUGT3huBVbHDNkK3Vzkkxi7E3VGXs5+dQAC5+qxLlb5igT3BXy1U 9RR4BMqpXW2v1k8wigIGI2a0ZWR59DaMnndSY0Gs4C6CImFpT0dUWQ0FinOwa1T8DQiVX/3hw4s 9QK03zGm0MowZS50ySzoUf3BhBbuRsm3QrSch9Q27uxlxoy7/0oIokO5JxkGX8FGtQlWfObTy95 R92nC/yP+NOp7MAQoRV8OlP9ZS+jlZw= X-Received: by 2002:a05:6a20:9381:b0:3c3:7179:a640 with SMTP id adf61e73a8af0-3d9adabade4mr14397385637.3.1788414782660; Wed, 02 Sep 2026 22:53:02 -0700 (PDT) From: Joel Stanley To: Alistair Francis , Daniel Henrique Barboza Cc: Weiwei Li , Liu Zhiwei , Chao Liu , Nicholas Piggin , Anirudh Srinivasan , Michael Ellerman , Portia Stephens , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 07/16] hw/riscv/atlantis: Make UART unimp region a SoC device Date: Thu, 3 Sep 2026 15:21:21 +0930 Message-ID: <20260903055131.257903-8-joel@jms.id.au> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260903055131.257903-1-joel@jms.id.au> References: <20260903055131.257903-1-joel@jms.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=joel.stan@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1788414903327158500 Make the unimplemented region covering the remainder of the console UART's register space a SoC child device, mapped using a helper. This makes it easier to map it into the SoC's memory container along with the other devices in the future. While here, rename the region from uart0 to uart1. The uart0 name was a leftover from an earlier revision that used a different device for the console. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- include/hw/riscv/tt_atlantis.h | 2 ++ hw/riscv/tt_atlantis.c | 19 ++++++++++++++++--- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 7f7d4a5a5905..c9308aa57017 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -13,6 +13,7 @@ #include "hw/core/sysbus.h" #include "hw/i2c/designware_i2c.h" #include "hw/intc/riscv_imsic.h" +#include "hw/misc/unimp.h" #include "hw/riscv/riscv_hart.h" =20 #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") @@ -31,6 +32,7 @@ struct TTAtlantisState { RISCVHartArrayState soc; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; + UnimplementedDeviceState uart1; =20 int fdt_size; }; diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 373d4dabf3a4..a2fb83aab78e 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -411,6 +411,17 @@ static void load_fdt(TTAtlantisState *s) create_fdt_memory(s); } =20 +static void mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, + const char *name, hwaddr addr, uint64_t= size) +{ + qdev_prop_set_string(DEVICE(dev), "name", name); + qdev_prop_set_uint64(DEVICE(dev), "size", size); + sysbus_realize(dev, &error_abort); + + memory_region_add_subregion_overlap(memory, addr, + sysbus_mmio_get_region(dev, 0), -1= 000); +} + static void tt_atlantis_machine_done(Notifier *notifier, void *data) { TTAtlantisState *s =3D container_of(notifier, TTAtlantisState, machine= _done); @@ -562,9 +573,11 @@ static void tt_atlantis_machine_init(MachineState *mac= hine) * Create an unimplemented device region so writes don't fault * and reads return zero, which keeps Linux happy. */ - create_unimplemented_device("tt-atlantis.uart0", - s->memmap[TT_ATL_UART1].base, - s->memmap[TT_ATL_UART1].size); + object_initialize_child(OBJECT(s), "uart1", &s->uart1, + TYPE_UNIMPLEMENTED_DEVICE); + mmio_map_unimplemented(system_memory, SYS_BUS_DEVICE(&s->uart1), + "tt-atlantis.uart1", s->memmap[TT_ATL_UART1].ba= se, + s->memmap[TT_ATL_UART1].size); =20 /* I2C */ for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788414855173817.7111401588987; Wed, 2 Sep 2026 22:54:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x20Ny-0006kL-7d; Thu, 03 Sep 2026 01:53:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x20Nr-0006hi-VG for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:13 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x20Np-0006TP-Q3 for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:10 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-cc1d57602e8so2059750a12.3 for ; Wed, 02 Sep 2026 22:53:09 -0700 (PDT) Received: from donnager-debian.. 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Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- include/hw/riscv/tt_atlantis.h | 2 -- hw/riscv/tt_atlantis.c | 9 +++++---- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index c9308aa57017..d0cca3b02424 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -33,8 +33,6 @@ struct TTAtlantisState { DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; - - int fdt_size; }; =20 enum { diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index a2fb83aab78e..7d31294ea1fb 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -367,10 +367,10 @@ static void finalize_fdt(TTAtlantisState *s) static void create_fdt(TTAtlantisState *s) { MachineState *ms =3D MACHINE(s); + int fdt_size =3D 0; =20 - ms->fdt =3D riscv_create_board_device_tree( - "Tenstorrent Atlantis RISC-V Machine", - "tenstorrent,atlantis", &s->fdt_size); + ms->fdt =3D riscv_create_board_device_tree("Tenstorrent Atlantis RISC-= V Machine", + "tenstorrent,atlantis", &fdt_= size); =20 qemu_fdt_add_subnode(ms->fdt, "/chosen"); =20 @@ -386,8 +386,9 @@ static void load_fdt(TTAtlantisState *s) MachineState *ms =3D MACHINE(s); char **node_path; Error *err =3D NULL; + int fdt_size =3D 0; =20 - ms->fdt =3D load_device_tree(ms->dtb, &s->fdt_size); + ms->fdt =3D load_device_tree(ms->dtb, &fdt_size); if (!ms->fdt) { error_report("load_device_tree() failed"); exit(1); --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788414888023535.0689521243147; Wed, 2 Sep 2026 22:54:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x20O2-0006nX-0G; Thu, 03 Sep 2026 01:53:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x20Ny-0006kR-2Q for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:18 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x20Nw-0006To-8w for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:17 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-8485b358552so1773625b3a.2 for ; Wed, 02 Sep 2026 22:53:14 -0700 (PDT) Received: from donnager-debian.. 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Use cpus instead as an accurate description of the hart array. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley --- include/hw/riscv/tt_atlantis.h | 2 +- hw/riscv/tt_atlantis.c | 34 +++++++++++++++++----------------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index d0cca3b02424..642490d21743 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -29,7 +29,7 @@ struct TTAtlantisState { Notifier machine_done; const MemMapEntry *memmap; =20 - RISCVHartArrayState soc; + RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 7d31294ea1fb..80300a18a4ab 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -113,13 +113,13 @@ static void create_fdt_aclint(TTAtlantisState *s, uin= t32_t *intc_phandles) uint32_t aclint_cells_size; hwaddr addr; =20 - aclint_mtimer_cells =3D g_new0(uint32_t, s->soc.num_harts * 2); + aclint_mtimer_cells =3D g_new0(uint32_t, s->cpus.num_harts * 2); =20 - for (int cpu =3D 0; cpu < s->soc.num_harts; cpu++) { + for (int cpu =3D 0; cpu < s->cpus.num_harts; cpu++) { aclint_mtimer_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu= ]); aclint_mtimer_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_TIMER); } - aclint_cells_size =3D s->soc.num_harts * sizeof(uint32_t) * 2; + aclint_cells_size =3D s->cpus.num_harts * sizeof(uint32_t) * 2; =20 addr =3D s->memmap[TT_ATL_ACLINT].base; =20 @@ -211,7 +211,7 @@ static void create_fdt_pmu(TTAtlantisState *s) { char pmu_name[] =3D "/pmu"; void *fdt =3D MACHINE(s)->fdt; - RISCVCPU *hart =3D &s->soc.harts[0]; + RISCVCPU *hart =3D &s->cpus.harts[0]; =20 qemu_fdt_add_subnode(fdt, pmu_name); qemu_fdt_setprop_string(fdt, pmu_name, "compatible", "riscv,pmu"); @@ -228,8 +228,8 @@ static void create_fdt_cpu(TTAtlantisState *s, const Me= mMapEntry *memmap, =20 riscv_fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); =20 - riscv_create_fdt_socket_cpus(fdt, s->soc.harts, 0, s->soc.num_harts, - s->soc.hartid_base, &fdt_phandle, + riscv_create_fdt_socket_cpus(fdt, s->cpus.harts, 0, s->cpus.num_harts, + s->cpus.hartid_base, &fdt_phandle, intc_phandles, false, false); =20 create_fdt_memory(s); @@ -253,13 +253,13 @@ static void create_fdt_cpu(TTAtlantisState *s, const = MemMapEntry *memmap, create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_MAPLIC], msi_m_phandle, intc_phandles, aplic_m_phandle, aplic_s_phandle, - IRQ_M_EXT, s->soc.num_harts); + IRQ_M_EXT, s->cpus.num_harts); =20 /* S-level APLIC node */ create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_SAPLIC], imsic_s_phandle, intc_phandles, aplic_s_phandle, 0, - IRQ_S_EXT, s->soc.num_harts); + IRQ_S_EXT, s->cpus.num_harts); } =20 static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, @@ -430,7 +430,7 @@ static void tt_atlantis_machine_done(Notifier *notifier= , void *data) hwaddr start_addr =3D s->memmap[TT_ATL_DDR_LO].base; hwaddr mem_size; target_ulong firmware_end_addr, kernel_start_addr; - const char *firmware_name =3D riscv_default_firmware_name(&s->soc); + const char *firmware_name =3D riscv_default_firmware_name(&s->cpus); uint64_t fdt_load_addr; uint64_t kernel_entry; RISCVBootInfo boot_info; @@ -447,7 +447,7 @@ static void tt_atlantis_machine_done(Notifier *notifier= , void *data) if (mem_size > s->memmap[TT_ATL_DDR_LO].size) { mem_size =3D s->memmap[TT_ATL_DDR_LO].size; } - riscv_boot_info_init_discontig_mem(&boot_info, &s->soc, + riscv_boot_info_init_discontig_mem(&boot_info, &s->cpus, s->memmap[TT_ATL_DDR_LO].base, mem_size); =20 @@ -477,7 +477,7 @@ static void tt_atlantis_machine_done(Notifier *notifier= , void *data) riscv_load_fdt(fdt_load_addr, machine->fdt); =20 /* load the reset vector */ - riscv_setup_rom_reset_vec(machine, &s->soc, start_addr, + riscv_setup_rom_reset_vec(machine, &s->cpus, start_addr, s->memmap[TT_ATL_BOOTROM].base, s->memmap[TT_ATL_BOOTROM].size, kernel_entry, @@ -497,18 +497,18 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) =20 s->memmap =3D tt_atlantis_memmap; =20 - object_initialize_child(OBJECT(machine), "soc", &s->soc, + object_initialize_child(OBJECT(machine), "soc", &s->cpus, TYPE_RISCV_HART_ARRAY); - object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, + object_property_set_str(OBJECT(&s->cpus), "cpu-type", machine->cpu_typ= e, &error_abort); - object_property_set_int(OBJECT(&s->soc), "hartid-base", 0, + object_property_set_int(OBJECT(&s->cpus), "hartid-base", 0, &error_abort); - object_property_set_int(OBJECT(&s->soc), "num-harts", hart_count, + object_property_set_int(OBJECT(&s->cpus), "num-harts", hart_count, &error_abort); - object_property_set_int(OBJECT(&s->soc), "resetvec", + object_property_set_int(OBJECT(&s->cpus), "resetvec", s->memmap[TT_ATL_BOOTROM].base, &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); =20 s->irqchip =3D riscv_create_aia(system_memory, true, TT_IMSIC_GUESTS, --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fix this for the device tree pointer by passing it directly to the functions that use it, instead of casting the TTAtlantisState to a MachineState. MachineState::smp.cpus is replaced with TTAtlantisState::cpus.num_harts, as these are equivalent after tt_atlantis_machine_init. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley --- hw/riscv/tt_atlantis.c | 51 +++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 80300a18a4ab..f2a4a051d1f6 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -80,9 +80,8 @@ static uint32_t next_phandle(void) return fdt_phandle++; } =20 -static void create_fdt_memory(TTAtlantisState *s) +static void create_fdt_memory(void *fdt, TTAtlantisState *s) { - void *fdt =3D MACHINE(s)->fdt; hwaddr size_lo =3D MACHINE(s)->ram_size; hwaddr size_hi =3D 0; =20 @@ -105,9 +104,9 @@ static void create_fdt_memory(TTAtlantisState *s) } } =20 -static void create_fdt_aclint(TTAtlantisState *s, uint32_t *intc_phandles) +static void create_fdt_aclint(void *fdt, TTAtlantisState *s, + uint32_t *intc_phandles) { - void *fdt =3D MACHINE(s)->fdt; g_autofree char *name =3D NULL; g_autofree uint32_t *aclint_mtimer_cells =3D NULL; uint32_t aclint_cells_size; @@ -207,10 +206,9 @@ static void create_fdt_one_aplic(void *fdt, qemu_fdt_setprop_cell(fdt, name, "phandle", aplic_phandle); } =20 -static void create_fdt_pmu(TTAtlantisState *s) +static void create_fdt_pmu(void *fdt, TTAtlantisState *s) { char pmu_name[] =3D "/pmu"; - void *fdt =3D MACHINE(s)->fdt; RISCVCPU *hart =3D &s->cpus.harts[0]; =20 qemu_fdt_add_subnode(fdt, pmu_name); @@ -218,32 +216,29 @@ static void create_fdt_pmu(TTAtlantisState *s) riscv_pmu_generate_fdt_node(fdt, hart->pmu_avail_ctrs, pmu_name); } =20 -static void create_fdt_cpu(TTAtlantisState *s, const MemMapEntry *memmap, +static void create_fdt_cpu(void *fdt, TTAtlantisState *s, uint32_t aplic_s_phandle, uint32_t imsic_s_phandle) { - MachineState *ms =3D MACHINE(s); - void *fdt =3D MACHINE(s)->fdt; - g_autofree uint32_t *intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); + g_autofree uint32_t *intc_phandles =3D g_new0(uint32_t, s->cpus.num_ha= rts); + int num_harts =3D s->cpus.num_harts; =20 riscv_fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); =20 - riscv_create_fdt_socket_cpus(fdt, s->cpus.harts, 0, s->cpus.num_harts, + riscv_create_fdt_socket_cpus(fdt, s->cpus.harts, 0, num_harts, s->cpus.hartid_base, &fdt_phandle, intc_phandles, false, false); =20 - create_fdt_memory(s); - - create_fdt_aclint(s, intc_phandles); + create_fdt_aclint(fdt, s, intc_phandles); =20 /* M-level IMSIC node */ uint32_t msi_m_phandle =3D next_phandle(); - create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_MIMSIC], ms->smp.cpus, + create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_MIMSIC], num_harts, intc_phandles, msi_m_phandle, IRQ_M_EXT, TT_IMSIC_GUEST_BITS); =20 /* S-level IMSIC node */ - create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_SIMSIC], ms->smp.cpus, + create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_SIMSIC], num_harts, intc_phandles, imsic_s_phandle, IRQ_S_EXT, TT_IMSIC_GUEST_BITS); =20 @@ -253,13 +248,13 @@ static void create_fdt_cpu(TTAtlantisState *s, const = MemMapEntry *memmap, create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_MAPLIC], msi_m_phandle, intc_phandles, aplic_m_phandle, aplic_s_phandle, - IRQ_M_EXT, s->cpus.num_harts); + IRQ_M_EXT, num_harts); =20 /* S-level APLIC node */ create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_SAPLIC], imsic_s_phandle, intc_phandles, aplic_s_phandle, 0, - IRQ_S_EXT, s->cpus.num_harts); + IRQ_S_EXT, num_harts); } =20 static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, @@ -318,10 +313,9 @@ static void create_fdt_i2c(void *fdt, const MemMapEntr= y *mem, uint32_t irq, qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0); } =20 -static void create_fdt_i2c_device(TTAtlantisState *s, int bus, +static void create_fdt_i2c_device(void *fdt, TTAtlantisState *s, int bus, const char *compat, int addr) { - void *fdt =3D MACHINE(s)->fdt; hwaddr base =3D s->memmap[TT_ATL_I2C0 + bus].base; g_autofree char *name =3D g_strdup_printf("/soc/i2c@%"HWADDR_PRIX"/sen= sor@%x", base, addr); @@ -331,14 +325,15 @@ static void create_fdt_i2c_device(TTAtlantisState *s,= int bus, qemu_fdt_setprop_cell(fdt, name, "reg", addr); } =20 -static void finalize_fdt(TTAtlantisState *s) +static void finalize_fdt(void *fdt, TTAtlantisState *s) { uint32_t aplic_s_phandle =3D next_phandle(); uint32_t imsic_s_phandle =3D next_phandle(); uint32_t periph_clk_phandle =3D next_phandle(); - void *fdt =3D MACHINE(s)->fdt; =20 - create_fdt_cpu(s, s->memmap, aplic_s_phandle, imsic_s_phandle); + create_fdt_cpu(fdt, s, aplic_s_phandle, imsic_s_phandle); + + create_fdt_memory(fdt, s); =20 /* * We want to do this, but the Linux aplic driver was broken before v6= .16 @@ -360,8 +355,8 @@ static void finalize_fdt(TTAtlantisState *s) } =20 /* I2C peripherals: qemu specific */ - create_fdt_i2c_device(s, 0, "dallas,ds1338", 0x6f); - create_fdt_i2c_device(s, 4, "ti,tmp105", 0x48); + create_fdt_i2c_device(fdt, s, 0, "dallas,ds1338", 0x6f); + create_fdt_i2c_device(fdt, s, 4, "ti,tmp105", 0x48); } =20 static void create_fdt(TTAtlantisState *s) @@ -378,7 +373,7 @@ static void create_fdt(TTAtlantisState *s) =20 qemu_fdt_add_subnode(ms->fdt, "/aliases"); =20 - create_fdt_pmu(s); + create_fdt_pmu(ms->fdt, s); } =20 static void load_fdt(TTAtlantisState *s) @@ -409,7 +404,7 @@ static void load_fdt(TTAtlantisState *s) g_strfreev(node_path); } =20 - create_fdt_memory(s); + create_fdt_memory(ms->fdt, s); } =20 static void mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, @@ -440,7 +435,7 @@ static void tt_atlantis_machine_done(Notifier *notifier= , void *data) * dynamic sysbus devices. Our FDT needs to be finalized. */ if (machine->dtb =3D=3D NULL) { - finalize_fdt(s); + finalize_fdt(machine->fdt, s); } =20 mem_size =3D machine->ram_size; --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788414831081710.3338055182011; Wed, 2 Sep 2026 22:53:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x20OC-0007FE-RT; Thu, 03 Sep 2026 01:53:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x20O7-0006tY-PD for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:28 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x20O6-0006Ub-2t for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:27 -0400 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-3964e480f76so2661869a91.1 for ; Wed, 02 Sep 2026 22:53:25 -0700 (PDT) Received: from donnager-debian.. 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Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- include/hw/riscv/tt_atlantis.h | 1 + hw/riscv/tt_atlantis.c | 19 ++++++++++--------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 642490d21743..a29c67c1cfcf 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -29,6 +29,7 @@ struct TTAtlantisState { Notifier machine_done; const MemMapEntry *memmap; =20 + MemoryRegion *memory; RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index f2a4a051d1f6..2a70119c2c6b 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -483,13 +483,14 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) { TTAtlantisState *s =3D TT_ATLANTIS_MACHINE(machine); =20 - MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *ram_hi =3D g_new(MemoryRegion, 1); MemoryRegion *ram_lo =3D g_new(MemoryRegion, 1); MemoryRegion *bootrom =3D g_new(MemoryRegion, 1); ram_addr_t lo_ram_size; int hart_count =3D machine->smp.cpus; =20 + s->memory =3D get_system_memory(); + s->memmap =3D tt_atlantis_memmap; =20 object_initialize_child(OBJECT(machine), "soc", &s->cpus, @@ -505,7 +506,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); =20 - s->irqchip =3D riscv_create_aia(system_memory, + s->irqchip =3D riscv_create_aia(s->memory, true, TT_IMSIC_GUESTS, TT_IMSIC_STRIDE, TT_IMSIC_STRIDE, @@ -518,7 +519,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) TT_IRQCHIP_NUM_MSIS, TT_IRQCHIP_NUM_PRIO_BITS); =20 - riscv_aclint_mtimer_create(system_memory, + riscv_aclint_mtimer_create(s->memory, s->memmap[TT_ATL_ACLINT].base, TT_ACLINT_MTIME_SIZE, 0, hart_count, @@ -541,23 +542,23 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) =20 memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", machine-= >ram, 0, machine->ram_size); - memory_region_add_subregion(system_memory, + memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_HI].base, ram_hi); =20 lo_ram_size =3D MIN(machine->ram_size, s->memmap[TT_ATL_DDR_LO].size); memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", machine->= ram, 0, lo_ram_size); - memory_region_add_subregion(system_memory, + memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_LO].base, ram_lo); =20 /* Boot ROM */ memory_region_init_rom(bootrom, NULL, "tt-atlantis.bootrom", s->memmap[TT_ATL_BOOTROM].size, &error_fatal); - memory_region_add_subregion(system_memory, s->memmap[TT_ATL_BOOTROM].b= ase, + memory_region_add_subregion(s->memory, s->memmap[TT_ATL_BOOTROM].base, bootrom); =20 /* UART1, the soc console (UART0 is for the boot microcontroller) */ - serial_mm_init(system_memory, s->memmap[TT_ATL_UART1].base, 2, + serial_mm_init(s->memory, s->memmap[TT_ATL_UART1].base, 2, qdev_get_gpio_in(s->irqchip, TT_ATL_UART1_IRQ), 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); /* @@ -571,7 +572,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) */ object_initialize_child(OBJECT(s), "uart1", &s->uart1, TYPE_UNIMPLEMENTED_DEVICE); - mmio_map_unimplemented(system_memory, SYS_BUS_DEVICE(&s->uart1), + mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->uart1), "tt-atlantis.uart1", s->memmap[TT_ATL_UART1].ba= se, s->memmap[TT_ATL_UART1].size); =20 @@ -583,7 +584,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) TYPE_DESIGNWARE_I2C); sbd =3D SYS_BUS_DEVICE(&s->i2c[i]); sysbus_realize(sbd, &error_fatal); - memory_region_add_subregion(system_memory, + memory_region_add_subregion(s->memory, s->memmap[TT_ATL_I2C0 + i].base, sysbus_mmio_get_region(sbd, 0)); sysbus_connect_irq(sbd, 0, --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788414872726622.1791423192606; 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This allows reading the RAM size without needing a pointer to MachineState, decoupling the memory layout setup from the machine. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley --- include/hw/riscv/tt_atlantis.h | 1 + hw/riscv/tt_atlantis.c | 20 ++++++++++++-------- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index a29c67c1cfcf..2ec283d0fd7b 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -30,6 +30,7 @@ struct TTAtlantisState { const MemMapEntry *memmap; =20 MemoryRegion *memory; + MemoryRegion *dram; RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 2a70119c2c6b..90b8e1bc904a 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -82,12 +82,13 @@ static uint32_t next_phandle(void) =20 static void create_fdt_memory(void *fdt, TTAtlantisState *s) { - hwaddr size_lo =3D MACHINE(s)->ram_size; + hwaddr ram_size =3D memory_region_size(s->dram); + hwaddr size_lo =3D ram_size; hwaddr size_hi =3D 0; =20 if (size_lo > s->memmap[TT_ATL_DDR_LO].size) { size_lo =3D s->memmap[TT_ATL_DDR_LO].size; - size_hi =3D MACHINE(s)->ram_size - size_lo; + size_hi =3D ram_size - size_lo; } =20 riscv_create_fdt_socket_memory(fdt, s->memmap[TT_ATL_DDR_LO].base, @@ -486,11 +487,14 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) MemoryRegion *ram_hi =3D g_new(MemoryRegion, 1); MemoryRegion *ram_lo =3D g_new(MemoryRegion, 1); MemoryRegion *bootrom =3D g_new(MemoryRegion, 1); - ram_addr_t lo_ram_size; + ram_addr_t lo_ram_size, ram_size; int hart_count =3D machine->smp.cpus; =20 s->memory =3D get_system_memory(); =20 + s->dram =3D machine->ram; + ram_size =3D memory_region_size(s->dram); + s->memmap =3D tt_atlantis_memmap; =20 object_initialize_child(OBJECT(machine), "soc", &s->cpus, @@ -533,20 +537,20 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) * The high address is where RAM lives. It is always present and may be * up to 64GB. The low address is an alias of the first 2GB of that RA= M. */ - if (machine->ram_size > s->memmap[TT_ATL_DDR_HI].size) { + if (ram_size > s->memmap[TT_ATL_DDR_HI].size) { char *sz =3D size_to_str(s->memmap[TT_ATL_DDR_HI].size); error_report("RAM size is too large, maximum is %s", sz); g_free(sz); exit(EXIT_FAILURE); } =20 - memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", machine-= >ram, - 0, machine->ram_size); + memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", s->dram, + 0, ram_size); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_HI].base, ram_hi); =20 - lo_ram_size =3D MIN(machine->ram_size, s->memmap[TT_ATL_DDR_LO].size); - memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", machine->= ram, + lo_ram_size =3D MIN(ram_size, s->memmap[TT_ATL_DDR_LO].size); + memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", s->dram, 0, lo_ram_size); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_LO].base, ram_lo); --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788414848003523.5410394736497; Wed, 2 Sep 2026 22:54:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x20OL-0007pE-Kc; Thu, 03 Sep 2026 01:53:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x20OI-0007fV-Kt for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:38 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x20OH-0006Vd-0p for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:38 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-85c9a79590aso2269769b3a.1 for ; Wed, 02 Sep 2026 22:53:36 -0700 (PDT) Received: from donnager-debian.. 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Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joel Stanley --- include/hw/riscv/tt_atlantis.h | 4 ++++ hw/riscv/tt_atlantis.c | 15 ++++++--------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 2ec283d0fd7b..9ca98bfb8478 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -31,10 +31,14 @@ struct TTAtlantisState { =20 MemoryRegion *memory; MemoryRegion *dram; + MemoryRegion ram_hi; + MemoryRegion ram_lo; + RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; + MemoryRegion bootrom; }; =20 enum { diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 90b8e1bc904a..d4fe505fe033 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -484,9 +484,6 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) { TTAtlantisState *s =3D TT_ATLANTIS_MACHINE(machine); =20 - MemoryRegion *ram_hi =3D g_new(MemoryRegion, 1); - MemoryRegion *ram_lo =3D g_new(MemoryRegion, 1); - MemoryRegion *bootrom =3D g_new(MemoryRegion, 1); ram_addr_t lo_ram_size, ram_size; int hart_count =3D machine->smp.cpus; =20 @@ -544,22 +541,22 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) exit(EXIT_FAILURE); } =20 - memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", s->dram, + memory_region_init_alias(&s->ram_hi, OBJECT(machine), "ram.high", s->d= ram, 0, ram_size); memory_region_add_subregion(s->memory, - s->memmap[TT_ATL_DDR_HI].base, ram_hi); + s->memmap[TT_ATL_DDR_HI].base, &s->ram_hi); =20 lo_ram_size =3D MIN(ram_size, s->memmap[TT_ATL_DDR_LO].size); - memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", s->dram, + memory_region_init_alias(&s->ram_lo, OBJECT(machine), "ram.low", s->dr= am, 0, lo_ram_size); memory_region_add_subregion(s->memory, - s->memmap[TT_ATL_DDR_LO].base, ram_lo); + s->memmap[TT_ATL_DDR_LO].base, &s->ram_lo); =20 /* Boot ROM */ - memory_region_init_rom(bootrom, NULL, "tt-atlantis.bootrom", + memory_region_init_rom(&s->bootrom, NULL, "tt-atlantis.bootrom", s->memmap[TT_ATL_BOOTROM].size, &error_fatal); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_BOOTROM].base, - bootrom); + &s->bootrom); =20 /* UART1, the soc console (UART0 is for the boot microcontroller) */ serial_mm_init(s->memory, s->memmap[TT_ATL_UART1].base, 2, --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788414895135763.3037538285362; Wed, 2 Sep 2026 22:54:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x20OP-00086R-Qq; Thu, 03 Sep 2026 01:53:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x20OO-00083L-4Z for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:44 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x20OM-0006WO-Hq for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:43 -0400 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-38511175ad3so2005035a91.2 for ; Wed, 02 Sep 2026 22:53:42 -0700 (PDT) Received: from donnager-debian.. ([180.150.112.50]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1431990a39bsm2770619c88.3.2026.09.02.22.53.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 22:53:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788414821; x=1789019621; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:from:to:cc:subject:date :message-id:reply-to:content-type; bh=ia4P/jyA4f87m0nyaT4ywXgyJnS0qKlG0zYD7mw5Fo0=; b=lDDadWvLig4+G5Wfwai3nfnmMx8i478pJvXLcZI0+PSUmjmpwC+lIzUi0f21rReQsR IOOxFx+d6aZM+18GYzXwfpWlS/eQ8bT5oR/ujjhx0rDPC1J3knFyQx+RzlYWzpm67XSD R36ZN+Pt3HQCWMSnPSjlEp+m0P3TtUULw3qtenpA93hlXA+VR7WkWsyeEvAiFfnqkijJ IlRzcAatQ/DINapn86pnIFEwlObtqFYECggCo/g7v37/P27r+8YMqplpUt0xN9muvwpg SuGtNrn65z98IPT5g063+ADniP0tVH6YcoaFPHK2eN30YBbsddc6bSWauhI/ahGvLtLf L40Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788414821; x=1789019621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=ia4P/jyA4f87m0nyaT4ywXgyJnS0qKlG0zYD7mw5Fo0=; b=sG+x5gO4KeQzqeevHlTcRYSHTPrctyFgy9ePvtJKXN6ftXZGm7IsCvj/qrwaePJbh3 Wds72R1UCE9cS4/tdwNc2qu+d3mScrEcZ+Pewgz+tZhovxgTM0kJv3PUgliGlJNBREK2 pUCR9SuDeJZXAO60f7zYvOuuo40UgfjkBlrbSgxZZ/LtmkmcdM5Ny4YkNMNpLMqGHcd9 1WBceajFC4g3bvVtydwUTT6gKTkS90gzwvAYlThBqbwrdUqOwVX8CvXvSpfgMjaCYhlJ ZZXKU5xl6zcSYB6oUcKlPY0fmAgNUsItAh3NzBqjnvGtIESPhKgTRuq29iczm+0C45ud tldg== X-Forwarded-Encrypted: i=1; AKwUvBw8AGsomHvMugPrYMd3ug7b9WPub+qucZoD1UKQIoM/0V2VNARvlcXXdj+Yk5YiDUFZKOZS2zsCM3hN@nongnu.org X-Gm-Message-State: AFuF++m2rO5+ItGs/N+Ra3fHfwt8krER8+c7YNy3RjFXE4KbKm499EsD pzKDDtHKFnzcKTMmhYlq4d5ETDmZU7598+rZz/olOxJJlKdjZ9lAwtwC X-Gm-Gg: AYBFou3UnGJSV1wo2SHDkJ+NM0vRMHCwxwAuS/KZw8kzjZBjYJEZw1qLKUKhEd/zmcA 27qfF8BmZMCSzICao6dMaOtF3BEp07EbMvwitRJAYG0cUt/nQIQF33bPgDxHf6bfh8JDfL89Tld cBO4RvNTfkLUE0JWFcnbOeDtYt3JCKl5Snd7+JB4zu9b2U+uTxpOE1qBCw/17rjKzXFqPTZOKo1 5jHmkWYAo1z/ic71/fnmTEPlMtMY2IVAEPqIJK5dV80PUv5JO0j3KrmZB73FgAuZom12H+Q9lGW MpPjHf0tRW2hc1Wq9E++bVQNTbHXo938UE0RpryuWfdGrd2mF7ByxaJpky99SoEOQihaPNtfEcn lVNZijk9P1bg+FGh/kBj6UcOKjMMq13McoffaojZiKghghYAShnlBXBecKh3UbYHLS12rWtpxz2 Jji7UhFtg60QMpgB+HSDxzBJe2sfrfLmVZsAqOs2reCFHrH2KbUCiS+bzvHLjzPzE16BBhVTJUB dz3PEKX0OJMzPk4kxfjhCob0Q4Nqs0+2onikZZfrpZWdRany7U3SBAxgl1qAZpswuYEkFLGDhWs NUxaLMgzIsFRXmPrY3aj+o6DneVLZ4c= X-Received: by 2002:a17:90b:268d:b0:398:ab03:95b2 with SMTP id 98e67ed59e1d1-39aee023191mr16722961a91.10.1788414821101; Wed, 02 Sep 2026 22:53:41 -0700 (PDT) From: Joel Stanley To: Alistair Francis , Daniel Henrique Barboza Cc: Portia Stephens , Weiwei Li , Liu Zhiwei , Chao Liu , Nicholas Piggin , Anirudh Srinivasan , Michael Ellerman , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 14/16] hw/riscv: Add property to hart array to allow private memory Date: Thu, 3 Sep 2026 15:21:28 +0930 Message-ID: <20260903055131.257903-15-joel@jms.id.au> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260903055131.257903-1-joel@jms.id.au> References: <20260903055131.257903-1-joel@jms.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=joel.stan@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1788414897504158500 Content-Type: text/plain; charset="utf-8" From: Portia Stephens There are platforms where CPUs have different mapping of system memory. The global system memory does not allow for this. This adds an optional property on the hart array to assign a specific memory region. The array passes the region to each hart it creates, so a machine can alias the harts' memory to system memory, while the harts view memory from their own memory region. Signed-off-by: Portia Stephens Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- include/hw/riscv/riscv_hart.h | 2 ++ hw/riscv/riscv_hart.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 197fa1623115..c3cd05a2c877 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -42,6 +42,8 @@ struct RISCVHartArrayState { uint64_t *rnmi_irqvec; uint32_t num_rnmi_excpvec; uint64_t *rnmi_excpvec; + /* Optional private memory region for use instead of system memory */ + MemoryRegion *memory; RISCVCPU *harts; }; =20 diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 747754be6158..32fd39737ff6 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -53,6 +53,8 @@ static const Property riscv_harts_props[] =3D { DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState, num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64, uint64_t), + DEFINE_PROP_LINK("memory", RISCVHartArrayState, memory, + TYPE_MEMORY_REGION, MemoryRegion *), }; =20 static void riscv_harts_cpu_reset(void *opaque) @@ -117,6 +119,12 @@ static bool riscv_hart_realize(RISCVHartArrayState *s,= int idx, object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_typ= e); qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); =20 + /* Use private memory instead of system_memory if provided */ + if (s->memory) { + object_property_set_link(OBJECT(&s->harts[idx]), "memory", + OBJECT(s->memory), &error_abort); + } + if (s->harts[idx].cfg.ext_smrnmi) { if (idx < s->num_rnmi_irqvec) { qdev_prop_set_uint64(DEVICE(&s->harts[idx]), --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788414848292687.6166924231208; Wed, 2 Sep 2026 22:54:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x20OW-0008J1-5O; Thu, 03 Sep 2026 01:53:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x20OU-0008G5-H9 for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:50 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x20OS-0006Wn-1R for qemu-devel@nongnu.org; Thu, 03 Sep 2026 01:53:50 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-8485b358552so1774108b3a.2 for ; Wed, 02 Sep 2026 22:53:47 -0700 (PDT) Received: from donnager-debian.. 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The machine keeps ownership of RAM, device tree generation, firmware loading, and the board-level I2C slaves. This makes it easier to compose the SoC into a more complex machine in the future. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- include/hw/riscv/tt_atlantis.h | 21 ++++- hw/riscv/tt_atlantis.c | 144 +++++++++++++++++++++++---------- 2 files changed, 119 insertions(+), 46 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 9ca98bfb8478..5d4e4d133bd9 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -19,14 +19,16 @@ #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_MACHINE) =20 +#define TYPE_TT_ATLANTIS_SOC "tt-atlantis-soc" +OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisSoCState, TT_ATLANTIS_SOC) + #define TT_ATL_NUM_I2C 5 =20 -struct TTAtlantisState { +struct TTAtlantisSoCState { /*< private >*/ - MachineState parent; + DeviceState parent; =20 /*< public >*/ - Notifier machine_done; const MemMapEntry *memmap; =20 MemoryRegion *memory; @@ -39,6 +41,19 @@ struct TTAtlantisState { DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; MemoryRegion bootrom; + + uint32_t num_harts; + char *cpu_type; +}; + +struct TTAtlantisState { + /*< private >*/ + MachineState parent; + + /*< public >*/ + Notifier machine_done; + + TTAtlantisSoCState soc; }; =20 enum { diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index d4fe505fe033..6c46121287c7 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -7,6 +7,7 @@ */ =20 #include "qemu/osdep.h" +#include "qapi/error.h" #include "qemu/cutils.h" #include "qemu/error-report.h" #include "qemu/guest-random.h" @@ -14,6 +15,7 @@ =20 #include "hw/core/boards.h" #include "hw/core/loader.h" +#include "hw/core/qdev-properties.h" #include "hw/core/sysbus.h" =20 #include "target/riscv/cpu.h" @@ -67,7 +69,7 @@ static const MemMapEntry tt_atlantis_memmap[] =3D { [TT_ATL_DDR_HI] =3D { 0x100000000, 0x1000000000 }, }; =20 -static I2CBus *i2c_get_bus(TTAtlantisState *s, unsigned busnr) +static I2CBus *i2c_get_bus(TTAtlantisSoCState *s, unsigned busnr) { assert(busnr < TT_ATL_NUM_I2C); =20 @@ -80,7 +82,7 @@ static uint32_t next_phandle(void) return fdt_phandle++; } =20 -static void create_fdt_memory(void *fdt, TTAtlantisState *s) +static void create_fdt_memory(void *fdt, TTAtlantisSoCState *s) { hwaddr ram_size =3D memory_region_size(s->dram); hwaddr size_lo =3D ram_size; @@ -105,7 +107,7 @@ static void create_fdt_memory(void *fdt, TTAtlantisStat= e *s) } } =20 -static void create_fdt_aclint(void *fdt, TTAtlantisState *s, +static void create_fdt_aclint(void *fdt, TTAtlantisSoCState *s, uint32_t *intc_phandles) { g_autofree char *name =3D NULL; @@ -207,7 +209,7 @@ static void create_fdt_one_aplic(void *fdt, qemu_fdt_setprop_cell(fdt, name, "phandle", aplic_phandle); } =20 -static void create_fdt_pmu(void *fdt, TTAtlantisState *s) +static void create_fdt_pmu(void *fdt, TTAtlantisSoCState *s) { char pmu_name[] =3D "/pmu"; RISCVCPU *hart =3D &s->cpus.harts[0]; @@ -217,7 +219,7 @@ static void create_fdt_pmu(void *fdt, TTAtlantisState *= s) riscv_pmu_generate_fdt_node(fdt, hart->pmu_avail_ctrs, pmu_name); } =20 -static void create_fdt_cpu(void *fdt, TTAtlantisState *s, +static void create_fdt_cpu(void *fdt, TTAtlantisSoCState *s, uint32_t aplic_s_phandle, uint32_t imsic_s_phandle) { @@ -314,7 +316,7 @@ static void create_fdt_i2c(void *fdt, const MemMapEntry= *mem, uint32_t irq, qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0); } =20 -static void create_fdt_i2c_device(void *fdt, TTAtlantisState *s, int bus, +static void create_fdt_i2c_device(void *fdt, TTAtlantisSoCState *s, int bu= s, const char *compat, int addr) { hwaddr base =3D s->memmap[TT_ATL_I2C0 + bus].base; @@ -326,7 +328,7 @@ static void create_fdt_i2c_device(void *fdt, TTAtlantis= State *s, int bus, qemu_fdt_setprop_cell(fdt, name, "reg", addr); } =20 -static void finalize_fdt(void *fdt, TTAtlantisState *s) +static void finalize_fdt(void *fdt, TTAtlantisSoCState *s) { uint32_t aplic_s_phandle =3D next_phandle(); uint32_t imsic_s_phandle =3D next_phandle(); @@ -360,9 +362,9 @@ static void finalize_fdt(void *fdt, TTAtlantisState *s) create_fdt_i2c_device(fdt, s, 4, "ti,tmp105", 0x48); } =20 -static void create_fdt(TTAtlantisState *s) +static void create_fdt(TTAtlantisState *ams) { - MachineState *ms =3D MACHINE(s); + MachineState *ms =3D MACHINE(ams); int fdt_size =3D 0; =20 ms->fdt =3D riscv_create_board_device_tree("Tenstorrent Atlantis RISC-= V Machine", @@ -374,12 +376,12 @@ static void create_fdt(TTAtlantisState *s) =20 qemu_fdt_add_subnode(ms->fdt, "/aliases"); =20 - create_fdt_pmu(ms->fdt, s); + create_fdt_pmu(ms->fdt, &ams->soc); } =20 -static void load_fdt(TTAtlantisState *s) +static void load_fdt(TTAtlantisState *ams) { - MachineState *ms =3D MACHINE(s); + MachineState *ms =3D MACHINE(ams); char **node_path; Error *err =3D NULL; int fdt_size =3D 0; @@ -405,7 +407,7 @@ static void load_fdt(TTAtlantisState *s) g_strfreev(node_path); } =20 - create_fdt_memory(ms->fdt, s); + create_fdt_memory(ms->fdt, &ams->soc); } =20 static void mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, @@ -419,10 +421,11 @@ static void mmio_map_unimplemented(MemoryRegion *memo= ry, SysBusDevice *dev, sysbus_mmio_get_region(dev, 0), -1= 000); } =20 -static void tt_atlantis_machine_done(Notifier *notifier, void *data) +static void tt_atlantis_machine_done(Notifier *n, void *data) { - TTAtlantisState *s =3D container_of(notifier, TTAtlantisState, machine= _done); - MachineState *machine =3D MACHINE(s); + TTAtlantisState *ams =3D container_of(n, TTAtlantisState, machine_done= ); + TTAtlantisSoCState *s =3D &ams->soc; + MachineState *machine =3D MACHINE(ams); hwaddr start_addr =3D s->memmap[TT_ATL_DDR_LO].base; hwaddr mem_size; target_ulong firmware_end_addr, kernel_start_addr; @@ -480,23 +483,39 @@ static void tt_atlantis_machine_done(Notifier *notifi= er, void *data) fdt_load_addr); } =20 -static void tt_atlantis_machine_init(MachineState *machine) +static void tt_atlantis_soc_init(Object *obj) { - TTAtlantisState *s =3D TT_ATLANTIS_MACHINE(machine); + TTAtlantisSoCState *s =3D TT_ATLANTIS_SOC(obj); + + object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); + + object_initialize_child(obj, "uart1", &s->uart1, + TYPE_UNIMPLEMENTED_DEVICE); =20 + for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { + object_initialize_child(obj, "i2c[*]", &s->i2c[i], + TYPE_DESIGNWARE_I2C); + } +} + +static void tt_atlantis_soc_realize(DeviceState *dev, Error **errp) +{ + TTAtlantisSoCState *s =3D TT_ATLANTIS_SOC(dev); ram_addr_t lo_ram_size, ram_size; - int hart_count =3D machine->smp.cpus; + int hart_count =3D s->num_harts; =20 s->memory =3D get_system_memory(); =20 - s->dram =3D machine->ram; + if (!s->dram) { + error_setg(errp, "'dram' link is not set"); + return; + } ram_size =3D memory_region_size(s->dram); =20 s->memmap =3D tt_atlantis_memmap; =20 - object_initialize_child(OBJECT(machine), "soc", &s->cpus, - TYPE_RISCV_HART_ARRAY); - object_property_set_str(OBJECT(&s->cpus), "cpu-type", machine->cpu_typ= e, + /* CPUs */ + object_property_set_str(OBJECT(&s->cpus), "cpu-type", s->cpu_type, &error_abort); object_property_set_int(OBJECT(&s->cpus), "hartid-base", 0, &error_abort); @@ -505,7 +524,9 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) object_property_set_int(OBJECT(&s->cpus), "resetvec", s->memmap[TT_ATL_BOOTROM].base, &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpus), errp)) { + return; + } =20 s->irqchip =3D riscv_create_aia(s->memory, true, TT_IMSIC_GUESTS, @@ -535,26 +556,27 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) * up to 64GB. The low address is an alias of the first 2GB of that RA= M. */ if (ram_size > s->memmap[TT_ATL_DDR_HI].size) { - char *sz =3D size_to_str(s->memmap[TT_ATL_DDR_HI].size); - error_report("RAM size is too large, maximum is %s", sz); - g_free(sz); - exit(EXIT_FAILURE); + g_autofree char *sz =3D size_to_str(s->memmap[TT_ATL_DDR_HI].size); + error_setg(errp, "RAM size is too large, maximum is %s", sz); + return; } =20 - memory_region_init_alias(&s->ram_hi, OBJECT(machine), "ram.high", s->d= ram, + memory_region_init_alias(&s->ram_hi, OBJECT(s), "ram.high", s->dram, 0, ram_size); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_HI].base, &s->ram_hi); =20 lo_ram_size =3D MIN(ram_size, s->memmap[TT_ATL_DDR_LO].size); - memory_region_init_alias(&s->ram_lo, OBJECT(machine), "ram.low", s->dr= am, + memory_region_init_alias(&s->ram_lo, OBJECT(s), "ram.low", s->dram, 0, lo_ram_size); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_LO].base, &s->ram_lo); =20 /* Boot ROM */ - memory_region_init_rom(&s->bootrom, NULL, "tt-atlantis.bootrom", - s->memmap[TT_ATL_BOOTROM].size, &error_fatal); + if (!memory_region_init_rom(&s->bootrom, OBJECT(s), "tt-atlantis.bootr= om", + s->memmap[TT_ATL_BOOTROM].size, errp)) { + return; + } memory_region_add_subregion(s->memory, s->memmap[TT_ATL_BOOTROM].base, &s->bootrom); =20 @@ -571,26 +593,56 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) * Create an unimplemented device region so writes don't fault * and reads return zero, which keeps Linux happy. */ - object_initialize_child(OBJECT(s), "uart1", &s->uart1, - TYPE_UNIMPLEMENTED_DEVICE); mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->uart1), "tt-atlantis.uart1", s->memmap[TT_ATL_UART1].ba= se, s->memmap[TT_ATL_UART1].size); =20 /* I2C */ for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { - SysBusDevice *sbd; + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->i2c[i]); =20 - object_initialize_child(OBJECT(s), "i2c[*]", &s->i2c[i], - TYPE_DESIGNWARE_I2C); - sbd =3D SYS_BUS_DEVICE(&s->i2c[i]); - sysbus_realize(sbd, &error_fatal); + if (!sysbus_realize(sbd, errp)) { + return; + } memory_region_add_subregion(s->memory, s->memmap[TT_ATL_I2C0 + i].base, sysbus_mmio_get_region(sbd, 0)); sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(s->irqchip, TT_ATL_I2C0_IRQ + = i)); } +} + +static const Property tt_atlantis_soc_props[] =3D { + DEFINE_PROP_STRING("cpu-type", TTAtlantisSoCState, cpu_type), + DEFINE_PROP_UINT32("num-harts", TTAtlantisSoCState, num_harts, 8), + DEFINE_PROP_LINK("dram", TTAtlantisSoCState, dram, + TYPE_MEMORY_REGION, MemoryRegion *), +}; + +static void tt_atlantis_soc_class_init(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D tt_atlantis_soc_realize; + device_class_set_props(dc, tt_atlantis_soc_props); + /* The SoC can only be instantiated from the machine */ + dc->user_creatable =3D false; +} + +static void tt_atlantis_machine_init(MachineState *machine) +{ + TTAtlantisState *ams =3D TT_ATLANTIS_MACHINE(machine); + TTAtlantisSoCState *s =3D &ams->soc; + + object_initialize_child(OBJECT(machine), "soc", &ams->soc, + TYPE_TT_ATLANTIS_SOC); + object_property_set_str(OBJECT(&ams->soc), "cpu-type", machine->cpu_ty= pe, + &error_abort); + object_property_set_int(OBJECT(&ams->soc), "num-harts", machine->smp.c= pus, + &error_abort); + object_property_set_link(OBJECT(&ams->soc), "dram", OBJECT(machine->ra= m), + &error_abort); + qdev_realize(DEVICE(&ams->soc), NULL, &error_fatal); =20 /* I2C peripherals: qemu specific */ i2c_slave_create_simple(i2c_get_bus(s, 0), "ds1338", 0x6f); @@ -598,13 +650,13 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) =20 /* Load or create device tree */ if (machine->dtb) { - load_fdt(s); + load_fdt(ams); } else { - create_fdt(s); + create_fdt(ams); } =20 - s->machine_done.notify =3D tt_atlantis_machine_done; - qemu_add_machine_init_done_notifier(&s->machine_done); + ams->machine_done.notify =3D tt_atlantis_machine_done; + qemu_add_machine_init_done_notifier(&ams->machine_done); } =20 static void tt_atlantis_machine_class_init(ObjectClass *oc, const void *da= ta) @@ -624,6 +676,12 @@ static void tt_atlantis_machine_class_init(ObjectClass= *oc, const void *data) =20 static const TypeInfo tt_atlantis_types[] =3D { { + .name =3D TYPE_TT_ATLANTIS_SOC, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(TTAtlantisSoCState), + .instance_init =3D tt_atlantis_soc_init, + .class_init =3D tt_atlantis_soc_class_init, + }, { .name =3D MACHINE_TYPE_NAME("tt-atlantis"), .parent =3D TYPE_MACHINE, .class_init =3D tt_atlantis_machine_class_init, --=20 2.47.3 From nobody Sat Sep 26 20:51:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([180.150.112.50]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1431990a39bsm2770619c88.3.2026.09.02.22.53.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 22:53:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788414832; x=1789019632; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:from:to:cc:subject:date :message-id:reply-to:content-type; bh=x1RKetAYUO6DQYUtxx7Wjswe/LX2S4835vuil13oPxY=; b=FsAMsirK0sKPSOEtisTMw0vKvlmkqX0IbVoqPNbDyEHE+S6FmbcFO9601s9+M/LdD0 w2IZ6lW4bD7aSfh0Y1EMJRxN6VoRsfMYARYmMfoXqBkOYRkXMc5iPqyyIJTXZOPEpiBD TAgoL3ld2XwRVv1/Wk+Hhr6KfGu5nFGLhUa6liDk8ja7H7KV7BdsslUxUNI4CwZzprAV 0iGN5OTwRq3aXA2HzBBBzqfW/TC9l55q9037BwHcWprvyNXJmkU2ZcEYn3r75Wd9x5LR 3+8Gdide+TpjfIhscePNEZ32h1W7u+PVCSsWoBrflm9B2ZV+LNFDPjpoOWKz+Ol1/9xP gj+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788414832; x=1789019632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=x1RKetAYUO6DQYUtxx7Wjswe/LX2S4835vuil13oPxY=; b=WPym7PWTXhiAFFA1/SM4v32gOCl6AOq+muiG3tjcHFUOC4TiHmR4T5mePs4MpTO+L/ 7UC8Q86MvijzYi3v3kHf1x0GqTpclXGRHa39WNJwW2tN/vEukeeAmg6uN+gThTigc0+i yJAlKVFzaSMgQHo5dFoNMlh0CaA6fzSypCn8WYM0/XirGw92FGBskP8a+Z6rWkN/pe8i UU6bf5bHdQhDWVhe+0ZT2tbpcZn8jIWWFliQXlvpEmK220IM1JFkFDdGzVrM3CH9amPK BKi2OppKBNEiC4Xe/7UMiUNcKWD8ConeerLA9rUB264lpxVmLFXTKsXh5TKqE82GNLR+ sIpw== X-Forwarded-Encrypted: i=1; AKwUvBz0oEuJqw1B5wk52aSTHwxecTi5YnCF8QRitAY1TujjQfjVweuWXuOSPzLLiDSrlDERfoKGQl+vovx8@nongnu.org X-Gm-Message-State: AFuF++n4owwBxK4+KIfz0lWact4B0P34YWunCankrz3e0kul4UeQxnfr xvliEJ3ID+68ab3KZXbZPELTE1zeKLddlhGait+SsJacvDXzNVWaYJUT X-Gm-Gg: AYBFou0kWnbJC8rUUGgphxpNxw9EUzmvcpRlz3r1uvT2o4uWA8bE/fjqA38rV56NlaA GMwmcNQc5BMMs04iF6Fdw9J3cXAmSgOk+ZkQXjvL5zdlpTmpuZzF8jL+z4xTXL50QuFk+LLz96C 6REXbIJUd1BNtf3Hq4a+3g63rc3aA5nF/7Ko4WiogbwvcsaoVvxGTlwsQahpZXBug8zHMMwqMvj lXqxIh5PIE21CrvaELfuHyoacu0mIlryVHCUlZq8dP0pz0tntXeXl4j6A7gNEwzbgiuA0qWAba3 cOkOyaKC4h22rwuRex+Ctzu/ezn7tDHZdkHngOIY05CCk8qMIQ0etAFeJUQVISmY3/Nw4Nr+eIU rmh3em302+P7UEg0/1j+bd7cZlS0Njgg7MD5bAIb6Wo3SUT/5phuqgF7/PSFvakJQHD6rP541ov MdP2c1G3U9YVr49U5tSu/lrnhUCwj+oMIVKEBz65i+84T/yzKz839PDU+65Y1ixhpy8KKAkMVHG 65ktcy3oCmEm/CBlQqtjzwjmUx6m9mIHxdoM6rKjpgX6QJN1kB73D/AGU8+2E78yg8+trDlcV6A /SA/fPUaTG6oaO7zmUw3 X-Received: by 2002:a05:6a20:6a1a:b0:3d3:b02a:61a5 with SMTP id adf61e73a8af0-3d9b0a3a286mr12173308637.28.1788414831639; Wed, 02 Sep 2026 22:53:51 -0700 (PDT) From: Joel Stanley To: Alistair Francis , Daniel Henrique Barboza Cc: Weiwei Li , Liu Zhiwei , Chao Liu , Nicholas Piggin , Anirudh Srinivasan , Michael Ellerman , Portia Stephens , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 16/16] hw/riscv/atlantis: Map the SoC through a memory container Date: Thu, 3 Sep 2026 15:21:30 +0930 Message-ID: <20260903055131.257903-17-joel@jms.id.au> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260903055131.257903-1-joel@jms.id.au> References: <20260903055131.257903-1-joel@jms.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=joel.stan@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1788414871178158500 Content-Type: text/plain; charset="utf-8" Give the Atlantis SoC a 'memory' link property. The machine creates a container MemoryRegion, maps it at address 0 of system memory, and passes it to the SoC together with the machine RAM. The SoC maps devices into the 'memory' container instead of system memory, allowing TTAtlantisSoCState to be composed together with other SoCs in the future. This prepares the machine for adding other microcontrollers that share the memory bus with the Ascalon complex (aka the Atlantis SoC), but with their own view of the address map. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- include/hw/riscv/tt_atlantis.h | 1 + hw/riscv/tt_atlantis.c | 17 +++++++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 5d4e4d133bd9..3923308b7c89 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -53,6 +53,7 @@ struct TTAtlantisState { /*< public >*/ Notifier machine_done; =20 + MemoryRegion soc_memory; TTAtlantisSoCState soc; }; =20 diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 6c46121287c7..c6f235a7eac0 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -504,8 +504,10 @@ static void tt_atlantis_soc_realize(DeviceState *dev, = Error **errp) ram_addr_t lo_ram_size, ram_size; int hart_count =3D s->num_harts; =20 - s->memory =3D get_system_memory(); - + if (!s->memory) { + error_setg(errp, "'memory' link is not set"); + return; + } if (!s->dram) { error_setg(errp, "'dram' link is not set"); return; @@ -524,6 +526,8 @@ static void tt_atlantis_soc_realize(DeviceState *dev, E= rror **errp) object_property_set_int(OBJECT(&s->cpus), "resetvec", s->memmap[TT_ATL_BOOTROM].base, &error_abort); + object_property_set_link(OBJECT(&s->cpus), "memory", OBJECT(s->memory), + &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpus), errp)) { return; } @@ -615,6 +619,8 @@ static void tt_atlantis_soc_realize(DeviceState *dev, E= rror **errp) static const Property tt_atlantis_soc_props[] =3D { DEFINE_PROP_STRING("cpu-type", TTAtlantisSoCState, cpu_type), DEFINE_PROP_UINT32("num-harts", TTAtlantisSoCState, num_harts, 8), + DEFINE_PROP_LINK("memory", TTAtlantisSoCState, memory, + TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_LINK("dram", TTAtlantisSoCState, dram, TYPE_MEMORY_REGION, MemoryRegion *), }; @@ -634,12 +640,19 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) TTAtlantisState *ams =3D TT_ATLANTIS_MACHINE(machine); TTAtlantisSoCState *s =3D &ams->soc; =20 + memory_region_init(&ams->soc_memory, OBJECT(machine), + "tt-atlantis.soc-memory", UINT64_MAX); + memory_region_add_subregion(get_system_memory(), 0, &ams->soc_memory); + object_initialize_child(OBJECT(machine), "soc", &ams->soc, TYPE_TT_ATLANTIS_SOC); object_property_set_str(OBJECT(&ams->soc), "cpu-type", machine->cpu_ty= pe, &error_abort); object_property_set_int(OBJECT(&ams->soc), "num-harts", machine->smp.c= pus, &error_abort); + + object_property_set_link(OBJECT(&ams->soc), "memory", + OBJECT(&ams->soc_memory), &error_abort); object_property_set_link(OBJECT(&ams->soc), "dram", OBJECT(machine->ra= m), &error_abort); qdev_realize(DEVICE(&ams->soc), NULL, &error_fatal); --=20 2.47.3