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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=nnmlinux@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1788284567640154100 Content-Type: text/plain; charset="utf-8" Add spapr_phb_vfio_errinjct() to the VFIO EEH backend in spapr_pci_vfio.c. The function maps guest RTAS IOA bus-error types to the corresponding VFIO EEH ioctl error types: RTAS_ERR_TYPE_IOA_BUS_ERROR -> EEH_ERR_TYPE_32 RTAS_ERR_TYPE_IOA_BUS_ERROR_64 -> EEH_ERR_TYPE_64 EEH_ERR_TYPE_32 / EEH_ERR_TYPE_64 are imported from the powerpc UAPI EEH header where available; fallback numeric definitions are provided to guard against older build environments. The backend consumes type, func, addr, and mask from the caller. It does not accept or interpret config_addr; PHB/PE selection is the caller's responsibility via the sphb pointer. Supporting type definitions are added to include/hw/ppc/spapr.h: - EEH_ERR_FUNC_* and EEH_ERR_FUNC_MAX - EEH_ERR_TYPE_32 / EEH_ERR_TYPE_64 (with #ifndef guards) - enum rtas_err_type (RTAS ibm,errinjct error token values) - RTAS_IBM_ERRINJCT token The function prototype is added to include/hw/pci-host/spapr.h inside the CONFIG_LINUX ifdef block alongside the other EEH hooks. Signed-off-by: Narayana Murty N Reviewed-by: Nikhil Kumar Singh --- include/hw/pci-host/spapr.h | 8 ++++ include/hw/ppc/spapr.h | 60 ++++++++++++++++++++++++++++- hw/ppc/spapr_pci_vfio.c | 75 +++++++++++++++++++++++++++++++++++++ 3 files changed, 142 insertions(+), 1 deletion(-) diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 0db87f1281..24109409f4 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -125,6 +125,8 @@ int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, i= nt *state); int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option); int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb); void spapr_phb_vfio_reset(DeviceState *qdev); +int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, + uint32_t func, uint64_t addr, uint64_t mask); #else static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb) { @@ -151,6 +153,12 @@ static inline int spapr_phb_vfio_eeh_configure(SpaprPh= bState *sphb) static inline void spapr_phb_vfio_reset(DeviceState *qdev) { } +static inline int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t ty= pe, + uint32_t func, uint64_t addr, + uint64_t mask) +{ + return RTAS_OUT_NOT_SUPPORTED; +} #endif =20 void spapr_phb_dma_reset(SpaprPhbState *sphb); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 9acda15d4f..253dc0e862 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -682,6 +682,63 @@ void push_sregs_to_kvm_pr(SpaprMachineState *spapr); #define RTAS_EEH_PE_UNAVAIL_INFO 1000 #define RTAS_EEH_PE_RECOVER_INFO 0 =20 +/* EEH error injection types and functions */ +#define EEH_ERR_FUNC_MIN 0 +#define EEH_ERR_FUNC_LD_MEM_ADDR 0 /* Memory load */ +#define EEH_ERR_FUNC_LD_MEM_DATA 1 +#define EEH_ERR_FUNC_LD_IO_ADDR 2 /* IO load */ +#define EEH_ERR_FUNC_LD_IO_DATA 3 +#define EEH_ERR_FUNC_LD_CFG_ADDR 4 /* Config load */ +#define EEH_ERR_FUNC_LD_CFG_DATA 5 +#define EEH_ERR_FUNC_ST_MEM_ADDR 6 /* Memory store */ +#define EEH_ERR_FUNC_ST_MEM_DATA 7 +#define EEH_ERR_FUNC_ST_IO_ADDR 8 /* IO store */ +#define EEH_ERR_FUNC_ST_IO_DATA 9 +#define EEH_ERR_FUNC_ST_CFG_ADDR 10 /* Config store */ +#define EEH_ERR_FUNC_ST_CFG_DATA 11 +#define EEH_ERR_FUNC_DMA_RD_ADDR 12 /* DMA read */ +#define EEH_ERR_FUNC_DMA_RD_DATA 13 +#define EEH_ERR_FUNC_DMA_RD_MASTER 14 +#define EEH_ERR_FUNC_DMA_RD_TARGET 15 +#define EEH_ERR_FUNC_DMA_WR_ADDR 16 /* DMA write */ +#define EEH_ERR_FUNC_DMA_WR_DATA 17 +#define EEH_ERR_FUNC_DMA_WR_MASTER 18 +#define EEH_ERR_FUNC_DMA_WR_TARGET 19 +#define EEH_ERR_FUNC_MAX EEH_ERR_FUNC_DMA_WR_TARGET + +/* + * RTAS ibm,errinjct error type byte values. These are RTAS ABI token + * numbers, not the same as the VFIO EEH ABI type values consumed by + * VFIO_EEH_PE_INJECT_ERR. An explicit mapping is required. + */ +/* Use powerpc EEH UAPI constants where available; define locally otherwis= e. */ +#ifndef EEH_ERR_TYPE_32 +#define EEH_ERR_TYPE_32 0 +#endif +#ifndef EEH_ERR_TYPE_64 +#define EEH_ERR_TYPE_64 1 +#endif + +/* RTAS PCI Error Injection Token Types */ +enum rtas_err_type { + RTAS_ERR_TYPE_FATAL =3D 0x1, + RTAS_ERR_TYPE_RECOVERED_RANDOM_EVENT =3D 0x2, + RTAS_ERR_TYPE_RECOVERED_SPECIAL_EVENT =3D 0x3, + RTAS_ERR_TYPE_CORRUPTED_PAGE =3D 0x4, + RTAS_ERR_TYPE_CORRUPTED_SLB =3D 0x5, + RTAS_ERR_TYPE_TRANSLATOR_FAILURE =3D 0x6, + RTAS_ERR_TYPE_IOA_BUS_ERROR =3D 0x7, + RTAS_ERR_TYPE_PLATFORM_SPECIFIC =3D 0x8, + RTAS_ERR_TYPE_CORRUPTED_DCACHE_START =3D 0x9, + RTAS_ERR_TYPE_CORRUPTED_DCACHE_END =3D 0xA, + RTAS_ERR_TYPE_CORRUPTED_ICACHE_START =3D 0xB, + RTAS_ERR_TYPE_CORRUPTED_ICACHE_END =3D 0xC, + RTAS_ERR_TYPE_CORRUPTED_TLB_START =3D 0xD, + RTAS_ERR_TYPE_CORRUPTED_TLB_END =3D 0xE, + RTAS_ERR_TYPE_IOA_BUS_ERROR_64 =3D 0xF, + RTAS_ERR_TYPE_UPSTREAM_IO_ERROR =3D 0x10 +}; + /* ibm,set-slot-reset */ #define RTAS_SLOT_RESET_DEACTIVATE 0 #define RTAS_SLOT_RESET_HOT 1 @@ -764,8 +821,9 @@ void push_sregs_to_kvm_pr(SpaprMachineState *spapr); #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) #define RTAS_CONFIGURE_KERNEL_DUMP (RTAS_TOKEN_BASE + 0x2D) +#define RTAS_IBM_ERRINJCT (RTAS_TOKEN_BASE + 0x2E) =20 -#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2E) +#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2F) =20 /* RTAS ibm,get-system-parameter token values */ #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c index a748a0bf4c..7afca0cec6 100644 --- a/hw/ppc/spapr_pci_vfio.c +++ b/hw/ppc/spapr_pci_vfio.c @@ -26,6 +26,7 @@ #include "hw/pci/pci_device.h" #include "hw/vfio/vfio-container-legacy.h" #include "qemu/error-report.h" +#include "hw/vfio/pci.h" #include CONFIG_DEVICES /* CONFIG_VFIO_PCI */ =20 /* @@ -317,6 +318,74 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) return RTAS_OUT_SUCCESS; } =20 +static int spapr_vfio_errinjct_rtas_type_to_vfio(uint32_t rtas_type) +{ + switch (rtas_type) { + case RTAS_ERR_TYPE_IOA_BUS_ERROR: + return EEH_ERR_TYPE_32; + case RTAS_ERR_TYPE_IOA_BUS_ERROR_64: + return EEH_ERR_TYPE_64; + default: + return -1; + } +} + +static bool spapr_vfio_errinjct_func_valid(uint32_t func) +{ + return func <=3D EEH_ERR_FUNC_MAX; +} + +int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, + uint32_t func, uint64_t addr, uint64_t mask) +{ + VFIOLegacyContainer *container; + struct vfio_eeh_pe_op op =3D { + .op =3D VFIO_EEH_PE_INJECT_ERR, + .argsz =3D sizeof(op), + }; + int vfio_type; + + if (!sphb) { + return RTAS_OUT_PARAM_ERROR; + } + + if (!spapr_vfio_errinjct_func_valid(func)) { + return RTAS_OUT_PARAM_ERROR; + } + + vfio_type =3D spapr_vfio_errinjct_rtas_type_to_vfio(type); + if (vfio_type < 0) { + return RTAS_OUT_NOT_SUPPORTED; + } + + container =3D vfio_eeh_as_container(&sphb->iommu_as); + if (!container) { + error_report("vfio/eeh errinjct: no VFIO EEH container for PHB"); + return RTAS_OUT_NOT_SUPPORTED; + } + + op.err.type =3D vfio_type; + op.err.func =3D func; + op.err.addr =3D addr; + op.err.mask =3D mask; + + if (ioctl(container->fd, VFIO_EEH_PE_OP, &op) < 0) { + error_report("vfio/eeh errinjct: VFIO_EEH_PE_OP failed: %s", + strerror(errno)); + switch (errno) { + case EINVAL: + return RTAS_OUT_PARAM_ERROR; + case ENOTTY: + case EOPNOTSUPP: + return RTAS_OUT_NOT_SUPPORTED; + default: + return RTAS_OUT_HW_ERROR; + } + } + + return RTAS_OUT_SUCCESS; +} + #else =20 bool spapr_phb_eeh_available(SpaprPhbState *sphb) @@ -349,4 +418,10 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) return RTAS_OUT_NOT_SUPPORTED; } =20 +int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, + uint32_t func, uint64_t addr, uint64_t mask) +{ + return RTAS_OUT_NOT_SUPPORTED; +} + #endif /* CONFIG_VFIO_PCI */ --=20 2.51.1 From nobody Sat Sep 26 20:50:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 1 Sep 2026 17:41:39 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=FmbjQPgbbsZQ4S3Su Szt0YAgZkAxY3tvdgF/o5k3rqw=; b=AV4TLBDH0ljL3Aa/pYlgDROnm18rvYutc hyXjyPnetXNiRjyUSr2EIHvCEep0btU8bLOrYnkurY7r/BLLahlpujPBma7lg/Or ySfH0cIsXpEXS4/SD1X4kXOMSMv6ZJyx9l4s/F3Z31BcFiy/IYuiYqQRcrH1noiS gjWyFVogvvuFx8X2WBCYqYW0k+i9+19RLIx4QAKsUW9186/eiRCB4kFT3ea9EB5W 2FaMa+3nUGwEdgq4TC76aA44nhuCbmGvnlHF1DpJStqv9kw6fkOvbEMD01ci5NX3 DZ1ARPdO7M1QIuPwIBf1IhhBtSB8r/Z9ddd/KxJP8gN4Xv6ODq6hg== From: Narayana Murty N To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, mahesh@linux.ibm.com, sbhat@linux.ibm.com, anushree.mathur@linux.vnet.ibm.com, clg@redhat.com, sourabhjain@linux.ibm.com, adityag@linux.ibm.com, nikhilks@linux.ibm.com Cc: pierrick.bouvier@oss.qualcomm.com, rathc@linux.ibm.com, npiggin@gmail.com, harshpb@linux.ibm.com, amachhiw@linux.ibm.com, hbathini@linux.ibm.com, shivangu@linux.ibm.com Subject: [PATCH v5 2/6] ppc/spapr: Add ibm,errinjct RTAS call handler Date: Tue, 1 Sep 2026 23:11:06 +0530 Message-ID: <20260901174110.45356-3-nnmlinux@linux.ibm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260901174110.45356-1-nnmlinux@linux.ibm.com> References: <20260901174110.45356-1-nnmlinux@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDE1NSBTYWx0ZWRfX/Fd6vom+C7Pr v2fxfdKJvn1T72Or3S6LjXkLn9D3rN7DIiXbeHzcBH7OEMt/TyS32VprycYsCe+dN/9nLj4LqUs kC7dMRXQOc3Um4id0WaFPF2X9mJp+UeWRoj6+3VK3bqiA8TxkzlIO9C95iqB0POyhnaaIzwM6+L c2muIk1vI9rm1a+1/Phdg/51zaSv1B8iPUaSbh9YILOsfEeHuEGSIn7NY+mXQ6tgi8LF0r+iUWD tRLdTGtoIVipik3Rofo9pkr+Qt0fjvckr/JpFSeAzOKCRClljYC7pnxikr6avHcTy/QfnXAKN1p anB5DpIHw+t8KQmycPP+6Vn5vRLUHS2pWOHP2d+ptWmPHZiZZ4Qfpgrf/xxAqat7aiQRRYt13gl uif3UKYOEZJUQeb7zJFJUJfjp7dZ31Py+HdVJmfrpJDIoH5BAglydgyWaT9iq2N38a2Z48pOMuf J5ggqOMRp4V6ed63akQ== X-Proofpoint-ORIG-GUID: KlxmL0Jru6BoCKGsElzgS9B5VTEx40j6 X-Authority-Analysis: v=2.4 cv=CNgamxrD c=1 sm=1 tr=0 ts=6a970e5d cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8 a=ckvBqbd_4HPzd86GAI0A:9 X-Proofpoint-GUID: 6qJbETqgdJ-_MIydWgP2ZUrxm0T_mGyq X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDE1NSBTYWx0ZWRfXz5J0zNAaJcvz WhSnRIJjfwoRS6YQgQ4JV0UN0ex+byPlG0R0BpF9l8vhhIav71kfqMplXJ2nwldjQbNTBIJqFNZ HI7fIm/V5ECHmU7TSRVbWkBni1U4KZ0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_05,2026-09-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010155 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=nnmlinux@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1788284585591158500 Content-Type: text/plain; charset="utf-8" Implement the 'ibm,errinjct' RTAS call for PHB-level PCI error injection via firmware. The handler decodes the RTAS parameter buffer, validates arguments, selects the target PHB by BUID, and delegates the injection to the VFIO EEH backend. IOA bus-error injection (types 0x7 and 0xF) is fully supported: - The BUID field in the RTAS parameter block selects the target PHB via spapr_pci_find_phb(); - For addr !=3D 0 or mask !=3D 0 the guest BAR address is translated to the corresponding host resource base address before calling the VFIO backend. Translation matches the guest BAR layout under the selected PHB, computes offset =3D guest_addr - guest_bar, reads the host sysfs resource file for the matching BAR, and yields host_addr =3D host_bar + offset. - For addr =3D=3D 0 and mask =3D=3D 0 translation is skipped and zero addr/mask are forwarded directly (powerpc-utils errinjct -a 0 -m 0). Non-IOA error types (corrupted-page, dcache, icache, tlb, recovered-special-event) are decoded and validated, then rejected with RTAS_OUT_NOT_SUPPORTED because their RTAS work buffers do not carry a BUID, making safe VFIO PHB/PE selection impossible. The translation helpers added to spapr_pci_vfio.c: - spapr_phb_vfio_translate_errinjct_addr() - public entry point - spapr_vfio_errinjct_find_bar_cb() - per-device BAR scan - spapr_vfio_errinjct_get_host_bar() - host sysfs BAR reader config_addr is retained as a logging/debug parameter only; PHB selection relies on BUID. Signed-off-by: Narayana Murty N Reviewed-by: Nikhil Kumar Singh --- include/hw/pci-host/spapr.h | 11 ++ include/hw/ppc/spapr.h | 3 + hw/ppc/spapr_pci.c | 135 ++++++++++++++++++++++++ hw/ppc/spapr_pci_vfio.c | 203 ++++++++++++++++++++++++++++++++++++ 4 files changed, 352 insertions(+) diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 24109409f4..492f66e1ef 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -127,6 +127,10 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb); void spapr_phb_vfio_reset(DeviceState *qdev); int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, uint32_t func, uint64_t addr, uint64_t mask); +int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, + uint32_t config_addr, + uint64_t guest_addr, + uint64_t *host_pci_bus_addr); #else static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb) { @@ -159,6 +163,13 @@ static inline int spapr_phb_vfio_errinjct(SpaprPhbStat= e *sphb, uint32_t type, { return RTAS_OUT_NOT_SUPPORTED; } +static inline int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sp= hb, + uint32_t config_a= ddr, + uint64_t guest_ad= dr, + uint64_t *host_ad= dr) +{ + return -ENOTSUP; +} #endif =20 void spapr_phb_dma_reset(SpaprPhbState *sphb); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 253dc0e862..47791c71bd 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -274,6 +274,9 @@ struct SpaprMachineState { bool fadump_registered; bool fadump_dump_active; FadumpMemStruct registered_fdm; + + /* ibm,errinjct session token (0 =3D no session open) */ + uint32_t errinjct_token; }; =20 #define H_SUCCESS 0 diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index c1d4b7806e..cff12ef268 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -704,6 +704,138 @@ param_error_exit: rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); } =20 +static int spapr_errinjct_parse_ioa_bus_error(target_ulong param_buf, + bool is_64bit, + uint64_t *addr, uint64_t *ma= sk, + uint32_t *config_addr, + uint64_t *buid, uint32_t *fu= nc) +{ + if (is_64bit) { + *addr =3D ((uint64_t)rtas_ld(param_buf, 0) << 32) | + rtas_ld(param_buf, 1); + *mask =3D ((uint64_t)rtas_ld(param_buf, 2) << 32) | + rtas_ld(param_buf, 3); + *config_addr =3D rtas_ld(param_buf, 4); + *buid =3D ((uint64_t)rtas_ld(param_buf, 5) << 32) | + rtas_ld(param_buf, 6); + *func =3D rtas_ld(param_buf, 7); + } else { + *addr =3D rtas_ld(param_buf, 0); + *mask =3D rtas_ld(param_buf, 1); + *config_addr =3D rtas_ld(param_buf, 2); + *buid =3D ((uint64_t)rtas_ld(param_buf, 3) << 32) | + rtas_ld(param_buf, 4); + *func =3D rtas_ld(param_buf, 5); + } + return RTAS_OUT_SUCCESS; +} + +/* + * Non-IOA RTAS error types (page corrupt, dcache, icache, tlb, special + * event) are validated but not supported for VFIO injection. VFIO EEH + * is PE/PHB-scoped and those work buffers do not carry a BUID, so QEMU + * cannot select the right VFIO container safely. + */ +static void spapr_errinjct_return_non_ioa_unsupported(target_ulong rets) +{ + rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); +} + +static void rtas_ibm_errinjct(PowerPCCPU *cpu, SpaprMachineState *spapr, + uint32_t token, uint32_t nargs, + target_ulong args, uint32_t nret, + target_ulong rets) +{ + SpaprPhbState *sphb =3D NULL; + target_ulong param_buf; + uint64_t addr =3D 0, mask =3D 0, buid =3D 0; + uint64_t inject_addr =3D 0; + uint32_t config_addr =3D 0; + uint32_t func =3D 0; + uint32_t type, o_token; + bool is_64bit; + int ret; + + if (nargs !=3D 3 || nret !=3D 1) { + goto param_error_exit; + } + + type =3D rtas_ld(args, 0); + o_token =3D rtas_ld(args, 1); + param_buf =3D rtas_ld(args, 2); + + if (!param_buf) { + goto param_error_exit; + } + + if (!spapr->errinjct_token || o_token !=3D spapr->errinjct_token) { + goto param_error_exit; + } + + switch (type) { + case RTAS_ERR_TYPE_IOA_BUS_ERROR: + case RTAS_ERR_TYPE_IOA_BUS_ERROR_64: + is_64bit =3D (type =3D=3D RTAS_ERR_TYPE_IOA_BUS_ERROR_64); + ret =3D spapr_errinjct_parse_ioa_bus_error(param_buf, is_64bit, + &addr, &mask, + &config_addr, &buid, &fun= c); + if (ret !=3D RTAS_OUT_SUCCESS) { + goto param_error_exit; + } + break; + + case RTAS_ERR_TYPE_RECOVERED_SPECIAL_EVENT: + case RTAS_ERR_TYPE_CORRUPTED_PAGE: + case RTAS_ERR_TYPE_CORRUPTED_DCACHE_START: + case RTAS_ERR_TYPE_CORRUPTED_DCACHE_END: + case RTAS_ERR_TYPE_CORRUPTED_ICACHE_START: + case RTAS_ERR_TYPE_CORRUPTED_ICACHE_END: + case RTAS_ERR_TYPE_CORRUPTED_TLB_START: + case RTAS_ERR_TYPE_CORRUPTED_TLB_END: + spapr_errinjct_return_non_ioa_unsupported(rets); + return; + + default: + goto param_error_exit; + } + + /* IOA path: BUID selects the target PHB */ + if (!buid) { + goto param_error_exit; + } + + sphb =3D spapr_pci_find_phb(spapr, buid); + if (!sphb) { + error_report("ibm,errinjct: no PHB for BUID=3D0x%016" PRIx64, buid= ); + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); + return; + } + + inject_addr =3D addr; + + /* + * addr=3D0, mask=3D0 means a non-address-scoped IOA injection. This + * matches powerpc-utils errinjct -a 0 -m 0 behaviour; skip translation + * and forward addr/mask as zero. + */ + if (addr || mask) { + ret =3D spapr_phb_vfio_translate_errinjct_addr(sphb, config_addr, + addr, &inject_addr); + if (ret) { + rtas_st(rets, 0, ret =3D=3D -EOPNOTSUPP ? RTAS_OUT_NOT_SUPPORT= ED + : RTAS_OUT_PARAM_ERROR); + return; + } + } + + ret =3D spapr_phb_vfio_errinjct(sphb, type, func, inject_addr, mask); + rtas_st(rets, 0, ret); + return; + +param_error_exit: + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); +} + static void pci_spapr_set_irq(void *opaque, int irq_num, int level) { /* @@ -2380,6 +2512,9 @@ void spapr_pci_rtas_init(void) spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, "ibm,slot-error-detail", rtas_ibm_slot_error_detail); + spapr_rtas_register(RTAS_IBM_ERRINJCT, + "ibm,errinjct", + rtas_ibm_errinjct); } =20 static void spapr_pci_register_types(void) diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c index 7afca0cec6..2f428531cc 100644 --- a/hw/ppc/spapr_pci_vfio.c +++ b/hw/ppc/spapr_pci_vfio.c @@ -318,6 +318,201 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) return RTAS_OUT_SUCCESS; } =20 +typedef struct SpaprVFIOErrinjctBarMatch { + uint64_t guest_addr; + + PCIDevice *pdev; + VFIOPCIDevice *vdev; + int bar; + + uint64_t guest_bar_start; + uint64_t bar_size; + uint64_t offset; +} SpaprVFIOErrinjctBarMatch; + +static VFIOPCIDevice *spapr_vfio_errinjct_pci_to_vfio(PCIDevice *pdev) +{ + if (!object_dynamic_cast(OBJECT(pdev), TYPE_VFIO_PCI)) { + return NULL; + } + + return container_of(pdev, VFIOPCIDevice, parent_obj); +} + +static void spapr_vfio_errinjct_find_bar_cb(PCIBus *bus, + PCIDevice *pdev, + void *opaque) +{ + SpaprVFIOErrinjctBarMatch *ctx =3D opaque; + VFIOPCIDevice *vdev; + int bar; + + if (ctx->pdev) { + return; + } + + vdev =3D spapr_vfio_errinjct_pci_to_vfio(pdev); + if (!vdev) { + return; + } + + for (bar =3D 0; bar < PCI_STD_NUM_BARS; bar++) { + pcibus_t guest_bar_start; + uint64_t bar_size; + uint64_t offset; + + bar_size =3D vdev->bars[bar].region.size; + if (!bar_size) { + continue; + } + + guest_bar_start =3D pci_get_bar_addr(pdev, bar); + if (guest_bar_start =3D=3D PCI_BAR_UNMAPPED) { + continue; + } + + if (ctx->guest_addr < guest_bar_start || + ctx->guest_addr - guest_bar_start >=3D bar_size) { + if (vdev->bars[bar].mem64) { + bar++; + } + continue; + } + + offset =3D ctx->guest_addr - guest_bar_start; + + ctx->pdev =3D pdev; + ctx->vdev =3D vdev; + ctx->bar =3D bar; + ctx->guest_bar_start =3D guest_bar_start; + ctx->bar_size =3D bar_size; + ctx->offset =3D offset; + + return; + } +} + +static int spapr_vfio_errinjct_get_host_bar(VFIOPCIDevice *vdev, + int bar, + uint64_t *host_bar_start) +{ + g_autofree char *path =3D NULL; + g_autofree char *contents =3D NULL; + char *line; + char *saveptr =3D NULL; + unsigned long long start; + unsigned long long end; + unsigned long long flags; + int i; + + if (!vdev || !host_bar_start || bar < 0 || bar >=3D PCI_STD_NUM_BARS) { + return -EINVAL; + } + + /* + * Read the host Linux sysfs resource file for the BAR. Do not use a + * VFIO PCI config-space read because that may return the + * guest-programmed BAR value rather than the host resource address. + */ + path =3D g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%u/resou= rce", + vdev->host.domain, + vdev->host.bus, + vdev->host.slot, + vdev->host.function); + + if (!g_file_get_contents(path, &contents, NULL, NULL)) { + error_report("vfio/eeh errinjct: failed to read %s", path); + return -ENOENT; + } + + line =3D strtok_r(contents, "\n", &saveptr); + + for (i =3D 0; line; i++, line =3D strtok_r(NULL, "\n", &saveptr)) { + if (i !=3D bar) { + continue; + } + + if (sscanf(line, "%llx %llx %llx", &start, &end, &flags) !=3D 3) { + error_report("vfio/eeh errinjct: malformed %s BAR%d", + path, bar); + return -EINVAL; + } + + if (!start || end < start) { + error_report("vfio/eeh errinjct: invalid host resource BAR%d " + "start=3D0x%llx end=3D0x%llx flags=3D0x%llx", + bar, start, end, flags); + return -EINVAL; + } + + *host_bar_start =3D start; + return 0; + } + + return -EINVAL; +} + +int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, + uint32_t config_addr, + uint64_t guest_addr, + uint64_t *host_pci_bus_addr) +{ + PCIHostState *phb; + SpaprVFIOErrinjctBarMatch ctx =3D { + .guest_addr =3D guest_addr, + .pdev =3D NULL, + .vdev =3D NULL, + .bar =3D -1, + }; + uint64_t host_bar_start; + int rc; + + if (!sphb || !host_pci_bus_addr) { + return -EINVAL; + } + + phb =3D PCI_HOST_BRIDGE(sphb); + + /* + * BUID has already selected @sphb before this helper is called. + * config_addr is retained for logging/debug only. Do not rely on it + * to find the target device; some RTAS IOA buffers may not carry a + * valid guest BDF-style config address. Scan VFIO BARs under this + * PHB and match guest_addr against the guest BAR layout instead. + */ + pci_for_each_device_under_bus(phb->bus, + spapr_vfio_errinjct_find_bar_cb, + &ctx); + + if (!ctx.pdev) { + error_report("vfio/eeh errinjct: guest addr 0x%" PRIx64 + " not within any VFIO BAR under BUID=3D0x%016" PRIx64 + " config_addr=3D0x%08x", + guest_addr, sphb->buid, config_addr); + return -ENODEV; + } + + rc =3D spapr_vfio_errinjct_get_host_bar(ctx.vdev, ctx.bar, &host_bar_s= tart); + if (rc) { + error_report("vfio/eeh errinjct: failed to get host BAR%d for " + "dev=3D%s BUID=3D0x%016" PRIx64 " config_addr=3D0x%08= x rc=3D%d", + ctx.bar, ctx.pdev->name, sphb->buid, config_addr, rc); + return rc; + } + + if (host_bar_start =3D=3D ctx.guest_bar_start) { + error_report("vfio/eeh errinjct: refusing guest BAR as host BAR: " + "dev=3D%s BAR%d guest_bar=3D0x%" PRIx64 + " host_bar=3D0x%" PRIx64, + ctx.pdev->name, ctx.bar, + ctx.guest_bar_start, host_bar_start); + return -EOPNOTSUPP; + } + + *host_pci_bus_addr =3D host_bar_start + ctx.offset; + return 0; +} + static int spapr_vfio_errinjct_rtas_type_to_vfio(uint32_t rtas_type) { switch (rtas_type) { @@ -424,4 +619,12 @@ int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint3= 2_t type, return RTAS_OUT_NOT_SUPPORTED; } =20 +int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, + uint32_t config_addr, + uint64_t guest_addr, + uint64_t *host_pci_bus_addr) +{ + return -ENOTSUP; +} + #endif /* CONFIG_VFIO_PCI */ --=20 2.51.1 From nobody Sat Sep 26 20:50:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1788284587; cv=none; d=zohomail.com; s=zohoarc; b=d8hOrgi7TlnsKSTRa4iDMyYiTvwI95cuNmAZ7B37L1g8xaP70hX5xZYB7nToBpqdtQ3A3JMaR7gg3I8q+GpJYZ3TuRJltnZUr/J9AN2euc0ADen3gp3sWwjYnsDcpBObfsRqkTqMTXDM8EhIspYW561sSDlmcdzJPDIXoBd3tn0= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=SwyboiY5S80NcRx3u Cc0+1ovue9I24l0bhHtzlfHvgc=; b=hhm0nH+LDMzy65Z1eB8qEQcymB7bj0OAl T77MknXnK1nk2u2x33EeJUb0ahbTH58Ben63yfb3Zfk+ElyHYAYuvbCIGYRgOyKH bPvrg41tnu0moltNNvZAKY/Ror1XJXYRDBDbrY6MvOdX3p+7Rsq6XptW826RGpig PeISvx/lUczltJDAt1ABPR/PWliSH+IRu2o8QkdW7AP/wABGCi2zM52c+2ZZ8y3z 7nCCbhh2ZB3YxIhWA10BNzvw3Fu6iFNZptHq0jqpOiLjV1i6cHlJlvl02H3RjB1L /E0OCHWEo44BK0+k0PYaqTV8Ho8gVnfYdYDtufnN82SovJ8130Vuw== From: Narayana Murty N To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, mahesh@linux.ibm.com, sbhat@linux.ibm.com, anushree.mathur@linux.vnet.ibm.com, clg@redhat.com, sourabhjain@linux.ibm.com, adityag@linux.ibm.com, nikhilks@linux.ibm.com Cc: pierrick.bouvier@oss.qualcomm.com, rathc@linux.ibm.com, npiggin@gmail.com, harshpb@linux.ibm.com, amachhiw@linux.ibm.com, hbathini@linux.ibm.com, shivangu@linux.ibm.com Subject: [PATCH v5 3/6] ppc/spapr: Add support for ibm, open-errinjct and ibm, close-errinjct Date: Tue, 1 Sep 2026 23:11:07 +0530 Message-ID: <20260901174110.45356-4-nnmlinux@linux.ibm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260901174110.45356-1-nnmlinux@linux.ibm.com> References: <20260901174110.45356-1-nnmlinux@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=PPc/P/qC c=1 sm=1 tr=0 ts=6a970e61 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=iw8L5VQ-6e4m0g-3eYQA:9 X-Proofpoint-GUID: qk-gRzAo7XK-TWB_rf-mpzO3crrO-KJw X-Proofpoint-ORIG-GUID: D1ivztSCIsx3ftd0C20nIWUbWrCDAWPU X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDE1NSBTYWx0ZWRfX1ihe41e54mBB EL3n33QS3+xwPBqo33M0k6jlE+U/a3QjAcxc8MkNHEDb5tfzxlDPpVevgGpa3wNUdqm5TYxic8E Vpu6uOT7ox3o1JbRRAWn+z0fGo1T3pU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDE1NSBTYWx0ZWRfXwu0oPlWFOVgL 4oUNtNyon5IHUCf4CTwAeegYYagGE+M7SNMniRmsRoqL7VBT6ZxpI4kfwHm0i6uwShyVWQvum9m Y4BUjddpdDqcwyXaLaLzW0oIunDqISM87EThK/vKioHKBRKMzPqtR4AhrrCCQxI5lYLsKyOsMLO r77qUm5MJP/5bI+vpcv+QjbHDd0bJB0R3SWXRk0Cvvsz4++p8f1aYgCP/5F+ZIX4mpPMOEoXCR5 3J+WOL08ZR1CEigPhxf+eD3V3e8o952XLO6ETeSFsnVWXgw788a+ySXzkAN2Tw4cT0qDno1s67k IMrCXaaYsKnCu5z/zkz3Mfl5/8yw8N8CFoSouni2EdQbmlkNlzj4lNcBVAGn2EELAYOcmj228hq 0PxVRLIlbGn3zPC9YqGZjIRm/Kb3LSkN9UId0IoH0g3UZHnCSu11Hs5h7Kk5AqBfPWLUqLbY41D UOC/p+CyBLMpqrdYVXQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_05,2026-09-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 spamscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010155 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=nnmlinux@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1788284587546158500 Content-Type: text/plain; charset="utf-8" Add RTAS handlers for ibm,open-errinjct and ibm,close-errinjct. These calls manage exclusive access to the error-injection facility through a simple session token mechanism: only one session may be open at a time. ibm,open-errinjct (nargs=3D0, nret=3D2): Returns rets[0]=3Dtoken, rets[1]=3Dstatus. On success: token=3D1, status=3DRTAS_OUT_SUCCESS. Already-open: token=3D0, status=3DRTAS_OUT_ALREADY_OPEN. Bad args: token=3D0, status=3DRTAS_OUT_PARAM_ERROR. ibm,close-errinjct (nargs=3D1, nret=3D1): Takes the session token in args[0]. Returns RTAS_OUT_SUCCESS on a matching open token. Returns RTAS_OUT_NOT_OPEN if the token is invalid or no session exists. RTAS_IBM_OPEN_ERRINJCT and RTAS_IBM_CLOSE_ERRINJCT token values and RTAS_OUT_ALREADY_OPEN / RTAS_OUT_NOT_OPEN return codes are added to include/hw/ppc/spapr.h. Signed-off-by: Narayana Murty N Reviewed-by: Nikhil Kumar Singh --- include/hw/ppc/spapr.h | 8 +++++- hw/ppc/spapr_pci.c | 57 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 47791c71bd..bcb1da5fab 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -825,8 +825,14 @@ enum rtas_err_type { #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) #define RTAS_CONFIGURE_KERNEL_DUMP (RTAS_TOKEN_BASE + 0x2D) #define RTAS_IBM_ERRINJCT (RTAS_TOKEN_BASE + 0x2E) +#define RTAS_IBM_OPEN_ERRINJCT (RTAS_TOKEN_BASE + 0x2F) +#define RTAS_IBM_CLOSE_ERRINJCT (RTAS_TOKEN_BASE + 0x30) =20 -#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2F) +#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x31) + +/* ibm,open-errinjct/ibm,close-errinjct return codes */ +#define RTAS_OUT_ALREADY_OPEN -4 +#define RTAS_OUT_NOT_OPEN -5 =20 /* RTAS ibm,get-system-parameter token values */ #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index cff12ef268..20cb913f12 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -836,6 +836,57 @@ param_error_exit: rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); } =20 +static void rtas_ibm_open_errinjct(PowerPCCPU *cpu, SpaprMachineState *spa= pr, + uint32_t token, uint32_t nargs, + target_ulong args, uint32_t nret, + target_ulong rets) +{ + if (nargs !=3D 0 || nret !=3D 2) { + rtas_st(rets, 0, 0); + rtas_st(rets, 1, RTAS_OUT_PARAM_ERROR); + return; + } + + if (spapr->errinjct_token) { + /* Session already open: return token=3D0, status=3DALREADY_OPEN */ + rtas_st(rets, 0, 0); + rtas_st(rets, 1, RTAS_OUT_ALREADY_OPEN); + return; + } + + spapr->errinjct_token =3D 1; + + /* + * ibm,open-errinjct has an unusual return convention: rets[0] is the + * session token and rets[1] is the status code. + */ + rtas_st(rets, 0, spapr->errinjct_token); + rtas_st(rets, 1, RTAS_OUT_SUCCESS); +} + +static void rtas_ibm_close_errinjct(PowerPCCPU *cpu, SpaprMachineState *sp= apr, + uint32_t token, uint32_t nargs, + target_ulong args, uint32_t nret, + target_ulong rets) +{ + uint32_t o_token; + + if (nargs !=3D 1 || nret !=3D 1) { + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); + return; + } + + o_token =3D rtas_ld(args, 0); + + if (!spapr->errinjct_token || o_token !=3D spapr->errinjct_token) { + rtas_st(rets, 0, RTAS_OUT_NOT_OPEN); + return; + } + + spapr->errinjct_token =3D 0; + rtas_st(rets, 0, RTAS_OUT_SUCCESS); +} + static void pci_spapr_set_irq(void *opaque, int irq_num, int level) { /* @@ -2515,6 +2566,12 @@ void spapr_pci_rtas_init(void) spapr_rtas_register(RTAS_IBM_ERRINJCT, "ibm,errinjct", rtas_ibm_errinjct); + spapr_rtas_register(RTAS_IBM_OPEN_ERRINJCT, + "ibm,open-errinjct", + rtas_ibm_open_errinjct); + spapr_rtas_register(RTAS_IBM_CLOSE_ERRINJCT, + "ibm,close-errinjct", + rtas_ibm_close_errinjct); } =20 static void spapr_pci_register_types(void) --=20 2.51.1 From nobody Sat Sep 26 20:50:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; 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Tue, 1 Sep 2026 17:41:46 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=hKQuSXR1kqgR808OI zjRax84ayGt+vvJWRiE0sO2lNA=; b=SSwnLATmd1qc7SmN0qjEMFelSOlbpvGrv GGCkJYl7s18ltI2q+xbB63IkVp+riih0nYL+fTWcpJ/lGntaLPJBbQtWcnSUUNk8 Yu7wgnCYmwzKjvGjGQj1fk+5fSKckf8VovsW70HChdiOHYKTjre2eZXMBlx4l0HQ bl2RXj2mzvth2U7snQgAbN9xa+W0jWCPlkzP7M/eW1AZIJptAc425iSqjyKK/yXD XaOm4CMGnenG6EssjqPP4j//zPsYrvlsviH2yx8xQ+qa1u9JVhZOI6LVuO/XIHRw Ca/e4ex0y+IC06awrDTa9YkFhfWz7DNA43ATaz0uvgjL3uCkXusGQ== From: Narayana Murty N To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, mahesh@linux.ibm.com, sbhat@linux.ibm.com, anushree.mathur@linux.vnet.ibm.com, clg@redhat.com, sourabhjain@linux.ibm.com, adityag@linux.ibm.com, nikhilks@linux.ibm.com Cc: pierrick.bouvier@oss.qualcomm.com, rathc@linux.ibm.com, npiggin@gmail.com, harshpb@linux.ibm.com, amachhiw@linux.ibm.com, hbathini@linux.ibm.com, shivangu@linux.ibm.com Subject: [PATCH v5 4/6] ppc/spapr: Advertise RTAS error injection call support via FDT property Date: Tue, 1 Sep 2026 23:11:08 +0530 Message-ID: <20260901174110.45356-5-nnmlinux@linux.ibm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260901174110.45356-1-nnmlinux@linux.ibm.com> References: <20260901174110.45356-1-nnmlinux@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=PPc/P/qC c=1 sm=1 tr=0 ts=6a970e65 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=LnazUrRgPASutW5i7uYA:9 X-Proofpoint-GUID: CKqTADGgy6lgmfZRvBhBwJHmyMSbM9jQ X-Proofpoint-ORIG-GUID: 3K5u4MTLKBFy6Im8B2GXdRZWBohvszHg X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDE1NSBTYWx0ZWRfXwM9pBTgT2qUx 5Dl2xo+UhDwQeHJL4NbRykVfMpVglA/rcumvwUf+WjnASGc7hPjaX2HmJpeof53xtENYtGOh5/6 3XtBjwW9HmiHBkHf9VIXf0LQ9P5StpA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDE1NSBTYWx0ZWRfXzUVSayTknDck LyiyGjZMTUnPtbNmrSvBPcCDLmuWef13ZQhuDx/Gi8+OSP5isgi0OxSzviNjXA1AfDBABxd5qmY nmaM9UkRYT0fQMTPwyNtVy2NmQqFBg2G13I6q59VKDayRAfFcNHL2sui+DDsm1u36wePdX6cpwD 5nzqj56UQ4x8fmivXBEqA311hhGSzXfUzCdFuJ/n8WD2M47vEv8N55Xsu46XP+XOzCEHFCr9xe/ by+bA9iFVTlYrvLUjyOzX7YnQxHBf53p0xJkVNS/2TxKs647agT6DHwsR9+YAd4ov2dR7gWd939 G/QdT4K8p3qc6wj/C+CHDSGCBVAu8fbR7rk0fZpOm9xNHTsQuO9pAMSvfPDXX22alX41QiUNGbe y3SabCmRQS7qyfC+TOOPn7A6w94a5veMZPRUzSuMUQ8XmybLsR4zE8w7DoeQZinAvf5jVRuLli3 63x2h+Ug1WkLfUZexGQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_05,2026-09-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 spamscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010155 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=nnmlinux@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1788284599664158500 Content-Type: text/plain; charset="utf-8" Advertise the supported ibm,errinjct token types to the guest through the "ibm,errinjct-tokens" property under the RTAS node in the device tree. The property blob is built directly from a QEMU-side static table. No host /proc/device-tree/rtas/ibm,errinjct-tokens probing is done QEMU presents the same token set regardless of the host platform, which avoids host-specific dependencies. Each entry in the blob is a NUL-terminated token name string followed by a big-endian uint32 type value, matching the PAPR specification for ibm,errinjct-tokens. "ibm,open-errinjct" and "ibm,close-errinjct" string properties are also added to advertise the session-management calls. Signed-off-by: Narayana Murty N Reviewed-by: Nikhil Kumar Singh --- hw/ppc/spapr.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 20e024907b..4c5b06d03d 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -116,6 +116,8 @@ =20 #define PHANDLE_INTC 0x00001111 =20 +#define ERRINJCT_BLOB_MAX 512 + /* These two functions implement the VCPU id numbering: one to compute them * all and one to identify thread 0 of a VCORE. Any change to the first one * is likely to have an impact on the second one, so let's keep them close. @@ -1081,6 +1083,65 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, = void *fdt) */ _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); =20 + /* + * Advertise supported ibm,errinjct token types to the guest via the + * "ibm,errinjct-tokens" RTAS FDT property. The blob is built locally + * from the QEMU-side token table; no /proc/device-tree probing is don= e. + * Each entry is: NUL-terminated name string || big-endian uint32 type. + */ + { + static const struct { + const char *name; + uint32_t type; + } tok_table[] =3D { + { "recovered-special-event", + RTAS_ERR_TYPE_RECOVERED_SPECIAL_EVENT }, + { "corrupted-page", RTAS_ERR_TYPE_CORRUPTED_PAGE = }, + { "ioa-bus-error", RTAS_ERR_TYPE_IOA_BUS_ERROR = }, + { "corrupted-dcache-start", + RTAS_ERR_TYPE_CORRUPTED_DCACHE_START }, + { "corrupted-dcache-end", + RTAS_ERR_TYPE_CORRUPTED_DCACHE_END }, + { "corrupted-icache-start", + RTAS_ERR_TYPE_CORRUPTED_ICACHE_START }, + { "corrupted-icache-end", + RTAS_ERR_TYPE_CORRUPTED_ICACHE_END }, + { "corrupted-tlb-start", + RTAS_ERR_TYPE_CORRUPTED_TLB_START }, + { "corrupted-tlb-end", RTAS_ERR_TYPE_CORRUPTED_TLB_END = }, + { "ioa-bus-error-64", RTAS_ERR_TYPE_IOA_BUS_ERROR_64 = }, + }; + g_autofree char *errinject_tokens =3D NULL; + uint8_t blob[ERRINJCT_BLOB_MAX]; + size_t blen =3D 0; + bool ok =3D true; + + for (int i =3D 0; i < G_N_ELEMENTS(tok_table) && ok; i++) { + size_t slen =3D strlen(tok_table[i].name) + 1; + uint32_t be_type; + + if (blen + slen + sizeof(be_type) > ERRINJCT_BLOB_MAX) { + ok =3D false; + break; + } + memcpy(blob + blen, tok_table[i].name, slen); + blen +=3D slen; + be_type =3D cpu_to_be32(tok_table[i].type); + memcpy(blob + blen, &be_type, sizeof(be_type)); + blen +=3D sizeof(be_type); + } + + if (ok) { + errinject_tokens =3D g_memdup2(blob, blen); + _FDT(fdt_setprop(fdt, rtas, "ibm,errinjct-tokens", + errinject_tokens, blen)); + _FDT(fdt_setprop_string(fdt, rtas, "ibm,open-errinjct", + "ibm,open-errinjct")); + _FDT(fdt_setprop_string(fdt, rtas, "ibm,close-errinjct", + "ibm,close-errinjct")); + } + } + _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", lrdr_capacity, sizeof(lrdr_capacity))); =20 --=20 2.51.1 From nobody Sat Sep 26 20:50:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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Tue, 1 Sep 2026 17:41:54 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D9E2820043; Tue, 1 Sep 2026 17:41:50 +0000 (GMT) Received: from Narayanas-MacBook-Pro.ibm.com (unknown [9.124.219.126]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 1 Sep 2026 17:41:50 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=n3K/e5HfaBeVj//PD re6UpZnsWicro8NxtK4oc2UB6k=; b=i2P7VcCpF/K1Z9clgOFfA5HIgADBH7+gr sCDZYs4I+J4NPgbdQgJl9cbp8oMALiTEJFMK4iGxTEzsHN9RhqnM4Ph25xv1kmzh CtNOOdkDpky63SMJL4DanAPMLjAjQnEDW546F17cezY2srZIMfJZFd4ascDGwpBF 8OV7jX75sY760HX1k1z5YHKxDOdOFXSibwbl7Kn92lBKXwzVGrwxH9EfK3RL2IWn MTXTymttT8OsOa/rMrxktLCzS7/0/n/R9j4YBxBlFVcEkAdwg36voEQdvZWpxfJh 4qHhshoMrIVI1qPfdIubb9LJ/fLSSTjqwkbRFCOA4XYsoF9SgJiCA== From: Narayana Murty N To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, mahesh@linux.ibm.com, sbhat@linux.ibm.com, anushree.mathur@linux.vnet.ibm.com, clg@redhat.com, sourabhjain@linux.ibm.com, adityag@linux.ibm.com, nikhilks@linux.ibm.com Cc: pierrick.bouvier@oss.qualcomm.com, rathc@linux.ibm.com, npiggin@gmail.com, harshpb@linux.ibm.com, amachhiw@linux.ibm.com, hbathini@linux.ibm.com, shivangu@linux.ibm.com Subject: [PATCH v5 5/6] ppc/spapr: Split VFIO EEH support from general VFIO code Date: Tue, 1 Sep 2026 23:11:09 +0530 Message-ID: <20260901174110.45356-6-nnmlinux@linux.ibm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260901174110.45356-1-nnmlinux@linux.ibm.com> References: <20260901174110.45356-1-nnmlinux@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDE1NSBTYWx0ZWRfX9SWuYeoTZiyY aMSGCWIJwZ+jjdwer69S9QCS7/Ht6PqbbsaBdZ/dTXH7stsWv6wiNMHjc4VfBl37M7HDaW0QA8I oiELpy3bn0YRCvSrO5XdelnPZyKZh2Gjb2SU6SAC19sj/U889Hk3PDwetjUUszc7VdlUEPzEwkv Bp6J4ehc5y/ghpnyG+2BC1Y4XjxaEq+ushYQHkQcvO5jXwY44F88ZJxDjpesqL1jhwWyP6ZIMPw 5hSGURbFXRFcKq21lcTjyROlyszgVDQFZgyMmND7upMbDxQ7ju/XuX7HK3OEFePR+HKw8TnxFEF jWqhMGjhkYu/IVxOfVY/ErVT0GEohpE/ByHMAMXd/1XsUhYXlpG5zWNv8/IpH4XqCScREaU+x/Y 6IeB6v3dGS4/WTwWYk5WSkGxWISjhjeVk+EdVf+YhF5sflj0Q5frJVQGSODdudZ8qQMkmvYHKcg p72YhuVIGMEofXXMqcw== X-Proofpoint-ORIG-GUID: xnyys0zsNTFKovckr45MZZ8WYukQh82G X-Authority-Analysis: v=2.4 cv=CNgamxrD c=1 sm=1 tr=0 ts=6a970e69 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=mDV3o1hIAAAA:8 a=EUspDBNiAAAA:8 a=VnNF1IyMAAAA:8 a=zpAuWh22E_a3uCvBUzYA:9 X-Proofpoint-GUID: 1HM_xwH5Uz56I6m-tJtont_mORMxNoIi X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDE1NSBTYWx0ZWRfXznFaWKxFvo7T PaFxLJ9SdjiIJa6Uaf3G8CO0ae6YnqN1jo0IUDAJmPij9PRVKbqhX9lCfr1dKM6z0TKPeiaZ/iL xl+yA9BzDEQthWu11t2v0OziqEyndjA= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_05,2026-09-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010155 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=nnmlinux@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1788284585489158500 Content-Type: text/plain; charset="utf-8" Move all EEH and error-injection functions from spapr_pci_vfio.c into a dedicated hw/ppc/spapr_eeh.c. spapr_eeh.c is compiled only when CONFIG_VFIO_PCI is enabled; spapr_pci_vfio.c is retained as a stub-only file compiled on Linux when CONFIG_VFIO_PCI is not available, providing the non-functional fallback implementations needed for Linux/pseries builds that do not include VFIO PCI. meson.build: replace the single spapr_pci_vfio.c entry with an if_true/if_false pair keyed on CONFIG_VFIO_PCI: CONFIG_VFIO_PCI=3Dy -> spapr_eeh.c (real implementation) CONFIG_VFIO_PCI=3Dn -> spapr_pci_vfio-stubs.c (stubs) No functional change to the EEH state machine. Reviewed-by: Pierrick Bouvier Signed-off-by: Narayana Murty N Reviewed-by: Nikhil Kumar Singh --- include/hw/pci-host/spapr.h | 56 +--- include/hw/ppc/spapr_vfio.h | 31 ++ hw/ppc/spapr_eeh.c | 571 +++++++++++++++++++++++++++++++++ hw/ppc/spapr_pci.c | 1 + hw/ppc/spapr_pci_vfio.c | 591 +---------------------------------- stubs/spapr_phb_vfio-stubs.c | 62 ++++ hw/ppc/Kconfig | 2 +- hw/ppc/meson.build | 1 + stubs/meson.build | 1 + 9 files changed, 670 insertions(+), 646 deletions(-) create mode 100644 include/hw/ppc/spapr_vfio.h create mode 100644 hw/ppc/spapr_eeh.c create mode 100644 stubs/spapr_phb_vfio-stubs.c diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 492f66e1ef..d2bc90a3d2 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -116,61 +116,7 @@ void spapr_phb_remove_pci_device_cb(DeviceState *dev); int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, void *fdt, int *fdt_start_offset, Error **errp); =20 -/* VFIO EEH hooks */ -#ifdef CONFIG_LINUX -bool spapr_phb_eeh_available(SpaprPhbState *sphb); -int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, - unsigned int addr, int option); -int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state); -int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option); -int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb); -void spapr_phb_vfio_reset(DeviceState *qdev); -int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, - uint32_t func, uint64_t addr, uint64_t mask); -int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, - uint32_t config_addr, - uint64_t guest_addr, - uint64_t *host_pci_bus_addr); -#else -static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb) -{ - return false; -} -static inline int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, - unsigned int addr, int opt= ion) -{ - return RTAS_OUT_HW_ERROR; -} -static inline int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, - int *state) -{ - return RTAS_OUT_HW_ERROR; -} -static inline int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option) -{ - return RTAS_OUT_HW_ERROR; -} -static inline int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) -{ - return RTAS_OUT_HW_ERROR; -} -static inline void spapr_phb_vfio_reset(DeviceState *qdev) -{ -} -static inline int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t ty= pe, - uint32_t func, uint64_t addr, - uint64_t mask) -{ - return RTAS_OUT_NOT_SUPPORTED; -} -static inline int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sp= hb, - uint32_t config_a= ddr, - uint64_t guest_ad= dr, - uint64_t *host_ad= dr) -{ - return -ENOTSUP; -} -#endif +/* VFIO EEH hooks - see hw/ppc/spapr_vfio.h for declarations */ =20 void spapr_phb_dma_reset(SpaprPhbState *sphb); =20 diff --git a/include/hw/ppc/spapr_vfio.h b/include/hw/ppc/spapr_vfio.h new file mode 100644 index 0000000000..5aabb262f2 --- /dev/null +++ b/include/hw/ppc/spapr_vfio.h @@ -0,0 +1,31 @@ +/* + * sPAPR VFIO EEH Header + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_PPC_SPAPR_VFIO_H +#define HW_PPC_SPAPR_VFIO_H + +/* + * Forward declarations to avoid pulling in full spapr headers + * This allows stubs and other files to compile without libfdt dependencies + */ +typedef struct SpaprPhbState SpaprPhbState; +typedef struct DeviceState DeviceState; + +/* VFIO EEH function declarations */ +bool spapr_phb_eeh_available(SpaprPhbState *sphb); +int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, + unsigned int addr, int option); +int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state); +int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option); +int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb); +void spapr_phb_vfio_reset(DeviceState *qdev); +void spapr_phb_vfio_eeh_reenable(SpaprPhbState *sphb); +int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, + uint32_t func, uint64_t addr, uint64_t mask); +int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, + uint32_t config_addr, + uint64_t guest_addr, + uint64_t *host_pci_bus_addr); +#endif /* HW_PPC_SPAPR_VFIO_H */ diff --git a/hw/ppc/spapr_eeh.c b/hw/ppc/spapr_eeh.c new file mode 100644 index 0000000000..a9b7fe2d67 --- /dev/null +++ b/hw/ppc/spapr_eeh.c @@ -0,0 +1,571 @@ +/* + * QEMU sPAPR PCI host for VFIO + * + * Copyright (c) 2011-2014 Alexey Kardashevskiy, IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include +#include +#include "hw/ppc/spapr.h" +#include "hw/pci-host/spapr.h" +#include "hw/pci/msix.h" +#include "hw/pci/pci_device.h" +#include "hw/vfio/vfio-container-legacy.h" +#include "qemu/error-report.h" +#include "hw/vfio/pci.h" +#include "hw/ppc/spapr_vfio.h" + +/* + * Interfaces for IBM EEH (Enhanced Error Handling) + */ +static bool vfio_eeh_container_ok(VFIOLegacyContainer *container) +{ + /* + * As of 2016-03-04 (linux-4.5) the host kernel EEH/VFIO + * implementation is broken if there are multiple groups in a + * container. The hardware works in units of Partitionable + * Endpoints (=3D=3D IOMMU groups) and the EEH operations naively + * iterate across all groups in the container, without any logic + * to make sure the groups have their state synchronized. For + * certain operations (ENABLE) that might be ok, until an error + * occurs, but for others (GET_STATE) it's clearly broken. + */ + + /* + * XXX Once fixed kernels exist, test for them here + */ + + if (QLIST_EMPTY(&container->group_list)) { + return false; + } + + if (QLIST_NEXT(QLIST_FIRST(&container->group_list), container_next)) { + return false; + } + + return true; +} + +static int vfio_eeh_container_op(VFIOLegacyContainer *container, uint32_t = op) +{ + struct vfio_eeh_pe_op pe_op =3D { + .argsz =3D sizeof(pe_op), + .op =3D op, + }; + int ret; + + if (!vfio_eeh_container_ok(container)) { + error_report("vfio/eeh: EEH_PE_OP 0x%x: " + "kernel requires a container with exactly one group",= op); + return -EPERM; + } + + ret =3D ioctl(container->fd, VFIO_EEH_PE_OP, &pe_op); + if (ret < 0) { + error_report("vfio/eeh: EEH_PE_OP 0x%x failed: %m", op); + return -errno; + } + + return ret; +} + +static VFIOLegacyContainer *vfio_eeh_as_container(AddressSpace *as) +{ + VFIOAddressSpace *space =3D vfio_address_space_get(as); + VFIOContainer *bcontainer =3D NULL; + + if (QLIST_EMPTY(&space->containers)) { + /* No containers to act on */ + goto out; + } + + bcontainer =3D QLIST_FIRST(&space->containers); + + if (QLIST_NEXT(bcontainer, next)) { + /* + * We don't yet have logic to synchronize EEH state across + * multiple containers + */ + bcontainer =3D NULL; + goto out; + } + +out: + vfio_address_space_put(space); + return VFIO_IOMMU_LEGACY(bcontainer); +} + +static bool vfio_eeh_as_ok(AddressSpace *as) +{ + VFIOLegacyContainer *container =3D vfio_eeh_as_container(as); + + return (container !=3D NULL) && vfio_eeh_container_ok(container); +} + +static int vfio_eeh_as_op(AddressSpace *as, uint32_t op) +{ + VFIOLegacyContainer *container =3D vfio_eeh_as_container(as); + + if (!container) { + return -ENODEV; + } + return vfio_eeh_container_op(container, op); +} + +bool spapr_phb_eeh_available(SpaprPhbState *sphb) +{ + return vfio_eeh_as_ok(&sphb->iommu_as); +} + +void spapr_phb_vfio_eeh_reenable(SpaprPhbState *sphb) +{ + vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_ENABLE); +} + +static void spapr_eeh_pci_find_device(PCIBus *bus, PCIDevice *pdev, + void *opaque) +{ + bool *found =3D opaque; + + if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { + *found =3D true; + } +} + +int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, + unsigned int addr, int option) +{ + uint32_t op; + int ret; + + switch (option) { + case RTAS_EEH_DISABLE: + op =3D VFIO_EEH_PE_DISABLE; + break; + case RTAS_EEH_ENABLE: { + PCIHostState *phb; + bool found =3D false; + + /* + * The EEH functionality is enabled per sphb level instead of + * per PCI device. We have already identified this specific sphb + * based on buid passed as argument to ibm,set-eeh-option rtas + * call. Now we just need to check the validity of the PCI + * pass-through devices (vfio-pci) under this sphb bus. + * We have already validated that all the devices under this sphb + * are from same iommu group (within same PE) before coming here. + * + * Prior to linux commit 98ba956f6a389 ("powerpc/pseries/eeh: + * Rework device EEH PE determination") kernel would call + * eeh-set-option for each device in the PE using the device's + * config_address as the argument rather than the PE address. + * Hence if we check validity of supplied config_addr whether + * it matches to this PHB will cause issues with older kernel + * versions v5.9 and older. If we return an error from + * eeh-set-option when the argument isn't a valid PE address + * then older kernels (v5.9 and older) will interpret that as + * EEH not being supported. + */ + phb =3D PCI_HOST_BRIDGE(sphb); + pci_for_each_device(phb->bus, (addr >> 16) & 0xFF, + spapr_eeh_pci_find_device, &found); + + if (!found) { + return RTAS_OUT_PARAM_ERROR; + } + + op =3D VFIO_EEH_PE_ENABLE; + break; + } + case RTAS_EEH_THAW_IO: + op =3D VFIO_EEH_PE_UNFREEZE_IO; + break; + case RTAS_EEH_THAW_DMA: + op =3D VFIO_EEH_PE_UNFREEZE_DMA; + break; + default: + return RTAS_OUT_PARAM_ERROR; + } + + ret =3D vfio_eeh_as_op(&sphb->iommu_as, op); + if (ret < 0) { + return RTAS_OUT_HW_ERROR; + } + + return RTAS_OUT_SUCCESS; +} + +int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state) +{ + int ret; + + ret =3D vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_GET_STATE); + if (ret < 0) { + return RTAS_OUT_PARAM_ERROR; + } + + *state =3D ret; + return RTAS_OUT_SUCCESS; +} + +static void spapr_phb_vfio_eeh_clear_dev_msix(PCIBus *bus, + PCIDevice *pdev, + void *opaque) +{ + /* Check if the device is VFIO PCI device */ + if (!object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { + return; + } + + /* + * The MSIx table will be cleaned out by reset. We need + * disable it so that it can be reenabled properly. Also, + * the cached MSIx table should be cleared as it's not + * reflecting the contents in hardware. + */ + if (msix_enabled(pdev)) { + uint16_t flags; + + flags =3D pci_host_config_read_common(pdev, + pdev->msix_cap + PCI_MSIX_FLAG= S, + pci_config_size(pdev), 2); + flags &=3D ~PCI_MSIX_FLAGS_ENABLE; + pci_host_config_write_common(pdev, + pdev->msix_cap + PCI_MSIX_FLAGS, + pci_config_size(pdev), flags, 2); + } + + msix_reset(pdev); +} + +static void spapr_phb_vfio_eeh_clear_bus_msix(PCIBus *bus, void *opaque) +{ + pci_for_each_device_under_bus(bus, spapr_phb_vfio_eeh_clear_dev_msi= x, + NULL); +} + +static void spapr_phb_vfio_eeh_pre_reset(SpaprPhbState *sphb) +{ + PCIHostState *phb =3D PCI_HOST_BRIDGE(sphb); + + pci_for_each_bus(phb->bus, spapr_phb_vfio_eeh_clear_bus_msix, NULL); +} + +int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option) +{ + uint32_t op; + int ret; + + switch (option) { + case RTAS_SLOT_RESET_DEACTIVATE: + op =3D VFIO_EEH_PE_RESET_DEACTIVATE; + break; + case RTAS_SLOT_RESET_HOT: + spapr_phb_vfio_eeh_pre_reset(sphb); + op =3D VFIO_EEH_PE_RESET_HOT; + break; + case RTAS_SLOT_RESET_FUNDAMENTAL: + spapr_phb_vfio_eeh_pre_reset(sphb); + op =3D VFIO_EEH_PE_RESET_FUNDAMENTAL; + break; + default: + return RTAS_OUT_PARAM_ERROR; + } + + ret =3D vfio_eeh_as_op(&sphb->iommu_as, op); + if (ret < 0) { + return RTAS_OUT_HW_ERROR; + } + + return RTAS_OUT_SUCCESS; +} + +int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) +{ + int ret; + + ret =3D vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_CONFIGURE); + if (ret < 0) { + return RTAS_OUT_PARAM_ERROR; + } + + return RTAS_OUT_SUCCESS; +} + +typedef struct SpaprVFIOErrinjctBarMatch { + uint64_t guest_addr; + + PCIDevice *pdev; + VFIOPCIDevice *vdev; + int bar; + + uint64_t guest_bar_start; + uint64_t bar_size; + uint64_t offset; +} SpaprVFIOErrinjctBarMatch; + +static VFIOPCIDevice *spapr_vfio_errinjct_pci_to_vfio(PCIDevice *pdev) +{ + if (!object_dynamic_cast(OBJECT(pdev), TYPE_VFIO_PCI)) { + return NULL; + } + + return container_of(pdev, VFIOPCIDevice, parent_obj); +} + +static void spapr_vfio_errinjct_find_bar_cb(PCIBus *bus, + PCIDevice *pdev, + void *opaque) +{ + SpaprVFIOErrinjctBarMatch *ctx =3D opaque; + VFIOPCIDevice *vdev; + int bar; + + if (ctx->pdev) { + return; + } + + vdev =3D spapr_vfio_errinjct_pci_to_vfio(pdev); + if (!vdev) { + return; + } + + for (bar =3D 0; bar < PCI_STD_NUM_BARS; bar++) { + pcibus_t guest_bar_start; + uint64_t bar_size; + uint64_t offset; + + bar_size =3D vdev->bars[bar].region.size; + if (!bar_size) { + continue; + } + + guest_bar_start =3D pci_get_bar_addr(pdev, bar); + if (guest_bar_start =3D=3D PCI_BAR_UNMAPPED) { + continue; + } + + if (ctx->guest_addr < guest_bar_start || + ctx->guest_addr - guest_bar_start >=3D bar_size) { + if (vdev->bars[bar].mem64) { + bar++; + } + continue; + } + + offset =3D ctx->guest_addr - guest_bar_start; + + ctx->pdev =3D pdev; + ctx->vdev =3D vdev; + ctx->bar =3D bar; + ctx->guest_bar_start =3D guest_bar_start; + ctx->bar_size =3D bar_size; + ctx->offset =3D offset; + + return; + } +} + +static int spapr_vfio_errinjct_get_host_bar(VFIOPCIDevice *vdev, + int bar, + uint64_t *host_bar_start) +{ + g_autofree char *path =3D NULL; + g_autofree char *contents =3D NULL; + char *line; + char *saveptr =3D NULL; + unsigned long long start; + unsigned long long end; + unsigned long long flags; + int i; + + if (!vdev || !host_bar_start || bar < 0 || bar >=3D PCI_STD_NUM_BARS) { + return -EINVAL; + } + + /* + * Read the host Linux sysfs resource file for the BAR. Do not use a + * VFIO PCI config-space read because that may return the + * guest-programmed BAR value rather than the host resource address. + */ + path =3D g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%u/resou= rce", + vdev->host.domain, + vdev->host.bus, + vdev->host.slot, + vdev->host.function); + + if (!g_file_get_contents(path, &contents, NULL, NULL)) { + error_report("vfio/eeh errinjct: failed to read %s", path); + return -ENOENT; + } + + line =3D strtok_r(contents, "\n", &saveptr); + + for (i =3D 0; line; i++, line =3D strtok_r(NULL, "\n", &saveptr)) { + if (i !=3D bar) { + continue; + } + + if (sscanf(line, "%llx %llx %llx", &start, &end, &flags) !=3D 3) { + error_report("vfio/eeh errinjct: malformed %s BAR%d", + path, bar); + return -EINVAL; + } + + if (!start || end < start) { + error_report("vfio/eeh errinjct: invalid host resource BAR%d " + "start=3D0x%llx end=3D0x%llx flags=3D0x%llx", + bar, start, end, flags); + return -EINVAL; + } + + *host_bar_start =3D start; + return 0; + } + + return -EINVAL; +} + +int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, + uint32_t config_addr, + uint64_t guest_addr, + uint64_t *host_pci_bus_addr) +{ + PCIHostState *phb; + SpaprVFIOErrinjctBarMatch ctx =3D { + .guest_addr =3D guest_addr, + .pdev =3D NULL, + .vdev =3D NULL, + .bar =3D -1, + }; + uint64_t host_bar_start; + int rc; + + if (!sphb || !host_pci_bus_addr) { + return -EINVAL; + } + + phb =3D PCI_HOST_BRIDGE(sphb); + + /* + * BUID has already selected @sphb before this helper is called. + * config_addr is retained for logging/debug only. Do not rely on it + * to find the target device; some RTAS IOA buffers may not carry a + * valid guest BDF-style config address. Scan VFIO BARs under this + * PHB and match guest_addr against the guest BAR layout instead. + */ + pci_for_each_device_under_bus(phb->bus, + spapr_vfio_errinjct_find_bar_cb, + &ctx); + + if (!ctx.pdev) { + error_report("vfio/eeh errinjct: guest addr 0x%" PRIx64 + " not within any VFIO BAR under BUID=3D0x%016" PRIx64 + " config_addr=3D0x%08x", + guest_addr, sphb->buid, config_addr); + return -ENODEV; + } + + rc =3D spapr_vfio_errinjct_get_host_bar(ctx.vdev, ctx.bar, &host_bar_s= tart); + if (rc) { + error_report("vfio/eeh errinjct: failed to get host BAR%d for " + "dev=3D%s BUID=3D0x%016" PRIx64 " config_addr=3D0x%08= x rc=3D%d", + ctx.bar, ctx.pdev->name, sphb->buid, config_addr, rc); + return rc; + } + + if (host_bar_start =3D=3D ctx.guest_bar_start) { + error_report("vfio/eeh errinjct: refusing guest BAR as host BAR: " + "dev=3D%s BAR%d guest_bar=3D0x%" PRIx64 + " host_bar=3D0x%" PRIx64, + ctx.pdev->name, ctx.bar, + ctx.guest_bar_start, host_bar_start); + return -EOPNOTSUPP; + } + + *host_pci_bus_addr =3D host_bar_start + ctx.offset; + return 0; +} + +static int spapr_vfio_errinjct_rtas_type_to_vfio(uint32_t rtas_type) +{ + switch (rtas_type) { + case RTAS_ERR_TYPE_IOA_BUS_ERROR: + return EEH_ERR_TYPE_32; + case RTAS_ERR_TYPE_IOA_BUS_ERROR_64: + return EEH_ERR_TYPE_64; + default: + return -1; + } +} + +static bool spapr_vfio_errinjct_func_valid(uint32_t func) +{ + return func <=3D EEH_ERR_FUNC_MAX; +} + +int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, + uint32_t func, uint64_t addr, uint64_t mask) +{ + VFIOLegacyContainer *container; + struct vfio_eeh_pe_op op =3D { + .op =3D VFIO_EEH_PE_INJECT_ERR, + .argsz =3D sizeof(op), + }; + int vfio_type; + + if (!sphb) { + return RTAS_OUT_PARAM_ERROR; + } + + if (!spapr_vfio_errinjct_func_valid(func)) { + return RTAS_OUT_PARAM_ERROR; + } + + vfio_type =3D spapr_vfio_errinjct_rtas_type_to_vfio(type); + if (vfio_type < 0) { + return RTAS_OUT_NOT_SUPPORTED; + } + + container =3D vfio_eeh_as_container(&sphb->iommu_as); + if (!container) { + error_report("vfio/eeh errinjct: no VFIO EEH container for PHB"); + return RTAS_OUT_NOT_SUPPORTED; + } + + op.err.type =3D vfio_type; + op.err.func =3D func; + op.err.addr =3D addr; + op.err.mask =3D mask; + + if (ioctl(container->fd, VFIO_EEH_PE_OP, &op) < 0) { + error_report("vfio/eeh errinjct: VFIO_EEH_PE_OP failed: %s", + strerror(errno)); + switch (errno) { + case EINVAL: + return RTAS_OUT_PARAM_ERROR; + case ENOTTY: + case EOPNOTSUPP: + return RTAS_OUT_NOT_SUPPORTED; + default: + return RTAS_OUT_HW_ERROR; + } + } + + return RTAS_OUT_SUCCESS; +} + diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 20cb913f12..33a1011890 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -33,6 +33,7 @@ #include "hw/pci/msix.h" #include "hw/pci/pci_host.h" #include "hw/ppc/spapr.h" +#include "hw/ppc/spapr_vfio.h" #include "hw/pci-host/spapr.h" #include #include "trace.h" diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c index 2f428531cc..e6ecc3f1ee 100644 --- a/hw/ppc/spapr_pci_vfio.c +++ b/hw/ppc/spapr_pci_vfio.c @@ -22,120 +22,12 @@ #include #include "hw/ppc/spapr.h" #include "hw/pci-host/spapr.h" +#include "hw/ppc/spapr_vfio.h" #include "hw/pci/msix.h" #include "hw/pci/pci_device.h" #include "hw/vfio/vfio-container-legacy.h" #include "qemu/error-report.h" #include "hw/vfio/pci.h" -#include CONFIG_DEVICES /* CONFIG_VFIO_PCI */ - -/* - * Interfaces for IBM EEH (Enhanced Error Handling) - */ -#ifdef CONFIG_VFIO_PCI -static bool vfio_eeh_container_ok(VFIOLegacyContainer *container) -{ - /* - * As of 2016-03-04 (linux-4.5) the host kernel EEH/VFIO - * implementation is broken if there are multiple groups in a - * container. The hardware works in units of Partitionable - * Endpoints (=3D=3D IOMMU groups) and the EEH operations naively - * iterate across all groups in the container, without any logic - * to make sure the groups have their state synchronized. For - * certain operations (ENABLE) that might be ok, until an error - * occurs, but for others (GET_STATE) it's clearly broken. - */ - - /* - * XXX Once fixed kernels exist, test for them here - */ - - if (QLIST_EMPTY(&container->group_list)) { - return false; - } - - if (QLIST_NEXT(QLIST_FIRST(&container->group_list), container_next)) { - return false; - } - - return true; -} - -static int vfio_eeh_container_op(VFIOLegacyContainer *container, uint32_t = op) -{ - struct vfio_eeh_pe_op pe_op =3D { - .argsz =3D sizeof(pe_op), - .op =3D op, - }; - int ret; - - if (!vfio_eeh_container_ok(container)) { - error_report("vfio/eeh: EEH_PE_OP 0x%x: " - "kernel requires a container with exactly one group",= op); - return -EPERM; - } - - ret =3D ioctl(container->fd, VFIO_EEH_PE_OP, &pe_op); - if (ret < 0) { - error_report("vfio/eeh: EEH_PE_OP 0x%x failed: %m", op); - return -errno; - } - - return ret; -} - -static VFIOLegacyContainer *vfio_eeh_as_container(AddressSpace *as) -{ - VFIOAddressSpace *space =3D vfio_address_space_get(as); - VFIOContainer *bcontainer =3D NULL; - - if (QLIST_EMPTY(&space->containers)) { - /* No containers to act on */ - goto out; - } - - bcontainer =3D QLIST_FIRST(&space->containers); - - if (QLIST_NEXT(bcontainer, next)) { - /* - * We don't yet have logic to synchronize EEH state across - * multiple containers - */ - bcontainer =3D NULL; - goto out; - } - -out: - vfio_address_space_put(space); - return VFIO_IOMMU_LEGACY(bcontainer); -} - -static bool vfio_eeh_as_ok(AddressSpace *as) -{ - VFIOLegacyContainer *container =3D vfio_eeh_as_container(as); - - return (container !=3D NULL) && vfio_eeh_container_ok(container); -} - -static int vfio_eeh_as_op(AddressSpace *as, uint32_t op) -{ - VFIOLegacyContainer *container =3D vfio_eeh_as_container(as); - - if (!container) { - return -ENODEV; - } - return vfio_eeh_container_op(container, op); -} - -bool spapr_phb_eeh_available(SpaprPhbState *sphb) -{ - return vfio_eeh_as_ok(&sphb->iommu_as); -} - -static void spapr_phb_vfio_eeh_reenable(SpaprPhbState *sphb) -{ - vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_ENABLE); -} =20 void spapr_phb_vfio_reset(DeviceState *qdev) { @@ -147,484 +39,3 @@ void spapr_phb_vfio_reset(DeviceState *qdev) */ spapr_phb_vfio_eeh_reenable(SPAPR_PCI_HOST_BRIDGE(qdev)); } - -static void spapr_eeh_pci_find_device(PCIBus *bus, PCIDevice *pdev, - void *opaque) -{ - bool *found =3D opaque; - - if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { - *found =3D true; - } -} - -int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, - unsigned int addr, int option) -{ - uint32_t op; - int ret; - - switch (option) { - case RTAS_EEH_DISABLE: - op =3D VFIO_EEH_PE_DISABLE; - break; - case RTAS_EEH_ENABLE: { - PCIHostState *phb; - bool found =3D false; - - /* - * The EEH functionality is enabled per sphb level instead of - * per PCI device. We have already identified this specific sphb - * based on buid passed as argument to ibm,set-eeh-option rtas - * call. Now we just need to check the validity of the PCI - * pass-through devices (vfio-pci) under this sphb bus. - * We have already validated that all the devices under this sphb - * are from same iommu group (within same PE) before coming here. - * - * Prior to linux commit 98ba956f6a389 ("powerpc/pseries/eeh: - * Rework device EEH PE determination") kernel would call - * eeh-set-option for each device in the PE using the device's - * config_address as the argument rather than the PE address. - * Hence if we check validity of supplied config_addr whether - * it matches to this PHB will cause issues with older kernel - * versions v5.9 and older. If we return an error from - * eeh-set-option when the argument isn't a valid PE address - * then older kernels (v5.9 and older) will interpret that as - * EEH not being supported. - */ - phb =3D PCI_HOST_BRIDGE(sphb); - pci_for_each_device(phb->bus, (addr >> 16) & 0xFF, - spapr_eeh_pci_find_device, &found); - - if (!found) { - return RTAS_OUT_PARAM_ERROR; - } - - op =3D VFIO_EEH_PE_ENABLE; - break; - } - case RTAS_EEH_THAW_IO: - op =3D VFIO_EEH_PE_UNFREEZE_IO; - break; - case RTAS_EEH_THAW_DMA: - op =3D VFIO_EEH_PE_UNFREEZE_DMA; - break; - default: - return RTAS_OUT_PARAM_ERROR; - } - - ret =3D vfio_eeh_as_op(&sphb->iommu_as, op); - if (ret < 0) { - return RTAS_OUT_HW_ERROR; - } - - return RTAS_OUT_SUCCESS; -} - -int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state) -{ - int ret; - - ret =3D vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_GET_STATE); - if (ret < 0) { - return RTAS_OUT_PARAM_ERROR; - } - - *state =3D ret; - return RTAS_OUT_SUCCESS; -} - -static void spapr_phb_vfio_eeh_clear_dev_msix(PCIBus *bus, - PCIDevice *pdev, - void *opaque) -{ - /* Check if the device is VFIO PCI device */ - if (!object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { - return; - } - - /* - * The MSIx table will be cleaned out by reset. We need - * disable it so that it can be reenabled properly. Also, - * the cached MSIx table should be cleared as it's not - * reflecting the contents in hardware. - */ - if (msix_enabled(pdev)) { - uint16_t flags; - - flags =3D pci_host_config_read_common(pdev, - pdev->msix_cap + PCI_MSIX_FLAG= S, - pci_config_size(pdev), 2); - flags &=3D ~PCI_MSIX_FLAGS_ENABLE; - pci_host_config_write_common(pdev, - pdev->msix_cap + PCI_MSIX_FLAGS, - pci_config_size(pdev), flags, 2); - } - - msix_reset(pdev); -} - -static void spapr_phb_vfio_eeh_clear_bus_msix(PCIBus *bus, void *opaque) -{ - pci_for_each_device_under_bus(bus, spapr_phb_vfio_eeh_clear_dev_msi= x, - NULL); -} - -static void spapr_phb_vfio_eeh_pre_reset(SpaprPhbState *sphb) -{ - PCIHostState *phb =3D PCI_HOST_BRIDGE(sphb); - - pci_for_each_bus(phb->bus, spapr_phb_vfio_eeh_clear_bus_msix, NULL); -} - -int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option) -{ - uint32_t op; - int ret; - - switch (option) { - case RTAS_SLOT_RESET_DEACTIVATE: - op =3D VFIO_EEH_PE_RESET_DEACTIVATE; - break; - case RTAS_SLOT_RESET_HOT: - spapr_phb_vfio_eeh_pre_reset(sphb); - op =3D VFIO_EEH_PE_RESET_HOT; - break; - case RTAS_SLOT_RESET_FUNDAMENTAL: - spapr_phb_vfio_eeh_pre_reset(sphb); - op =3D VFIO_EEH_PE_RESET_FUNDAMENTAL; - break; - default: - return RTAS_OUT_PARAM_ERROR; - } - - ret =3D vfio_eeh_as_op(&sphb->iommu_as, op); - if (ret < 0) { - return RTAS_OUT_HW_ERROR; - } - - return RTAS_OUT_SUCCESS; -} - -int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) -{ - int ret; - - ret =3D vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_CONFIGURE); - if (ret < 0) { - return RTAS_OUT_PARAM_ERROR; - } - - return RTAS_OUT_SUCCESS; -} - -typedef struct SpaprVFIOErrinjctBarMatch { - uint64_t guest_addr; - - PCIDevice *pdev; - VFIOPCIDevice *vdev; - int bar; - - uint64_t guest_bar_start; - uint64_t bar_size; - uint64_t offset; -} SpaprVFIOErrinjctBarMatch; - -static VFIOPCIDevice *spapr_vfio_errinjct_pci_to_vfio(PCIDevice *pdev) -{ - if (!object_dynamic_cast(OBJECT(pdev), TYPE_VFIO_PCI)) { - return NULL; - } - - return container_of(pdev, VFIOPCIDevice, parent_obj); -} - -static void spapr_vfio_errinjct_find_bar_cb(PCIBus *bus, - PCIDevice *pdev, - void *opaque) -{ - SpaprVFIOErrinjctBarMatch *ctx =3D opaque; - VFIOPCIDevice *vdev; - int bar; - - if (ctx->pdev) { - return; - } - - vdev =3D spapr_vfio_errinjct_pci_to_vfio(pdev); - if (!vdev) { - return; - } - - for (bar =3D 0; bar < PCI_STD_NUM_BARS; bar++) { - pcibus_t guest_bar_start; - uint64_t bar_size; - uint64_t offset; - - bar_size =3D vdev->bars[bar].region.size; - if (!bar_size) { - continue; - } - - guest_bar_start =3D pci_get_bar_addr(pdev, bar); - if (guest_bar_start =3D=3D PCI_BAR_UNMAPPED) { - continue; - } - - if (ctx->guest_addr < guest_bar_start || - ctx->guest_addr - guest_bar_start >=3D bar_size) { - if (vdev->bars[bar].mem64) { - bar++; - } - continue; - } - - offset =3D ctx->guest_addr - guest_bar_start; - - ctx->pdev =3D pdev; - ctx->vdev =3D vdev; - ctx->bar =3D bar; - ctx->guest_bar_start =3D guest_bar_start; - ctx->bar_size =3D bar_size; - ctx->offset =3D offset; - - return; - } -} - -static int spapr_vfio_errinjct_get_host_bar(VFIOPCIDevice *vdev, - int bar, - uint64_t *host_bar_start) -{ - g_autofree char *path =3D NULL; - g_autofree char *contents =3D NULL; - char *line; - char *saveptr =3D NULL; - unsigned long long start; - unsigned long long end; - unsigned long long flags; - int i; - - if (!vdev || !host_bar_start || bar < 0 || bar >=3D PCI_STD_NUM_BARS) { - return -EINVAL; - } - - /* - * Read the host Linux sysfs resource file for the BAR. Do not use a - * VFIO PCI config-space read because that may return the - * guest-programmed BAR value rather than the host resource address. - */ - path =3D g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%u/resou= rce", - vdev->host.domain, - vdev->host.bus, - vdev->host.slot, - vdev->host.function); - - if (!g_file_get_contents(path, &contents, NULL, NULL)) { - error_report("vfio/eeh errinjct: failed to read %s", path); - return -ENOENT; - } - - line =3D strtok_r(contents, "\n", &saveptr); - - for (i =3D 0; line; i++, line =3D strtok_r(NULL, "\n", &saveptr)) { - if (i !=3D bar) { - continue; - } - - if (sscanf(line, "%llx %llx %llx", &start, &end, &flags) !=3D 3) { - error_report("vfio/eeh errinjct: malformed %s BAR%d", - path, bar); - return -EINVAL; - } - - if (!start || end < start) { - error_report("vfio/eeh errinjct: invalid host resource BAR%d " - "start=3D0x%llx end=3D0x%llx flags=3D0x%llx", - bar, start, end, flags); - return -EINVAL; - } - - *host_bar_start =3D start; - return 0; - } - - return -EINVAL; -} - -int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, - uint32_t config_addr, - uint64_t guest_addr, - uint64_t *host_pci_bus_addr) -{ - PCIHostState *phb; - SpaprVFIOErrinjctBarMatch ctx =3D { - .guest_addr =3D guest_addr, - .pdev =3D NULL, - .vdev =3D NULL, - .bar =3D -1, - }; - uint64_t host_bar_start; - int rc; - - if (!sphb || !host_pci_bus_addr) { - return -EINVAL; - } - - phb =3D PCI_HOST_BRIDGE(sphb); - - /* - * BUID has already selected @sphb before this helper is called. - * config_addr is retained for logging/debug only. Do not rely on it - * to find the target device; some RTAS IOA buffers may not carry a - * valid guest BDF-style config address. Scan VFIO BARs under this - * PHB and match guest_addr against the guest BAR layout instead. - */ - pci_for_each_device_under_bus(phb->bus, - spapr_vfio_errinjct_find_bar_cb, - &ctx); - - if (!ctx.pdev) { - error_report("vfio/eeh errinjct: guest addr 0x%" PRIx64 - " not within any VFIO BAR under BUID=3D0x%016" PRIx64 - " config_addr=3D0x%08x", - guest_addr, sphb->buid, config_addr); - return -ENODEV; - } - - rc =3D spapr_vfio_errinjct_get_host_bar(ctx.vdev, ctx.bar, &host_bar_s= tart); - if (rc) { - error_report("vfio/eeh errinjct: failed to get host BAR%d for " - "dev=3D%s BUID=3D0x%016" PRIx64 " config_addr=3D0x%08= x rc=3D%d", - ctx.bar, ctx.pdev->name, sphb->buid, config_addr, rc); - return rc; - } - - if (host_bar_start =3D=3D ctx.guest_bar_start) { - error_report("vfio/eeh errinjct: refusing guest BAR as host BAR: " - "dev=3D%s BAR%d guest_bar=3D0x%" PRIx64 - " host_bar=3D0x%" PRIx64, - ctx.pdev->name, ctx.bar, - ctx.guest_bar_start, host_bar_start); - return -EOPNOTSUPP; - } - - *host_pci_bus_addr =3D host_bar_start + ctx.offset; - return 0; -} - -static int spapr_vfio_errinjct_rtas_type_to_vfio(uint32_t rtas_type) -{ - switch (rtas_type) { - case RTAS_ERR_TYPE_IOA_BUS_ERROR: - return EEH_ERR_TYPE_32; - case RTAS_ERR_TYPE_IOA_BUS_ERROR_64: - return EEH_ERR_TYPE_64; - default: - return -1; - } -} - -static bool spapr_vfio_errinjct_func_valid(uint32_t func) -{ - return func <=3D EEH_ERR_FUNC_MAX; -} - -int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, - uint32_t func, uint64_t addr, uint64_t mask) -{ - VFIOLegacyContainer *container; - struct vfio_eeh_pe_op op =3D { - .op =3D VFIO_EEH_PE_INJECT_ERR, - .argsz =3D sizeof(op), - }; - int vfio_type; - - if (!sphb) { - return RTAS_OUT_PARAM_ERROR; - } - - if (!spapr_vfio_errinjct_func_valid(func)) { - return RTAS_OUT_PARAM_ERROR; - } - - vfio_type =3D spapr_vfio_errinjct_rtas_type_to_vfio(type); - if (vfio_type < 0) { - return RTAS_OUT_NOT_SUPPORTED; - } - - container =3D vfio_eeh_as_container(&sphb->iommu_as); - if (!container) { - error_report("vfio/eeh errinjct: no VFIO EEH container for PHB"); - return RTAS_OUT_NOT_SUPPORTED; - } - - op.err.type =3D vfio_type; - op.err.func =3D func; - op.err.addr =3D addr; - op.err.mask =3D mask; - - if (ioctl(container->fd, VFIO_EEH_PE_OP, &op) < 0) { - error_report("vfio/eeh errinjct: VFIO_EEH_PE_OP failed: %s", - strerror(errno)); - switch (errno) { - case EINVAL: - return RTAS_OUT_PARAM_ERROR; - case ENOTTY: - case EOPNOTSUPP: - return RTAS_OUT_NOT_SUPPORTED; - default: - return RTAS_OUT_HW_ERROR; - } - } - - return RTAS_OUT_SUCCESS; -} - -#else - -bool spapr_phb_eeh_available(SpaprPhbState *sphb) -{ - return false; -} - -void spapr_phb_vfio_reset(DeviceState *qdev) -{ -} - -int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, - unsigned int addr, int option) -{ - return RTAS_OUT_NOT_SUPPORTED; -} - -int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state) -{ - return RTAS_OUT_NOT_SUPPORTED; -} - -int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option) -{ - return RTAS_OUT_NOT_SUPPORTED; -} - -int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) -{ - return RTAS_OUT_NOT_SUPPORTED; -} - -int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, - uint32_t func, uint64_t addr, uint64_t mask) -{ - return RTAS_OUT_NOT_SUPPORTED; -} - -int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, - uint32_t config_addr, - uint64_t guest_addr, - uint64_t *host_pci_bus_addr) -{ - return -ENOTSUP; -} - -#endif /* CONFIG_VFIO_PCI */ diff --git a/stubs/spapr_phb_vfio-stubs.c b/stubs/spapr_phb_vfio-stubs.c new file mode 100644 index 0000000000..4d86d9000e --- /dev/null +++ b/stubs/spapr_phb_vfio-stubs.c @@ -0,0 +1,62 @@ +/* + * Stubs for sPAPR PCI VFIO EEH + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/ppc/spapr_vfio.h" + +/* RTAS return codes */ +#define RTAS_OUT_NOT_SUPPORTED (-3) + + +bool spapr_phb_eeh_available(SpaprPhbState *sphb) +{ + return false; +} + +int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, + unsigned int addr, int option) +{ + return RTAS_OUT_NOT_SUPPORTED; +} + +int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state) +{ + return RTAS_OUT_NOT_SUPPORTED; +} + +int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option) +{ + return RTAS_OUT_NOT_SUPPORTED; +} + +int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) +{ + return RTAS_OUT_NOT_SUPPORTED; +} + +void spapr_phb_vfio_reset(DeviceState *qdev) +{ +} + +void spapr_phb_vfio_eeh_reenable(SpaprPhbState *sphb) +{ +} + +int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, + uint32_t func, uint64_t addr, uint64_t mask) +{ + return RTAS_OUT_NOT_SUPPORTED; +} + +int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, + uint32_t config_addr, + uint64_t guest_addr, + uint64_t *host_pci_bus_addr) +{ + return -ENOTSUP; +} + + diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index 347dcce690..3714d708d9 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -6,7 +6,7 @@ config PSERIES imply PCI_DEVICES imply TEST_DEVICES imply VIRTIO_VGA - imply VFIO_PCI if LINUX # needed by spapr_pci_vfio.c + imply VFIO_PCI if LINUX # needed by spapr_pci_vfio.c and spapr_eeh.c select NVDIMM select DIMM select PCI diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index 37aa535db2..4e03973440 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -36,6 +36,7 @@ ppc_ss.add(when: 'CONFIG_SPAPR_RNG', if_true: files('spap= r_rng.c')) if host_os =3D=3D 'linux' ppc_ss.add(when: 'CONFIG_PSERIES', if_true: files( 'spapr_pci_vfio.c', + 'spapr_eeh.c', )) endif =20 diff --git a/stubs/meson.build b/stubs/meson.build index 3b2f2680b1..2879d6f70e 100644 --- a/stubs/meson.build +++ b/stubs/meson.build @@ -90,6 +90,7 @@ if have_system stub_ss.add(files('hmp-cmd-info_tlb.c')) stub_ss.add(files('hmp-cmds-hw-s390x.c')) stub_ss.add(files('hmp-cmds-target-i386.c')) + stub_ss.add(files('spapr_phb_vfio-stubs.c')) endif =20 if have_system or have_user --=20 2.51.1 From nobody Sat Sep 26 20:50:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=nnmlinux@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1788284565533158500 Content-Type: text/plain; charset="utf-8" Adding self as reviewer for the sPAPR EEH under PPC RAS. Updating the EEH specific file name as got updated in previous patches. Signed-off-by: Narayana Murty N --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4a49a40294..581c109392 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1770,11 +1770,13 @@ M: Aditya Gupta R: Sourabh Jain R: Hari Bathini R: Shivang Upadhyay +R: Narayana Murty N L: qemu-ppc@nongnu.org S: Maintained F: hw/ppc/spapr_events.c F: hw/ppc/spapr_fadump.c F: hw/ppc/spapr_pci_vfio.c +F: hw/ppc/spapr_eeh.c F: hw/ppc/spapr_rtas.c F: hw/ppc/pnv_mpipl.c F: include/hw/ppc/spapr_fadump.h --=20 2.51.1