From nobody Sat Sep 26 20:51:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268801; cv=none; d=zohomail.com; s=zohoarc; b=AGSjVQ4ymaHV0Vyz/5E3EEIbTihhVdXOU3pved+E1Svpnom7gXY39ZbVjU0cNIKYUKzAS1fjM1ffOBi7D8R7MhqV0xhmIf9wQShSIZt6g83apJPpxTODToaI7mPq9REEz450UlgM8CfaFpAVaDskS8xaPkJHdGISd0foYmtQo4w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268801; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ygClSMwDjEFyP3afUj3IeO5rZvDHlKl8+PhkVw27Jz8=; b=Xr8p4Q0diy+xiU4h+ukYRv4rEcvlAEUSO8lCyaKX84XB+VrDkwM3mSQdGVg7EXEIuKTdYPH0Vio6r7bIi/DJdU8LrSZNcXCHmKdD6SOIe5/6kj4ct6X/QsziRcmbl+GV5klfSX1ghntD+mCHY5JRjWQyckWrGKbiz3Z6i7+8G1c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268801804976.2157706486313; Tue, 1 Sep 2026 06:20:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1OMz-0000w7-EK; Tue, 01 Sep 2026 09:17:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1OMv-0000vW-0S for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:41 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1OMs-00076n-BW for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:40 -0400 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-c25366c9b42so102254766b.2 for ; Tue, 01 Sep 2026 06:17:37 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268656; x=1788873456; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=ygClSMwDjEFyP3afUj3IeO5rZvDHlKl8+PhkVw27Jz8=; b=kXlmQ8U4gmWnjTBK8umJk/ujrd7wNL3T7FuMJ/VOtAAOlDyqzZo4K+lKCt51avelr/ VLnR00aMFFtTH9RrdyMiAf3dL2wplhwUXZeD4AR19hxxsYuaV1Adtu4lyteJ4jla/2Wu SuKY7ekK59uyxgdhSKgW0O6cj2XAx/KwGvJzHS0n2/Gib+bVNnC9XV3rDyI5IujtMWYN T3h2WQQgRPyYlhIZOLcV+jYaBmh2mJ7VxDOVb12C42WPrs8OazEqtw3n4BQASwUnPo5o LghHwxOWfC14+OGNBUwpNpmPF9OnM+dG2MlxCHK1Ov565xWTCZ7cLaNydbcV01i9mdxx 2UlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268656; x=1788873456; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=ygClSMwDjEFyP3afUj3IeO5rZvDHlKl8+PhkVw27Jz8=; b=LDpk2TtIiF0SmXgsoCEbczxpP443i+/hnBsKnsXziJUgO0CPIZorGPu8D9KhXkBusM dFgpsO66NfmsTpeiV8ya3CxDCReGURHMOr+2rWXrekGzB9m0JPzbyqAVMI3z/0q4tG8c 8+i4YFSX/PNEbz+cJX/ac0JmiZnzgpIgSgyJ2VtjClxRioTOUzgZ5iso8iUTRpDRJrNl e/s70PNpgxInSoOHJ3zN9vtrflWmU5OBfSvMfgTQU3G7cZiYfpMksDEbldB8bnLKvZkl UKBq2F0TBGkHeVP5/oGdz1ZK4l22/7qAcpzoiNQsbv/cMLRSMHrGIbOZRYkxsN/qJV8j zydQ== X-Gm-Message-State: AFuF++mfpzFcAWNCFJyW0xksXwzjaTg8UQwRodM77FlwuwkWXnZ3ezNy lbX2EMqC1L7+6rVz8StlLH0yRPh/4StNKcngzMwZWcfEGlq+qeZWWdLZEBW7S+7+xZjhzrv9oXo ytQKS9gA= X-Gm-Gg: AR+sD104Z2RHsjNkEVrJ0Gba1hjv6YDNpMVacQyQXucY/F1bgj2aYqAPJh+qlR919Rd 68Hj0drRFIyGEsA6OvLHN4sQOViW68uaQFHPBBlsyDnutTB/DHsd05mtHj3SxZFUCVY96caRFpk b/XwqLGpad3bV2fHS3RvOflIUCxPsXZKI5mLf1h+x2Z7KbtOLLf9l3srr5pc7Ps4EkIIq7P7JKT xdSmo3uTWxkN4fssrrJ+tBBcNcELtmMH4kEh/+ucNWFOFINEB6B2zkfj6YCdli3337GsTJqsshm 8ELOexDKsUOoNdYj1dSlPo+BOA9LNA49vnd5J5qVvlNjSoqCVYBMckJHYvZ4049RS9HvHEwwURG t75ZpoIYa1XlSO7b4CNf+oEy69Kc7nT2A/QB0cp9KYgrG9QYl2PHDdlOBYNHmKS/1vBv2sMAjqD pB1UuNbG9Esj1uG1qdZw+BzuM8fMFNHYypbDNo3QSYgjSIFy1FJW3Rw9IWDztp5DbmH0ZbgLzoK UTfU1sDNzQLXydgWXpB5JNEm0RYGZb8VLOXC+/HQtoqIZcM6ruOPZWaRlwSDf9uAA4xbCk= X-Received: by 2002:a17:906:730e:b0:c25:254:292e with SMTP id a640c23a62f3a-c25567a9274mr2115403966b.0.1788268655129; Tue, 01 Sep 2026 06:17:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/58] hw/char/pl011: support backend hotswap Date: Tue, 1 Sep 2026 14:16:35 +0100 Message-ID: <20260901131732.2263947-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268803659158501 From: Alexander Mikhalitsyn Currently, when Incus issues "chardev-change" QMP command to change chardev backend from ringbuf to socket it receives an error (with aarch64 V= M): "Chardev user does not support chardev hotswap" [1], [2] Let's fix this by properly implementing BackendChangeHandler for pl011. Please, note that we have to "replay" CHR_IOCTL_SERIAL_SET_BREAK, because if BRK bit was set before backend change (i.e. (s->lcr & LCR_BRK) is true), then after change we need to send break to a new backend too. Link: https://discuss.linuxcontainers.org/t/unable-to-connect-to-vm-console= -on-arm-architecture/23096/3 [1] Link: https://github.com/lxc/distrobuilder/issues/892 [2] Reported-by: St=C3=A9phane Graber Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alexander Mikhalitsyn Message-id: 20260821104832.151452-1-alexander@mihalicyn.com Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/char/pl011.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index cb12c3e224f..5ad9e7358d5 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -425,6 +425,11 @@ static void pl011_loopback_break(PL011State *s, int br= k_enable) } } =20 +static inline void pl011_set_break(PL011State *s, int brk_enable) +{ + qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, &brk_enable); +} + static void pl011_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { @@ -462,9 +467,8 @@ static void pl011_write(void *opaque, hwaddr offset, pl011_reset_tx_fifo(s); } if ((s->lcr ^ value) & LCR_BRK) { - int break_enable =3D value & LCR_BRK; - qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, - &break_enable); + bool break_enable =3D value & LCR_BRK; + pl011_set_break(s, break_enable); pl011_loopback_break(s, break_enable); } s->lcr =3D value; @@ -660,12 +664,29 @@ static void pl011_init(Object *obj) s->id =3D pl011_id_arm; } =20 +static int pl011_be_change(void *opaque); + +static inline void pl011_set_handlers(PL011State *s) +{ + qemu_chr_fe_set_handlers(&s->chr, pl011_can_receive, pl011_receive, + pl011_event, pl011_be_change, s, NULL, true); +} + +static int pl011_be_change(void *opaque) +{ + PL011State *s =3D opaque; + + pl011_set_handlers(s); + pl011_set_break(s, s->lcr & LCR_BRK); + + return 0; +} + static void pl011_realize(DeviceState *dev, Error **errp) { PL011State *s =3D PL011(dev); =20 - qemu_chr_fe_set_handlers(&s->chr, pl011_can_receive, pl011_receive, - pl011_event, NULL, s, NULL, true); + pl011_set_handlers(s); } =20 static void pl011_reset(DeviceState *dev) --=20 2.43.0 From nobody Sat Sep 26 20:51:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268733; cv=none; d=zohomail.com; s=zohoarc; b=eszPEV/OzgvoOeOiX3aeaDTnOvOV/xSRyrEBog2teChcy1inMzmkMP53s9cPVmH2Dj2z3W0JTXBpZrlHJWi13MXD7Cp2/FNRxi3fw0S5Dgz2W+OHPIl7oUUAAMhR0VU1L39J87IyQQSa3mowmNXbWa9iTFWcqJCoiwL9tQnjSu0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268733; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=AuvITvHbmN25u273hcimyVG9B2jeI5oleKMoM9/dBbs=; b=fULpJfihWwecBn/31m/ihmBvenjU/31eXasPz7YdZ4b0bztzR0oqsM58DRQUDaPRxmkP+mNtu0r81NJunivcaO7iiWGK2vXSWbiRENTW8i8nsZ5eJbBVmuEQ02gzN9AgpuZTxHfOVZwMXygwueLK5BqSZlFV074aIK6H0wKufAg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268733700444.1621266303972; Tue, 1 Sep 2026 06:18:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ON0-0000wS-CT; Tue, 01 Sep 2026 09:17:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1OMu-0000vV-WA for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:41 -0400 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1OMs-00076m-B3 for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:39 -0400 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-c250c6a6a9aso749265466b.1 for ; Tue, 01 Sep 2026 06:17:37 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268656; x=1788873456; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=AuvITvHbmN25u273hcimyVG9B2jeI5oleKMoM9/dBbs=; b=fh1Kth3jh9zpV6zYEaDcwevVRiRqZ9l8dpyEtqmcW07TojxpFmJsNqu8LmGI3D1E2X 0NBh5FCbgzcq264e7NF45JbTr9cXiO/jdNYTztVmYyRIflM5Q52tgxdj2h9f4iz+c5nj eUVVUYukvlZEKreADHYl2QHFWIvEu1QgYo0RG3nIjLHUgVNuwAo/lsjatPFVRdLQ5iVT vrnVF/t10+LwfZiYex2U2B54Y4T5FKlwB53Dxxv+jtK4yOJczaF3gfovSDg3rjEAAICV 7vXeOHnuXq1hyYrEV2Zg9oQqhivjwkaU7Y+FeMGyUxi9nmWoAQraNCKdZjVBUagwysmQ 4Q1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268656; x=1788873456; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=AuvITvHbmN25u273hcimyVG9B2jeI5oleKMoM9/dBbs=; b=Ho62SOZkoV5K2uC1W2ccMJv5KPEYk9CdvtGuix+eusSWT9iJFREQ32jkN4MIvYtbKa 7iFAbKq4BxiUCg8gf8ohIXN5U1pUQV09uE6M/cyWwSE7FwX9/gJRFJSD8mx/K7vzKmog dgBO6ifYQrfplIrupQZE0Xm6cJolqAzdMDyXURpjylP1sucdv/4YkHv2KtW35mJgzWzI QGSZxs56jH+VTujH4sgx2AmBs62U+9Euodo/1aQYT3lEvtZPSMfX5y3boHpqD2a0CzYh yrxhOMRuwylHZE1kVXux8eYPAGwsJzl99nTNllXnMCNmZ83U+rpnw36puMdlvZ+Q6uN1 Mttw== X-Gm-Message-State: AFuF++kYByO53cX32K7dZJACzi7twfYFlbOw+M5WqkLkTxylkM4TLHm0 YoQLCyKJochXUSvmLK3Lp6kRoZWtISR9qT6LhbhAKyUu2Hf8nz3jtJyr0u/1Izo4Tk+SmWSJ9vC 0sQ2n6lc= X-Gm-Gg: AR+sD10sZQjoeloE9OBkHB6YhlyBtgc0+Yg0URUSc9Mm8Fj2pC19BzRNQLTIrPgLWik HGjpKK5+fQJGrLS78Ll8/8ZxPEV+5VG2yRzml65/4UoZDVmz8sCLJqXWnr0Kg0nbUx6vcO2l6Mj DnwnYxL+0seUx+FHysHKM0LERb7VTywvgtnYd3abOhn+QRd7Bt4Wc5M+p7mdvfz84/Nz8SEAIZB eXu61AHuxPyYol2T1Ik2MTKWNQJ0tERNgTnj5oN2+XgnHDAJ96n9BfbsAvLXbZSiOxP5qw1JloJ csH/fKIWglms5aWGTVflC3xI2ir1SJBVy39DsQFhi01HOLFosr1eAlmuu3mNSKzjxcivj4OXRFZ 1CinEs/M82KQc3+IVrIQdOiQ2xP4N41TjFxrALhZ4eCXCJk5KhyRKGlgHHryXp0IGjH5xgHy4Fh SUqhYEkBIVmwlJFYNfHKZ2hjrJoD9Nt5SZf54KPTACfFCcXBsX2n8BZAIcStzMpZq/VcojoGjSN dhDtiSJt3d3D8cTMrnIVd6XWhtII4e3fdcZJalRjTGu/SjoqqtRUM4EQgwnV1yAuGkrpw== X-Received: by 2002:a17:907:9945:b0:c25:5fa5:dea4 with SMTP id a640c23a62f3a-c25b3b80cecmr422144966b.4.1788268656375; Tue, 01 Sep 2026 06:17:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/58] target/arm: fix TTA instruction S bit for IDAU-exempt addresses Date: Tue, 1 Sep 2026 14:16:36 +0100 Message-ID: <20260901131732.2263947-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268735754154100 Content-Type: text/plain; charset="utf-8" From: Alexandre Frey The TTA (Test Target Alternate Domain) instruction is specific to ARMv8-M processors with the Security Extension (TrustZone). It allows Secure code to query the security attributes and access permissions of a memory address as seen from the Non-secure domain, and is typically used by Secure code to validate pointers received from Non-secure callers before dereferencing them. The TTA instruction incorrectly reports the S bit (bit 22) of the result register for IDAU-exempt addresses when executed from Secure state. According to the ARMv8-M Architecture Reference Manual (DDI0553B.z), the TTResp() pseudocode (E2.1.408) always calls SecurityCheck() with the current security state, regardless of the alt flag: sAttributes =3D SecurityCheck(address, FALSE, IsSecure()); The alt flag only affects which MPU bank is queried for the R/RW/MREGION fields. It does not affect the SAU/IDAU security attribute lookup that determines the S bit. For an IDAU-exempt address, SecurityCheck() (E2.1.366) sets: result.ns =3D !isSecure; // isSecure =3D current CPU security state So TTA executed from Secure state on an IDAU-exempt address should return S=3D1. This is confirmed by testing on real Cortex-M33 hardware. QEMU currently passes targetsec (which is flipped to !env->v7m.secure when alt=3Dtrue) to v8m_security_lookup(), causing the IDAU-exempt path to set sattrs->ns =3D TRUE and return S=3D0 instead. Fix this by always passing the current security state to v8m_security_lookup(), as the spec requires. Cc: qemu-stable@nongnu.org Fixes: 5158de241b0f ("target/arm: Implement TT instruction") (the is_secure argument to v8m_security_lookup() was only added in dbf2a71ad62b992 ("target/arm: Add is_secure parameter to v8m_security_lookup"), but the code before that implicitly had the equivalent bug.) Signed-off-by: Alexandre Frey Message-id: ZR6PR04MB44238851A057F385D7EECEAD3599AE2@ZR6PR04MB442388.eurprd= 04.prod.outlook.com Reviewed-by: Peter Maydell [PMM: added comment] Signed-off-by: Peter Maydell --- target/arm/tcg/m_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index f4ba93b291b..33c9e7c55bc 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -2869,8 +2869,9 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) } =20 if (env->v7m.secure) { + /* Note that security check is done as Secure even if alt is true = */ v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, - targetsec, &sattrs); + env->v7m.secure, &sattrs); nsr =3D sattrs.ns && r; nsrw =3D sattrs.ns && rw; } else { --=20 2.43.0 From nobody Sat Sep 26 20:51:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268796; cv=none; d=zohomail.com; s=zohoarc; b=EIFEZG8zL79loJ4KD32wDWolWsuxhm8KRntBPEvtkSBUwTFtKGBQp+VDOSXbRf0FdiFggL+KZyn8kOchgiC7z3b1Dy6k84H0sBJcXzPFuFgTQsH6w1V1MsklOmt38yCmZD4tm2cYTcAe6NBZ9C3QMCCo0ixW2gnZmql7nRzrnzs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268796; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=KvmZdE5sHZHsp8nQ4URbmqmTTXnudp+zBG9tJOq6/2M=; b=jNyfSd8NUNVoYki5pNCpiplyvqjVGU4NTwVBZBAnppyCeOhC84XcW4YO9e2Cg3tv+D7atAM1EHrNoywwgdcqxwdum3PpLtFZQukhjfVhFwmmjGYay32EH95HHBCIfUfVsM2w9ScugRu4fd50C+jpALY+sz4ol+coURdt4Cki5iw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268796641149.04969069535116; Tue, 1 Sep 2026 06:19:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1OMx-0000vv-W7; Tue, 01 Sep 2026 09:17:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1OMv-0000vY-9j for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:41 -0400 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1OMt-000774-HS for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:41 -0400 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-c252e703fa3so694917566b.3 for ; Tue, 01 Sep 2026 06:17:38 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268658; x=1788873458; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=KvmZdE5sHZHsp8nQ4URbmqmTTXnudp+zBG9tJOq6/2M=; b=Qun7uIPJWYbfTrQ7bCJkNzefhlLDsX/DywxdRRhRx48dO9p2yamlBQy6M72E9ZJGLa xQa7R4S5FuUjDA6SU8aCDWX68bqQMbDmnKHAtl0+L9FaQ76HYjZfTPnu5nNcJFa5uffH jBiVz/SV9zFIfLDa/w927m7Nk/OU9ooFOi6Z8EkoGAmL1IC2tVvSsAhdFkNA+9TY28nM wY3HB5JSRurLHg37HFhsy9tvzfNvBSOL1vdLZldwhkcawSStzXk0uguiOj7UJLhmcc0m PjzrrtxgzNpF5OzQGzhamDoUu0LHCJb5/ldYX6YJMXTU9Ljog1VpRQtXuRsKwydQxKiD m91g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268658; x=1788873458; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=KvmZdE5sHZHsp8nQ4URbmqmTTXnudp+zBG9tJOq6/2M=; b=dHnUYzGCH7whjOT/hZqWv1OFaSA4VY3GnO4Ym1wg3wAM2OeyglOGHVkO3R+kvkH2Qk IRDLXFXBgPFrxJEW7sENmefUCxkhGQCFxz0Q1fjcHIv4ZNxOUQLkl0pS1vsAVuIEb8vp pS9aFiUzyyhQj8x+ZecWVUj3vryAVRPhOrX2tUgojGYzvlSGU/ckRtWfsExl/ltaXIle WwV/5gXcvp0jQT+L26twbjwTJpsfMGZYbyQ1juKIuGkBNxa4i3czPnrK6NM/CbHTH1vW EzV3y7ZHn+txKFuX3Ase4e1LQWlqKAAz+R4iIlKpI4zmZiE3o6fK5lwCyL6RFjvBiXoC P9Sg== X-Gm-Message-State: AFuF++lcNzV7ist7TEK/PYIB1oHCjCFDrkCOz07ZKF2i4HZNj4O1BNpF srZomfm73uibvCReRNqW/GJyfXxgTdIorZAFHXfHSmyJHFcFvEMw+rf54hGI2M9Z08OXcV1GRT5 FevMhRL0= X-Gm-Gg: AR+sD11eYtCrUd73mIxYfzexwJH9gmvWzfxNULeDRtwFO0pKD8FKrK/yUrH7x1ESEKw 9rShTMJyrKgqIS+KRtihRl9PjuBOC4XkB9KsOBo7kZvYql+g5+6FiFU4VFqeRv9WxDGnq6jvUZA o62vaKH5W2GcpBs5/UO5EjRCZWlVcD39rq+F7YyxlExGuUgT2ob8LoeMzslJl4Gjzt6LrPe2MwK IE1jflXC4rgAp1Pjz0CQeD0k5CrAuExRMechx0NTcGsxj94QeHl4pBKWXpDLjmxpQWuMSa3CwxY TfJcIgPZF6/yFANUzPX9BUJ0PSzT/N2NUQqJShrTg+EnGmeE8/K+SAgVrzVo4YdC7snx2Bj5xba wL6krb/iPVn8OXpuXQl9LhHvu8R0z1vjCc/vLxB/smGWwgW1NSV3aZS1rnFfHcCpzxfIlx8OleF tz+rnXwAIt5BEWUIJSm7ITKaixJEcZdXusM9/R7GPxXe2nFV9rx0LZU4ZHt2J9QzzHxZtuwKiJU C7OLUXXxRP9JJB8ggOt3YdckWstEA1JpDRAhu6e7v/YfjEuJHi2puT1yNP5M6zIhvbkYp69Tm5g 6O2v X-Received: by 2002:a17:906:2545:b0:c25:977e:5377 with SMTP id a640c23a62f3a-c25b3bde234mr501456966b.10.1788268657757; Tue, 01 Sep 2026 06:17:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/58] target/arm: Correct reset value of SCTLR for arm926, arm1026 Date: Tue, 1 Sep 2026 14:16:37 +0100 Message-ID: <20260901131732.2263947-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268797321158500 Content-Type: text/plain; charset="utf-8" For the arm926 CPU we reset the SCTLR to 0x00090078. This is not the value specified in the ARM926EJ-S TRM (ARM DDI 0198E), which states that bits 16 and 18 are SBO, bit 17 is SBZ, and bits [31:19] are SBZ. It's also not the value seen on real hardware. Similarly, for the arm1026 we use the same SCTLR reset value but the TRM says that bits 18 and 16 are the SBO ones. This has been wrong in QEMU since 2007 when we first started actively resetting the SCTLR to some fixed value rather than zero. This wrong value didn't affect any of QEMU's behaviour, because we don't implement any handling of the old pre-v6 meanings of these bits (which were IMPDEF), and their v8 reuse is guarded by appropriate version checks. Correct the reset values to 0x00050078 (i.e set bit 18 and not 19). Cc: qemu-stable@nongnu.org Fixes: 610c3c8afd99f4f11 ("Reset ARM cp15.c1_sys to default values. Fix XSc= ale cp15 accesses.") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4202 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260821114138.4068582-1-peter.maydell@linaro.org --- target/arm/tcg/cpu32.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index bc07e33877a..241c1f5e966 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -33,7 +33,7 @@ static void arm926_initfn(Object *obj) cpu->midr =3D 0x41069265; cpu->reset_fpsid =3D 0x41011090; cpu->ctr =3D 0x1dd20d2; - cpu->reset_sctlr =3D 0x00090078; + cpu->reset_sctlr =3D 0x00050078; =20 /* * ARMv5 does not have the ID_ISAR registers, but we can still @@ -74,7 +74,7 @@ static void arm1026_initfn(Object *obj) cpu->midr =3D 0x4106a262; cpu->reset_fpsid =3D 0x410110a0; cpu->ctr =3D 0x1dd20d2; - cpu->reset_sctlr =3D 0x00090078; + cpu->reset_sctlr =3D 0x00050078; cpu->reset_auxcr =3D 1; =20 /* --=20 2.43.0 From nobody Sat Sep 26 20:51:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788269042; cv=none; d=zohomail.com; s=zohoarc; b=G6X2Oi8NXhoj63m+eCd6hwucsP1x7P9OqcxWHPJDWvoISw3SpLR+LRsTDxnQKfjdz6knHdUZA+SSc5LVPbyBqLkUSXRvwDHA+8xhdLdiGeUAzwMNXECvNbwD7ek4ZnB0vHGrLT+DDyGnDXrSLD4L3YcRqRXrd8/7PFlgWuQN4mo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788269042; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=rGk9086+658YDSmXaw95r1eVO+HDDXP2VbVahmR2kXM=; b=TSuItLs1LaCKtetMeJdd9nH+Je1tCnG5QlYn8YY73YPrzuETIocOo1Qthedh1ObqGQubO2yvGj+oQ56UHHTXMMyySAtdliKs9+4SeohrMxncDPL1fhwRCcUh2aq677/ED+6zzg1ysqLA43hWjj0RfuKhUJa55ei7TXsv/84WM5Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788269042417542.2096675339448; Tue, 1 Sep 2026 06:24:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ON3-0000xY-81; Tue, 01 Sep 2026 09:17:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1OMw-0000vw-UM for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:43 -0400 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1OMu-00077F-Oq for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:42 -0400 Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-c1712a04ddaso773481766b.2 for ; Tue, 01 Sep 2026 06:17:39 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268659; x=1788873459; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=rGk9086+658YDSmXaw95r1eVO+HDDXP2VbVahmR2kXM=; b=EJfhGbXV/wlDZRqW/bMtLf3g+O40gq8gYR0Ul+d/tpXdmNRGOBeaInHxdwoMSlA+xz Bgy5e3NhVZJjhM0HzrGHvPr8gPtg2FPhooNxX+e6yNct03dZA7gjjLfOK7SBzIyeuTSS hEr2MXC0IlTVml3EaAlgMDboEMBlkmEYcfTkS2bMedjcPA2FHTtSbhTe9IMyRjcVvKvN WuEyCSCYOL+TqX3A5BZOgiQcAsLoiwqsLHK0A0Cc9436kcvE1sdhSQD/wYjihyHpTzPY J4DLXHC1mqRIFbCniv1nwbO8aGzRlc7f0ZHxo7pOfoNh+mOH2+iyFoCY3WSO4TX6ebWF 7hbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268659; x=1788873459; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=rGk9086+658YDSmXaw95r1eVO+HDDXP2VbVahmR2kXM=; b=Sx/hCrqd6yQ6m2dcm22cbDDF5PRKiJOs3bMG8qUOISXVGrPRZVKzvRjh/YNup18WPV Lo0rL5BM2IHgdDA0UCDQJzqXiRkDhblckYYlmLUaijse1jHPcd26a1TMx54+tVD9qS75 RyCY/brJ+r4pNi2dchNoEpYQDTGvDVx5t2ymsQfYwl+lAYWUgb451ieE35tu3tuzL7Ot jaGtmmYtkVxvTVLuQ9D5wKZdnwE4P19UiKgy4qe6FPf87BpckOB70SKDAhIX8/tfQaDB 30cK1q2E9u6wavKN3RQgPfS8gpfQ48STItkkXC6LNjJnVnvBD/dT2urI5IFOBlJb46UI HRCA== X-Gm-Message-State: AFuF++lpLCpsQOcG8QejWHTHN+mTbzoaxrEjvr4S4FKtJ//t5y7Mxcsv 6MWh08DrW4pCzi5jEPIu6yjUTP09P3CGgStZvQ1wu3grk5XsW4Yv3scPaju8scJEuOW+IOTg7AA 8gRNP7Tc= X-Gm-Gg: AR+sD13Q1u7BJuBXnayHtSZK06LaQXsRw41OKTrr4uos/DqO58vkMs84LAql1tNcjfG RBUHdPjPzUPZ83HJVzq0Z7afw4LwUiuDzh8APN5pm5KUKq5VU4KcH1/QMEKRsT/K1vXe58DkUQO giTOUr1GmU1re4Mie5z5JCgyafN8JdaWb9GZ2cZRcAvtM31C0+EwvvimD6BOxXiyUykHinfKNPF TBJC5enFyrTOgjFjZgxi2yZOGvw+P5bf4b5pMgNd5mKJ+cLvu/lXTOLBP4FQ84JFBEJJQNVuAV5 vSWF9RqF2mry5ArsC52eGQUgtwB1PXrj7vSu+TAtsUT309vkjr7MLhD8bLhEeSV3sxweye9i25m ieu1qfg5BbD8X3SOHt1KcPO+R/hJWp24KOKqMKw1fHubltT192Nof/WJZifxFqODshUb00/x0S9 DQADKWZnnyQqBeghfX3VkBuv9q/5UHmP++uhkSyPrLVH61RHYLKba66N8fSUJishHY1hW4wOo95 jqzcj7NBPVc6B9aHF0pfk+Xjazc7KQHeT4+iYDNBblezyO+N6CuxtR8maGdS52uHRJTP392k8lA qi0L X-Received: by 2002:a17:906:9fc5:b0:c20:f4ee:7c97 with SMTP id a640c23a62f3a-c2556c19e06mr2196809066b.5.1788268658704; Tue, 01 Sep 2026 06:17:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/58] target/arm: Don't provide TLBTR for pre-v6 CPUs Date: Tue, 1 Sep 2026 14:16:38 +0100 Message-ID: <20260901131732.2263947-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269044903154100 Content-Type: text/plain; charset="utf-8" The TLBTR register (encoding cp15, 0, c0, c0, 3) is listed in the v7A Arm ARM appendix O as being present in v4 and v5 (section O.7.1, diagram "Organization of CP15 registers in an ARMv4 or ARMv5 VMSA implementation"). However, it isn't listed in the v5 Arm ARM, and checking individual TRMs for the arm926, arm1026, sa1100, sa1110 and ti925 shows that none of them implement it, so it seems much more likely that TLBTR was new for v6. It's also confirmed not to be present on a real arm926. Gate the register on ARM_FEATURE_V6 being present; this means that on pre-v6 cores the encoding will fall back to reporting the MIDR (due to the CP_ANY wildcarding), matching the hardware behaviour. We can also remove the "make id_tlbtr_reginfo r/w for strongarm and omap" code, because those CPUs are pre-v6 so won't be using that reginfo struct now. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4207 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260821120036.4161792-1-peter.maydell@linaro.org --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4f30a94ecd3..e10ec21a8cd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7353,7 +7353,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) id_cp_reginfo[i].access =3D PL1_RW; } id_mpuir_reginfo.access =3D PL1_RW; - id_tlbtr_reginfo.access =3D PL1_RW; } if (arm_feature(env, ARM_FEATURE_V8)) { define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); @@ -7364,7 +7363,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); } define_arm_cp_regs(cpu, id_cp_reginfo); - if (!arm_feature(env, ARM_FEATURE_PMSA)) { + if (arm_feature(env, ARM_FEATURE_V6) && + !arm_feature(env, ARM_FEATURE_PMSA)) { define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); } else if (arm_feature(env, ARM_FEATURE_PMSA) && arm_feature(env, ARM_FEATURE_V8)) { --=20 2.43.0 From nobody Sat Sep 26 20:51:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788269063; cv=none; d=zohomail.com; s=zohoarc; b=kDQ7flgHZs7aMY4lYuc8/qm6YxfNhpmhl2mgxxh4oSwfGa7idXjWlz4iuBLeLWDu55qs+izLtC63IU2Mqd+wuVnNcKr5nxjPPyvMchKozNfuC48et2qkwZKrTiL4hPxQcSbpcl1WsUXGAjtYLhM3DjEEVwaZKkAOKOivOt9un88= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788269063; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=LhK8ng4dHk6UGuzECtUXyM2fYusVOLIbD0caqcPUyD4=; b=TFnSLqZTrFJ5Sto+s7vw4xeQ3Ja0tEtkfXZG6SvKUVGsoJFxG4X+QsZV3tGnLiq6/2s4tawaPjh1NciKwU81YybOolyZMLB3KvpOMRjj5Baln0qB09Os0V+RLIqJ/M8J+h0S39BbDpk9W8zm/LDP/4Od/rWZlUjO/O6YrVjrAyE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788269063475204.49486879791448; Tue, 1 Sep 2026 06:24:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ON3-0000xH-6y; Tue, 01 Sep 2026 09:17:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1OMy-0000wD-M3 for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:45 -0400 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1OMw-00077U-MR for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:44 -0400 Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-c25420fe973so145314166b.0 for ; Tue, 01 Sep 2026 06:17:41 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268660; x=1788873460; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=LhK8ng4dHk6UGuzECtUXyM2fYusVOLIbD0caqcPUyD4=; b=htgroZ7D/A6KSrYGK6pPUIPKhgZwic3SEQN1WuJpu9j0yvt4Fm7vz7+vy1jBs0HSGb Ty3O3EHimR35u7Ea7z+N6/Fu7Wq9wNFyVOnuBrb8uk3adC9wGToKWztY/dJtlOtw5cuF OxcRsCyFNkUlUjj/aYU1NvbmlXf6/z9QR1RQjszrA6/qDagM+sFeCsW/rb2fF1ZKQDFs SE5yiFnYL2Z567PbpGfiNoaMr6sJzGThfZTaVwV1sauuQZhagPsmJ393cwNTey1uTTVJ ZqvR5hgpBUZqzuMJ5pZtT9WmwWWJKtdt303PL0QLZjwNefGjtmhwR9LlpYLA3q1V5hE+ w5Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268660; x=1788873460; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=LhK8ng4dHk6UGuzECtUXyM2fYusVOLIbD0caqcPUyD4=; b=n4Pm0bSNb6DLlhz66a6eY/FLzjQtzeYJ2O+PTskIFa8vo771cU0xfLCdBJHyeCksXa NYCCKbbG4bkTiO2drC9XY79XnigUHd6HWGTnSQGx44HbrI+xjzRJaGsCJAXaU1uMt9K2 KqgPRqTLEGj3qoDNT83cBPh4YZ8itee7WcCKx67QouKMGmHlaQtrBgzv+PoFW7fmIeIR TPHFJ1vGwFK2Ljdf9rOx99J+UkzGQb235aU00dmYFJCslWjddby5uKaU4MFTWEr6sAlO 4cvarsiJzembf6wj7E5Me3qm5prbHd5aoo0MgFWbqRBVySzCNmKSikE15OIG1sELOyiF 4hBg== X-Gm-Message-State: AFuF++kisf+/IUXXaT6PkZ5hZIKg9Sv5kmLemBtzrOY9oIgWK3zwD5UT UIO/i4UbYUmGP1ILeGvR/8kVECRuCK1TEgqBv8HQRvEKCqwBaDNmERk22ixkYV6Qh1hUNPnaga3 SpotDoAE= X-Gm-Gg: AR+sD11OXtz0+34daMZvpj0enAKlcwUcM7fJTO37mtFBgpcaSkZRZf0g9Gsc8zVGM9w GAm1iUZgNpo7z75/BiRrZgUjG8D46n5e8cNEc60Unc3SFWZqCNkkXZha8d3Ms6kWfzOR1Rtvzlc mIf3Gx1h2ASXCQfOkW7gJlPyTCQLWITLzA8FxHiXlT7rlpIAoDKQ0NR++rhlvODEJLgESFDSK8r GYxxRd6hmfQItxeeNsPM7PKl4+BxSyLTEnKvVno7qJAhiBCPJxDSELzRSpyYjuQmaLEERqR3nfe oILIDdXEhT8UmAQMjjD3VJBcrKoD39d6vLNVIJxPhonGmNwXnXCQcPBSyoYmY7aMHNQlyfPSgPq cKxDC4dlyf1hS637uzeShrwaAPUGo4YnTy+d7ozVO5CsDpikQdjpdGo29FflsWUOyh/FCqLk/UG E6UTUft29rnDdLOVyRxmwP/jEJzuq7T70iumdHkvtJG0VJyzDQ0Y8h8NaltCZ4M9/HsQfVkdpey QIvI6UzZHROfViexZsN/prIGMSFIYa1t9b0K7ZDaZGb8tDIWPU0unFjUpYXx/y9wIfp+A== X-Received: by 2002:a17:907:9286:b0:c1c:2007:298e with SMTP id a640c23a62f3a-c25575b3e98mr2181046266b.24.1788268659744; Tue, 01 Sep 2026 06:17:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/58] tests/qtest/pflash-cfi02-test: Don't use musicpal machine for testing Date: Tue, 1 Sep 2026 14:16:39 +0100 Message-ID: <20260901131732.2263947-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269065589158500 We currently use the musicpal machine for testing the pflash-cfi02 device. We'd like to remove that machine, so switch the tests to the sh4 r2d board type instead. We use r2d because it happens to have the same "2 bank" config that musicpal did. (Of our other options, xilinx-zynq-a9 has only a 1-bank setup so wouldn't allow the same range of testing, and the canon-a1100 board both doesn't support specifying a flash drive via -drive if=3Dpflash, plus it seems likely it too might be a candidate for deprecate-and-drop.) The r2d flash device is not quite the same config as the musicpal one: it has a different base address and size, and different ID values. So we need to update the test to match. Signed-off-by: Peter Maydell Acked-by: Jan Kiszka Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260819185430.3467629-2-peter.maydell@linaro.org --- tests/qtest/meson.build | 6 +++--- tests/qtest/pflash-cfi02-test.c | 38 ++++++++++++++++++++------------- 2 files changed, 26 insertions(+), 18 deletions(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index cbdef5a5455..6393b447754 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -198,7 +198,9 @@ qtests_ppc64 =3D \ (config_all_devices.has_key('CONFIG_USB_XHCI_NEC') ? ['usb-hcd-xhci-test= '] : []) + \ qtests_pci + ['migration-test', 'cpu-plug-test', 'drive_del-test'] =20 -qtests_sh4 =3D (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endia= nness-test'] : []) +qtests_sh4 =3D (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endia= nness-test'] : []) + \ + (config_all_devices.has_key('CONFIG_PFLASH_CFI02') and + config_all_devices.has_key('CONFIG_R2D') ? ['pflash-cfi02-test'] : []) qtests_sh4eb =3D (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['end= ianness-test'] : []) =20 qtests_sparc =3D ['prom-env-test', 'm48t59-test', 'boot-serial-test'] + \ @@ -245,8 +247,6 @@ qtests_arm =3D \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-time= r-test'] : []) + \ (config_all_devices.has_key('CONFIG_STELLARIS') or config_all_devices.has_key('CONFIG_MPS2') ? ['cmsdk-apb-watchdog-test']= : []) + \ - (config_all_devices.has_key('CONFIG_PFLASH_CFI02') and - config_all_devices.has_key('CONFIG_MUSICPAL') ? ['pflash-cfi02-test'] := []) + \ (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed : []) += \ (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ (config_all_devices.has_key('CONFIG_GENERIC_LOADER') ? ['hexloader-test'= ] : []) + \ diff --git a/tests/qtest/pflash-cfi02-test.c b/tests/qtest/pflash-cfi02-tes= t.c index 8c073efcb4b..fe630c9c168 100644 --- a/tests/qtest/pflash-cfi02-test.c +++ b/tests/qtest/pflash-cfi02-test.c @@ -11,17 +11,25 @@ #include "libqtest.h" =20 /* - * To test the pflash_cfi02 device, we run QEMU with the musicpal machine = with + * To test the pflash_cfi02 device, we run QEMU with the sh4 r2d machine w= ith * a pflash drive. This enables us to test some flash configurations, but = not * all. In particular, we're limited to a 16-bit wide flash device. */ =20 -#define MP_FLASH_SIZE_MAX (32 * 1024 * 1024) -#define BASE_ADDR (0x100000000ULL - MP_FLASH_SIZE_MAX) +/* + * These need to match the flash size and address in r2d.c. + * If the flash size changes then the sector_len[] and nb_blocs[] + * values in configuration[] below will need to be updated to match. + */ +#define BASE_ADDR 0x00000000 =20 -#define UNIFORM_FLASH_SIZE (8 * 1024 * 1024) +#define UNIFORM_FLASH_SIZE (16 * 1024 * 1024) #define UNIFORM_FLASH_SECTOR_SIZE (64 * 1024) =20 +/* These must match the id0, id1 args to pflash_cfi02_register() in r2d.c = */ +#define FLASH_ID0 0x0001 +#define FLASH_ID1 0x227E + /* Use a newtype to keep flash addresses separate from byte addresses. */ typedef struct { uint64_t addr; @@ -260,7 +268,7 @@ static void test_geometry(const void *opaque) { const FlashConfig *config =3D opaque; QTestState *qtest; - qtest =3D qtest_initf("-M musicpal" + qtest =3D qtest_initf("-M r2d" " -drive if=3Dpflash,file=3D%s,format=3Draw,copy-o= n-read=3Don" /* Device geometry properties. */ " -global driver=3Dcfi.pflash02," @@ -295,16 +303,16 @@ static void test_geometry(const void *opaque) /* Check the IDs. */ unlock(c); flash_cmd(c, UNLOCK0_ADDR, AUTOSELECT_CMD); - g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), =3D=3D, replicate(c, 0x= BF)); + g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), =3D=3D, replicate(c, FL= ASH_ID0)); if (c->bank_width >=3D 2) { /* - * XXX: The ID returned by the musicpal flash chip is 16 bits which + * XXX: The ID returned by the r2d flash chip is 16 bits which * wouldn't happen with an 8-bit device. It would probably be best= to * prohibit addresses larger than the device width in pflash_cfi02= .c, * but then we couldn't test smaller device widths at all. */ g_assert_cmphex(flash_query(c, FLASH_ADDR(1)), =3D=3D, - replicate(c, 0x236D)); + replicate(c, FLASH_ID1)); } reset(c); =20 @@ -436,7 +444,7 @@ static void test_geometry(const void *opaque) flash_cmd(c, FLASH_ADDR(0x5555), UNLOCK0_CMD); flash_cmd(c, FLASH_ADDR(0x2AAA), UNLOCK1_CMD); flash_cmd(c, FLASH_ADDR(0x5555), AUTOSELECT_CMD); - g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), =3D=3D, replicate(c, 0x= BF)); + g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), =3D=3D, replicate(c, FL= ASH_ID0)); reset(c); =20 /* @@ -580,7 +588,7 @@ static void test_cfi_in_autoselect(const void *opaque) { const FlashConfig *config =3D opaque; QTestState *qtest; - qtest =3D qtest_initf("-M musicpal" + qtest =3D qtest_initf("-M r2d" " -drive if=3Dpflash,file=3D%s,format=3Draw,copy-o= n-read=3Don", image_path); FlashConfig explicit_config =3D expand_config_defaults(config); @@ -590,7 +598,7 @@ static void test_cfi_in_autoselect(const void *opaque) /* 1. Enter autoselect. */ unlock(c); flash_cmd(c, UNLOCK0_ADDR, AUTOSELECT_CMD); - g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), =3D=3D, replicate(c, 0x= BF)); + g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), =3D=3D, replicate(c, FL= ASH_ID0)); =20 /* 2. Enter CFI. */ flash_cmd(c, CFI_ADDR, CFI_CMD); @@ -600,7 +608,7 @@ static void test_cfi_in_autoselect(const void *opaque) =20 /* 3. Exit CFI. */ reset(c); - g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), =3D=3D, replicate(c, 0x= BF)); + g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), =3D=3D, replicate(c, FL= ASH_ID0)); =20 qtest_quit(qtest); } @@ -613,7 +621,7 @@ static void cleanup(void *opaque) =20 /* * XXX: Tests are limited to bank_width =3D 2 for now because that's what - * hw/arm/musicpal.c has. + * hw/sh4/r2d.c has. */ static const FlashConfig configuration[] =3D { /* One x16 device. */ @@ -624,13 +632,13 @@ static const FlashConfig configuration[] =3D { { .bank_width =3D 2, .nb_blocs =3D { 127, 1, 2, 1 }, - .sector_len =3D { 0x10000, 0x08000, 0x02000, 0x04000 }, + .sector_len =3D { 0x20000, 0x10000, 0x04000, 0x08000 }, }, /* Nonuniform sectors (bottom boot). */ { .bank_width =3D 2, .nb_blocs =3D { 1, 2, 1, 127 }, - .sector_len =3D { 0x04000, 0x02000, 0x08000, 0x10000 }, + .sector_len =3D { 0x08000, 0x04000, 0x10000, 0x20000 }, }, }; =20 --=20 2.43.0 From nobody Sat Sep 26 20:51:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788269049; cv=none; d=zohomail.com; s=zohoarc; b=Te8yPNAITjKn/Kxyz+Pu1wGjNnmZ1QgRc5pZglqLBdgWhoiTyovxF10dwhW0mW0FPyi2oEdGvdVuL+5pZqFjqiFcsgMq6nGXrlYTPYbbNt4tQlyOE2aaqPB09uTXXm1TlYEfIY4MNpKu1mrG+i3RnRFX1BHe8XTxcBAGdecm22k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788269049; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=M0YLelMvdPY0PFJ+LIacPHO7n6wFdYWwaSVpnDcAu9k=; b=Yui3wsbPXqDD9nB4QaZ01fdZjQivmRek121VijbCaqMag+eV6XwHk/F4e7TzvsLabYu2iB+fuijZdHg7bVvE18ILmk7j/BBaoGQ3yp+5Yb6ljBmALDtc8nyMzKMSUmUfJtT0km/Db7GGWsaTGsUniioXrNa860LyWlWMlVWxux8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788269049850360.6556456259766; Tue, 1 Sep 2026 06:24:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ON1-0000wx-2d; Tue, 01 Sep 2026 09:17:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1OMy-0000w5-8I for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:44 -0400 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1OMw-00077o-Mk for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:43 -0400 Received: by mail-ed1-x52e.google.com with SMTP id 4fb4d7f45d1cf-6a0c8283146so390767a12.0 for ; Tue, 01 Sep 2026 06:17:41 -0700 (PDT) Received: from lanath.. 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Remove the spurious dependency. Signed-off-by: Peter Maydell Acked-by: Jan Kiszka Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260819185430.3467629-3-peter.maydell@linaro.org --- hw/arm/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 260d2f07516..5e9a0bd8dc6 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -155,7 +155,6 @@ config REALVIEW select ARM11MPCORE select ARM_TIMER select VERSATILE_PCI - select WM8750 # audio codec select LSI_SCSI_PCI select PCI select PL011 # UART --=20 2.43.0 From nobody Sat Sep 26 20:51:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788269083; cv=none; d=zohomail.com; s=zohoarc; b=UD+w2GFu0ZUYJtOfRWC6O+oPWjbE+TfYxlcdoo38MW9MuFklqf24+mqQFUE4/CybDovJHFtlLiXpwlzQMP8mUGe10AKU+IGR5w9qfcwaJecQYWF8kpsgzRSjKQ6FHMKp/mBLkw/wrz7OG1iY/zuTkczl8jnu0pNkXx1ukIEyc6k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788269083; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=JNJ7z8S7DJIAUzG77JFj1aY80rjNGHR1ahUwXjIaZpI=; b=BT2ocxndrww5QIR+XRf3+w0DxioNTJTSd/2NiFOFQJY/mA9Nkd3HshgFjZFwKhxV0BamqMsnhFqWR0ezqKBPUPcMBwWWux68AdzP1VNUot97P2AoJr48GxG4psm554grivzznOudL2TMZ+B2M8ZYp6XgLfa/m7mSgAowxQuNj1Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788269083176897.110113270987; Tue, 1 Sep 2026 06:24:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ON8-00010o-AI; Tue, 01 Sep 2026 09:17:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ON2-0000xX-MA for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:49 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1OMx-000787-Ny for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:48 -0400 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-c2020421077so714511166b.3 for ; Tue, 01 Sep 2026 06:17:43 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268662; x=1788873462; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=JNJ7z8S7DJIAUzG77JFj1aY80rjNGHR1ahUwXjIaZpI=; b=t8/f+GogFV1LbDRswocxE6FeYseMZmP9Ap57sWykg5nEOat2ESDQ+XhCwD6U02CTYx 6G0BI5SIDlG2BP7o2CTwcaKHCXlfNbTnt04pifQsYqQ2OYaa3Hv4VfIqRvOVM3c3Ns/F 7PxAFi1nJIvdIeHRh+gSLr5s7IiZGymTrvu8nyYlhjH9y3trP5O9Vo47qAVIpNu3B0tN ZQdV8MaGEvedXTHd9roAJsQmklYPgkR0IVhSq3Qybx7EMS19UQnNXUSfDGZimTXvQ60q DTQlMgOJ8+PJpP4rNdUabEyfJ9vF1HCTqid4q2KXR3RMVe1SUNAkP3TAXyH4ZWnMAB1s 1p8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268662; x=1788873462; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=JNJ7z8S7DJIAUzG77JFj1aY80rjNGHR1ahUwXjIaZpI=; b=MJOHTkKjXagdM+rriz3dUG8SL/DrXQTLi2sLXOa3GrRvg4WUodBmruXy0BBWqADFr8 tuXSng8AKfhFKMwsugor8JzVGgGNXW1TvLNNl9ECKCvUgcV3vDXxDbA4Cs7d8PlgDj3d OG/lFkullCzqqywN8/vDyVv2fNuDUQoKmQd9wLaIKTmPFT56a6ajOMvbTZbHF/TI9DfD YTQZSzfK577jMGnn/MdSCn7XfpC8wzN/pMUiIgJ15VJcb5XHZGcUxCri6Ct77nm7nRG3 bKN1d4AxjKPZJJdXOk3UJa/3VVkZfcvloRGtlEqupX/wNSrjrwg2S/GF9w24bc7OjUFQ DdKw== X-Gm-Message-State: AFuF++l/IMHakOLz8ObGbMzhxTpE5qPkX5jTnr7lXqKQ5sZo9r216ffQ zzwWyhjpOpt5e+AIIWed+DsTPKrz8Q2ywNw8543z64qcAlTN8Dn/ksqCu/zMozlDBUdfcCq97BA Uk7i0NZ8= X-Gm-Gg: AR+sD11J5hqc49idYEBUl3nw6E+qvLTD50dY+aKdMXIVTPxsZu7xqyGtAKsjhwcl20k Y79OK3MiUGcL/ssMBrC1snObBuaCaIDiXkBLMza1Jy/Btx6GvdLUSZCnIEwN6I6KCudE8LVWDYG jCLv79xeKElRisCZI1OB+SMl1mnnmDFQw2sKVqSqVNRMNSaiROaJCTyK13w1Mqp9Ps3CMB8gC9P lVAW5ahQRncRPBFl/+psQ29/MJTKM8BkrJGmZThVQ41bzHWkwyhUR3dv7PBSE8I5B+aC4zL8dFZ /HCMC0CULpOtAoJAsWj5072R3bCezPYZMNnMpKQgZPJIxswW6WXCyLcwkWPwPZ6K7IyOyOKXw6u p6HcBYzLJm1PNytn+x610iFBDYenPtJBpcYLIeAqOaxdgfl2V2noSk026LOJzHleiU12ZOjIVKI jy9DeyAQBgu8Ni3Q0HbMBdPYCQZvyrn8DcriVTRul+4NzX2aPVa3Nz16ZEmIUtMla/F266WQ8QY u/gESZ55iE5R3RFhe+jaBoEd8SZ38aPlZvxZ296IUbyfaqp14rEYOgm96CzU230sB2qsA== X-Received: by 2002:a17:907:c78f:b0:c24:e0dc:8b66 with SMTP id a640c23a62f3a-c2556c7d3a5mr2289180866b.6.1788268661915; Tue, 01 Sep 2026 06:17:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/58] hw/arm: Remove the 'musicpal' machine Date: Tue, 1 Sep 2026 14:16:41 +0100 Message-ID: <20260901131732.2263947-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269085648154100 The 'musicpal' machine emulates the Freecom MusicPal, which was an "internet radio" released in the mid-2000s. The stock system used a 2.6.16 Linux kernel, but as far as I'm aware, support for the hardware was never upstreamed to the mainline kernel. There are a number of reasons for deprecating this board: * The hardware is now solidly obsolete * It was never supported in mainline Linux * The SoC is a Marvell one with no public datasheet * The only QEMU changes to it have been the usual tree wide updates and refactoring work * The only bug report we've ever had about it has been one of the usual "bug found by static analysis" kind But in fact we can just drop it immediately, because in commit 59754f85ed35 ("target/arm: Do memory type alignment check when translation disabled") in 2024 we broke the boot of the standard firmware image for this board. (The image's u-boot does a LDRH to an unaligned address, which is UNPREDICTABLE; we used to let it through, but that commit makes it take a Data Abort, so the image crashes before it boots the kernel.) Since nobody complained, we can deduce that nobody's actually using this machine. Remove the machine proper, and note this in the docs. Devices used only by this board will be removed in subsequent commits. Signed-off-by: Peter Maydell Acked-by: Jan Kiszka Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260819185430.3467629-4-peter.maydell@linaro.org --- MAINTAINERS | 10 - configs/devices/arm-softmmu/default.mak | 1 - docs/about/removed-features.rst | 10 + docs/system/arm/musicpal.rst | 19 - docs/system/target-arm.rst | 1 - hw/arm/Kconfig | 12 - hw/arm/meson.build | 1 - hw/arm/musicpal.c | 1397 ----------------------- 8 files changed, 10 insertions(+), 1441 deletions(-) delete mode 100644 docs/system/arm/musicpal.rst delete mode 100644 hw/arm/musicpal.c diff --git a/MAINTAINERS b/MAINTAINERS index 4a49a40294e..a1830cdad15 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -995,16 +995,6 @@ S: Odd Fixes F: hw/arm/musca.c F: docs/system/arm/musca.rst =20 -Musicpal -M: Jan Kiszka -M: Peter Maydell -L: qemu-arm@nongnu.org -S: Odd Fixes -F: hw/arm/musicpal.c -F: hw/net/mv88w8618_eth.c -F: include/hw/net/mv88w8618_eth.h -F: docs/system/arm/musicpal.rst - Nuvoton NPCM7xx M: Tyrone Ting M: Hao Wu diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-= softmmu/default.mak index 71cf1645110..22caa6a63ef 100644 --- a/configs/devices/arm-softmmu/default.mak +++ b/configs/devices/arm-softmmu/default.mak @@ -14,7 +14,6 @@ # CONFIG_EXYNOS4=3Dn # CONFIG_INTEGRATOR=3Dn # CONFIG_FSL_IMX31=3Dn -# CONFIG_MUSICPAL=3Dn # CONFIG_MPS3R=3Dn # CONFIG_MUSCA=3Dn # CONFIG_SX1=3Dn diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.= rst index 0735b4ea1d5..6a9944a0c79 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -1251,6 +1251,16 @@ machine they want to use to avoid confusion. Existi= ng users of the ``spike`` machine must ensure that they're setting the ``spike`` machine in the command line (``-M spike``). =20 +Arm ``musicpal`` machine (removed in 11.2) +'''''''''''''''''''''''''''''''''''''''''' + +The ``musicpal`` machine was an emulation of the Freecom MusicPal, an +"internet radio" device from the mid-2000s. This hardware was never +supported in upstream Linux, was based on a Marvell SoC with no public +documentation, and is now obsolete. We accidentally broke booting this +board in 2024, without anybody noticing; it has therefore been removed +without a deprecation period. + linux-user mode CPUs -------------------- =20 diff --git a/docs/system/arm/musicpal.rst b/docs/system/arm/musicpal.rst deleted file mode 100644 index 9de380edf81..00000000000 --- a/docs/system/arm/musicpal.rst +++ /dev/null @@ -1,19 +0,0 @@ -Freecom MusicPal (``musicpal``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D - -The Freecom MusicPal internet radio emulation includes the following -elements: - -- Marvell MV88W8618 Arm core. - -- 32 MB RAM, 256 KB SRAM, 8 MB flash. - -- Up to 2 16550 UARTs - -- MV88W8xx8 Ethernet controller - -- MV88W8618 audio controller, WM8750 CODEC and mixer - -- 128x64 display with brightness control - -- 2 buttons, 2 navigation wheels with button function diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index e34492402f0..260cd7e4d6b 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -87,7 +87,6 @@ Board-specific documentation arm/cubieboard arm/emcraft-sf2 arm/exynos - arm/musicpal arm/kzm arm/nrf arm/nuvoton diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 5e9a0bd8dc6..57db2a2fdf8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -103,18 +103,6 @@ config MUSCA config MARVELL_88W8618 bool =20 -config MUSICPAL - bool - default y - depends on TCG && ARM - select OR_IRQ - select BITBANG_I2C - select MARVELL_88W8618 - select PTIMER - select PFLASH_CFI02 - select SERIAL_MM - select WM8750 - config NETDUINO2 bool default y diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 8ee5307a919..78acb04c8b9 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -6,7 +6,6 @@ arm_common_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: file= s('msf2-som.c')) arm_common_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.= c')) arm_common_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) arm_common_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c')) -arm_common_ss.add(when: 'CONFIG_MUSICPAL', if_true: [files('musicpal.c')]) arm_common_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinopl= us2.c')) arm_common_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex= -stm32-h405.c')) arm_common_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npc= m7xx_boards.c')) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c deleted file mode 100644 index 8a70ed7377e..00000000000 --- a/hw/arm/musicpal.c +++ /dev/null @@ -1,1397 +0,0 @@ -/* - * Marvell MV88W8618 / Freecom MusicPal emulation. - * - * Copyright (c) 2008 Jan Kiszka - * - * This code is licensed under the GNU GPL v2. - * - * Contributions after 2012-01-13 are licensed under the terms of the - * GNU GPL, version 2 or (at your option) any later version. - */ - -#include "qemu/osdep.h" -#include "qemu/units.h" -#include "qapi/error.h" -#include "hw/core/sysbus.h" -#include "migration/vmstate.h" -#include "hw/arm/boot.h" -#include "hw/arm/machines-qom.h" -#include "net/net.h" -#include "system/system.h" -#include "hw/core/boards.h" -#include "hw/char/serial-mm.h" -#include "qemu/timer.h" -#include "hw/core/ptimer.h" -#include "hw/core/qdev-properties.h" -#include "hw/block/flash.h" -#include "standard-headers/linux/input-event-codes.h" -#include "ui/console.h" -#include "hw/i2c/i2c.h" -#include "hw/i2c/bitbang_i2c.h" -#include "hw/core/irq.h" -#include "hw/core/or-irq.h" -#include "hw/audio/wm8750.h" -#include "system/block-backend.h" -#include "system/runstate.h" -#include "system/dma.h" -#include "ui/pixel_ops.h" -#include "qemu/cutils.h" -#include "qom/object.h" -#include "hw/net/mv88w8618_eth.h" -#include "qemu/error-report.h" -#include "target/arm/cpu-qom.h" - -#define MP_MISC_BASE 0x80002000 -#define MP_MISC_SIZE 0x00001000 - -#define MP_ETH_BASE 0x80008000 - -#define MP_WLAN_BASE 0x8000C000 -#define MP_WLAN_SIZE 0x00000800 - -#define MP_UART1_BASE 0x8000C840 -#define MP_UART2_BASE 0x8000C940 - -#define MP_GPIO_BASE 0x8000D000 -#define MP_GPIO_SIZE 0x00001000 - -#define MP_FLASHCFG_BASE 0x90006000 -#define MP_FLASHCFG_SIZE 0x00001000 - -#define MP_AUDIO_BASE 0x90007000 - -#define MP_PIC_BASE 0x90008000 -#define MP_PIC_SIZE 0x00001000 - -#define MP_PIT_BASE 0x90009000 -#define MP_PIT_SIZE 0x00001000 - -#define MP_LCD_BASE 0x9000c000 -#define MP_LCD_SIZE 0x00001000 - -#define MP_SRAM_BASE 0xC0000000 -#define MP_SRAM_SIZE 0x00020000 - -#define MP_RAM_DEFAULT_SIZE 32*1024*1024 -#define MP_FLASH_SIZE_MAX 32*1024*1024 - -#define MP_TIMER1_IRQ 4 -#define MP_TIMER2_IRQ 5 -#define MP_TIMER3_IRQ 6 -#define MP_TIMER4_IRQ 7 -#define MP_EHCI_IRQ 8 -#define MP_ETH_IRQ 9 -#define MP_UART_SHARED_IRQ 11 -#define MP_GPIO_IRQ 12 -#define MP_RTC_IRQ 28 -#define MP_AUDIO_IRQ 30 - -/* Wolfson 8750 I2C address */ -#define MP_WM_ADDR 0x1A - -/* LCD register offsets */ -#define MP_LCD_IRQCTRL 0x180 -#define MP_LCD_IRQSTAT 0x184 -#define MP_LCD_SPICTRL 0x1ac -#define MP_LCD_INST 0x1bc -#define MP_LCD_DATA 0x1c0 - -/* Mode magics */ -#define MP_LCD_SPI_DATA 0x00100011 -#define MP_LCD_SPI_CMD 0x00104011 -#define MP_LCD_SPI_INVALID 0x00000000 - -/* Commands */ -#define MP_LCD_INST_SETPAGE0 0xB0 -/* ... */ -#define MP_LCD_INST_SETPAGE7 0xB7 - -#define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ - -#define TYPE_MUSICPAL_LCD "musicpal_lcd" -OBJECT_DECLARE_SIMPLE_TYPE(musicpal_lcd_state, MUSICPAL_LCD) - -struct musicpal_lcd_state { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - MemoryRegion iomem; - uint32_t brightness; - uint32_t mode; - uint32_t irqctrl; - uint32_t page; - uint32_t page_off; - QemuConsole *con; - uint8_t video_ram[128*64/8]; -}; - -static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col) -{ - switch (s->brightness) { - case 7: - return col; - case 0: - return 0; - default: - return (col * s->brightness) / 7; - } -} - -static inline void set_lcd_pixel32(musicpal_lcd_state *s, - int x, int y, uint32_t col) -{ - int dx, dy; - DisplaySurface *surface =3D qemu_console_surface(s->con); - uint32_t *pixel =3D - &((uint32_t *) surface_data(surface))[(y * 128 * 3 + x) * 3]; - - for (dy =3D 0; dy < 3; dy++, pixel +=3D 127 * 3) { - for (dx =3D 0; dx < 3; dx++, pixel++) { - *pixel =3D col; - } - } -} - -static bool lcd_refresh(void *opaque) -{ - musicpal_lcd_state *s =3D opaque; - int x, y, col; - - col =3D rgb_to_pixel32(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0= xff), - scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff= ), - scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); - for (x =3D 0; x < 128; x++) { - for (y =3D 0; y < 64; y++) { - if (s->video_ram[x + (y / 8) * 128] & (1 << (y % 8))) { - set_lcd_pixel32(s, x, y, col); - } else { - set_lcd_pixel32(s, x, y, 0); - } - } - } - - qemu_console_update(s->con, 0, 0, 128*3, 64*3); - return true; -} - -static void lcd_invalidate(void *opaque) -{ -} - -static void musicpal_lcd_gpio_brightness_in(void *opaque, int irq, int lev= el) -{ - musicpal_lcd_state *s =3D opaque; - s->brightness &=3D ~(1 << irq); - s->brightness |=3D level << irq; -} - -static uint64_t musicpal_lcd_read(void *opaque, hwaddr offset, - unsigned size) -{ - musicpal_lcd_state *s =3D opaque; - - switch (offset) { - case MP_LCD_IRQCTRL: - return s->irqctrl; - - default: - return 0; - } -} - -static void musicpal_lcd_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - musicpal_lcd_state *s =3D opaque; - - switch (offset) { - case MP_LCD_IRQCTRL: - s->irqctrl =3D value; - break; - - case MP_LCD_SPICTRL: - if (value =3D=3D MP_LCD_SPI_DATA || value =3D=3D MP_LCD_SPI_CMD) { - s->mode =3D value; - } else { - s->mode =3D MP_LCD_SPI_INVALID; - } - break; - - case MP_LCD_INST: - if (value >=3D MP_LCD_INST_SETPAGE0 && value <=3D MP_LCD_INST_SETP= AGE7) { - s->page =3D value - MP_LCD_INST_SETPAGE0; - s->page_off =3D 0; - } - break; - - case MP_LCD_DATA: - if (s->mode =3D=3D MP_LCD_SPI_CMD) { - if (value >=3D MP_LCD_INST_SETPAGE0 && - value <=3D MP_LCD_INST_SETPAGE7) { - s->page =3D value - MP_LCD_INST_SETPAGE0; - s->page_off =3D 0; - } - } else if (s->mode =3D=3D MP_LCD_SPI_DATA) { - s->video_ram[s->page*128 + s->page_off] =3D value; - s->page_off =3D (s->page_off + 1) & 127; - } - break; - } -} - -static const MemoryRegionOps musicpal_lcd_ops =3D { - .read =3D musicpal_lcd_read, - .write =3D musicpal_lcd_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -static const GraphicHwOps musicpal_gfx_ops =3D { - .invalidate =3D lcd_invalidate, - .gfx_update =3D lcd_refresh, -}; - -static void musicpal_lcd_realize(DeviceState *dev, Error **errp) -{ - musicpal_lcd_state *s =3D MUSICPAL_LCD(dev); - s->con =3D qemu_graphic_console_create(dev, 0, &musicpal_gfx_ops, s); - qemu_console_resize(s->con, 128 * 3, 64 * 3); -} - -static void musicpal_lcd_init(Object *obj) -{ - SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); - DeviceState *dev =3D DEVICE(sbd); - musicpal_lcd_state *s =3D MUSICPAL_LCD(dev); - - s->brightness =3D 7; - - memory_region_init_io(&s->iomem, obj, &musicpal_lcd_ops, s, - "musicpal-lcd", MP_LCD_SIZE); - sysbus_init_mmio(sbd, &s->iomem); - - qdev_init_gpio_in(dev, musicpal_lcd_gpio_brightness_in, 3); -} - -static const VMStateDescription musicpal_lcd_vmsd =3D { - .name =3D "musicpal_lcd", - .version_id =3D 1, - .minimum_version_id =3D 1, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(brightness, musicpal_lcd_state), - VMSTATE_UINT32(mode, musicpal_lcd_state), - VMSTATE_UINT32(irqctrl, musicpal_lcd_state), - VMSTATE_UINT32(page, musicpal_lcd_state), - VMSTATE_UINT32(page_off, musicpal_lcd_state), - VMSTATE_BUFFER(video_ram, musicpal_lcd_state), - VMSTATE_END_OF_LIST() - } -}; - -static void musicpal_lcd_class_init(ObjectClass *klass, const void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->vmsd =3D &musicpal_lcd_vmsd; - dc->realize =3D musicpal_lcd_realize; -} - -static const TypeInfo musicpal_lcd_info =3D { - .name =3D TYPE_MUSICPAL_LCD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(musicpal_lcd_state), - .instance_init =3D musicpal_lcd_init, - .class_init =3D musicpal_lcd_class_init, -}; - -/* PIC register offsets */ -#define MP_PIC_STATUS 0x00 -#define MP_PIC_ENABLE_SET 0x08 -#define MP_PIC_ENABLE_CLR 0x0C - -#define TYPE_MV88W8618_PIC "mv88w8618_pic" -OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_pic_state, MV88W8618_PIC) - -struct mv88w8618_pic_state { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - MemoryRegion iomem; - uint32_t level; - uint32_t enabled; - qemu_irq parent_irq; -}; - -static void mv88w8618_pic_update(mv88w8618_pic_state *s) -{ - qemu_set_irq(s->parent_irq, (s->level & s->enabled)); -} - -static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) -{ - mv88w8618_pic_state *s =3D opaque; - - if (level) { - s->level |=3D 1 << irq; - } else { - s->level &=3D ~(1 << irq); - } - mv88w8618_pic_update(s); -} - -static uint64_t mv88w8618_pic_read(void *opaque, hwaddr offset, - unsigned size) -{ - mv88w8618_pic_state *s =3D opaque; - - switch (offset) { - case MP_PIC_STATUS: - return s->level & s->enabled; - - default: - return 0; - } -} - -static void mv88w8618_pic_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - mv88w8618_pic_state *s =3D opaque; - - switch (offset) { - case MP_PIC_ENABLE_SET: - s->enabled |=3D value; - break; - - case MP_PIC_ENABLE_CLR: - s->enabled &=3D ~value; - s->level &=3D ~value; - break; - } - mv88w8618_pic_update(s); -} - -static void mv88w8618_pic_reset(DeviceState *d) -{ - mv88w8618_pic_state *s =3D MV88W8618_PIC(d); - - s->level =3D 0; - s->enabled =3D 0; -} - -static const MemoryRegionOps mv88w8618_pic_ops =3D { - .read =3D mv88w8618_pic_read, - .write =3D mv88w8618_pic_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -static void mv88w8618_pic_init(Object *obj) -{ - SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); - mv88w8618_pic_state *s =3D MV88W8618_PIC(dev); - - qdev_init_gpio_in(DEVICE(dev), mv88w8618_pic_set_irq, 32); - sysbus_init_irq(dev, &s->parent_irq); - memory_region_init_io(&s->iomem, obj, &mv88w8618_pic_ops, s, - "musicpal-pic", MP_PIC_SIZE); - sysbus_init_mmio(dev, &s->iomem); -} - -static const VMStateDescription mv88w8618_pic_vmsd =3D { - .name =3D "mv88w8618_pic", - .version_id =3D 1, - .minimum_version_id =3D 1, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(level, mv88w8618_pic_state), - VMSTATE_UINT32(enabled, mv88w8618_pic_state), - VMSTATE_END_OF_LIST() - } -}; - -static void mv88w8618_pic_class_init(ObjectClass *klass, const void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - device_class_set_legacy_reset(dc, mv88w8618_pic_reset); - dc->vmsd =3D &mv88w8618_pic_vmsd; -} - -static const TypeInfo mv88w8618_pic_info =3D { - .name =3D TYPE_MV88W8618_PIC, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(mv88w8618_pic_state), - .instance_init =3D mv88w8618_pic_init, - .class_init =3D mv88w8618_pic_class_init, -}; - -/* PIT register offsets */ -#define MP_PIT_TIMER1_LENGTH 0x00 -/* ... */ -#define MP_PIT_TIMER4_LENGTH 0x0C -#define MP_PIT_CONTROL 0x10 -#define MP_PIT_TIMER1_VALUE 0x14 -/* ... */ -#define MP_PIT_TIMER4_VALUE 0x20 -#define MP_BOARD_RESET 0x34 - -/* Magic board reset value (probably some watchdog behind it) */ -#define MP_BOARD_RESET_MAGIC 0x10000 - -typedef struct mv88w8618_timer_state { - ptimer_state *ptimer; - uint32_t limit; - int freq; - qemu_irq irq; -} mv88w8618_timer_state; - -#define TYPE_MV88W8618_PIT "mv88w8618_pit" -OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_pit_state, MV88W8618_PIT) - -struct mv88w8618_pit_state { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - MemoryRegion iomem; - mv88w8618_timer_state timer[4]; -}; - -static void mv88w8618_timer_tick(void *opaque) -{ - mv88w8618_timer_state *s =3D opaque; - - qemu_irq_raise(s->irq); -} - -static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state = *s, - uint32_t freq) -{ - sysbus_init_irq(dev, &s->irq); - s->freq =3D freq; - - s->ptimer =3D ptimer_init(mv88w8618_timer_tick, s, PTIMER_POLICY_LEGAC= Y); -} - -static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, - unsigned size) -{ - mv88w8618_pit_state *s =3D opaque; - mv88w8618_timer_state *t; - - switch (offset) { - case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE: - t =3D &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2]; - return ptimer_get_count(t->ptimer); - - default: - return 0; - } -} - -static void mv88w8618_pit_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - mv88w8618_pit_state *s =3D opaque; - mv88w8618_timer_state *t; - int i; - - switch (offset) { - case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH: - t =3D &s->timer[offset >> 2]; - t->limit =3D value; - ptimer_transaction_begin(t->ptimer); - if (t->limit > 0) { - ptimer_set_limit(t->ptimer, t->limit, 1); - } else { - ptimer_stop(t->ptimer); - } - ptimer_transaction_commit(t->ptimer); - break; - - case MP_PIT_CONTROL: - for (i =3D 0; i < 4; i++) { - t =3D &s->timer[i]; - ptimer_transaction_begin(t->ptimer); - if (value & 0xf && t->limit > 0) { - ptimer_set_limit(t->ptimer, t->limit, 0); - ptimer_set_freq(t->ptimer, t->freq); - ptimer_run(t->ptimer, 0); - } else { - ptimer_stop(t->ptimer); - } - ptimer_transaction_commit(t->ptimer); - value >>=3D 4; - } - break; - - case MP_BOARD_RESET: - if (value =3D=3D MP_BOARD_RESET_MAGIC) { - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); - } - break; - } -} - -static void mv88w8618_pit_reset(DeviceState *d) -{ - mv88w8618_pit_state *s =3D MV88W8618_PIT(d); - int i; - - for (i =3D 0; i < 4; i++) { - mv88w8618_timer_state *t =3D &s->timer[i]; - ptimer_transaction_begin(t->ptimer); - ptimer_stop(t->ptimer); - ptimer_transaction_commit(t->ptimer); - t->limit =3D 0; - } -} - -static const MemoryRegionOps mv88w8618_pit_ops =3D { - .read =3D mv88w8618_pit_read, - .write =3D mv88w8618_pit_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -static void mv88w8618_pit_init(Object *obj) -{ - SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); - mv88w8618_pit_state *s =3D MV88W8618_PIT(dev); - int i; - - /* Letting them all run at 1 MHz is likely just a pragmatic - * simplification. */ - for (i =3D 0; i < 4; i++) { - mv88w8618_timer_init(dev, &s->timer[i], 1000000); - } - - memory_region_init_io(&s->iomem, obj, &mv88w8618_pit_ops, s, - "musicpal-pit", MP_PIT_SIZE); - sysbus_init_mmio(dev, &s->iomem); -} - -static void mv88w8618_pit_finalize(Object *obj) -{ - SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); - mv88w8618_pit_state *s =3D MV88W8618_PIT(dev); - int i; - - for (i =3D 0; i < 4; i++) { - ptimer_free(s->timer[i].ptimer); - } -} - -static const VMStateDescription mv88w8618_timer_vmsd =3D { - .name =3D "timer", - .version_id =3D 1, - .minimum_version_id =3D 1, - .fields =3D (const VMStateField[]) { - VMSTATE_PTIMER(ptimer, mv88w8618_timer_state), - VMSTATE_UINT32(limit, mv88w8618_timer_state), - VMSTATE_END_OF_LIST() - } -}; - -static const VMStateDescription mv88w8618_pit_vmsd =3D { - .name =3D "mv88w8618_pit", - .version_id =3D 1, - .minimum_version_id =3D 1, - .fields =3D (const VMStateField[]) { - VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1, - mv88w8618_timer_vmsd, mv88w8618_timer_state), - VMSTATE_END_OF_LIST() - } -}; - -static void mv88w8618_pit_class_init(ObjectClass *klass, const void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - device_class_set_legacy_reset(dc, mv88w8618_pit_reset); - dc->vmsd =3D &mv88w8618_pit_vmsd; -} - -static const TypeInfo mv88w8618_pit_info =3D { - .name =3D TYPE_MV88W8618_PIT, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(mv88w8618_pit_state), - .instance_init =3D mv88w8618_pit_init, - .instance_finalize =3D mv88w8618_pit_finalize, - .class_init =3D mv88w8618_pit_class_init, -}; - -/* Flash config register offsets */ -#define MP_FLASHCFG_CFGR0 0x04 - -#define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg" -OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_flashcfg_state, MV88W8618_FLASHCFG) - -struct mv88w8618_flashcfg_state { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - MemoryRegion iomem; - uint32_t cfgr0; -}; - -static uint64_t mv88w8618_flashcfg_read(void *opaque, - hwaddr offset, - unsigned size) -{ - mv88w8618_flashcfg_state *s =3D opaque; - - switch (offset) { - case MP_FLASHCFG_CFGR0: - return s->cfgr0; - - default: - return 0; - } -} - -static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - mv88w8618_flashcfg_state *s =3D opaque; - - switch (offset) { - case MP_FLASHCFG_CFGR0: - s->cfgr0 =3D value; - break; - } -} - -static const MemoryRegionOps mv88w8618_flashcfg_ops =3D { - .read =3D mv88w8618_flashcfg_read, - .write =3D mv88w8618_flashcfg_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -static void mv88w8618_flashcfg_init(Object *obj) -{ - SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); - mv88w8618_flashcfg_state *s =3D MV88W8618_FLASHCFG(dev); - - s->cfgr0 =3D 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ - memory_region_init_io(&s->iomem, obj, &mv88w8618_flashcfg_ops, s, - "musicpal-flashcfg", MP_FLASHCFG_SIZE); - sysbus_init_mmio(dev, &s->iomem); -} - -static const VMStateDescription mv88w8618_flashcfg_vmsd =3D { - .name =3D "mv88w8618_flashcfg", - .version_id =3D 1, - .minimum_version_id =3D 1, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state), - VMSTATE_END_OF_LIST() - } -}; - -static void mv88w8618_flashcfg_class_init(ObjectClass *klass, const void *= data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->vmsd =3D &mv88w8618_flashcfg_vmsd; -} - -static const TypeInfo mv88w8618_flashcfg_info =3D { - .name =3D TYPE_MV88W8618_FLASHCFG, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(mv88w8618_flashcfg_state), - .instance_init =3D mv88w8618_flashcfg_init, - .class_init =3D mv88w8618_flashcfg_class_init, -}; - -/* Misc register offsets */ -#define MP_MISC_BOARD_REVISION 0x18 - -#define MP_BOARD_REVISION 0x31 - -struct MusicPalMiscState { - SysBusDevice parent_obj; - MemoryRegion iomem; -}; - -#define TYPE_MUSICPAL_MISC "musicpal-misc" -OBJECT_DECLARE_SIMPLE_TYPE(MusicPalMiscState, MUSICPAL_MISC) - -static uint64_t musicpal_misc_read(void *opaque, hwaddr offset, - unsigned size) -{ - switch (offset) { - case MP_MISC_BOARD_REVISION: - return MP_BOARD_REVISION; - - default: - return 0; - } -} - -static void musicpal_misc_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ -} - -static const MemoryRegionOps musicpal_misc_ops =3D { - .read =3D musicpal_misc_read, - .write =3D musicpal_misc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -static void musicpal_misc_init(Object *obj) -{ - SysBusDevice *sd =3D SYS_BUS_DEVICE(obj); - MusicPalMiscState *s =3D MUSICPAL_MISC(obj); - - memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_misc_ops, NULL, - "musicpal-misc", MP_MISC_SIZE); - sysbus_init_mmio(sd, &s->iomem); -} - -static const TypeInfo musicpal_misc_info =3D { - .name =3D TYPE_MUSICPAL_MISC, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_init =3D musicpal_misc_init, - .instance_size =3D sizeof(MusicPalMiscState), -}; - -/* WLAN register offsets */ -#define MP_WLAN_MAGIC1 0x11c -#define MP_WLAN_MAGIC2 0x124 - -static uint64_t mv88w8618_wlan_read(void *opaque, hwaddr offset, - unsigned size) -{ - switch (offset) { - /* Workaround to allow loading the binary-only wlandrv.ko crap - * from the original Freecom firmware. */ - case MP_WLAN_MAGIC1: - return ~3; - case MP_WLAN_MAGIC2: - return -1; - - default: - return 0; - } -} - -static void mv88w8618_wlan_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ -} - -static const MemoryRegionOps mv88w8618_wlan_ops =3D { - .read =3D mv88w8618_wlan_read, - .write =3Dmv88w8618_wlan_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -static void mv88w8618_wlan_realize(DeviceState *dev, Error **errp) -{ - MemoryRegion *iomem =3D g_new(MemoryRegion, 1); - - memory_region_init_io(iomem, OBJECT(dev), &mv88w8618_wlan_ops, NULL, - "musicpal-wlan", MP_WLAN_SIZE); - sysbus_init_mmio(SYS_BUS_DEVICE(dev), iomem); -} - -/* GPIO register offsets */ -#define MP_GPIO_OE_LO 0x008 -#define MP_GPIO_OUT_LO 0x00c -#define MP_GPIO_IN_LO 0x010 -#define MP_GPIO_IER_LO 0x014 -#define MP_GPIO_IMR_LO 0x018 -#define MP_GPIO_ISR_LO 0x020 -#define MP_GPIO_OE_HI 0x508 -#define MP_GPIO_OUT_HI 0x50c -#define MP_GPIO_IN_HI 0x510 -#define MP_GPIO_IER_HI 0x514 -#define MP_GPIO_IMR_HI 0x518 -#define MP_GPIO_ISR_HI 0x520 - -/* GPIO bits & masks */ -#define MP_GPIO_LCD_BRIGHTNESS 0x00070000 -#define MP_GPIO_I2C_DATA_BIT 29 -#define MP_GPIO_I2C_CLOCK_BIT 30 - -/* LCD brightness bits in GPIO_OE_HI */ -#define MP_OE_LCD_BRIGHTNESS 0x0007 - -#define TYPE_MUSICPAL_GPIO "musicpal_gpio" -OBJECT_DECLARE_SIMPLE_TYPE(musicpal_gpio_state, MUSICPAL_GPIO) - -struct musicpal_gpio_state { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - MemoryRegion iomem; - uint32_t lcd_brightness; - uint32_t out_state; - uint32_t in_state; - uint32_t ier; - uint32_t imr; - uint32_t isr; - qemu_irq irq; - qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */ -}; - -static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { - int i; - uint32_t brightness; - - /* compute brightness ratio */ - switch (s->lcd_brightness) { - case 0x00000007: - brightness =3D 0; - break; - - case 0x00020000: - brightness =3D 1; - break; - - case 0x00020001: - brightness =3D 2; - break; - - case 0x00040000: - brightness =3D 3; - break; - - case 0x00010006: - brightness =3D 4; - break; - - case 0x00020005: - brightness =3D 5; - break; - - case 0x00040003: - brightness =3D 6; - break; - - case 0x00030004: - default: - brightness =3D 7; - } - - /* set lcd brightness GPIOs */ - for (i =3D 0; i <=3D 2; i++) { - qemu_set_irq(s->out[i], (brightness >> i) & 1); - } -} - -static void musicpal_gpio_pin_event(void *opaque, int pin, int level) -{ - musicpal_gpio_state *s =3D opaque; - uint32_t mask =3D 1 << pin; - uint32_t delta =3D level << pin; - uint32_t old =3D s->in_state & mask; - - s->in_state &=3D ~mask; - s->in_state |=3D delta; - - if ((old ^ delta) && - ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { - s->isr =3D mask; - qemu_irq_raise(s->irq); - } -} - -static uint64_t musicpal_gpio_read(void *opaque, hwaddr offset, - unsigned size) -{ - musicpal_gpio_state *s =3D opaque; - - switch (offset) { - case MP_GPIO_OE_HI: /* used for LCD brightness control */ - return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS; - - case MP_GPIO_OUT_LO: - return s->out_state & 0xFFFF; - case MP_GPIO_OUT_HI: - return s->out_state >> 16; - - case MP_GPIO_IN_LO: - return s->in_state & 0xFFFF; - case MP_GPIO_IN_HI: - return s->in_state >> 16; - - case MP_GPIO_IER_LO: - return s->ier & 0xFFFF; - case MP_GPIO_IER_HI: - return s->ier >> 16; - - case MP_GPIO_IMR_LO: - return s->imr & 0xFFFF; - case MP_GPIO_IMR_HI: - return s->imr >> 16; - - case MP_GPIO_ISR_LO: - return s->isr & 0xFFFF; - case MP_GPIO_ISR_HI: - return s->isr >> 16; - - default: - return 0; - } -} - -static void musicpal_gpio_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - musicpal_gpio_state *s =3D opaque; - switch (offset) { - case MP_GPIO_OE_HI: /* used for LCD brightness control */ - s->lcd_brightness =3D (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS)= | - (value & MP_OE_LCD_BRIGHTNESS); - musicpal_gpio_brightness_update(s); - break; - - case MP_GPIO_OUT_LO: - s->out_state =3D (s->out_state & 0xFFFF0000) | (value & 0xFFFF); - break; - case MP_GPIO_OUT_HI: - s->out_state =3D (s->out_state & 0xFFFF) | (value << 16); - s->lcd_brightness =3D (s->lcd_brightness & 0xFFFF) | - (s->out_state & MP_GPIO_LCD_BRIGHTNESS); - musicpal_gpio_brightness_update(s); - qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1= ); - qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & = 1); - break; - - case MP_GPIO_IER_LO: - s->ier =3D (s->ier & 0xFFFF0000) | (value & 0xFFFF); - break; - case MP_GPIO_IER_HI: - s->ier =3D (s->ier & 0xFFFF) | (value << 16); - break; - - case MP_GPIO_IMR_LO: - s->imr =3D (s->imr & 0xFFFF0000) | (value & 0xFFFF); - break; - case MP_GPIO_IMR_HI: - s->imr =3D (s->imr & 0xFFFF) | (value << 16); - break; - } -} - -static const MemoryRegionOps musicpal_gpio_ops =3D { - .read =3D musicpal_gpio_read, - .write =3D musicpal_gpio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -static void musicpal_gpio_reset(DeviceState *d) -{ - musicpal_gpio_state *s =3D MUSICPAL_GPIO(d); - - s->lcd_brightness =3D 0; - s->out_state =3D 0; - s->in_state =3D 0xffffffff; - s->ier =3D 0; - s->imr =3D 0; - s->isr =3D 0; -} - -static void musicpal_gpio_init(Object *obj) -{ - SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); - DeviceState *dev =3D DEVICE(sbd); - musicpal_gpio_state *s =3D MUSICPAL_GPIO(dev); - - sysbus_init_irq(sbd, &s->irq); - - memory_region_init_io(&s->iomem, obj, &musicpal_gpio_ops, s, - "musicpal-gpio", MP_GPIO_SIZE); - sysbus_init_mmio(sbd, &s->iomem); - - qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); - - qdev_init_gpio_in(dev, musicpal_gpio_pin_event, 32); -} - -static const VMStateDescription musicpal_gpio_vmsd =3D { - .name =3D "musicpal_gpio", - .version_id =3D 1, - .minimum_version_id =3D 1, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state), - VMSTATE_UINT32(out_state, musicpal_gpio_state), - VMSTATE_UINT32(in_state, musicpal_gpio_state), - VMSTATE_UINT32(ier, musicpal_gpio_state), - VMSTATE_UINT32(imr, musicpal_gpio_state), - VMSTATE_UINT32(isr, musicpal_gpio_state), - VMSTATE_END_OF_LIST() - } -}; - -static void musicpal_gpio_class_init(ObjectClass *klass, const void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - device_class_set_legacy_reset(dc, musicpal_gpio_reset); - dc->vmsd =3D &musicpal_gpio_vmsd; -} - -static const TypeInfo musicpal_gpio_info =3D { - .name =3D TYPE_MUSICPAL_GPIO, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(musicpal_gpio_state), - .instance_init =3D musicpal_gpio_init, - .class_init =3D musicpal_gpio_class_init, -}; - -/* Keyboard codes & masks */ -#define MP_KEY_WHEEL_VOL (1 << 0) -#define MP_KEY_WHEEL_VOL_INV (1 << 1) -#define MP_KEY_WHEEL_NAV (1 << 2) -#define MP_KEY_WHEEL_NAV_INV (1 << 3) -#define MP_KEY_BTN_FAVORITS (1 << 4) -#define MP_KEY_BTN_MENU (1 << 5) -#define MP_KEY_BTN_VOLUME (1 << 6) -#define MP_KEY_BTN_NAVIGATION (1 << 7) - -#define TYPE_MUSICPAL_KEY "musicpal_key" -OBJECT_DECLARE_SIMPLE_TYPE(musicpal_key_state, MUSICPAL_KEY) - -struct musicpal_key_state { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - QemuInputHandlerState *hs; - uint32_t pressed_keys; - qemu_irq out[8]; -}; - -static void musicpal_key_event(DeviceState *dev, QemuConsole *src, - QemuInputEvent *evt) -{ - musicpal_key_state *s =3D MUSICPAL_KEY(dev); - uint32_t event =3D 0; - int i; - - switch (evt->key.key) { - case KEY_UP: - event =3D MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; - break; - - case KEY_DOWN: - event =3D MP_KEY_WHEEL_NAV; - break; - - case KEY_LEFT: - event =3D MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; - break; - - case KEY_RIGHT: - event =3D MP_KEY_WHEEL_VOL; - break; - - case KEY_F: - event =3D MP_KEY_BTN_FAVORITS; - break; - - case KEY_TAB: - event =3D MP_KEY_BTN_VOLUME; - break; - - case KEY_ENTER: - event =3D MP_KEY_BTN_NAVIGATION; - break; - - case KEY_M: - event =3D MP_KEY_BTN_MENU; - break; - } - - /* - * We allow repeated wheel-events when the arrow keys are held down, - * but do not repeat already-pressed buttons for the other key inputs. - */ - if (!(event & (MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_VOL))) { - if (evt->key.down && (s->pressed_keys & event)) { - event =3D 0; - } - } - - if (event) { - /* Raise GPIO pin first if repeating a key */ - if (evt->key.down && (s->pressed_keys & event)) { - for (i =3D 0; i <=3D 7; i++) { - if (event & (1 << i)) { - qemu_set_irq(s->out[i], 1); - } - } - } - for (i =3D 0; i <=3D 7; i++) { - if (event & (1 << i)) { - qemu_set_irq(s->out[i], !evt->key.down); - } - } - if (evt->key.down) { - s->pressed_keys |=3D event; - } else { - s->pressed_keys &=3D ~event; - } - } -} - -static void musicpal_key_init(Object *obj) -{ - SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); - DeviceState *dev =3D DEVICE(sbd); - musicpal_key_state *s =3D MUSICPAL_KEY(dev); - - s->pressed_keys =3D 0; - - qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); -} - -static const QemuInputHandler musicpal_key_handler =3D { - .name =3D "musicpal_key", - .mask =3D INPUT_EVENT_MASK_KEY, - .event =3D musicpal_key_event, -}; - -static void musicpal_key_realize(DeviceState *dev, Error **errp) -{ - musicpal_key_state *s =3D MUSICPAL_KEY(dev); - - s->hs =3D qemu_input_handler_register(dev, &musicpal_key_handler); -} - -static void musicpal_key_unrealize(DeviceState *dev) -{ - musicpal_key_state *s =3D MUSICPAL_KEY(dev); - - g_clear_pointer(&s->hs, qemu_input_handler_unregister); -} - -static const VMStateDescription musicpal_key_vmsd =3D { - .name =3D "musicpal_key", - .version_id =3D 2, - .minimum_version_id =3D 2, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(pressed_keys, musicpal_key_state), - VMSTATE_END_OF_LIST() - } -}; - -static void musicpal_key_class_init(ObjectClass *klass, const void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->vmsd =3D &musicpal_key_vmsd; - dc->realize =3D musicpal_key_realize; - dc->unrealize =3D musicpal_key_unrealize; -} - -static const TypeInfo musicpal_key_info =3D { - .name =3D TYPE_MUSICPAL_KEY, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(musicpal_key_state), - .instance_init =3D musicpal_key_init, - .class_init =3D musicpal_key_class_init, -}; - -#define FLASH_SECTOR_SIZE (64 * KiB) - -#define TYPE_MUSICPAL_MACHINE MACHINE_TYPE_NAME("musicpal") -OBJECT_DECLARE_SIMPLE_TYPE(MusicPalMachineState, MUSICPAL_MACHINE) - -struct MusicPalMachineState { - MachineState parent; - - struct arm_boot_info bootinfo; -}; - -static void musicpal_init(MachineState *machine) -{ - MusicPalMachineState *mpms =3D MUSICPAL_MACHINE(machine); - ARMCPU *cpu; - DeviceState *dev; - DeviceState *pic; - DeviceState *uart_orgate; - DeviceState *i2c_dev; - DeviceState *lcd_dev; - DeviceState *key_dev; - I2CSlave *wm8750_dev; - SysBusDevice *s; - I2CBus *i2c; - int i; - unsigned long flash_size; - DriveInfo *dinfo; - MachineClass *mc =3D MACHINE_GET_CLASS(machine); - MemoryRegion *address_space_mem =3D get_system_memory(); - MemoryRegion *sram =3D g_new(MemoryRegion, 1); - - /* For now we use a fixed - the original - RAM size */ - if (machine->ram_size !=3D mc->default_ram_size) { - char *sz =3D size_to_str(mc->default_ram_size); - error_report("Invalid RAM size, should be %s", sz); - g_free(sz); - exit(EXIT_FAILURE); - } - - cpu =3D ARM_CPU(cpu_create(machine->cpu_type)); - - memory_region_add_subregion(address_space_mem, 0, machine->ram); - - memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE, - &error_fatal); - memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); - - pic =3D sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, - qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); - sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, - qdev_get_gpio_in(pic, MP_TIMER1_IRQ), - qdev_get_gpio_in(pic, MP_TIMER2_IRQ), - qdev_get_gpio_in(pic, MP_TIMER3_IRQ), - qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL); - - /* Logically OR both UART IRQs together */ - uart_orgate =3D qdev_new(TYPE_OR_IRQ); - object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fa= tal); - qdev_realize_and_unref(uart_orgate, NULL, &error_fatal); - qdev_connect_gpio_out(uart_orgate, 0, - qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ)); - - serial_mm_init(address_space_mem, MP_UART1_BASE, 2, - qdev_get_gpio_in(uart_orgate, 0), - 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN); - serial_mm_init(address_space_mem, MP_UART2_BASE, 2, - qdev_get_gpio_in(uart_orgate, 1), - 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN); - - /* Register flash */ - dinfo =3D drive_get(IF_PFLASH, 0, 0); - if (dinfo) { - BlockBackend *blk =3D blk_by_legacy_dinfo(dinfo); - - flash_size =3D blk_getlength(blk); - if (flash_size !=3D 8 * MiB && flash_size !=3D 16 * MiB && - flash_size !=3D 32 * MiB) { - error_report("Invalid flash image size"); - exit(1); - } - - /* - * The original U-Boot accesses the flash at 0xFE000000 instead of - * 0xFF800000 (if there is 8 MB flash). So remap flash access if t= he - * image is smaller than 32 MB. - */ - pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, - "musicpal.flash", flash_size, - blk, FLASH_SECTOR_SIZE, - MP_FLASH_SIZE_MAX / flash_size, - 2, 0x00BF, 0x236D, 0x0000, 0x0000, - 0x5555, 0x2AAA, 0); - } - sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL); - - dev =3D qdev_new(TYPE_MV88W8618_ETH); - qemu_configure_nic_device(dev, true, "mv88w8618"); - object_property_set_link(OBJECT(dev), "dma-memory", - OBJECT(get_system_memory()), &error_fatal); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, - qdev_get_gpio_in(pic, MP_ETH_IRQ)); - - sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); - - sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); - - dev =3D sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, - qdev_get_gpio_in(pic, MP_GPIO_IRQ)); - i2c_dev =3D sysbus_create_simple(TYPE_GPIO_I2C, -1, NULL); - i2c =3D (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); - - lcd_dev =3D sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL); - key_dev =3D sysbus_create_simple(TYPE_MUSICPAL_KEY, -1, NULL); - - /* I2C read data */ - qdev_connect_gpio_out(i2c_dev, 0, - qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); - /* I2C data */ - qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); - /* I2C clock */ - qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); - - for (i =3D 0; i < 3; i++) { - qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); - } - for (i =3D 0; i < 4; i++) { - qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8)); - } - for (i =3D 4; i < 8; i++) { - qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15)); - } - - wm8750_dev =3D i2c_slave_new(TYPE_WM8750, MP_WM_ADDR); - if (machine->audiodev) { - qdev_prop_set_string(DEVICE(wm8750_dev), "audiodev", machine->audi= odev); - } - i2c_slave_realize_and_unref(wm8750_dev, i2c, &error_abort); - - dev =3D qdev_new(TYPE_MV88W8618_AUDIO); - s =3D SYS_BUS_DEVICE(dev); - object_property_set_link(OBJECT(dev), "wm8750", OBJECT(wm8750_dev), - NULL); - sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, MP_AUDIO_BASE); - sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ)); - - mpms->bootinfo.loader_start =3D 0x0; - mpms->bootinfo.board_id =3D 0x20e; - mpms->bootinfo.ram_size =3D MP_RAM_DEFAULT_SIZE; - arm_load_kernel(cpu, machine, &mpms->bootinfo); -} - -static void musicpal_machine_init(MachineClass *mc) -{ - mc->desc =3D "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; - mc->init =3D musicpal_init; - mc->ignore_memory_transaction_failures =3D true; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("arm926"); - mc->default_ram_size =3D MP_RAM_DEFAULT_SIZE; - mc->default_ram_id =3D "musicpal.ram"; - - machine_add_audiodev_property(mc); -} - -DEFINE_MACHINE_EXTENDED("musicpal", MACHINE, MusicPalMachineState, - musicpal_machine_init, false, - arm_machine_interfaces) - -static void mv88w8618_wlan_class_init(ObjectClass *klass, const void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->realize =3D mv88w8618_wlan_realize; -} - -static const TypeInfo mv88w8618_wlan_info =3D { - .name =3D "mv88w8618_wlan", - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SysBusDevice), - .class_init =3D mv88w8618_wlan_class_init, -}; - -static void musicpal_register_types(void) -{ - type_register_static(&mv88w8618_pic_info); - type_register_static(&mv88w8618_pit_info); - type_register_static(&mv88w8618_flashcfg_info); - type_register_static(&mv88w8618_wlan_info); - type_register_static(&musicpal_lcd_info); - type_register_static(&musicpal_gpio_info); - type_register_static(&musicpal_key_info); - type_register_static(&musicpal_misc_info); -} - -type_init(musicpal_register_types) --=20 2.43.0 From nobody Sat Sep 26 20:51:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268663; x=1788873463; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=HhC5z+Rc0v8EepQ+8i0JjAyQTcJlTKlWPfhzeE2BgnA=; b=r4wwfNli2PDvZG7VffQGfu5XCHKRxLAan9g0HOchjnvzVwmtzBXo3kX1QVp2hq27UF a53RrJw0u10UrfIBA7KE1kIImeWnIoMZa/0Ur+nYEDpo4eKo4SeJp7fGnI1TJhA7QGYR ZDlGkZ+p7vlknryxh4uQh4kwu4LmghjJCrQYgwyyZVVempLLwFmKiKNEtl05qALlqlff u7GcisqpCn9TjXLx0Eb3jST/xScjkYo9SrKWCPetK98K9cu6zk+h8L2SmKs8RmuK5NAs PH4Ej0BCMOGuDM9mjV1zz6CdllyvRA0worV9S0K19zn7zSMA1al9MFAm7otnBSydSpd+ jbsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268663; x=1788873463; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=HhC5z+Rc0v8EepQ+8i0JjAyQTcJlTKlWPfhzeE2BgnA=; b=SmbB+7ihfmKq7xIfFwpLnYLZOB5QqNV6CLGzYC9nVfOHazRkrF2pXYU4Xqfb0nPHcx xK/GkZFPZbZKW2K1MVQ5tiE4jSVycXCVweskrMNQfaFpjdkfoTSnuHOD4d2nVitrDAA1 HaBojdAGiTVv3Dl9vLACU2eVbxFy/ObDBGz2TO31ppqvvIx6L49L3xeYtFeZPD9tkN9q ME1+Wx3F9UmabUl9HxMGRXqJAy+Vq+jBmLjL4mZVmrP8v/VNthbLQzWTyAw5HqC/l+ab yl1tYZ2B84CQt3vDkf08eLEOXVFV6m644ZMK0N/hHfHkH+xUP7o53xMtghC60wIGS23i UvMw== X-Gm-Message-State: AFuF++nGKK1IAfRp2x3u6PNq6eJ4DJmB7pWgRLr3k3k+e8ZZDx0+zlrq OseZtbwq0JxmwkL3k/7nEwA5EZR2izoZuskFN1WgxTg1AQRADUyBiweIg2g2E/sLGkGJ3A6nDol rx2ylaEM= X-Gm-Gg: AR+sD10H+sb1RBlEz0qRysuknW1P0Is5BYHVEDr9wcIJ7FcYNIgfxyWd8hpUwE6RICb aLdjLEpN7XRYcma4EromLNJzLqIx7WpPQdEZEMLQbQBu3ygs/P/I7hsMkmCfiDlsLKiY9wrD0zT Sqb+FcyTrCJHtIEzH2qLwqI4kBrQwl9WAND9rIIP0vydiV/eHFnOWazPUJ+iN5OulKs3WQ3e7X3 ccoMM6ZRD+6zHGs4uDdeyZG9qvtqVX3d1mvdbzTDrEzhgwCNtH7Jwd8lTE/niO/jg9YIShdqPvh 2IrQpoTH3Ao4cNu/q8BGGan3V6mACnaLMol59U28ykTN8wJmqkiXLUsttKvpo+kjfmwrEc4ioo6 CT/PKHHKGer+ZypvyIxcQRqkZ6/64mKpK8Xee80mkiybSx83ppyyVun6d1/Sjd1ZPtdbpnidH0f WchS6NmrX+WSBe89R0ZTaDzmsJYy7+tqUaXR5fZZYkFoE0mC9hHWH3bkqMH1rhtBgoSZdwSvtWk ICTZlvQQFMVL6zo1i5EgsehxjUJLyrz+WBorp1fKlAJjH0RH6rBUie793Ko52VwDzh0Ag== X-Received: by 2002:a17:906:ee82:b0:c25:5114:c832 with SMTP id a640c23a62f3a-c25b3b804b3mr551915666b.3.1788268662834; Tue, 01 Sep 2026 06:17:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/58] hw: Remove Marvell 88W8618 devices Date: Tue, 1 Sep 2026 14:16:42 +0100 Message-ID: <20260901131732.2263947-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269027323158500 The mv88w8618 ethernet and audio devices were used only by the now-removed musicpal machine, so can also be deleted. Signed-off-by: Peter Maydell Acked-by: Jan Kiszka Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260819185430.3467629-5-peter.maydell@linaro.org --- hw/arm/Kconfig | 3 - hw/audio/marvell_88w8618.c | 315 -------------------------- hw/audio/meson.build | 1 - hw/net/meson.build | 1 - hw/net/mv88w8618_eth.c | 403 --------------------------------- include/hw/net/mv88w8618_eth.h | 13 -- 6 files changed, 736 deletions(-) delete mode 100644 hw/audio/marvell_88w8618.c delete mode 100644 hw/net/mv88w8618_eth.c delete mode 100644 include/hw/net/mv88w8618_eth.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 57db2a2fdf8..5db7ce057f4 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -100,9 +100,6 @@ config MUSCA select SPLIT_IRQ select UNIMP =20 -config MARVELL_88W8618 - bool - config NETDUINO2 bool default y diff --git a/hw/audio/marvell_88w8618.c b/hw/audio/marvell_88w8618.c deleted file mode 100644 index 061d076dade..00000000000 --- a/hw/audio/marvell_88w8618.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Marvell 88w8618 audio emulation extracted from - * Marvell MV88w8618 / Freecom MusicPal emulation. - * - * Copyright (c) 2008 Jan Kiszka - * - * This code is licensed under the GNU GPL v2. - * - * Contributions after 2012-01-13 are licensed under the terms of the - * GNU GPL, version 2 or (at your option) any later version. - */ - -#include "qemu/osdep.h" -#include "hw/core/sysbus.h" -#include "exec/cpu-common.h" -#include "migration/vmstate.h" -#include "hw/core/irq.h" -#include "hw/core/qdev-properties.h" -#include "hw/audio/wm8750.h" -#include "qemu/audio.h" -#include "qapi/error.h" -#include "qemu/module.h" -#include "qom/object.h" -#include "system/physmem.h" - -#define MP_AUDIO_SIZE 0x00001000 - -/* Audio register offsets */ -#define MP_AUDIO_PLAYBACK_MODE 0x00 -#define MP_AUDIO_CLOCK_DIV 0x18 -#define MP_AUDIO_IRQ_STATUS 0x20 -#define MP_AUDIO_IRQ_ENABLE 0x24 -#define MP_AUDIO_TX_START_LO 0x28 -#define MP_AUDIO_TX_THRESHOLD 0x2C -#define MP_AUDIO_TX_STATUS 0x38 -#define MP_AUDIO_TX_START_HI 0x40 - -/* Status register and IRQ enable bits */ -#define MP_AUDIO_TX_HALF (1 << 6) -#define MP_AUDIO_TX_FULL (1 << 7) - -/* Playback mode bits */ -#define MP_AUDIO_16BIT_SAMPLE (1 << 0) -#define MP_AUDIO_PLAYBACK_EN (1 << 7) -#define MP_AUDIO_CLOCK_24MHZ (1 << 9) -#define MP_AUDIO_MONO (1 << 14) - -OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_audio_state, MV88W8618_AUDIO) - -struct mv88w8618_audio_state { - SysBusDevice parent_obj; - - MemoryRegion iomem; - qemu_irq irq; - uint32_t playback_mode; - uint32_t status; - uint32_t irq_enable; - uint32_t phys_buf; - uint32_t target_buffer; - uint32_t threshold; - uint32_t play_pos; - uint32_t last_free; - uint32_t clock_div; - void *wm; -}; - -static void mv88w8618_audio_callback(void *opaque, int free_out, int free_= in) -{ - mv88w8618_audio_state *s =3D opaque; - int16_t *codec_buffer; - QEMU_UNINITIALIZED int8_t buf[4096]; - int8_t *mem_buffer; - int pos, block_size; - - if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) { - return; - } - if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) { - free_out <<=3D 1; - } - if (!(s->playback_mode & MP_AUDIO_MONO)) { - free_out <<=3D 1; - } - block_size =3D s->threshold / 2; - if (free_out - s->last_free < block_size) { - return; - } - if (block_size > 4096) { - return; - } - physical_memory_read(s->target_buffer + s->play_pos, buf, block_size); - mem_buffer =3D buf; - if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) { - if (s->playback_mode & MP_AUDIO_MONO) { - codec_buffer =3D wm8750_dac_buffer(s->wm, block_size >> 1); - for (pos =3D 0; pos < block_size; pos +=3D 2) { - *codec_buffer++ =3D *(int16_t *)mem_buffer; - *codec_buffer++ =3D *(int16_t *)mem_buffer; - mem_buffer +=3D 2; - } - } else { - memcpy(wm8750_dac_buffer(s->wm, block_size >> 2), - (uint32_t *)mem_buffer, block_size); - } - } else { - if (s->playback_mode & MP_AUDIO_MONO) { - codec_buffer =3D wm8750_dac_buffer(s->wm, block_size); - for (pos =3D 0; pos < block_size; pos++) { - *codec_buffer++ =3D cpu_to_le16(256 * *mem_buffer); - *codec_buffer++ =3D cpu_to_le16(256 * *mem_buffer++); - } - } else { - codec_buffer =3D wm8750_dac_buffer(s->wm, block_size >> 1); - for (pos =3D 0; pos < block_size; pos +=3D 2) { - *codec_buffer++ =3D cpu_to_le16(256 * *mem_buffer++); - *codec_buffer++ =3D cpu_to_le16(256 * *mem_buffer++); - } - } - } - wm8750_dac_commit(s->wm); - - s->last_free =3D free_out - block_size; - - if (s->play_pos =3D=3D 0) { - s->status |=3D MP_AUDIO_TX_HALF; - s->play_pos =3D block_size; - } else { - s->status |=3D MP_AUDIO_TX_FULL; - s->play_pos =3D 0; - } - - if (s->status & s->irq_enable) { - qemu_irq_raise(s->irq); - } -} - -static void mv88w8618_audio_clock_update(mv88w8618_audio_state *s) -{ - int rate; - - if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ) { - rate =3D 24576000 / 64; /* 24.576MHz */ - } else { - rate =3D 11289600 / 64; /* 11.2896MHz */ - } - rate /=3D ((s->clock_div >> 8) & 0xff) + 1; - - wm8750_set_bclk_in(s->wm, rate); -} - -static uint64_t mv88w8618_audio_read(void *opaque, hwaddr offset, - unsigned size) -{ - mv88w8618_audio_state *s =3D opaque; - - switch (offset) { - case MP_AUDIO_PLAYBACK_MODE: - return s->playback_mode; - - case MP_AUDIO_CLOCK_DIV: - return s->clock_div; - - case MP_AUDIO_IRQ_STATUS: - return s->status; - - case MP_AUDIO_IRQ_ENABLE: - return s->irq_enable; - - case MP_AUDIO_TX_STATUS: - return s->play_pos >> 2; - - default: - return 0; - } -} - -static void mv88w8618_audio_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - mv88w8618_audio_state *s =3D opaque; - - switch (offset) { - case MP_AUDIO_PLAYBACK_MODE: - if (value & MP_AUDIO_PLAYBACK_EN && - !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) { - s->status =3D 0; - s->last_free =3D 0; - s->play_pos =3D 0; - } - s->playback_mode =3D value; - mv88w8618_audio_clock_update(s); - break; - - case MP_AUDIO_CLOCK_DIV: - s->clock_div =3D value; - s->last_free =3D 0; - s->play_pos =3D 0; - mv88w8618_audio_clock_update(s); - break; - - case MP_AUDIO_IRQ_STATUS: - s->status &=3D ~value; - break; - - case MP_AUDIO_IRQ_ENABLE: - s->irq_enable =3D value; - if (s->status & s->irq_enable) { - qemu_irq_raise(s->irq); - } - break; - - case MP_AUDIO_TX_START_LO: - s->phys_buf =3D (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF); - s->target_buffer =3D s->phys_buf; - s->play_pos =3D 0; - s->last_free =3D 0; - break; - - case MP_AUDIO_TX_THRESHOLD: - s->threshold =3D (value + 1) * 4; - break; - - case MP_AUDIO_TX_START_HI: - s->phys_buf =3D (s->phys_buf & 0xFFFF) | (value << 16); - s->target_buffer =3D s->phys_buf; - s->play_pos =3D 0; - s->last_free =3D 0; - break; - } -} - -static void mv88w8618_audio_reset(DeviceState *d) -{ - mv88w8618_audio_state *s =3D MV88W8618_AUDIO(d); - - s->playback_mode =3D 0; - s->status =3D 0; - s->irq_enable =3D 0; - s->clock_div =3D 0; - s->threshold =3D 0; - s->phys_buf =3D 0; -} - -static const MemoryRegionOps mv88w8618_audio_ops =3D { - .read =3D mv88w8618_audio_read, - .write =3D mv88w8618_audio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -static void mv88w8618_audio_init(Object *obj) -{ - SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); - mv88w8618_audio_state *s =3D MV88W8618_AUDIO(dev); - - sysbus_init_irq(dev, &s->irq); - - memory_region_init_io(&s->iomem, obj, &mv88w8618_audio_ops, s, - "audio", MP_AUDIO_SIZE); - sysbus_init_mmio(dev, &s->iomem); - - object_property_add_link(OBJECT(dev), "wm8750", TYPE_WM8750, - (Object **) &s->wm, - qdev_prop_allow_set_link_before_realize, - 0); -} - -static void mv88w8618_audio_realize(DeviceState *dev, Error **errp) -{ - mv88w8618_audio_state *s =3D MV88W8618_AUDIO(dev); - - wm8750_data_req_set(s->wm, mv88w8618_audio_callback, s); -} - -static const VMStateDescription mv88w8618_audio_vmsd =3D { - .name =3D "mv88w8618_audio", - .version_id =3D 1, - .minimum_version_id =3D 1, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(playback_mode, mv88w8618_audio_state), - VMSTATE_UINT32(status, mv88w8618_audio_state), - VMSTATE_UINT32(irq_enable, mv88w8618_audio_state), - VMSTATE_UINT32(phys_buf, mv88w8618_audio_state), - VMSTATE_UINT32(target_buffer, mv88w8618_audio_state), - VMSTATE_UINT32(threshold, mv88w8618_audio_state), - VMSTATE_UINT32(play_pos, mv88w8618_audio_state), - VMSTATE_UINT32(last_free, mv88w8618_audio_state), - VMSTATE_UINT32(clock_div, mv88w8618_audio_state), - VMSTATE_END_OF_LIST() - } -}; - -static void mv88w8618_audio_class_init(ObjectClass *klass, const void *dat= a) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->realize =3D mv88w8618_audio_realize; - device_class_set_legacy_reset(dc, mv88w8618_audio_reset); - dc->vmsd =3D &mv88w8618_audio_vmsd; - dc->user_creatable =3D false; -} - -static const TypeInfo mv88w8618_audio_info =3D { - .name =3D TYPE_MV88W8618_AUDIO, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(mv88w8618_audio_state), - .instance_init =3D mv88w8618_audio_init, - .class_init =3D mv88w8618_audio_class_init, -}; - -static void mv88w8618_register_types(void) -{ - type_register_static(&mv88w8618_audio_info); -} - -type_init(mv88w8618_register_types) diff --git a/hw/audio/meson.build b/hw/audio/meson.build index 2154cbdb57a..c977679e23a 100644 --- a/hw/audio/meson.build +++ b/hw/audio/meson.build @@ -7,7 +7,6 @@ system_ss.add(when: 'CONFIG_CS4231A', if_true: files('cs423= 1a.c')) system_ss.add(when: 'CONFIG_ES1370', if_true: files('es1370.c')) system_ss.add(when: 'CONFIG_GUS', if_true: files('gus.c', 'gusemu_hal.c', = 'gusemu_mixer.c')) system_ss.add(when: 'CONFIG_HDA', if_true: files('intel-hda.c', 'hda-codec= .c')) -system_ss.add(when: 'CONFIG_MARVELL_88W8618', if_true: files('marvell_88w8= 618.c')) system_ss.add(when: 'CONFIG_PCSPK', if_true: files('pcspk.c')) system_ss.add(when: 'CONFIG_PL041', if_true: files('pl041.c', 'lm4549.c')) system_ss.add(when: 'CONFIG_SB16', if_true: files('sb16.c')) diff --git a/hw/net/meson.build b/hw/net/meson.build index 84f142df222..b4c95b58faf 100644 --- a/hw/net/meson.build +++ b/hw/net/meson.build @@ -27,7 +27,6 @@ system_ss.add(when: 'CONFIG_ALLWINNER_EMAC', if_true: fil= es('allwinner_emac.c')) system_ss.add(when: 'CONFIG_ALLWINNER_SUN8I_EMAC', if_true: files('allwinn= er-sun8i-emac.c')) system_ss.add(when: 'CONFIG_IMX_FEC', if_true: files('imx_fec.c')) system_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-emac.c')) -system_ss.add(when: 'CONFIG_MARVELL_88W8618', if_true: files('mv88w8618_et= h.c')) =20 system_ss.add(when: 'CONFIG_CADENCE', if_true: files('cadence_gem.c')) system_ss.add(when: 'CONFIG_STELLARIS_ENET', if_true: files('stellaris_ene= t.c')) diff --git a/hw/net/mv88w8618_eth.c b/hw/net/mv88w8618_eth.c deleted file mode 100644 index 1fcfbe912ee..00000000000 --- a/hw/net/mv88w8618_eth.c +++ /dev/null @@ -1,403 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Marvell MV88W8618 / Freecom MusicPal emulation. - * - * Copyright (c) 2008 Jan Kiszka - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "hw/core/qdev-properties.h" -#include "hw/core/sysbus.h" -#include "hw/core/irq.h" -#include "hw/net/mv88w8618_eth.h" -#include "migration/vmstate.h" -#include "system/dma.h" -#include "net/net.h" - -#define MP_ETH_SIZE 0x00001000 - -/* Ethernet register offsets */ -#define MP_ETH_SMIR 0x010 -#define MP_ETH_PCXR 0x408 -#define MP_ETH_SDCMR 0x448 -#define MP_ETH_ICR 0x450 -#define MP_ETH_IMR 0x458 -#define MP_ETH_FRDP0 0x480 -#define MP_ETH_FRDP1 0x484 -#define MP_ETH_FRDP2 0x488 -#define MP_ETH_FRDP3 0x48C -#define MP_ETH_CRDP0 0x4A0 -#define MP_ETH_CRDP1 0x4A4 -#define MP_ETH_CRDP2 0x4A8 -#define MP_ETH_CRDP3 0x4AC -#define MP_ETH_CTDP0 0x4E0 -#define MP_ETH_CTDP1 0x4E4 - -/* MII PHY access */ -#define MP_ETH_SMIR_DATA 0x0000FFFF -#define MP_ETH_SMIR_ADDR 0x03FF0000 -#define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ -#define MP_ETH_SMIR_RDVALID (1 << 27) - -/* PHY registers */ -#define MP_ETH_PHY1_BMSR 0x00210000 -#define MP_ETH_PHY1_PHYSID1 0x00410000 -#define MP_ETH_PHY1_PHYSID2 0x00610000 - -#define MP_PHY_BMSR_LINK 0x0004 -#define MP_PHY_BMSR_AUTONEG 0x0008 - -#define MP_PHY_88E3015 0x01410E20 - -/* TX descriptor status */ -#define MP_ETH_TX_OWN (1U << 31) - -/* RX descriptor status */ -#define MP_ETH_RX_OWN (1U << 31) - -/* Interrupt cause/mask bits */ -#define MP_ETH_IRQ_RX_BIT 0 -#define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) -#define MP_ETH_IRQ_TXHI_BIT 2 -#define MP_ETH_IRQ_TXLO_BIT 3 - -/* Port config bits */ -#define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ - -/* SDMA command bits */ -#define MP_ETH_CMD_TXHI (1 << 23) -#define MP_ETH_CMD_TXLO (1 << 22) - -typedef struct mv88w8618_tx_desc { - uint32_t cmdstat; - uint16_t res; - uint16_t bytes; - uint32_t buffer; - uint32_t next; -} mv88w8618_tx_desc; - -typedef struct mv88w8618_rx_desc { - uint32_t cmdstat; - uint16_t bytes; - uint16_t buffer_size; - uint32_t buffer; - uint32_t next; -} mv88w8618_rx_desc; - -OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_eth_state, MV88W8618_ETH) - -struct mv88w8618_eth_state { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - MemoryRegion iomem; - qemu_irq irq; - MemoryRegion *dma_mr; - AddressSpace dma_as; - uint32_t smir; - uint32_t icr; - uint32_t imr; - int mmio_index; - uint32_t vlan_header; - uint32_t tx_queue[2]; - uint32_t rx_queue[4]; - uint32_t frx_queue[4]; - uint32_t cur_rx[4]; - NICState *nic; - NICConf conf; -}; - -static void eth_rx_desc_put(AddressSpace *dma_as, uint32_t addr, - mv88w8618_rx_desc *desc) -{ - cpu_to_le32s(&desc->cmdstat); - cpu_to_le16s(&desc->bytes); - cpu_to_le16s(&desc->buffer_size); - cpu_to_le32s(&desc->buffer); - cpu_to_le32s(&desc->next); - dma_memory_write(dma_as, addr, desc, sizeof(*desc), MEMTXATTRS_UNSPECI= FIED); -} - -static void eth_rx_desc_get(AddressSpace *dma_as, uint32_t addr, - mv88w8618_rx_desc *desc) -{ - dma_memory_read(dma_as, addr, desc, sizeof(*desc), MEMTXATTRS_UNSPECIF= IED); - le32_to_cpus(&desc->cmdstat); - le16_to_cpus(&desc->bytes); - le16_to_cpus(&desc->buffer_size); - le32_to_cpus(&desc->buffer); - le32_to_cpus(&desc->next); -} - -static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t = size) -{ - mv88w8618_eth_state *s =3D qemu_get_nic_opaque(nc); - uint32_t desc_addr; - mv88w8618_rx_desc desc; - int i; - - for (i =3D 0; i < 4; i++) { - desc_addr =3D s->cur_rx[i]; - if (!desc_addr) { - continue; - } - do { - eth_rx_desc_get(&s->dma_as, desc_addr, &desc); - if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >=3D si= ze) { - dma_memory_write(&s->dma_as, desc.buffer + s->vlan_header, - buf, size, MEMTXATTRS_UNSPECIFIED); - desc.bytes =3D size + s->vlan_header; - desc.cmdstat &=3D ~MP_ETH_RX_OWN; - s->cur_rx[i] =3D desc.next; - - s->icr |=3D MP_ETH_IRQ_RX; - if (s->icr & s->imr) { - qemu_irq_raise(s->irq); - } - eth_rx_desc_put(&s->dma_as, desc_addr, &desc); - return size; - } - desc_addr =3D desc.next; - } while (desc_addr !=3D s->rx_queue[i]); - } - return size; -} - -static void eth_tx_desc_put(AddressSpace *dma_as, uint32_t addr, - mv88w8618_tx_desc *desc) -{ - cpu_to_le32s(&desc->cmdstat); - cpu_to_le16s(&desc->res); - cpu_to_le16s(&desc->bytes); - cpu_to_le32s(&desc->buffer); - cpu_to_le32s(&desc->next); - dma_memory_write(dma_as, addr, desc, sizeof(*desc), MEMTXATTRS_UNSPECI= FIED); -} - -static void eth_tx_desc_get(AddressSpace *dma_as, uint32_t addr, - mv88w8618_tx_desc *desc) -{ - dma_memory_read(dma_as, addr, desc, sizeof(*desc), MEMTXATTRS_UNSPECIF= IED); - le32_to_cpus(&desc->cmdstat); - le16_to_cpus(&desc->res); - le16_to_cpus(&desc->bytes); - le32_to_cpus(&desc->buffer); - le32_to_cpus(&desc->next); -} - -static void eth_send(mv88w8618_eth_state *s, int queue_index) -{ - uint32_t desc_addr =3D s->tx_queue[queue_index]; - mv88w8618_tx_desc desc; - uint32_t next_desc; - uint8_t buf[2048]; - int len; - - do { - eth_tx_desc_get(&s->dma_as, desc_addr, &desc); - next_desc =3D desc.next; - if (desc.cmdstat & MP_ETH_TX_OWN) { - len =3D desc.bytes; - if (len < 2048) { - dma_memory_read(&s->dma_as, desc.buffer, buf, len, - MEMTXATTRS_UNSPECIFIED); - qemu_send_packet(qemu_get_queue(s->nic), buf, len); - } - desc.cmdstat &=3D ~MP_ETH_TX_OWN; - s->icr |=3D 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index); - eth_tx_desc_put(&s->dma_as, desc_addr, &desc); - } - desc_addr =3D next_desc; - } while (desc_addr !=3D s->tx_queue[queue_index]); -} - -static uint64_t mv88w8618_eth_read(void *opaque, hwaddr offset, - unsigned size) -{ - mv88w8618_eth_state *s =3D opaque; - - switch (offset) { - case MP_ETH_SMIR: - if (s->smir & MP_ETH_SMIR_OPCODE) { - switch (s->smir & MP_ETH_SMIR_ADDR) { - case MP_ETH_PHY1_BMSR: - return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG | - MP_ETH_SMIR_RDVALID; - case MP_ETH_PHY1_PHYSID1: - return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; - case MP_ETH_PHY1_PHYSID2: - return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; - default: - return MP_ETH_SMIR_RDVALID; - } - } - return 0; - - case MP_ETH_ICR: - return s->icr; - - case MP_ETH_IMR: - return s->imr; - - case MP_ETH_FRDP0 ... MP_ETH_FRDP3: - return s->frx_queue[(offset - MP_ETH_FRDP0) / 4]; - - case MP_ETH_CRDP0 ... MP_ETH_CRDP3: - return s->rx_queue[(offset - MP_ETH_CRDP0) / 4]; - - case MP_ETH_CTDP0 ... MP_ETH_CTDP1: - return s->tx_queue[(offset - MP_ETH_CTDP0) / 4]; - - default: - return 0; - } -} - -static void mv88w8618_eth_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - mv88w8618_eth_state *s =3D opaque; - - switch (offset) { - case MP_ETH_SMIR: - s->smir =3D value; - break; - - case MP_ETH_PCXR: - s->vlan_header =3D ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; - break; - - case MP_ETH_SDCMR: - if (value & MP_ETH_CMD_TXHI) { - eth_send(s, 1); - } - if (value & MP_ETH_CMD_TXLO) { - eth_send(s, 0); - } - if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr= ) { - qemu_irq_raise(s->irq); - } - break; - - case MP_ETH_ICR: - s->icr &=3D value; - break; - - case MP_ETH_IMR: - s->imr =3D value; - if (s->icr & s->imr) { - qemu_irq_raise(s->irq); - } - break; - - case MP_ETH_FRDP0 ... MP_ETH_FRDP3: - s->frx_queue[(offset - MP_ETH_FRDP0) / 4] =3D value; - break; - - case MP_ETH_CRDP0 ... MP_ETH_CRDP3: - s->rx_queue[(offset - MP_ETH_CRDP0) / 4] =3D - s->cur_rx[(offset - MP_ETH_CRDP0) / 4] =3D value; - break; - - case MP_ETH_CTDP0 ... MP_ETH_CTDP1: - s->tx_queue[(offset - MP_ETH_CTDP0) / 4] =3D value; - break; - } -} - -static const MemoryRegionOps mv88w8618_eth_ops =3D { - .read =3D mv88w8618_eth_read, - .write =3D mv88w8618_eth_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -static void eth_cleanup(NetClientState *nc) -{ - mv88w8618_eth_state *s =3D qemu_get_nic_opaque(nc); - - s->nic =3D NULL; -} - -static NetClientInfo net_mv88w8618_info =3D { - .type =3D NET_CLIENT_DRIVER_NIC, - .size =3D sizeof(NICState), - .receive =3D eth_receive, - .cleanup =3D eth_cleanup, -}; - -static void mv88w8618_eth_init(Object *obj) -{ - SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); - DeviceState *dev =3D DEVICE(sbd); - mv88w8618_eth_state *s =3D MV88W8618_ETH(dev); - - sysbus_init_irq(sbd, &s->irq); - memory_region_init_io(&s->iomem, obj, &mv88w8618_eth_ops, s, - "mv88w8618-eth", MP_ETH_SIZE); - sysbus_init_mmio(sbd, &s->iomem); -} - -static void mv88w8618_eth_realize(DeviceState *dev, Error **errp) -{ - mv88w8618_eth_state *s =3D MV88W8618_ETH(dev); - - if (!s->dma_mr) { - error_setg(errp, TYPE_MV88W8618_ETH " 'dma-memory' link not set"); - return; - } - - address_space_init(&s->dma_as, s->dma_mr, "emac-dma"); - s->nic =3D qemu_new_nic(&net_mv88w8618_info, &s->conf, - object_get_typename(OBJECT(dev)), dev->id, - &dev->mem_reentrancy_guard, s); -} - -static const VMStateDescription mv88w8618_eth_vmsd =3D { - .name =3D "mv88w8618_eth", - .version_id =3D 1, - .minimum_version_id =3D 1, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(smir, mv88w8618_eth_state), - VMSTATE_UINT32(icr, mv88w8618_eth_state), - VMSTATE_UINT32(imr, mv88w8618_eth_state), - VMSTATE_UINT32(vlan_header, mv88w8618_eth_state), - VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2), - VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4), - VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4), - VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4), - VMSTATE_END_OF_LIST() - } -}; - -static const Property mv88w8618_eth_properties[] =3D { - DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf), - DEFINE_PROP_LINK("dma-memory", mv88w8618_eth_state, dma_mr, - TYPE_MEMORY_REGION, MemoryRegion *), -}; - -static void mv88w8618_eth_class_init(ObjectClass *klass, const void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->vmsd =3D &mv88w8618_eth_vmsd; - device_class_set_props(dc, mv88w8618_eth_properties); - dc->realize =3D mv88w8618_eth_realize; -} - -static const TypeInfo mv88w8618_eth_info =3D { - .name =3D TYPE_MV88W8618_ETH, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(mv88w8618_eth_state), - .instance_init =3D mv88w8618_eth_init, - .class_init =3D mv88w8618_eth_class_init, -}; - -static void musicpal_register_types(void) -{ - type_register_static(&mv88w8618_eth_info); -} - -type_init(musicpal_register_types) - diff --git a/include/hw/net/mv88w8618_eth.h b/include/hw/net/mv88w8618_eth.h deleted file mode 100644 index 41074940ec0..00000000000 --- a/include/hw/net/mv88w8618_eth.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Marvell MV88W8618 / Freecom MusicPal emulation. - * - * Copyright (c) 2008-2021 QEMU contributors - */ - -#ifndef HW_NET_MV88W8618_ETH_H -#define HW_NET_MV88W8618_ETH_H - -#define TYPE_MV88W8618_ETH "mv88w8618_eth" - -#endif --=20 2.43.0 From nobody Sat Sep 26 20:51:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268664; x=1788873464; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=P2MBWA2TMfgwFY+UVp3Avh31Z1wHTxd78goSFCjmXBc=; b=V1Hcj0PCyBJ8sp2MKTbqpfd+hjR/y4pvyHF5EseFA7z5ffp5nb2d6bKMHHIqhqNxIK iJuhDZ2pVrCXho4d6aUVFiotyCWAgaxtMHrZmp3lvttsF8Sk0IjSA/b9JfWtXOSi0xLp RPuEGx7NDEMJQNfqG3i/GPEsrbySEVIZPEHEr9K1AfMO/JUD2GOl3FTujpFWuikG4/A/ jSekaCHcLxhBf2S6cokFkkEa5jF9xv7p0IXLH1ZWiNrz+yKXVl18DE6BO7enCTGhlJCN +UpCchEsGMxP+B2wNzgKBPESPHxiqe72cYfvBhDrV+AOUlGryHrzAHzoUU3sPuTbSbc6 U/EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268664; x=1788873464; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=P2MBWA2TMfgwFY+UVp3Avh31Z1wHTxd78goSFCjmXBc=; b=ne0UM/RF6c5F51FV+NsyxslwkxHXQ6WxOtWgXSuYte0b/l2Km77o4DZKdbg2lZ/CNZ 8C9Gsx6X987BnORIW/4FdIPu9uH9oUBJW/VKSKSAqNHZ86EQ0zAauSKEp2+ryGIk8l6F kyPdl7Zy/lFR9Eo7/HF/7Lg88W6nPCd2mFzLiY0VV/ZpfbA6CDky1YpBg4CsxoDF2JS1 9Wwix5xnpXwD+dXf/EvZ6csv7s7KNZtgac5hoGsCIpu9rHZQSrSva2wwNxnhOvesmoWj LQjY5q7dU9SsoiUf5+LgmtsQc0Hdy0+uK5G+bV0LD1MvWBOoi3TLEqtT2T7+qb3m1Esc besQ== X-Gm-Message-State: AFuF++lyfshxOekh6PtW7ol+6MEz2LOkCjk9FWh2pb1OM5SWf/9yKwyO rj4wNyspu72LDMp3uY3WZZQtQFy+tfn4k6YadrScuj9QczzTpzWOt/29XNaSx+MRAOqX99lVxeR mAZAoWW0= X-Gm-Gg: AR+sD11WWJe3Kjp8FPGWSfH0Ey6RDWvbxEGSV8vNGEFGR2mY/HTg4HACfxnAWgKTbO1 NOWce7rjFmQkC/lqG0Igl4gvyi9QVd+6Z4akIqPVaHN+m6LK6n1r24QebihwkZEABwPRVHmxvaT EjtZCXB4pEhHk93NtYPbIhQCECj3aGlApkTn4XkpgwDiUKxsJzTSW9jtRO/2TTRv4k5DATJBYOq Q5Yh+CbvvTVENtCzU70Soiat6npZzaTArJhpKhkKKs4c60P+gq8F1mNEi0HgpYNd91rJegykyVI 1F47DCot7qI0YkVV3DGl4XWPI3AkuSb4KYYHxjbDAK7+rggIqxpr9cCLXl+i3H4NHLR5n1RfvV9 b3gZ24dKJkXIExqeGSKpmzz4pgu0DTDdJVW+SFD2UGaF7a5HOQk7TSBm88gnXkzt3b6qUp0Tdci oVYYY2PYTwDPrRP3SIBrge6rABrDY9BH9SWWFS0tdcwDSuDjzBcBlWuXI622a1Fa2BrqR//3Sw8 zbrE820H8N2l9hAdVyS3938orDGh9pYVZCbOAOxikEyhEqr2TCDlDxRzb/bmn307YEfkg== X-Received: by 2002:a17:906:170b:b0:c24:d6f0:1223 with SMTP id a640c23a62f3a-c25b3cba78bmr438843766b.12.1788268663844; Tue, 01 Sep 2026 06:17:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/58] hw/audio: Remove wm8750 I2C audio device Date: Tue, 1 Sep 2026 14:16:43 +0100 Message-ID: <20260901131732.2263947-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269114283154100 The wm8750 audio I2C device was used only by the audio device on the SoC used in the now-removed musicpal machine. Since it has no users, we can delete it entirely. Although the wm8750 is an I2C device that could technically have been created on the command line, it isn't possible to do this usefully because the device only works when C code calls functions like wm8750_data_req_set() and wm8750_dac_buffer(). This resolves the problem noted in issue #4135 that there's a buffer overflow in the interaction between the marvell_88w8618 audio device and the wm8750, by removing the offending code entirely. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4135 Signed-off-by: Peter Maydell Acked-by: Jan Kiszka Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260819185430.3467629-6-peter.maydell@linaro.org --- hw/audio/Kconfig | 4 - hw/audio/meson.build | 1 - hw/audio/wm8750.c | 738 -------------------------------------- include/hw/audio/wm8750.h | 30 -- 4 files changed, 773 deletions(-) delete mode 100644 hw/audio/wm8750.c delete mode 100644 include/hw/audio/wm8750.h diff --git a/hw/audio/Kconfig b/hw/audio/Kconfig index daf060e1be0..ed93fa26984 100644 --- a/hw/audio/Kconfig +++ b/hw/audio/Kconfig @@ -38,10 +38,6 @@ config PCSPK default y depends on I8254 =20 -config WM8750 - bool - depends on I2C - config PL041 bool =20 diff --git a/hw/audio/meson.build b/hw/audio/meson.build index c977679e23a..3312bcec101 100644 --- a/hw/audio/meson.build +++ b/hw/audio/meson.build @@ -11,6 +11,5 @@ system_ss.add(when: 'CONFIG_PCSPK', if_true: files('pcspk= .c')) system_ss.add(when: 'CONFIG_PL041', if_true: files('pl041.c', 'lm4549.c')) system_ss.add(when: 'CONFIG_SB16', if_true: files('sb16.c')) system_ss.add(when: 'CONFIG_VT82C686', if_true: files('via-ac97.c')) -system_ss.add(when: 'CONFIG_WM8750', if_true: files('wm8750.c')) system_ss.add(when: ['CONFIG_VIRTIO_SND', 'CONFIG_VIRTIO'], if_true: files= ('virtio-snd.c')) system_ss.add(when: ['CONFIG_VIRTIO_SND', 'CONFIG_VIRTIO', 'CONFIG_VIRTIO_= PCI'], if_true: files('virtio-snd-pci.c')) diff --git a/hw/audio/wm8750.c b/hw/audio/wm8750.c deleted file mode 100644 index e2507b0269a..00000000000 --- a/hw/audio/wm8750.c +++ /dev/null @@ -1,738 +0,0 @@ -/* - * WM8750 audio CODEC. - * - * Copyright (c) 2006 Openedhand Ltd. - * Written by Andrzej Zaborowski - * - * This file is licensed under GNU GPL. - */ - -#include "qemu/osdep.h" -#include "hw/i2c/i2c.h" -#include "migration/vmstate.h" -#include "qemu/module.h" -#include "hw/audio/wm8750.h" -#include "qemu/audio.h" -#include "qom/object.h" - -#define IN_PORT_N 3 -#define OUT_PORT_N 3 - -#define CODEC "wm8750" - -typedef struct { - int adc; - int adc_hz; - int dac; - int dac_hz; -} WMRate; - -OBJECT_DECLARE_SIMPLE_TYPE(WM8750State, WM8750) - -struct WM8750State { - I2CSlave parent_obj; - - uint8_t i2c_data[2]; - int i2c_len; - AudioBackend *audio_be; - SWVoiceIn *adc_voice[IN_PORT_N]; - SWVoiceOut *dac_voice[OUT_PORT_N]; - int enable; - void (*data_req)(void *, int, int); - void *opaque; - uint8_t data_in[4096]; - uint8_t data_out[4096]; - int idx_in, req_in; - int idx_out, req_out; - - SWVoiceOut **out[2]; - uint8_t outvol[7], outmute[2]; - SWVoiceIn **in[2]; - uint8_t invol[4], inmute[2]; - - uint8_t diff[2], pol, ds, monomix[2], alc, mute; - uint8_t path[4], mpath[2], power, format; - const WMRate *rate; - uint8_t rate_vmstate; - int adc_hz, dac_hz, ext_adc_hz, ext_dac_hz, master; -}; - -/* pow(10.0, -i / 20.0) * 255, i =3D 0..42 */ -static const uint8_t wm8750_vol_db_table[] =3D { - 255, 227, 203, 181, 161, 143, 128, 114, 102, 90, 81, 72, 64, 57, 51, 4= 5, - 40, 36, 32, 29, 26, 23, 20, 18, 16, 14, 13, 11, 10, 9, 8, 7, 6, 6, 5, = 5, - 4, 4, 3, 3, 3, 2, 2 -}; - -#define WM8750_OUTVOL_TRANSFORM(x) wm8750_vol_db_table[(0x7f - x) / 3] -#define WM8750_INVOL_TRANSFORM(x) (x << 2) - -static inline void wm8750_in_load(WM8750State *s) -{ - if (s->idx_in + s->req_in <=3D sizeof(s->data_in)) - return; - s->idx_in =3D MAX(0, (int) sizeof(s->data_in) - s->req_in); - audio_be_read(s->audio_be, *s->in[0], s->data_in + s->idx_in, - sizeof(s->data_in) - s->idx_in); -} - -static inline void wm8750_out_flush(WM8750State *s) -{ - int sent =3D 0; - while (sent < s->idx_out) - sent +=3D audio_be_write(s->audio_be, *s->out[0], - s->data_out + sent, s->idx_out - sent) - ?: s->idx_out; - s->idx_out =3D 0; -} - -static void wm8750_audio_in_cb(void *opaque, int avail_b) -{ - WM8750State *s =3D (WM8750State *) opaque; - s->req_in =3D avail_b; - s->data_req(s->opaque, s->req_out >> 2, avail_b >> 2); -} - -static void wm8750_audio_out_cb(void *opaque, int free_b) -{ - WM8750State *s =3D (WM8750State *) opaque; - - if (s->idx_out >=3D free_b) { - s->idx_out =3D free_b; - s->req_out =3D 0; - wm8750_out_flush(s); - } else - s->req_out =3D free_b - s->idx_out; - - s->data_req(s->opaque, s->req_out >> 2, s->req_in >> 2); -} - -static const WMRate wm_rate_table[] =3D { - { 256, 48000, 256, 48000 }, /* SR: 00000 */ - { 384, 48000, 384, 48000 }, /* SR: 00001 */ - { 256, 48000, 1536, 8000 }, /* SR: 00010 */ - { 384, 48000, 2304, 8000 }, /* SR: 00011 */ - { 1536, 8000, 256, 48000 }, /* SR: 00100 */ - { 2304, 8000, 384, 48000 }, /* SR: 00101 */ - { 1536, 8000, 1536, 8000 }, /* SR: 00110 */ - { 2304, 8000, 2304, 8000 }, /* SR: 00111 */ - { 1024, 12000, 1024, 12000 }, /* SR: 01000 */ - { 1526, 12000, 1536, 12000 }, /* SR: 01001 */ - { 768, 16000, 768, 16000 }, /* SR: 01010 */ - { 1152, 16000, 1152, 16000 }, /* SR: 01011 */ - { 384, 32000, 384, 32000 }, /* SR: 01100 */ - { 576, 32000, 576, 32000 }, /* SR: 01101 */ - { 128, 96000, 128, 96000 }, /* SR: 01110 */ - { 192, 96000, 192, 96000 }, /* SR: 01111 */ - { 256, 44100, 256, 44100 }, /* SR: 10000 */ - { 384, 44100, 384, 44100 }, /* SR: 10001 */ - { 256, 44100, 1408, 8018 }, /* SR: 10010 */ - { 384, 44100, 2112, 8018 }, /* SR: 10011 */ - { 1408, 8018, 256, 44100 }, /* SR: 10100 */ - { 2112, 8018, 384, 44100 }, /* SR: 10101 */ - { 1408, 8018, 1408, 8018 }, /* SR: 10110 */ - { 2112, 8018, 2112, 8018 }, /* SR: 10111 */ - { 1024, 11025, 1024, 11025 }, /* SR: 11000 */ - { 1536, 11025, 1536, 11025 }, /* SR: 11001 */ - { 512, 22050, 512, 22050 }, /* SR: 11010 */ - { 768, 22050, 768, 22050 }, /* SR: 11011 */ - { 512, 24000, 512, 24000 }, /* SR: 11100 */ - { 768, 24000, 768, 24000 }, /* SR: 11101 */ - { 128, 88200, 128, 88200 }, /* SR: 11110 */ - { 192, 88200, 192, 88200 }, /* SR: 11111 */ -}; - -static void wm8750_vol_update(WM8750State *s) -{ - /* FIXME: multiply all volumes by s->invol[2], s->invol[3] */ - - audio_be_set_volume_in_lr(s->audio_be, s->adc_voice[0], s->mute, - s->inmute[0] ? 0 : WM8750_INVOL_TRANSFORM(s->invol[0]), - s->inmute[1] ? 0 : WM8750_INVOL_TRANSFORM(s->invol[1])= ); - audio_be_set_volume_in_lr(s->audio_be, s->adc_voice[1], s->mute, - s->inmute[0] ? 0 : WM8750_INVOL_TRANSFORM(s->invol[0]), - s->inmute[1] ? 0 : WM8750_INVOL_TRANSFORM(s->invol[1])= ); - audio_be_set_volume_in_lr(s->audio_be, s->adc_voice[2], s->mute, - s->inmute[0] ? 0 : WM8750_INVOL_TRANSFORM(s->invol[0]), - s->inmute[1] ? 0 : WM8750_INVOL_TRANSFORM(s->invol[1])= ); - - /* FIXME: multiply all volumes by s->outvol[0], s->outvol[1] */ - - /* Speaker: LOUT2VOL ROUT2VOL */ - audio_be_set_volume_out_lr(s->audio_be, s->dac_voice[0], s->mute, - s->outmute[0] ? 0 : WM8750_OUTVOL_TRANSFORM(s->outvol[= 4]), - s->outmute[1] ? 0 : WM8750_OUTVOL_TRANSFORM(s->outvol[= 5])); - - /* Headphone: LOUT1VOL ROUT1VOL */ - audio_be_set_volume_out_lr(s->audio_be, s->dac_voice[1], s->mute, - s->outmute[0] ? 0 : WM8750_OUTVOL_TRANSFORM(s->outvol[= 2]), - s->outmute[1] ? 0 : WM8750_OUTVOL_TRANSFORM(s->outvol[= 3])); - - /* MONOOUT: MONOVOL MONOVOL */ - audio_be_set_volume_out_lr(s->audio_be, s->dac_voice[2], s->mute, - s->outmute[0] ? 0 : WM8750_OUTVOL_TRANSFORM(s->outvol[= 6]), - s->outmute[1] ? 0 : WM8750_OUTVOL_TRANSFORM(s->outvol[= 6])); -} - -static void wm8750_set_format(WM8750State *s) -{ - int i; - struct audsettings in_fmt; - struct audsettings out_fmt; - - wm8750_out_flush(s); - - if (s->in[0] && *s->in[0]) - audio_be_set_active_in(s->audio_be, *s->in[0], 0); - if (s->out[0] && *s->out[0]) - audio_be_set_active_out(s->audio_be, *s->out[0], 0); - - for (i =3D 0; i < IN_PORT_N; i ++) - if (s->adc_voice[i]) { - audio_be_close_in(s->audio_be, s->adc_voice[i]); - s->adc_voice[i] =3D NULL; - } - for (i =3D 0; i < OUT_PORT_N; i ++) - if (s->dac_voice[i]) { - audio_be_close_out(s->audio_be, s->dac_voice[i]); - s->dac_voice[i] =3D NULL; - } - - if (!s->enable) - return; - - /* Setup input */ - in_fmt.big_endian =3D false; - in_fmt.nchannels =3D 2; - in_fmt.freq =3D s->adc_hz; - in_fmt.fmt =3D AUDIO_FORMAT_S16; - - s->adc_voice[0] =3D audio_be_open_in(s->audio_be, s->adc_voice[0], - CODEC ".input1", s, wm8750_audio_in_cb, &in_fmt); - s->adc_voice[1] =3D audio_be_open_in(s->audio_be, s->adc_voice[1], - CODEC ".input2", s, wm8750_audio_in_cb, &in_fmt); - s->adc_voice[2] =3D audio_be_open_in(s->audio_be, s->adc_voice[2], - CODEC ".input3", s, wm8750_audio_in_cb, &in_fmt); - - /* Setup output */ - out_fmt.big_endian =3D false; - out_fmt.nchannels =3D 2; - out_fmt.freq =3D s->dac_hz; - out_fmt.fmt =3D AUDIO_FORMAT_S16; - - s->dac_voice[0] =3D audio_be_open_out(s->audio_be, s->dac_voice[0], - CODEC ".speaker", s, wm8750_audio_out_cb, &out_fmt); - s->dac_voice[1] =3D audio_be_open_out(s->audio_be, s->dac_voice[1], - CODEC ".headphone", s, wm8750_audio_out_cb, &out_fmt); - /* MONOMIX is also in stereo for simplicity */ - s->dac_voice[2] =3D audio_be_open_out(s->audio_be, s->dac_voice[2], - CODEC ".monomix", s, wm8750_audio_out_cb, &out_fmt); - /* no sense emulating OUT3 which is a mix of other outputs */ - - wm8750_vol_update(s); - - /* We should connect the left and right channels to their - * respective inputs/outputs but we have completely no need - * for mixing or combining paths to different ports, so we - * connect both channels to where the left channel is routed. */ - if (s->in[0] && *s->in[0]) - audio_be_set_active_in(s->audio_be, *s->in[0], 1); - if (s->out[0] && *s->out[0]) - audio_be_set_active_out(s->audio_be, *s->out[0], 1); -} - -static void wm8750_clk_update(WM8750State *s, int ext) -{ - if (s->master || !s->ext_dac_hz) - s->dac_hz =3D s->rate->dac_hz; - else - s->dac_hz =3D s->ext_dac_hz; - - if (s->master || !s->ext_adc_hz) - s->adc_hz =3D s->rate->adc_hz; - else - s->adc_hz =3D s->ext_adc_hz; - - if (s->master || (!s->ext_dac_hz && !s->ext_adc_hz)) { - if (!ext) - wm8750_set_format(s); - } else { - if (ext) - wm8750_set_format(s); - } -} - -static void wm8750_reset(I2CSlave *i2c) -{ - WM8750State *s =3D WM8750(i2c); - - s->rate =3D &wm_rate_table[0]; - s->enable =3D 0; - wm8750_clk_update(s, 1); - s->diff[0] =3D 0; - s->diff[1] =3D 0; - s->ds =3D 0; - s->alc =3D 0; - s->in[0] =3D &s->adc_voice[0]; - s->invol[0] =3D 0x17; - s->invol[1] =3D 0x17; - s->invol[2] =3D 0xc3; - s->invol[3] =3D 0xc3; - s->out[0] =3D &s->dac_voice[0]; - s->outvol[0] =3D 0xff; - s->outvol[1] =3D 0xff; - s->outvol[2] =3D 0x79; - s->outvol[3] =3D 0x79; - s->outvol[4] =3D 0x79; - s->outvol[5] =3D 0x79; - s->outvol[6] =3D 0x79; - s->inmute[0] =3D 0; - s->inmute[1] =3D 0; - s->outmute[0] =3D 0; - s->outmute[1] =3D 0; - s->mute =3D 1; - s->path[0] =3D 0; - s->path[1] =3D 0; - s->path[2] =3D 0; - s->path[3] =3D 0; - s->mpath[0] =3D 0; - s->mpath[1] =3D 0; - s->format =3D 0x0a; - s->idx_in =3D sizeof(s->data_in); - s->req_in =3D 0; - s->idx_out =3D 0; - s->req_out =3D 0; - wm8750_vol_update(s); - s->i2c_len =3D 0; -} - -static int wm8750_event(I2CSlave *i2c, enum i2c_event event) -{ - WM8750State *s =3D WM8750(i2c); - - switch (event) { - case I2C_START_SEND: - s->i2c_len =3D 0; - break; - case I2C_FINISH: -#ifdef VERBOSE - if (s->i2c_len < 2) - printf("%s: message too short (%i bytes)\n", - __func__, s->i2c_len); -#endif - break; - default: - break; - } - - return 0; -} - -#define WM8750_LINVOL 0x00 -#define WM8750_RINVOL 0x01 -#define WM8750_LOUT1V 0x02 -#define WM8750_ROUT1V 0x03 -#define WM8750_ADCDAC 0x05 -#define WM8750_IFACE 0x07 -#define WM8750_SRATE 0x08 -#define WM8750_LDAC 0x0a -#define WM8750_RDAC 0x0b -#define WM8750_BASS 0x0c -#define WM8750_TREBLE 0x0d -#define WM8750_RESET 0x0f -#define WM8750_3D 0x10 -#define WM8750_ALC1 0x11 -#define WM8750_ALC2 0x12 -#define WM8750_ALC3 0x13 -#define WM8750_NGATE 0x14 -#define WM8750_LADC 0x15 -#define WM8750_RADC 0x16 -#define WM8750_ADCTL1 0x17 -#define WM8750_ADCTL2 0x18 -#define WM8750_PWR1 0x19 -#define WM8750_PWR2 0x1a -#define WM8750_ADCTL3 0x1b -#define WM8750_ADCIN 0x1f -#define WM8750_LADCIN 0x20 -#define WM8750_RADCIN 0x21 -#define WM8750_LOUTM1 0x22 -#define WM8750_LOUTM2 0x23 -#define WM8750_ROUTM1 0x24 -#define WM8750_ROUTM2 0x25 -#define WM8750_MOUTM1 0x26 -#define WM8750_MOUTM2 0x27 -#define WM8750_LOUT2V 0x28 -#define WM8750_ROUT2V 0x29 -#define WM8750_MOUTV 0x2a - -static int wm8750_tx(I2CSlave *i2c, uint8_t data) -{ - WM8750State *s =3D WM8750(i2c); - uint8_t cmd; - uint16_t value; - - if (s->i2c_len >=3D 2) { -#ifdef VERBOSE - printf("%s: long message (%i bytes)\n", __func__, s->i2c_len); -#endif - return 1; - } - s->i2c_data[s->i2c_len ++] =3D data; - if (s->i2c_len !=3D 2) - return 0; - - cmd =3D s->i2c_data[0] >> 1; - value =3D ((s->i2c_data[0] << 8) | s->i2c_data[1]) & 0x1ff; - - switch (cmd) { - case WM8750_LADCIN: /* ADC Signal Path Control (Left) */ - s->diff[0] =3D (((value >> 6) & 3) =3D=3D 3); /* LINSEL */ - if (s->diff[0]) - s->in[0] =3D &s->adc_voice[0 + s->ds * 1]; - else - s->in[0] =3D &s->adc_voice[((value >> 6) & 3) * 1 + 0]; - break; - - case WM8750_RADCIN: /* ADC Signal Path Control (Right) */ - s->diff[1] =3D (((value >> 6) & 3) =3D=3D 3); /* RINSEL */ - if (s->diff[1]) - s->in[1] =3D &s->adc_voice[0 + s->ds * 1]; - else - s->in[1] =3D &s->adc_voice[((value >> 6) & 3) * 1 + 0]; - break; - - case WM8750_ADCIN: /* ADC Input Mode */ - s->ds =3D (value >> 8) & 1; /* DS */ - if (s->diff[0]) - s->in[0] =3D &s->adc_voice[0 + s->ds * 1]; - if (s->diff[1]) - s->in[1] =3D &s->adc_voice[0 + s->ds * 1]; - s->monomix[0] =3D (value >> 6) & 3; /* MONOMIX */ - break; - - case WM8750_ADCTL1: /* Additional Control (1) */ - s->monomix[1] =3D (value >> 1) & 1; /* DMONOMIX */ - break; - - case WM8750_PWR1: /* Power Management (1) */ - s->enable =3D ((value >> 6) & 7) =3D=3D 3; /* VMIDSEL, VREF */ - wm8750_set_format(s); - break; - - case WM8750_LINVOL: /* Left Channel PGA */ - s->invol[0] =3D value & 0x3f; /* LINVOL */ - s->inmute[0] =3D (value >> 7) & 1; /* LINMUTE */ - wm8750_vol_update(s); - break; - - case WM8750_RINVOL: /* Right Channel PGA */ - s->invol[1] =3D value & 0x3f; /* RINVOL */ - s->inmute[1] =3D (value >> 7) & 1; /* RINMUTE */ - wm8750_vol_update(s); - break; - - case WM8750_ADCDAC: /* ADC and DAC Control */ - s->pol =3D (value >> 5) & 3; /* ADCPOL */ - s->mute =3D (value >> 3) & 1; /* DACMU */ - wm8750_vol_update(s); - break; - - case WM8750_ADCTL3: /* Additional Control (3) */ - break; - - case WM8750_LADC: /* Left ADC Digital Volume */ - s->invol[2] =3D value & 0xff; /* LADCVOL */ - wm8750_vol_update(s); - break; - - case WM8750_RADC: /* Right ADC Digital Volume */ - s->invol[3] =3D value & 0xff; /* RADCVOL */ - wm8750_vol_update(s); - break; - - case WM8750_ALC1: /* ALC Control (1) */ - s->alc =3D (value >> 7) & 3; /* ALCSEL */ - break; - - case WM8750_NGATE: /* Noise Gate Control */ - case WM8750_3D: /* 3D enhance */ - break; - - case WM8750_LDAC: /* Left Channel Digital Volume */ - s->outvol[0] =3D value & 0xff; /* LDACVOL */ - wm8750_vol_update(s); - break; - - case WM8750_RDAC: /* Right Channel Digital Volume */ - s->outvol[1] =3D value & 0xff; /* RDACVOL */ - wm8750_vol_update(s); - break; - - case WM8750_BASS: /* Bass Control */ - break; - - case WM8750_LOUTM1: /* Left Mixer Control (1) */ - s->path[0] =3D (value >> 8) & 1; /* LD2LO */ - /* TODO: mute/unmute respective paths */ - wm8750_vol_update(s); - break; - - case WM8750_LOUTM2: /* Left Mixer Control (2) */ - s->path[1] =3D (value >> 8) & 1; /* RD2LO */ - /* TODO: mute/unmute respective paths */ - wm8750_vol_update(s); - break; - - case WM8750_ROUTM1: /* Right Mixer Control (1) */ - s->path[2] =3D (value >> 8) & 1; /* LD2RO */ - /* TODO: mute/unmute respective paths */ - wm8750_vol_update(s); - break; - - case WM8750_ROUTM2: /* Right Mixer Control (2) */ - s->path[3] =3D (value >> 8) & 1; /* RD2RO */ - /* TODO: mute/unmute respective paths */ - wm8750_vol_update(s); - break; - - case WM8750_MOUTM1: /* Mono Mixer Control (1) */ - s->mpath[0] =3D (value >> 8) & 1; /* LD2MO */ - /* TODO: mute/unmute respective paths */ - wm8750_vol_update(s); - break; - - case WM8750_MOUTM2: /* Mono Mixer Control (2) */ - s->mpath[1] =3D (value >> 8) & 1; /* RD2MO */ - /* TODO: mute/unmute respective paths */ - wm8750_vol_update(s); - break; - - case WM8750_LOUT1V: /* LOUT1 Volume */ - s->outvol[2] =3D value & 0x7f; /* LOUT1VOL */ - wm8750_vol_update(s); - break; - - case WM8750_LOUT2V: /* LOUT2 Volume */ - s->outvol[4] =3D value & 0x7f; /* LOUT2VOL */ - wm8750_vol_update(s); - break; - - case WM8750_ROUT1V: /* ROUT1 Volume */ - s->outvol[3] =3D value & 0x7f; /* ROUT1VOL */ - wm8750_vol_update(s); - break; - - case WM8750_ROUT2V: /* ROUT2 Volume */ - s->outvol[5] =3D value & 0x7f; /* ROUT2VOL */ - wm8750_vol_update(s); - break; - - case WM8750_MOUTV: /* MONOOUT Volume */ - s->outvol[6] =3D value & 0x7f; /* MONOOUTVOL */ - wm8750_vol_update(s); - break; - - case WM8750_ADCTL2: /* Additional Control (2) */ - break; - - case WM8750_PWR2: /* Power Management (2) */ - s->power =3D value & 0x7e; - /* TODO: mute/unmute respective paths */ - wm8750_vol_update(s); - break; - - case WM8750_IFACE: /* Digital Audio Interface Format */ - s->format =3D value; - s->master =3D (value >> 6) & 1; /* MS */ - wm8750_clk_update(s, s->master); - break; - - case WM8750_SRATE: /* Clocking and Sample Rate Control */ - s->rate =3D &wm_rate_table[(value >> 1) & 0x1f]; - wm8750_clk_update(s, 0); - break; - - case WM8750_RESET: /* Reset */ - wm8750_reset(I2C_SLAVE(s)); - break; - -#ifdef VERBOSE - default: - printf("%s: unknown register %02x\n", __func__, cmd); -#endif - } - - return 0; -} - -static uint8_t wm8750_rx(I2CSlave *i2c) -{ - return 0x00; -} - -static int wm8750_pre_save(void *opaque) -{ - WM8750State *s =3D opaque; - - s->rate_vmstate =3D s->rate - wm_rate_table; - - return 0; -} - -static int wm8750_post_load(void *opaque, int version_id) -{ - WM8750State *s =3D opaque; - - s->rate =3D &wm_rate_table[s->rate_vmstate & 0x1f]; - return 0; -} - -static const VMStateDescription vmstate_wm8750 =3D { - .name =3D CODEC, - .version_id =3D 0, - .minimum_version_id =3D 0, - .pre_save =3D wm8750_pre_save, - .post_load =3D wm8750_post_load, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT8_ARRAY(i2c_data, WM8750State, 2), - VMSTATE_INT32(i2c_len, WM8750State), - VMSTATE_INT32(enable, WM8750State), - VMSTATE_INT32(idx_in, WM8750State), - VMSTATE_INT32(req_in, WM8750State), - VMSTATE_INT32(idx_out, WM8750State), - VMSTATE_INT32(req_out, WM8750State), - VMSTATE_UINT8_ARRAY(outvol, WM8750State, 7), - VMSTATE_UINT8_ARRAY(outmute, WM8750State, 2), - VMSTATE_UINT8_ARRAY(invol, WM8750State, 4), - VMSTATE_UINT8_ARRAY(inmute, WM8750State, 2), - VMSTATE_UINT8_ARRAY(diff, WM8750State, 2), - VMSTATE_UINT8(pol, WM8750State), - VMSTATE_UINT8(ds, WM8750State), - VMSTATE_UINT8_ARRAY(monomix, WM8750State, 2), - VMSTATE_UINT8(alc, WM8750State), - VMSTATE_UINT8(mute, WM8750State), - VMSTATE_UINT8_ARRAY(path, WM8750State, 4), - VMSTATE_UINT8_ARRAY(mpath, WM8750State, 2), - VMSTATE_UINT8(format, WM8750State), - VMSTATE_UINT8(power, WM8750State), - VMSTATE_UINT8(rate_vmstate, WM8750State), - VMSTATE_I2C_SLAVE(parent_obj, WM8750State), - VMSTATE_END_OF_LIST() - } -}; - -static void wm8750_realize(DeviceState *dev, Error **errp) -{ - WM8750State *s =3D WM8750(dev); - - if (!audio_be_check(&s->audio_be, errp)) { - return; - } - - wm8750_reset(I2C_SLAVE(s)); -} - -#if 0 -static void wm8750_fini(I2CSlave *i2c) -{ - WM8750State *s =3D WM8750(i2c); - - wm8750_reset(I2C_SLAVE(s)); - g_free(s); -} -#endif - -void wm8750_data_req_set(DeviceState *dev, data_req_cb *data_req, void *op= aque) -{ - WM8750State *s =3D WM8750(dev); - - s->data_req =3D data_req; - s->opaque =3D opaque; -} - -void wm8750_dac_dat(void *opaque, uint32_t sample) -{ - WM8750State *s =3D (WM8750State *) opaque; - - *(uint32_t *) &s->data_out[s->idx_out] =3D sample; - s->req_out -=3D 4; - s->idx_out +=3D 4; - if (s->idx_out >=3D sizeof(s->data_out) || s->req_out <=3D 0) - wm8750_out_flush(s); -} - -void *wm8750_dac_buffer(void *opaque, int samples) -{ - WM8750State *s =3D (WM8750State *) opaque; - /* XXX: Should check if there are samples free samples availabl= e */ - void *ret =3D s->data_out + s->idx_out; - - s->idx_out +=3D samples << 2; - s->req_out -=3D samples << 2; - return ret; -} - -void wm8750_dac_commit(void *opaque) -{ - WM8750State *s =3D (WM8750State *) opaque; - - wm8750_out_flush(s); -} - -uint32_t wm8750_adc_dat(void *opaque) -{ - WM8750State *s =3D (WM8750State *) opaque; - uint32_t *data; - - if (s->idx_in >=3D sizeof(s->data_in)) { - wm8750_in_load(s); - if (s->idx_in >=3D sizeof(s->data_in)) { - return 0x80008000; /* silence in AUDIO_FORMAT_S16 sample forma= t */ - } - } - - data =3D (uint32_t *) &s->data_in[s->idx_in]; - s->req_in -=3D 4; - s->idx_in +=3D 4; - return *data; -} - -void wm8750_set_bclk_in(void *opaque, int new_hz) -{ - WM8750State *s =3D (WM8750State *) opaque; - - s->ext_adc_hz =3D new_hz; - s->ext_dac_hz =3D new_hz; - wm8750_clk_update(s, 1); -} - -static const Property wm8750_properties[] =3D { - DEFINE_AUDIO_PROPERTIES(WM8750State, audio_be), -}; - -static void wm8750_class_init(ObjectClass *klass, const void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - I2CSlaveClass *sc =3D I2C_SLAVE_CLASS(klass); - - dc->realize =3D wm8750_realize; - sc->event =3D wm8750_event; - sc->recv =3D wm8750_rx; - sc->send =3D wm8750_tx; - dc->vmsd =3D &vmstate_wm8750; - device_class_set_props(dc, wm8750_properties); -} - -static const TypeInfo wm8750_info =3D { - .name =3D TYPE_WM8750, - .parent =3D TYPE_I2C_SLAVE, - .instance_size =3D sizeof(WM8750State), - .class_init =3D wm8750_class_init, -}; - -static void wm8750_register_types(void) -{ - type_register_static(&wm8750_info); -} - -type_init(wm8750_register_types) diff --git a/include/hw/audio/wm8750.h b/include/hw/audio/wm8750.h deleted file mode 100644 index f7bafd5e384..00000000000 --- a/include/hw/audio/wm8750.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or - * more details. - * - * You should have received a copy of the GNU General Public License along= with - * this program. If not, see . - */ -#ifndef HW_DAC_WM8750_H -#define HW_DAC_WM8750_H - - -#define TYPE_WM8750 "wm8750" -#define TYPE_MV88W8618_AUDIO "mv88w8618_audio" - -typedef void data_req_cb(void *opaque, int free_out, int free_in); - -void wm8750_data_req_set(DeviceState *dev, data_req_cb *data_req, void *op= aque); -void wm8750_dac_dat(void *opaque, uint32_t sample); -uint32_t wm8750_adc_dat(void *opaque); -void *wm8750_dac_buffer(void *opaque, int samples); -void wm8750_dac_commit(void *opaque); -void wm8750_set_bclk_in(void *opaque, int new_hz); - -#endif --=20 2.43.0 From nobody Sat Sep 26 20:51:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788269092; cv=none; d=zohomail.com; s=zohoarc; b=VWbhu9csaq1GGPWG9+s2bRCHPUqBtqY4W6RhYCkYGMFdMZTEXh+x3hKzNIldGYfW/HkajqxmTnnme6R6p6A4yqQ5w8rJ7Tf30k55WwwZGM1slO9u7Ii16kIgi+w8DeqBe6IBzS1M8Cbi1gVjgpiPB1YOtXDKD+m0gGYbTEAyNWE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788269092; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=hHa7uKqDce6F9DSBhR1Ee9VldNHnO6yCRGsv4+2ezRk=; b=BRK1bZcMYii7oS8/QYIy8qANma97QYKdRdI6UgEj0tzzZD9PdKhOd58xg+8VfvUVkzk8avVq889Zu0hgJLmBGgGaB+GuthRolw6FKgVaz9Kp9TZAONnyjsSNCMBuTZ51P8ww9orbK1hdCevNwWfiGJJLqMlQg1mfmz7h0OBPiYI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178826909237153.00144006076334; Tue, 1 Sep 2026 06:24:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ON8-00010j-6P; Tue, 01 Sep 2026 09:17:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ON1-0000x6-Uh for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:48 -0400 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ON0-00078m-8D for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:47 -0400 Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-c20ce3c118aso207117066b.0 for ; Tue, 01 Sep 2026 06:17:45 -0700 (PDT) Received: from lanath.. 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This is correct for the new-style unaligned accesses rules that were introduced in ARMv6 when SCTLR.U =3D=3D 1 and then became the only option from ARMv7 (where SCTLR.U is RES1). However, it isn't right for the old ARMv4 and ARMv5 setup (and ARMv6 when SCTLR.U =3D 0). We don't emulate the v4/v5 alignment rules (which notably include "for unaligned LDR, do an aligned load and rotate"); but taking an alignment fault is definitely wrong and isn't what QEMU has traditionally done. Restrict this behaviour to when SCTLR.U is 1. (The other place we enable alignment checks on Device memory is in ptw.c, but we only set TLB_CHECK_ALIGNED for LPAE translations, which are guaranteed to be v7 or later.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260819190015.3555218-1-peter.maydell@linaro.org --- target/arm/tcg/hflags.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 296ec8101ab..c7739fc61b2 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -47,6 +47,18 @@ static bool aprofile_require_alignment(CPUARMState *env,= int el, uint64_t sctlr) return false; } =20 + /* + * Pre-v6 had a completely different model for unaligned accesses, + * which doesn't include taking unaligned faults for Device memory. + * v6 has the new model only when SCTLR.U is set. Later architecture + * versions repurpose the SCTLR bit for something else, so we mustn't + * test it except for actual v6 CPUs. + */ + if (!arm_feature(env, ARM_FEATURE_V6) || + (!arm_feature(env, ARM_FEATURE_V7) && !(sctlr & SCTLR_U))) { + return false; + } + /* * With VMSA, if translation is disabled, then the default memory type * is Device(-nGnRnE) instead of Normal, which requires that alignment --=20 2.43.0 From nobody Sat Sep 26 20:51:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268706; cv=none; d=zohomail.com; s=zohoarc; b=Vh4wqbricMp08kLRaoCs5ZVJCtrcUUaqP2ngcOKXjAWFl0RmhEO4uXlPyLjayQHE0Cr7zxpAK5zktoqSgZ2mO9toEaMPajs6wxwCeVHvmrySNI6ZGAiL7HM+SEVxpdtZQE3sbeNZ38XRkKy7zHxdoMJyuN+HyrcPwJqSpkbDMgU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268706; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=m3t5attEc6DBgbJ3tNga/MsrgOgKkBBlm9lBtl53/Sc=; b=cbTtJDxfOLrNNDwt+hOhdePbZzwQWMHhf9olbgvYYPQyXh6k7AFBBD/nB3rm4i2DgdccF2MhfMzjdRr0jVEIrA1ITOr5N5AJD/auNjnbQ2QwDwV25rQbUQUpz/1JEiUt5jbYlAWbRYIkUtL3FpFq/YraDxGtmDDk0g4RavFTOP4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17882687059821003.3925949048839; Tue, 1 Sep 2026 06:18:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ON9-000119-36; Tue, 01 Sep 2026 09:17:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ON3-0000xn-25 for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:49 -0400 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ON1-00078x-GB for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:48 -0400 Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-c25420fe973so145335366b.0 for ; Tue, 01 Sep 2026 06:17:46 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268666; x=1788873466; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=m3t5attEc6DBgbJ3tNga/MsrgOgKkBBlm9lBtl53/Sc=; b=lHHg25t3GH+g+uMWz8saYbVJOdJk00T48o0b45XIoWxgUrM+802gyZkXRyopHPiCpk F97SGMivZQ6kdjVF0vn9F1Lam0rc8LGqdu6gWMhLaBNaOggmJwBNoMcvUKWu32wLPabo NT+ndh3uUFkrkJ4xZhNyagS+AYMvAjzR+RKn5bp4CJVTaGywI7wSWGgHVzeJLNTC8kON HG0eAFlV9DA1nr3rdM8GXRnSLgwsVyrDh8NdbtxaZEXXR2/h8Ns5oh1e3uvlOjuMkAjs +skZIYSBdHjaxIqDtHw/tDnDTbeKHduIFFJTOmHNC69UKYMR4zu9DUvTuNgpxHhwHq7F C+uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268666; x=1788873466; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=m3t5attEc6DBgbJ3tNga/MsrgOgKkBBlm9lBtl53/Sc=; b=f+PbmHK7Z3jx+FmWIeIXB8l5I7jgmXsXKJ9i1UrXD74tOIgfCt40jZ6TB1er2zimOe 92Z0gM6Yg8PrD8xiJFORLskF9SJYbgOYaNR3Sc81z+GyVFHE4lja3R5Av5o2h0CYJ0bl 9S2h3lUxRewCpqp2JtXtTKfO8O1zFOoq5t4X0nGX7A+jq4dtRZ5bhLQKq7qYyQJzbBIt rxDkZLo7+G/ob3PgOx8JmrwR9YIvnL7xDIzFpu70Y7vpTOkmNOa93XOhwgjaGtgZWYZV F9meydvYwAIj27cM33UiqBqqDW4CUJjrKks1offU8p/mwue2pHfPs7wUWAWtMjdX6vHN RMWQ== X-Gm-Message-State: AFuF++mlQ7d/o2hrluv4l4/DsF77sgCzkMd5fM3i+yG5SiZGLir3aT0z FDv7pRBPUBaeLlfeKTMBNO8sFqO8F3RZFbPaTrxjqVGSOqU96LZEvs0Ldq/2QzTrRgNFBClXfZk WXKFlba0= X-Gm-Gg: AR+sD126GQPmruglpE+akZ2B7EMOZLPfJ+qxnSHPWMG9d9jJl/oVj8zpXLazJ06vizs 5fP1CoHchSTSfBGqFVIsDRDJ8SS8gjiLnn07BGfw7eyVZeeJ0p52TY5jTnTCEAd/q7+C59ZfL66 GqaRtRQwzpQkSi4WN55Vj1yDUoQnQViPzcu1AL1+ld3XV2CilpZ938P27FvUdhMkFzyG91LIeXP r8MrYybbbxVYrjhcNBi9NrC/GPeHIINS5DmKT/iXSNKWvzHLcur28qONHgVu+GxJoz1eAcuzvvq FRt2CiNRIexUrx7b/7Lub0eRooGgUe5/CIvMR1rT1v96y5up4A6EPTF5tKQZshJ+QR2nzSGs+5D Uq5qCOuwogYfE6N12Lts+OZSlSbUo5jWYlCghjfS8ChVHCKL+HLvF3K1QwHArArwr8kc1doeWl1 T6t6/oAhZJPcB51RH0hE8MeEGiixF2b56vuwTJk3enbQGlzeip3AedBi+1tBPwKkBF7Kn6si/SJ Mg6g2wQdxxzshJB6aSxL9JMsZEX+Y6QiU1NASTaB2frnBvJPZpzz1f0nVhN7FBoWf0rSA== X-Received: by 2002:a17:907:9809:b0:c24:6f60:3f7e with SMTP id a640c23a62f3a-c2556fe8495mr2355910866b.2.1788268665712; Tue, 01 Sep 2026 06:17:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/58] target/arm: Make CBZ/CBNZ UNDEF before v6T2 Date: Tue, 1 Sep 2026 14:16:45 +0100 Message-ID: <20260901131732.2263947-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268709146158500 Content-Type: text/plain; charset="utf-8" The Thumb CBZ/CBNZ encodings are only introduced in v6T2 (for A-profile) and v7M (for M-profile). We missed out the feature-check in trans_CBZ(), so don't UNDEF on v5T or v6M. Add the missing check: conveniently, the ARM_FEATURE_THUMB2 feature is true for exactly the cases where CBZ is implemented. Cc: qemu-stable@nongnu.org Fixes: 9ee6e8bb853bde ("ARMv7 support.") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260821132550.168896-2-peter.maydell@linaro.org --- target/arm/tcg/translate.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index c866148383f..1a7dd77a9c8 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -5783,7 +5783,14 @@ static bool trans_TBH(DisasContext *s, arg_tbranch *= a) =20 static bool trans_CBZ(DisasContext *s, arg_CBZ *a) { - TCGv_i32 tmp =3D load_reg(s, a->rn); + TCGv_i32 tmp; + + /* CBZ was introduced in v6T2 and v7M */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) { + return false; + } + + tmp =3D load_reg(s, a->rn); =20 arm_gen_condlabel(s); tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE, --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268881; cv=none; d=zohomail.com; s=zohoarc; b=Na1J/JWjuOntEEuZRywwDbdHZFlkvJcVnPfs/OhV/lcXCpe5VITTClnCLXDatLZzxeldUpmHimLVK8FwEKrztaVO5386XrV1hpvwQvDcgQCSUokrXY3QEt7bN46WHH6ibvukcrnUhpHVOXTdfd4Rde0wSdeh2vdUD9TgqqbMWkA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268881; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=V53Rb25nHYpLt74htQ81hutLVHNLXyZvQF/s+NqbH70=; b=RsTxaeQdM+jDNzqM9+9ll2wX7Y25LgrKEJiHYIdJFHE/e6PmCddgTa4Hf3YtOr6Mwnrbqon7E/7inD//RwIP66qHCPsiU1vTvTLUqzjialqi5pe4LOhXpSL+J3XfBh7U2vBvZIvPfJOvJjZZHwV1xrJSS7hmvSdexszOoRAT3NM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268881626797.8210825153524; Tue, 1 Sep 2026 06:21:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ON6-00010Y-9H; Tue, 01 Sep 2026 09:17:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ON4-0000zX-86 for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:50 -0400 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ON2-000797-8U for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:49 -0400 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-c15e592da74so567692166b.1 for ; Tue, 01 Sep 2026 06:17:47 -0700 (PDT) Received: from lanath.. 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We were missing the feature-check, so fail to UNDEF on earlier cores. Add the missing check. Cc: qemu-stable@nongnu.org Fixes: 9ee6e8bb853bde ("ARMv7 support.") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260821132550.168896-3-peter.maydell@linaro.org --- target/arm/tcg/translate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 1a7dd77a9c8..f013f94b217 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -1,3 +1,4 @@ + /* * ARM translation * @@ -6038,6 +6039,16 @@ static bool trans_IT(DisasContext *s, arg_IT *a) { int cond_mask =3D a->cond_mask; =20 + /* + * IT insn introduced in v6T2 for A-profile; it is only present + * on M-profile if the Main Extension is implemented. + */ + if (!(arm_dc_feature(s, ARM_FEATURE_M) + ? arm_dc_feature(s, ARM_FEATURE_M_MAIN) + : arm_dc_feature(s, ARM_FEATURE_THUMB2))) { + return false; + } + /* * No actual code generated for this insn, just setup state. * --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268772; cv=none; d=zohomail.com; s=zohoarc; b=N49CEXEPfoQlZKqSJja5EhyZRALY2PlKiLoEQI0DMP/XBDjnf7616IsNDPh5496wZI+LW3ehbcYWJW3z3dvvRIhIWyQsvhMDjHgmxDSegzj5CKWneibAvydJXtrD12wT47kcS6hZK3hAUs0WFi5TL2rKFHEAaEN9XUyIrBXhMEA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268772; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=x6RZtMUWEU74PB1FgRz3pqt0ToXGlta6YwXXlSSBNRk=; b=CVP25NAjG+ao6QgBs6pbwopY600m9Y2IrxFEF5FMZNjRJm7asD35DuccBAK7xSpdxCJgo9USzUtQY3CXHcdKTmy787+iAqYogFdJBqbmYamxrGxFxPb6NIc7C5rlhVj8UxMwmzEoSB6eMk2iRiDYZbs18h5jfj1mGtGZ/nh7shE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268772239256.72801415398567; Tue, 1 Sep 2026 06:19:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONB-00012A-8R; Tue, 01 Sep 2026 09:17:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ON5-00010C-T3 for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:52 -0400 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ON4-0007A6-0j for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:51 -0400 Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-c25420fe973so145344566b.0 for ; Tue, 01 Sep 2026 06:17:48 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268667; x=1788873467; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=x6RZtMUWEU74PB1FgRz3pqt0ToXGlta6YwXXlSSBNRk=; b=a5SXPX111un6KznJjxzMLbTKgJXIzyXoa2xr1WhNBm1KLDNHXLcZCi4ofUC7VoVPbX tQorSmN4nmgdGbXUD3mFr/rpzzfkpFJHVJrG8aacsDqIaVRXuDwcuoYwfJSSUup90SRf RKbPnC511tpXa9Q3OnkgAqwQfUE69XgGWyNcmOpXOFu/R/MKo4C+ANuW3h+PTFDwXuRM V0zcyEfmRCy4+gGR69DxXkMu1FIZ/b7nbxw06Mwu8J/XxHEeAa7cYEMOgzfkVnlDH7Yf lLy9Yl96oLsJHLZq5Y14oxl6/ZtU9uaZdbBapTTzRmMxwQG4nGTgZTd7/e97+Dcj2PSa 4AIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268667; x=1788873467; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=x6RZtMUWEU74PB1FgRz3pqt0ToXGlta6YwXXlSSBNRk=; b=ovN87HZc1I7oajoUPESKtmBpGKFFa5byO0im8laayNhCHLe8xbkwf3Vr3s/GoRn2f7 KOKckmRjm3/2iOmPkeqTBLbsCPwIgFv6T9ZBffeRvqx5Zvmt/0HO4gTOPzuakZGV+2J/ Pga5iBKG8qo8jDEPfDcPqmbuU9uyE5JwjevZnQhDVEg1dr5D4NqVJ69VW4x9vzUp0B3P 7RTF3kSCEX6VTeazuMEwdEK+Dmf9N7AUn7oL5qJFOVRziFtXOMq4xm21IJqzipqEWWrs XJEhjM7LpKyO+sZqOg66gb9hInVEJP6XwEaPOcwF1zj9UYW51lVbrxfuTbgfS4oF/VEE Kmng== X-Gm-Message-State: AFuF++kxJfg0dHxmJaTz3fhF4d8WvqLrYKNEwuT1RxE4RvmiV4RtgzwS 6DtMUjmyvjnF8QhPaZjKA4SiaV5V5V3P2S/G1/FQA0sw28pQTave1ExzNaEzyDUD3kAT9dc/4Im SE1HUyLc= X-Gm-Gg: AR+sD119EtHCzgIwO6k4xqwmFxESetWZJ8jJrU7m5vzaXudQykKl06s5Uh4S/k+ZQjz rX6yc/bP91XxAei+SkplVV3aLPsy6L2lSTAhkhe8Xz7gs/4NBFzE2Mda0u/BUyzeJAzWorrYLYS J3v2UnNjaFKX74ZtVNpaHtu5//+Ipw1s+n3o/HJjzq8bW0Ym800Mmi9BXiuUQ0A543VFkbc+NMu HKQwJ/cdtsnQZ/q+LsWZMeGALt3jg7pAdI75PSi2uUmuoDoGshWNfTiOWKjyhKws8JlG0KU6ysf D2e/DBqKWBNKicfur/ywIos641bv4BxyJHoTmM8KkRd5fsG522kYiWD/nRLUJmLQ0I0UjEG7NxL 6J74++1KP712FiG1pVctwTAWFlHMLxUSM1QOgT0pxEHVtskIkKvNAS1dQfiHZvfPaNkFtUD03Zo KrHkNJsEGUS6KY2Fo1F11DTXypfJ2xFKeB5rSk4s0YFgvPd8CB8/XN8FM3ty8FjX9Ssp2+rmX8+ jPDX6/jQnpLQUsVUYaTrr7DFX7rth42W1qgYvBpVC3QiJqjdxPe97gtnRmna66WXCf1fQ== X-Received: by 2002:a17:907:3e04:b0:c1c:2173:d412 with SMTP id a640c23a62f3a-c2556fe9307mr2076595066b.1.1788268667603; Tue, 01 Sep 2026 06:17:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/58] target/arm: Make Thumb T1 hint space UNDEF before v6T2 Date: Tue, 1 Sep 2026 14:16:47 +0100 Message-ID: <20260901131732.2263947-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268774444154100 Content-Type: text/plain; charset="utf-8" The "hint space" is a region of the encoding space which is defined to NOP if not specified as an architected instruction, so that future instructions can be added there which fall back to NOPs on older CPUs. In the A32 encoding, this hint space was carved out of the MSR (imm) insn by using the fact that a field_mask (bits [19:15]) of 0b0000 meant that an MSR (imm) would set no parts of the CPSR from the immediate, so it was always NOP on existing CPUs. For the T1 encoding, the hint space is in a range that used to UNDEF in Armv5, and so the hint insns and the NOP region must all UNDEF before v6T2. Rather than putting this check in the trans functions for each hint insn and for the NOP space (which is a lot of places, and awkward since those trans functions are often shared with the A64 and A32 encodings), put in a decode line that covers the whole space which we check before any of the hints and which will explicitly UNDEF if necessary. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4208 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260821132550.168896-4-peter.maydell@linaro.org --- target/arm/tcg/t16.decode | 3 +++ target/arm/tcg/translate.c | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/target/arm/tcg/t16.decode b/target/arm/tcg/t16.decode index 9a8f89538ac..43cd36e949c 100644 --- a/target/arm/tcg/t16.decode +++ b/target/arm/tcg/t16.decode @@ -224,6 +224,9 @@ REVSH 1011 1010 11 ... ... @rdm =20 { { + # Before v6T2 this was not NOP space and must UNDEF + MAYBE_UNDEF_T1_HINT 1011 1111 ---- 0000 + YIELD 1011 1111 0001 0000 WFE 1011 1111 0010 0000 WFI 1011 1111 0011 0000 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index f013f94b217..8c56348a665 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -3340,6 +3340,24 @@ static bool trans_NOP(DisasContext *s, arg_NOP *a) return true; } =20 +static bool trans_MAYBE_UNDEF_T1_HINT(DisasContext *s, + arg_MAYBE_UNDEF_T1_HINT *a) +{ + /* + * The Thumb T1 encoding hint space was only defined starting + * in v6T2 for A-profile. For M-profile it always exists, even + * in v6M. + */ + if (arm_dc_feature(s, ARM_FEATURE_M) || + arm_dc_feature(s, ARM_FEATURE_THUMB2)) { + /* Allow decode to fall through to the hint insns and NOP space */ + return false; + } + /* On the earlier cores, we must UNDEF */ + unallocated_encoding(s); + return true; +} + static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) { uint32_t val =3D ror32(a->imm, a->rot * 2); --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788269104; cv=none; d=zohomail.com; s=zohoarc; b=JeGc6h/MyywJu08zC2XIy+F/S5xJqB9EX5i1oz7ecmNXJC8bj5tCeKkWk6CrkrN6JlKoUt81Iw5WHZLZHq/sg+TSmz54oJ4tRB+1zm1tBmgh8vBzCGb9B6sfA+IpIqMQ6aW+F4hkkTTHYtZdaJpykKGqKsdkfldFGSZpt5o68xM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788269104; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=OsrVSZpdhbl0zgw5Bd147ufAXlFL6P0PvWbOYEnG4Tg=; b=FvPrm55sAo1uGGC2sJGDxncZtTQP8axnAIBAWTOfwYrIHsSyEMlKT2uH0mdw2jAxFREY/0CuwlVvvO/hfafuqPTxnRlvYJ+mmfFNYNyWP3iJdXKVB/eYP8syWhdOVefSkLwTJ3htw9bAUdRIVrrknLHILu8cfbTsQO3aaoykSk8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788269104887660.7347730701023; Tue, 1 Sep 2026 06:25:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONA-00011w-Ho; Tue, 01 Sep 2026 09:17:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ON6-00010F-2z for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:52 -0400 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ON4-0007AR-8l for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:51 -0400 Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-c253425b253so132337566b.1 for ; Tue, 01 Sep 2026 06:17:49 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268669; x=1788873469; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=OsrVSZpdhbl0zgw5Bd147ufAXlFL6P0PvWbOYEnG4Tg=; b=v2faCUh/9mkJx4wjB6feqdlCLK5XztpF/QjPPRvkRz8k8zLI3105KTmMSBcOzgeOXC wxlVZxH4gKcsa25m+GCynYzh4RdIBLz/ZkfCrvw6PNY0NUvMDfIBNJzI3r4T5pU3UYLd xDj93xQyQJ8i5eaWOsSsvpiBEmLWi/cnyy67pLc7WZcv1TdMprut7SXZ1N39jlnbNduU 8xgj2J6x3WrxmRGjstbtfMmkW7wQxnkKWmMn3iXEbcr/lREkc9STOcYjqBwGuFRuqdLL Elwd7uX+7IqmrGs/I1hy9xoSNownR3M5fc0DIMBCkW/7aAZz35RIUU5MP8CZzVt7k5wr 4oYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268669; x=1788873469; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=OsrVSZpdhbl0zgw5Bd147ufAXlFL6P0PvWbOYEnG4Tg=; b=pGAeSvalL/h5X7UpXL1/LVMwbnX205NuPyl+YesNpixZFR2FYmfd1kJq8aKvLGwtzG xBA9JYDtmgC17EGmvdPE6xCYbecY/2/HI1VS/ynkwCusBdhq6kViT84IDlMkGI702QX0 21AMtR0cip9AJH5XakMDYO5i0Te1ZTcHghEftsM+D4jLSTiJeJVBAluxD85P+gtSgdXL XOtAAsPtOt/SE+U6hUorG6NGSinX4zWx6bgZwLIgnlrb5e3fLZ83lwnow2Vg10Rr981H pAKw39/aODg2y+Km5KsVqs1ydxO72EhG5qNNsj096cioGhapxRrh2XYaFZf/pZISLEoC SUlg== X-Gm-Message-State: AFuF++liHf7AEnWAw7xGG6g26830eFaspeYnbIxbKUKEQXj3G9EgHOjW aHqX254/B1U+XBCYFFhVuwmC3sLli+l64/nVriGV04lu7+eMT7+cDvd4I7gPn3Q9COD0NJ2uki5 IDigX4fE= X-Gm-Gg: AR+sD11Lu7LJL/PISRX7LAITxiG3daJMp4z/ItwanIjbQfrGGHnEEh40SKs5X5qAVpr 5iWQlK3dJX4s2OyTEVTMbvJRsu5C9+7vK1J++EEtee0qHAs/paG0no0rNSrdKSDbMVenVE3pquW 5ZLnzDSVxCQO1GAMms3Zim49n2Nh5U5n5oXdpi6acjRDQnHmQv21RegZyXGT3iRHvF8baFzuUz3 k7l6H5EXTw6zUybyVl4Ig0YxBjwI/NfgDySNGS2QZOGWgFgNcOZM1l+GU00tOBqkW/PUnvli2tw FDZ05s6lbN5t+tvUpD3njr7u9VevcbKyRY0zgg5h/gj4S1Stt0HV1EiaHO1qdLTNfAsYGMiGpzH RQHcynVFu66kN2DQaCmafA0RO96cpMhYM/wbv21RV9sxxIch2SgUgR5x2YZOqwhbhJ0sdySb0o/ KTgg2M1OPsGywPb/MLmOWjQ3EJbSUVhCKzexDoXnumsJFY7gx8oUE4PfV34Qcqc4TGG4Eb37E9x MAavF0NxPKtswhYWw7TYVz978KNziaJPttpIp/MAwM6DD9yEMybJmFfJDVc2LlLBfmmuWtEM20Z DQAw X-Received: by 2002:a17:907:cd0e:b0:c25:2fb9:b897 with SMTP id a640c23a62f3a-c2557164d7fmr2171221466b.18.1788268668654; Tue, 01 Sep 2026 06:17:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/58] target/arm/tcg/cpu-v7m.c: add cortex-m85 model Date: Tue, 1 Sep 2026 14:16:48 +0100 Message-ID: <20260901131732.2263947-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269105885158500 Content-Type: text/plain; charset="utf-8" From: Simon Xu Add Arm Cortex-M85 CPU. This is quite similar to the existing Cortex-M85. ID register values are based on the r1p1 TRM: https://developer.arm.com/documentation/101924/0101/ In hardware, PACBTI support can be configured in or out; as QEMU does not yet implement it, we report it as not present in ID_ISAR5. Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Message-Id: <20260805153005.9989-2-simonxhy0404@gmail.com> [PMM: tweaked commit message, expanded comment about PACBTI] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/cpu-v7m.c | 47 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index dc249ce1f14..48b31d5eac8 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -237,6 +237,51 @@ static void cortex_m55_initfn(Object *obj) cpu->ctr =3D 0x8303c003; } =20 +static void cortex_m85_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_V8_1M); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x411fd231; /* r1p1 */ + cpu->revidr =3D 0; + cpu->pmsav7_dregion =3D 16; + cpu->sau_sregion =3D 8; + /* These are the MVFR* values for the FPU + full MVE configuration */ + cpu->isar.mvfr0 =3D 0x10110221; + cpu->isar.mvfr1 =3D 0x12100211; + cpu->isar.mvfr2 =3D 0x00000040; + SET_IDREG(isar, ID_PFR0, 0x20000030); + SET_IDREG(isar, ID_PFR1, 0x00000230); + SET_IDREG(isar, ID_DFR0, 0x10200000); + SET_IDREG(isar, ID_AFR0, 0x00000000); + SET_IDREG(isar, ID_MMFR0, 0x00111040); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x01000000); + SET_IDREG(isar, ID_MMFR3, 0x00000011); + SET_IDREG(isar, ID_ISAR0, 0x01103110); + SET_IDREG(isar, ID_ISAR1, 0x02212000); + SET_IDREG(isar, ID_ISAR2, 0x20232232); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + /* + * Real Cortex-M85 CPUs can be configured with or without PACBTI. + * If PACBTI is present then ID_ISAR5[23:20] read as 0b0100, + * indicating that QARMA3 is used. QEMU does not yet implement + * PACBTI emulation for M-profile, so we report as a "no-PACBTI" + * CPU for now. + */ + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); + SET_IDREG(isar, CLIDR, 0x00000000); /* caches not implemented */ + cpu->ctr =3D 0x8303c003; +} + static const TCGCPUOps arm_v7m_tcg_ops =3D { /* ARM processors have a weak memory model */ .guest_default_memory_order =3D 0, @@ -290,6 +335,8 @@ static const ARMCPUInfo arm_v7m_cpus[] =3D { .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m55", .initfn =3D cortex_m55_initfn, .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m85", .initfn =3D cortex_m85_initfn, + .class_init =3D arm_v7m_class_init }, }; =20 static void arm_v7m_cpu_register_types(void) --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268783; cv=none; d=zohomail.com; s=zohoarc; b=Z3aGf3i8tn7N0JBcl8UbYUjUhcLelpq/VUfklKP4BiNPCkK02OkJ71NHgXX0E0bwKizi9xZKGNss8C74303X5O2j/4ChJQp/T8opOcPYs52qwNnM7GP5SMs0e5FwbGRxyZQzzdn9yiLRbLJ2zmpjyt8xXVe8EFQcqAktgOdV8Mk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268783; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=CoZBy8mdMV8ir86rLFIE1AfaPu8GaWAQzlSGhPYwi/0=; b=O4bAHJlTMa0AYWIlnCXbNG82YFWFbpoh1quAK9mdVQYX3WZDC9bkxGkj9k1jdYK/T3rC65OlFOXzA1nWrdulbkjhcDDMb88eJj28iL/h30sToES5VTNmgVnND1dYzqcJppS4B0k1jF7PSdIfg9TvcZCi3YGzaf7p1ek7LNT6s5E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268783783376.6741451668473; Tue, 1 Sep 2026 06:19:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONB-00012G-Mg; Tue, 01 Sep 2026 09:17:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ON7-00010k-HE for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:54 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ON5-0007Ap-9r for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:53 -0400 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-c250f28f1cdso745937466b.0 for ; Tue, 01 Sep 2026 06:17:50 -0700 (PDT) Received: from lanath.. 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Device list changes between SSE-310 and SSE-300: New NPU0 Power Policy Unit and Configuration interface. All other devices are the same. Update comments in include/hw/arm/armsse.h to include SSE-300 and SSE-310 and their respective documentations. New SSE-310 IRQ mapping. sys_version and iidr values from the "SSE-310 with M85 and U55 FPGA" documentation for the mps3-an555. Refractor comments and code pertaining to both the SSE-300 and SSE-310. Arm Corstone SSE-310 TRM: https://developer.arm.com/documentation/102778/0000/ Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Reviewed-by: Peter Maydell Message-Id: <20260805153005.9989-3-simonxhy0404@gmail.com> Signed-off-by: Peter Maydell --- hw/arm/armsse.c | 208 +++++++++++++++++++++++++++++++- include/hw/arm/armsse-version.h | 2 + include/hw/arm/armsse.h | 9 +- 3 files changed, 211 insertions(+), 8 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 55fbc2c2901..8ea4caaef24 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -26,7 +26,7 @@ #include "hw/core/qdev-clock.h" =20 /* - * The SSE-300 puts some devices in different places to the + * The SSE-300 and SSE-310 put some devices in different places to the * SSE-200 (and original IoTKit). We use an array of these structs * to define how each variant lays out these devices. (Parts of the * SoC that are the same for all variants aren't handled via these @@ -118,6 +118,18 @@ static const Property sse300_properties[] =3D { DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), }; =20 +static const Property sse310_properties[] =3D { + DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), + DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 21), + DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), + DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), + DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), +}; + static const ARMSSEDeviceInfo iotkit_devices[] =3D { { .name =3D "timer0", @@ -480,6 +492,146 @@ static const ARMSSEDeviceInfo sse300_devices[] =3D { } }; =20 +static const ARMSSEDeviceInfo sse310_devices[] =3D { + { + .name =3D "timer0", + .type =3D TYPE_SSE_TIMER, + .index =3D 0, + .addr =3D 0x48000000, + .ppc =3D 0, + .ppc_port =3D 0, + .irq =3D 3, + }, + { + .name =3D "timer1", + .type =3D TYPE_SSE_TIMER, + .index =3D 1, + .addr =3D 0x48001000, + .ppc =3D 0, + .ppc_port =3D 1, + .irq =3D 4, + }, + { + .name =3D "timer2", + .type =3D TYPE_SSE_TIMER, + .index =3D 2, + .addr =3D 0x48002000, + .ppc =3D 0, + .ppc_port =3D 2, + .irq =3D 5, + }, + { + .name =3D "timer3", + .type =3D TYPE_SSE_TIMER, + .index =3D 3, + .addr =3D 0x48003000, + .ppc =3D 0, + .ppc_port =3D 5, + .irq =3D 27, + }, + { + .name =3D "s32ktimer", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 0, + .addr =3D 0x4802f000, + .ppc =3D 1, + .ppc_port =3D 0, + .irq =3D 2, + .slowclk =3D true, + }, + { + .name =3D "s32kwatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 0, + .addr =3D 0x5802e000, + .ppc =3D NO_PPC, + .irq =3D NMI_0, + .slowclk =3D true, + }, + { + .name =3D "watchdog", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 0, + .addr =3D 0x48040000, + .size =3D 0x2000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "armsse-sysinfo", + .type =3D TYPE_IOTKIT_SYSINFO, + .index =3D 0, + .addr =3D 0x48020000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "armsse-sysctl", + .type =3D TYPE_IOTKIT_SYSCTL, + .index =3D 0, + .addr =3D 0x58021000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "SYS_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 1, + .addr =3D 0x58022000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "CPU0CORE_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 2, + .addr =3D 0x58023000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "MGMT_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 3, + .addr =3D 0x58028000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "DEBUG_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 4, + .addr =3D 0x58029000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "NPU0_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 5, + .addr =3D 0x5802a000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "NPU0_CFG", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 6, + .addr =3D 0x40004000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D NULL, + } +}; + /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ static const bool sse200_irq_is_common[32] =3D { [0 ... 5] =3D true, @@ -507,6 +659,20 @@ static const bool sse300_irq_is_common[32] =3D { /* 30, 31: reserved */ }; =20 +static const bool sse310_irq_is_common[32] =3D { + [0 ... 5] =3D true, + /* 6-8: reserved */ + [9 ... 12] =3D true, + /* 13: reserved */ + [14] =3D true, + /* 15: reserved */ + [16] =3D true, + /* 17-26: reserved */ + [27] =3D true, + /* 28, 29: per-CPU CTI interrupts */ + /* 30, 31: reserved */ +}; + static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, @@ -574,6 +740,28 @@ static const ARMSSEInfo armsse_variants[] =3D { .devinfo =3D sse300_devices, .irq_is_common =3D sse300_irq_is_common, }, + { + .name =3D TYPE_SSE310, + .sse_version =3D ARMSSE_SSE310, + .cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m85"), + .sram_banks =3D 2, + .sram_bank_base =3D 0x21000000, + .num_cpus =3D 1, + .sys_version =3D 0x7e10043b, + .iidr =3D 0x74e0043b, + .cpuwait_rst =3D 0, + .has_mhus =3D false, + .has_cachectrl =3D false, + .has_cpusecctrl =3D true, + .has_cpuid =3D true, + .has_cpu_pwrctrl =3D true, + .has_sse_counter =3D true, + .has_tcms =3D true, + .props =3D sse310_properties, + .props_count =3D ARRAY_SIZE(sse310_properties), + .devinfo =3D sse310_devices, + .irq_is_common =3D sse310_irq_is_common, + } }; =20 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) @@ -604,6 +792,14 @@ static uint32_t armsse_sys_config_value(ARMSSE *s, con= st ARMSSEInfo *info) sys_config =3D deposit32(sys_config, 4, 5, s->sram_addr_width); sys_config =3D deposit32(sys_config, 16, 3, 3); /* CPU0 =3D Cortex= -M55 */ break; + case ARMSSE_SSE310: + sys_config =3D 0; + sys_config =3D deposit32(sys_config, 0, 4, info->sram_banks); + sys_config =3D deposit32(sys_config, 4, 5, s->sram_addr_width); + sys_config =3D deposit32(sys_config, 10, 1, 0); /* No CoreSight So= C */ + sys_config =3D deposit32(sys_config, 11, 2, 0); /* Basic level PI = */ + sys_config =3D deposit32(sys_config, 16, 3, 4); /* CPU0 =3D Cortex= -M85 */ + break; default: g_assert_not_reached(); } @@ -1205,7 +1401,7 @@ static void armsse_realize(DeviceState *dev, Error **= errp) qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI"= , 0)); =20 - /* The SSE-300 has a System Counter / System Timestamp Generator */ + /* The SSE-300/SSE-310 has a System Counter / System Timestamp Generat= or */ if (info->has_sse_counter) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->sse_counter); =20 @@ -1225,12 +1421,12 @@ static void armsse_realize(DeviceState *dev, Error = **errp) } =20 if (info->has_tcms) { - /* The SSE-300 has an ITCM at 0x0000_0000 and a DTCM at 0x2000_000= 0 */ - memory_region_init_ram(&s->itcm, NULL, "sse300-itcm", 512 * KiB, e= rrp); + /* SSE-300/SSE-310 have ITCM at 0x0000_0000 and DTCM at 0x2000_000= 0 */ + memory_region_init_ram(&s->itcm, NULL, "itcm", 512 * KiB, errp); if (*errp) { return; } - memory_region_init_ram(&s->dtcm, NULL, "sse300-dtcm", 512 * KiB, e= rrp); + memory_region_init_ram(&s->dtcm, NULL, "dtcm", 512 * KiB, errp); if (*errp) { return; } @@ -1461,7 +1657,7 @@ static void armsse_realize(DeviceState *dev, Error **= errp) * 0x50010000: L1 icache control registers * 0x50011000: CPUSECCTRL (CPU local security control registers) * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block - * The SSE-300 has an extra: + * The SSE-300 and SSE-310 have an extra: * 0x40012000 and 0x50012000: CPU_PWRCTRL register block */ if (info->has_cachectrl) { diff --git a/include/hw/arm/armsse-version.h b/include/hw/arm/armsse-versio= n.h index 60780fa9843..6b498cb3342 100644 --- a/include/hw/arm/armsse-version.h +++ b/include/hw/arm/armsse-version.h @@ -25,6 +25,7 @@ enum { ARMSSE_IOTKIT =3D 0, ARMSSE_SSE200 =3D 200, ARMSSE_SSE300 =3D 300, + ARMSSE_SSE310 =3D 310 }; =20 static inline bool armsse_version_valid(uint32_t sse_version) @@ -33,6 +34,7 @@ static inline bool armsse_version_valid(uint32_t sse_vers= ion) case ARMSSE_IOTKIT: case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: return true; default: return false; diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index bdf2d4db8e2..ab2ece07567 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -11,12 +11,16 @@ =20 /* * This is a model of the Arm "Subsystems for Embedded" family of - * hardware, which include the IoT Kit and the SSE-050, SSE-100 and - * SSE-200. Currently we model: + * hardware, which include the IoT Kit and the SSE-050, SSE-100, + * SSE-200, SSE-300, and SSE-310. Currently we model: * - the Arm IoT Kit which is documented in * https://developer.arm.com/documentation/ecm0601256/latest * - the SSE-200 which is documented in * https://developer.arm.com/documentation/101104/latest/ + * - the SSE-300 which is documented in + * https://support.arm.com/documentation/101773/latest/ + * - the SSE-310 which is documented in + * https://support.arm.com/documentation/102778/latest/ * * The IoTKit contains: * a Cortex-M33 @@ -127,6 +131,7 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, #define TYPE_IOTKIT "iotkit" #define TYPE_SSE200 "sse-200" #define TYPE_SSE300 "sse-300" +#define TYPE_SSE310 "sse-310" =20 /* We have an IRQ splitter and an OR gate input for each external PPC * and the 2 internal PPCs --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268802; cv=none; d=zohomail.com; s=zohoarc; b=ibjwYls3bsFVRMisNW++tf17I4txJVizh/34AtFt19okh1QY5Sukw4KjQjpc5qtA2yiJOvd4EmB8hUQrvw8Qs0qHvgIGnmhvVPn5AS6Vw3BsH2IacfzEYeetlDoF4ezjRzH5yXf4Yr9thZZ0LPl6xYZVjkaizEplp9j1oQdCX7o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268802; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=IglmI3ZIkNFV+A9WkCcAhwihdAJmoFH/GPtd9JGl38g=; b=HoeOVlldej6ByLngeuB33Qeq8DpMuUlFIS/th0iEV+y+bSTnR14Yp/IGSu0CpZiD/7dtDAZrgMYQr38lY0ZlJ71hFNxTmpI+OOl8rPMnCc4AGRs1sj3xaNc6uCqkv+FDUbKbfoECnpQawCvDDeKfYmgT8CPv7hDBvGA+0Cwlge8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268802658661.8561092626417; Tue, 1 Sep 2026 06:20:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONC-00012T-AS; Tue, 01 Sep 2026 09:17:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ON8-00010u-Gr for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:54 -0400 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ON6-0007Ay-9W for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:54 -0400 Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-c25344a8c6cso640517166b.0 for ; Tue, 01 Sep 2026 06:17:51 -0700 (PDT) Received: from lanath.. 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Add new SSE-310 PIDR and CLIDR values. Add new SSE-310 PPUINTSTAT register as RAZ with LOG_UMIMP on reads and RO on writes. Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Message-Id: <20260805153005.9989-4-simonxhy0404@gmail.com> Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/iotkit-sysctl.c | 86 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 79 insertions(+), 7 deletions(-) diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index dff89c677f7..90dde4d4dc9 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -51,6 +51,7 @@ REG32(CPUWAIT, 0x118) REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */ REG32(WICCTRL, 0x120) REG32(EWCTRL, 0x124) +REG32(PPUINTSTAT, 0x128) REG32(PWRCTRL, 0x1fc) FIELD(PWRCTRL, PPU_ACCESS_UNLOCK, 0, 1) FIELD(PWRCTRL, PPU_ACCESS_FILTER, 1, 1) @@ -87,6 +88,12 @@ static const int sse200_sysctl_id[] =3D { 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ }; =20 +static const int sse310_sysctl_id[] =3D { + 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ + 0x54, 0xb8, 0x4b, 0x00, /* PID0..PID3 */ + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ +}; + /* * Set the initial secure vector table offset address for the core. * This will take effect when the CPU next resets. @@ -118,6 +125,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->scsecctrl; break; default: @@ -130,6 +138,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->fclk_div; break; default: @@ -142,6 +151,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->sysclk_div; break; default: @@ -154,6 +164,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->clock_force; break; default: @@ -180,6 +191,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->initsvtor1; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: goto bad_offset; default: g_assert_not_reached(); @@ -192,6 +204,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->cpuwait; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: /* In SSE300 this is reserved (for INITSVTOR2) */ goto bad_offset; default: @@ -208,6 +221,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->nmi_enable; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: /* In SSE300 this is reserved (for INITSVTOR3) */ goto bad_offset; default: @@ -221,7 +235,8 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->wicctrl; break; case ARMSSE_SSE300: - /* In SSE300 this offset is CPUWAIT */ + case ARMSSE_SSE310: + /* In SSE300 and SSE310 this offset is CPUWAIT */ r =3D s->cpuwait; break; default: @@ -236,19 +251,36 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwad= dr offset, r =3D s->ewctrl; break; case ARMSSE_SSE300: - /* In SSE300 this offset is NMI_ENABLE */ + case ARMSSE_SSE310: + /* In SSE300 and SSE310 this offset is NMI_ENABLE */ r =3D s->nmi_enable; break; default: g_assert_not_reached(); } break; + case A_PPUINTSTAT: + switch (s->sse_version) { + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + case ARMSSE_SSE300: + goto bad_offset; + case ARMSSE_SSE310: + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PPUINTSTAT unimplemented\n"); + r =3D 0; + break; + default: + g_assert_not_reached(); + } + break; case A_PWRCTRL: switch (s->sse_version) { case ARMSSE_IOTKIT: case ARMSSE_SSE200: goto bad_offset; case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->pwrctrl; break; default: @@ -261,6 +293,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->pdcm_pd_sys_sense; break; default: @@ -273,6 +306,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_SSE200: goto bad_offset; case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->pdcm_pd_cpu0_sense; break; default: @@ -287,6 +321,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->pdcm_pd_sram0_sense; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: goto bad_offset; default: g_assert_not_reached(); @@ -300,6 +335,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->pdcm_pd_sram1_sense; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: goto bad_offset; default: g_assert_not_reached(); @@ -313,6 +349,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->pdcm_pd_sram2_sense; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->pdcm_pd_vmr0_sense; break; default: @@ -327,6 +364,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->pdcm_pd_sram3_sense; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->pdcm_pd_vmr1_sense; break; default: @@ -342,6 +380,9 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_SSE300: r =3D sse200_sysctl_id[(offset - A_PID4) / 4]; break; + case ARMSSE_SSE310: + r =3D sse310_sysctl_id[(offset - A_PID4) / 4]; + break; default: g_assert_not_reached(); } @@ -367,7 +408,8 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, =20 static void cpuwait_write(IoTKitSysCtl *s, uint32_t value) { - int num_cpus =3D (s->sse_version =3D=3D ARMSSE_SSE300) ? 1 : 2; + int num_cpus =3D (s->sse_version =3D=3D ARMSSE_SSE300 || + s->sse_version =3D=3D ARMSSE_SSE310) ? 1 : 2; int i; =20 for (i =3D 0; i < num_cpus; i++) { @@ -418,7 +460,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, case A_INITSVTOR0: switch (s->sse_version) { case ARMSSE_SSE300: - /* SSE300 has a LOCK bit which prevents further writes when se= t */ + case ARMSSE_SSE310: + /* SSE300, SSE310 have a LOCK bit which prevents further write= s */ if (s->initsvtor0 & R_INITSVTOR0_LOCK_MASK) { qemu_log_mask(LOG_GUEST_ERROR, "IoTKit INITSVTOR0 write when register locke= d\n"); @@ -443,6 +486,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, cpuwait_write(s, value); break; case ARMSSE_SSE300: + case ARMSSE_SSE310: /* In SSE300 this is reserved (for INITSVTOR2) */ goto bad_offset; default: @@ -457,7 +501,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->wicctrl =3D value; break; case ARMSSE_SSE300: - /* In SSE300 this offset is CPUWAIT */ + case ARMSSE_SSE310: + /* In SSE300 and SSE310 this offset is CPUWAIT */ cpuwait_write(s, value); break; default: @@ -485,6 +530,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemente= d\n"); s->scsecctrl =3D value; break; @@ -498,6 +544,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented= \n"); s->fclk_div =3D value; break; @@ -511,6 +558,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplement= ed\n"); s->sysclk_div =3D value; break; @@ -524,6 +572,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemen= ted\n"); s->clock_force =3D value; break; @@ -540,6 +589,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, set_init_vtor(1, s->initsvtor1); break; case ARMSSE_SSE300: + case ARMSSE_SSE310: goto bad_offset; default: g_assert_not_reached(); @@ -554,7 +604,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->ewctrl =3D value; break; case ARMSSE_SSE300: - /* In SSE300 this offset is NMI_ENABLE */ + case ARMSSE_SSE310: + /* In SSE300 and SSE310 this offset is NMI_ENABLE */ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplement= ed\n"); s->nmi_enable =3D value; break; @@ -562,12 +613,25 @@ static void iotkit_sysctl_write(void *opaque, hwaddr = offset, g_assert_not_reached(); } break; + case A_PPUINTSTAT: + switch (s->sse_version) { + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + case ARMSSE_SSE300: + goto bad_offset; + case ARMSSE_SSE310: + goto ro_offset; + default: + g_assert_not_reached(); + } + break; case A_PWRCTRL: switch (s->sse_version) { case ARMSSE_IOTKIT: case ARMSSE_SSE200: goto bad_offset; case ARMSSE_SSE300: + case ARMSSE_SSE310: if (!(s->pwrctrl & R_PWRCTRL_PPU_ACCESS_UNLOCK_MASK)) { qemu_log_mask(LOG_GUEST_ERROR, "IoTKit PWRCTRL write when register locked\n= "); @@ -585,6 +649,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n= "); s->pdcm_pd_sys_sense =3D value; @@ -599,6 +664,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, case ARMSSE_SSE200: goto bad_offset; case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl PDCM_PD_CPU0_SENSE unimplemented\= n"); s->pdcm_pd_cpu0_sense =3D value; @@ -617,6 +683,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->pdcm_pd_sram0_sense =3D value; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: goto bad_offset; default: g_assert_not_reached(); @@ -632,6 +699,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->pdcm_pd_sram1_sense =3D value; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: goto bad_offset; default: g_assert_not_reached(); @@ -647,6 +715,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->pdcm_pd_sram2_sense =3D value; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl PDCM_PD_VMR0_SENSE unimplemented\= n"); s->pdcm_pd_vmr0_sense =3D value; @@ -665,6 +734,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->pdcm_pd_sram3_sense =3D value; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl PDCM_PD_VMR1_SENSE unimplemented\= n"); s->pdcm_pd_vmr1_sense =3D value; @@ -683,6 +753,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->nmi_enable =3D value; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: /* In SSE300 this is reserved (for INITSVTOR3) */ goto bad_offset; default: @@ -769,7 +840,8 @@ static bool sse300_needed(void *opaque) { IoTKitSysCtl *s =3D IOTKIT_SYSCTL(opaque); =20 - return s->sse_version =3D=3D ARMSSE_SSE300; + return s->sse_version =3D=3D ARMSSE_SSE300 || + s->sse_version =3D=3D ARMSSE_SSE310; } =20 static const VMStateDescription iotkit_sysctl_sse300_vmstate =3D { --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268705; cv=none; d=zohomail.com; s=zohoarc; b=e9Lx0KsP/Ofux0B1QX0xvQUP8LAb+Ar0sO1sgjnUoN4xql+IilyWfhOBcQyR8IWlU/jKfK52pdYiSjsGHPacXutStF1s5v/55VLy7dGDRiHrjVQGcpYK4/zkA9JDkvI2VFIdZNSzFZW8sJ2G/qy9nsGSCBLRT5MIhy+Hp3KVazY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Reviewed-by: Peter Maydell Message-Id: <20260805153005.9989-6-simonxhy0404@gmail.com> Signed-off-by: Peter Maydell --- hw/misc/iotkit-secctl.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c index 93753c2ced2..9f6fb81088d 100644 --- a/hw/misc/iotkit-secctl.c +++ b/hw/misc/iotkit-secctl.c @@ -109,6 +109,18 @@ static const uint8_t iotkit_secctl_ns_sse300_idregs[] = =3D { 0x0d, 0xf0, 0x05, 0xb1, }; =20 +static const uint8_t iotkit_secctl_s_sse310_idregs[] =3D { + 0x04, 0x00, 0x00, 0x00, + 0x52, 0xb8, 0x3b, 0x00, + 0x0d, 0xf0, 0x05, 0xb1, +}; + +static const uint8_t iotkit_secctl_ns_sse310_idregs[] =3D { + 0x04, 0x00, 0x00, 0x00, + 0x53, 0xb8, 0x3b, 0x00, + 0x0d, 0xf0, 0x05, 0xb1, +}; + =20 /* The register sets for the various PPCs (AHB internal, APB internal, * AHB expansion, APB expansion) are all set up so that they are @@ -232,6 +244,9 @@ static MemTxResult iotkit_secctl_s_read(void *opaque, h= waddr addr, case ARMSSE_SSE300: r =3D iotkit_secctl_s_sse300_idregs[(offset - A_PID4) / 4]; break; + case ARMSSE_SSE310: + r =3D iotkit_secctl_s_sse310_idregs[(offset - A_PID4) / 4]; + break; default: r =3D iotkit_secctl_s_idregs[(offset - A_PID4) / 4]; break; @@ -499,6 +514,9 @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, = hwaddr addr, case ARMSSE_SSE300: r =3D iotkit_secctl_ns_sse300_idregs[(offset - A_PID4) / 4]; break; + case ARMSSE_SSE310: + r =3D iotkit_secctl_ns_sse310_idregs[(offset - A_PID4) / 4]; + break; default: r =3D iotkit_secctl_ns_idregs[(offset - A_PID4) / 4]; break; --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268849; cv=none; d=zohomail.com; s=zohoarc; b=LqZshTqZdeISHX91GtqCcaYeNMWZctIH1FnYyKt31o9PcXy+jDpON/dL2e85v31Dwi6Lljf0hurf01va0p9TVs71y+5B+MWZchQQvqDhBlarbcSUyM3ylgBhkRE4BxfANJxGOiL0Pu9KX666ujtXl4bjFIH/EzFwF4aBbDqTmS8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268849; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=HgyviTIOYw8VAyLJ2LdZVp/ABus10EL8EvtUFSkealY=; b=Sdix36DhGqTHXAf/O1mxMC1RjJkGc0zLlpAvrg4YA9NBiC7Ra34PFYsGQ0Jt2MP+By6gNelNaOVeHFPz+VAEcWEz1TLwUdFN/1doJCq3OYX9IxSCaynkjYul8+kycHmhOqjJp16Q0fC1+7u5aP9dX4hhDdcnutk17DkI4cyYYfQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268849618396.95391956619767; Tue, 1 Sep 2026 06:20:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONC-00012L-4P; Tue, 01 Sep 2026 09:17:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ONA-00011q-BF for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:56 -0400 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ON8-0007BS-9H for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:55 -0400 Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-69c108fee7fso6253703a12.3 for ; Tue, 01 Sep 2026 06:17:53 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268673; x=1788873473; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=HgyviTIOYw8VAyLJ2LdZVp/ABus10EL8EvtUFSkealY=; b=BKcsFJtFUrfJHL4YG0WnHofZwwiK86gj23adhx2vMZrNzlKZsT73tyVyIkFw+5Ex9j STm/faXdim2y3EXGilXlMoMHVM6Fj0gv0bIF2YsAsJRPpO0xhky7DPLbRtNh4uMf7W4j 2mjwgXg5eaRn3GDqNebX6NN9UPGTdoSd99tdPIK2/rWD+hLkUBbzmdwXL6KZq0shPayY CgJF2cLjGIwtl1jkmqTyNNp1s285LFpEOM6k7ijY5Id3Z6XGQDN8M7jb6EvpoADzN7Pw H3BifKRoYNmEq39srWatiweI2IRD/uTtPsWKR5TjPk0Vw3ZA1iXPKJ/gpdfu3kJ3UCfO mkkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268673; x=1788873473; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=HgyviTIOYw8VAyLJ2LdZVp/ABus10EL8EvtUFSkealY=; b=mnwxNzoSt/01DxL47VPv0N5uHfsg19YB+eT8LYfohHMZknGF/EdS9HLRlIFd0YNI6+ SFslXCZEvkI29Jo8hknOiHySaxKkTgIKCnBgcuz1bK3COwJogk7zJb1O02BRzAb1REqu kIwJRQsyxH6w13lJavFV/fUvHRoYtJwN39SCLVCcLcws0PxoNbNPl+dlLrBsy9FAVvUN eZhTrrHUyX8CqdahQ5PyiG05v3nrtPdd2AV/6wVZ88wLGXe9PhmakL6c19cSlY/KfiGR pOSRsSbguIb1Z6yk3qdnpk1PfZuZ5ElcysbgqWiZMsjn4DkSV+PqWnMIH3wBf+LZWims V91g== X-Gm-Message-State: AFuF++lm8e1jZN0rV11v8ZqU2lW7VX9LL4jEIgYRlPYj8kKAf2A2cqCY 1ZyxVMdM5xGixouguIHl01KXDBvwJ7r7Do4HwPgLHYIpXfYsXcTq03AUByDL7f0ntMU9nDbCMkX SRss7/5M= X-Gm-Gg: AYBFou17dLU6t1jAKVr3gH22fPOXc3WxLAFycWNEFoBczJTFk4+WKGNAVjtopDzk+dL QDcrkq9bBfKES7Gj08RC/oxG/m+5DtmX3W637kUJXWtT9iNTu2rZLzMvo8mIT4lFWRo32yErjpp MfanAplVxChccIiKdkblwuoaaUIGyp8XpJY0NO9TvsbbkaStWkPFGNtq5+fpFpFxErOPrj6eFgy m8+/h+yF/Opq4mrhIwXvEAGVkS0v12x4Hff/tp55gpsAk+sm7u+5ilwvCPoWEXxdqZcXqfiQ/2P 3wyas3VIJFD7FIah+hKi5JcmMOL2CJocbgMsnIrATNxxsw1fquAKGsgfv+0/+4oK+b6CzcKJevw sjXtBtDDIJspguk1k66+CfKPZmSnPyW5etp3fRMw9PCGwotPlEcsZEAfcTA7JizHd/rorCnZWWk 4p4HabAcUwB5snSAja4ZrgJZeWa/TknM4makAKe7rnesSP6zv7loawapkMLQ4r4pX35teRFfQhj hg55hdZVwwZ7rgscWGNKCao1InkhJDKYW7NSlhbVokRJX05qPomYKVZQ90gqJQTvbArcg== X-Received: by 2002:a17:906:c113:b0:c25:cb7a:12d6 with SMTP id a640c23a62f3a-c25cb7a1365mr10450966b.14.1788268672673; Tue, 01 Sep 2026 06:17:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/58] hw/misc/iotkit-secctl.c: use GNU C case ranges Date: Tue, 1 Sep 2026 14:16:52 +0100 Message-ID: <20260901131732.2263947-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268851865158500 Content-Type: text/plain; charset="utf-8" From: Simon Xu Replace case fall throughs with case ranges when register addresses are continous. Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Reviewed-by: Peter Maydell Message-Id: <20260805153005.9989-7-simonxhy0404@gmail.com> Signed-off-by: Peter Maydell --- hw/misc/iotkit-secctl.c | 112 ++++++---------------------------------- 1 file changed, 16 insertions(+), 96 deletions(-) diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c index 9f6fb81088d..2d06d6f80f5 100644 --- a/hw/misc/iotkit-secctl.c +++ b/hw/misc/iotkit-secctl.c @@ -187,36 +187,24 @@ static MemTxResult iotkit_secctl_s_read(void *opaque,= hwaddr addr, case A_BRGINTEN: r =3D s->brginten; break; - case A_AHBNSPPCEXP0: - case A_AHBNSPPCEXP1: - case A_AHBNSPPCEXP2: - case A_AHBNSPPCEXP3: + case A_AHBNSPPCEXP0 ... A_AHBNSPPCEXP3: r =3D s->ahbexp[offset_to_ppc_idx(offset)].ns; break; case A_APBNSPPC0: case A_APBNSPPC1: r =3D s->apb[offset_to_ppc_idx(offset)].ns; break; - case A_APBNSPPCEXP0: - case A_APBNSPPCEXP1: - case A_APBNSPPCEXP2: - case A_APBNSPPCEXP3: + case A_APBNSPPCEXP0 ... A_APBNSPPCEXP3: r =3D s->apbexp[offset_to_ppc_idx(offset)].ns; break; - case A_AHBSPPPCEXP0: - case A_AHBSPPPCEXP1: - case A_AHBSPPPCEXP2: - case A_AHBSPPPCEXP3: + case A_AHBSPPPCEXP0 ... A_AHBSPPPCEXP3: r =3D s->ahbexp[offset_to_ppc_idx(offset)].sp; break; case A_APBSPPPC0: case A_APBSPPPC1: r =3D s->apb[offset_to_ppc_idx(offset)].sp; break; - case A_APBSPPPCEXP0: - case A_APBSPPPCEXP1: - case A_APBSPPPCEXP2: - case A_APBSPPPCEXP3: + case A_APBSPPPCEXP0 ... A_APBSPPPCEXP3: r =3D s->apbexp[offset_to_ppc_idx(offset)].sp; break; case A_SECMSCINTSTAT: @@ -228,18 +216,7 @@ static MemTxResult iotkit_secctl_s_read(void *opaque, = hwaddr addr, case A_NSMSCEXP: r =3D s->nsmscexp; break; - case A_PID4: - case A_PID5: - case A_PID6: - case A_PID7: - case A_PID0: - case A_PID1: - case A_PID2: - case A_PID3: - case A_CID0: - case A_CID1: - case A_CID2: - case A_CID3: + case A_PID4 ... A_CID3: switch (s->sse_version) { case ARMSSE_SSE300: r =3D iotkit_secctl_s_sse300_idregs[(offset - A_PID4) / 4]; @@ -389,10 +366,7 @@ static MemTxResult iotkit_secctl_s_write(void *opaque,= hwaddr addr, case A_BRGINTEN: s->brginten =3D value & 0xffff0000; break; - case A_AHBNSPPCEXP0: - case A_AHBNSPPCEXP1: - case A_AHBNSPPCEXP2: - case A_AHBNSPPCEXP3: + case A_AHBNSPPCEXP0 ... A_AHBNSPPCEXP3: ppc =3D &s->ahbexp[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_ns_write(ppc, value); break; @@ -401,17 +375,11 @@ static MemTxResult iotkit_secctl_s_write(void *opaque= , hwaddr addr, ppc =3D &s->apb[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_ns_write(ppc, value); break; - case A_APBNSPPCEXP0: - case A_APBNSPPCEXP1: - case A_APBNSPPCEXP2: - case A_APBNSPPCEXP3: + case A_APBNSPPCEXP0 ... A_APBNSPPCEXP3: ppc =3D &s->apbexp[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_ns_write(ppc, value); break; - case A_AHBSPPPCEXP0: - case A_AHBSPPPCEXP1: - case A_AHBSPPPCEXP2: - case A_AHBSPPPCEXP3: + case A_AHBSPPPCEXP0 ... A_AHBSPPPCEXP3: ppc =3D &s->ahbexp[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_sp_write(ppc, value); break; @@ -420,10 +388,7 @@ static MemTxResult iotkit_secctl_s_write(void *opaque,= hwaddr addr, ppc =3D &s->apb[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_sp_write(ppc, value); break; - case A_APBSPPPCEXP0: - case A_APBSPPPCEXP1: - case A_APBSPPPCEXP2: - case A_APBSPPPCEXP3: + case A_APBSPPPCEXP0 ... A_APBSPPPCEXP3: ppc =3D &s->apbexp[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_sp_write(ppc, value); break; @@ -444,18 +409,7 @@ static MemTxResult iotkit_secctl_s_write(void *opaque,= hwaddr addr, case A_BRGINTSTAT: case A_AHBNSPPC0: case A_AHBSPPPC0: - case A_PID4: - case A_PID5: - case A_PID6: - case A_PID7: - case A_PID0: - case A_PID1: - case A_PID2: - case A_PID3: - case A_CID0: - case A_CID1: - case A_CID2: - case A_CID3: + case A_PID4 ... A_CID3: qemu_log_mask(LOG_GUEST_ERROR, "IoTKit SecCtl S block write: " "read-only offset 0x%x\n", offset); @@ -482,34 +436,17 @@ static MemTxResult iotkit_secctl_ns_read(void *opaque= , hwaddr addr, case A_AHBNSPPPC0: r =3D 0; break; - case A_AHBNSPPPCEXP0: - case A_AHBNSPPPCEXP1: - case A_AHBNSPPPCEXP2: - case A_AHBNSPPPCEXP3: + case A_AHBNSPPPCEXP0 ... A_AHBNSPPPCEXP3: r =3D s->ahbexp[offset_to_ppc_idx(offset)].nsp; break; case A_APBNSPPPC0: case A_APBNSPPPC1: r =3D s->apb[offset_to_ppc_idx(offset)].nsp; break; - case A_APBNSPPPCEXP0: - case A_APBNSPPPCEXP1: - case A_APBNSPPPCEXP2: - case A_APBNSPPPCEXP3: + case A_APBNSPPPCEXP0 ... A_APBNSPPPCEXP3: r =3D s->apbexp[offset_to_ppc_idx(offset)].nsp; break; - case A_PID4: - case A_PID5: - case A_PID6: - case A_PID7: - case A_PID0: - case A_PID1: - case A_PID2: - case A_PID3: - case A_CID0: - case A_CID1: - case A_CID2: - case A_CID3: + case A_PID4 ... A_CID3: switch (s->sse_version) { case ARMSSE_SSE300: r =3D iotkit_secctl_ns_sse300_idregs[(offset - A_PID4) / 4]; @@ -560,10 +497,7 @@ static MemTxResult iotkit_secctl_ns_write(void *opaque= , hwaddr addr, } =20 switch (offset) { - case A_AHBNSPPPCEXP0: - case A_AHBNSPPPCEXP1: - case A_AHBNSPPPCEXP2: - case A_AHBNSPPPCEXP3: + case A_AHBNSPPPCEXP0 ... A_AHBNSPPPCEXP3: ppc =3D &s->ahbexp[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_nsp_write(ppc, value); break; @@ -572,26 +506,12 @@ static MemTxResult iotkit_secctl_ns_write(void *opaqu= e, hwaddr addr, ppc =3D &s->apb[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_nsp_write(ppc, value); break; - case A_APBNSPPPCEXP0: - case A_APBNSPPPCEXP1: - case A_APBNSPPPCEXP2: - case A_APBNSPPPCEXP3: + case A_APBNSPPPCEXP0 ... A_APBNSPPPCEXP3: ppc =3D &s->apbexp[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_nsp_write(ppc, value); break; case A_AHBNSPPPC0: - case A_PID4: - case A_PID5: - case A_PID6: - case A_PID7: - case A_PID0: - case A_PID1: - case A_PID2: - case A_PID3: - case A_CID0: - case A_CID1: - case A_CID2: - case A_CID3: + case A_PID4 ... A_CID3: qemu_log_mask(LOG_GUEST_ERROR, "IoTKit SecCtl NS block write: " "read-only offset 0x%x\n", offset); --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268704; cv=none; d=zohomail.com; s=zohoarc; b=h4NrAAt1SBoVsL/AdEllzeXuwzeeMVsK36ECdLHPt9l1oGWXXEYWeJ8oL0ECCoz1zJMZ2cWWUexHPq4uq5BuVAR3CDn/fev563zckYK8khxVj+oi84SYFiTGPExE+iMpIq1lysRXO7+P4tiwkkVxZdh6+A2HuV4nA2UR6l4r2z0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268704; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Fwv5pyfNb8QZcfDc8HjkDq34cIxSmnuvmyZtBTjC3AA=; b=leTSZTsbJkfAUVIA9fV8cv0nqCGV/Q9v8sXj5fliNx6lbHNjmxyB6hoRgtLuBzsn6Cl/Iou7N/x8skzLymqcRXoJtiAmqewRb/R3Jxi4Ic1gSddvTRh6cvjct65Sd4m3uzuaLlGFEVDqh4NsWfb0vkXNyoYr3QkXCN8P1I4BVp0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268704937358.02016085164075; Tue, 1 Sep 2026 06:18:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONC-000130-QB; Tue, 01 Sep 2026 09:17:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ONA-00011v-H3 for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:56 -0400 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ON8-0007Bb-Tb for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:56 -0400 Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-c2531f453eeso727320266b.3 for ; Tue, 01 Sep 2026 06:17:54 -0700 (PDT) Received: from lanath.. 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Add sys_config2 register and always report 0 on read as we do not implement the NPU. Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Reviewed-by: Peter Maydell Message-Id: <20260805153005.9989-8-simonxhy0404@gmail.com> Signed-off-by: Peter Maydell --- hw/misc/iotkit-sysinfo.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c index 19f089e6ee9..f3d07f32474 100644 --- a/hw/misc/iotkit-sysinfo.c +++ b/hw/misc/iotkit-sysinfo.c @@ -31,6 +31,7 @@ REG32(SYS_VERSION, 0x0) REG32(SYS_CONFIG, 0x4) REG32(SYS_CONFIG1, 0x8) +REG32(SYS_CONFIG2, 0xc) REG32(IIDR, 0xfc8) REG32(PID4, 0xfd0) REG32(PID5, 0xfd4) @@ -58,6 +59,12 @@ static const int sysinfo_sse300_id[] =3D { 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ }; =20 +static const int sysinfo_sse310_id[] =3D { + 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ + 0x58, 0xb8, 0x2b, 0x00, /* PID0..PID3 */ + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ +}; + static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr offset, unsigned size) { @@ -68,13 +75,22 @@ static uint64_t iotkit_sysinfo_read(void *opaque, hwadd= r offset, case A_SYS_VERSION: r =3D s->sys_version; break; - case A_SYS_CONFIG: r =3D s->sys_config; break; case A_SYS_CONFIG1: switch (s->sse_version) { case ARMSSE_SSE300: + case ARMSSE_SSE310: + return 0; + break; + default: + goto bad_read; + } + break; + case A_SYS_CONFIG2: + switch (s->sse_version) { + case ARMSSE_SSE310: return 0; break; default: @@ -84,6 +100,7 @@ static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr= offset, case A_IIDR: switch (s->sse_version) { case ARMSSE_SSE300: + case ARMSSE_SSE310: return s->iidr; break; default: @@ -95,6 +112,9 @@ static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr= offset, case ARMSSE_SSE300: r =3D sysinfo_sse300_id[(offset - A_PID4) / 4]; break; + case ARMSSE_SSE310: + r =3D sysinfo_sse310_id[(offset - A_PID4) / 4]; + break; default: r =3D sysinfo_id[(offset - A_PID4) / 4]; break; --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268939; cv=none; d=zohomail.com; s=zohoarc; b=T0/1XdDYqVKsRRIXnwHhvCrJpUANc7xHW0aA+cMNm6UHuS0ZUdGlwpXEYwp82jRA1WAbbJfeomxo8lyA4PevXwmWTTp0KsbUPNkddIo7RmeNtcPdDyFcR7dYKaL8gkli1pKiq631rGrelQAIXuwt+ltNkwqEAxAy7SYA15tDGWs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268939; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=o1nePPo8i10ilYcV4CD8N6UBKH0v+1I5NmABoSXkSQs=; b=KDXlNdlZVpzWaE9P7q1OB4ySK6Qa686njIo4IafpNkztwAK0hNTEcCZ3uloY2qdm1XHeAzmYO5g6fY35paTHy626eN+YXgASC9/ztMxU1dEh8FqYRocJIF+XRuk0dLuKXr7a/2XLhY3bY3vPUvmgvkMNZsDes2eoFSGOcrdij/E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178826893900753.203419723718525; Tue, 1 Sep 2026 06:22:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1OND-00013N-LG; Tue, 01 Sep 2026 09:17:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ONC-00012K-0C for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:58 -0400 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ONA-0007Bw-3T for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:17:57 -0400 Received: by mail-ed1-x536.google.com with SMTP id 4fb4d7f45d1cf-69c108fee7fso6253758a12.3 for ; Tue, 01 Sep 2026 06:17:55 -0700 (PDT) Received: from lanath.. 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Implement register access as RW with LOG_UNIMP for writes. Add "has-gpioalt2" property to make each board configurable. Add gpioalt2 vmstate subsection for device state migration. Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Message-Id: <20260805153005.9989-10-simonxhy0404@gmail.com> Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 6 ++++++ hw/misc/mps2-fpgaio.c | 35 +++++++++++++++++++++++++++++++++++ include/hw/misc/mps2-fpgaio.h | 2 ++ 3 files changed, 43 insertions(+) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index d6d178642ba..79f53a0d09e 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -122,6 +122,7 @@ struct MPS2TZMachineClass { uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ bool fpgaio_has_dbgctrl; /* Does FPGAIO have DBGCTRL register? */ + bool fpgaio_has_gpioalt2; /* Does FPGAIO have GPIOALT2 register? */ int numirq; /* Number of external interrupts */ int uart_overflow_irq; /* number of the combined UART overflow IRQ */ uint32_t init_svtor; /* init-svtor setting for SSE */ @@ -494,6 +495,7 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mm= s, void *opaque, qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_swit= ches); qdev_prop_set_bit(DEVICE(fpgaio), "has-dbgctrl", mmc->fpgaio_has_dbgct= rl); + qdev_prop_set_bit(DEVICE(fpgaio), "has-gpioalt2", mmc->fpgaio_has_gpio= alt2); sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); } @@ -1350,6 +1352,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, = const void *data) mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_has_switches =3D false; mmc->fpgaio_has_dbgctrl =3D false; + mmc->fpgaio_has_gpioalt2 =3D false; mmc->numirq =3D 92; mmc->uart_overflow_irq =3D 47; mmc->init_svtor =3D 0x10000000; @@ -1384,6 +1387,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, = const void *data) mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_has_switches =3D false; mmc->fpgaio_has_dbgctrl =3D false; + mmc->fpgaio_has_gpioalt2 =3D false; mmc->numirq =3D 92; mmc->uart_overflow_irq =3D 47; mmc->init_svtor =3D 0x10000000; @@ -1418,6 +1422,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, = const void *data) mmc->fpgaio_num_leds =3D 10; mmc->fpgaio_has_switches =3D true; mmc->fpgaio_has_dbgctrl =3D false; + mmc->fpgaio_has_gpioalt2 =3D false; mmc->numirq =3D 95; mmc->uart_overflow_irq =3D 47; mmc->init_svtor =3D 0x10000000; @@ -1457,6 +1462,7 @@ static void mps3tz_an547_class_init(ObjectClass *oc, = const void *data) mmc->fpgaio_num_leds =3D 10; mmc->fpgaio_has_switches =3D true; mmc->fpgaio_has_dbgctrl =3D true; + mmc->fpgaio_has_gpioalt2 =3D false; mmc->numirq =3D 96; mmc->uart_overflow_irq =3D 48; mmc->init_svtor =3D 0x00000000; diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index da78cb60701..208f9fd60fb 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -31,6 +31,7 @@ REG32(LED0, 0) REG32(DBGCTRL, 4) REG32(BUTTON, 8) +REG32(GPIOALT2, 0xc) REG32(CLK1HZ, 0x10) REG32(CLK100HZ, 0x14) REG32(COUNTER, 0x18) @@ -142,6 +143,9 @@ static uint64_t mps2_fpgaio_read(void *opaque, hwaddr o= ffset, unsigned size) */ r =3D 0; break; + case A_GPIOALT2: + r =3D s->gpioalt2; + break; case A_PRESCALE: r =3D s->prescale; break; @@ -210,6 +214,14 @@ static void mps2_fpgaio_write(void *opaque, hwaddr off= set, uint64_t value, "MPS2 FPGAIO: DBGCTRL unimplemented\n"); s->dbgctrl =3D value; break; + case A_GPIOALT2: + if (!s->has_gpioalt2) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, + "MPS2 FPGAIO: GPIOALT2 unimplemented\n"); + s->gpioalt2 =3D value; + break; case A_PRESCALE: resync_counter(s); s->prescale =3D value; @@ -301,6 +313,24 @@ static void mps2_fpgaio_realize(DeviceState *dev, Erro= r **errp) } } =20 +static bool needed_gpioalt2(void *opaque) +{ + MPS2FPGAIO *s =3D MPS2_FPGAIO(opaque); + + return s->has_gpioalt2; +} + +static const VMStateDescription mps2_fpgaio_gpioalt2_vmstate =3D { + .name =3D "mps2-fpgaio/gpioalt2", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D needed_gpioalt2, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(gpioalt2, MPS2FPGAIO), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription mps2_fpgaio_vmstate =3D { .name =3D "mps2-fpgaio", .version_id =3D 3, @@ -317,6 +347,10 @@ static const VMStateDescription mps2_fpgaio_vmstate = =3D { VMSTATE_INT64(pscntr_sync_ticks, MPS2FPGAIO), VMSTATE_END_OF_LIST() }, + .subsections =3D (const VMStateDescription * const []) { + &mps2_fpgaio_gpioalt2_vmstate, + NULL + } }; =20 static const Property mps2_fpgaio_properties[] =3D { @@ -326,6 +360,7 @@ static const Property mps2_fpgaio_properties[] =3D { DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), DEFINE_PROP_BOOL("has-switches", MPS2FPGAIO, has_switches, false), DEFINE_PROP_BOOL("has-dbgctrl", MPS2FPGAIO, has_dbgctrl, false), + DEFINE_PROP_BOOL("has-gpioalt2", MPS2FPGAIO, has_gpioalt2, false), }; =20 static void mps2_fpgaio_class_init(ObjectClass *klass, const void *data) diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index edd9f231212..75126866169 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -40,11 +40,13 @@ struct MPS2FPGAIO { uint32_t num_leds; bool has_switches; bool has_dbgctrl; + bool has_gpioalt2; =20 uint32_t led0; uint32_t prescale; uint32_t misc; uint32_t dbgctrl; + uint32_t gpioalt2; =20 /* QEMU_CLOCK_VIRTUAL time at which counter and pscntr were last synce= d */ int64_t pscntr_sync_ticks; --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Add UnimplementedDeivceState for timing adapters and qspi controllers in MPS2TZMachineState. Changes in AN555: Timing adapters in APB PPC EX0 instead of MPC. Additional QSPI controllers in AHB PPC EX0. Additional AHB PPC EX1 with DMA. Create standalone unimplemented devices for MPC instead of timing adapters. Set fpgaio_has_gpioalt2 to true. Include documentation for SSE-310 and mps3-an555. Arm mps3-an555 TRM: https://developer.arm.com/documentation/107642/latest/ As our M85 model doesn't yet have PACBTI, note this omission in the documentation of where we deviate from the real AN555. Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Reviewed-by: Peter Maydell Message-Id: <20260805153005.9989-9-simonxhy0404@gmail.com> [PMM: added doc note about PACBTI] Signed-off-by: Peter Maydell --- docs/system/arm/mps2.rst | 7 +- hw/arm/mps2-tz.c | 156 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 157 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index a305935cc49..24f6fe4fdbf 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -1,5 +1,5 @@ -Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, = ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an53= 6``, ``mps3-an547``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, = ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an53= 6``, ``mps3-an547``, ``mps3-an555``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 These board models use Arm M-profile or R-profile CPUs. =20 @@ -31,6 +31,8 @@ FPGA images using M-profile CPUs: Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524 ``mps3-an547`` Cortex-M55 on an MPS3, as documented in Arm Application Note AN547 +``mps3-an555`` + Cortex-M85 on an MPS3, as documented in Arm Application Note AN555 =20 FPGA images using R-profile CPUs: =20 @@ -66,6 +68,7 @@ Differences between QEMU and real hardware: held in halt via the initial SCC CFG_REG0 register setting. You can create the second CPU with ``-smp 2``; both CPUs will then start execution immediately on startup. +- AN555 provides a Cortex-M85 without the PACBTI extension =20 Note that for the AN536 the first UART is accessible only by CPU0, and the second UART is accessible only by CPU1. The diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 79f53a0d09e..41dfb185353 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -1,5 +1,5 @@ /* - * ARM V2M MPS2 board emulation, trustzone aware FPGA images + * Arm V2M MPS2 and MPS3 board emulation, trustzone aware FPGA images * * Copyright (c) 2017 Linaro Limited * Written by Peter Maydell @@ -18,13 +18,17 @@ * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN= 547 + * "mps3-an555" -- Single Cortex-M85 as documented in Application Note AN= 555 * * Links to the TRM for the board itself and to the various Application * Notes which document the FPGA images can be found here: * https://developer.arm.com/products/system-design/development-boards/fpg= a-prototyping-boards/mps2 * - * Board TRM: + * MPS2 and MPS2+ Board TRM: * https://developer.arm.com/documentation/100112/latest/ + * MPS3 Board TRM: + * https://developer.arm.com/documentation/100765/latest/ + * * Application Note AN505: * https://developer.arm.com/documentation/dai0505/latest/ * Application Note AN521: @@ -33,6 +37,8 @@ * https://developer.arm.com/documentation/dai0524/latest/ * Application Note AN547: * https://developer.arm.com/documentation/dai0547/latest/ + * Application Note AN555: + * https://developer.arm.com/documentation/107642/latest/ * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Gu= ide * (ARM ECM0601256) for the details of some of the device layout: @@ -42,6 +48,8 @@ * https://developer.arm.com/documentation/101104/latest/ * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM: * https://developer.arm.com/documentation/101773/latest/ + * and the AN555 uses the SSE-310, whose layout is in the SSE-310 TRM: + * https://developer.arm.com/documentation/102778/latest/ */ =20 #include "qemu/osdep.h" @@ -85,6 +93,7 @@ typedef enum MPS2TZFPGAType { FPGA_AN521, FPGA_AN524, FPGA_AN547, + FPGA_AN555, } MPS2TZFPGAType; =20 /* @@ -154,6 +163,8 @@ struct MPS2TZMachineState { UnimplementedDeviceState gfx; UnimplementedDeviceState cldc; UnimplementedDeviceState usb; + UnimplementedDeviceState ta[3]; /* timing adatper */ + UnimplementedDeviceState qspi_controller[3]; PL031State rtc; PL080State dma[4]; TZMSC msc[4]; @@ -174,6 +185,7 @@ struct MPS2TZMachineState { #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") #define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547") +#define TYPE_MPS3TZ_AN555_MACHINE MACHINE_TYPE_NAME("mps3-an555") =20 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) =20 @@ -208,6 +220,15 @@ static const uint32_t an524_oscclk[] =3D { 23750000, }; =20 +static const uint32_t an555_oscclk[] =3D { + 24000000, + 25000000, + 30000000, + 50000000, + 24576000, + 23750000, +}; + static const RAMInfo an505_raminfo[] =3D { { .name =3D "ssram-0", .base =3D 0x00000000, @@ -1030,7 +1051,6 @@ static void mps2tz_common_init(MachineState *machine) { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, {= 38, 39, 45 } }, { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, {= 40, 41, 46 } }, { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, {= 124, 125, 126 } }, - { /* port 9 reserved */ }, { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, @@ -1097,7 +1117,6 @@ static void mps2tz_common_init(MachineState *machine) { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, {= 39, 40, 46 } }, { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, {= 41, 42, 47 } }, { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, {= 125, 126, 127 } }, - { /* port 9 reserved */ }, { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, @@ -1126,6 +1145,81 @@ static void mps2tz_common_init(MachineState *machine) }, }; =20 + const PPCInfo an555_ppcs[] =3D { { + .name =3D "apb_ppcexp0", + .ports =3D { + { "sram-timing-adapter", make_unimp_dev, &mms->ta[0], 0x41= 700000, 0x1000 }, + { "qspi-timing-adapter", make_unimp_dev, &mms->ta[1], 0x41= 701000, 0x1000 }, + { "ddr4-timing-adapter", make_unimp_dev, &mms->ta[2], 0x41= 702000, 0x1000 }, + }, + }, { + .name =3D "apb_ppcexp1", + .ports =3D { + { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000, {}, + { .i2c_internal =3D true /* touchscreen */ } }, + { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000, {}, + { .i2c_internal =3D true /* audio conf */ } }, + { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53= } }, + { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54= } }, + { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55= } }, + { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000, {}, + { .i2c_internal =3D false /* shield 0 */ } }, + { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000, {}, + { .i2c_internal =3D false /* shield 1 */ } }, + { /* port 7 reserved */ }, + { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000, {}, + { .i2c_internal =3D true /* DDR4 EEPROM */ } }, + }, + }, { + .name =3D "apb_ppcexp2", + .ports =3D { + { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 }, + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000= , 0x1000 }, + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 = }, + { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, {= 33, 34, 43 } }, + { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, {= 35, 36, 44 } }, + { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, {= 37, 38, 45 } }, + { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, {= 39, 40, 46 } }, + { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, {= 41, 42, 47 } }, + { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, {= 125, 126, 127 } }, + { /* port 9 reserved */ }, + { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, + { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, + }, + }, { + .name =3D "ahb_ppcexp0", + .ports =3D { + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x10= 00 }, + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x10= 00 }, + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x10= 00 }, + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x10= 00 }, + { /* port 4 USER AHB interface 0 */ }, + { /* port 5 USER AHB interface 1 */ }, + { /* port 6 USER AHB interface 2 */ }, + { /* port 7 USER AHB interface 3 */ }, + { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 4= 9 } }, + { /* port 9 reserved */ }, + { /* port 10 reserved */ }, + { /* port 11 reserved */ }, + { /* port 12 reserved */ }, + { "qspi-controller0", make_unimp_dev, &mms->qspi_controlle= r[0], + 0x41800000, 0x1000 }, + { "qspi-controller1", make_unimp_dev, &mms->qspi_controlle= r[1], + 0x41801000, 0x1000 }, + { "qspi-controller2", make_unimp_dev, &mms->qspi_controlle= r[2], + 0x41802000, 0x1000 }, + }, + }, { + .name =3D "ahb_ppcexp1", + .ports =3D { + { "dma0", make_dma, &mms->dma[0], 0x41200000, 0x1000, { 59= , 57, 58 } }, + { "dma1", make_dma, &mms->dma[1], 0x41201000, 0x1000, { 62= , 60, 61 } }, + { "dma2", make_dma, &mms->dma[2], 0x41202000, 0x1000, { 65= , 63, 64 } }, + { "dma3", make_dma, &mms->dma[3], 0x41203000, 0x1000, { 68= , 66, 67 } }, + }, + }, + }; + switch (mmc->fpga_type) { case FPGA_AN505: case FPGA_AN521: @@ -1140,6 +1234,10 @@ static void mps2tz_common_init(MachineState *machine) ppcs =3D an547_ppcs; num_ppcs =3D ARRAY_SIZE(an547_ppcs); break; + case FPGA_AN555: + ppcs =3D an555_ppcs; + num_ppcs =3D ARRAY_SIZE(an555_ppcs); + break; default: g_assert_not_reached(); } @@ -1223,6 +1321,12 @@ static void mps2tz_common_init(MachineState *machine) create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x= 1000); } =20 + if (mmc->fpga_type =3D=3D FPGA_AN555) { + create_unimplemented_device("SRAM MPC", 0x57000000, 0x1000); + create_unimplemented_device("QSPI MPC", 0x57001000, 0x1000); + create_unimplemented_device("DDR4 MPC", 0x57002000, 0x1000); + } + create_non_mpc_ram(mms); =20 if (mmc->fpga_type =3D=3D FPGA_AN524) { @@ -1474,6 +1578,42 @@ static void mps3tz_an547_class_init(ObjectClass *oc,= const void *data) mps2tz_set_default_ram_info(mmc); } =20 +static void mps3tz_an555_class_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m85"), + NULL + }; + + mc->desc =3D "ARM MPS3 with AN555 FPGA image for Cortex-M85"; + mc->default_cpus =3D 1; + mc->min_cpus =3D mc->default_cpus; + mc->max_cpus =3D mc->default_cpus; + mmc->fpga_type =3D FPGA_AN555; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m85"); + mc->valid_cpu_types =3D valid_cpu_types; + mmc->scc_id =3D 0x41055551; + mmc->sysclk_frq =3D 25 * 1000 * 1000; /* 25MHz */ + mmc->apb_periph_frq =3D 25 * 1000 * 1000; /* 25MHz */ + mmc->oscclk =3D an555_oscclk; + mmc->len_oscclk =3D ARRAY_SIZE(an555_oscclk); + mmc->fpgaio_num_leds =3D 10; + mmc->fpgaio_has_switches =3D true; + mmc->fpgaio_has_dbgctrl =3D true; + mmc->fpgaio_has_gpioalt2 =3D true; + mmc->numirq =3D 96; + mmc->uart_overflow_irq =3D 48; + mmc->init_svtor =3D 0x00000000; + mmc->cpu0_mpu_s =3D mmc->cpu0_mpu_ns =3D 8; + mmc->sram_addr_width =3D 21; + mmc->raminfo =3D an547_raminfo; /* same as AN547*/ + mmc->armsse_type =3D TYPE_SSE310; + mmc->boot_ram_size =3D 512 * KiB; + mps2tz_set_default_ram_info(mmc); +} + static const TypeInfo mps2tz_info =3D { .name =3D TYPE_MPS2TZ_MACHINE, .parent =3D TYPE_MACHINE, @@ -1515,6 +1655,13 @@ static const TypeInfo mps3tz_an547_info =3D { .interfaces =3D arm_machine_interfaces, }; =20 +static const TypeInfo mps3tz_an555_info =3D { + .name =3D TYPE_MPS3TZ_AN555_MACHINE, + .parent =3D TYPE_MPS2TZ_MACHINE, + .class_init =3D mps3tz_an555_class_init, + .interfaces =3D arm_machine_interfaces, +}; + static void mps2tz_machine_init(void) { type_register_static(&mps2tz_info); @@ -1522,6 +1669,7 @@ static void mps2tz_machine_init(void) type_register_static(&mps2tz_an521_info); type_register_static(&mps3tz_an524_info); type_register_static(&mps3tz_an547_info); + type_register_static(&mps3tz_an555_info); } =20 type_init(mps2tz_machine_init); --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 01 Sep 2026 06:17:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/58] target/arm: Move -cpu max stuff out of cpu32.c Date: Tue, 1 Sep 2026 14:16:56 +0100 Message-ID: <20260901131732.2263947-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268787604158500 From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20260827041557.775080-2-richard.henderson@linaro.org Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/cpu-max-v8.c | 117 ++++++++++++++++++++++++++++++++++++ target/arm/tcg/cpu32.c | 111 ---------------------------------- target/arm/tcg/meson.build | 1 + 3 files changed, 118 insertions(+), 111 deletions(-) create mode 100644 target/arm/tcg/cpu-max-v8.c diff --git a/target/arm/tcg/cpu-max-v8.c b/target/arm/tcg/cpu-max-v8.c new file mode 100644 index 00000000000..5c0ba28edf8 --- /dev/null +++ b/target/arm/tcg/cpu-max-v8.c @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + + +/* Share AArch32 -cpu max features with AArch64. */ +void aa32_max_features(ARMCPU *cpu) +{ + uint32_t t; + ARMISARegisters *isar =3D &cpu->isar; + + /* Add additional features supported by QEMU */ + t =3D GET_IDREG(isar, ID_ISAR5); + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ + SET_IDREG(isar, ID_ISAR5, t); + + t =3D GET_IDREG(isar, ID_ISAR6); + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ + SET_IDREG(isar, ID_ISAR6, t); + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ + + t =3D GET_IDREG(isar, ID_MMFR4); + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ + t =3D FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */ + SET_IDREG(isar, ID_MMFR4, t); + + FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ + + t =3D GET_IDREG(isar, ID_PFR0); + t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ + SET_IDREG(isar, ID_PFR0, t); + + t =3D GET_IDREG(isar, ID_PFR2); + t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ + SET_IDREG(isar, ID_PFR2, t); + + t =3D GET_IDREG(isar, ID_DFR0); + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ + SET_IDREG(isar, ID_DFR0, t); + + /* Debug ID registers. */ + + /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ + t =3D 0x00008000; + t =3D FIELD_DP32(t, DBGDIDR, SE_IMP, 1); + t =3D FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); + t =3D FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ + t =3D FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); + t =3D FIELD_DP32(t, DBGDIDR, BRPS, 5); + t =3D FIELD_DP32(t, DBGDIDR, WRPS, 3); + cpu->isar.dbgdidr =3D t; + + t =3D 0; + t =3D FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); + t =3D FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); + t =3D FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); + t =3D FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); + t =3D FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); + t =3D FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); + t =3D FIELD_DP32(t, DBGDEVID, AUXREGS, 0); + t =3D FIELD_DP32(t, DBGDEVID, CIDMASK, 0); + cpu->isar.dbgdevid =3D t; + + /* Bits[31:4] are RES0. */ + t =3D 0; + t =3D FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); + cpu->isar.dbgdevid1 =3D t; + + FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ +} + +void aarch32_max_tcg_init(ARMCPU *cpu) +{ + aarch64_aa32_a57_init(cpu, false); + aa32_max_features(cpu); +#ifdef CONFIG_USER_ONLY + /* + * Break with true ARMv8 and add back old-style VFP short-vector + * support. Only do this for user-mode, where -cpu max is the default, + * so that older v6 and v7 programs are more likely to work without + * adjustment. + */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); +#endif +} diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 241c1f5e966..94a705e8066 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -758,114 +758,3 @@ static void arm_tcg_cpu_register_types(void) type_init(arm_tcg_cpu_register_types) =20 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ - -/* Share AArch32 -cpu max features with AArch64. */ -void aa32_max_features(ARMCPU *cpu) -{ - uint32_t t; - ARMISARegisters *isar =3D &cpu->isar; - - /* Add additional features supported by QEMU */ - t =3D GET_IDREG(isar, ID_ISAR5); - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ - SET_IDREG(isar, ID_ISAR5, t); - - t =3D GET_IDREG(isar, ID_ISAR6); - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ - SET_IDREG(isar, ID_ISAR6, t); - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ - - t =3D GET_IDREG(isar, ID_MMFR4); - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ - t =3D FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */ - SET_IDREG(isar, ID_MMFR4, t); - - FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ - - t =3D GET_IDREG(isar, ID_PFR0); - t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ - SET_IDREG(isar, ID_PFR0, t); - - t =3D GET_IDREG(isar, ID_PFR2); - t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ - SET_IDREG(isar, ID_PFR2, t); - - t =3D GET_IDREG(isar, ID_DFR0); - t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ - SET_IDREG(isar, ID_DFR0, t); - - /* Debug ID registers. */ - - /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ - t =3D 0x00008000; - t =3D FIELD_DP32(t, DBGDIDR, SE_IMP, 1); - t =3D FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); - t =3D FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); - t =3D FIELD_DP32(t, DBGDIDR, BRPS, 5); - t =3D FIELD_DP32(t, DBGDIDR, WRPS, 3); - cpu->isar.dbgdidr =3D t; - - t =3D 0; - t =3D FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); - t =3D FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); - t =3D FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); - t =3D FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); - t =3D FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); - t =3D FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); - t =3D FIELD_DP32(t, DBGDEVID, AUXREGS, 0); - t =3D FIELD_DP32(t, DBGDEVID, CIDMASK, 0); - cpu->isar.dbgdevid =3D t; - - /* Bits[31:4] are RES0. */ - t =3D 0; - t =3D FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); - cpu->isar.dbgdevid1 =3D t; - - FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ -} - -void aarch32_max_tcg_init(ARMCPU *cpu) -{ - aarch64_aa32_a57_init(cpu, false); - aa32_max_features(cpu); -#ifdef CONFIG_USER_ONLY - /* - * Break with true ARMv8 and add back old-style VFP short-vector - * support. Only do this for user-mode, where -cpu max is the default, - * so that older v6 and v7 programs are more likely to work without - * adjustment. - */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); -#endif -} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index cbfac0036e7..35e70b004d9 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -65,6 +65,7 @@ arm_common_user_system_ss.add( translate32_d, vfp_d, files( + 'cpu-max-v8.c', 'debug.c', 'gengvec.c', 'hflags.c', --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268704; cv=none; d=zohomail.com; s=zohoarc; b=T2LxTZdIWEY9wesb8xbdDNZIIkfcooeTqi+nwgo6wFvk9KqFfFdHughVM3PLeYZ769d1w/oZvhr74Obgcos0odUp8XfS4xqjNzLDmAImbwbbmXe+SIgKnTabsX9cn/a/YAmPLi8qMnlOIwSo5jnxMekvWduMDwvYxg1jDQKJtVg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268704; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=OCnS1TSwyGi8oae/WH470zGgu7DaGQ2CJrcgjTVsuBE=; b=aVIN0cfe56sMdooSfJZSft+iSyUslc8aS/cGmjsae2OpXmUc1hxGyVpnyp6da3ln4SgW9r1HKjmyyC8snjtPY6VxVTA8rvkKinhxTzgEE0FGp/4zktvD8psUh6PBDl7sF/4LjGpYwhnrDh3rEqSNxV7o+ogqkN5t3No09F8WA5s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268704937529.4890449428808; Tue, 1 Sep 2026 06:18:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONG-00015r-5F; Tue, 01 Sep 2026 09:18:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ONE-00014z-NQ for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:00 -0400 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1OND-0007Cc-2q for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:00 -0400 Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-c252c7270faso793189866b.3 for ; Tue, 01 Sep 2026 06:17:58 -0700 (PDT) Received: from lanath.. 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Signed-off-by: Richard Henderson Message-id: 20260827041557.775080-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/tcg/cpu32.c | 5 ----- target/arm/tcg/meson.build | 10 +++++----- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 94a705e8066..f292a269bf2 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -19,9 +19,6 @@ #include "cpregs.h" =20 =20 -/* CPU models. These are not needed for the AArch64 linux-user build. */ -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - static void arm926_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -756,5 +753,3 @@ static void arm_tcg_cpu_register_types(void) } =20 type_init(arm_tcg_cpu_register_types) - -#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 35e70b004d9..a3e9d55e853 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -30,10 +30,6 @@ translate32_d =3D [ arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64) arm_stubs_ss.add(files('stubs32.c')) =20 -arm_ss.add(files( - 'cpu32.c', -)) - arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'gengvec64.c', 'translate-a64.c', @@ -49,7 +45,10 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( )) =20 arm_common_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c= ')) -arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) +arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( + 'cpu-v7m.c', + 'cpu32.c', +)) =20 arm_common_ss.add(zlib) arm_common_ss.add(files( @@ -86,6 +85,7 @@ arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_= true: files( )) =20 arm_common_system_ss.add(files( + 'cpu32.c', 'cpregs-at.c', 'gicv5-cpuif.c', 'psci.c', --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268991; cv=none; d=zohomail.com; s=zohoarc; b=HIq2VRxll2Y6Q8Kpw0c06YbRO9wc3MZVZgodDIpqADcCm5s5rV85f2g4S4Fqy//h1xxA/FzgdiBrYUe1QbaQQfGgXXZSzrV6qQHer//vc4JUepfzumzdYAG70c5CSCx902O4+Th67wEi0KQdCcmTUEiA633sFCMKj87yCZgh5LE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268991; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=kLokBAeBm6DcfQnHRcIg7xh0aKwQc9QxK3xRnb9ycHE=; b=AFJXjJG9MEK5s2TkzUWDB1M/196kNkFfMVcMBPBaJuMLr2eEDPBgnIhFeWeLYNWAuVhsKgwcyPBAKgao5B0yLXd7GLdCUyQjeNc4Q0bgmxK7M8MgN7amBRBkotYCyfzwrKki/TYZpGBgACwCCabMIzgl5nr5LXV/rXWiMzP5EP4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268991273618.5330227291709; Tue, 1 Sep 2026 06:23:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONI-00016Z-9K; Tue, 01 Sep 2026 09:18:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ONF-00015W-Qk for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:01 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ONE-0007Cn-99 for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:01 -0400 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-c259e5c22ffso368088966b.1 for ; Tue, 01 Sep 2026 06:17:59 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268679; x=1788873479; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=kLokBAeBm6DcfQnHRcIg7xh0aKwQc9QxK3xRnb9ycHE=; b=QJGPWsXDd7bBpcN6wDAgxthP+l8KfWQfbOlY4qGyIRPp+ZB3mBeoey9I39f/3zBWzb RNr9LOPj3IJ1plhhKPZNSznEwKZ8Pb1OVXAZDHhKN1KxFeUJ43pvtt8nisgmEEanYYt3 90TuefaNUTgA8Eldr2sMVkLr3VqKdesM6UfDL2WCsAYSjTtw7kVzHBodo+SvVNYCEEzh Mx3vsZidkl50zmyt2R+AzaByD286x45WfQaQN6QMip2CI/10gULsp5NWBiBfVffz5cAK N/EPux0foG6t4dt5QJGmr6XGGIJmwKuu50iAZ8mBCrudpQanNQ6vlBensubPJJboWrIv RXjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268679; x=1788873479; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=kLokBAeBm6DcfQnHRcIg7xh0aKwQc9QxK3xRnb9ycHE=; b=P802Ft5XKgGtYwv7dMPa1b0m06fVd8GvVUKwuBdQ7Lp1JY93KkltN3oMxBAyfm/DvA Jo3AWgH7d+xmTh1nYLVfsXtPv5FVMwfiJVJvsqWbzpr+J3cRTkwDcb+TYA2x7YofSEQV CEhzoA02ma0pz464GFbsIKkuQU0Q+hO3l091GVBN4bue9gfb9s/29GL+WI38WbvyqPww U2TEy8dO4LUaRNjusgp7Sj1o4iSi2YcnGqsPUrohBGtIrIDOYxPiJD7zTKftdOERqEYk jy/dAacd96py4RAk9SZ9s8prpSGl/fnnY68NTxK4DK8+Z3W/Ulng4BsMJNYVbJ65jo12 kI4w== X-Gm-Message-State: AFuF++nra7+Cieyot8do8yqHpLm70yiVJbbq8TTdjngJA+PtMuRVs0vo QY0u/5QB4/VT1lprn0W17l8CUGDY0sEZR9OdbeFXLfgXm+ZGCulSxlUCfEyT9i6JtyUYTHxOglL UCukCx0g= X-Gm-Gg: AR+sD12P4K58u9dfhL5dow53jyBVTRQmaTGwJ9mcRCdf7Mp6v9jQlW0g9ZTqPzl6lBJ zWTcf5fmfDaRkjrw3Vo8o/cRkMt2fLalAyZERiIwliTh+38RdajqmoVlCdidiJSlftEAwripVmz IL/fMLCclRbKOzgs6kB2nDFaJHyMfB+j7bMFsyIYas7+dOY9p5AirJqXeBY9bfkghSCUqWmDps9 +IFpQ1gC2fqE6WLTblUdEX+T8unQlF8/dvEOn2yZn0z4ixNSNQxqfZiXyTMir4ZNlRpxfTZYbGt aWSsJnhv7H2RuSCxm2vWvNzGThAI54qx0A+GwuPTKV/d7ZstId4ofF8kCwYY+QjtgDiRc80nq0P 6Ic+pZMD8rwQ75HLVYWJxZV67RD7n8o0Q8ruHzBzDRPq01grhRLt0JC5ZnG4a7g9aanF+V1Efz+ zkA3jAEUs4QMyB0MJc88bjjphLVDSIv5lCHqHYXpwErfi+GX4T/Vxe7N+mkLhRmzQgY69v7yaRT WMLLw99Q8KfzGolSVNPsdjJGgGkBYxILadns/yRlu+aVDMHbTFgdfwUyIv8FOowk2z9Wg== X-Received: by 2002:a05:6938:a090:10b0:c25:8e4f:edf6 with SMTP id a640c23a62f3a-c258e501bbdmr816600166b.1.1788268678574; Tue, 01 Sep 2026 06:17:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/58] target/arm: Rename and adjust aarch32_max_v8_tcg_initfn Date: Tue, 1 Sep 2026 14:16:58 +0100 Message-ID: <20260901131732.2263947-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268994075154100 From: Richard Henderson Rename from aarch32_max_tcg_init and take an Object pointer, in preparation from being used with TypeInit. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-id: 20260827041557.775080-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-max.c | 2 +- target/arm/internals.h | 2 +- target/arm/tcg/cpu-max-v8.c | 4 +++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 4df52bcb08e..9ed45c8764f 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -108,7 +108,7 @@ static void cpu_max_initfn(Object *obj) =20 if (tcg_enabled()) { if (!aarch64_enabled) { - aarch32_max_tcg_init(cpu); + aarch32_max_v8_tcg_initfn(obj); } else { aarch64_max_tcg_initfn(obj); } diff --git a/target/arm/internals.h b/target/arm/internals.h index f6b4e173a54..fc7d5ad6f2c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1838,7 +1838,7 @@ uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool s= ecure, bool el_is_in_host(CPUARMState *env, int el); =20 void aa32_max_features(ARMCPU *cpu); -void aarch32_max_tcg_init(ARMCPU *cpu); +void aarch32_max_v8_tcg_initfn(Object *obj); int exception_target_el(CPUARMState *env); bool arm_singlestep_active(CPUARMState *env); bool arm_generate_debug_exceptions(CPUARMState *env); diff --git a/target/arm/tcg/cpu-max-v8.c b/target/arm/tcg/cpu-max-v8.c index 5c0ba28edf8..5a9845d88f3 100644 --- a/target/arm/tcg/cpu-max-v8.c +++ b/target/arm/tcg/cpu-max-v8.c @@ -101,8 +101,10 @@ void aa32_max_features(ARMCPU *cpu) FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ } =20 -void aarch32_max_tcg_init(ARMCPU *cpu) +void aarch32_max_v8_tcg_initfn(Object *obj) { + ARMCPU *cpu =3D ARM_CPU(obj); + aarch64_aa32_a57_init(cpu, false); aa32_max_features(cpu); #ifdef CONFIG_USER_ONLY --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268947; cv=none; d=zohomail.com; s=zohoarc; b=kCz5mNNlF6GxlByfh5BkOhFdJIAeeJs5zWGud+3Itj1AKXzMMDhj4X70/9k7kDg0EyJ7C79ymJOZa/KlO1AbSRFLlb6LjAdL9WE7b+YLH3YFhymV0Dq9PaN4xSVKBIC8mR9VFnfae59gIbV7hh5l3gSh6+hAzb4xJWyswgiz89E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268947; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=l23r3sBjF+KBdIzoy6ejBdKn1IF+X+LERpXbzhCmfaE=; b=kQfJpnJlf9m6yt64tTK92lBVmBo+rYebly77PiS4jG6hZVta2CYW+mUiHlgkOhTH2kiiY23aRYd9iloSE25IdTEwSFn0rFbKuOvEWEDjfyZrq2VmUoYq102vGDhXbYfbzEjQpkDa1P/Vg8hx+7AoDVejr74G+VaQv3seYhdATi4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268947410284.6314160967297; Tue, 1 Sep 2026 06:22:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONI-00016a-OV; Tue, 01 Sep 2026 09:18:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ONG-000162-PD for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:02 -0400 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ONF-0007D2-1c for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:02 -0400 Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-69fab5a852cso1375775a12.0 for ; Tue, 01 Sep 2026 06:18:00 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.17.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:17:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268679; x=1788873479; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=l23r3sBjF+KBdIzoy6ejBdKn1IF+X+LERpXbzhCmfaE=; b=UoU5zQ0rYGIG9K4gwIc7s/zFkrWu7fBCITir3UKOB4H+0T5dxKob63ssQVwEZP6jsd t6aGJIb+xtZbc+kWCyGcGgHjVB3CT1OO/GBorpIpKh/1GpAQJPyH2CW8stqD9AjFkflf TbvixW3er3CwmaXXQ7CeDEwOhkyWi/zeDVcLOLDQ0an8Qxv1B+hjESc9+mMdlJmCWhRJ Wdbqt7aV0/MdTxfi1HXjzetBBXFQpqKRrIjO+z+bwo6QQe3n3IX8Y0ttPe33N9I+L6U4 u0EzSOrBu6+p2zXf4jVNOBL1k4Yzp61Rf4AZ+RIFUIfyySlOwhUT8goJIDuh3O0q7xZW hzHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268679; x=1788873479; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=l23r3sBjF+KBdIzoy6ejBdKn1IF+X+LERpXbzhCmfaE=; b=Ob6vft513mDKZbdTH/crf3TLgfY+9R5FZwfbF+l+IZgQQbeNDoPzOwonncbVfZEYQv MKjgz3+aIP6XuFsCyjzrHgAJeZEbLMV0LwuACTIVQH2PgF2jXu6gR8ibDSky7YU0u2zG 1ia59n4VlqIjoG6+izyKEbHWWBl20OmqNSLWW66aBiah5qUJJyloQIj+slwObxz2v8Z+ Sk8NXlKeV0/3peqDcPa4HRFw6Tx4lXH/k/a2qAVMFvD6NQiWrWf98pLfRgOmFBMQW8po CjfCysRTm5DcZfWHfVHC8xOYkbp3INX/Pv8xDUpDkdl8qRm6KH7RU3wKRHaHi8D8x8vA Q6ng== X-Gm-Message-State: AFuF++m/b4d52T3hm60zyIr/NMBvtFcA8HDmKfO6bxRr/1x3YDh0xpyk wtbYYWhQYDFBdxXFofsH5LrOKSMs/kM8hDEJZoaeN5iWvihF0tbtpK01rCcY0D1JWiN0T9W9edc fo5fxTKQ= X-Gm-Gg: AYBFou1IMcC7waHeKAIqgYhH2J56mnnIi/WS5x9WWrnz++8kXc7apFC3fA7Ycclc+Bj TnJ1zq9b83eyVTsn1tJfN/R676vBojTamN6Cx/syUYeQ46FeUl0A2c9Vr8fxRoAmGrmn/8ULFnk i6A/U3sKgMt3yrqxSZBOJhTOIx3s/ndIDZaXnrJFePDz5yGB0bb6f0XlFx+l+qiIymyRcJaCLlI 9BDMAFSwqbWdTdEfMM0qPR/j/jGbWz3+DX0mGO8mnW0kNEXJ4fmzcKMavWYUxbEotUj4aRCGnz0 T8DsvCfmBUdRV9yEOIR/wC9CxGYEVYm3ELVDl3h+ou/Pxwa/DokDZei/qjdj0zOhK04M27YYEjO tw7J1n+4sFjwLZTDr5HS5B3gbtbjvUlxwZ351HPXLPCDaHo5LsPTvat57O2KkeaE+bvAQ24xVN9 t2jVVNfXxAUepU2SfofZGbXLEie1LMP0luEuBIPZp5Jjd/l1Qy2mHJ/lpL8rTuSu2fSmvfo9plj zhKyuaWdPi2XsMVbavpBvWRESxRI7veHuNIEDaqBZrblIb8jHeMTsdLgnLIqMBp+ioh1dI= X-Received: by 2002:a17:906:c147:b0:c24:adf4:5c73 with SMTP id a640c23a62f3a-c2556fb926dmr2033613666b.1.1788268679526; Tue, 01 Sep 2026 06:17:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/58] target/arm: Introduce cpu types max-v8 and max-v9 Date: Tue, 1 Sep 2026 14:16:59 +0100 Message-ID: <20260901131732.2263947-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268948369158500 From: Richard Henderson Introduce the names and allow them with the virt and sbsa-ref machine types. So far, the cpu types both exactly match "max". Signed-off-by: Richard Henderson Message-id: 20260827041557.775080-5-richard.henderson@linaro.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 2 ++ hw/arm/virt.c | 2 ++ target/arm/tcg/cpu-max-v8.c | 11 +++++++++++ target/arm/tcg/cpu64.c | 1 + 4 files changed, 16 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 484b90053e8..56d08f605c8 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -913,6 +913,8 @@ static void sbsa_ref_class_init(ObjectClass *oc, const = void *data) ARM_CPU_TYPE_NAME("neoverse-v1"), ARM_CPU_TYPE_NAME("neoverse-n2"), ARM_CPU_TYPE_NAME("max"), + ARM_CPU_TYPE_NAME("max-v8"), + ARM_CPU_TYPE_NAME("max-v9"), NULL, }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index e7a56e37f73..d738b95c726 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -4132,6 +4132,7 @@ static GPtrArray *virt_get_valid_cpu_types(const Mach= ineState *ms) if (tcg_enabled()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max-v8"))); } if (tcg_enabled() && target_aarch64()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35"))); @@ -4143,6 +4144,7 @@ static GPtrArray *virt_get_valid_cpu_types(const Mach= ineState *ms) g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max-v9"))); } if (target_aarch64()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); diff --git a/target/arm/tcg/cpu-max-v8.c b/target/arm/tcg/cpu-max-v8.c index 5a9845d88f3..55f8c341423 100644 --- a/target/arm/tcg/cpu-max-v8.c +++ b/target/arm/tcg/cpu-max-v8.c @@ -2,6 +2,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "qemu/target-info.h" #include "internals.h" =20 =20 @@ -117,3 +118,13 @@ void aarch32_max_v8_tcg_initfn(Object *obj) cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); #endif } + +static void cpu_max_v8_register_type(void) +{ + static const ARMCPUInfo max_v8[2] =3D { + { .name =3D "max-v8", .initfn =3D aarch32_max_v8_tcg_initfn }, + { .name =3D "max-v8", .initfn =3D aarch64_max_tcg_initfn } + }; + arm_cpu_register(&max_v8[target_aarch64()]); +} +type_init(cpu_max_v8_register_type) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index b38c61ba623..d44a8221c8b 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1488,6 +1488,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, { .name =3D "neoverse-n2", .initfn =3D aarch64_neoverse_n2_init= fn }, + { .name =3D "max-v9", .initfn =3D aarch64_max_tcg_initfn }, }; =20 static void aarch64_cpu_register_types(void) --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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These tests must use Armv8. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-id: 20260827041557.775080-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- tests/functional/aarch64/test_virt_aarch64_off.py | 4 ++-- tests/qtest/arm-cpu-features.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/functional/aarch64/test_virt_aarch64_off.py b/tests/func= tional/aarch64/test_virt_aarch64_off.py index 13d8b73b0d7..73c9a4109c0 100755 --- a/tests/functional/aarch64/test_virt_aarch64_off.py +++ b/tests/functional/aarch64/test_virt_aarch64_off.py @@ -18,9 +18,9 @@ class ArmVirtMachine(LinuxKernelTest): def test_arm_virt(self): self.set_machine('virt') # KVM aarch64=3Doff requires a host CPU that supports it, so - # restrict the test to TCG only + # restrict the test to TCG ARMv8. self.require_accelerator('tcg') - self.vm.add_args('-cpu', 'max,aarch64=3Doff') + self.vm.add_args('-cpu', 'max-v8,aarch64=3Doff') =20 kernel_path =3D self.ASSET_KERNEL.fetch() =20 diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index cb4d01fd46a..7348fb8d28b 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -493,8 +493,8 @@ static void test_query_cpu_model_expansion(const void *= data) sve_tests_default(qts, "max"); pauth_tests_default(qts, "max"); =20 - /* TCG allows us to turn off AArch64 on the 'max' CPU type */ - assert_set_feature(qts, "max", "aarch64", false); + /* TCG allows us to turn off AArch64 on the 'max-v8' CPU type */ + assert_set_feature(qts, "max-v8", "aarch64", false); } =20 qtest_quit(qts); --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268881; cv=none; d=zohomail.com; s=zohoarc; b=b4rmSb/4sIc6ogO9ExjbS1unwVFV5l1D/UuviuTSOAxQ4UQwkYNxN2FiLkYInH/9TtWmegoBEAozAwHcVhRTpxzf0r9P/e9iDUcfXDANM+kSo4sQbGvdUxOaSplfEdBVUzsODJ4RUzwScUjDy7M0Y37a++rprwNg/zCsqkS4L10= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268881; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=LKNqbhlu++jyYLQp8f/93LiN6+qvZQ8FMUXbv8EoVvk=; b=ZFWla4QB6pmzstErdus21YSmi3NfPnNDAz0VyyyaQbXy6xTm7tXq6W6hOJSjgJE7dPqDhJ/Ng5izl7t9FsO8V8lz7eDHncqUB2zSWnoe6IutU9OtNPL+egfM/qhiiUWuxvBcY0MbCoCjmar1dI9moIhH8phk+D1qMFQksEumYA0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268881594333.1215328450355; Tue, 1 Sep 2026 06:21:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONM-000188-06; Tue, 01 Sep 2026 09:18:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ONK-00017I-2L for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:06 -0400 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ONH-0007DV-CK for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:05 -0400 Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-c250c6a6a6eso112333866b.0 for ; Tue, 01 Sep 2026 06:18:03 -0700 (PDT) Received: from lanath.. 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Do not include the prohibited v8 features in "max-v9". In aarch64 tcg mode, define "max" as "max-v9". Signed-off-by: Richard Henderson Message-id: 20260827041557.775080-7-richard.henderson@linaro.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 13 ++- target/arm/cpu-max.c | 2 +- target/arm/internals.h | 3 +- target/arm/tcg/cpu-max-v8.c | 2 +- target/arm/tcg/cpu64.c | 160 ++++++++++++++++++++++------------ target/arm/tcg/stubs32.c | 7 +- 6 files changed, 128 insertions(+), 59 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index cc42db9e0b7..ff02435975b 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -230,7 +230,18 @@ to the `Arm Architecture Reference Manual for A-profil= e architecture When a specific named CPU is being emulated, only those features which are present in hardware for that CPU are emulated. (If a feature is not in the list above then it is not supported, even if the real -hardware should have it.) The ``max`` CPU enables all features. +hardware should have it.) + +The ``max-v8`` CPU enables all of the listed Armv8-A architecture +extensions but none of the Armv9-A architecture extensions. + +The ``max-v9`` CPU enables all of the listed extensions except for +those that are prohibited by the Armv9-A architecture: FEAT_AA32EL1, +FEAT_AA32EL2, FEAT_AA32EL3, and FEAT_DoubleLock. + +The ``max`` CPU is an alias for ``max-v9`` under AArch64 TCG emulation, +an alias for ``max-v8`` under AArch32 TCG emulation, or an alias +for ``host`` under hardware virtualization. =20 R-profile CPU architecture support =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 9ed45c8764f..739500a04fc 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -110,7 +110,7 @@ static void cpu_max_initfn(Object *obj) if (!aarch64_enabled) { aarch32_max_v8_tcg_initfn(obj); } else { - aarch64_max_tcg_initfn(obj); + aarch64_max_v9_tcg_initfn(obj); } return; } diff --git a/target/arm/internals.h b/target/arm/internals.h index fc7d5ad6f2c..1775835ad50 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1809,7 +1809,8 @@ void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **er= rp); void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); -void aarch64_max_tcg_initfn(Object *obj); +void aarch64_max_v8_tcg_initfn(Object *obj); +void aarch64_max_v9_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); diff --git a/target/arm/tcg/cpu-max-v8.c b/target/arm/tcg/cpu-max-v8.c index 55f8c341423..65f851f2006 100644 --- a/target/arm/tcg/cpu-max-v8.c +++ b/target/arm/tcg/cpu-max-v8.c @@ -123,7 +123,7 @@ static void cpu_max_v8_register_type(void) { static const ARMCPUInfo max_v8[2] =3D { { .name =3D "max-v8", .initfn =3D aarch32_max_v8_tcg_initfn }, - { .name =3D "max-v8", .initfn =3D aarch64_max_tcg_initfn } + { .name =3D "max-v8", .initfn =3D aarch64_max_v8_tcg_initfn }, }; arm_cpu_register(&max_v8[target_aarch64()]); } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index d44a8221c8b..251c4b3cf60 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1166,11 +1166,10 @@ static void aarch64_neoverse_n2_initfn(Object *obj) } =20 /* - * -cpu max: a CPU with as many features enabled as our emulation supports. - * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; - * this only needs to handle 64 bits. + * -cpu max-v8: an ARMv8 CPU with as many features enabled as + * our emulation supports. */ -void aarch64_max_tcg_initfn(Object *obj) +void aarch64_max_v8_tcg_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); ARMISARegisters *isar =3D &cpu->isar; @@ -1244,7 +1243,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* v8.0: FEAT_SHA1 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* v8.1: FEAT_SHA512 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* v8.0: FEAT_CRC32 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 3); /* v9.3: FEAT_LSE128 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* v8.0: FEAT_LSE */ t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* v8.0: FEAT_RDM */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* v8.1: FEAT_SHA3 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* v8.1: FEAT_SM3 */ @@ -1277,16 +1276,10 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* v8.7: FEAT_MOPS */ t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* v8.7: FEAT_HBC */ t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* v8.6: FEAT_WFxT */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* v9.3: FEAT_CMPBR */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* v9.2: FEAT_LUT */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 1); /* v8.7: FEAT_CSSC */ t =3D FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* v8.8: FEAT_ATS1A */ SET_IDREG(isar, ID_AA64ISAR2, t); =20 - t =3D GET_IDREG(isar, ID_AA64ISAR3); - t =3D FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* v9.2: FEAT_FAMINMAX= */ - t =3D FIELD_DP64(t, ID_AA64ISAR3, FPRCVT, 1); /* v9.5: FEAT_FPRCVT */ - SET_IDREG(isar, ID_AA64ISAR3, t); - t =3D GET_IDREG(isar, ID_AA64PFR0); t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* v8.2: FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* v8.2: FEAT_FP16 */ @@ -1308,17 +1301,14 @@ void aarch64_max_tcg_initfn(Object *obj) */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* v8.5: FEAT_MTE3 */ t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* v8.3: FEAT_DoubleFa= ult */ - t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* v9.2: FEAT_SME2 */ t =3D FIELD_DP64(t, ID_AA64PFR1, RNDR_TRAP, 1); /* v8.4: FEAT_RNG_TRAP= */ t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* v8.0: FEAT_CSV2_3 */ t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* v8.7: FEAT_NMI */ - t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* v9.3: FEAT_GCS */ /* v8.7: FEAT_MTE_NO_ADDRESS_TAGS + FEAT_MTE_CANONICAL_TAGS */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTEX, 1); SET_IDREG(isar, ID_AA64PFR1, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR2); - t =3D FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* v9.2: FEAT_FPMR */ t =3D FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 1); /* v8.7: FEAT_MTE_TAGG= ED_FAR */ t =3D FIELD_DP64(t, ID_AA64PFR2, MTESTOREONLY, 1); /* v8.7: FEAT_MTE_S= TORE_ONLY */ t =3D FIELD_DP64(t, ID_AA64PFR2, MTEPERM, 1); /* v8.7: FEAT_MTE_PERM= */ @@ -1368,25 +1358,14 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D GET_IDREG(isar, ID_AA64MMFR3); t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* v8.0: FEAT_TCR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* v8.0: FEAT_SCTLR2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* v9.2: FEAT_MEC */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* v8.2: FEAT_FPACC_= SPEC */ t =3D FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* v8.8: FEAT_S1PIE */ t =3D FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* v8.8: FEAT_S2PIE */ t =3D FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* v8.8: FEAT_AIE */ SET_IDREG(isar, ID_AA64MMFR3, t); =20 - t =3D GET_IDREG(isar, ID_AA64MMFR4); - t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* v9.4: FEAT_ASID2 */ - SET_IDREG(isar, ID_AA64MMFR4, t); - t =3D GET_IDREG(isar, ID_AA64ZFR0); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* v9.2: FEAT_SVE2p1 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMUL= L128 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitP= erm */ t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 2); /* v8.2: FEAT_EBF16 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* v9.2: FEAT_SVE_B16B= 16 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3= */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* v9.0: FEAT_SVE_SM4 = */ t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* v8.1: FEAT_I8MM */ t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* v8.2: FEAT_F32MM */ t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* v8.2: FEAT_F64MM */ @@ -1398,6 +1377,106 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* v8.5: FEAT_HPMN0 */ SET_IDREG(isar, ID_AA64DFR0, t); =20 + /* Replicate the same data to the 32-bit id registers. */ + aa32_max_features(cpu); + +#ifdef CONFIG_USER_ONLY + /* + * For usermode -cpu max we can use a larger and more efficient DCZ + * blocksize since we don't have to follow what the hardware does. + */ + cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ + set_dczid_bs(cpu, 7); /* 512 bytes */ +#endif + + /* v8.2: FEAT_SVE */ + cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); + aarch64_add_sve_properties(OBJECT(cpu)); + object_property_add(OBJECT(cpu), "sve-max-vq", "uint32", + cpu_max_get_sve_max_vq, cpu_max_set_sve_max_vq, + NULL, NULL); + + /* v8.2: FEAT_PAuth2 */ + aarch64_add_pauth_properties(OBJECT(cpu)); + + /* v8.4: FEAT_MTE2 */ + cpu->gm_blocksize =3D 6; /* 256 bytes */ + + /* v8.6: FEAT_LPA2 */ + qdev_property_add_static(DEVICE(cpu), &arm_cpu_lpa2_property); +} + +/* + * -cpu max-v9: an ARMv9 CPU with as many features enabled as + * our emulation supports. + */ +void aarch64_max_v9_tcg_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; + uint64_t t; + + /* Armv9.0 is based on a minimum of Armv8.5. */ + aarch64_max_v8_tcg_initfn(obj); + + /* + * Armv9.0 does not support AArch32 except at EL0, + * therefore indicate EL1 through EL3 are AArch64-only. + */ + t =3D GET_IDREG(isar, ID_AA64PFR0); + t =3D FIELD_DP64(t, ID_AA64PFR0, EL1, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, EL2, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, EL3, 1); + SET_IDREG(isar, ID_AA64PFR0, t); + + /* v9.0 prohibits FEAT_DoubleLock. */ + FIELD_DP64_IDREG(isar, ID_AA64DFR0, DOUBLELOCK, -1); + FIELD_DP64_IDREG(isar, ID_AA64PFR0, RAS, 1); + isar->dbgdevid =3D FIELD_DP32(isar->dbgdevid, DBGDEVID, DOUBLELOCK, 0); + + /* + * Below, note the revision from which the feature is OPTIONAL. + */ + t =3D GET_IDREG(isar, ID_AA64ISAR0); + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 3); /* v9.3: FEAT_LSE128 */ + SET_IDREG(isar, ID_AA64ISAR0, t); + + t =3D GET_IDREG(isar, ID_AA64ISAR2); + t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* v9.3: FEAT_CMPBR */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* v9.2: FEAT_LUT */ + SET_IDREG(isar, ID_AA64ISAR2, t); + + t =3D GET_IDREG(isar, ID_AA64ISAR3); + t =3D FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* v9.2: FEAT_FAMINMAX= */ + t =3D FIELD_DP64(t, ID_AA64ISAR3, FPRCVT, 1); /* v9.5: FEAT_FPRCVT */ + SET_IDREG(isar, ID_AA64ISAR3, t); + + t =3D GET_IDREG(isar, ID_AA64PFR1); + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* v9.2: FEAT_SME2 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* v9.3: FEAT_GCS */ + SET_IDREG(isar, ID_AA64PFR1, t); + + t =3D GET_IDREG(isar, ID_AA64PFR2); + t =3D FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* v9.2: FEAT_FPMR */ + SET_IDREG(isar, ID_AA64PFR2, t); + + t =3D GET_IDREG(isar, ID_AA64MMFR3); + t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* v9.2: FEAT_MEC */ + SET_IDREG(isar, ID_AA64MMFR3, t); + + t =3D GET_IDREG(isar, ID_AA64MMFR4); + t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* v9.4: FEAT_ASID2 */ + SET_IDREG(isar, ID_AA64MMFR4, t); + + t =3D GET_IDREG(isar, ID_AA64ZFR0); + t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* v9.2: FEAT_SVE2p1 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMUL= L128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitP= erm */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* v9.2: FEAT_SVE_B16B= 16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3= */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* v9.0: FEAT_SVE_SM4 = */ + SET_IDREG(isar, ID_AA64ZFR0, t); + t =3D GET_IDREG(isar, ID_AA64SMFR0); t =3D FIELD_DP64(t, ID_AA64SMFR0, SMOP4, 1); /* v9.4: FEAT_SME_MOP4= */ t =3D FIELD_DP64(t, ID_AA64SMFR0, STMOP, 1); /* v9.4: FEAT_SME_TMOP= */ @@ -1434,43 +1513,16 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64FPFR0, F8CVT, 1); /* v9.2: FEAT_FP8 */ SET_IDREG(isar, ID_AA64FPFR0, t); =20 - /* Replicate the same data to the 32-bit id registers. */ - aa32_max_features(cpu); - -#ifdef CONFIG_USER_ONLY - /* - * For usermode -cpu max we can use a larger and more efficient DCZ - * blocksize since we don't have to follow what the hardware does. - */ - cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ - set_dczid_bs(cpu, 7); /* 512 bytes */ -#endif - - /* v8.4: FEAT_MTE2 */ - cpu->gm_blocksize =3D 6; /* 256 bytes */ - - /* v8.2: FEAT_SVE */ - cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); - aarch64_add_sve_properties(obj); - object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, - cpu_max_set_sve_max_vq, NULL, NULL); - /* v9.2: FEAT_SME */ cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; aarch64_add_sme_properties(obj); =20 - /* v8.2: FEAT_PAuth2 */ - aarch64_add_pauth_properties(obj); - /* v9.1: FEAT_RME */ object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rm= e); =20 /* v9.4: FEAT_RME_GPC2 */ object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz, cpu_max_set_l0gptsz, NULL, NULL); - - /* v8.6: FEAT_LPA2 */ - qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); } =20 static const ARMCPUInfo aarch64_cpus[] =3D { @@ -1488,7 +1540,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, { .name =3D "neoverse-n2", .initfn =3D aarch64_neoverse_n2_init= fn }, - { .name =3D "max-v9", .initfn =3D aarch64_max_tcg_initfn }, + { .name =3D "max-v9", .initfn =3D aarch64_max_v9_tcg_initf= n }, }; =20 static void aarch64_cpu_register_types(void) diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c index 78f819ef6ff..af0911a24c3 100644 --- a/target/arm/tcg/stubs32.c +++ b/target/arm/tcg/stubs32.c @@ -28,7 +28,12 @@ void aarch64_host_initfn(Object *obj) g_assert_not_reached(); } =20 -void aarch64_max_tcg_initfn(Object *obj) +void aarch64_max_v8_tcg_initfn(Object *obj) +{ + g_assert_not_reached(); +} + +void aarch64_max_v9_tcg_initfn(Object *obj) { g_assert_not_reached(); } --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268733; cv=none; d=zohomail.com; s=zohoarc; b=Lc/qWHS/kzk/qqDumPEFOwqZr4un1bLwS59h3cL7nfpcqiD1evx7srS7AziNlEoMtg7Q/W0tnp5f5JIIDXhbFLjVN3WCaLLW+q3UaJS/+difB+wVi9wrzBqtcTAixfz/szzefy4Bl12lzMyjRKX9hEnMLgvh0HMPLSWwNzYAigo= ARC-Message-Signature: i=1; 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Tue, 01 Sep 2026 06:18:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/58] target/arm: Add FGWTE3_EL3 Date: Tue, 1 Sep 2026 14:17:02 +0100 Message-ID: <20260901131732.2263947-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268737941154100 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260806172709.333300-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 1 + target/arm/cpu-features.h | 5 +++++ target/arm/cpu.h | 2 +- target/arm/helper.c | 20 ++++++++++++++++++++ 4 files changed, 27 insertions(+), 1 deletion(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 391c0e322b7..34592679e49 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -385,6 +385,7 @@ typedef enum CPAccessResult { /* Indexes into fgt_write[] */ #define FGTREG_HFGWTR 0 #define FGTREG_HDFGWTR 1 +#define FGTREG_FGWTE3 2 /* Indexes into fgt_exec[] */ #define FGTREG_HFGITR 0 =20 diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 280ead6f9cb..3c8d7033dea 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1467,6 +1467,11 @@ static inline bool isar_feature_aa64_asid2(const ARM= ISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) !=3D 0; } =20 +static inline bool isar_feature_aa64_fgwte3(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR4, FGWTE3) !=3D 0; +} + /* * Note the E2H0 ID fields is signed, increasingly negative as more * isn't implemented. diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e8dfc3179f2..e3f931dba26 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -553,7 +553,7 @@ typedef struct CPUArchState { * FEAT_FGT2 will add more elements to these arrays. */ uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ - uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ + uint64_t fgt_write[3]; /* HFGWTR, HDFGWTR, FGWTE3 */ uint64_t fgt_exec[1]; /* HFGITR */ =20 /* RME registers */ diff --git a/target/arm/helper.c b/target/arm/helper.c index e10ec21a8cd..1b24aca2937 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6394,6 +6394,22 @@ static const ARMCPRegInfo fpmr_reginfo[] =3D { } }; =20 +static void fgwte3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* All bits are W1S and can only be cleared by cpu reset. */ + env->cp15.fgt_write[FGTREG_FGWTE3] |=3D value; +} + +static const ARMCPRegInfo fgwte3_reginfo[] =3D { + { .name =3D "FGWTE3_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 5, + .access =3D PL3_RW, .resetvalue =3D 0, + .writefn =3D fgwte3_write, .raw_writefn =3D raw_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_write[FGTREG_FGWTE3]) + }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7705,6 +7721,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, ccsidr2_reginfo); } =20 + if (cpu_isar_feature(aa64_fgwte3, cpu)) { + define_arm_cp_regs(cpu, fgwte3_reginfo); + } + define_pm_cpregs(cpu); define_gcs_cpregs(cpu); } --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 01 Sep 2026 06:18:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/58] target/arm: Add FGWTE3_EL3 bit definitions Date: Tue, 1 Sep 2026 14:17:03 +0100 Message-ID: <20260901131732.2263947-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269104003154100 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260806172709.333300-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 34592679e49..2c9927b1d95 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -689,6 +689,30 @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) =20 +FIELD(FGWTE3_EL3, ACTLR_EL3, 0, 1) +FIELD(FGWTE3_EL3, AFSR0_EL3, 1, 1) +FIELD(FGWTE3_EL3, AFSR1_EL3, 2, 1) +FIELD(FGWTE3_EL3, AMAIR_EL3, 3, 1) +FIELD(FGWTE3_EL3, AMAIR2_EL3, 4, 1) +FIELD(FGWTE3_EL3, GCSCR_EL3, 5, 1) +FIELD(FGWTE3_EL3, GCSPR_EL3, 6, 1) +FIELD(FGWTE3_EL3, GPCCR_EL3, 7, 1) +FIELD(FGWTE3_EL3, GPTBR_EL3, 8, 1) +FIELD(FGWTE3_EL3, MAIR_EL3, 9, 1) +FIELD(FGWTE3_EL3, MAIR2_EL3, 10, 1) +FIELD(FGWTE3_EL3, MDCR_EL3, 11, 1) +FIELD(FGWTE3_EL3, MECID_RL_A_EL3, 12, 1) +FIELD(FGWTE3_EL3, MPAM3_EL3, 13, 1) +FIELD(FGWTE3_EL3, PIR_EL3, 14, 1) +FIELD(FGWTE3_EL3, SCTLR_EL3, 15, 1) +FIELD(FGWTE3_EL3, SCTLR2_EL3, 16, 1) +FIELD(FGWTE3_EL3, SPMROOTCR_EL3, 17, 1) +FIELD(FGWTE3_EL3, TCR_EL3, 18, 1) +FIELD(FGWTE3_EL3, TPIDR_EL3, 19, 1) +FIELD(FGWTE3_EL3, TTBR0_EL3, 20, 1) +FIELD(FGWTE3_EL3, VBAR_EL3, 21, 1) +FIELD(FGWTE3_EL3, GPCBW_EL3, 22, 1) + FIELD(FGT, NXS, 13, 1) /* Honour HCR_EL2.FGTnXS to suppress FGT */ /* Which fine-grained trap bit register to check, if any */ FIELD(FGT, TYPE, 10, 3) --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 01 Sep 2026 06:18:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/58] target/arm: Add FGWTE3 FGT bit definitions Date: Tue, 1 Sep 2026 14:17:04 +0100 Message-ID: <20260901131732.2263947-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269114189154100 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260806172709.333300-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 2c9927b1d95..9f2532fe667 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -728,6 +728,9 @@ FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uin= t64_t */ #define DO_BIT(REG, BITNAME) \ FGT_##BITNAME =3D FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT =20 +#define DO_EL3_BIT(REG, BITNAME) \ + FGT_##BITNAME =3D FGT_##REG | R_##REG##_EL3_##BITNAME##_SHIFT + /* Some bits have reversed sense, so 0 means trap and 1 means not */ #define DO_REV_BIT(REG, BITNAME) \ FGT_##BITNAME =3D FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT @@ -787,6 +790,7 @@ typedef enum FGTBit { FGT_HDFGRTR =3D FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), FGT_HDFGWTR =3D FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), FGT_HFGITR =3D FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), + FGT_FGWTE3 =3D FGT_W | (FGTREG_FGWTE3 << R_FGT_IDX_SHIFT), =20 /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */ DO_BIT(HFGRTR, AFSR0_EL1), @@ -919,10 +923,37 @@ typedef enum FGTBit { DO_REV_BIT(HFGITR, NGCSPUSHM_EL1), DO_REV_BIT(HFGITR, NGCSEPP), DO_BIT(HFGITR, ATS1E1A), + + /* Trap bits in FGWTE3_EL3, starting from bit 0 */ + DO_EL3_BIT(FGWTE3, ACTLR_EL3), + DO_EL3_BIT(FGWTE3, AFSR0_EL3), + DO_EL3_BIT(FGWTE3, AFSR1_EL3), + DO_EL3_BIT(FGWTE3, AMAIR_EL3), + DO_EL3_BIT(FGWTE3, AMAIR2_EL3), + DO_EL3_BIT(FGWTE3, GCSCR_EL3), + DO_EL3_BIT(FGWTE3, GCSPR_EL3), + DO_EL3_BIT(FGWTE3, GPCCR_EL3), + DO_EL3_BIT(FGWTE3, GPTBR_EL3), + DO_EL3_BIT(FGWTE3, MAIR_EL3), + DO_EL3_BIT(FGWTE3, MAIR2_EL3), + DO_EL3_BIT(FGWTE3, MDCR_EL3), + DO_EL3_BIT(FGWTE3, MECID_RL_A_EL3), + DO_EL3_BIT(FGWTE3, MPAM3_EL3), + DO_EL3_BIT(FGWTE3, PIR_EL3), + DO_EL3_BIT(FGWTE3, SCTLR_EL3), + DO_EL3_BIT(FGWTE3, SCTLR2_EL3), + DO_EL3_BIT(FGWTE3, SPMROOTCR_EL3), + DO_EL3_BIT(FGWTE3, TCR_EL3), + DO_EL3_BIT(FGWTE3, TPIDR_EL3), + DO_EL3_BIT(FGWTE3, TTBR0_EL3), + DO_EL3_BIT(FGWTE3, VBAR_EL3), + DO_EL3_BIT(FGWTE3, GPCBW_EL3), } FGTBit; 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Tue, 01 Sep 2026 06:18:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/58] target/arm: Implement FGWTE3 traps Date: Tue, 1 Sep 2026 14:17:05 +0100 Message-ID: <20260901131732.2263947-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268731927154100 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260806172709.333300-5-richard.henderson@linaro.org [PMM: fixed comment indent] Signed-off-by: Peter Maydell --- target/arm/tcg/op_helper.c | 40 +++++++++++++++++++++++----------- target/arm/tcg/translate-a64.c | 16 +++++++++++++- 2 files changed, 42 insertions(+), 14 deletions(-) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 857e897a48d..c2b09176cb1 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -1061,13 +1061,15 @@ const void *HELPER(access_check_cp_reg)(CPUARMState= *env, uint32_t key, * Fine-grained traps also are lower priority than undef-to-EL1, * higher priority than trap-to-EL3, and we don't care about priority * order with other EL2 traps because the syndrome value is the same. + * + * FGWTE3 traps are exclusively traps to EL3 on registers that are + * only accessible to EL3, so there's no possibility of a trap to EL2. + * So we can handle these checks here too. */ - if (arm_fgt_active(env, arm_current_el(env))) { + if (ri->fgt) { uint64_t trapword =3D 0; unsigned int idx =3D FIELD_EX32(ri->fgt, FGT, IDX); unsigned int bitpos =3D FIELD_EX32(ri->fgt, FGT, BITPOS); - bool rev =3D FIELD_EX32(ri->fgt, FGT, REV); - bool nxs =3D FIELD_EX32(ri->fgt, FGT, NXS); bool trapbit; =20 if (ri->fgt & FGT_EXEC) { @@ -1080,19 +1082,31 @@ const void *HELPER(access_check_cp_reg)(CPUARMState= *env, uint32_t key, assert(idx < ARRAY_SIZE(env->cp15.fgt_write)); trapword =3D env->cp15.fgt_write[idx]; } + trapbit =3D extract64(trapword, bitpos, 1); =20 - if (nxs && (arm_hcrx_el2_eff(env) & HCRX_FGTNXS)) { + if ((ri->access & ~PL3_RW) =3D=3D 0) { /* - * If HCRX_EL2.FGTnXS is 1 then the fine-grained trap for - * TLBI maintenance insns does *not* apply to the nXS variant. + * EL3 cpreg -- must be FGWTE3, and FGWTE3_EL3 can only be + * set from AArch64, and if the feature is enabled. */ - trapbit =3D 0; - } else { - trapbit =3D extract64(trapword, bitpos, 1); - } - if (trapbit !=3D rev) { - res =3D CP_ACCESS_TRAP_EL2; - goto fail; + if (trapbit) { + res =3D CP_ACCESS_TRAP_EL3; + goto fail; + } + } else if (arm_fgt_active(env, arm_current_el(env))) { + bool nxs =3D FIELD_EX32(ri->fgt, FGT, NXS); + bool rev =3D FIELD_EX32(ri->fgt, FGT, REV); + if (nxs && (arm_hcrx_el2_eff(env) & HCRX_FGTNXS)) { + /* + * If HCRX_EL2.FGTnXS is 1 then the fine-grained trap for + * TLBI maintenance insns does *not* apply to the nXS vari= ant. + */ + trapbit =3D 0; + } + if (trapbit !=3D rev) { + res =3D CP_ACCESS_TRAP_EL2; + goto fail; + } } } =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4f9a93950b1..c60f4c4103d 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2886,6 +2886,7 @@ static void handle_sys(DisasContext *s, bool isread, { uint32_t key =3D ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2); const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); + bool need_helper =3D false; bool need_exit_tb =3D false; bool nv_trap_to_el2 =3D false; bool nv_redirect_reg =3D false; @@ -2999,7 +3000,20 @@ static void handle_sys(DisasContext *s, bool isread, ri =3D redirect_cpreg(s, key, isread); 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Tue, 01 Sep 2026 06:18:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/58] target/arm: Set fgt in cpregs for FGWTE3 Date: Tue, 1 Sep 2026 14:17:06 +0100 Message-ID: <20260901131732.2263947-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269099935154100 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260806172709.333300-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs-gcs.c | 5 +++-- target/arm/helper.c | 49 ++++++++++++++++++++++------------------- 2 files changed, 29 insertions(+), 25 deletions(-) diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c index e31827342d9..9c9ae9cd715 100644 --- a/target/arm/cpregs-gcs.c +++ b/target/arm/cpregs-gcs.c @@ -97,7 +97,7 @@ static const ARMCPRegInfo gcs_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[2]) }, { .name =3D "GCSCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_GCSCR_EL3, .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[3]) }, =20 { .name =3D "GCSPR_EL0", .state =3D ARM_CP_STATE_AA64, @@ -119,7 +119,8 @@ static const ARMCPRegInfo gcs_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[2]) }, { .name =3D "GCSPR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, - .access =3D PL3_RW, .writefn =3D gcspr_write, + .access =3D PL3_RW, .fgt =3D FGT_GCSPR_EL3, + .writefn =3D gcspr_write, .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[2]) }, =20 { .name =3D "GCSPUSHM", .state =3D ARM_CP_STATE_AA64, diff --git a/target/arm/helper.c b/target/arm/helper.c index 1b24aca2937..c3f607e6d6b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1056,7 +1056,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .resetvalue =3D 0 }, { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[3]), + .access =3D PL3_RW, .fgt =3D FGT_MAIR_EL3, + .fieldoffset =3D offsetof(CPUARMState, cp15.mair_el[3]), .resetvalue =3D 0 }, /* * For non-long-descriptor page tables these are PRRR and NMRR; @@ -3728,7 +3729,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .type =3D ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, .resetvalue =3D 0, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_MDCR_EL3, .writefn =3D mdcr_el3_write, .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el3) }, { .name =3D "SDCR", .type =3D ARM_CP_ALIAS | ARM_CP_IO, @@ -4498,11 +4499,11 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.mvbar) }, { .name =3D "TTBR0_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, .resetvalue =3D 0, + .access =3D PL3_RW, .fgt =3D FGT_TTBR0_EL3, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[3]) }, { .name =3D "TCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_TCR_EL3, /* no .writefn needed as this can't cause an ASID change */ .resetvalue =3D 0, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[3]) }, @@ -4524,7 +4525,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_MON]) }, { .name =3D "VBAR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, .writefn =3D vbar_write, + .access =3D PL3_RW, .fgt =3D FGT_VBAR_EL3, .writefn =3D vbar_write, .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[3]), .resetvalue =3D 0 }, { .name =3D "CPTR_EL3", .state =3D ARM_CP_STATE_AA64, @@ -4533,20 +4534,20 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[3]) }, { .name =3D "TPIDR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, - .access =3D PL3_RW, .resetvalue =3D 0, + .access =3D PL3_RW, .fgt =3D FGT_TPIDR_EL3, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[3]) }, { .name =3D "AMAIR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL3_RW, .fgt =3D FGT_AMAIR_EL3, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR0_EL3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL3_RW, .fgt =3D FGT_AFSR0_EL3, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR1_EL3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL3_RW, .fgt =3D FGT_AFSR1_EL3, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 #ifndef CONFIG_USER_ONLY @@ -5114,15 +5115,17 @@ static void gpcbw_write(CPUARMState *env, const ARM= CPRegInfo *ri, static const ARMCPRegInfo rme_reginfo[] =3D { { .name =3D "GPCCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 6, - .access =3D PL3_RW, .writefn =3D gpccr_write, .resetfn =3D gpccr_res= et, + .access =3D PL3_RW, .fgt =3D FGT_GPCCR_EL3, + .writefn =3D gpccr_write, .resetfn =3D gpccr_reset, .fieldoffset =3D offsetof(CPUARMState, cp15.gpccr_el3) }, { .name =3D "GPCBW_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 5, - .access =3D PL3_RW, .writefn =3D gpcbw_write, + .access =3D PL3_RW, .fgt =3D FGT_GPCBW_EL3, .writefn =3D gpcbw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.gpcbw_el3) }, { .name =3D "GPTBR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 4, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.gptb= r_el3) }, + .access =3D PL3_RW, .fgt =3D FGT_GPTBR_EL3, + .fieldoffset =3D offsetof(CPUARMState, cp15.gptbr_el3) }, { .name =3D "MFAR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 0, .opc2 =3D 5, .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mfar= _el3) }, @@ -5232,7 +5235,7 @@ static const ARMCPRegInfo mec_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a1_el2) }, { .name =3D "MECID_RL_A_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 1, .crn =3D 10, .crm =3D 10, - .access =3D PL3_RW, .accessfn =3D mecid_access, + .access =3D PL3_RW, .accessfn =3D mecid_access, .fgt =3D FGT_MECID_R= L_A_EL3, .writefn =3D mecid_write, .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_rl_a_el3) }, { .name =3D "VMECID_P_EL2", .state =3D ARM_CP_STATE_AA64, @@ -6182,7 +6185,7 @@ static const ARMCPRegInfo sctlr2_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[2]) }, { .name =3D "SCTLR2_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, - .access =3D PL3_RW, .writefn =3D sctlr2_el3_write, + .access =3D PL3_RW, .fgt =3D FGT_SCTLR2_EL3, .writefn =3D sctlr2_el3= _write, .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[3]) }, }; =20 @@ -6308,7 +6311,7 @@ static const ARMCPRegInfo s1pie_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.pir_el[2]) }, { .name =3D "PIR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 3, .crn =3D 10, .crm =3D 2, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_PIR_EL3, .fieldoffset =3D offsetof(CPUARMState, cp15.pir_el[3]) }, { .name =3D "PIRE0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 2, .crn =3D 10, .crm =3D 2, @@ -6366,7 +6369,7 @@ static const ARMCPRegInfo aie_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.mair2_el[2]) }, { .name =3D "MAIR2_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 1, .opc2 =3D 1, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_MAIR2_EL3, .fieldoffset =3D offsetof(CPUARMState, cp15.mair2_el[3]) }, =20 { .name =3D "AMAIR2_EL1", .state =3D ARM_CP_STATE_AA64, @@ -6382,7 +6385,7 @@ static const ARMCPRegInfo aie_reginfo[] =3D { .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AMAIR2_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_AMAIR2_EL3, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 @@ -7110,7 +7113,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D arm_feature(env, ARM_FEATURE_AARCH64) }, { .name =3D "SCTLR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 0, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_SCTLR_EL3, .raw_writefn =3D raw_write, .writefn =3D sctlr_write, .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[3]), .resetvalue =3D cpu->reset_sctlr }, @@ -7485,8 +7488,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D 0 }, { .name =3D "ACTLR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL3_RW, .fgt =3D FGT_ACTLR_EL3, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; define_arm_cp_regs(cpu, auxcr_reginfo); if (cpu_isar_feature(aa32_ac2, cpu)) { --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 01 Sep 2026 06:18:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/58] target/arm: Enable FEAT_FGWTE3 for -cpu max Date: Tue, 1 Sep 2026 14:17:07 +0100 Message-ID: <20260901131732.2263947-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269085402158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260806172709.333300-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index ff02435975b..e342ebb4445 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -78,6 +78,7 @@ the following architecture extensions: - FEAT_FAMINMAX (Floating-point maximum and minimum absolute value instruc= tions) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FGT (Fine-Grained Traps) +- FEAT_FGWTE3 (Fine-Grained Write Trap EL3) - FEAT_FHM (Floating-point half-precision multiplication instructions) - FEAT_FP (Floating Point extensions) - FEAT_FP16 (Half-precision floating-point data processing) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 251c4b3cf60..2d48b736bc7 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1466,6 +1466,7 @@ void aarch64_max_v9_tcg_initfn(Object *obj) =20 t =3D GET_IDREG(isar, ID_AA64MMFR4); t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* v9.4: FEAT_ASID2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR4, FGWTE3, 1); /* v9.4: FEAT_FGWTE3 */ SET_IDREG(isar, ID_AA64MMFR4, t); =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788269010; cv=none; d=zohomail.com; s=zohoarc; b=kTXvenbpHEpxIS5V0s8adqsuX8t766zG7XOPgPtiHg3KE/RcPjZ7o9AUEpbIhFs8zD192XtahHESSYTwFJj5U9j9cV0G3DsF5xz28qZspg8s95kOJyUbaHt/UJOilDTjztyqsim4RCjoseN19mdSuPAXCG9933X+H1pOp7+XIqs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788269010; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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During decode, retain z2z name and duplicate the same field into zd and zn. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 8 ++-- target/arm/tcg/translate-sme.c | 71 +++++++++++++++++----------------- 2 files changed, 39 insertions(+), 40 deletions(-) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index e8176fffdbf..30946330ffe 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -220,11 +220,13 @@ UMOPA2_s 1010000 1 10 0 ..... ... ... ..... . = 10 .. @op_32 %zd_ax2 1:4 !function=3Dtimes_2 %zd_ax4 2:3 !function=3Dtimes_4 =20 +&zzz_en zd zn zm esz n &z2z_en zdn zm esz n + @z2z_2x1 ....... . esz:2 .. zm:4 ....0. ..... .... . \ - &z2z_en n=3D2 zdn=3D%zd_ax2 + &zzz_en n=3D2 zd=3D%zd_ax2 zn=3D%zd_ax2 @z2z_4x1 ....... . esz:2 .. zm:4 ....1. ..... ...0 . \ - &z2z_en n=3D4 zdn=3D%zd_ax4 + &zzz_en n=3D4 zd=3D%zd_ax4 zn=3D%zd_ax4 =20 SMAX_n1 1100000 1 .. 10 .... 1010.0 00000 .... 0 @z2z_2x1 SMAX_n1 1100000 1 .. 10 .... 1010.0 00000 .... 0 @z2z_4x1 @@ -990,8 +992,6 @@ UZP_2 11000001 esz:2 1 zm:5 110100 zn:5 .... = 1 \ UZP_2 11000001 00 1 zm:5 110101 zn:5 .... 1 \ &zzz_e zd=3D%zd_ax2 esz=3D4 =20 -&zzz_en zd zn zm esz n - FCLAMP 11000001 esz:2 1 zm:5 110000 zn:5 .... 0 \ &zzz_en zd=3D%zd_ax2 n=3D2 FCLAMP 11000001 esz:2 1 zm:5 110010 zn:5 ...0 0 \ diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 768b76f01ec..e3b96914dad 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -659,31 +659,30 @@ TRANS_FEAT(BMOPA, aa64_sme2, do_outprod, a, MO_32, ge= n_helper_sme2_bmopa_s) TRANS_FEAT(SMOPA2_s, aa64_sme2, do_outprod, a, MO_32, gen_helper_sme2_smop= a2_s) TRANS_FEAT(UMOPA2_s, aa64_sme2, do_outprod, a, MO_32, gen_helper_sme2_umop= a2_s) =20 -static bool do_z2z_n1(DisasContext *s, arg_z2z_en *a, GVecGen3Fn *fn) +static bool do_zzz_n1(DisasContext *s, arg_zzz_en *a, GVecGen3Fn *fn) { - int esz, dn, vsz, mofs, n; - bool overlap =3D false; + int esz =3D a->esz, vsz, mofs; + int overlap =3D -1; =20 if (!sme_sm_enabled_check(s)) { return true; } =20 - esz =3D a->esz; - n =3D a->n; - dn =3D a->zdn; mofs =3D vec_full_reg_offset(s, a->zm); vsz =3D streaming_vec_reg_size(s); =20 - for (int i =3D 0; i < n; i++) { - int dofs =3D vec_full_reg_offset(s, dn + i); + for (int i =3D 0, n =3D a->n; i < n; i++) { + int dofs =3D vec_full_reg_offset(s, a->zd + i); + int nofs =3D vec_full_reg_offset(s, a->zn + i); if (dofs =3D=3D mofs) { - overlap =3D true; + overlap =3D i; } else { - fn(esz, dofs, dofs, mofs, vsz, vsz); + fn(esz, dofs, nofs, mofs, vsz, vsz); } } - if (overlap) { - fn(esz, mofs, mofs, mofs, vsz, vsz); + if (overlap >=3D 0) { + int nofs =3D vec_full_reg_offset(s, a->zn + overlap); + fn(esz, mofs, nofs, mofs, vsz, vsz); } return true; } @@ -710,14 +709,14 @@ static void gen_sme2_urshl(unsigned vece, uint32_t rd= _ofs, uint32_t rn_ofs, tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, 0, fns[vece= ]); } =20 -TRANS_FEAT(ADD_n1, aa64_sme2, do_z2z_n1, a, tcg_gen_gvec_add) -TRANS_FEAT(SMAX_n1, aa64_sme2, do_z2z_n1, a, tcg_gen_gvec_smax) -TRANS_FEAT(SMIN_n1, aa64_sme2, do_z2z_n1, a, tcg_gen_gvec_smin) -TRANS_FEAT(UMAX_n1, aa64_sme2, do_z2z_n1, a, tcg_gen_gvec_umax) -TRANS_FEAT(UMIN_n1, aa64_sme2, do_z2z_n1, a, tcg_gen_gvec_umin) -TRANS_FEAT(SRSHL_n1, aa64_sme2, do_z2z_n1, a, gen_sme2_srshl) -TRANS_FEAT(URSHL_n1, aa64_sme2, do_z2z_n1, a, gen_sme2_urshl) -TRANS_FEAT(SQDMULH_n1, aa64_sme2, do_z2z_n1, a, gen_gvec_sve2_sqdmulh) +TRANS_FEAT(ADD_n1, aa64_sme2, do_zzz_n1, a, tcg_gen_gvec_add) +TRANS_FEAT(SMAX_n1, aa64_sme2, do_zzz_n1, a, tcg_gen_gvec_smax) +TRANS_FEAT(SMIN_n1, aa64_sme2, do_zzz_n1, a, tcg_gen_gvec_smin) +TRANS_FEAT(UMAX_n1, aa64_sme2, do_zzz_n1, a, tcg_gen_gvec_umax) +TRANS_FEAT(UMIN_n1, aa64_sme2, do_zzz_n1, a, tcg_gen_gvec_umin) +TRANS_FEAT(SRSHL_n1, aa64_sme2, do_zzz_n1, a, gen_sme2_srshl) +TRANS_FEAT(URSHL_n1, aa64_sme2, do_zzz_n1, a, gen_sme2_urshl) +TRANS_FEAT(SQDMULH_n1, aa64_sme2, do_zzz_n1, a, gen_gvec_sve2_sqdmulh) =20 static bool do_z2z_nn(DisasContext *s, arg_z2z_en *a, GVecGen3Fn *fn) { @@ -750,11 +749,11 @@ TRANS_FEAT(SRSHL_nn, aa64_sme2, do_z2z_nn, a, gen_sme= 2_srshl) TRANS_FEAT(URSHL_nn, aa64_sme2, do_z2z_nn, a, gen_sme2_urshl) TRANS_FEAT(SQDMULH_nn, aa64_sme2, do_z2z_nn, a, gen_gvec_sve2_sqdmulh) =20 -static bool do_z2z_n1_fpst(DisasContext *s, arg_z2z_en *a, +static bool do_zzz_n1_fpst(DisasContext *s, arg_zzz_en *a, gen_helper_gvec_3_ptr * const fns[4]) { - int esz =3D a->esz, n, dn, vsz, mofs; - bool overlap =3D false; + int esz =3D a->esz, vsz, mofs; + int overlap =3D -1; gen_helper_gvec_3_ptr *fn =3D fns[esz]; TCGv_ptr fpst; =20 @@ -770,21 +769,21 @@ static bool do_z2z_n1_fpst(DisasContext *s, arg_z2z_e= n *a, } =20 fpst =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); - n =3D a->n; - dn =3D a->zdn; mofs =3D vec_full_reg_offset(s, a->zm); vsz =3D streaming_vec_reg_size(s); =20 - for (int i =3D 0; i < n; i++) { - int dofs =3D vec_full_reg_offset(s, dn + i); + for (int i =3D 0, n =3D a->n; i < n; i++) { + int dofs =3D vec_full_reg_offset(s, a->zd + i); + int nofs =3D vec_full_reg_offset(s, a->zn + i); if (dofs =3D=3D mofs) { - overlap =3D true; + overlap =3D i; } else { - tcg_gen_gvec_3_ptr(dofs, dofs, mofs, fpst, vsz, vsz, 0, fn); + tcg_gen_gvec_3_ptr(dofs, nofs, mofs, fpst, vsz, vsz, 0, fn); } } - if (overlap) { - tcg_gen_gvec_3_ptr(mofs, mofs, mofs, fpst, vsz, vsz, 0, fn); + if (overlap >=3D 0) { + int nofs =3D vec_full_reg_offset(s, a->zn + overlap); + tcg_gen_gvec_3_ptr(mofs, nofs, mofs, fpst, vsz, vsz, 0, fn); } return true; } @@ -831,7 +830,7 @@ static gen_helper_gvec_3_ptr * const f_vector_fmax[2][4= ] =3D { gen_helper_gvec_ah_fmax_s, gen_helper_gvec_ah_fmax_d }, }; -TRANS_FEAT(FMAX_n1, aa64_sme2, do_z2z_n1_fpst, a, f_vector_fmax[s->fpcr_ah= ]) +TRANS_FEAT(FMAX_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmax[s->fpcr_ah= ]) TRANS_FEAT(FMAX_nn, aa64_sme2, do_z2z_nn_fpst, a, f_vector_fmax[s->fpcr_ah= ]) =20 static gen_helper_gvec_3_ptr * const f_vector_fmin[2][4] =3D { @@ -844,7 +843,7 @@ static gen_helper_gvec_3_ptr * const f_vector_fmin[2][4= ] =3D { gen_helper_gvec_ah_fmin_s, gen_helper_gvec_ah_fmin_d }, }; -TRANS_FEAT(FMIN_n1, aa64_sme2, do_z2z_n1_fpst, a, f_vector_fmin[s->fpcr_ah= ]) +TRANS_FEAT(FMIN_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmin[s->fpcr_ah= ]) TRANS_FEAT(FMIN_nn, aa64_sme2, do_z2z_nn_fpst, a, f_vector_fmin[s->fpcr_ah= ]) =20 static gen_helper_gvec_3_ptr * const f_vector_fmaxnm[4] =3D { @@ -853,7 +852,7 @@ static gen_helper_gvec_3_ptr * const f_vector_fmaxnm[4]= =3D { gen_helper_gvec_fmaxnum_s, gen_helper_gvec_fmaxnum_d, }; -TRANS_FEAT(FMAXNM_n1, aa64_sme2, do_z2z_n1_fpst, a, f_vector_fmaxnm) +TRANS_FEAT(FMAXNM_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmaxnm) TRANS_FEAT(FMAXNM_nn, aa64_sme2, do_z2z_nn_fpst, a, f_vector_fmaxnm) =20 static gen_helper_gvec_3_ptr * const f_vector_fminnm[4] =3D { @@ -862,7 +861,7 @@ static gen_helper_gvec_3_ptr * const f_vector_fminnm[4]= =3D { gen_helper_gvec_fminnum_s, gen_helper_gvec_fminnum_d, }; -TRANS_FEAT(FMINNM_n1, aa64_sme2, do_z2z_n1_fpst, a, f_vector_fminnm) +TRANS_FEAT(FMINNM_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fminnm) TRANS_FEAT(FMINNM_nn, aa64_sme2, do_z2z_nn_fpst, a, f_vector_fminnm) =20 static gen_helper_gvec_3_ptr * const f_vector_famax[4] =3D { @@ -887,7 +886,7 @@ static gen_helper_gvec_3_ptr * const f_vector_fscale[4]= =3D { gen_helper_gvec_fscale_s, gen_helper_gvec_fscale_d, }; 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During decode, retain z2z name and duplicate the same field into zd and zn. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 5 ++- target/arm/tcg/translate-sme.c | 61 ++++++++++++++++------------------ 2 files changed, 30 insertions(+), 36 deletions(-) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 30946330ffe..36fbe24faf8 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -221,7 +221,6 @@ UMOPA2_s 1010000 1 10 0 ..... ... ... ..... . 10= .. @op_32 %zd_ax4 2:3 !function=3Dtimes_4 =20 &zzz_en zd zn zm esz n -&z2z_en zdn zm esz n =20 @z2z_2x1 ....... . esz:2 .. zm:4 ....0. ..... .... . \ &zzz_en n=3D2 zd=3D%zd_ax2 zn=3D%zd_ax2 @@ -266,9 +265,9 @@ FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0= @z2z_4x1 %zm_ax4 18:3 !function=3Dtimes_4 =20 @z2z_2x2 ....... . esz:2 . ....0 ....0. ..... .... . \ - &z2z_en n=3D2 zdn=3D%zd_ax2 zm=3D%zm_ax2 + &zzz_en n=3D2 zd=3D%zd_ax2 zn=3D%zd_ax2 zm=3D%zm_ax2 @z2z_4x4 ....... . esz:2 . ...00 ....1. ..... ...0 . \ - &z2z_en n=3D4 zdn=3D%zd_ax4 zm=3D%zm_ax4 + &zzz_en n=3D4 zd=3D%zd_ax4 zn=3D%zd_ax4 zm=3D%zm_ax4 =20 SMAX_nn 1100000 1 .. 1 ..... 1011.0 00000 .... 0 @z2z_2x2 SMAX_nn 1100000 1 .. 1 ..... 1011.0 00000 .... 0 @z2z_4x4 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index e3b96914dad..ca88b3cdcc7 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -718,36 +718,33 @@ TRANS_FEAT(SRSHL_n1, aa64_sme2, do_zzz_n1, a, gen_sme= 2_srshl) TRANS_FEAT(URSHL_n1, aa64_sme2, do_zzz_n1, a, gen_sme2_urshl) TRANS_FEAT(SQDMULH_n1, aa64_sme2, do_zzz_n1, a, gen_gvec_sve2_sqdmulh) =20 -static bool do_z2z_nn(DisasContext *s, arg_z2z_en *a, GVecGen3Fn *fn) +static bool do_zzz_nn(DisasContext *s, arg_zzz_en *a, GVecGen3Fn *fn) { - int esz, dn, dm, vsz, n; + int esz =3D a->esz, vsz; =20 if (!sme_sm_enabled_check(s)) { return true; } =20 - esz =3D a->esz; - n =3D a->n; - dn =3D a->zdn; - dm =3D a->zm; vsz =3D streaming_vec_reg_size(s); =20 - for (int i =3D 0; i < n; i++) { - int dofs =3D vec_full_reg_offset(s, dn + i); - int mofs =3D vec_full_reg_offset(s, dm + i); + for (int i =3D 0, n =3D a->n; i < n; i++) { + int dofs =3D vec_full_reg_offset(s, a->zd + i); + int nofs =3D vec_full_reg_offset(s, a->zn + i); + int mofs =3D vec_full_reg_offset(s, a->zm + i); =20 - fn(esz, dofs, dofs, mofs, vsz, vsz); + fn(esz, dofs, nofs, mofs, vsz, vsz); } return true; } =20 -TRANS_FEAT(SMAX_nn, aa64_sme2, do_z2z_nn, a, tcg_gen_gvec_smax) -TRANS_FEAT(SMIN_nn, aa64_sme2, do_z2z_nn, a, tcg_gen_gvec_smin) -TRANS_FEAT(UMAX_nn, aa64_sme2, do_z2z_nn, a, tcg_gen_gvec_umax) -TRANS_FEAT(UMIN_nn, aa64_sme2, do_z2z_nn, a, tcg_gen_gvec_umin) -TRANS_FEAT(SRSHL_nn, aa64_sme2, do_z2z_nn, a, gen_sme2_srshl) -TRANS_FEAT(URSHL_nn, aa64_sme2, do_z2z_nn, a, gen_sme2_urshl) -TRANS_FEAT(SQDMULH_nn, aa64_sme2, do_z2z_nn, a, gen_gvec_sve2_sqdmulh) +TRANS_FEAT(SMAX_nn, aa64_sme2, do_zzz_nn, a, tcg_gen_gvec_smax) +TRANS_FEAT(SMIN_nn, aa64_sme2, do_zzz_nn, a, tcg_gen_gvec_smin) +TRANS_FEAT(UMAX_nn, aa64_sme2, do_zzz_nn, a, tcg_gen_gvec_umax) +TRANS_FEAT(UMIN_nn, aa64_sme2, do_zzz_nn, a, tcg_gen_gvec_umin) +TRANS_FEAT(SRSHL_nn, aa64_sme2, do_zzz_nn, a, gen_sme2_srshl) +TRANS_FEAT(URSHL_nn, aa64_sme2, do_zzz_nn, a, gen_sme2_urshl) +TRANS_FEAT(SQDMULH_nn, aa64_sme2, do_zzz_nn, a, gen_gvec_sve2_sqdmulh) =20 static bool do_zzz_n1_fpst(DisasContext *s, arg_zzz_en *a, gen_helper_gvec_3_ptr * const fns[4]) @@ -788,10 +785,10 @@ static bool do_zzz_n1_fpst(DisasContext *s, arg_zzz_e= n *a, return true; } =20 -static bool do_z2z_nn_fpst(DisasContext *s, arg_z2z_en *a, +static bool do_zzz_nn_fpst(DisasContext *s, arg_zzz_en *a, gen_helper_gvec_3_ptr * const fns[4]) { - int esz =3D a->esz, n, dn, dm, vsz; + int esz =3D a->esz, vsz; gen_helper_gvec_3_ptr *fn =3D fns[esz]; TCGv_ptr fpst; =20 @@ -806,16 +803,14 @@ static bool do_z2z_nn_fpst(DisasContext *s, arg_z2z_e= n *a, } =20 fpst =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); - n =3D a->n; - dn =3D a->zdn; - dm =3D a->zm; vsz =3D streaming_vec_reg_size(s); =20 - for (int i =3D 0; i < n; i++) { - int dofs =3D vec_full_reg_offset(s, dn + i); - int mofs =3D vec_full_reg_offset(s, dm + i); + for (int i =3D 0, n =3D a->n; i < n; i++) { + int dofs =3D vec_full_reg_offset(s, a->zd + i); + int nofs =3D vec_full_reg_offset(s, a->zn + i); + int mofs =3D vec_full_reg_offset(s, a->zm + i); =20 - tcg_gen_gvec_3_ptr(dofs, dofs, mofs, fpst, vsz, vsz, 0, fn); + tcg_gen_gvec_3_ptr(dofs, nofs, mofs, fpst, vsz, vsz, 0, fn); } return true; } @@ -831,7 +826,7 @@ static gen_helper_gvec_3_ptr * const f_vector_fmax[2][4= ] =3D { gen_helper_gvec_ah_fmax_d }, }; TRANS_FEAT(FMAX_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmax[s->fpcr_ah= ]) -TRANS_FEAT(FMAX_nn, aa64_sme2, do_z2z_nn_fpst, a, f_vector_fmax[s->fpcr_ah= ]) +TRANS_FEAT(FMAX_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmax[s->fpcr_ah= ]) =20 static gen_helper_gvec_3_ptr * const f_vector_fmin[2][4] =3D { { gen_helper_gvec_fmin_b16, @@ -844,7 +839,7 @@ static gen_helper_gvec_3_ptr * const f_vector_fmin[2][4= ] =3D { gen_helper_gvec_ah_fmin_d }, }; TRANS_FEAT(FMIN_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmin[s->fpcr_ah= ]) -TRANS_FEAT(FMIN_nn, aa64_sme2, do_z2z_nn_fpst, a, f_vector_fmin[s->fpcr_ah= ]) +TRANS_FEAT(FMIN_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmin[s->fpcr_ah= ]) =20 static gen_helper_gvec_3_ptr * const f_vector_fmaxnm[4] =3D { gen_helper_gvec_fmaxnum_b16, @@ -853,7 +848,7 @@ static gen_helper_gvec_3_ptr * const f_vector_fmaxnm[4]= =3D { gen_helper_gvec_fmaxnum_d, }; TRANS_FEAT(FMAXNM_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmaxnm) -TRANS_FEAT(FMAXNM_nn, aa64_sme2, do_z2z_nn_fpst, a, f_vector_fmaxnm) +TRANS_FEAT(FMAXNM_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmaxnm) =20 static gen_helper_gvec_3_ptr * const f_vector_fminnm[4] =3D { gen_helper_gvec_fminnum_b16, @@ -862,7 +857,7 @@ static gen_helper_gvec_3_ptr * const f_vector_fminnm[4]= =3D { gen_helper_gvec_fminnum_d, }; TRANS_FEAT(FMINNM_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fminnm) -TRANS_FEAT(FMINNM_nn, aa64_sme2, do_z2z_nn_fpst, a, f_vector_fminnm) +TRANS_FEAT(FMINNM_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fminnm) =20 static gen_helper_gvec_3_ptr * const f_vector_famax[4] =3D { NULL, @@ -870,7 +865,7 @@ static gen_helper_gvec_3_ptr * const f_vector_famax[4] = =3D { gen_helper_gvec_famax_s, gen_helper_gvec_famax_d, }; -TRANS_FEAT(FAMAX_nn, aa64_sme2_faminmax, do_z2z_nn_fpst, a, f_vector_famax) +TRANS_FEAT(FAMAX_nn, aa64_sme2_faminmax, do_zzz_nn_fpst, a, f_vector_famax) =20 static gen_helper_gvec_3_ptr * const f_vector_famin[4] =3D { NULL, @@ -878,7 +873,7 @@ static gen_helper_gvec_3_ptr * const f_vector_famin[4] = =3D { gen_helper_gvec_famin_s, gen_helper_gvec_famin_d, }; -TRANS_FEAT(FAMIN_nn, aa64_sme2_faminmax, do_z2z_nn_fpst, a, f_vector_famin) +TRANS_FEAT(FAMIN_nn, aa64_sme2_faminmax, do_zzz_nn_fpst, a, f_vector_famin) =20 static gen_helper_gvec_3_ptr * const f_vector_fscale[4] =3D { NULL, @@ -887,7 +882,7 @@ static gen_helper_gvec_3_ptr * const f_vector_fscale[4]= =3D { gen_helper_gvec_fscale_d, }; TRANS_FEAT(FSCALE_n1, aa64_sme2_f8cvt, do_zzz_n1_fpst, a, f_vector_fscale) -TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_z2z_nn_fpst, a, f_vector_fscale) +TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_zzz_nn_fpst, a, f_vector_fscale) =20 /* Add/Sub vector Z[m] to each Z[n*N] with result in ZA[d*N]. */ static bool do_azz_n1(DisasContext *s, arg_azz_n *a, int esz, --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260826174213.614571-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 5 ++ target/arm/tcg/sme.decode | 90 ++++++++++++++++++++++++++++------ target/arm/tcg/translate-sme.c | 65 +++++++++++++----------- 3 files changed, 115 insertions(+), 45 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 3c8d7033dea..b803fff2ffa 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1748,6 +1748,11 @@ static inline bool isar_feature_aa64_sme2p2_or_sve2p= 2(const ARMISARegisters *id) return isar_feature_aa64_sme2p2(id) || isar_feature_aa64_sve2p2(id); } =20 +static inline bool isar_feature_aa64_sme2_sve_b16b16(const ARMISARegisters= *id) +{ + return isar_feature_aa64_sme2(id) && isar_feature_aa64_sve_b16b16(id); +} + static inline bool isar_feature_aa64_sme2_i16i64(const ARMISARegisters *id) { return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_i16i64(id); diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 36fbe24faf8..e1bef9987b0 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -227,6 +227,11 @@ UMOPA2_s 1010000 1 10 0 ..... ... ... ..... . 1= 0 .. @op_32 @z2z_4x1 ....... . esz:2 .. zm:4 ....1. ..... ...0 . \ &zzz_en n=3D4 zd=3D%zd_ax4 zn=3D%zd_ax4 =20 +@z2z_2x1_e0 ....... . .. .. zm:4 ....0. ..... .... . \ + &zzz_en esz=3D0 n=3D2 zd=3D%zd_ax2 zn=3D%zd_ax2 +@z2z_4x1_e0 ....... . .. .. zm:4 ....1. ..... ...0 . \ + &zzz_en esz=3D0 n=3D4 zd=3D%zd_ax4 zn=3D%zd_ax4 + SMAX_n1 1100000 1 .. 10 .... 1010.0 00000 .... 0 @z2z_2x1 SMAX_n1 1100000 1 .. 10 .... 1010.0 00000 .... 0 @z2z_4x1 UMAX_n1 1100000 1 .. 10 .... 1010.0 00000 .... 1 @z2z_2x1 @@ -236,14 +241,38 @@ SMIN_n1 1100000 1 .. 10 .... 1010.0 00001 ....= 0 @z2z_4x1 UMIN_n1 1100000 1 .. 10 .... 1010.0 00001 .... 1 @z2z_2x1 UMIN_n1 1100000 1 .. 10 .... 1010.0 00001 .... 1 @z2z_4x1 =20 -FMAX_n1 1100000 1 .. 10 .... 1010.0 01000 .... 0 @z2z_2x1 -FMAX_n1 1100000 1 .. 10 .... 1010.0 01000 .... 0 @z2z_4x1 -FMIN_n1 1100000 1 .. 10 .... 1010.0 01000 .... 1 @z2z_2x1 -FMIN_n1 1100000 1 .. 10 .... 1010.0 01000 .... 1 @z2z_4x1 -FMAXNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 0 @z2z_2x1 -FMAXNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 0 @z2z_4x1 -FMINNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 1 @z2z_2x1 -FMINNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 1 @z2z_4x1 +{ + BFMAX_n1 1100000 1 00 10 .... 1010.0 01000 .... 0 @z2z_2x1_e0 + FMAX_n1 1100000 1 .. 10 .... 1010.0 01000 .... 0 @z2z_2x1 +} +{ + BFMAX_n1 1100000 1 00 10 .... 1010.0 01000 .... 0 @z2z_4x1_e0 + FMAX_n1 1100000 1 .. 10 .... 1010.0 01000 .... 0 @z2z_4x1 +} +{ + BFMIN_n1 1100000 1 00 10 .... 1010.0 01000 .... 1 @z2z_2x1_e0 + FMIN_n1 1100000 1 .. 10 .... 1010.0 01000 .... 1 @z2z_2x1 +} +{ + BFMIN_n1 1100000 1 00 10 .... 1010.0 01000 .... 1 @z2z_4x1_e0 + FMIN_n1 1100000 1 .. 10 .... 1010.0 01000 .... 1 @z2z_4x1 +} +{ + BFMAXNM_n1 1100000 1 00 10 .... 1010.0 01001 .... 0 @z2z_2x1_e0 + FMAXNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 0 @z2z_2x1 +} +{ + BFMAXNM_n1 1100000 1 00 10 .... 1010.0 01001 .... 0 @z2z_4x1_e0 + FMAXNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 0 @z2z_4x1 +} +{ + BFMINNM_n1 1100000 1 00 10 .... 1010.0 01001 .... 1 @z2z_2x1_e0 + FMINNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 1 @z2z_2x1 +} +{ + BFMINNM_n1 1100000 1 00 10 .... 1010.0 01001 .... 1 @z2z_4x1_e0 + FMINNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 1 @z2z_4x1 +} =20 SRSHL_n1 1100000 1 .. 10 .... 1010.0 10001 .... 0 @z2z_2x1 SRSHL_n1 1100000 1 .. 10 .... 1010.0 10001 .... 0 @z2z_4x1 @@ -269,6 +298,11 @@ FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... = 0 @z2z_4x1 @z2z_4x4 ....... . esz:2 . ...00 ....1. ..... ...0 . \ &zzz_en n=3D4 zd=3D%zd_ax4 zn=3D%zd_ax4 zm=3D%zm_ax4 =20 +@z2z_2x2_e0 ....... . .. . ....0 ....0. ..... .... . \ + &zzz_en esz=3D0 n=3D2 zd=3D%zd_ax2 zn=3D%zd_ax2 zm=3D%zm_a= x2 +@z2z_4x4_e0 ....... . .. . ...00 ....1. ..... ...0 . \ + &zzz_en esz=3D0 n=3D4 zd=3D%zd_ax4 zn=3D%zd_ax4 zm=3D%zm_a= x4 + SMAX_nn 1100000 1 .. 1 ..... 1011.0 00000 .... 0 @z2z_2x2 SMAX_nn 1100000 1 .. 1 ..... 1011.0 00000 .... 0 @z2z_4x4 UMAX_nn 1100000 1 .. 1 ..... 1011.0 00000 .... 1 @z2z_2x2 @@ -278,14 +312,38 @@ SMIN_nn 1100000 1 .. 1 ..... 1011.0 00001 ....= 0 @z2z_4x4 UMIN_nn 1100000 1 .. 1 ..... 1011.0 00001 .... 1 @z2z_2x2 UMIN_nn 1100000 1 .. 1 ..... 1011.0 00001 .... 1 @z2z_4x4 =20 -FMAX_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 0 @z2z_2x2 -FMAX_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 0 @z2z_4x4 -FMIN_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 1 @z2z_2x2 -FMIN_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 1 @z2z_4x4 -FMAXNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 0 @z2z_2x2 -FMAXNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 0 @z2z_4x4 -FMINNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 1 @z2z_2x2 -FMINNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 1 @z2z_4x4 +{ + BFMAX_nn 1100000 1 00 1 ..... 1011.0 01000 .... 0 @z2z_2x2_e0 + FMAX_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 0 @z2z_2x2 +} +{ + BFMAX_nn 1100000 1 00 1 ..... 1011.0 01000 .... 0 @z2z_4x4_e0 + FMAX_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 0 @z2z_4x4 +} +{ + BFMIN_nn 1100000 1 00 1 ..... 1011.0 01000 .... 1 @z2z_2x2_e0 + FMIN_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 1 @z2z_2x2 +} +{ + BFMIN_nn 1100000 1 00 1 ..... 1011.0 01000 .... 1 @z2z_4x4_e0 + FMIN_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 1 @z2z_4x4 +} +{ + BFMAXNM_nn 1100000 1 00 1 ..... 1011.0 01001 .... 0 @z2z_2x2_e0 + FMAXNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 0 @z2z_2x2 +} +{ + BFMAXNM_nn 1100000 1 00 1 ..... 1011.0 01001 .... 0 @z2z_4x4_e0 + FMAXNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 0 @z2z_4x4 +} +{ + BFMINNM_nn 1100000 1 00 1 ..... 1011.0 01001 .... 1 @z2z_2x2_e0 + FMINNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 1 @z2z_2x2 +} +{ + BFMINNM_nn 1100000 1 00 1 ..... 1011.0 01001 .... 1 @z2z_4x4_e0 + FMINNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 1 @z2z_4x4 +} =20 SRSHL_nn 1100000 1 .. 1 ..... 1011.0 10001 .... 0 @z2z_2x2 SRSHL_nn 1100000 1 .. 1 ..... 1011.0 10001 .... 0 @z2z_4x4 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index ca88b3cdcc7..db1950f407b 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -747,20 +747,15 @@ TRANS_FEAT(URSHL_nn, aa64_sme2, do_zzz_nn, a, gen_sme= 2_urshl) TRANS_FEAT(SQDMULH_nn, aa64_sme2, do_zzz_nn, a, gen_gvec_sve2_sqdmulh) =20 static bool do_zzz_n1_fpst(DisasContext *s, arg_zzz_en *a, - gen_helper_gvec_3_ptr * const fns[4]) + gen_helper_gvec_3_ptr *fn) { int esz =3D a->esz, vsz, mofs; int overlap =3D -1; - gen_helper_gvec_3_ptr *fn =3D fns[esz]; TCGv_ptr fpst; =20 if (fn =3D=3D NULL) { return false; } - /* These insns use MO_8 to encode BFloat16. */ - if (esz =3D=3D MO_8 && !dc_isar_feature(aa64_sve_b16b16, s)) { - return false; - } if (!sme_sm_enabled_check(s)) { return true; } @@ -786,18 +781,14 @@ static bool do_zzz_n1_fpst(DisasContext *s, arg_zzz_e= n *a, } =20 static bool do_zzz_nn_fpst(DisasContext *s, arg_zzz_en *a, - gen_helper_gvec_3_ptr * const fns[4]) + gen_helper_gvec_3_ptr *fn) { int esz =3D a->esz, vsz; - gen_helper_gvec_3_ptr *fn =3D fns[esz]; TCGv_ptr fpst; =20 if (fn =3D=3D NULL) { return false; } - if (esz =3D=3D MO_8 && !dc_isar_feature(aa64_sve_b16b16, s)) { - return false; - } if (!sme_sm_enabled_check(s)) { return true; } @@ -816,48 +807,64 @@ static bool do_zzz_nn_fpst(DisasContext *s, arg_zzz_e= n *a, } =20 static gen_helper_gvec_3_ptr * const f_vector_fmax[2][4] =3D { - { gen_helper_gvec_fmax_b16, + { NULL, gen_helper_gvec_fmax_h, gen_helper_gvec_fmax_s, gen_helper_gvec_fmax_d }, - { gen_helper_gvec_ah_fmax_b16, + { NULL, gen_helper_gvec_ah_fmax_h, gen_helper_gvec_ah_fmax_s, gen_helper_gvec_ah_fmax_d }, }; -TRANS_FEAT(FMAX_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmax[s->fpcr_ah= ]) -TRANS_FEAT(FMAX_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmax[s->fpcr_ah= ]) +TRANS_FEAT(FMAX_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmax[s->fpcr_ah= ][a->esz]) +TRANS_FEAT(FMAX_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmax[s->fpcr_ah= ][a->esz]) +TRANS_FEAT(BFMAX_n1, aa64_sme2_sve_b16b16, do_zzz_n1_fpst, a, + s->fpcr_ah ? gen_helper_gvec_ah_fmax_b16 : gen_helper_gvec_fmax= _b16) +TRANS_FEAT(BFMAX_nn, aa64_sme2_sve_b16b16, do_zzz_nn_fpst, a, + s->fpcr_ah ? gen_helper_gvec_ah_fmax_b16 : gen_helper_gvec_fmax= _b16) =20 static gen_helper_gvec_3_ptr * const f_vector_fmin[2][4] =3D { - { gen_helper_gvec_fmin_b16, + { NULL, gen_helper_gvec_fmin_h, gen_helper_gvec_fmin_s, gen_helper_gvec_fmin_d }, - { gen_helper_gvec_ah_fmin_b16, + { NULL, gen_helper_gvec_ah_fmin_h, gen_helper_gvec_ah_fmin_s, gen_helper_gvec_ah_fmin_d }, }; -TRANS_FEAT(FMIN_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmin[s->fpcr_ah= ]) -TRANS_FEAT(FMIN_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmin[s->fpcr_ah= ]) +TRANS_FEAT(FMIN_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmin[s->fpcr_ah= ][a->esz]) +TRANS_FEAT(FMIN_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmin[s->fpcr_ah= ][a->esz]) +TRANS_FEAT(BFMIN_n1, aa64_sme2_sve_b16b16, do_zzz_n1_fpst, a, + s->fpcr_ah ? gen_helper_gvec_ah_fmin_b16 : gen_helper_gvec_fmin= _b16) +TRANS_FEAT(BFMIN_nn, aa64_sme2_sve_b16b16, do_zzz_nn_fpst, a, + s->fpcr_ah ? gen_helper_gvec_ah_fmin_b16 : gen_helper_gvec_fmin= _b16) =20 static gen_helper_gvec_3_ptr * const f_vector_fmaxnm[4] =3D { - gen_helper_gvec_fmaxnum_b16, + NULL, gen_helper_gvec_fmaxnum_h, gen_helper_gvec_fmaxnum_s, gen_helper_gvec_fmaxnum_d, }; -TRANS_FEAT(FMAXNM_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmaxnm) -TRANS_FEAT(FMAXNM_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmaxnm) +TRANS_FEAT(FMAXNM_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmaxnm[a->esz= ]) +TRANS_FEAT(FMAXNM_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmaxnm[a->esz= ]) +TRANS_FEAT(BFMAXNM_n1, aa64_sme2_sve_b16b16, do_zzz_n1_fpst, a, + gen_helper_gvec_fmaxnum_b16) +TRANS_FEAT(BFMAXNM_nn, aa64_sme2_sve_b16b16, do_zzz_nn_fpst, a, + gen_helper_gvec_fmaxnum_b16) =20 static gen_helper_gvec_3_ptr * const f_vector_fminnm[4] =3D { - gen_helper_gvec_fminnum_b16, + NULL, gen_helper_gvec_fminnum_h, gen_helper_gvec_fminnum_s, gen_helper_gvec_fminnum_d, }; -TRANS_FEAT(FMINNM_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fminnm) -TRANS_FEAT(FMINNM_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fminnm) +TRANS_FEAT(FMINNM_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fminnm[a->esz= ]) +TRANS_FEAT(FMINNM_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fminnm[a->esz= ]) +TRANS_FEAT(BFMINNM_n1, aa64_sme2_sve_b16b16, do_zzz_n1_fpst, a, + gen_helper_gvec_fminnum_b16) +TRANS_FEAT(BFMINNM_nn, aa64_sme2_sve_b16b16, do_zzz_nn_fpst, a, + gen_helper_gvec_fminnum_b16) =20 static gen_helper_gvec_3_ptr * const f_vector_famax[4] =3D { NULL, @@ -865,7 +872,7 @@ static gen_helper_gvec_3_ptr * const f_vector_famax[4] = =3D { gen_helper_gvec_famax_s, gen_helper_gvec_famax_d, }; -TRANS_FEAT(FAMAX_nn, aa64_sme2_faminmax, do_zzz_nn_fpst, a, f_vector_famax) +TRANS_FEAT(FAMAX_nn, aa64_sme2_faminmax, do_zzz_nn_fpst, a, f_vector_famax= [a->esz]) =20 static gen_helper_gvec_3_ptr * const f_vector_famin[4] =3D { NULL, @@ -873,7 +880,7 @@ static gen_helper_gvec_3_ptr * const f_vector_famin[4] = =3D { gen_helper_gvec_famin_s, gen_helper_gvec_famin_d, }; -TRANS_FEAT(FAMIN_nn, aa64_sme2_faminmax, do_zzz_nn_fpst, a, f_vector_famin) +TRANS_FEAT(FAMIN_nn, aa64_sme2_faminmax, do_zzz_nn_fpst, a, f_vector_famin= [a->esz]) =20 static gen_helper_gvec_3_ptr * const f_vector_fscale[4] =3D { NULL, @@ -881,8 +888,8 @@ static gen_helper_gvec_3_ptr * const f_vector_fscale[4]= =3D { gen_helper_gvec_fscale_s, gen_helper_gvec_fscale_d, }; -TRANS_FEAT(FSCALE_n1, aa64_sme2_f8cvt, do_zzz_n1_fpst, a, f_vector_fscale) -TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_zzz_nn_fpst, a, f_vector_fscale) +TRANS_FEAT(FSCALE_n1, aa64_sme2_f8cvt, do_zzz_n1_fpst, a, f_vector_fscale[= a->esz]) +TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_zzz_nn_fpst, a, f_vector_fscale[= a->esz]) =20 /* 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Tue, 01 Sep 2026 06:18:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/58] target/arm: Implement FMUL (multiple/multiple and single vectors) Date: Tue, 1 Sep 2026 14:17:11 +0100 Message-ID: <20260901131732.2263947-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269018982158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260826174213.614571-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 15 ++++++++++++--- target/arm/tcg/translate-sme.c | 9 +++++++++ 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index e1bef9987b0..60c7cacc10e 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -219,6 +219,8 @@ UMOPA2_s 1010000 1 10 0 ..... ... ... ..... . 10= .. @op_32 =20 %zd_ax2 1:4 !function=3Dtimes_2 %zd_ax4 2:3 !function=3Dtimes_4 +%zn_ax2 6:4 !function=3Dtimes_2 +%zn_ax4 7:3 !function=3Dtimes_4 =20 &zzz_en zd zn zm esz n =20 @@ -288,6 +290,11 @@ SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... = 0 @z2z_4x1 FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_2x1 FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_4x1 =20 +FMUL_n1 1100000 1 esz:2 1 zm:4 0 111010 ....0 ....0 \ + &zzz_en n=3D2 zd=3D%zd_ax2 zn=3D%zn_ax2 +FMUL_n1 1100000 1 esz:2 1 zm:4 1 111010 ...00 ...00 \ + &zzz_en n=3D4 zd=3D%zd_ax4 zn=3D%zn_ax4 + ### SME2 Multi-vector Multiple Vectors SVE Destructive =20 %zm_ax2 17:4 !function=3Dtimes_2 @@ -361,6 +368,11 @@ FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... = 1 @z2z_4x4 FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_2x2 FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_4x4 =20 +FMUL_nn 1100000 1 esz:2 1 ....0 111001 ....0 ....0 \ + &zzz_en n=3D2 zd=3D%zd_ax2 zn=3D%zn_ax2 zm=3D%zm_ax2 +FMUL_nn 1100000 1 esz:2 1 ...01 111001 ...00 ...00 \ + &zzz_en n=3D4 zd=3D%zd_ax4 zn=3D%zn_ax4 zm=3D%zm_ax4 + ### SME2 Multi-vector Multiple and Single Array Vectors =20 &azz_n n off rv zn zm @@ -521,9 +533,6 @@ FDOT_n1_hb 11000001 001 1 .... 0 .. 100 ..... 01 .= .. @azz_nx1_o3 n=3D4 =20 ### SME2 Multi-vector Multiple Array Vectors =20 -%zn_ax2 6:4 !function=3Dtimes_2 -%zn_ax4 7:3 !function=3Dtimes_4 - @azz_2x2_o3 ........ ... ..... . .. ... ..... .. off:3 \ &azz_n n=3D2 rv=3D%mova_rv zn=3D%zn_ax2 zm=3D%zm_ax2 @azz_4x4_o3 ........ ... ..... . .. ... ..... .. off:3 \ diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index db1950f407b..463754b057f 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -891,6 +891,15 @@ static gen_helper_gvec_3_ptr * const f_vector_fscale[4= ] =3D { TRANS_FEAT(FSCALE_n1, aa64_sme2_f8cvt, do_zzz_n1_fpst, a, f_vector_fscale[= a->esz]) TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_zzz_nn_fpst, a, f_vector_fscale[= a->esz]) =20 +static gen_helper_gvec_3_ptr * const f_vector_fmul[4] =3D { + NULL, + gen_helper_gvec_fmul_h, + gen_helper_gvec_fmul_s, + gen_helper_gvec_fmul_d, +}; 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 2 ++ linux-user/aarch64/elfload.c | 2 ++ target/arm/tcg/cpu64.c | 5 +++-- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index e342ebb4445..862341933ac 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -180,6 +180,7 @@ the following architecture extensions: - FEAT_SME (Scalable Matrix Extension) - FEAT_SME2 (Scalable Matrix Extension version 2) - FEAT_SME2p1 (Scalable Matrix Extension version 2.1) +- FEAT_SME2p2 (Scalable Matrix Extension version 2.2) - FEAT_SME_B16B16 (Non-widening BFloat16 arithmetic for SME2) - FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) - FEAT_SME_F16F16 (Non-widening half-precision FP16 arithmetic for SME2) @@ -204,6 +205,7 @@ the following architecture extensions: - FEAT_SVE_SM4 (Scalable Vector SM4 instructions) - FEAT_SVE2 (Scalable Vector Extension version 2) - FEAT_SVE2p1 (Scalable Vector Extension version 2.1) +- FEAT_SVE2p2 (Scalable Vector Extension version 2.2) - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2) diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index 48be49580a2..c086548f7fd 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -178,6 +178,8 @@ abi_ulong get_elf_hwcap(CPUState *cs) GET_FEATURE_ID(aa64_fprcvt, ARM_HWCAP_A64_FPRCVT); GET_FEATURE_ID(aa64_sme_mop4, ARM_HWCAP_A64_SME_SMOP4); GET_FEATURE_ID(aa64_sme_tmop, ARM_HWCAP_A64_SME_STMOP); + GET_FEATURE_ID(aa64_sve2p2, ARM_HWCAP_A64_SVE2P2); + GET_FEATURE_ID(aa64_sme2p2, ARM_HWCAP_A64_SME2P2); =20 return hwcaps; } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 2d48b736bc7..12270b42977 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1470,8 +1470,9 @@ void aarch64_max_v9_tcg_initfn(Object *obj) SET_IDREG(isar, ID_AA64MMFR4, t); =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* v9.2: FEAT_SVE2p1 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 3); /* v9.4: FEAT_SVE2p2 */ t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMUL= L128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, ELTPERM, 1); /* v9.4: FEAT_SVE2p2 */ t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitP= erm */ t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* v9.2: FEAT_SVE_B16B= 16 */ t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3= */ @@ -1498,7 +1499,7 @@ void aarch64_max_v9_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I32, 5); /* v9.2: FEAT_SME2 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* v9.2: FEAT_SME_F64F= 64 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* v9.2: FEAT_SME_I16I= 64 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 2); /* v9.2: FEAT_SME2p1 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 3); /* v9.4: FEAT_SME2p2 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, LUTv2, 1); /* v9.2: FEAT_SME_LUTv= 2 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* v9.2: FEAT_SME_FA64= */ SET_IDREG(isar, ID_AA64SMFR0, t); --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-sve.c | 67 +++++++++++++++++++++++++++------- 1 file changed, 54 insertions(+), 13 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 0becef16a94..7e0b47412ba 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4425,13 +4425,6 @@ TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_f= pst_arg_zzz, *** SVE Floating Point Arithmetic - Predicated Group */ =20 -#define DO_ZPZZ_FP(NAME, FEAT, name) \ - static gen_helper_gvec_4_ptr * const name##_zpzz_fns[4] =3D { \ - NULL, gen_helper_##name##_h, \ - gen_helper_##name##_s, gen_helper_##name##_d \ - }; \ - TRANS_FEAT(NAME, FEAT, gen_gvec_fpst_arg_zpzz, name##_zpzz_fns[a->esz]= , a) - #define DO_ZPZZ_AH_FP(NAME, FEAT, name, ah_name) \ static gen_helper_gvec_4_ptr * const name##_zpzz_fns[4] =3D { \ NULL, gen_helper_##name##_h, \ @@ -4474,9 +4467,33 @@ DO_ZPZZ_AH_FP_B16(FMAX_zpzz, aa64_sme_or_sve, sve_fm= ax, sve_ah_fmax) DO_ZPZZ_FP_B16(FMINNM_zpzz, aa64_sme_or_sve, sve_fminnum) DO_ZPZZ_FP_B16(FMAXNM_zpzz, aa64_sme_or_sve, sve_fmaxnum) DO_ZPZZ_AH_FP(FABD, aa64_sme_or_sve, sve_fabd, sve_ah_fabd) -DO_ZPZZ_FP(FSCALE, aa64_sme_or_sve, sve_fscalbn) -DO_ZPZZ_FP(FDIV, aa64_sme_or_sve, sve_fdiv) -DO_ZPZZ_FP(FMULX, aa64_sme_or_sve, sve_fmulx) + +static gen_helper_gvec_4_ptr * const sve_fscalbn_zpzz_fns[4] =3D { + NULL, + gen_helper_sve_fscalbn_h, + gen_helper_sve_fscalbn_s, + gen_helper_sve_fscalbn_d, +}; +TRANS_FEAT(FSCALE, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, + sve_fscalbn_zpzz_fns[a->esz], a) + +static gen_helper_gvec_4_ptr * const sve_fdiv_zpzz_fns[4] =3D { + NULL, + gen_helper_sve_fdiv_h, + gen_helper_sve_fdiv_s, + gen_helper_sve_fdiv_d, +}; +TRANS_FEAT(FDIV, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, + sve_fdiv_zpzz_fns[a->esz], a) + +static gen_helper_gvec_4_ptr * const sve_fmulx_zpzz_fns[4] =3D { + NULL, + gen_helper_sve_fmulx_h, + gen_helper_sve_fmulx_s, + gen_helper_sve_fmulx_d, +}; +TRANS_FEAT(FMULX, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, + sve_fmulx_zpzz_fns[a->esz], a) =20 static gen_helper_gvec_4_ptr * const sve2_famax_zpzz_fns[4] =3D { NULL, @@ -8067,9 +8084,33 @@ TRANS_FEAT_NONSTREAMING(HISTCNT, aa64_sve2, gen_gvec= _ool_arg_zpzz, TRANS_FEAT_NONSTREAMING(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz, a->esz =3D=3D 0 ? gen_helper_sve2_histseg : NULL, = a, 0) =20 -DO_ZPZZ_FP(FADDP, aa64_sme_or_sve2, sve2_faddp_zpzz) -DO_ZPZZ_FP(FMAXNMP, aa64_sme_or_sve2, sve2_fmaxnmp_zpzz) -DO_ZPZZ_FP(FMINNMP, aa64_sme_or_sve2, sve2_fminnmp_zpzz) +static gen_helper_gvec_4_ptr * const sve_faddp_zpzz_fns[4] =3D { + NULL, + gen_helper_sve2_faddp_zpzz_h, + gen_helper_sve2_faddp_zpzz_s, + gen_helper_sve2_faddp_zpzz_d, +}; +TRANS_FEAT(FADDP, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpzz, + sve_faddp_zpzz_fns[a->esz], a) + +static gen_helper_gvec_4_ptr * const sve_fmaxnmp_zpzz_fns[4] =3D { + NULL, + gen_helper_sve2_fmaxnmp_zpzz_h, + gen_helper_sve2_fmaxnmp_zpzz_s, + gen_helper_sve2_fmaxnmp_zpzz_d, +}; +TRANS_FEAT(FMAXNMP, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpzz, + sve_fmaxnmp_zpzz_fns[a->esz], a) + +static gen_helper_gvec_4_ptr * const sve_fminnmp_zpzz_fns[4] =3D { + NULL, + gen_helper_sve2_fminnmp_zpzz_h, + gen_helper_sve2_fminnmp_zpzz_s, + gen_helper_sve2_fminnmp_zpzz_d, +}; +TRANS_FEAT(FMINNMP, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpzz, + sve_fminnmp_zpzz_fns[a->esz], a) + DO_ZPZZ_AH_FP(FMAXP, aa64_sme_or_sve2, sve2_fmaxp_zpzz, sve2_ah_fmaxp_zpzz) DO_ZPZZ_AH_FP(FMINP, aa64_sme_or_sve2, sve2_fminp_zpzz, sve2_ah_fminp_zpzz) =20 --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788269104; cv=none; d=zohomail.com; s=zohoarc; b=lsLSVkYthVUYmDFS6tSE4O40ABtH9Z2vX7KGvbHZFjU7iVMXgwfgliOrZ+QBv3RFeINFPdwWFvw6DTDG25gZui3ieIifuW4xhfe6vhj3S4hG4hWdgsSk/mDXS3UFNkD1o58xAxCuXxcRSouzlpSXcAvY7gpGi9/tmgisQT/MAFk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788269104; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=SwN7fvVZ8M13AiEa1TXkKrudgvk3fc/1walmMso5UkI=; b=jYumpMzQKPXDk+4lEdmNaex+k4BeqbjiZECOaKI0K+8avBrjrIdVjb5+toBVTbXgvsT14BDoQvL+5nPHI97UqwwyvBYuvnt8rMUsJ3diJwCENP5muI1K+YMUowCSPbsZ4xqYE2jFo6QFY2x570xGnrp4lyYKACQOXt5KIY0YQKA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788269104258210.13304230234291; Tue, 1 Sep 2026 06:25:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONa-0001EK-Hl; Tue, 01 Sep 2026 09:18:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ONV-0001CK-JJ for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:17 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ONT-0007Iw-DR for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:17 -0400 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-c207cb16cf5so786087866b.1 for ; Tue, 01 Sep 2026 06:18:15 -0700 (PDT) Received: from lanath.. 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-sve.c | 59 ++++++++++++++++++++++++++-------- 1 file changed, 46 insertions(+), 13 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 7e0b47412ba..347eeb4602e 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4438,14 +4438,6 @@ TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_f= pst_arg_zzz, s->fpcr_ah ? name##_ah_zpzz_fns[a->esz] : \ name##_zpzz_fns[a->esz], a) =20 -/* Similar, but for insns where sz =3D=3D 0 encodes bfloat16 */ -#define DO_ZPZZ_FP_B16(NAME, FEAT, name) \ - static gen_helper_gvec_4_ptr * const name##_zpzz_fns[4] =3D { \ - gen_helper_##name##_b16, gen_helper_##name##_h, \ - gen_helper_##name##_s, gen_helper_##name##_d \ - }; \ - TRANS_FEAT(NAME, FEAT, gen_gvec_fpst_arg_zpzz, name##_zpzz_fns[a->esz]= , a) - #define DO_ZPZZ_AH_FP_B16(NAME, FEAT, name, ah_name) \ static gen_helper_gvec_4_ptr * const name##_zpzz_fns[4] =3D { \ gen_helper_##name##_b16, gen_helper_##name##_h, \ @@ -4459,13 +4451,54 @@ TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_= fpst_arg_zzz, s->fpcr_ah ? name##_ah_zpzz_fns[a->esz] : \ name##_zpzz_fns[a->esz], a) =20 -DO_ZPZZ_FP_B16(FADD_zpzz, aa64_sme_or_sve, sve_fadd) -DO_ZPZZ_FP_B16(FSUB_zpzz, aa64_sme_or_sve, sve_fsub) -DO_ZPZZ_FP_B16(FMUL_zpzz, aa64_sme_or_sve, sve_fmul) +static gen_helper_gvec_4_ptr * const sve_fadd_zpzz_fns[4] =3D { + gen_helper_sve_fadd_b16, + gen_helper_sve_fadd_h, + gen_helper_sve_fadd_s, + gen_helper_sve_fadd_d +}; +TRANS_FEAT(FADD_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, + sve_fadd_zpzz_fns[a->esz], a) + +static gen_helper_gvec_4_ptr * const sve_fsub_zpzz_fns[4] =3D { + gen_helper_sve_fsub_b16, + gen_helper_sve_fsub_h, + gen_helper_sve_fsub_s, + gen_helper_sve_fsub_d +}; +TRANS_FEAT(FSUB_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, + sve_fsub_zpzz_fns[a->esz], a) + +static gen_helper_gvec_4_ptr * const sve_fmul_zpzz_fns[4] =3D { + gen_helper_sve_fmul_b16, + gen_helper_sve_fmul_h, + gen_helper_sve_fmul_s, + gen_helper_sve_fmul_d +}; +TRANS_FEAT(FMUL_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, + sve_fmul_zpzz_fns[a->esz], a) + DO_ZPZZ_AH_FP_B16(FMIN_zpzz, aa64_sme_or_sve, sve_fmin, sve_ah_fmin) DO_ZPZZ_AH_FP_B16(FMAX_zpzz, aa64_sme_or_sve, sve_fmax, sve_ah_fmax) -DO_ZPZZ_FP_B16(FMINNM_zpzz, aa64_sme_or_sve, sve_fminnum) -DO_ZPZZ_FP_B16(FMAXNM_zpzz, aa64_sme_or_sve, sve_fmaxnum) + +static gen_helper_gvec_4_ptr * const sve_fmaxnum_fns[4] =3D { + gen_helper_sve_fmaxnum_b16, + gen_helper_sve_fmaxnum_h, + gen_helper_sve_fmaxnum_s, + gen_helper_sve_fmaxnum_d +}; +TRANS_FEAT(FMAXNM_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, + sve_fmaxnum_fns[a->esz], a) + +static gen_helper_gvec_4_ptr * const sve_fminnum_fns[4] =3D { + gen_helper_sve_fminnum_b16, + gen_helper_sve_fminnum_h, + gen_helper_sve_fminnum_s, + gen_helper_sve_fminnum_d +}; +TRANS_FEAT(FMINNM_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, + sve_fminnum_fns[a->esz], a) + DO_ZPZZ_AH_FP(FABD, aa64_sme_or_sve, sve_fabd, sve_ah_fabd) =20 static gen_helper_gvec_4_ptr * const sve_fscalbn_zpzz_fns[4] =3D { --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268815; cv=none; d=zohomail.com; s=zohoarc; b=hwU2akhrNY+f2kX4M9pzWV2lot4D0feFcybvrZhBqiCFila2B4Yo8oxSNxPmd2661Oy3IET9ArQp/DkrjFK4xze7zUBA/gblUDkir9XUap7ExUlRTeBTyD2jn8qSzrSA+2Q8Ik37DgR2EvgrgL7bUAQrXzy2mTnO0N211CmP2oQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268815; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=1ImiUh1kTDR8eHJXplIXTJFDbp7qOBySF2XtCDZMRgM=; b=Pj5uiADXy+Yi4GT7sz/SXx85+RELUhg8+2CIocR/tAtTkvAy8kVyOLmm16cTRsTNlmHR+W6FQv+SPcxg+mBSN/8usdSaMjRUuT2VWlZtkIs7G3euLBTIVvIytoVu89rX0TA7WKBLf1oh7jzJY0CX4S/zAME6H3hLqLLTUbZmeE4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268815788134.50101688837572; Tue, 1 Sep 2026 06:20:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONY-0001Cw-1p; Tue, 01 Sep 2026 09:18:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ONW-0001CX-5H for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:18 -0400 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ONU-0007JY-D5 for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:17 -0400 Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-c15e2dab83eso164200666b.1 for ; Tue, 01 Sep 2026 06:18:16 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee2853dsm617907466b.18.2026.09.01.06.18.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:18:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1788268695; x=1788873495; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=1ImiUh1kTDR8eHJXplIXTJFDbp7qOBySF2XtCDZMRgM=; b=E4eADEtkYhutztpsRP2M5nI6YEGBIFFWGzEe7/49BUwzJr8p7K7bmtNihUvMjU9dxd tWEiJtPARyjmE8PPzLRiBmp3AYdPhPELN1E4XKt0odhOKLzVx7A5awaETj6RTFWNiQiV /wxUTTGVEl6y1zjxqOIVEmvPgFw3L9o1PYDmdLT+gy009z+KVZ4ruHXT6A8T8hKsVLYI 947pVHgPhbMaCHFd/LSmtCqRCesClrMWsq+c4TxEPUWqP06cwovvSs+/ABWnPMMHHV7B d5502rasTGO3zVli0t7ClDGqjRntmcB6DKe/PSu1jNxGt334btdGcDpS++skLYRif5au Nnow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788268695; x=1788873495; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=1ImiUh1kTDR8eHJXplIXTJFDbp7qOBySF2XtCDZMRgM=; b=FHZXjTwJvzWXGbiPeG5s8LGSGdl2U6N61+sTem8WNHwQFefrbp42jUdjMUYt5rrHiB x1UhgHrH9O3Sd/pddxOyNmkTPa9RiSRbcf+EkPOoojTcJBR0Tc3fOFrRw0WDQ23QGLXc rWTcIIjUy+fS6lwgxwqHM66wx3ku0X0iAD/wt+3smZ0To+LTKW5Wn9QDepOYdXhLqcMC wyfkjupufFo62P5omMhyZq521scZwKRDICbs3ZKS+XfgWSbRcZCG38rZeJ0jyphAJ4AP yytv1B1QCVU9XDxM0wIl3dUemdhy+LmLGbmOld1ypL75twlRaErHDU5fS2K0N3bFthdk CY9g== X-Gm-Message-State: AFuF++lDrD7DXSoG527RXXRfY0240zWp+H1upcaZd0bVn7Z9MSRfJGjP 6ECxVG+Lwwi6fN64FwgJs8xzJRd89FccUiiJOSEvyi3mDXGMEfJ9WG30PBokLVcX+m0ftKKO0pS +WsvWiQg= X-Gm-Gg: AR+sD11488OSBbGcAQmG7iDh9SdyzSG28T5Qw2IIt6nEnX9FyUFqQKJevL3QzeprlJy bfChj9WU0QYfOWhNMgK8l+Bf7tbuQsoQsMwuq5lW2SLEYxsWOjqNaw2LdwvMujlEAX9NlfeyNq4 2dTY4ju/2gPRTZsO/CM70tJu02JJ+eJ1Muf1+CZz7UrshPSIdK+k7I6SfMxRcINT/ZsGaHL4LF7 fc8F97A6TEy4T6NC703ERVCBlxh2REJ3hBk8UX+sj0V1jH6cyaCej9AWi8yHOFra67ukgNmPfuL Ra7RMT/R+6nwbSKwKZdzE0gdKOtNSfGVga7YbKRtRznO2zCbJVbL+4dnzYMGudkcpBmFgPjuhVp tpzIv7Vujbs25eFihHL11KgO1MBpVJDWbF0TcFqnsZnpPafwlN/iSGeEr1qn9v5I69Tm+UeCu8t rC1g9QZrSGctwW3aDD1nOVL0QZSUPM2hOvBHrS+2OE66sa4lvK9Ow68Uy1rYr/xyB9JYjg/ha5x QqOjDZDl1pT3laLfgHkO3CjSsSe/XBx+pFZlYydcRMehwX/7hsChG7m64vWrkxDA0ltDw== X-Received: by 2002:a17:907:c02:b0:c25:4612:2efd with SMTP id a640c23a62f3a-c2557167f51mr2170655266b.9.1788268694879; Tue, 01 Sep 2026 06:18:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/58] target/arm: Remove DO_ZPZZ_AH_FP from translate-sme.c Date: Tue, 1 Sep 2026 14:17:15 +0100 Message-ID: <20260901131732.2263947-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268817620158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Expand the macro at each use site. Merge the two arrays and index by fpcr_ah. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-sve.c | 41 +++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 347eeb4602e..6e984d02f82 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4425,19 +4425,6 @@ TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_f= pst_arg_zzz, *** SVE Floating Point Arithmetic - Predicated Group */ =20 -#define DO_ZPZZ_AH_FP(NAME, FEAT, name, ah_name) \ - static gen_helper_gvec_4_ptr * const name##_zpzz_fns[4] =3D { \ - NULL, gen_helper_##name##_h, \ - gen_helper_##name##_s, gen_helper_##name##_d \ - }; \ - static gen_helper_gvec_4_ptr * const name##_ah_zpzz_fns[4] =3D { \ - NULL, gen_helper_##ah_name##_h, \ - gen_helper_##ah_name##_s, gen_helper_##ah_name##_d \ - }; \ - TRANS_FEAT(NAME, FEAT, gen_gvec_fpst_arg_zpzz, \ - s->fpcr_ah ? name##_ah_zpzz_fns[a->esz] : \ - name##_zpzz_fns[a->esz], a) - #define DO_ZPZZ_AH_FP_B16(NAME, FEAT, name, ah_name) \ static gen_helper_gvec_4_ptr * const name##_zpzz_fns[4] =3D { \ gen_helper_##name##_b16, gen_helper_##name##_h, \ @@ -4499,7 +4486,14 @@ static gen_helper_gvec_4_ptr * const sve_fminnum_fns= [4] =3D { TRANS_FEAT(FMINNM_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, sve_fminnum_fns[a->esz], a) =20 -DO_ZPZZ_AH_FP(FABD, aa64_sme_or_sve, sve_fabd, sve_ah_fabd) +static gen_helper_gvec_4_ptr * const sve_fabd_zpzz_fns[4][2] =3D { + { NULL, NULL }, + { gen_helper_sve_fabd_h, gen_helper_sve_ah_fabd_h }, + { gen_helper_sve_fabd_s, gen_helper_sve_ah_fabd_s }, + { gen_helper_sve_fabd_d, gen_helper_sve_ah_fabd_d }, +}; +TRANS_FEAT(FABD, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, + sve_fabd_zpzz_fns[a->esz][s->fpcr_ah], a) =20 static gen_helper_gvec_4_ptr * const sve_fscalbn_zpzz_fns[4] =3D { NULL, @@ -8144,8 +8138,23 @@ static gen_helper_gvec_4_ptr * const sve_fminnmp_zpz= z_fns[4] =3D { TRANS_FEAT(FMINNMP, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpzz, sve_fminnmp_zpzz_fns[a->esz], a) =20 -DO_ZPZZ_AH_FP(FMAXP, aa64_sme_or_sve2, sve2_fmaxp_zpzz, sve2_ah_fmaxp_zpzz) -DO_ZPZZ_AH_FP(FMINP, aa64_sme_or_sve2, sve2_fminp_zpzz, sve2_ah_fminp_zpzz) +static gen_helper_gvec_4_ptr * const sve_fmaxp_zpzz_fns[4][2] =3D { + { NULL, NULL }, + { gen_helper_sve2_fmaxp_zpzz_h, gen_helper_sve2_ah_fmaxp_zpzz_h }, + { gen_helper_sve2_fmaxp_zpzz_s, gen_helper_sve2_ah_fmaxp_zpzz_s }, + { gen_helper_sve2_fmaxp_zpzz_d, gen_helper_sve2_ah_fmaxp_zpzz_d }, +}; +TRANS_FEAT(FMAXP, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, + sve_fmaxp_zpzz_fns[a->esz][s->fpcr_ah], a) + +static gen_helper_gvec_4_ptr * const sve_fminp_zpzz_fns[4][2] =3D { + { NULL, NULL }, + { gen_helper_sve2_fminp_zpzz_h, gen_helper_sve2_ah_fminp_zpzz_h }, + { gen_helper_sve2_fminp_zpzz_s, gen_helper_sve2_ah_fminp_zpzz_s }, + { gen_helper_sve2_fminp_zpzz_d, gen_helper_sve2_ah_fminp_zpzz_d }, +}; +TRANS_FEAT(FMINP, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, + sve_fminp_zpzz_fns[a->esz][s->fpcr_ah], a) =20 static bool do_fmmla(DisasContext *s, arg_rrrr_esz *a, gen_helper_gvec_4_ptr *fn) --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268934; cv=none; d=zohomail.com; s=zohoarc; b=jrCvndbwXypp6C4xuImnficgXRkqAro9zNOj05gqsuTjXruARXqtDwhLUcbR3lW7ae1r9gdspzVpKoRHTqyoF093UTNqFFOXfOP1YOIA2Txx10dscVAr2PTUPiicx3ZB/BEaFXXkaKpNP4RvnMCKHYTyobhU4dnRcLXONzRETGY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268934; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=YSrvZ4Rhcw1n3WZsHzE3E0qS5jCZCm+NTt1dWv0DclQ=; b=a2UxbCJjlaewJs0NRsbajJmYkLOW4a7VgzCB8QweAbTgQOm036x1S/RzayqgDASSeP73YWcgV5rXVd02ftNSwB+YTUQV5YAvK6yXsGz/wTC+qwfWhNVJtf6xT5W4kwZ9JaPvvcKls4l5dFole3CtngbODtOt1R88ikK5mLKktQE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268934169888.98141047905; Tue, 1 Sep 2026 06:22:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONZ-0001Dv-FW; Tue, 01 Sep 2026 09:18:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ONX-0001Ct-0R for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:19 -0400 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ONV-0007Ju-Df for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:18 -0400 Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-c15e592da74so567781866b.1 for ; Tue, 01 Sep 2026 06:18:17 -0700 (PDT) Received: from lanath.. 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Merge the two arrays and index by fpcr_ah. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-sve.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 6e984d02f82..f65c2b0af53 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4425,19 +4425,6 @@ TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_f= pst_arg_zzz, *** SVE Floating Point Arithmetic - Predicated Group */ =20 -#define DO_ZPZZ_AH_FP_B16(NAME, FEAT, name, ah_name) \ - static gen_helper_gvec_4_ptr * const name##_zpzz_fns[4] =3D { \ - gen_helper_##name##_b16, gen_helper_##name##_h, \ - gen_helper_##name##_s, gen_helper_##name##_d \ - }; \ - static gen_helper_gvec_4_ptr * const name##_ah_zpzz_fns[4] =3D { \ - gen_helper_##ah_name##_b16, gen_helper_##ah_name##_h, \ - gen_helper_##ah_name##_s, gen_helper_##ah_name##_d \ - }; \ - TRANS_FEAT(NAME, FEAT, gen_gvec_fpst_arg_zpzz, \ - s->fpcr_ah ? name##_ah_zpzz_fns[a->esz] : \ - name##_zpzz_fns[a->esz], a) - static gen_helper_gvec_4_ptr * const sve_fadd_zpzz_fns[4] =3D { gen_helper_sve_fadd_b16, gen_helper_sve_fadd_h, @@ -4465,8 +4452,23 @@ static gen_helper_gvec_4_ptr * const sve_fmul_zpzz_f= ns[4] =3D { TRANS_FEAT(FMUL_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, sve_fmul_zpzz_fns[a->esz], a) =20 -DO_ZPZZ_AH_FP_B16(FMIN_zpzz, aa64_sme_or_sve, sve_fmin, sve_ah_fmin) -DO_ZPZZ_AH_FP_B16(FMAX_zpzz, aa64_sme_or_sve, sve_fmax, sve_ah_fmax) +static gen_helper_gvec_4_ptr * const sve_fmin_fns[4][2] =3D { + { gen_helper_sve_fmin_b16, gen_helper_sve_ah_fmin_b16 }, + { gen_helper_sve_fmin_h, gen_helper_sve_ah_fmin_h }, + { gen_helper_sve_fmin_s, gen_helper_sve_ah_fmin_s }, + { gen_helper_sve_fmin_d, gen_helper_sve_ah_fmin_d }, +}; +TRANS_FEAT(FMIN_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, + sve_fmin_fns[a->esz][s->fpcr_ah], a) + +static gen_helper_gvec_4_ptr * const sve_fmax_fns[4][2] =3D { + { gen_helper_sve_fmax_b16, gen_helper_sve_ah_fmax_b16 }, + { gen_helper_sve_fmax_h, gen_helper_sve_ah_fmax_h }, + { gen_helper_sve_fmax_s, gen_helper_sve_ah_fmax_s }, + { gen_helper_sve_fmax_d, gen_helper_sve_ah_fmax_d }, +}; +TRANS_FEAT(FMAX_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, + sve_fmax_fns[a->esz][s->fpcr_ah], a) =20 static gen_helper_gvec_4_ptr * const sve_fmaxnum_fns[4] =3D { gen_helper_sve_fmaxnum_b16, --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788269088; cv=none; d=zohomail.com; s=zohoarc; b=HPxJeG6OSLArRh7R4/lFAgDYgsInMddSG42rZbU+KE4bcuFkL1NebKz9rtqX3KUh4vMnlk5KrVIQN626ZVp4m1DvM8iWRZl4nSHYmJ4EHH/dOGH4mx02JVO/lltQouuAUceZj/nzwLY68bjRwK4uxcZ1xwlzS5aaDlxopMyAcKc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788269088; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ck+G1J8XeMofV26XYg3w08XT7q7hGF82RVGXpKaMHQE=; b=OXIjKRUX3qFp1ufS90edA6NThTDHITIzUBVmAZr1/1D5KuXQCsSacVF9g5Q0nrauB7KZQ+EMp/FDluVd4tbC+H8B2uxDlo4T31asLv7B+UCr6FuvlDXegYSvk8Bb6PwDckUBoHK5GWiu9yf2ywl5BjD/k+YyO9W42EPuq0lh24A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788269088660994.8472538103016; Tue, 1 Sep 2026 06:24:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONa-0001El-VJ; Tue, 01 Sep 2026 09:18:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ONY-0001DP-AJ for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:20 -0400 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ONW-0007K6-AV for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:19 -0400 Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-c197e7e4e94so715295866b.2 for ; Tue, 01 Sep 2026 06:18:17 -0700 (PDT) Received: from lanath.. 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Tue, 01 Sep 2026 06:18:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/58] target/arm: Split decode of BFloat SVE FADD, FSUB, FMUL, FMIN*, FMAX* Date: Tue, 1 Sep 2026 14:17:17 +0100 Message-ID: <20260901131732.2263947-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269089393158501 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Split decode so that feature detection can be handled external to gen_gvec_fpst_arg_zpzz Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 38 +++++++++++++++++++++++++++------- target/arm/tcg/translate-sve.c | 32 ++++++++++++++++++---------- 2 files changed, 52 insertions(+), 18 deletions(-) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index bdc2b7f0c04..07dac681acf 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -159,6 +159,9 @@ @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz =20 +@rdn_pg_rm_e0 ........ .. ... ... ... pg:3 rm:5 rd:5 \ + &rprr_esz esz=3D0 rn=3D%reg_movprfx + # Three register operand, with governing predicate, vector element size @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ &rprrr_esz ra=3D%reg_movprfx @@ -1163,14 +1166,35 @@ FRSQRTS 01100101 .. 0 ..... 000 111 ..... .= .... @rd_rn_rm ### SVE FP Arithmetic Predicated Group =20 # SVE floating-point arithmetic (predicated) -FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm -FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm -FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm +{ + BFADD_zpzz 01100101 00 00 0000 100 ... ..... ..... @rdn_pg_rm_e0 + FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm +} +{ + BFSUB_zpzz 01100101 00 00 0001 100 ... ..... ..... @rdn_pg_rm_e0 + FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm +} +{ + BFMUL_zpzz 01100101 00 00 0010 100 ... ..... ..... @rdn_pg_rm_e0 + FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm +} FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FS= UBR -FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm -FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm -FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm -FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm +{ + BFMAXNM_zpzz 01100101 00 00 0100 100 ... ..... ..... @rdn_pg_rm_e0 + FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm +} +{ + BFMINNM_zpzz 01100101 00 00 0101 100 ... ..... ..... @rdn_pg_rm_e0 + FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm +} +{ + BFMAX_zpzz 01100101 00 00 0110 100 ... ..... ..... @rdn_pg_rm_e0 + FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm +} +{ + BFMIN_zpzz 01100101 00 00 0111 100 ... ..... ..... @rdn_pg_rm_e0 + FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm +} FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index f65c2b0af53..0ad0aff0504 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -412,10 +412,6 @@ static bool gen_gvec_fpst_zzzp(DisasContext *s, gen_he= lper_gvec_4_ptr *fn, static bool gen_gvec_fpst_arg_zpzz(DisasContext *s, gen_helper_gvec_4_ptr = *fn, arg_rprr_esz *a) { - /* These insns use MO_8 to encode BFloat16. */ - if (a->esz =3D=3D MO_8 && !dc_isar_feature(aa64_sve_b16b16, s)) { - return false; - } return gen_gvec_fpst_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A6= 4); } @@ -4426,65 +4422,79 @@ TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_= fpst_arg_zzz, */ =20 static gen_helper_gvec_4_ptr * const sve_fadd_zpzz_fns[4] =3D { - gen_helper_sve_fadd_b16, + NULL, gen_helper_sve_fadd_h, gen_helper_sve_fadd_s, gen_helper_sve_fadd_d }; +TRANS_FEAT(BFADD_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz, + gen_helper_sve_fadd_b16, a) TRANS_FEAT(FADD_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, sve_fadd_zpzz_fns[a->esz], a) =20 static gen_helper_gvec_4_ptr * const sve_fsub_zpzz_fns[4] =3D { - gen_helper_sve_fsub_b16, + NULL, gen_helper_sve_fsub_h, gen_helper_sve_fsub_s, gen_helper_sve_fsub_d }; +TRANS_FEAT(BFSUB_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz, + gen_helper_sve_fsub_b16, a) TRANS_FEAT(FSUB_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, sve_fsub_zpzz_fns[a->esz], a) =20 static gen_helper_gvec_4_ptr * const sve_fmul_zpzz_fns[4] =3D { - gen_helper_sve_fmul_b16, + NULL, gen_helper_sve_fmul_h, gen_helper_sve_fmul_s, gen_helper_sve_fmul_d }; +TRANS_FEAT(BFMUL_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz, + gen_helper_sve_fmul_b16, a) TRANS_FEAT(FMUL_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, sve_fmul_zpzz_fns[a->esz], a) =20 static gen_helper_gvec_4_ptr * const sve_fmin_fns[4][2] =3D { - { gen_helper_sve_fmin_b16, gen_helper_sve_ah_fmin_b16 }, + { NULL, NULL }, { gen_helper_sve_fmin_h, gen_helper_sve_ah_fmin_h }, { gen_helper_sve_fmin_s, gen_helper_sve_ah_fmin_s }, { gen_helper_sve_fmin_d, gen_helper_sve_ah_fmin_d }, }; +TRANS_FEAT(BFMIN_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz, + s->fpcr_ah ? gen_helper_sve_ah_fmin_b16 : gen_helper_sve_fmin_b= 16, a) TRANS_FEAT(FMIN_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, sve_fmin_fns[a->esz][s->fpcr_ah], a) =20 static gen_helper_gvec_4_ptr * const sve_fmax_fns[4][2] =3D { - { gen_helper_sve_fmax_b16, gen_helper_sve_ah_fmax_b16 }, + { NULL, NULL }, { gen_helper_sve_fmax_h, gen_helper_sve_ah_fmax_h }, { gen_helper_sve_fmax_s, gen_helper_sve_ah_fmax_s }, { gen_helper_sve_fmax_d, gen_helper_sve_ah_fmax_d }, }; +TRANS_FEAT(BFMAX_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz, + s->fpcr_ah ? gen_helper_sve_ah_fmax_b16 : gen_helper_sve_fmax_b= 16, a) TRANS_FEAT(FMAX_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, sve_fmax_fns[a->esz][s->fpcr_ah], a) =20 static gen_helper_gvec_4_ptr * const sve_fmaxnum_fns[4] =3D { - gen_helper_sve_fmaxnum_b16, + NULL, gen_helper_sve_fmaxnum_h, gen_helper_sve_fmaxnum_s, gen_helper_sve_fmaxnum_d }; +TRANS_FEAT(BFMAXNM_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz, + gen_helper_sve_fmaxnum_b16, a) TRANS_FEAT(FMAXNM_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, sve_fmaxnum_fns[a->esz], a) =20 static gen_helper_gvec_4_ptr * const sve_fminnum_fns[4] =3D { - gen_helper_sve_fminnum_b16, + NULL, gen_helper_sve_fminnum_h, gen_helper_sve_fminnum_s, gen_helper_sve_fminnum_d }; +TRANS_FEAT(BFMINNM_zpzz, aa64_sve_b16b16, gen_gvec_fpst_arg_zpzz, + gen_helper_sve_fminnum_b16, a) TRANS_FEAT(FMINNM_zpzz, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, sve_fminnum_fns[a->esz], a) =20 --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1788268963; cv=none; d=zohomail.com; s=zohoarc; b=A2BpOfzXR4UUEmE7qujRgY8Pe1pF3NnsbM6iUS6I1i7CHzqf1Y2gD6SfDC6xECve3/LGWbmFytfYsaB9WtmIebk7R8J/7FEAu92/ybuRJRhtkO4L/QRZ7XCM+BqvH+J8Cf4b/+P2CRFNcjSKKTUSAA69XKnAfGKZpbW+A59tQl0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788268963; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=uVPxQDhxI2au/Ew0b23LZPt7RptISjtkf7L0+V6de5Y=; b=J/A2ANNPOx4EwokhZ1SRTJe4OKUrm798EWCbiUTgHDynnk0B/d3s+kZJiyzUjJvP/fRPsnvmiazmYfD75YW2HHLyLXAy2r7X1SWdXW5+MXm1IC9RJ8jFXv7Aj1Ud/wLbK6RL/jYPKRd3+F6IgEh1PVYr7tLUsfD/FJhL6NkTEfc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788268963676890.2529672333571; Tue, 1 Sep 2026 06:22:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1ONZ-0001E8-RZ; Tue, 01 Sep 2026 09:18:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1ONY-0001Dj-Vb for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:20 -0400 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1ONX-0007KJ-7h for qemu-devel@nongnu.org; Tue, 01 Sep 2026 09:18:20 -0400 Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-c25366c9b42so102363666b.2 for ; Tue, 01 Sep 2026 06:18:18 -0700 (PDT) Received: from lanath.. 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Tue, 01 Sep 2026 06:18:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 44/58] target/arm: Implement SVE BFSCALE Date: Tue, 1 Sep 2026 14:17:18 +0100 Message-ID: <20260901131732.2263947-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268966524158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 5 +++++ target/arm/tcg/helper-sve-defs.h | 2 ++ target/arm/tcg/sve.decode | 5 ++++- target/arm/tcg/sve_helper.c | 1 + target/arm/tcg/translate-sve.c | 2 ++ 5 files changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index b803fff2ffa..60463a67431 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1585,6 +1585,11 @@ static inline bool isar_feature_aa64_sve_b16b16(cons= t ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16); } =20 +static inline bool isar_feature_aa64_sve_bfscale(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16) >=3D 2; +} + static inline bool isar_feature_aa64_ssve_fexpa(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SFEXPA); diff --git a/target/arm/tcg/helper-sve-defs.h b/target/arm/tcg/helper-sve-d= efs.h index 19bd936f6ef..f78e77662de 100644 --- a/target/arm/tcg/helper-sve-defs.h +++ b/target/arm/tcg/helper-sve-defs.h @@ -1303,6 +1303,8 @@ DEF_HELPER_FLAGS_6(sve_ah_fabd_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_ah_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32) =20 +DEF_HELPER_FLAGS_6(sve_fscalbn_b16, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_6(sve_fscalbn_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_6(sve_fscalbn_s, TCG_CALL_NO_RWG, diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 07dac681acf..ed19ae237f4 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1196,7 +1196,10 @@ FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..= ... @rdm_pg_rn # FSUBR FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm } FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm -FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm +{ + BFSCALE 01100101 00 00 1001 100 ... ..... ..... @rdn_pg_rm_e0 + FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm +} FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FD= IVR FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index ac96b18784f..8389dce6299 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -4827,6 +4827,7 @@ DO_ZPZZ_FP(sve_ah_fabd_h, uint16_t, H1_2, ah_abd_h) DO_ZPZZ_FP(sve_ah_fabd_s, uint32_t, H1_4, ah_abd_s) DO_ZPZZ_FP(sve_ah_fabd_d, uint64_t, H1_8, ah_abd_d) =20 +DO_ZPZZ_FP(sve_fscalbn_b16, int16_t, H1_2, bfloat16_scalbn) DO_ZPZZ_FP(sve_fscalbn_h, int16_t, H1_2, float16_scalbn) DO_ZPZZ_FP(sve_fscalbn_s, int32_t, H1_4, float32_scalbn) DO_ZPZZ_FP(sve_fscalbn_d, int64_t, H1_8, scalbn_d) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 0ad0aff0504..37875b6b366 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4515,6 +4515,8 @@ static gen_helper_gvec_4_ptr * const sve_fscalbn_zpzz= _fns[4] =3D { }; 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Tue, 01 Sep 2026 06:18:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 45/58] target/arm: Implement SME BFSCALE Date: Tue, 1 Sep 2026 14:17:19 +0100 Message-ID: <20260901131732.2263947-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268823656158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 5 +++++ target/arm/tcg/helper-a64-defs.h | 1 + target/arm/tcg/sme.decode | 20 ++++++++++++++++---- target/arm/tcg/translate-sme.c | 4 ++++ target/arm/tcg/vec_helper64.c | 1 + 5 files changed, 27 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 60463a67431..07507d263e9 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1877,6 +1877,11 @@ static inline bool isar_feature_aa64_sme_tmop_f8f32(= const ARMISARegisters *id) return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_f8f32(i= d); } =20 +static inline bool isar_feature_aa64_sme2_sve_bfscale(const ARMISARegister= s *id) +{ + return isar_feature_aa64_sme2(id) && isar_feature_aa64_sve_bfscale(id); +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/tcg/helper-a64-defs.h b/target/arm/tcg/helper-a64-d= efs.h index 12f58c6a442..c1e5d86b272 100644 --- a/target/arm/tcg/helper-a64-defs.h +++ b/target/arm/tcg/helper-a64-defs.h @@ -151,6 +151,7 @@ DEF_HELPER_FLAGS_5(gvec_famin_s, TCG_CALL_NO_RWG, void,= ptr, ptr, ptr, fpst, i32 DEF_HELPER_FLAGS_5(gvec_famax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) DEF_HELPER_FLAGS_5(gvec_famin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fps= t, i32) =20 +DEF_HELPER_FLAGS_5(gvec_fscale_b16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = fpst, i32) DEF_HELPER_FLAGS_5(gvec_fscale_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fp= st, i32) DEF_HELPER_FLAGS_5(gvec_fscale_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fp= st, i32) DEF_HELPER_FLAGS_5(gvec_fscale_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fp= st, i32) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 60c7cacc10e..4e19c42b196 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -287,8 +287,14 @@ ADD_n1 1100000 1 .. 10 .... 1010.0 11000 .... = 0 @z2z_4x1 SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_2x1 SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_4x1 =20 -FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_2x1 -FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_4x1 +{ + BFSCALE_n1 1100000 1 00 10 .... 1010.0 01100 .... 0 @z2z_2x1_e0 + FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_2x1 +} +{ + BFSCALE_n1 1100000 1 00 10 .... 1010.0 01100 .... 0 @z2z_4x1_e0 + FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_4x1 +} =20 FMUL_n1 1100000 1 esz:2 1 zm:4 0 111010 ....0 ....0 \ &zzz_en n=3D2 zd=3D%zd_ax2 zn=3D%zn_ax2 @@ -365,8 +371,14 @@ FAMAX_nn 1100000 1 .. 1 ..... 1011.0 01010 .... = 0 @z2z_4x4 FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_2x2 FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_4x4 =20 -FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_2x2 -FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_4x4 +{ + BFSCALE_nn 1100000 1 00 1 ..... 1011.0 01100 .... 0 @z2z_2x2_e0 + FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_2x2 +} +{ + BFSCALE_nn 1100000 1 00 1 ..... 1011.0 01100 .... 0 @z2z_4x4_e0 + FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_4x4 +} =20 FMUL_nn 1100000 1 esz:2 1 ....0 111001 ....0 ....0 \ &zzz_en n=3D2 zd=3D%zd_ax2 zn=3D%zn_ax2 zm=3D%zm_ax2 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 463754b057f..d28574a8cf0 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -890,6 +890,10 @@ static gen_helper_gvec_3_ptr * const f_vector_fscale[4= ] =3D { }; TRANS_FEAT(FSCALE_n1, aa64_sme2_f8cvt, do_zzz_n1_fpst, a, f_vector_fscale[= a->esz]) TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_zzz_nn_fpst, a, f_vector_fscale[= a->esz]) +TRANS_FEAT(BFSCALE_n1, aa64_sme2_sve_bfscale, do_zzz_n1_fpst, a, + gen_helper_gvec_fscale_b16) +TRANS_FEAT(BFSCALE_nn, aa64_sme2_sve_bfscale, do_zzz_nn_fpst, a, + gen_helper_gvec_fscale_b16) =20 static gen_helper_gvec_3_ptr * const f_vector_fmul[4] =3D { NULL, diff --git a/target/arm/tcg/vec_helper64.c b/target/arm/tcg/vec_helper64.c index d8b25b868ea..88799693507 100644 --- a/target/arm/tcg/vec_helper64.c +++ b/target/arm/tcg/vec_helper64.c @@ -179,6 +179,7 @@ DO_3OP(gvec_famin_s, float32_famin, float32) DO_3OP(gvec_famax_d, float64_famax, float64) DO_3OP(gvec_famin_d, float64_famin, float64) =20 +DO_3OP(gvec_fscale_b16, bfloat16_scalbn, int16_t) DO_3OP(gvec_fscale_h, float16_scalbn, int16_t) DO_3OP(gvec_fscale_s, float32_scalbn, int32_t) DO_3OP(gvec_fscale_d, scalbn_d, int64_t) --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 01 Sep 2026 06:18:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 46/58] target/arm: Implement SME BFMUL Date: Tue, 1 Sep 2026 14:17:20 +0100 Message-ID: <20260901131732.2263947-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268807617158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 24 ++++++++++++++++++++---- target/arm/tcg/translate-sme.c | 4 ++++ 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 4e19c42b196..3e4cb7e5829 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -296,10 +296,18 @@ SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 ....= 0 @z2z_4x1 FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_4x1 } =20 -FMUL_n1 1100000 1 esz:2 1 zm:4 0 111010 ....0 ....0 \ +{ + BFMUL_n1 1100000 1 00 1 zm:4 0 111010 ....0 ....0 \ + &zzz_en n=3D2 zd=3D%zd_ax2 zn=3D%zn_ax2 esz=3D0 + FMUL_n1 1100000 1 esz:2 1 zm:4 0 111010 ....0 ....0 \ &zzz_en n=3D2 zd=3D%zd_ax2 zn=3D%zn_ax2 -FMUL_n1 1100000 1 esz:2 1 zm:4 1 111010 ...00 ...00 \ +} +{ + BFMUL_n1 1100000 1 00 1 zm:4 1 111010 ...00 ...00 \ + &zzz_en n=3D4 zd=3D%zd_ax4 zn=3D%zn_ax4 esz=3D0 + FMUL_n1 1100000 1 esz:2 1 zm:4 1 111010 ...00 ...00 \ &zzz_en n=3D4 zd=3D%zd_ax4 zn=3D%zn_ax4 +} =20 ### SME2 Multi-vector Multiple Vectors SVE Destructive =20 @@ -380,10 +388,18 @@ FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 ....= 1 @z2z_4x4 FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_4x4 } =20 -FMUL_nn 1100000 1 esz:2 1 ....0 111001 ....0 ....0 \ +{ + BFMUL_nn 1100000 1 00 1 ....0 111001 ....0 ....0 \ + &zzz_en n=3D2 zd=3D%zd_ax2 zn=3D%zn_ax2 zm=3D%zm_ax2 esz=3D0 + FMUL_nn 1100000 1 esz:2 1 ....0 111001 ....0 ....0 \ &zzz_en n=3D2 zd=3D%zd_ax2 zn=3D%zn_ax2 zm=3D%zm_ax2 -FMUL_nn 1100000 1 esz:2 1 ...01 111001 ...00 ...00 \ +} +{ + BFMUL_nn 1100000 1 00 1 ...01 111001 ...00 ...00 \ + &zzz_en n=3D4 zd=3D%zd_ax4 zn=3D%zn_ax4 zm=3D%zm_ax4 esz=3D0 + FMUL_nn 1100000 1 esz:2 1 ...01 111001 ...00 ...00 \ &zzz_en n=3D4 zd=3D%zd_ax4 zn=3D%zn_ax4 zm=3D%zm_ax4 +} =20 ### SME2 Multi-vector Multiple and Single Array Vectors =20 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index d28574a8cf0..08b25b0be9d 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -903,6 +903,10 @@ static gen_helper_gvec_3_ptr * const f_vector_fmul[4] = =3D { }; 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Tue, 01 Sep 2026 06:18:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 47/58] target/arm: Enable FEAT_SVE_BFSCALE for -cpu max Date: Tue, 1 Sep 2026 14:17:21 +0100 Message-ID: <20260901131732.2263947-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269065534158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + linux-user/aarch64/elfload.c | 1 + target/arm/tcg/cpu64.c | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 862341933ac..af5245cd21b 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -199,6 +199,7 @@ the following architecture extensions: - FEAT_SVE (Scalable Vector Extension) - FEAT_SVE_AES (Scalable Vector AES instructions) - FEAT_SVE_B16B16 (Non-widening BFloat16 arithmetic for SVE2) +- FEAT_SVE_BFSCALE (BFloat16 Floating-Point Adjust Exponent) - FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions) - FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions) - FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions) diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index c086548f7fd..bcf2e6b9c18 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -180,6 +180,7 @@ abi_ulong get_elf_hwcap(CPUState *cs) GET_FEATURE_ID(aa64_sme_tmop, ARM_HWCAP_A64_SME_STMOP); GET_FEATURE_ID(aa64_sve2p2, ARM_HWCAP_A64_SVE2P2); GET_FEATURE_ID(aa64_sme2p2, ARM_HWCAP_A64_SME2P2); + GET_FEATURE_ID(aa64_sve_bfscale, ARM_HWCAP_A64_SVE_BFSCALE); =20 return hwcaps; } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 12270b42977..2eb049b6002 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1474,7 +1474,7 @@ void aarch64_max_v9_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMUL= L128 */ t =3D FIELD_DP64(t, ID_AA64ZFR0, ELTPERM, 1); /* v9.4: FEAT_SVE2p2 */ t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitP= erm */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* v9.2: FEAT_SVE_B16B= 16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 2); /* v9.2: FEAT_SVE_BFSC= ALE */ t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3= */ t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* v9.0: FEAT_SVE_SM4 = */ SET_IDREG(isar, ID_AA64ZFR0, t); --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- bsd-user/aarch64/target_arch_elf.h | 2 +- linux-user/aarch64/elfload.c | 2 +- target/arm/cpu-features.h | 2 +- target/arm/tcg/translate-sve.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/bsd-user/aarch64/target_arch_elf.h b/bsd-user/aarch64/target_a= rch_elf.h index 2fb7dcd778b..6f9d192b4ff 100644 --- a/bsd-user/aarch64/target_arch_elf.h +++ b/bsd-user/aarch64/target_arch_elf.h @@ -127,7 +127,7 @@ static uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2); GET_FEATURE_ID(aa64_sve_aes, ARM_HWCAP2_A64_SVEAES); - GET_FEATURE_ID(aa64_sve2_pmull128, ARM_HWCAP2_A64_SVEPMULL); + GET_FEATURE_ID(aa64_sve_pmull128, ARM_HWCAP2_A64_SVEPMULL); GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM); GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3); GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4); diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index bcf2e6b9c18..40c5e1dbd38 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -193,7 +193,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2); GET_FEATURE_ID(aa64_sve_aes, ARM_HWCAP2_A64_SVEAES); - GET_FEATURE_ID(aa64_sve2_pmull128, ARM_HWCAP2_A64_SVEPMULL); + GET_FEATURE_ID(aa64_sve_pmull128, ARM_HWCAP2_A64_SVEPMULL); GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM); GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3); GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4); diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 07507d263e9..8e00b82ad18 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1539,7 +1539,7 @@ static inline bool isar_feature_aa64_sve_aes(const AR= MISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) !=3D 0; } =20 -static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *= id) +static inline bool isar_feature_aa64_sve_pmull128(const ARMISARegisters *i= d) { return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) >=3D 2; } diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 37875b6b366..773e4ba4e7b 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -7243,7 +7243,7 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_e= sz *a, bool sel) }; =20 if (a->esz =3D=3D 0) { - if (!dc_isar_feature(aa64_sve2_pmull128, s)) { + if (!dc_isar_feature(aa64_sve_pmull128, s)) { return false; } s->is_nonstreaming =3D !dc_isar_feature(aa64_ssve_aes, s); --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- bsd-user/aarch64/target_arch_elf.h | 2 +- linux-user/aarch64/elfload.c | 2 +- target/arm/cpu-features.h | 2 +- target/arm/tcg/translate-sve.c | 6 +++--- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/bsd-user/aarch64/target_arch_elf.h b/bsd-user/aarch64/target_a= rch_elf.h index 6f9d192b4ff..818b6f690a3 100644 --- a/bsd-user/aarch64/target_arch_elf.h +++ b/bsd-user/aarch64/target_arch_elf.h @@ -128,7 +128,7 @@ static uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2); GET_FEATURE_ID(aa64_sve_aes, ARM_HWCAP2_A64_SVEAES); GET_FEATURE_ID(aa64_sve_pmull128, ARM_HWCAP2_A64_SVEPMULL); - GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM); + GET_FEATURE_ID(aa64_sve_bitperm, ARM_HWCAP2_A64_SVEBITPERM); GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3); GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4); GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index 40c5e1dbd38..0569350e376 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -194,7 +194,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2); GET_FEATURE_ID(aa64_sve_aes, ARM_HWCAP2_A64_SVEAES); GET_FEATURE_ID(aa64_sve_pmull128, ARM_HWCAP2_A64_SVEPMULL); - GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM); + GET_FEATURE_ID(aa64_sve_bitperm, ARM_HWCAP2_A64_SVEBITPERM); GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3); GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4); GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 8e00b82ad18..7d7837c6851 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1544,7 +1544,7 @@ static inline bool isar_feature_aa64_sve_pmull128(con= st ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) >=3D 2; } =20 -static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *i= d) +static inline bool isar_feature_aa64_sve_bitperm(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BITPERM) !=3D 0; } diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 773e4ba4e7b..87d6b5785c4 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -7430,21 +7430,21 @@ static gen_helper_gvec_3 * const bext_fns[4] =3D { gen_helper_sve2_bext_b, gen_helper_sve2_bext_h, gen_helper_sve2_bext_s, gen_helper_sve2_bext_d, }; -TRANS_FEAT_NONSTREAMING(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, +TRANS_FEAT_NONSTREAMING(BEXT, aa64_sve_bitperm, gen_gvec_ool_arg_zzz, bext_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const bdep_fns[4] =3D { gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h, gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d, }; -TRANS_FEAT_NONSTREAMING(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, +TRANS_FEAT_NONSTREAMING(BDEP, aa64_sve_bitperm, gen_gvec_ool_arg_zzz, bdep_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const bgrp_fns[4] =3D { gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h, gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d, }; 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Reorg trans_RAX1 to use TRANS_FEAT_STREAMING_IF. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- bsd-user/aarch64/target_arch_elf.h | 2 +- linux-user/aarch64/elfload.c | 2 +- target/arm/cpu-features.h | 2 +- target/arm/tcg/translate-sve.c | 13 ++----------- 4 files changed, 5 insertions(+), 14 deletions(-) diff --git a/bsd-user/aarch64/target_arch_elf.h b/bsd-user/aarch64/target_a= rch_elf.h index 818b6f690a3..8669f3f8330 100644 --- a/bsd-user/aarch64/target_arch_elf.h +++ b/bsd-user/aarch64/target_arch_elf.h @@ -129,7 +129,7 @@ static uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa64_sve_aes, ARM_HWCAP2_A64_SVEAES); GET_FEATURE_ID(aa64_sve_pmull128, ARM_HWCAP2_A64_SVEPMULL); GET_FEATURE_ID(aa64_sve_bitperm, ARM_HWCAP2_A64_SVEBITPERM); - GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3); + GET_FEATURE_ID(aa64_sve_sha3, ARM_HWCAP2_A64_SVESHA3); GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4); GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index 0569350e376..83791768c6e 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -195,7 +195,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) GET_FEATURE_ID(aa64_sve_aes, ARM_HWCAP2_A64_SVEAES); GET_FEATURE_ID(aa64_sve_pmull128, ARM_HWCAP2_A64_SVEPMULL); GET_FEATURE_ID(aa64_sve_bitperm, ARM_HWCAP2_A64_SVEBITPERM); - GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3); + GET_FEATURE_ID(aa64_sve_sha3, ARM_HWCAP2_A64_SVESHA3); GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4); GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 7d7837c6851..60e3f88c9e7 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1554,7 +1554,7 @@ static inline bool isar_feature_aa64_sme_sve_bf16(con= st ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BFLOAT16) !=3D 0; } =20 -static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) +static inline bool isar_feature_aa64_sve_sha3(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SHA3) !=3D 0; } diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 87d6b5785c4..cf5445870cc 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -8307,17 +8307,8 @@ TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gve= c_ool_arg_zzz, TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, gen_helper_crypto_sm4ekey, a, 0) =20 -static bool trans_RAX1(DisasContext *s, arg_RAX1 *a) -{ - if (!dc_isar_feature(aa64_sve2_sha3, s)) { - return false; - } - if (!dc_isar_feature(aa64_sme2p1, s)) { - /* SME2p1 adds this as valid in streaming SVE mode */ - s->is_nonstreaming =3D true; - } - return gen_gvec_fn_arg_zzz(s, gen_gvec_rax1, a); -} +TRANS_FEAT_STREAMING_IF(RAX1, aa64_sve_sha3, aa64_sme2p1, + gen_gvec_fn_arg_zzz, gen_gvec_rax1, a) =20 TRANS_FEAT(FCVTNT_sh_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64) --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- bsd-user/aarch64/target_arch_elf.h | 2 +- linux-user/aarch64/elfload.c | 2 +- target/arm/cpu-features.h | 2 +- target/arm/tcg/translate-sve.c | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/bsd-user/aarch64/target_arch_elf.h b/bsd-user/aarch64/target_a= rch_elf.h index 8669f3f8330..0ec7a7b5859 100644 --- a/bsd-user/aarch64/target_arch_elf.h +++ b/bsd-user/aarch64/target_arch_elf.h @@ -130,7 +130,7 @@ static uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa64_sve_pmull128, ARM_HWCAP2_A64_SVEPMULL); GET_FEATURE_ID(aa64_sve_bitperm, ARM_HWCAP2_A64_SVEBITPERM); GET_FEATURE_ID(aa64_sve_sha3, ARM_HWCAP2_A64_SVESHA3); - GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4); + GET_FEATURE_ID(aa64_sve_sm4, ARM_HWCAP2_A64_SVESM4); GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); GET_FEATURE_ID(aa64_sve_i8mm, ARM_HWCAP2_A64_SVEI8MM); diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index 83791768c6e..7afbfca4183 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -196,7 +196,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) GET_FEATURE_ID(aa64_sve_pmull128, ARM_HWCAP2_A64_SVEPMULL); GET_FEATURE_ID(aa64_sve_bitperm, ARM_HWCAP2_A64_SVEBITPERM); GET_FEATURE_ID(aa64_sve_sha3, ARM_HWCAP2_A64_SVESHA3); - GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4); + GET_FEATURE_ID(aa64_sve_sm4, ARM_HWCAP2_A64_SVESM4); GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); GET_FEATURE_ID(aa64_sve_i8mm, ARM_HWCAP2_A64_SVEI8MM); diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 60e3f88c9e7..749dbfe6fb0 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1559,7 +1559,7 @@ static inline bool isar_feature_aa64_sve_sha3(const A= RMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SHA3) !=3D 0; } =20 -static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) +static inline bool isar_feature_aa64_sve_sm4(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SM4) !=3D 0; } diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index cf5445870cc..3d823674cca 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -8302,9 +8302,9 @@ TRANS_FEAT_STREAMING_IF(AESE, aa64_sve_aes, aa64_ssve= _aes, TRANS_FEAT_STREAMING_IF(AESD, aa64_sve_aes, aa64_ssve_aes, gen_gvec_ool_arg_zzz, gen_helper_crypto_aesd, a, 0) =20 -TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, +TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve_sm4, gen_gvec_ool_arg_zzz, gen_helper_crypto_sm4e, a, 0) -TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, +TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve_sm4, gen_gvec_ool_arg_zzz, gen_helper_crypto_sm4ekey, a, 0) =20 TRANS_FEAT_STREAMING_IF(RAX1, aa64_sve_sha3, aa64_sme2p1, --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 01 Sep 2026 06:18:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 52/58] target/arm: Implement and enable FEAT_SSVE_BitPerm for -cpu max Date: Tue, 1 Sep 2026 14:17:26 +0100 Message-ID: <20260901131732.2263947-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268993076158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + linux-user/aarch64/elfload.c | 1 + target/arm/cpu-features.h | 5 +++++ target/arm/tcg/cpu64.c | 1 + target/arm/tcg/translate-sve.c | 12 ++++++------ 5 files changed, 14 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index af5245cd21b..e3ec4b6137a 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -192,6 +192,7 @@ the following architecture extensions: - FEAT_SME_MOP4 (Quarter-tile outer product instructions) - FEAT_SME_TMOP (Structured sparsity outer product instructions) - FEAT_SSVE_AES (Streaming SVE Mode Advanced Encryption Standard and 128-b= it polynomial multiply long instructions) +- FEAT_SSVE_BitPerm (Streaming Scalable Vector Bit Permutes instructions) - FEAT_SSVE_FEXPA (Streaming FEXPA instruction) - FEAT_SSVE_FP8DOT2 (SVE2 FP8 2-way dot product to half-precision instruct= ions in Streaming SVE mode) - FEAT_SSVE_FP8DOT4 (SVE2 FP8 4-way dot product to single-precision instru= ctions in Streaming SVE mode) diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index 7afbfca4183..4359312ee38 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -181,6 +181,7 @@ abi_ulong get_elf_hwcap(CPUState *cs) GET_FEATURE_ID(aa64_sve2p2, ARM_HWCAP_A64_SVE2P2); GET_FEATURE_ID(aa64_sme2p2, ARM_HWCAP_A64_SME2P2); GET_FEATURE_ID(aa64_sve_bfscale, ARM_HWCAP_A64_SVE_BFSCALE); + GET_FEATURE_ID(aa64_ssve_bitperm, ARM_HWCAP_A64_SME_SBITPERM); =20 return hwcaps; } diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 749dbfe6fb0..b23b5a83c68 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1610,6 +1610,11 @@ static inline bool isar_feature_aa64_ssve_aes(const = ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64SMFR0, AES); } =20 +static inline bool isar_feature_aa64_ssve_bitperm(const ARMISARegisters *i= d) +{ + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SBITPERM); +} + static inline bool isar_feature_aa64_ssve_f8fma(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8FMA); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 2eb049b6002..4994a87afed 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1484,6 +1484,7 @@ void aarch64_max_v9_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64SMFR0, STMOP, 1); /* v9.4: FEAT_SME_TMOP= */ t =3D FIELD_DP64(t, ID_AA64SMFR0, SFEXPA, 1); /* v9.4: FEAT_SSVE_FEX= PA */ t =3D FIELD_DP64(t, ID_AA64SMFR0, AES, 1); /* v9.5: FEAT_SSVE_AES= */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SBITPERM, 1); /* v9.4: FEAT_SSVE_Bit= Perm */ t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP2, 1); /* v9.2: FEAT_SSVE_FP8= DOT2 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP4, 1); /* v9.2: FEAT_SSVE_FP8= DOT4 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8FMA, 1); /* v9.2: FEAT_SSVE_FP8= FMA */ diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 3d823674cca..8a5903da4fc 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -7430,22 +7430,22 @@ static gen_helper_gvec_3 * const bext_fns[4] =3D { gen_helper_sve2_bext_b, gen_helper_sve2_bext_h, gen_helper_sve2_bext_s, gen_helper_sve2_bext_d, }; -TRANS_FEAT_NONSTREAMING(BEXT, aa64_sve_bitperm, gen_gvec_ool_arg_zzz, - bext_fns[a->esz], a, 0) +TRANS_FEAT_STREAMING_IF(BEXT, aa64_sve_bitperm, aa64_ssve_bitperm, + gen_gvec_ool_arg_zzz, bext_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const bdep_fns[4] =3D { gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h, gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d, }; -TRANS_FEAT_NONSTREAMING(BDEP, aa64_sve_bitperm, gen_gvec_ool_arg_zzz, - bdep_fns[a->esz], a, 0) +TRANS_FEAT_STREAMING_IF(BDEP, aa64_sve_bitperm, aa64_ssve_bitperm, + gen_gvec_ool_arg_zzz, bdep_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const bgrp_fns[4] =3D { gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h, gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d, }; -TRANS_FEAT_NONSTREAMING(BGRP, aa64_sve_bitperm, gen_gvec_ool_arg_zzz, - bgrp_fns[a->esz], a, 0) +TRANS_FEAT_STREAMING_IF(BGRP, aa64_sve_bitperm, aa64_ssve_bitperm, + gen_gvec_ool_arg_zzz, bgrp_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const cadd_fns[4] =3D { gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h, --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 5 ++++ target/arm/tcg/crypto_helper.c | 55 ++++++++++++++++++++++++---------- target/arm/tcg/helper-defs.h | 2 ++ target/arm/tcg/sve.decode | 13 ++++++-- target/arm/tcg/translate-sve.c | 35 ++++++++++++++++++++++ 5 files changed, 92 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index b23b5a83c68..eecbc3b889e 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1544,6 +1544,11 @@ static inline bool isar_feature_aa64_sve_pmull128(co= nst ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) >=3D 2; } =20 +static inline bool isar_feature_aa64_sve_aes2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) >=3D 3; +} + static inline bool isar_feature_aa64_sve_bitperm(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BITPERM) !=3D 0; diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index 11977cb7723..27b5813b6d9 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -47,6 +47,27 @@ static void clear_tail_16(void *vd, uint32_t desc) =20 static const AESState aes_zero =3D { }; =20 +static void aese_kernel(AESState *ad, const AESState *st, const AESState *= rk) +{ + AESState t; + + /* + * Our uint64_t are in the wrong order for big-endian. + * The Arm AddRoundKey comes first, while the API AddRoundKey + * comes last: perform the xor here, and provide zero to API. + */ + if (HOST_BIG_ENDIAN) { + t.d[0] =3D st->d[1] ^ rk->d[1]; + t.d[1] =3D st->d[0] ^ rk->d[0]; + aesenc_SB_SR_AK(&t, &t, &aes_zero, false); + ad->d[0] =3D t.d[1]; + ad->d[1] =3D t.d[0]; + } else { + t.v =3D st->v ^ rk->v; + aesenc_SB_SR_AK(ad, &t, &aes_zero, false); + } +} + void HELPER(crypto_aese)(void *vd, void *vn, void *vm, uint32_t desc) { intptr_t i, opr_sz =3D simd_oprsz(desc); @@ -55,27 +76,29 @@ void HELPER(crypto_aese)(void *vd, void *vn, void *vm, = uint32_t desc) AESState *ad =3D (AESState *)(vd + i); AESState *st =3D (AESState *)(vn + i); AESState *rk =3D (AESState *)(vm + i); - AESState t; =20 - /* - * Our uint64_t are in the wrong order for big-endian. - * The Arm AddRoundKey comes first, while the API AddRoundKey - * comes last: perform the xor here, and provide zero to API. - */ - if (HOST_BIG_ENDIAN) { - t.d[0] =3D st->d[1] ^ rk->d[1]; - t.d[1] =3D st->d[0] ^ rk->d[0]; - aesenc_SB_SR_AK(&t, &t, &aes_zero, false); - ad->d[0] =3D t.d[1]; - ad->d[1] =3D t.d[0]; - } else { - t.v =3D st->v ^ rk->v; - aesenc_SB_SR_AK(ad, &t, &aes_zero, false); - } + aese_kernel(ad, st, rk); } clear_tail(vd, opr_sz, simd_maxsz(desc)); } =20 +void HELPER(crypto_aese_idx)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t opr_sz =3D simd_oprsz(desc); + intptr_t idx =3D simd_data(desc); + void *vm_idx =3D vm + idx * 16; + intptr_t s =3D opr_sz - 16; + + do { + intptr_t base =3D ROUND_DOWN(s, 4 * 16); + AESState rk =3D *(AESState *)(vm_idx + base); + do { + aese_kernel(vd + s, vn + s, &rk); + s -=3D 16; + } while (s >=3D base); + } while (s > 0); +} + void HELPER(crypto_aesd)(void *vd, void *vn, void *vm, uint32_t desc) { intptr_t i, opr_sz =3D simd_oprsz(desc); diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h index 42376af2c68..9b320b5c97e 100644 --- a/target/arm/tcg/helper-defs.h +++ b/target/arm/tcg/helper-defs.h @@ -461,6 +461,8 @@ DEF_HELPER_FLAGS_4(crypto_aesd, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(crypto_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(crypto_aese_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) + DEF_HELPER_FLAGS_4(crypto_sha1su0, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) DEF_HELPER_FLAGS_4(crypto_sha1c, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(crypto_sha1p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index ed19ae237f4..64e0dd0eae9 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -60,6 +60,8 @@ # as propagated via the MOVPRFX instruction. %reg_movprfx 0:5 =20 +%zd_ax2 1:4 !function=3Dtimes_2 +%zd_ax4 2:3 !function=3Dtimes_4 %rn_ax2 6:4 !function=3Dtimes_2 =20 %pnd 0:3 !function=3Dplus_8 @@ -70,6 +72,7 @@ # when creating helpers common to those for the individual # instruction patterns. =20 +&rx_n rdn rm index n &rr_esz rd rn esz &rri rd rn imm &rr_dbm rd rn dbm @@ -1974,6 +1977,14 @@ AESE 01000101 00 10001 0 11100 0 ..... ..= ... @rdn_rm_e0 AESD 01000101 00 10001 0 11100 1 ..... ..... @rdn_rm_e0 SM4E 01000101 00 10001 1 11100 0 ..... ..... @rdn_rm_e0 =20 +@aes2_2 ........ .. . index:2 0........ rm:5 ..... \ + &rx_n n=3D2 rdn=3D%zd_ax2 +@aes2_4 ........ .. . index:2 1........ rm:5 ..... \ + &rx_n n=3D4 rdn=3D%zd_ax4 + +AESE_idx 01000101 00 1 .. .10111010 ..... ....0 @aes2_2 +AESE_idx 01000101 00 1 .. .10111010 ..... ...00 @aes2_4 + # SVE2 crypto constructive binary operations SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0 RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0 @@ -2078,8 +2089,6 @@ FCLAMP 01100100 .. 1 ..... 001001 ..... ....= . @rda_rn_rm &zcrr_ldst rd png rn rm esz nreg &zcri_ldst rd png rn imm esz nreg %png 10:3 !function=3Dplus_8 -%zd_ax2 1:4 !function=3Dtimes_2 -%zd_ax4 2:3 !function=3Dtimes_4 =20 LD1_zcrr 10100000000 rm:5 0 esz:2 ... rn:5 .... - \ &zcrr_ldst %png rd=3D%zd_ax2 nreg=3D2 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 8a5903da4fc..9ce172dd939 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -8310,6 +8310,41 @@ TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve_sm4, gen_g= vec_ool_arg_zzz, TRANS_FEAT_STREAMING_IF(RAX1, aa64_sve_sha3, aa64_sme2p1, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a) =20 +static bool do_aes2_idx(DisasContext *s, arg_rx_n *a, gen_helper_gvec_3 *f= n) +{ + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + int overlap =3D -1; + int index, mofs; + + if (vsz =3D=3D 16) { + index =3D 0; + } else if (vsz =3D=3D 32) { + index =3D a->index % 2; + } else { + index =3D a->index; + } + + mofs =3D vec_full_reg_offset(s, a->rm); + + for (int i =3D 0, n =3D a->n; i < n; i++) { + int dofs =3D vec_full_reg_offset(s, a->rdn + i); + if (dofs =3D=3D mofs) { + overlap =3D i; + } else { + tcg_gen_gvec_3_ool(dofs, dofs, mofs, vsz, vsz, index, fn); + } + } + if (overlap >=3D 0) { + tcg_gen_gvec_3_ool(mofs, mofs, mofs, vsz, vsz, index, fn); + } + } + return true; +} + +TRANS_FEAT_STREAMING_IF(AESE_idx, aa64_sve_aes2, aa64_ssve_aes, + do_aes2_idx, a, gen_helper_crypto_aese_idx) + TRANS_FEAT(FCVTNT_sh_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64) TRANS_FEAT(FCVTNT_sh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 01 Sep 2026 06:18:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 54/58] target/arm: Implement AESD (indexed) Date: Tue, 1 Sep 2026 14:17:28 +0100 Message-ID: <20260901131732.2263947-55-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269051556154100 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/crypto_helper.c | 47 +++++++++++++++++++++++++--------- target/arm/tcg/helper-defs.h | 1 + target/arm/tcg/sve.decode | 3 +++ target/arm/tcg/translate-sve.c | 2 ++ 4 files changed, 41 insertions(+), 12 deletions(-) diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index 27b5813b6d9..05f193b3d17 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -99,6 +99,23 @@ void HELPER(crypto_aese_idx)(void *vd, void *vn, void *v= m, uint32_t desc) } while (s > 0); } =20 +static void aesd_kernel(AESState *ad, const AESState *st, const AESState *= rk) +{ + AESState t; + + /* Our uint64_t are in the wrong order for big-endian. */ + if (HOST_BIG_ENDIAN) { + t.d[0] =3D st->d[1] ^ rk->d[1]; + t.d[1] =3D st->d[0] ^ rk->d[0]; + aesdec_ISB_ISR_AK(&t, &t, &aes_zero, false); + ad->d[0] =3D t.d[1]; + ad->d[1] =3D t.d[0]; + } else { + t.v =3D st->v ^ rk->v; + aesdec_ISB_ISR_AK(ad, &t, &aes_zero, false); + } +} + void HELPER(crypto_aesd)(void *vd, void *vn, void *vm, uint32_t desc) { intptr_t i, opr_sz =3D simd_oprsz(desc); @@ -107,23 +124,29 @@ void HELPER(crypto_aesd)(void *vd, void *vn, void *vm= , uint32_t desc) AESState *ad =3D (AESState *)(vd + i); AESState *st =3D (AESState *)(vn + i); AESState *rk =3D (AESState *)(vm + i); - AESState t; =20 - /* Our uint64_t are in the wrong order for big-endian. */ - if (HOST_BIG_ENDIAN) { - t.d[0] =3D st->d[1] ^ rk->d[1]; - t.d[1] =3D st->d[0] ^ rk->d[0]; - aesdec_ISB_ISR_AK(&t, &t, &aes_zero, false); - ad->d[0] =3D t.d[1]; - ad->d[1] =3D t.d[0]; - } else { - t.v =3D st->v ^ rk->v; - aesdec_ISB_ISR_AK(ad, &t, &aes_zero, false); - } + aesd_kernel(ad, st, rk); } clear_tail(vd, opr_sz, simd_maxsz(desc)); } =20 +void HELPER(crypto_aesd_idx)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t opr_sz =3D simd_oprsz(desc); + intptr_t idx =3D simd_data(desc); + void *vm_idx =3D vm + idx * 16; + intptr_t s =3D opr_sz - 16; + + do { + intptr_t base =3D ROUND_DOWN(s, 4 * 16); + AESState rk =3D *(AESState *)(vm_idx + base); + do { + aesd_kernel(vd + s, vn + s, &rk); + s -=3D 16; + } while (s >=3D base); + } while (s > 0); +} + void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t desc) { intptr_t i, opr_sz =3D simd_oprsz(desc); diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h index 9b320b5c97e..1a0e4130aa2 100644 --- a/target/arm/tcg/helper-defs.h +++ b/target/arm/tcg/helper-defs.h @@ -462,6 +462,7 @@ DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void,= ptr, ptr, i32) DEF_HELPER_FLAGS_3(crypto_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(crypto_aese_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) +DEF_HELPER_FLAGS_4(crypto_aesd_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) =20 DEF_HELPER_FLAGS_4(crypto_sha1su0, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) DEF_HELPER_FLAGS_4(crypto_sha1c, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 64e0dd0eae9..1ab1b4042b5 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1985,6 +1985,9 @@ SM4E 01000101 00 10001 1 11100 0 ..... ...= .. @rdn_rm_e0 AESE_idx 01000101 00 1 .. .10111010 ..... ....0 @aes2_2 AESE_idx 01000101 00 1 .. .10111010 ..... ...00 @aes2_4 =20 +AESD_idx 01000101 00 1 .. .10111011 ..... ....0 @aes2_2 +AESD_idx 01000101 00 1 .. .10111011 ..... ...00 @aes2_4 + # SVE2 crypto constructive binary operations SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0 RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 9ce172dd939..cb1542f3931 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -8344,6 +8344,8 @@ static bool do_aes2_idx(DisasContext *s, arg_rx_n *a,= gen_helper_gvec_3 *fn) =20 TRANS_FEAT_STREAMING_IF(AESE_idx, aa64_sve_aes2, aa64_ssve_aes, do_aes2_idx, a, gen_helper_crypto_aese_idx) +TRANS_FEAT_STREAMING_IF(AESD_idx, aa64_sve_aes2, aa64_ssve_aes, + do_aes2_idx, a, gen_helper_crypto_aesd_idx) =20 TRANS_FEAT(FCVTNT_sh_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64) --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 01 Sep 2026 06:18:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 55/58] target/arm: Implement AESEMC Date: Tue, 1 Sep 2026 14:17:29 +0100 Message-ID: <20260901131732.2263947-56-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269008737154100 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/crypto_helper.c | 31 +++++++++++++++++++++++++++++++ target/arm/tcg/helper-defs.h | 1 + target/arm/tcg/sve.decode | 3 +++ target/arm/tcg/translate-sve.c | 2 ++ 4 files changed, 37 insertions(+) diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index 05f193b3d17..ae677cdf209 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -193,6 +193,37 @@ void HELPER(crypto_aesimc)(void *vd, void *vm, uint32_= t desc) clear_tail(vd, opr_sz, simd_maxsz(desc)); } =20 +void HELPER(crypto_aesemc)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t opr_sz =3D simd_oprsz(desc); + intptr_t idx =3D simd_data(desc); + void *vm_idx =3D vm + idx * 16; + intptr_t s =3D opr_sz - 16; + + do { + intptr_t base =3D ROUND_DOWN(s, 4 * 16); + AESState rk =3D *(AESState *)(vm_idx + base); + do { + AESState *ad =3D (AESState *)(vd + s); + AESState *st =3D (AESState *)(vn + s); + AESState t; + + /* Like above: Arm AK comes first; api AK comes last */ + if (HOST_BIG_ENDIAN) { + t.d[0] =3D st->d[1] ^ rk.d[1]; + t.d[1] =3D st->d[0] ^ rk.d[0]; + aesenc_SB_SR_MC_AK(&t, &t, &aes_zero, false); + ad->d[0] =3D t.d[1]; + ad->d[1] =3D t.d[0]; + } else { + t.v =3D st->v ^ rk.v; + aesenc_SB_SR_MC_AK(ad, &t, &aes_zero, false); + } + s -=3D 16; + } while (s >=3D base); + } while (s > 0); +} + /* * SHA-1 logical functions */ diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h index 1a0e4130aa2..512054d2f5d 100644 --- a/target/arm/tcg/helper-defs.h +++ b/target/arm/tcg/helper-defs.h @@ -460,6 +460,7 @@ DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(crypto_aesd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(crypto_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_aesemc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) =20 DEF_HELPER_FLAGS_4(crypto_aese_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(crypto_aesd_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 1ab1b4042b5..5832e0190c6 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1988,6 +1988,9 @@ AESE_idx 01000101 00 1 .. .10111010 ..... ...0= 0 @aes2_4 AESD_idx 01000101 00 1 .. .10111011 ..... ....0 @aes2_2 AESD_idx 01000101 00 1 .. .10111011 ..... ...00 @aes2_4 =20 +AESEMC 01000101 00 1 .. .11111010 ..... ....0 @aes2_2 +AESEMC 01000101 00 1 .. .11111010 ..... ...00 @aes2_4 + # SVE2 crypto constructive binary operations SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0 RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index cb1542f3931..64ff2345307 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -8346,6 +8346,8 @@ TRANS_FEAT_STREAMING_IF(AESE_idx, aa64_sve_aes2, aa64= _ssve_aes, do_aes2_idx, a, gen_helper_crypto_aese_idx) TRANS_FEAT_STREAMING_IF(AESD_idx, aa64_sve_aes2, aa64_ssve_aes, do_aes2_idx, a, gen_helper_crypto_aesd_idx) +TRANS_FEAT_STREAMING_IF(AESEMC, aa64_sve_aes2, aa64_ssve_aes, + do_aes2_idx, a, gen_helper_crypto_aesemc) =20 TRANS_FEAT(FCVTNT_sh_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64) --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 01 Sep 2026 06:18:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 56/58] target/arm: Implement AESDIMC Date: Tue, 1 Sep 2026 14:17:30 +0100 Message-ID: <20260901131732.2263947-57-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269095428158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/crypto_helper.c | 31 +++++++++++++++++++++++++++++++ target/arm/tcg/helper-defs.h | 1 + target/arm/tcg/sve.decode | 3 +++ target/arm/tcg/translate-sve.c | 2 ++ 4 files changed, 37 insertions(+) diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index ae677cdf209..07d008c1be5 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -224,6 +224,37 @@ void HELPER(crypto_aesemc)(void *vd, void *vn, void *v= m, uint32_t desc) } while (s > 0); } =20 +void HELPER(crypto_aesdimc)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t opr_sz =3D simd_oprsz(desc); + intptr_t idx =3D simd_data(desc); + void *vm_idx =3D vm + idx * 16; + intptr_t s =3D opr_sz - 16; + + do { + intptr_t base =3D ROUND_DOWN(s, 4 * 16); + AESState rk =3D *(AESState *)(vm_idx + base); + do { + AESState *ad =3D (AESState *)(vd + s); + AESState *st =3D (AESState *)(vn + s); + AESState t; + + /* Like above: Arm AK comes first; api AK comes last */ + if (HOST_BIG_ENDIAN) { + t.d[0] =3D st->d[1] ^ rk.d[1]; + t.d[1] =3D st->d[0] ^ rk.d[0]; + aesdec_ISB_ISR_IMC_AK(&t, &t, &aes_zero, false); + ad->d[0] =3D t.d[1]; + ad->d[1] =3D t.d[0]; + } else { + t.v =3D st->v ^ rk.v; + aesdec_ISB_ISR_IMC_AK(ad, &t, &aes_zero, false); + } + s -=3D 16; + } while (s >=3D base); + } while (s > 0); +} + /* * SHA-1 logical functions */ diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h index 512054d2f5d..269ac515065 100644 --- a/target/arm/tcg/helper-defs.h +++ b/target/arm/tcg/helper-defs.h @@ -461,6 +461,7 @@ DEF_HELPER_FLAGS_4(crypto_aesd, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(crypto_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_4(crypto_aesemc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(crypto_aesdimc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) =20 DEF_HELPER_FLAGS_4(crypto_aese_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(crypto_aesd_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, = i32) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 5832e0190c6..7030d81db7e 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1991,6 +1991,9 @@ AESD_idx 01000101 00 1 .. .10111011 ..... ...0= 0 @aes2_4 AESEMC 01000101 00 1 .. .11111010 ..... ....0 @aes2_2 AESEMC 01000101 00 1 .. .11111010 ..... ...00 @aes2_4 =20 +AESDIMC 01000101 00 1 .. .11111011 ..... ....0 @aes2_2 +AESDIMC 01000101 00 1 .. .11111011 ..... ...00 @aes2_4 + # SVE2 crypto constructive binary operations SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0 RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 64ff2345307..1098cf0b388 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -8348,6 +8348,8 @@ TRANS_FEAT_STREAMING_IF(AESD_idx, aa64_sve_aes2, aa64= _ssve_aes, do_aes2_idx, a, gen_helper_crypto_aesd_idx) TRANS_FEAT_STREAMING_IF(AESEMC, aa64_sve_aes2, aa64_ssve_aes, do_aes2_idx, a, gen_helper_crypto_aesemc) +TRANS_FEAT_STREAMING_IF(AESDIMC, aa64_sve_aes2, aa64_ssve_aes, + do_aes2_idx, a, gen_helper_crypto_aesdimc) =20 TRANS_FEAT(FCVTNT_sh_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64) --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 01 Sep 2026 06:18:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 57/58] target/arm: Implement PMULL, PMLAL Date: Tue, 1 Sep 2026 14:17:31 +0100 Message-ID: <20260901131732.2263947-58-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788268768397154101 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260826174213.614571-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve-defs.h | 3 +++ target/arm/tcg/sve.decode | 5 +++++ target/arm/tcg/translate-sve.c | 5 +++++ target/arm/tcg/vec_helper64.c | 34 ++++++++++++++++++++++++++++++++ 4 files changed, 47 insertions(+) diff --git a/target/arm/tcg/helper-sve-defs.h b/target/arm/tcg/helper-sve-d= efs.h index f78e77662de..498468a7723 100644 --- a/target/arm/tcg/helper-sve-defs.h +++ b/target/arm/tcg/helper-sve-defs.h @@ -3215,3 +3215,6 @@ DEF_HELPER_FLAGS_4(sve_expand_b, TCG_CALL_NO_WG, void= , ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_expand_h, TCG_CALL_NO_WG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_expand_s, TCG_CALL_NO_WG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_expand_d, TCG_CALL_NO_WG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_pmlal_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 7030d81db7e..42f451ff9f0 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1994,6 +1994,11 @@ AESEMC 01000101 00 1 .. .11111010 ..... ...= 00 @aes2_4 AESDIMC 01000101 00 1 .. .11111011 ..... ....0 @aes2_2 AESDIMC 01000101 00 1 .. .11111011 ..... ...00 @aes2_4 =20 +PMULL 01000101 00 1 rm:5 111110 rn:5 ....0 \ + &rrr_esz esz=3D0 rd=3D%zd_ax2 +PMLAL 01000101 00 1 rm:5 111111 rn:5 ....0 \ + &rrr_esz esz=3D0 rd=3D%zd_ax2 + # SVE2 crypto constructive binary operations SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0 RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 1098cf0b388..10375577b1e 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -8351,6 +8351,11 @@ TRANS_FEAT_STREAMING_IF(AESEMC, aa64_sve_aes2, aa64_= ssve_aes, TRANS_FEAT_STREAMING_IF(AESDIMC, aa64_sve_aes2, aa64_ssve_aes, do_aes2_idx, a, gen_helper_crypto_aesdimc) =20 +TRANS_FEAT_STREAMING_IF(PMULL, aa64_sve_aes2, aa64_ssve_aes, + gen_gvec_ool_arg_zzz, gen_helper_sve_pmull_q, a, 0) +TRANS_FEAT_STREAMING_IF(PMLAL, aa64_sve_aes2, aa64_ssve_aes, + gen_gvec_ool_arg_zzz, gen_helper_sve_pmlal_q, a, 0) + TRANS_FEAT(FCVTNT_sh_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64) TRANS_FEAT(FCVTNT_sh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, diff --git a/target/arm/tcg/vec_helper64.c b/target/arm/tcg/vec_helper64.c index 88799693507..4f43869d9e9 100644 --- a/target/arm/tcg/vec_helper64.c +++ b/target/arm/tcg/vec_helper64.c @@ -89,6 +89,40 @@ void HELPER(sve2_pmull_d)(void *vd, void *vn, void *vm, = uint32_t desc) } } =20 +void HELPER(sve_pmull_q)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t opr_sz =3D simd_oprsz(desc); + uint64_t *n =3D vn, *m =3D vm; + uint64_t *d0 =3D vd; + uint64_t *d1 =3D vd + sizeof(ARMVectorReg); + + for (intptr_t i =3D 0; i < opr_sz / 16; ++i) { + Int128 rl =3D clmul_64(n[2 * i + 0], m[2 * i + 0]); + Int128 rh =3D clmul_64(n[2 * i + 1], m[2 * i + 1]); + d0[2 * i + 0] =3D int128_getlo(rl); + d0[2 * i + 1] =3D int128_gethi(rl); + d1[2 * i + 0] =3D int128_getlo(rh); + d1[2 * i + 1] =3D int128_gethi(rh); + } +} + +void HELPER(sve_pmlal_q)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t opr_sz =3D simd_oprsz(desc); + uint64_t *n =3D vn, *m =3D vm; + uint64_t *d0 =3D vd; + uint64_t *d1 =3D vd + sizeof(ARMVectorReg); + + for (intptr_t i =3D 0; i < opr_sz / 16; ++i) { + Int128 rl =3D clmul_64(n[2 * i + 0], m[2 * i + 0]); + Int128 rh =3D clmul_64(n[2 * i + 1], m[2 * i + 1]); + d0[2 * i + 0] ^=3D int128_getlo(rl); + d0[2 * i + 1] ^=3D int128_gethi(rl); + d1[2 * i + 0] ^=3D int128_getlo(rh); + d1[2 * i + 1] ^=3D int128_gethi(rh); + } +} + DO_3OP_PAIR(gvec_ah_fmaxp_h, helper_vfp_ah_maxh, float16, H2) DO_3OP_PAIR(gvec_ah_fmaxp_s, helper_vfp_ah_maxs, float32, H4) DO_3OP_PAIR(gvec_ah_fmaxp_d, helper_vfp_ah_maxd, float64, /**/) --=20 2.43.0 From nobody Sat Sep 26 20:51:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 01 Sep 2026 06:18:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 58/58] target/arm: Enable FEAT_SVE_AES2 for -cpu max Date: Tue, 1 Sep 2026 14:17:32 +0100 Message-ID: <20260901131732.2263947-59-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901131732.2263947-1-peter.maydell@linaro.org> References: <20260901131732.2263947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1788269087532154100 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260826174213.614571-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + linux-user/aarch64/elfload.c | 1 + target/arm/tcg/cpu64.c | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index e3ec4b6137a..34b63f9867f 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -199,6 +199,7 @@ the following architecture extensions: - FEAT_SSVE_FP8FMA (SVE2 FP8 multiply-accumulate to half-precision and sin= gle-precision instructions in Streaming SVE mode) - FEAT_SVE (Scalable Vector Extension) - FEAT_SVE_AES (Scalable Vector AES instructions) +- FEAT_SVE_AES2 (SVE multi-vector Advanced Encryption Standard and 128-bit= polynomial multiply long instructions) - FEAT_SVE_B16B16 (Non-widening BFloat16 arithmetic for SVE2) - FEAT_SVE_BFSCALE (BFloat16 Floating-Point Adjust Exponent) - FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions) diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index 4359312ee38..f87f22f6903 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -182,6 +182,7 @@ abi_ulong get_elf_hwcap(CPUState *cs) GET_FEATURE_ID(aa64_sme2p2, ARM_HWCAP_A64_SME2P2); GET_FEATURE_ID(aa64_sve_bfscale, ARM_HWCAP_A64_SVE_BFSCALE); GET_FEATURE_ID(aa64_ssve_bitperm, ARM_HWCAP_A64_SME_SBITPERM); + GET_FEATURE_ID(aa64_sve_aes2, ARM_HWCAP_A64_SVE_AES2); =20 return hwcaps; } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 4994a87afed..affd87a3ae5 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1471,7 +1471,7 @@ void aarch64_max_v9_tcg_initfn(Object *obj) =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 3); /* v9.4: FEAT_SVE2p2 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMUL= L128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 3); /* v9.5: FEAT_SVE_AES2= */ t =3D FIELD_DP64(t, ID_AA64ZFR0, ELTPERM, 1); /* v9.4: FEAT_SVE2p2 */ t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitP= erm */ t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 2); /* v9.2: FEAT_SVE_BFSC= ALE */ --=20 2.43.0