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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256436533158500 Both cpu_exec_start() and cpu_exec_end() take a non-const CPUState argument, however here we get that argument via PTETranslate::env so @in->env can not be const. Remove the const qualifier. Fixes: 4a1e9d4d11c ("target/i386: Use atomic ops for pte updates") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/i386/tcg/system/excp_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/= excp_helper.c index d7ea77c8558..44be98a3c92 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -106,7 +106,7 @@ static inline uint64_t ptw_ldq(const PTETranslate *in, = uint64_t ra) * even 64-bit ones, because PG_PRESENT_MASK, PG_ACCESSED_MASK and * PG_DIRTY_MASK are all in the low 32 bits. */ -static bool ptw_setl_slow(const PTETranslate *in, uint32_t old, uint32_t n= ew) +static bool ptw_setl_slow(PTETranslate *in, uint32_t old, uint32_t new) { uint32_t cmp; =20 @@ -125,7 +125,7 @@ static bool ptw_setl_slow(const PTETranslate *in, uint3= 2_t old, uint32_t new) return cmp =3D=3D old; } =20 -static inline bool ptw_setl(const PTETranslate *in, uint32_t old, uint32_t= set) +static inline bool ptw_setl(PTETranslate *in, uint32_t old, uint32_t set) { if (set & ~old) { uint32_t new =3D old | set; --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788256446; cv=none; d=zohomail.com; s=zohoarc; b=NBgdFCns1EfZXF8rMrFv0UhSy+GC4BnaOo8SkzDzQyVmSHasDbWp7w2hnsaH5HpRQF4cWTrjcdsZJ3oWaVs2qFZHfS94yI/jB+r1cuASOJD7WYB5+P9Tmwbl3DvbmzYvBdunNYK4pD4W0+we9LwjePgnly74EMvfXRgJxQgGjT4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788256446; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RXSFdJhduuq/vV0dSoh2i7hiqI/DLrn0WKuxvW2l1mE=; b=Sg82nvsMsIdxBmYWRzVec05ungp820QCp+oxocMvqJp2u5tL+zJqFNAQB3pIETljL36SLwAE5ySK8aJ3sSG54Mzo9AiFzsksBNAAzBAxFBSFcBAPzYnyRgfvNKYJD4ahadjZWwbp28Li8j2VrckUwaMjbOVjKpOBMv4zWVH/Y8g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788256446352641.9950705484343; Tue, 1 Sep 2026 02:54:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1LAh-0007TI-Ht; Tue, 01 Sep 2026 05:52:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LAf-0007T4-U2 for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:52:49 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LAe-0007Dx-9u for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:52:49 -0400 Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68179RAR1811504 for ; Tue, 1 Sep 2026 09:52:47 GMT Received: from mail-qv1-f69.google.com (mail-qv1-f69.google.com [209.85.219.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gdd4dv6mm-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 01 Sep 2026 09:52:47 +0000 (GMT) Received: by mail-qv1-f69.google.com with SMTP id 6a1803df08f44-90e7de22fddso65659646d6.3 for ; Tue, 01 Sep 2026 02:52:47 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256448538158500 init_main_thread() is registered as Object::free() hook, thus take an Object* argument. Uncast the void pointer as such. While now cpu_env() accept any pointer type, next commit will restrict it to CPUState* type. QOM-cast the Object to CPU type, otherwise we will get: ../linux-user/i386/cpu_loop.c: In function =E2=80=98target_cpu_free=E2=80= =99: include/hw/core/cpu.h:604:31: error: =E2=80=98_Generic=E2=80=99 selector = of type =E2=80=98void=E2=80=99 is not compatible with any association ../linux-user/x86_64/../i386/cpu_loop.c:331:19: note: in expansion of macro= =E2=80=98cpu_env=E2=80=99 331 | target_munmap(cpu_env(obj)->gdt.base, | ^~~~~~~ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- linux-user/i386/cpu_loop.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index fe922fceb5a..2f733b0b477 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -326,9 +326,10 @@ void cpu_loop(CPUX86State *env) } } =20 -static void target_cpu_free(void *obj) +static void target_cpu_free(void *ptr) { - target_munmap(cpu_env(obj)->gdt.base, + Object *obj =3D ptr; + target_munmap(X86_CPU(obj)->env.gdt.base, sizeof(uint64_t) * TARGET_GDT_ENTRIES); g_free(obj); } --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788256530; cv=none; d=zohomail.com; s=zohoarc; b=Fz0q+/kv5yLXvjpd7Lux8Kn5es/gdUH5Cd20NjiZWq1vBeoFuNCs+ts8869sQoBRx6nZNnDmVguZUh+QstYWym51gpYJODmSEb+0Hc8BhM/5cJ3NbF89i8wAcZm4wOM2UFe0M3nuWrqnQPhbKuR00lfldYFyL3cUTaZ4kPznB3Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788256530; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aim88kbyx4mLrKFfSdKR/nIKrzOmFcmOxoRL9bSxY1A=; b=krGPgrRh8ucmomSh91+6z07zIWq/cXefvFTpLoy8rsaOWaeSB6Ho1wTGpCF47m+ggqHOOCoy8UZ0nJA5A7Eppry5KO+lURd6yO/U9wu83fgF0pMd/vqnpZeQeA2FWLJbqajzBscsKJ6HmG5zPd0rCVXuE0Qh76ea6EbaCswxBdQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788256530513975.7267383845816; Tue, 1 Sep 2026 02:55:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1LAp-0007Ub-Ji; Tue, 01 Sep 2026 05:52:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LAo-0007UE-8Z for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:52:58 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LAm-0007Fh-BU for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:52:58 -0400 Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 681792dn705426 for ; Tue, 1 Sep 2026 09:52:55 GMT Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gdrcsh61v-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 01 Sep 2026 09:52:54 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-939281526e1so71895585a.0 for ; Tue, 01 Sep 2026 02:52:54 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256533252154100 From: Philippe Mathieu-Daud=C3=A9 Use _Generic() controlling-expression to add the const-qualified variants of cpu_env(), env_cpu() and env_archcpu(). This allows to safely access CPU architecture state when it should not be modified. Alias env_cpu_const() which is still used. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- Following checkpatch.pl errors ignored: ERROR: spaces required around that ':' (ctx:VxE) #46: FILE: include/exec/cpu-common.h:89: + CPUArchState: \ ^ ERROR: spaces required around that ':' (ctx:VxE) #62: FILE: include/exec/cpu-common.h:101: + CPUArchState: \ ^ ERROR: spaces required around that ':' (ctx:VxE) #90: FILE: include/hw/core/cpu.h:605: + CPUState: \ ^ total: 3 errors, 0 warnings, 64 lines checked --- include/exec/cpu-common.h | 30 +++++++++++------------------- include/hw/core/cpu.h | 17 ++++++++++++----- 2 files changed, 23 insertions(+), 24 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 6594f7fa1be..60997628cc6 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -85,21 +85,11 @@ static inline bool cpu_loop_exit_requested(const CPUSta= te *cpu) * * Return the ArchCPU associated with the environment. */ -static inline ArchCPU *env_archcpu(CPUArchState *env) -{ - return (void *)env - sizeof(CPUState); -} - -/** - * env_cpu_const(env) - * @env: The architecture environment - * - * Return the CPUState associated with the environment. - */ -static inline const CPUState *env_cpu_const(const CPUArchState *env) -{ - return (void *)env - sizeof(CPUState); -} +#define env_archcpu(env) _Generic(env, \ + CPUArchState *: \ + (ArchCPU *)((void *)env - sizeof(CPUState)), \ + const CPUArchState *: \ + (const ArchCPU *)((const void *)env - sizeof(CPUState))) =20 /** * env_cpu(env) @@ -107,9 +97,11 @@ static inline const CPUState *env_cpu_const(const CPUAr= chState *env) * * Return the CPUState associated with the environment. */ -static inline CPUState *env_cpu(CPUArchState *env) -{ - return (CPUState *)env_cpu_const(env); -} +#define env_cpu(env) _Generic(env, \ + CPUArchState *: \ + (CPUState *)((void *)(env) - sizeof(CPUState)), \ + const CPUArchState *: \ + (const CPUState *)((const void *)(env) - sizeof(CPUState))) +#define env_cpu_const(cpu) env_cpu(cpu) =20 #endif /* CPU_COMMON_H */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 81af7b9ee1a..18970ea39f5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -594,11 +594,18 @@ struct CPUState { QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=3D sizeof(CPUState) - sizeof(CPUNegativeOffsetState)); =20 -static inline CPUArchState *cpu_env(CPUState *cpu) -{ - /* We validate that CPUArchState follows CPUState in cpu-target.c */ - return (CPUArchState *)(cpu + 1); -} +/** + * cpu_env(cpu) + * @cpu: The vCPU + * + * Return the CPUArchState associated with the CPU. + */ +#define cpu_env(cpu) _Generic(cpu, \ + /* We validate that CPUArchState follows CPUState in target-info-stub.= c */ \ + CPUState *: \ + (CPUArchState *)((cpu) + 1), \ + const CPUState *: \ + (const CPUArchState *)((cpu) + 1)) =20 #ifdef CONFIG_TCG /* --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788256610; cv=none; d=zohomail.com; s=zohoarc; b=niRleNQyXCRv2R6SFUL5ssdz5513lc71AShAoYX/UCsQnVw6HvyRNVYjaFTMaiCTgfHrZ/BK2VfWVum/79311Ej24HKvzJyAso0rL9Y71fMmx0HgYcToE02ugdgDS5Q9XkoFItyrGcwn1PYcg+HSm4h7EQxImCxI2Qt0pc0xxk4= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_CSS_A=0.1 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256612458154100 Use the generic env_cpu() macro introduced in the previous commit and remove the few env_cpu_const() uses. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/exec/cpu-common.h | 1 - linux-user/elfload.c | 2 +- linux-user/i386/elfload.c | 2 +- linux-user/x86_64/elfload.c | 2 +- 4 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 60997628cc6..c14362f780d 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -102,6 +102,5 @@ static inline bool cpu_loop_exit_requested(const CPUSta= te *cpu) (CPUState *)((void *)(env) - sizeof(CPUState)), \ const CPUArchState *: \ (const CPUState *)((const void *)(env) - sizeof(CPUState))) -#define env_cpu_const(cpu) env_cpu(cpu) =20 #endif /* CPU_COMMON_H */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 88508deac50..c4bdaa146a7 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2128,7 +2128,7 @@ static int wmr_write_region(void *opaque, vaddr start, #endif static int elf_core_dump(int signr, const CPUArchState *env) { - const CPUState *cpu =3D env_cpu_const(env); + const CPUState *cpu =3D env_cpu(env); const TaskState *ts =3D (const TaskState *)get_task_state((CPUState *)= cpu); struct rlimit dumpsize; CountAndSizeRegions css; diff --git a/linux-user/i386/elfload.c b/linux-user/i386/elfload.c index 26b12001a3e..2e10f38a412 100644 --- a/linux-user/i386/elfload.c +++ b/linux-user/i386/elfload.c @@ -38,7 +38,7 @@ void elf_core_copy_regs(target_elf_gregset_t *r, const CP= UX86State *env) r->pt.es =3D tswapal(env->segs[R_ES].selector & 0xffff); r->pt.fs =3D tswapal(env->segs[R_FS].selector & 0xffff); r->pt.gs =3D tswapal(env->segs[R_GS].selector & 0xffff); - r->pt.orig_ax =3D tswapal(get_task_state(env_cpu_const(env))->orig_ax); + r->pt.orig_ax =3D tswapal(get_task_state(env_cpu(env))->orig_ax); r->pt.ip =3D tswapal(env->eip); r->pt.cs =3D tswapal(env->segs[R_CS].selector & 0xffff); r->pt.flags =3D tswapal(env->eflags); diff --git a/linux-user/x86_64/elfload.c b/linux-user/x86_64/elfload.c index 49a6f6180e0..121a8167acc 100644 --- a/linux-user/x86_64/elfload.c +++ b/linux-user/x86_64/elfload.c @@ -59,7 +59,7 @@ void elf_core_copy_regs(target_elf_gregset_t *r, const CP= UX86State *env) r->pt.dx =3D tswapal(env->regs[R_EDX]); r->pt.si =3D tswapal(env->regs[R_ESI]); r->pt.di =3D tswapal(env->regs[R_EDI]); - r->pt.orig_ax =3D tswapal(get_task_state(env_cpu_const(env))->orig_ax); + r->pt.orig_ax =3D tswapal(get_task_state(env_cpu(env))->orig_ax); r->pt.ip =3D tswapal(env->eip); r->pt.cs =3D tswapal(env->segs[R_CS].selector & 0xffff); r->pt.flags =3D tswapal(env->eflags); --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788256421; cv=none; d=zohomail.com; s=zohoarc; b=DADAeSjgjzlrdYcaUfcWnSITCrz4wmroq7BOfihhs/8Ktifkx7TKFNlkyxk/K9elyCFKtl2Iqpl6TTcc2LDOx4j/9k/Obv+ht4tg7kSM6lYl9MehXtz2d7nkm+1RajMcoIZeFPt1nDTpWOtRK1yl//QlTDXqG3mItGZbwsLrQTk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256424396154100 Mark the CPUState structure const when it is only accessed read-only. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 4 ++-- include/system/cpus.h | 4 ++-- system/cpus.c | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 18970ea39f5..328e30045ce 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -900,7 +900,7 @@ void qemu_cpu_kick(CPUState *cpu); * Returns: %true if run state is not running or if artificially stopped; * %false otherwise. */ -bool cpu_is_stopped(CPUState *cpu); +bool cpu_is_stopped(const CPUState *cpu); =20 /** * do_run_on_cpu: @@ -1007,7 +1007,7 @@ void cpu_interrupt(CPUState *cpu, int mask); * * Checks if any of interrupts in @mask are pending on @cpu. */ -static inline bool cpu_test_interrupt(CPUState *cpu, int mask) +static inline bool cpu_test_interrupt(const CPUState *cpu, int mask) { return qatomic_load_acquire(&cpu->interrupt_request) & mask; } diff --git a/include/system/cpus.h b/include/system/cpus.h index 508444ccf1c..bf36b823769 100644 --- a/include/system/cpus.h +++ b/include/system/cpus.h @@ -13,10 +13,10 @@ const AccelOpsClass *cpus_get_accel(void); #define VCPU_THREAD_NAME_SIZE 16 =20 void cpus_kick_thread(CPUState *cpu); -bool cpu_work_list_empty(CPUState *cpu); +bool cpu_work_list_empty(const CPUState *cpu); bool cpu_thread_is_idle(CPUState *cpu); bool all_cpu_threads_idle(void); -bool cpu_can_run(CPUState *cpu); +bool cpu_can_run(const CPUState *cpu); void qemu_process_cpu_events_common(CPUState *cpu); void cpu_thread_signal_created(CPUState *cpu); void cpu_thread_signal_destroyed(CPUState *cpu); diff --git a/system/cpus.c b/system/cpus.c index f37e215c586..e11a5aab6a6 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -69,12 +69,12 @@ static QemuMutex bql; */ static const AccelOpsClass *cpus_accel; =20 -bool cpu_is_stopped(CPUState *cpu) +bool cpu_is_stopped(const CPUState *cpu) { return cpu->stopped || !runstate_is_running(); } =20 -bool cpu_work_list_empty(CPUState *cpu) +bool cpu_work_list_empty(const CPUState *cpu) { return QSIMPLEQ_EMPTY_ATOMIC(&cpu->work_list); } @@ -271,7 +271,7 @@ void cpu_interrupt(CPUState *cpu, int mask) cpus_accel->handle_interrupt(cpu, mask); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256494835154100 Add the const qualifier to CPUARMState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- Ignoring one checkpatch.pl warning: WARNING: line over 80 characters #116: FILE: target/arm/cpu.h:2277: +static inline ARMSecuritySpace arm_security_space_below_el3(const CPUARM= State *env) total: 0 errors, 1 warnings, 789 lines checked --- target/arm/cpu.h | 55 ++++++++++++++++---------------- target/arm/internals.h | 65 +++++++++++++++++++------------------- target/arm/helper.c | 41 ++++++++++++------------ target/arm/tcg/debug.c | 18 +++++------ target/arm/tcg/hflags.c | 35 ++++++++++---------- target/arm/tcg/m_helper.c | 8 ++--- target/arm/tcg/op_helper.c | 2 +- 7 files changed, 114 insertions(+), 110 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e8dfc3179f2..8fc72e1c1aa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1342,9 +1342,9 @@ static inline uint64_t *sve_bswap64(uint64_t *dst, ui= nt64_t *src, int nr) void aarch64_sync_32_to_64(CPUARMState *env); void aarch64_sync_64_to_32(CPUARMState *env); =20 -int fp_exception_el(CPUARMState *env, int cur_el); -int sve_exception_el(CPUARMState *env, int cur_el); -int sme_exception_el(CPUARMState *env, int cur_el); +int fp_exception_el(const CPUARMState *env, int cur_el); +int sve_exception_el(const CPUARMState *env, int cur_el); +int sme_exception_el(const CPUARMState *env, int cur_el); =20 /** * sve_vqm1_for_el_sm: @@ -1356,10 +1356,10 @@ int sme_exception_el(CPUARMState *env, int cur_el); * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. * If @sm, compute for SVL, otherwise NVL. */ -uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); +uint32_t sve_vqm1_for_el_sm(const CPUARMState *env, int el, bool sm); =20 /* Likewise, but using @sm =3D PSTATE.SM. */ -uint32_t sve_vqm1_for_el(CPUARMState *env, int el); +uint32_t sve_vqm1_for_el(const CPUARMState *env, int el); =20 static inline bool is_a64(const CPUARMState *env) { @@ -2205,7 +2205,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **e= rrp); * an exception return to those levels. Unlike arm_security_space, * this doesn't care about the current EL. */ -ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); +ARMSecuritySpace arm_security_space_below_el3(const CPUARMState *env); =20 /** * arm_is_secure_below_el3: @@ -2214,14 +2214,14 @@ ARMSecuritySpace arm_security_space_below_el3(CPUAR= MState *env); * Return true if exception levels below EL3 are in secure state, * or would be following an exception return to those levels. */ -static inline bool arm_is_secure_below_el3(CPUARMState *env) +static inline bool arm_is_secure_below_el3(const CPUARMState *env) { ARMSecuritySpace ss =3D arm_security_space_below_el3(env); return ss =3D=3D ARMSS_Secure; } =20 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ -static inline bool arm_is_el3_or_mon(CPUARMState *env) +static inline bool arm_is_el3_or_mon(const CPUARMState *env) { assert(!arm_feature(env, ARM_FEATURE_M)); if (arm_feature(env, ARM_FEATURE_EL3)) { @@ -2243,7 +2243,7 @@ static inline bool arm_is_el3_or_mon(CPUARMState *env) * * Return the current security space of the cpu. */ -ARMSecuritySpace arm_security_space(CPUARMState *env); +ARMSecuritySpace arm_security_space(const CPUARMState *env); =20 /** * arm_is_secure: @@ -2251,7 +2251,7 @@ ARMSecuritySpace arm_security_space(CPUARMState *env); * * Return true if the processor is in secure state. */ -static inline bool arm_is_secure(CPUARMState *env) +static inline bool arm_is_secure(const CPUARMState *env) { return arm_space_is_secure(arm_security_space(env)); } @@ -2260,7 +2260,7 @@ static inline bool arm_is_secure(CPUARMState *env) * Return true if the current security state has AArch64 EL2 or AArch32 Hy= p. * This corresponds to the pseudocode EL2Enabled(). */ -static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, +static inline bool arm_is_el2_enabled_secstate(const CPUARMState *env, ARMSecuritySpace space) { assert(space !=3D ARMSS_Root); @@ -2268,44 +2268,44 @@ static inline bool arm_is_el2_enabled_secstate(CPUA= RMState *env, && (space !=3D ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); } =20 -static inline bool arm_is_el2_enabled(CPUARMState *env) +static inline bool arm_is_el2_enabled(const CPUARMState *env) { return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(e= nv)); } =20 #else -static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *e= nv) +static inline ARMSecuritySpace arm_security_space_below_el3(const CPUARMSt= ate *env) { return ARMSS_NonSecure; } =20 -static inline bool arm_is_secure_below_el3(CPUARMState *env) +static inline bool arm_is_secure_below_el3(const CPUARMState *env) { return false; } =20 -static inline bool arm_is_el3_or_mon(CPUARMState *env) +static inline bool arm_is_el3_or_mon(const CPUARMState *env) { return false; } =20 -static inline ARMSecuritySpace arm_security_space(CPUARMState *env) +static inline ARMSecuritySpace arm_security_space(const CPUARMState *env) { return ARMSS_NonSecure; } =20 -static inline bool arm_is_secure(CPUARMState *env) +static inline bool arm_is_secure(const CPUARMState *env) { return false; } =20 -static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, +static inline bool arm_is_el2_enabled_secstate(const CPUARMState *env, ARMSecuritySpace space) { return false; } =20 -static inline bool arm_is_el2_enabled(CPUARMState *env) +static inline bool arm_is_el2_enabled(const CPUARMState *env) { return false; } @@ -2317,10 +2317,11 @@ static inline bool arm_is_el2_enabled(CPUARMState *= env) * "for all purposes other than a direct read or write access of HCR_EL2." * Not included here is HCR_RW. */ -uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space= ); -uint64_t arm_hcr_el2_eff(CPUARMState *env); -uint64_t arm_hcr_el2_nvx_eff(CPUARMState *env); -uint64_t arm_hcrx_el2_eff(CPUARMState *env); +uint64_t arm_hcr_el2_eff_secstate(const CPUARMState *env, + ARMSecuritySpace space); +uint64_t arm_hcr_el2_eff(const CPUARMState *env); +uint64_t arm_hcr_el2_nvx_eff(const CPUARMState *env); +uint64_t arm_hcrx_el2_eff(const CPUARMState *env); =20 /* * Function for determining whether guest cp register reads and writes sho= uld @@ -2330,13 +2331,13 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env); * it doesn't exist at all) then there is no register banking, and all * accesses are to the non-secure version. */ -bool access_secure_reg(CPUARMState *env); +bool access_secure_reg(const CPUARMState *env); =20 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure); =20 /* Return the highest implemented Exception Level */ -static inline int arm_highest_el(CPUARMState *env) +static inline int arm_highest_el(const CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_EL3)) { return 3; @@ -2348,7 +2349,7 @@ static inline int arm_highest_el(CPUARMState *env) } =20 /* Return true if a v7M CPU is in Handler mode */ -static inline bool arm_v7m_is_handler_mode(CPUARMState *env) +static inline bool arm_v7m_is_handler_mode(const CPUARMState *env) { return env->v7m.exception !=3D 0; } @@ -2446,7 +2447,7 @@ static inline bool arm_sctlr_b(const CPUARMState *env) (env->cp15.sctlr_el[1] & SCTLR_B) !=3D 0; } =20 -uint64_t arm_sctlr(CPUARMState *env, int el); +uint64_t arm_sctlr(const CPUARMState *env, int el); =20 /* * We have more than 32-bits worth of state per TB, so we split the data diff --git a/target/arm/internals.h b/target/arm/internals.h index 8f44906a3be..f1a80c890ee 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -50,7 +50,7 @@ #define BANK_HYP 6 #define BANK_MON 7 =20 -static inline MemOp mo_endian(CPUARMState *env) +static inline MemOp mo_endian(const CPUARMState *env) { return EX_TBFLAG_ANY(env->hflags, BE_DATA) ? MO_BE : MO_LE; } @@ -452,14 +452,14 @@ static inline FloatRoundMode arm_rmode_to_sf(ARMFPRou= nding rmode) } =20 /* Return the effective value of SCR_EL3.RW */ -static inline bool arm_scr_rw_eff(CPUARMState *env) +static inline bool arm_scr_rw_eff(const CPUARMState *env) { /* * SCR_EL3.RW has an effective value of 1 if: * - we are NS and EL2 is implemented but doesn't support AArch32 * - we are S and EL2 is enabled (in which case it must be AArch64) */ - ARMCPU *cpu =3D env_archcpu(env); + const ARMCPU *cpu =3D env_archcpu(env); =20 if (env->cp15.scr_el3 & SCR_RW) { return true; @@ -473,7 +473,7 @@ static inline bool arm_scr_rw_eff(CPUARMState *env) } =20 /* Return true if the specified exception level is running in AArch64 stat= e. */ -static inline bool arm_el_is_aa64(CPUARMState *env, int el) +static inline bool arm_el_is_aa64(const CPUARMState *env, int el) { /* * This isn't valid for EL0 (if we're in EL0, is_a64() is what you wan= t, @@ -510,7 +510,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int= el) * Return the current Exception Level (as per ARMv8; note that this differs * from the ARMv7 Privilege Level). */ -static inline int arm_current_el(CPUARMState *env) +static inline int arm_current_el(const CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_M)) { return arm_v7m_is_handler_mode(env) || @@ -538,7 +538,7 @@ static inline int arm_current_el(CPUARMState *env) } } =20 -static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, +static inline bool arm_cpu_data_is_big_endian_a32(const CPUARMState *env, bool sctlr_b) { #ifdef CONFIG_USER_ONLY @@ -568,7 +568,7 @@ static inline bool arm_cpu_data_is_big_endian_a64(int e= l, uint64_t sctlr) } =20 /* Return true if the processor is in big-endian mode. */ -static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) +static inline bool arm_cpu_data_is_big_endian(const CPUARMState *env) { if (!is_a64(env)) { return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); @@ -580,7 +580,7 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMSta= te *env) } =20 #ifdef CONFIG_USER_ONLY -static inline bool arm_cpu_bswap_data(CPUARMState *env) +static inline bool arm_cpu_bswap_data(const CPUARMState *env) { return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); } @@ -1036,7 +1036,7 @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_= idx) } =20 /* Return the MMU index for a v7M CPU in the specified security state */ -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(const CPUARMState *env, bool secsta= te); =20 /* * Return true if the stage 1 translation regime is using LPAE @@ -1078,7 +1078,7 @@ static inline void arm_call_el_change_hook(ARMCPU *cp= u) } =20 /* Return the SCTLR value which controls this address translation regime */ -static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) +static inline uint64_t regime_sctlr(const CPUARMState *env, ARMMMUIdx mmu_= idx) { return env->cp15.sctlr_el[regime_el(mmu_idx)]; } @@ -1094,7 +1094,7 @@ static inline uint64_t regime_sctlr(CPUARMState *env,= ARMMMUIdx mmu_idx) R_VTCR_DS_MASK) =20 /* Return the value of the TCR controlling this translation regime */ -static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) +static inline uint64_t regime_tcr(const CPUARMState *env, ARMMMUIdx mmu_id= x) { if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { return env->cp15.vtcr_el2; @@ -1116,7 +1116,8 @@ static inline uint64_t regime_tcr(CPUARMState *env, A= RMMMUIdx mmu_idx) } =20 /* Return true if the translation regime is using LPAE format page tables = */ -static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mm= u_idx) +static inline bool regime_using_lpae_format(const CPUARMState *env, + ARMMMUIdx mmu_idx) { int el =3D regime_el(mmu_idx); if (el =3D=3D 2 || arm_el_is_aa64(env, el)) { @@ -1138,7 +1139,7 @@ static inline bool regime_using_lpae_format(CPUARMSta= te *env, ARMMMUIdx mmu_idx) * Note that the ID register BRPS field is "number of bps - 1", * and we return the actual number of breakpoints. */ -static inline int arm_num_brps(ARMCPU *cpu) +static inline int arm_num_brps(const ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, BRPS) + 1; @@ -1152,7 +1153,7 @@ static inline int arm_num_brps(ARMCPU *cpu) * Note that the ID register WRPS field is "number of wps - 1", * and we return the actual number of watchpoints. */ -static inline int arm_num_wrps(ARMCPU *cpu) +static inline int arm_num_wrps(const ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, WRPS) + 1; @@ -1166,7 +1167,7 @@ static inline int arm_num_wrps(ARMCPU *cpu) * Note that the ID register CTX_CMPS field is "number of cmps - 1", * and we return the actual number of comparators. */ -static inline int arm_num_ctx_cmps(ARMCPU *cpu) +static inline int arm_num_ctx_cmps(const ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, CTX_CMPS) + 1; @@ -1180,7 +1181,7 @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu) * Return true if the CPU is currently using the process stack * pointer, or false if it is using the main stack pointer. */ -static inline bool v7m_using_psp(CPUARMState *env) +static inline bool v7m_using_psp(const CPUARMState *env) { /* Handler mode always uses the main stack; for thread mode * the CONTROL.SPSEL bit determines the answer. @@ -1196,7 +1197,7 @@ static inline bool v7m_using_psp(CPUARMState *env) * Return the SP limit value for the current CPU security state * and stack pointer. */ -static inline uint32_t v7m_sp_limit(CPUARMState *env) +static inline uint32_t v7m_sp_limit(const CPUARMState *env) { if (v7m_using_psp(env)) { return env->v7m.psplim[env->v7m.secure]; @@ -1210,7 +1211,7 @@ static inline uint32_t v7m_sp_limit(CPUARMState *env) * Return true if the v7M CPACR permits access to the FPU for the specified * security state and privilege level. */ -static inline bool v7m_cpacr_pass(CPUARMState *env, +static inline bool v7m_cpacr_pass(const CPUARMState *env, bool is_secure, bool is_priv) { switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { @@ -1300,7 +1301,7 @@ void arm_cpu_update_vserr(ARMCPU *cpu); * * Return the full ARMMMUIdx for the translation regime for EL. */ -ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); +ARMMMUIdx arm_mmu_idx_el(const CPUARMState *env, int el); =20 /** * arm_mmu_idx: @@ -1308,7 +1309,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); * * Return the full ARMMMUIdx for the current translation regime. */ -ARMMMUIdx arm_mmu_idx(CPUARMState *env); +ARMMMUIdx arm_mmu_idx(const CPUARMState *env); =20 /** * arm_stage1_mmu_idx: @@ -1463,7 +1464,7 @@ int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mm= u_idx); int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx); =20 /* Determine if allocation tags are available. */ -static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, +static inline bool allocation_tag_access_enabled(const CPUARMState *env, i= nt el, uint64_t sctlr) { if (el < 3 @@ -1772,9 +1773,9 @@ enum MVEECIState { #define PMCCFILTR_M PMXEVTYPER_M #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) =20 -static inline uint32_t pmu_num_counters(CPUARMState *env) +static inline uint32_t pmu_num_counters(const CPUARMState *env) { - ARMCPU *cpu =3D env_archcpu(env); + const ARMCPU *cpu =3D env_archcpu(env); =20 return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT; } @@ -1814,7 +1815,7 @@ void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa64_ena= bled); void aarch64_host_initfn(Object *obj); =20 /* Return true if the gdbstub is presenting an AArch64 CPU */ -static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu) +static inline bool arm_gdbstub_is_aarch64(const ARMCPU *cpu) { return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); } @@ -1832,13 +1833,13 @@ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint= 32_t secure); uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode, bool spsel); =20 -bool el_is_in_host(CPUARMState *env, int el); +bool el_is_in_host(const CPUARMState *env, int el); =20 void aa32_max_features(ARMCPU *cpu); void aarch32_max_tcg_init(ARMCPU *cpu); -int exception_target_el(CPUARMState *env); -bool arm_singlestep_active(CPUARMState *env); -bool arm_generate_debug_exceptions(CPUARMState *env); +int exception_target_el(const CPUARMState *env); +bool arm_singlestep_active(const CPUARMState *env); +bool arm_generate_debug_exceptions(const CPUARMState *env); =20 /** * pauth_ptr_mask: @@ -1847,7 +1848,7 @@ bool arm_generate_debug_exceptions(CPUARMState *env); * Return a mask of the address bits that contain the authentication code, * given the MMU config defined by @param. */ -static inline uint64_t pauth_ptr_mask(ARMVAParameters param) +static inline uint64_t pauth_ptr_mask(const ARMVAParameters param) { int bot_pac_bit =3D 64 - param.tsz; int top_pac_bit =3D 64 - 8 * param.tbi; @@ -1903,7 +1904,7 @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *= env) * Return the maximum SVE/SME VQ for this CPU. This defines * the maximum possible size of the Zn vector registers. */ -static inline int arm_max_vq(ARMCPU *cpu) +static inline int arm_max_vq(const ARMCPU *cpu) { return MAX(cpu->sve_max_vq, cpu->sme_max_vq); } @@ -1911,7 +1912,7 @@ static inline int arm_max_vq(ARMCPU *cpu) /* * Return true if it is possible to take a fine-grained-trap to EL2. */ -static inline bool arm_fgt_active(CPUARMState *env, int el) +static inline bool arm_fgt_active(const CPUARMState *env, int el) { /* * The Arm ARM only requires the "{E2H,TGE} !=3D {1,1}" test for traps @@ -2011,7 +2012,7 @@ void vfp_clear_float_status_exc_flags(CPUARMState *en= v); * specified by mask changing to the values in val. */ void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask); -bool arm_pan_enabled(CPUARMState *env); +bool arm_pan_enabled(const CPUARMState *env); uint32_t cpsr_read_for_spsr_elx(CPUARMState *env); void cpsr_write_from_spsr_elx(CPUARMState *env, uint32_t val); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 4f30a94ecd3..0b7cf021e47 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -283,7 +283,7 @@ void arm_init_cpreg_list(ARMCPU *cpu) } } =20 -bool arm_pan_enabled(CPUARMState *env) +bool arm_pan_enabled(const CPUARMState *env) { if (is_a64(env)) { if ((arm_hcr_el2_eff(env) & (HCR_NV | HCR_NV1)) =3D=3D (HCR_NV | H= CR_NV1)) { @@ -3915,7 +3915,8 @@ static void hcr_reset(CPUARMState *env, const ARMCPRe= gInfo *ri) * Bits that are not included here: * RW (read from SCR_EL3.RW as needed) */ -uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space) +uint64_t arm_hcr_el2_eff_secstate(const CPUARMState *env, + ARMSecuritySpace space) { uint64_t ret =3D env->cp15.hcr_el2; =20 @@ -3980,7 +3981,7 @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, A= RMSecuritySpace space) return ret; } =20 -uint64_t arm_hcr_el2_eff(CPUARMState *env) +uint64_t arm_hcr_el2_eff(const CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_M)) { return 0; @@ -3988,7 +3989,7 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return arm_hcr_el2_eff_secstate(env, arm_security_space_below_el3(env)= ); } =20 -uint64_t arm_hcr_el2_nvx_eff(CPUARMState *env) +uint64_t arm_hcr_el2_nvx_eff(const CPUARMState *env) { uint64_t hcr =3D arm_hcr_el2_eff(env); =20 @@ -4001,7 +4002,7 @@ uint64_t arm_hcr_el2_nvx_eff(CPUARMState *env) /* * Corresponds to ARM pseudocode function ELIsInHost(). */ -bool el_is_in_host(CPUARMState *env, int el) +bool el_is_in_host(const CPUARMState *env, int el) { uint64_t mask; =20 @@ -4099,7 +4100,7 @@ static const ARMCPRegInfo hcrx_el2_reginfo =3D { }; =20 /* Return the effective value of HCRX_EL2. */ -uint64_t arm_hcrx_el2_eff(CPUARMState *env) +uint64_t arm_hcrx_el2_eff(const CPUARMState *env) { /* * The bits in this register behave as 0 for all purposes other than @@ -4113,7 +4114,7 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env) * This may need to be revisited for future bits. */ if (!arm_is_el2_enabled(env)) { - ARMCPU *cpu =3D env_archcpu(env); + const ARMCPU *cpu =3D env_archcpu(env); uint64_t hcrx =3D 0; =20 /* Bits which whose effective value is 1 if el2 not enabled. */ @@ -4721,7 +4722,7 @@ static const ARMCPRegInfo minimal_ras_reginfo[] =3D { * pseudocode does *not* separate out the FP trap checks, but has them * all in one function. */ -int sve_exception_el(CPUARMState *env, int el) +int sve_exception_el(const CPUARMState *env, int el) { #ifndef CONFIG_USER_ONLY if (el <=3D 1 && !el_is_in_host(env, el)) { @@ -4770,7 +4771,7 @@ int sve_exception_el(CPUARMState *env, int el) * Return the exception level to which exceptions should be taken for SME. * C.f. the ARM pseudocode function CheckSMEAccess. */ -int sme_exception_el(CPUARMState *env, int el) +int sme_exception_el(const CPUARMState *env, int el) { #ifndef CONFIG_USER_ONLY if (el <=3D 1 && !el_is_in_host(env, el)) { @@ -4818,10 +4819,10 @@ int sme_exception_el(CPUARMState *env, int el) /* * Given that SVE or SME is enabled, return the vector length for EL. */ -uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm) +uint32_t sve_vqm1_for_el_sm(const CPUARMState *env, int el, bool sm) { - ARMCPU *cpu =3D env_archcpu(env); - uint64_t *cr =3D env->vfp.zcr_el; + const ARMCPU *cpu =3D env_archcpu(env); + const uint64_t *cr =3D env->vfp.zcr_el; uint32_t map =3D cpu->sve_vq.map; uint32_t len =3D ARM_MAX_VQ - 1; =20 @@ -4856,7 +4857,7 @@ uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el,= bool sm) return ctz32(cpu->sme_vq.map); } =20 -uint32_t sve_vqm1_for_el(CPUARMState *env, int el) +uint32_t sve_vqm1_for_el(const CPUARMState *env, int el) { return sve_vqm1_for_el_sm(env, el, FIELD_EX64(env->svcr, SVCR, SM)); } @@ -9748,7 +9749,7 @@ void arm_cpu_do_interrupt(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -uint64_t arm_sctlr(CPUARMState *env, int el) +uint64_t arm_sctlr(const CPUARMState *env, int el) { /* Only EL0 needs to be adjusted for EL1&0 or EL2&0 or EL3&0 */ if (el =3D=3D 0) { @@ -10072,7 +10073,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, * Return the exception level to which FP-disabled exceptions should * be taken, or 0 if FP is enabled. */ -int fp_exception_el(CPUARMState *env, int cur_el) +int fp_exception_el(const CPUARMState *env, int cur_el) { #ifndef CONFIG_USER_ONLY uint64_t hcr_el2; @@ -10179,13 +10180,13 @@ int fp_exception_el(CPUARMState *env, int cur_el) } =20 #ifndef CONFIG_TCG -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(const CPUARMState *env, bool secsta= te) { g_assert_not_reached(); } #endif =20 -ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) +ARMMMUIdx arm_mmu_idx_el(const CPUARMState *env, int el) { ARMMMUIdx idx; uint64_t hcr; @@ -10238,7 +10239,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) return idx; } =20 -ARMMMUIdx arm_mmu_idx(CPUARMState *env) +ARMMMUIdx arm_mmu_idx(const CPUARMState *env) { return arm_mmu_idx_el(env, arm_current_el(env)); } @@ -10359,7 +10360,7 @@ void aarch64_sve_change_el(CPUARMState *env, int ol= d_el, } =20 #ifndef CONFIG_USER_ONLY -ARMSecuritySpace arm_security_space(CPUARMState *env) +ARMSecuritySpace arm_security_space(const CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_M)) { return arm_secure_to_space(env->v7m.secure); @@ -10391,7 +10392,7 @@ ARMSecuritySpace arm_security_space(CPUARMState *en= v) return arm_security_space_below_el3(env); } =20 -ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) +ARMSecuritySpace arm_security_space_below_el3(const CPUARMState *env) { assert(!arm_feature(env, ARM_FEATURE_M)); =20 diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 528d2889c3a..af800917dea 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -16,7 +16,7 @@ #include "system/tcg.h" =20 /* Return the Exception Level targeted by debug exceptions. */ -static int arm_debug_target_el(CPUARMState *env) +static int arm_debug_target_el(const CPUARMState *env) { bool secure =3D arm_is_secure(env); bool route_to_el2 =3D false; @@ -61,7 +61,7 @@ raise_exception_debug(CPUARMState *env, uint32_t excp, ui= nt32_t syndrome) } =20 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ -static bool aa64_generate_debug_exceptions(CPUARMState *env) +static bool aa64_generate_debug_exceptions(const CPUARMState *env) { int cur_el =3D arm_current_el(env); int debug_el; @@ -91,7 +91,7 @@ static bool aa64_generate_debug_exceptions(CPUARMState *e= nv) return debug_el > cur_el; } =20 -static bool aa32_generate_debug_exceptions(CPUARMState *env) +static bool aa32_generate_debug_exceptions(const CPUARMState *env) { int el =3D arm_current_el(env); =20 @@ -145,7 +145,7 @@ static bool aa32_generate_debug_exceptions(CPUARMState = *env) * CheckSoftwareStep(), where it is elided because both branches would * always return the same value. */ -bool arm_generate_debug_exceptions(CPUARMState *env) +bool arm_generate_debug_exceptions(const CPUARMState *env) { if ((env->cp15.oslsr_el1 & 1) || (env->cp15.osdlr_el1 & 1)) { return false; @@ -161,7 +161,7 @@ bool arm_generate_debug_exceptions(CPUARMState *env) * Is single-stepping active? (Note that the "is EL_D AArch64?" check * implicitly means this always returns false in pre-v8 CPUs.) */ -bool arm_singlestep_active(CPUARMState *env) +bool arm_singlestep_active(const CPUARMState *env) { return extract32(env->cp15.mdscr_el1, 0, 1) && arm_el_is_aa64(env, arm_debug_target_el(env)) @@ -169,9 +169,9 @@ bool arm_singlestep_active(CPUARMState *env) } =20 /* Return true if the linked breakpoint entry lbn passes its checks */ -static bool linked_bp_matches(ARMCPU *cpu, int lbn) +static bool linked_bp_matches(const ARMCPU *cpu, int lbn) { - CPUARMState *env =3D &cpu->env; + const CPUARMState *env =3D &cpu->env; uint64_t bcr =3D env->cp15.dbgbcr[lbn]; int brps =3D arm_num_brps(cpu); int ctx_cmps =3D arm_num_ctx_cmps(cpu); @@ -252,9 +252,9 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) return contextidr =3D=3D (uint32_t)env->cp15.dbgbvr[lbn]; } =20 -static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp) +static bool bp_wp_matches(const ARMCPU *cpu, int n, bool is_wp) { - CPUARMState *env =3D &cpu->env; + const CPUARMState *env =3D &cpu->env; uint64_t cr; int pac, hmc, ssc, wt, lbn; /* diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 296ec8101ab..ec837794287 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -14,7 +14,7 @@ #include "accel/tcg/cpu-ops.h" #include "cpregs.h" =20 -static inline bool fgt_svc(CPUARMState *env, int el) +static inline bool fgt_svc(const CPUARMState *env, int el) { /* * Assuming fine-grained-traps are active, return true if we @@ -29,7 +29,8 @@ static inline bool fgt_svc(CPUARMState *env, int el) } =20 /* Return true if memory alignment should be enforced. */ -static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t = sctlr) +static bool aprofile_require_alignment(const CPUARMState *env, + int el, uint64_t sctlr) { #ifdef CONFIG_USER_ONLY return false; @@ -65,7 +66,7 @@ static bool aprofile_require_alignment(CPUARMState *env, = int el, uint64_t sctlr) #endif } =20 -bool access_secure_reg(CPUARMState *env) +bool access_secure_reg(const CPUARMState *env) { bool ret =3D (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && @@ -74,7 +75,7 @@ bool access_secure_reg(CPUARMState *env) return ret; } =20 -static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, +static CPUARMTBFlags rebuild_hflags_common(const CPUARMState *env, int fp_= el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) { @@ -88,7 +89,7 @@ static CPUARMTBFlags rebuild_hflags_common(CPUARMState *e= nv, int fp_el, return flags; } =20 -static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, +static CPUARMTBFlags rebuild_hflags_common_32(const CPUARMState *env, int = fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) { @@ -105,7 +106,7 @@ static CPUARMTBFlags rebuild_hflags_common_32(CPUARMSta= te *env, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } =20 -static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, +static CPUARMTBFlags rebuild_hflags_m32(const CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { CPUARMTBFlags flags =3D {}; @@ -139,7 +140,7 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *en= v, int fp_el, } =20 /* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ -static bool sme_fa64(CPUARMState *env, int el) +static bool sme_fa64(const CPUARMState *env, int el) { if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { return false; @@ -164,7 +165,7 @@ static bool sme_fa64(CPUARMState *env, int el) return true; } =20 -static int neon_exception_el(CPUARMState *env, int cur_el) +static int neon_exception_el(const CPUARMState *env, int cur_el) { /* * Return the EL to trap to for A32 Neon specific traps @@ -244,7 +245,7 @@ static int neon_exception_el(CPUARMState *env, int cur_= el) return 0; } =20 -static bool arm_d32dis(CPUARMState *env, int cur_el) +static bool arm_d32dis(const CPUARMState *env, int cur_el) { bool cpacr_d32dis =3D FIELD_EX64(env->cp15.cpacr_el1, CPACR, D32DIS); =20 @@ -262,7 +263,7 @@ static bool arm_d32dis(CPUARMState *env, int cur_el) return cpacr_d32dis; } =20 -static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, +static CPUARMTBFlags rebuild_hflags_a32(const CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { CPUARMTBFlags flags =3D {}; @@ -318,7 +319,7 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *en= v, int fp_el, * Return the exception level to which exceptions should be taken for ZT0. * C.f. the ARM pseudocode function CheckSMEZT0Enabled, after the ZA check. */ -static int zt0_exception_el(CPUARMState *env, int el) +static int zt0_exception_el(const CPUARMState *env, int el) { #ifndef CONFIG_USER_ONLY if (el <=3D 1 @@ -344,7 +345,7 @@ static int zt0_exception_el(CPUARMState *env, int el) * Compare the EnFPM bits in the "Accessing FPMR" pseudocode. Note that * the floating-point enabled check will be handled separately. */ -static int fpmr_exception_el(CPUARMState *env, int el) +static int fpmr_exception_el(const CPUARMState *env, int el) { switch (el) { case 0: @@ -377,8 +378,8 @@ static int fpmr_exception_el(CPUARMState *env, int el) return 0; } =20 -static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_e= l, - ARMMMUIdx mmu_idx) +static CPUARMTBFlags rebuild_hflags_a64(const CPUARMState *env, int el, + int fp_el, ARMMMUIdx mmu_idx) { CPUARMTBFlags flags =3D {}; ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); @@ -664,7 +665,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *en= v, int el, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } =20 -static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) +static CPUARMTBFlags rebuild_hflags_internal(const CPUARMState *env) { int el =3D arm_current_el(env); int fp_el =3D fp_exception_el(env, el); @@ -733,7 +734,7 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int e= l) env->hflags =3D rebuild_hflags_a64(env, el, fp_el, mmu_idx); } =20 -static void assert_hflags_rebuild_correctly(CPUARMState *env) +static void assert_hflags_rebuild_correctly(const CPUARMState *env) { #ifdef CONFIG_DEBUG_TCG CPUARMTBFlags c =3D env->hflags; @@ -749,7 +750,7 @@ static void assert_hflags_rebuild_correctly(CPUARMState= *env) #endif } =20 -static bool mve_no_pred(CPUARMState *env) +static bool mve_no_pred(const CPUARMState *env) { /* * Return true if there is definitely no predication of MVE diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index f4ba93b291b..09084154bdd 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -156,14 +156,14 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) return 0; } =20 -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(const CPUARMState *env, bool secsta= te) { return ARMMMUIdx_MUser; } =20 #else /* !CONFIG_USER_ONLY */ =20 -static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, +static ARMMMUIdx arm_v7m_mmu_idx_all(const CPUARMState *env, bool secstate, bool priv, bool negpri) { ARMMMUIdx mmu_idx =3D ARM_MMU_IDX_M; @@ -183,7 +183,7 @@ static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, return mmu_idx; } =20 -static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, +static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(const CPUARMState *= env, bool secstate, bool= priv) { bool negpri =3D armv7m_nvic_neg_prio_requested(env->nvic, secstate); @@ -192,7 +192,7 @@ static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(= CPUARMState *env, } =20 /* Return the MMU index for a v7M CPU in the specified security state */ -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(const CPUARMState *env, bool secsta= te) { bool priv =3D arm_v7m_is_handler_mode(env) || !(env->v7m.control[secstate] & 1); diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 857e897a48d..8de3a6fdad5 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -30,7 +30,7 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) =20 -int exception_target_el(CPUARMState *env) +int exception_target_el(const CPUARMState *env) { int target_el =3D MAX(1, arm_current_el(env)); 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- target/avr/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index a818db753b2..1e4e839bd83 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -183,7 +183,7 @@ int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *= buf, int reg); int avr_print_insn(bfd_vma addr, disassemble_info *info); vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr); =20 -static inline int avr_feature(CPUAVRState *env, AVRFeature feature) +static inline int avr_feature(const CPUAVRState *env, AVRFeature feature) { return (env->features & (1U << feature)) !=3D 0; } @@ -204,12 +204,12 @@ enum { TB_FLAGS_SKIP =3D 2, }; =20 -static inline int cpu_interrupts_enabled(CPUAVRState *env) +static inline int cpu_interrupts_enabled(const CPUAVRState *env) { return env->sregI !=3D 0; } =20 -static inline uint8_t cpu_get_sreg(CPUAVRState *env) +static inline uint8_t cpu_get_sreg(const CPUAVRState *env) { return (env->sregC) << 0 | (env->sregZ) << 1 --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788256421; cv=none; d=zohomail.com; s=zohoarc; b=TeujkYmm4kvYh+Y5s7x059lYtdA9NP6dI+Qh5oMvFpwDg6Y4yaKzVurYVqqH5Ic3UQ4sfgXzgtLN9b0Br7Dc+ohmRv515M1B1AY8t/foe9L7L+lCViYV/QrmfxOTqz0FQ+xhQ2A/JFEUkxE+QClqGZXY+HIXp/9uJnrLgNbDR4E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788256421; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FYs3uPH5Pb8hS6ZkgeHaIaSrfIoM0pZKlpLy0wB+Gps=; b=UuRLO876zE4rdnRABzQdPNiIIbMim23zME0pwfJ4H21fS2k8Q7WCw4ycHALofWgRpljB9MZz6Ba3tzU7zrx4dzeoT7KOaZTdaNMHE5kVUoAaYGPEFVmPf5Xvk//mhlpQxNAkIDwxCp5HdCmugbhyoWKSzueUunU8zdywH7UELTM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788256421453106.8350261967081; Tue, 1 Sep 2026 02:53:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1LBQ-0008Cv-ES; Tue, 01 Sep 2026 05:53:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LBO-0008BH-IA for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:53:34 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LBM-0007aX-Rr for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:53:34 -0400 Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68179Dcl1892410 for ; Tue, 1 Sep 2026 09:53:31 GMT Received: from mail-qk1-f200.google.com (mail-qk1-f200.google.com [209.85.222.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gdp7c9qs3-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 01 Sep 2026 09:53:31 +0000 (GMT) Received: by mail-qk1-f200.google.com with SMTP id af79cd13be357-92e53b8a302so662037485a.1 for ; Tue, 01 Sep 2026 02:53:31 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256422574158500 @env argument is accessed without modification in hexagon_thread_is_enabled(), qualify it as const. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Brian Cain --- target/hexagon/cpu.h | 2 +- target/hexagon/cpu_helper.h | 4 ++-- target/hexagon/cpu.c | 4 ++-- target/hexagon/cpu_helper.c | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index c50fbb3f72a..e4f120eda17 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -216,7 +216,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonS= tate *env, * @return true if the @a thread_env hardware thread is * not stopped. */ -bool hexagon_thread_is_enabled(CPUHexagonState *thread_env); +bool hexagon_thread_is_enabled(const CPUHexagonState *thread_env); uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg); void hexagon_cpu_soft_reset(CPUHexagonState *env); #endif diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index d1767503156..a669091a89d 100644 --- a/target/hexagon/cpu_helper.h +++ b/target/hexagon/cpu_helper.h @@ -9,8 +9,8 @@ =20 uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index); void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old); -int get_cpu_mode(CPUHexagonState *env); -int get_exe_mode(CPUHexagonState *env); +int get_cpu_mode(const CPUHexagonState *env); +int get_exe_mode(const CPUHexagonState *env); void clear_wait_mode(CPUHexagonState *env); void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause); void hexagon_start_threads(CPUHexagonState *env, uint32_t mask); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 9765716b516..4cc6bd67c28 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -345,9 +345,9 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *c= s, } =20 #ifndef CONFIG_USER_ONLY -bool hexagon_thread_is_enabled(CPUHexagonState *env) +bool hexagon_thread_is_enabled(const CPUHexagonState *env) { - HexagonCPU *cpu =3D env_archcpu(env); + const HexagonCPU *cpu =3D env_archcpu(env); uint32_t modectl; uint32_t thread_enabled_mask; bool E_bit; diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index 64c5746c6d9..610e29a0503 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -212,9 +212,9 @@ void hexagon_ssr_set_cause(CPUHexagonState *env, uint32= _t cause) } =20 =20 -int get_exe_mode(CPUHexagonState *env) +int get_exe_mode(const CPUHexagonState *env) { - HexagonCPU *cpu; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256444025154100 x86_cpu_pending_interrupt() and x86_cpu_interrupts_enabled() only read CPU state without modification, add the const qualifiers to CPUState and CPUX86State parameters. Simplify directly using cpu_env() in x86_cpu_pending_interrupt. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- target/i386/cpu.h | 4 ++-- target/i386/cpu.c | 5 ++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 641f3ee5c2f..b0436dbf665 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2596,7 +2596,7 @@ void x86_cpu_gdb_init(CPUState *cs); int cpu_x86_support_mca_broadcast(CPUX86State *env); =20 #ifndef CONFIG_USER_ONLY -int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); +int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request); =20 bool x86_cpu_translate_for_debug(CPUState *cpu, vaddr addr, TranslateForDebugResult *result); @@ -3104,7 +3104,7 @@ static inline bool ctl_has_irq(CPUX86State *env) return (env->int_ctl & V_IRQ_MASK) && (int_prio >=3D tpr); } =20 -static inline bool x86_cpu_interrupts_enabled(CPUX86State *env) +static inline bool x86_cpu_interrupts_enabled(const CPUX86State *env) { return ((env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) || diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e5ffb10d156..1fc02cf94e6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10601,10 +10601,9 @@ static vaddr x86_cpu_get_pc(CPUState *cs) } =20 #if !defined(CONFIG_USER_ONLY) -int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) +int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + const CPUX86State *env =3D cpu_env(cs); =20 if (interrupt_request & CPU_INTERRUPT_POLL) { return CPU_INTERRUPT_POLL; --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788256478; cv=none; d=zohomail.com; s=zohoarc; b=iMU2gpv8Va48xSJUC/haebpT1fRemSdfEKALF8JhL3B6EhE5TcUToYClfOVRAwOyi3IrZx3SloQRjQZrW8Eoj/O+rpHGeveUYtoH/dZ8Ym+9lt6GSZ5mZZCb39ecL2yTyLgaKjmWivxpAQYE5u+TQ2ANdVWVtnqI3iiVD9gxVq8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788256478; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wc0yFFveao/k/OMW8MeygH5JlbqUOVDVNRms4LgrmoE=; b=LcWy08Nqyj16NrZOGueMA7p1XAHM5vPD7jCrK2HcZikWnHI3+mPvx4b5LwPLcd15+v9TskT6k7qDfhtwN/tFfomFDfpt3s3SKEJLk+xuZsxOFJhVCdhUTSzmHNVP6tJiiBlJPFpE+k7+JBiu5SD2vckZc64YVRcIcTr1lIREP5Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788256478444364.6771761280712; Tue, 1 Sep 2026 02:54:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1LBj-0000fC-0H; Tue, 01 Sep 2026 05:53:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LBe-0000ZG-4P for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:53:50 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LBc-0007cN-HJ for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:53:49 -0400 Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 681792e4705426 for ; Tue, 1 Sep 2026 09:53:47 GMT Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gdrcsh67m-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 01 Sep 2026 09:53:46 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-92ef13b61bcso938575585a.1 for ; Tue, 01 Sep 2026 02:53:46 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Tue, 01 Sep 2026 02:53:45 -0700 (PDT) X-Received: by 2002:a05:620a:c53:b0:939:47f3:c0ea with SMTP id af79cd13be357-93947f3c157mr943126385a.34.1788256425298; Tue, 01 Sep 2026 02:53:45 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Zhao Liu , Peter Maydell , Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bibo Mao , Song Gao <17746591750@163.com>, Xianglai Li Subject: [PATCH v5 10/21] target/loongarch: Constify LoongArchTLB Date: Tue, 1 Sep 2026 11:52:16 +0200 Message-ID: <20260901095229.72018-11-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901095229.72018-1-philmd@oss.qualcomm.com> References: <20260901095229.72018-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX4HD9IzCWu+tO er2xPzuOGL9B87NGkPTTNHplQx8+xUuaR19SckQwJqvES4v5ZoWvfxgFi38XpwhdKv58/H3UW2n DoLI3919CMarc2hBcwA87KveHmmSJlU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX4vZ5WuPKYkr+ tdhU9vUQ6o7mA04/6r/7Zi8UtRSQWTlCRRRKfMIw4Nv+hSKIb7dxArbistRTH2eXFZqGTmSb50T S4/oCzFYEpPQHD4F1sTtBCGFgaYo64Puz6SUBwtB5oBf2n6yRKhadQ8VTQcdlkkUQDR9aKmW0/a xWJSgw5D99bNcyTCoTqlnfA0gnFcWVQFQUV4YrwLxQou3G9IVRbmJTGOG4DOJ1KlpfKmOy3P4Cd utwCFaN2vnmcznl+1QsUJtfvFu/Km+Kr5ilm2N6sl6H6xydSIVLqmGwI9mZYtxHBsZ2b0SCuUVn LMdgiDVW3tabhMJeUKogMpuY2BvSzg+eUwiLN2NxlthySQ4X/RsvjmWOBIonCUq8SllA+FWrzj/ 8UQJ8oh2slR5bmYwoBiphb3G1Xa7P4+MXq0sQS5r6oGJXWu1r7uviduvndpjCy2R0cgces9k9Eh UtipisqYXDbinT869UQ== X-Proofpoint-GUID: QEGZJHMFFvw94p-cFpk5vl57DjVz-E1Y X-Proofpoint-ORIG-GUID: QEGZJHMFFvw94p-cFpk5vl57DjVz-E1Y X-Authority-Analysis: v=2.4 cv=QsNuG1yd c=1 sm=1 tr=0 ts=6a96a0aa cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=ttdALjtd2qF5AbuOeikA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_02,2026-08-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010087 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256478822158500 The pointed LoongArchTLB is only read, not modified: mark it const. Reviewed-by: Bibo Mao Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/loongarch/tcg/tlb_helper.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index a4b90beca65..40cc0764248 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -238,11 +238,11 @@ static uint32_t get_random_tlb(uint32_t low, uint32_t= high) * field in tlb entry contains bit[47:13], so need adjust. * virt_vpn =3D vaddr[47:13] */ -static LoongArchTLB *loongarch_tlb_search_cb(CPULoongArchState *env, - vaddr vaddr, int csr_asid, - tlb_match func) +static const LoongArchTLB * +loongarch_tlb_search_cb(CPULoongArchState *env, vaddr vaddr, + int csr_asid, tlb_match func) { - LoongArchTLB *tlb; + const LoongArchTLB *tlb; uint16_t tlb_asid, stlb_idx; uint8_t tlb_e, tlb_ps, stlb_ps; bool tlb_g; @@ -296,7 +296,7 @@ static bool loongarch_tlb_search(CPULoongArchState *env= , vaddr vaddr, { int csr_asid; tlb_match func; - LoongArchTLB *tlb; + const LoongArchTLB *tlb; CPUSysState *sys =3D env_sys(env); =20 func =3D tlb_match_any; @@ -594,7 +594,7 @@ void helper_invtlb_page_asid(CPULoongArchState *env, ta= rget_ulong info, target_ulong addr) { int asid =3D info & 0x3ff; - LoongArchTLB *tlb; + const LoongArchTLB *tlb; tlb_match func; =20 func =3D tlb_match_asid; @@ -608,7 +608,7 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *en= v, target_ulong info, target_ulong addr) { int asid =3D info & 0x3ff; - LoongArchTLB *tlb; + const LoongArchTLB *tlb; tlb_match func; =20 func =3D tlb_match_any; @@ -842,7 +842,7 @@ static TLBRet loongarch_map_tlb_entry(CPULoongArchState= *env, MMUAccessType access_type, int index, int mmu_idx) { - LoongArchTLB *tlb =3D &env->tlb[index]; + const LoongArchTLB *tlb =3D &env->tlb[index]; uint8_t tlb_ps, n; =20 tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788256597; cv=none; d=zohomail.com; s=zohoarc; b=F6RL9uFLZQBoR8wgeqIYwbwx/FlOo8RSFNefdQyX/ii2FYeMz0tTH1an1Bw4hEzg9R/BCiKsike3q1s+VYY7DuwsKB5JGpFchXvkapXhB1yVf7pEmyxFKxlAFageNXYQUGojNNYkj7uBaF36kzO8exIVq3T+IUrrN4xpqO9KABg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788256597; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=l/YzYoACAzMQZT0mHSEMi7Bfq6APst8PG0qMwh1Z/kg=; b=Q8R5B4V+TNKs4yX3CRxbmbZwxHcBv3Fg1RVT7G0Xhm9bIDqdekPVrQPHg9x0KXBCV3BvBAYiDCdrhEpFWdCTJ0t4wbtVKGxn6iJIOBptd3MPOPbJsV3lM/xxdCDReZqnCU9oxWJEPQ6sP4c7Q+V+4rmMiCufDsOj15sDTX2mXMY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788256597223676.1116291714939; Tue, 1 Sep 2026 02:56:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1LBq-0000x2-Sv; Tue, 01 Sep 2026 05:54:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LBk-0000pp-EI for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:53:56 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LBi-0007d2-PT for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:53:56 -0400 Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68179PfR1282911 for ; Tue, 1 Sep 2026 09:53:54 GMT Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gdndx9vq8-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 01 Sep 2026 09:53:53 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-933023a5980so945295385a.3 for ; Tue, 01 Sep 2026 02:53:53 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Bibo Mao --- target/loongarch/cpu.h | 6 +++--- target/loongarch/internals.h | 2 +- target/loongarch/cpu.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 97db3b453fe..ad8e7497279 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -486,7 +486,7 @@ struct LoongArchCPUClass { #define MMU_USER_IDX MMU_PLV_USER #define MMU_DA_IDX 4 =20 -static inline CPUSysState *env_sys(CPULoongArchState *env) +static inline CPUSysState *env_sys(const CPULoongArchState *env) { return env->sys_state; } @@ -496,12 +496,12 @@ static inline void set_sys_state(CPULoongArchState *e= nv, CPUSysState *sys) env->sys_state =3D sys; } =20 -static inline bool is_la64(CPULoongArchState *env) +static inline bool is_la64(const CPULoongArchState *env) { return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) =3D=3D CPUCFG1_ARCH_L= A64; } =20 -static inline bool is_va32(CPULoongArchState *env) +static inline bool is_va32(const CPULoongArchState *env) { /* VA32 if !LA64 or VA32L[1-3] */ bool va32 =3D !is_la64(env); diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index 5e9a6c7bd65..a831507f439 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -39,7 +39,7 @@ uint64_t cpu_loongarch_get_constant_timer_counter(LoongAr= chCPU *cpu); uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu); void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu, uint64_t value); -bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env); +bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env); #endif /* !CONFIG_USER_ONLY */ =20 uint64_t read_fcc(CPULoongArchState *env); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 7b601bd3728..3b3cbde882f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -96,7 +96,7 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int lev= el) } =20 /* Check if there is pending and not masked out interrupt */ -bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) +bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env) { uint32_t pending; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256637509158500 Add the const qualifier to CPULoongArchState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 20 ++++++++++---------- target/loongarch/tcg/tcg_loongarch.h | 2 +- target/loongarch/cpu_helper.c | 20 ++++++++++---------- target/loongarch/tcg/tlb_helper.c | 12 ++++++------ 4 files changed, 27 insertions(+), 27 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 54fb732d62d..61b59f3d3f3 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -30,14 +30,14 @@ typedef struct MMUContext { uint64_t pte_buddy[2]; } MMUContext; =20 -static inline bool cpu_has_ptw(CPULoongArchState *env) +static inline bool cpu_has_ptw(const CPULoongArchState *env) { - CPUSysState *sys =3D env_sys(env); + const CPUSysState *sys =3D env_sys(env); =20 return !!FIELD_EX64(sys->CSR_PWCH, CSR_PWCH, HPTW_EN); } =20 -static inline bool pte_present(CPULoongArchState *env, uint64_t entry) +static inline bool pte_present(const CPULoongArchState *env, uint64_t entr= y) { uint8_t present; =20 @@ -50,7 +50,7 @@ static inline bool pte_present(CPULoongArchState *env, ui= nt64_t entry) return !!present; } =20 -static inline bool pte_write(CPULoongArchState *env, uint64_t entry) +static inline bool pte_write(const CPULoongArchState *env, uint64_t entry) { uint8_t writable; =20 @@ -89,17 +89,17 @@ static inline bool pte_dirty(uint64_t entry) return !!FIELD_EX64(entry, TLBENTRY, D); } =20 -bool check_ps(CPULoongArchState *ent, uint8_t ps); -TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context, +bool check_ps(const CPULoongArchState *ent, uint8_t ps); +TLBRet loongarch_check_pte(const CPULoongArchState *env, MMUContext *conte= xt, MMUAccessType access_type, int mmu_idx); -TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context, +TLBRet get_physical_address(const CPULoongArchState *env, MMUContext *cont= ext, MMUAccessType access_type, int mmu_idx, int is_debug); -TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, +TLBRet loongarch_ptw(const CPULoongArchState *env, MMUContext *context, int access_type, int mmu_idx, int debug); -void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, +void get_dir_base_width(const CPULoongArchState *env, uint64_t *dir_base, uint64_t *dir_width, unsigned int level); hwaddr loongarch_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); -uint64_t loongarch_palen_mask(CPULoongArchState *env); +uint64_t loongarch_palen_mask(const CPULoongArchState *env); =20 #endif /* LOONGARCH_CPU_MMU_H */ diff --git a/target/loongarch/tcg/tcg_loongarch.h b/target/loongarch/tcg/tc= g_loongarch.h index 7fb627f2d63..0f20c60d73d 100644 --- a/target/loongarch/tcg/tcg_loongarch.h +++ b/target/loongarch/tcg/tcg_loongarch.h @@ -16,7 +16,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 -TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env, +TLBRet loongarch_get_addr_from_tlb(const CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx); =20 diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 123cad3d930..3401e7ed727 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -18,10 +18,10 @@ #include "cpu-mmu.h" #include "tcg/tcg_loongarch.h" =20 -void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, +void get_dir_base_width(const CPULoongArchState *env, uint64_t *dir_base, uint64_t *dir_width, unsigned int level) { - CPUSysState *sys =3D env_sys(env); + const CPUSysState *sys =3D env_sys(env); =20 switch (level) { case 1: @@ -48,7 +48,7 @@ void get_dir_base_width(CPULoongArchState *env, uint64_t = *dir_base, } } =20 -TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context, +TLBRet loongarch_check_pte(const CPULoongArchState *env, MMUContext *conte= xt, MMUAccessType access_type, int mmu_idx) { uint64_t plv =3D mmu_idx; @@ -111,7 +111,7 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUC= ontext *context, return TLBRET_MATCH; } =20 -static MemTxResult loongarch_cmpxchg_phys(CPUState *cs, hwaddr phys, +static MemTxResult loongarch_cmpxchg_phys(const CPUState *cs, hwaddr phys, uint64_t old, uint64_t new) { hwaddr addr1, l =3D 8; @@ -146,11 +146,11 @@ static MemTxResult loongarch_cmpxchg_phys(CPUState *c= s, hwaddr phys, return ret; } =20 -TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, +TLBRet loongarch_ptw(const CPULoongArchState *env, MMUContext *context, int access_type, int mmu_idx, int debug) { const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; - CPUState *cs =3D env_cpu(env); + const CPUState *cs =3D env_cpu(env); hwaddr index =3D 0, phys =3D 0; uint64_t palen_mask =3D loongarch_palen_mask(env); uint64_t dir_base, dir_width; @@ -273,7 +273,7 @@ restart: return ret; } =20 -static TLBRet loongarch_map_address(CPULoongArchState *env, +static TLBRet loongarch_map_address(const CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx, int is_debug) @@ -299,7 +299,7 @@ static TLBRet loongarch_map_address(CPULoongArchState *= env, return TLBRET_NOMATCH; } =20 -static hwaddr dmw_va2pa(CPULoongArchState *env, vaddr va, uint64_t dmw) +static hwaddr dmw_va2pa(const CPULoongArchState *env, vaddr va, uint64_t d= mw) { if (is_la64(env)) { return va & TARGET_VIRT_MASK; @@ -310,7 +310,7 @@ static hwaddr dmw_va2pa(CPULoongArchState *env, vaddr v= a, uint64_t dmw) } } =20 -TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context, +TLBRet get_physical_address(const CPULoongArchState *env, MMUContext *cont= ext, MMUAccessType access_type, int mmu_idx, int is_debug) { @@ -376,7 +376,7 @@ hwaddr loongarch_cpu_get_phys_addr_debug(CPUState *cs, = vaddr addr) return context.physical; } =20 -uint64_t loongarch_palen_mask(CPULoongArchState *env) +uint64_t loongarch_palen_mask(const CPULoongArchState *env) { /* PALEN stores physical address bits - 1 */ uint64_t phys_bits =3D FIELD_EX32(env->cpucfg[1], CPUCFG1, PALEN) + 1; diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 40cc0764248..6194b976c36 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -35,9 +35,9 @@ static bool tlb_match_asid(bool global, int asid, int tlb= _asid) return !global && tlb_asid =3D=3D asid; } =20 -bool check_ps(CPULoongArchState *env, uint8_t tlb_ps) +bool check_ps(const CPULoongArchState *env, uint8_t tlb_ps) { - CPUSysState *sys =3D env_sys(env); + const CPUSysState *sys =3D env_sys(env); =20 if (tlb_ps >=3D 64) { return false; @@ -239,7 +239,7 @@ static uint32_t get_random_tlb(uint32_t low, uint32_t h= igh) * virt_vpn =3D vaddr[47:13] */ static const LoongArchTLB * -loongarch_tlb_search_cb(CPULoongArchState *env, vaddr vaddr, +loongarch_tlb_search_cb(const CPULoongArchState *env, vaddr vaddr, int csr_asid, tlb_match func) { const LoongArchTLB *tlb; @@ -291,7 +291,7 @@ loongarch_tlb_search_cb(CPULoongArchState *env, vaddr v= addr, return NULL; } =20 -static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr, +static bool loongarch_tlb_search(const CPULoongArchState *env, vaddr vaddr, int *index) { int csr_asid; @@ -837,7 +837,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong = base, target_ulong odd, sys->CSR_TLBREHI =3D FIELD_DP64(sys->CSR_TLBREHI, CSR_TLBREHI, PS, ps); } =20 -static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env, +static TLBRet loongarch_map_tlb_entry(const CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int index, int mmu_idx) @@ -853,7 +853,7 @@ static TLBRet loongarch_map_tlb_entry(CPULoongArchState= *env, return loongarch_check_pte(env, context, access_type, mmu_idx); } =20 -TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env, +TLBRet loongarch_get_addr_from_tlb(const CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx) { --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256566095154100 Add the const qualifier to CPUMIPSState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- target/mips/cpu.h | 8 ++++---- target/mips/internal.h | 10 +++++----- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 319147a948c..32549791a18 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1300,7 +1300,7 @@ static inline int hflags_mmu_index(uint32_t hflags) } } =20 -static inline int mips_env_mmu_index(CPUMIPSState *env) +static inline int mips_env_mmu_index(const CPUMIPSState *env) { return hflags_mmu_index(env->hflags); } @@ -1372,19 +1372,19 @@ static inline bool ase_3d_available(const CPUMIPSSt= ate *env) } =20 /* Check presence of MSA implementation */ -static inline bool ase_msa_available(CPUMIPSState *env) +static inline bool ase_msa_available(const CPUMIPSState *env) { return env->CP0_Config3 & (1 << CP0C3_MSAP); } =20 /* Check presence of Loongson CSR instructions */ -static inline bool ase_lcsr_available(CPUMIPSState *env) +static inline bool ase_lcsr_available(const CPUMIPSState *env) { return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP); } =20 /* Check presence of multi-threading ASE implementation */ -static inline bool ase_mt_available(CPUMIPSState *env) +static inline bool ase_mt_available(const CPUMIPSState *env) { return env->CP0_Config3 & (1 << CP0C3_MT); } diff --git a/target/mips/internal.h b/target/mips/internal.h index c5c286872eb..7dba22300b1 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -165,7 +165,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val); =20 extern const VMStateDescription vmstate_mips_cpu; =20 -static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) +static inline bool cpu_mips_hw_interrupts_enabled(const CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && !(env->CP0_Status & (1 << CP0St_EXL)) && @@ -180,7 +180,7 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMI= PSState *env) } =20 /* Check if there is pending and not masked out interrupt */ -static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) +static inline bool cpu_mips_hw_interrupts_pending(const CPUMIPSState *env) { int32_t pending; int32_t status; @@ -247,9 +247,9 @@ static inline void restore_pamask(CPUMIPSState *env) } } =20 -static inline int mips_vpe_active(CPUMIPSState *env) +static inline int mips_vpe_active(const CPUMIPSState *env) { - MIPSCPU *cpu =3D env_archcpu(env); + const MIPSCPU *cpu =3D env_archcpu(env); int active =3D 1; =20 /* Check that the VPE is enabled. */ @@ -281,7 +281,7 @@ static inline int mips_vpe_active(CPUMIPSState *env) return active; } =20 -static inline int mips_vp_active(CPUMIPSState *env) +static inline int mips_vp_active(const CPUMIPSState *env) { CPUState *cs; =20 --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788256570; cv=none; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256571142158500 Add the const qualifier to S390CPU when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Ilya Leoshkevich Reviewed-by: Marc-Andr=C3=A9 Lureau Acked-by: Eric Farman --- target/s390x/cpu.h | 2 +- target/s390x/s390x-internal.h | 12 ++++++------ target/s390x/interrupt.c | 22 +++++++++++----------- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index f55b79ef8ac..998bbb0d7ff 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -854,7 +854,7 @@ static inline unsigned int s390_cpu_set_state(uint8_t c= pu_state, S390CPU *cpu) return 0; } #endif /* CONFIG_USER_ONLY */ -static inline uint8_t s390_cpu_get_state(S390CPU *cpu) +static inline uint8_t s390_cpu_get_state(const S390CPU *cpu) { return cpu->env.cpu_state; } diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index c23ee1c8476..df1297b5c67 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -333,12 +333,12 @@ void cpu_inject_clock_comparator(S390CPU *cpu); void cpu_inject_cpu_timer(S390CPU *cpu); void cpu_inject_emergency_signal(S390CPU *cpu, uint16_t src_cpu_addr); int cpu_inject_external_call(S390CPU *cpu, uint16_t src_cpu_addr); -bool s390_cpu_has_io_int(S390CPU *cpu); -bool s390_cpu_has_ext_int(S390CPU *cpu); -bool s390_cpu_has_mcck_int(S390CPU *cpu); -bool s390_cpu_has_int(S390CPU *cpu); -bool s390_cpu_has_restart_int(S390CPU *cpu); -bool s390_cpu_has_stop_int(S390CPU *cpu); +bool s390_cpu_has_io_int(const S390CPU *cpu); +bool s390_cpu_has_ext_int(const S390CPU *cpu); +bool s390_cpu_has_mcck_int(const S390CPU *cpu); +bool s390_cpu_has_int(const S390CPU *cpu); +bool s390_cpu_has_restart_int(const S390CPU *cpu); +bool s390_cpu_has_stop_int(const S390CPU *cpu); void cpu_inject_restart(S390CPU *cpu); void cpu_inject_stop(S390CPU *cpu); #endif /* CONFIG_USER_ONLY */ diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c index 1dca835c5d8..d7e3fd45e4b 100644 --- a/target/s390x/interrupt.c +++ b/target/s390x/interrupt.c @@ -139,10 +139,10 @@ void s390_crw_mchk(void) fsc->inject_crw_mchk(fs); } =20 -bool s390_cpu_has_mcck_int(S390CPU *cpu) +bool s390_cpu_has_mcck_int(const S390CPU *cpu) { QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 if (!(env->psw.mask & PSW_MASK_MCHECK)) { return false; @@ -157,10 +157,10 @@ bool s390_cpu_has_mcck_int(S390CPU *cpu) return false; } =20 -bool s390_cpu_has_ext_int(S390CPU *cpu) +bool s390_cpu_has_ext_int(const S390CPU *cpu) { QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 if (!(env->psw.mask & PSW_MASK_EXT)) { return false; @@ -199,10 +199,10 @@ bool s390_cpu_has_ext_int(S390CPU *cpu) return false; } =20 -bool s390_cpu_has_io_int(S390CPU *cpu) +bool s390_cpu_has_io_int(const S390CPU *cpu) { QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 if (!(env->psw.mask & PSW_MASK_IO)) { return false; @@ -211,21 +211,21 @@ bool s390_cpu_has_io_int(S390CPU *cpu) return qemu_s390_flic_has_io(flic, env->cregs[6]); } =20 -bool s390_cpu_has_restart_int(S390CPU *cpu) +bool s390_cpu_has_restart_int(const S390CPU *cpu) { - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 return env->pending_int & INTERRUPT_RESTART; } =20 -bool s390_cpu_has_stop_int(S390CPU *cpu) +bool s390_cpu_has_stop_int(const S390CPU *cpu) { - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 return env->pending_int & INTERRUPT_STOP; } =20 -bool s390_cpu_has_int(S390CPU *cpu) +bool s390_cpu_has_int(const S390CPU *cpu) { if (!tcg_enabled()) { return false; --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256651187154100 @iprio[] is an array only accessed read-only. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 718b66487a2..b974c2f4b4f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -646,7 +646,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env); int riscv_cpu_vsirq_pending(CPURISCVState *env); int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_prio, - uint64_t pending, uint8_t *iprio); + uint64_t pending, const uint8_t *iprio); =20 =20 bool riscv_cpu_fp_enabled(CPURISCVState *env); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ab68ce65e93..953e598babb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -869,7 +869,7 @@ uint8_t riscv_cpu_default_priority(int irq) =20 int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_prio, - uint64_t pending, uint8_t *iprio) + uint64_t pending, const uint8_t *iprio) { int irq, best_irq =3D RISCV_EXCP_NONE; unsigned int prio, best_prio =3D UINT_MAX; --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788256567; cv=none; d=zohomail.com; s=zohoarc; b=fynpPnG9P1MwVRx3B7PNbbWOEx8YmeyVUF0v0Y2ALVM+X5Rfb6n8sXcDfeqykXQ5oPomHdWB5mH08h7M9oN5LY/SgVYVcqaUxx4A6g4CPrmw3KWjP1C33sjjw1vbfCLZV2qSKI03/NF0buL5VRyA9wg6aURWlbSM2Sck9afymjA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788256567; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LlN7DBlJH2rNs5BonSHdBtLWwwfelN+OMDpoUJfdbI4=; b=UpVs7yV+YdmnODrTUELwfCZxoziDuKl5AsxOnJYZGeJEM8LCEHI7GrHXb/16oWp2eZjuEGCIeWe7bcwNZQ0WUPrlsDjtvMuYUqKbnCI4zyyBDhaMPRsL5kyg/lE4e6BxpexLfTdzBKUmRbr969gNoel7CTEVzi0dTxPY6/VMTNU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788256567950304.73099523275084; Tue, 1 Sep 2026 02:56:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1LCV-00036V-5L; Tue, 01 Sep 2026 05:54:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LCT-00031W-2M for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:54:41 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LCP-0007jQ-DK for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:54:39 -0400 Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68179HGU1975447 for ; Tue, 1 Sep 2026 09:54:36 GMT Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gdp7r1pcq-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 01 Sep 2026 09:54:36 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-934963b2bc0so711457185a.3 for ; Tue, 01 Sep 2026 02:54:36 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256569219158500 Add the const qualifier to CPURISCVState when the argument is accessed without modification. Simplify directly using cpu_env() in riscv_cpu_has_work(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/riscv/cpu.h | 51 ++++++++++++++++++----------------- target/riscv/internals.h | 2 +- target/riscv/cpu.c | 10 +++---- target/riscv/tcg/cpu_helper.c | 18 ++++++------- target/riscv/tcg/csr.c | 3 ++- 5 files changed, 44 insertions(+), 40 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b974c2f4b4f..eb40526f99e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -640,22 +640,22 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteA= rray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); uint8_t riscv_cpu_default_priority(int irq); -uint64_t riscv_cpu_all_pending(CPURISCVState *env); -int riscv_cpu_mirq_pending(CPURISCVState *env); -int riscv_cpu_sirq_pending(CPURISCVState *env); -int riscv_cpu_vsirq_pending(CPURISCVState *env); -int riscv_cpu_pending_to_irq(CPURISCVState *env, +uint64_t riscv_cpu_all_pending(const CPURISCVState *env); +int riscv_cpu_mirq_pending(const CPURISCVState *env); +int riscv_cpu_sirq_pending(const CPURISCVState *env); +int riscv_cpu_vsirq_pending(const CPURISCVState *env); +int riscv_cpu_pending_to_irq(const CPURISCVState *env, int extirq, unsigned int extirq_def_prio, uint64_t pending, const uint8_t *iprio); =20 =20 -bool riscv_cpu_fp_enabled(CPURISCVState *env); -bool riscv_cpu_vector_enabled(CPURISCVState *env); +bool riscv_cpu_fp_enabled(const CPURISCVState *env); +bool riscv_cpu_vector_enabled(const CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); -bool cpu_get_fcfien(CPURISCVState *env); -bool cpu_get_bcfien(CPURISCVState *env); -bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt); +int riscv_env_mmu_index(const CPURISCVState *env, bool ifetch); +bool cpu_get_fcfien(const CPURISCVState *env); +bool cpu_get_bcfien(const CPURISCVState *env); +bool riscv_env_smode_dbltrp_enabled(const CPURISCVState *env, bool virt); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t reta= ddr); @@ -685,7 +685,8 @@ void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bo= ol level); void riscv_cpu_interrupt(CPURISCVState *env); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ =20 -RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t); +RISCVException smstateen_acc_ok(const CPURISCVState *env, + int index, uint64_t bit); #endif /* !CONFIG_USER_ONLY */ =20 void riscv_cpu_set_mode(CPURISCVState *env, privilege_mode_t newpriv, @@ -750,20 +751,20 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) +static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env) { return env->misa_mxl; } #endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) =20 -static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) +static inline const RISCVCPUConfig *riscv_cpu_cfg(const CPURISCVState *env) { return &env_archcpu(env)->cfg; } =20 #if !defined(CONFIG_USER_ONLY) -static inline privilege_mode_t cpu_address_mode(CPURISCVState *env) +static inline privilege_mode_t cpu_address_mode(const CPURISCVState *env) { privilege_mode_t mode =3D env->priv; =20 @@ -773,7 +774,8 @@ static inline privilege_mode_t cpu_address_mode(CPURISC= VState *env) return mode; } =20 -static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mod= e) +static inline RISCVMXL cpu_get_xl(const CPURISCVState *env, + privilege_mode_t mode) { RISCVMXL xl =3D env->misa_mxl; /* @@ -801,7 +803,7 @@ static inline RISCVMXL cpu_get_xl(CPURISCVState *env, p= rivilege_mode_t mode) #if defined(TARGET_RISCV32) #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) +static inline RISCVMXL cpu_recompute_xl(const CPURISCVState *env) { #if !defined(CONFIG_USER_ONLY) return cpu_get_xl(env, env->priv); @@ -814,7 +816,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *= env) #if defined(TARGET_RISCV32) #define cpu_address_xl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL cpu_address_xl(CPURISCVState *env) +static inline RISCVMXL cpu_address_xl(const CPURISCVState *env) { #ifdef CONFIG_USER_ONLY return env->xl; @@ -826,7 +828,7 @@ static inline RISCVMXL cpu_address_xl(CPURISCVState *en= v) } #endif =20 -static inline uint16_t riscv_cpu_xlen(CPURISCVState *env) +static inline uint16_t riscv_cpu_xlen(const CPURISCVState *env) { return 16 << env->xl; } @@ -834,7 +836,7 @@ static inline uint16_t riscv_cpu_xlen(CPURISCVState *en= v) #ifdef TARGET_RISCV32 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) +static inline RISCVMXL riscv_cpu_sxl(const CPURISCVState *env) { #ifdef CONFIG_USER_ONLY return env->misa_mxl; @@ -857,7 +859,8 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) * Returns true if the effective privilege mode is modified. */ static inline QEMU_ALWAYS_INLINE -bool riscv_cpu_eff_priv(CPURISCVState *env, privilege_mode_t *priv, bool *= virt) +bool riscv_cpu_eff_priv(const CPURISCVState *env, + privilege_mode_t *priv, bool *virt) { privilege_mode_t mode =3D env->priv; bool virt_enabled =3D false; @@ -929,9 +932,9 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, u= int32_t vsew, =20 bool riscv_cpu_is_32bit(RISCVCPU *cpu); =20 -bool riscv_cpu_virt_mem_enabled(CPURISCVState *env, bool is_vm_ldst); -RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); -RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env); +bool riscv_cpu_virt_mem_enabled(const CPURISCVState *env, bool is_vm_ldst); +RISCVPmPmm riscv_pm_get_pmm(const CPURISCVState *env); +RISCVPmPmm riscv_pm_get_vm_ldst_pmm(const CPURISCVState *env); uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); =20 /* diff --git a/target/riscv/internals.h b/target/riscv/internals.h index fb2d8b3e17a..b9528209deb 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -66,7 +66,7 @@ static inline bool mmuidx_2stage(int mmu_idx) * Return the endianness for the current privilege * level, based on the MSTATUS MBE/SBE/UBE bits. */ -static inline MemOp mo_endian_env(CPURISCVState *env) +static inline MemOp mo_endian_env(const CPURISCVState *env) { bool be =3D false; #if !defined(CONFIG_USER_ONLY) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 953e598babb..6004da4ac33 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -867,7 +867,7 @@ uint8_t riscv_cpu_default_priority(int irq) return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; }; =20 -int riscv_cpu_pending_to_irq(CPURISCVState *env, +int riscv_cpu_pending_to_irq(const CPURISCVState *env, int extirq, unsigned int extirq_def_prio, uint64_t pending, const uint8_t *iprio) { @@ -911,7 +911,7 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env, * using hvip bits 13:63 from HS-mode. Those are returned in * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending(). */ -uint64_t riscv_cpu_all_pending(CPURISCVState *env) +uint64_t riscv_cpu_all_pending(const CPURISCVState *env) { uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; @@ -920,7 +920,7 @@ uint64_t riscv_cpu_all_pending(CPURISCVState *env) return (env->mip | vsgein | vstip) & env->mie; } =20 -int riscv_cpu_mirq_pending(CPURISCVState *env) +int riscv_cpu_mirq_pending(const CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & ~env->mideleg & ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); @@ -929,7 +929,7 @@ int riscv_cpu_mirq_pending(CPURISCVState *env) irqs, env->miprio); } =20 -int riscv_cpu_sirq_pending(CPURISCVState *env) +int riscv_cpu_sirq_pending(const CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & ~env->hi= deleg; uint64_t irqs_f =3D env->mvip & env->mvien & ~env->mideleg & env->sie; @@ -938,7 +938,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env) irqs | irqs_f, env->siprio); } =20 -int riscv_cpu_vsirq_pending(CPURISCVState *env) +int riscv_cpu_vsirq_pending(const CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & env->hid= eleg; uint64_t irqs_f_vs =3D env->hvip & env->hvien & ~env->hideleg & env->v= sie; diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 07d92226527..397beb356a9 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -39,7 +39,7 @@ #include "pmp.h" #include "qemu/plugin.h" =20 -int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) +int riscv_env_mmu_index(const CPURISCVState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return 0; @@ -63,7 +63,7 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) #endif } =20 -bool cpu_get_fcfien(CPURISCVState *env) +bool cpu_get_fcfien(const CPURISCVState *env) { /* no cfi extension, return false */ if (!env_archcpu(env)->cfg.ext_zicfilp) { @@ -90,7 +90,7 @@ bool cpu_get_fcfien(CPURISCVState *env) } } =20 -bool cpu_get_bcfien(CPURISCVState *env) +bool cpu_get_bcfien(const CPURISCVState *env) { /* no cfi extension, return false */ if (!env_archcpu(env)->cfg.ext_zicfiss) { @@ -119,7 +119,7 @@ bool cpu_get_bcfien(CPURISCVState *env) } } =20 -bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt) +bool riscv_env_smode_dbltrp_enabled(const CPURISCVState *env, bool virt) { #ifdef CONFIG_USER_ONLY return false; @@ -163,7 +163,7 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env,= bool virt) * M-mode: mseccfg.PMM * Other existing modes: disabled */ -RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) +RISCVPmPmm riscv_pm_get_pmm(const CPURISCVState *env) { #ifndef CONFIG_USER_ONLY privilege_mode_t priv_mode; @@ -215,7 +215,7 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) #endif } =20 -RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env) +RISCVPmPmm riscv_pm_get_vm_ldst_pmm(const CPURISCVState *env) { #ifndef CONFIG_USER_ONLY privilege_mode_t priv_mode; @@ -241,7 +241,7 @@ RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env) #endif } =20 -bool riscv_cpu_virt_mem_enabled(CPURISCVState *env, bool is_vm_ldst) +bool riscv_cpu_virt_mem_enabled(const CPURISCVState *env, bool is_vm_ldst) { #ifndef CONFIG_USER_ONLY int satp_mode =3D 0; @@ -426,7 +426,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) } =20 /* Return true is floating point support is currently enabled */ -bool riscv_cpu_fp_enabled(CPURISCVState *env) +bool riscv_cpu_fp_enabled(const CPURISCVState *env) { if (env->mstatus & MSTATUS_FS) { if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { @@ -439,7 +439,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) } =20 /* Return true is vector support is currently enabled */ -bool riscv_cpu_vector_enabled(CPURISCVState *env) +bool riscv_cpu_vector_enabled(const CPURISCVState *env) { if (env->mstatus & MSTATUS_VS) { if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 002f7e69c1f..f341865fb81 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -49,7 +49,8 @@ void riscv_set_csr_ops(int csrno, const riscv_csr_operati= ons *ops) =20 /* Predicates */ #if !defined(CONFIG_USER_ONLY) -RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t) +RISCVException smstateen_acc_ok(const CPURISCVState *env, + int index, uint64_t bit) { bool virt =3D env->virt_enabled; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256611309158500 Add the const qualifier to CPUSPARCState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- target/sparc/cpu.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 5f583ed9de2..31a16c2af03 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -680,28 +680,28 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, = target_ulong addr, #endif =20 #if defined (TARGET_SPARC64) -static inline int cpu_has_hypervisor(CPUSPARCState *env1) +static inline int cpu_has_hypervisor(const CPUSPARCState *env1) { return env1->def.features & CPU_FEATURE_HYPV; } =20 -static inline int cpu_hypervisor_mode(CPUSPARCState *env1) +static inline int cpu_hypervisor_mode(const CPUSPARCState *env1) { return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); } =20 -static inline int cpu_supervisor_mode(CPUSPARCState *env1) +static inline int cpu_supervisor_mode(const CPUSPARCState *env1) { return env1->pstate & PS_PRIV; } #else -static inline int cpu_supervisor_mode(CPUSPARCState *env1) +static inline int cpu_supervisor_mode(const CPUSPARCState *env1) { return env1->psrs; } #endif =20 -static inline int cpu_interrupts_enabled(CPUSPARCState *env1) +static inline int cpu_interrupts_enabled(const CPUSPARCState *env1) { #if !defined (TARGET_SPARC64) if (env1->psret !=3D 0) @@ -715,7 +715,7 @@ static inline int cpu_interrupts_enabled(CPUSPARCState = *env1) return 0; } =20 -static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) +static inline int cpu_pil_allowed(const CPUSPARCState *env1, int pil) { #if !defined(TARGET_SPARC64) /* level 15 is non-maskable on sparc v8 */ --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788256530; cv=none; d=zohomail.com; s=zohoarc; b=cxoIxOBfGrlmxEDu/pIsf+qW1gfEXH92nFsNuu6aq64lBsItVVunMuBOEO1DBYHsg6ANlFnUgCIb6e6XNVunqEVFsXMsUVyAPtpNl26Bkgq5kdQ6iLK/21l9A92qp6vU1x1uo7NZFJfUB4vQSUHuN032JP0gSu/Jx7keYB7+ySM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788256530; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iDP7SSBBed9OilMDhZqOv3xXCrS8V81wrx791E5ihCQ=; b=iLAMmIp/xNrXZWddzNsQvfaZHr24uxXBa2BGo9FbHPh8YpqDrt3TodmsRmexgGCtFRcs5WlmBj9gTKCAY9a9uyhyIB7GbTdUYb841sfOxM+kqZVlfEIg2U+dJZ/j3xeQeFvFxQhMcaTLchCFJfT3Ron0bXt/mfGO6PpIqhva958= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788256529994971.636736668432; Tue, 1 Sep 2026 02:55:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1LCe-0003KK-Q9; Tue, 01 Sep 2026 05:54:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LCb-0003H0-47 for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:54:49 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LCZ-0007kT-Ll for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:54:48 -0400 Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68179MIU1892621 for ; Tue, 1 Sep 2026 09:54:46 GMT Received: from mail-qk1-f200.google.com (mail-qk1-f200.google.com [209.85.222.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gdp7c9r04-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 01 Sep 2026 09:54:45 +0000 (GMT) Received: by mail-qk1-f200.google.com with SMTP id af79cd13be357-92e820609d9so900993585a.2 for ; Tue, 01 Sep 2026 02:54:45 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256531031158500 As mentioned in commit de680286b52 ("accel/tcg: Make cpu_exec_interrupt hook mandatory"): > Tricore doesn't currently implement the architectural > interrupt handling. Add a comment to help understanding why this SysemuCPUOps has_work() handler is simply always returning %true. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/tricore/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 6d448727005..82b56c3cd56 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -113,6 +113,7 @@ static void tricore_cpu_reset_hold(Object *obj, ResetTy= pe type) =20 static bool tricore_cpu_has_work(CPUState *cs) { + /* Interrupts are not implemented */ return true; } =20 --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788256593; cv=none; d=zohomail.com; s=zohoarc; b=N7oB9U0x1SAkI3+YkNn+F9hBA3XnS8GfkYqDQhKKTUjIOngUi0JiYMPBnqXGehCr7G4HV3QPwEcgU6cNDl/oS0WQCrg1v9E7stjWMIPnignSVOFYfKLvPnWrU0nYY9NNoPWVXUvJxcdX41OCVjUJuzVmlCWRxAxJWcvUa31FX4Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788256593; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HEBSDWkPfatOfZfORlKDlW+OAil/75LNccJZJS9x74U=; b=Vs7d3UB8mEfGcFO8vrqi7cmkcctnMSfik/hRaNAHpJCoGflNlGVGE7IDfTFaMoXaDFCqRBkZ5ydUleMH1GuMB90VnEeq933mtnVIeHVKr1xPCngt2rkB9Bb7eKIafIyRH0JlJTNL2ypzamXaiKEWIMaCr3kr2dG1c6KumC8VOK8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788256593471253.79551168879073; Tue, 1 Sep 2026 02:56:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1LCk-0003nI-Us; Tue, 01 Sep 2026 05:54:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LCi-0003T9-1h for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:54:56 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LCg-0007lk-IB for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:54:55 -0400 Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68178omm2973865 for ; Tue, 1 Sep 2026 09:54:53 GMT Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gdsnu0ubq-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 01 Sep 2026 09:54:53 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-93909014c85so728527585a.0 for ; Tue, 01 Sep 2026 02:54:53 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256595231158500 Add the const qualifier to CPUXtensaState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Max Filippov --- target/xtensa/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 442e98bd1ba..49d6ad9083d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -708,7 +708,7 @@ void xtensa_set_abi_call0(void); bool xtensa_abi_call0(void); #endif =20 -static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) +static inline uint32_t xtensa_replicate_windowstart(const CPUXtensaState *= env) { return env->sregs[WINDOW_START] | (env->sregs[WINDOW_START] << env->config->nareg / 4); --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1788256663; cv=none; d=zohomail.com; s=zohoarc; b=DeTqmIe8mSkWAae7FoUWqnUGAjkvHcYKRDN9mWaKOb3HlvPYz1ghpkJsd4cDAMgppKFCwF0V0BqlSvSFXBE+2luCe7hES9lyzE+Bu7UQ60s2vfqU+9XESJ6Mc58pRDmc3jFaZmUZ2FBJLHqTJ3IaHKwFJhfh5FswBBfj5Qklqe0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788256663; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bCUerKU8i6MSUxweaHPVhCPYkRB41oDv8MTEbo0FvN0=; b=JwjGvOZSOQHPWfTdDrHoYpiPqXg9ujirZl/z/um2gyNO1pC5ybqSYuSD2it+0TweOmdYL/ByZ3xYYrRyasWCfRIaNX3y42mH9G3RlQp3BFryZwrjfQSgeUJeV5dsPUtZ/vCX9f832LmKT7rYXO+oVL76/fZz2gO6bX2yT5FFFQQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788256663712509.9083605791062; Tue, 1 Sep 2026 02:57:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x1LD6-0004TT-HN; Tue, 01 Sep 2026 05:55:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LD3-0004Mu-4N for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:55:17 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x1LCz-0007nE-JJ for qemu-devel@nongnu.org; Tue, 01 Sep 2026 05:55:16 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 681798UX1211500 for ; Tue, 1 Sep 2026 09:55:02 GMT Received: from mail-qk1-f200.google.com (mail-qk1-f200.google.com [209.85.222.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gdnk8sw8s-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 01 Sep 2026 09:55:02 +0000 (GMT) Received: by mail-qk1-f200.google.com with SMTP id af79cd13be357-939281526e1so72004385a.0 for ; Tue, 01 Sep 2026 02:55:01 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Chinmay Rath , Nicholas Piggin , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Cornelia Huck , Eric Farman , Matthew Rosato , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 20/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Date: Tue, 1 Sep 2026 11:52:26 +0200 Message-ID: <20260901095229.72018-21-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901095229.72018-1-philmd@oss.qualcomm.com> References: <20260901095229.72018-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=f6p4wuyM c=1 sm=1 tr=0 ts=6a96a0f6 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=cM1bI5kxBi4gRGPUlTgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfXy8rMXZVQ0AeM GLb9PoNEIwGRHMaA6oGJAVpThRKfXxomMxlo3Me3I4YIFT0sliEFGxSjf051WyjsoKrytGrHAOd IPBuS8To1KmAYxF5GiKFEJeh3dBVjc/wrI8e0RqOeTp3pKnaOzfIt3G/SxoI/HeupfSpZAquXWX FSENkcDjVObqtL8Z3MfBdhLj9IElLrHfCd/JWWckmuWsmN+pD8SM8UNcUfMfkMj+pFBnz8wYBA6 B24P+flB0LigJTr6FBJRK7QgpILPdJYskieGYQRBdZcytp/APrLwxdXTqKYK6BL1+zbIVD3I6Sd gf+0OcKeqOe3ygOE7U6TlsHA/sJE/Z/sDAYNorRPtosIkh+/tpTFUwwuG162v8FS64fXpPBPl6A wDFnoPzbnDoQrCGxdp6ZpE4UwqrrXkEufa150mJQ+fnfjx/ZOIz+e6P/9DJ323kGbtdWQxjBccS MD8obPiUvbl6oaiEHLg== X-Proofpoint-ORIG-GUID: qzAalv1sn3asAk5QttZoMCYSK64HaUHE X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX6LwbBsiis6CJ LRieTF/1IDxyOyoyrmFa+ksaptbtc0cP7TjaeSRrSfRM/mdOY/dOPHir8Wqqj3rL55RKVDrbPlX b2/uesCMKtDuogZ62ClUOdJZKZRgjME= X-Proofpoint-GUID: qzAalv1sn3asAk5QttZoMCYSK64HaUHE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_02,2026-08-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 priorityscore=1501 suspectscore=0 impostorscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010087 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256665768154100 All functions called by target has_work() handler take a const @cpu argument. We can now fulfill the comment added in commit c2804566f6 ("target/arm: do not clear halting reason in has_work helper"), qualifying the handler const to denote its idempotency. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/sysemu-cpu-ops.h | 4 ++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 4 ++-- target/avr/cpu.c | 3 ++- target/hexagon/cpu.c | 4 ++-- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 4 ++-- target/or1k/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/cpu.c | 5 ++--- target/rx/cpu.c | 2 +- target/s390x/cpu-system.c | 4 ++-- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 4 ++-- 20 files changed, 28 insertions(+), 28 deletions(-) diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 9a45596169a..095bdcd997a 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -19,10 +19,10 @@ typedef struct SysemuCPUOps { /** * @has_work: Callback for checking if there is work to do. * - * This function should be idempotent (i.e. not change state) as + * This function is idempotent (i.e. not change state) as * it will likely be queried multiple times before a CPU resumes. */ - bool (*has_work)(CPUState *cpu); /* MANDATORY NON-NULL */ + bool (*has_work)(const CPUState *cpu); /* MANDATORY NON-NULL */ /** * @get_memory_mapping: Callback for obtaining the memory mappings. */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 7d1d036e1d3..21d4f8ac23b 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -77,7 +77,7 @@ static void alpha_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool alpha_cpu_has_work(CPUState *cs) +static bool alpha_cpu_has_work(const CPUState *cs) { /* Here we are checking to see if the CPU should wake up from HALT. We will have gotten into this state only for WTINT from PALmode. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9761bb173c1..ba66359d410 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -141,9 +141,9 @@ int arm_cpu_mmu_index(CPUState *cs, bool ifetch) * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here * unconditionally. */ -static bool arm_cpu_has_work(CPUState *cs) +static bool arm_cpu_has_work(const CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); + const ARMCPU *cpu =3D ARM_CPU(cs); =20 /* * Only another PSCI call can wake the CPU up in which case the diff --git a/target/avr/cpu.c b/target/avr/cpu.c index a01e6fa4751..a96bef46ff1 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -23,6 +23,7 @@ #include "qemu/qemu-print.h" #include "exec/translation-block.h" #include "system/address-spaces.h" +#include "hw/core/cpu.h" #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" @@ -43,7 +44,7 @@ static vaddr avr_cpu_get_pc(CPUState *cs) return cpu->env.pc_w * 2; } =20 -static bool avr_cpu_has_work(CPUState *cs) +static bool avr_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET) && cpu_interrupts_enabled(cpu_env(cs)); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 4cc6bd67c28..868aef0cde4 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -364,9 +364,9 @@ bool hexagon_thread_is_enabled(const CPUHexagonState *e= nv) return E_bit; } =20 -static bool hexagon_cpu_has_work(CPUState *cs) +static bool hexagon_cpu_has_work(const CPUState *cs) { - CPUHexagonState *env =3D cpu_env(cs); + const CPUHexagonState *env =3D cpu_env(cs); =20 return hexagon_thread_is_enabled(env) && (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 7b1309a7c38..dbf58466c24 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -134,7 +134,7 @@ static void hppa_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool hppa_cpu_has_work(CPUState *cs) +static bool hppa_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1fc02cf94e6..0606ac16664 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10638,7 +10638,7 @@ int x86_cpu_pending_interrupt(const CPUState *cs, i= nt interrupt_request) return 0; } =20 -static bool x86_cpu_has_work(CPUState *cs) +static bool x86_cpu_has_work(const CPUState *cs) { return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; } diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 3b3cbde882f..3fc208e44f8 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -110,7 +110,7 @@ bool cpu_loongarch_hw_interrupts_pending(const CPULoong= ArchState *env) #endif =20 #ifndef CONFIG_USER_ONLY -static bool loongarch_cpu_has_work(CPUState *cs) +static bool loongarch_cpu_has_work(const CPUState *cs) { bool has_work =3D false; =20 diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 523694d8fbf..da3681fab1f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -76,7 +76,7 @@ static void m68k_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool m68k_cpu_has_work(CPUState *cs) +static bool m68k_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6013a8def8e..d1d2f0ec7e3 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -127,7 +127,7 @@ static void mb_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool mb_cpu_has_work(CPUState *cs) +static bool mb_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c069aa1c0b7..0f39f8fe0a5 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -134,9 +134,9 @@ static vaddr mips_cpu_get_pc(CPUState *cs) } =20 #if !defined(CONFIG_USER_ONLY) -static bool mips_cpu_has_work(CPUState *cs) +static bool mips_cpu_has_work(const CPUState *cs) { - CPUMIPSState *env =3D cpu_env(cs); + const CPUMIPSState *env =3D cpu_env(cs); bool has_work =3D false; =20 /* diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c index 42d9351b6d7..10b13ae69cd 100644 --- a/target/or1k/cpu.c +++ b/target/or1k/cpu.c @@ -76,7 +76,7 @@ static void openrisc_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool openrisc_cpu_has_work(CPUState *cs) +static bool openrisc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER= ); } diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index ef59c56f416..c72a7168a23 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7222,7 +7222,7 @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetc= h) #endif /* CONFIG_TCG */ =20 #ifndef CONFIG_USER_ONLY -static bool ppc_cpu_has_work(CPUState *cs) +static bool ppc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6004da4ac33..5c16c52e010 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -953,10 +953,9 @@ int riscv_cpu_vsirq_pending(const CPURISCVState *env) (irqs | irqs_f_vs), env->hviprio); } =20 -static bool riscv_cpu_has_work(CPUState *cs) +static bool riscv_cpu_has_work(const CPUState *cs) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + const CPURISCVState *env =3D cpu_env(cs); /* * Definition of the WFI instruction requires it to ignore the privile= ge * mode and delegation registers, but respect individual enables diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 69946928995..dfa09a85bce 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -73,7 +73,7 @@ static void rx_restore_state_to_opc(CPUState *cs, cpu->env.pc =3D data[0]; } =20 -static bool rx_cpu_has_work(CPUState *cs) +static bool rx_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c index 84faceb3338..3a0ff46e144 100644 --- a/target/s390x/cpu-system.c +++ b/target/s390x/cpu-system.c @@ -39,9 +39,9 @@ #include "system/tcg.h" #include "hw/core/sysemu-cpu-ops.h" =20 -static bool s390_cpu_has_work(CPUState *cs) +static bool s390_cpu_has_work(const CPUState *cs) { - S390CPU *cpu =3D S390_CPU(cs); + const S390CPU *cpu =3D S390_CPU(cs); =20 /* STOPPED cpus can never wake up */ if (s390_cpu_get_state(cpu) !=3D S390_CPU_STATE_LOAD && diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 55c73a1da35..b0ed356d0f7 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -107,7 +107,7 @@ static bool superh_io_recompile_replay_branch(CPUState = *cs, return false; } =20 -static bool superh_cpu_has_work(CPUState *cs) +static bool superh_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 2baa5036871..8dd9b0d5ee3 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -783,7 +783,7 @@ static void sparc_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool sparc_cpu_has_work(CPUState *cs) +static bool sparc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && cpu_interrupts_enabled(cpu_env(cs)); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 82b56c3cd56..357f3737053 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -111,7 +111,7 @@ static void tricore_cpu_reset_hold(Object *obj, ResetTy= pe type) cpu_state_reset(cpu_env(cs)); } =20 -static bool tricore_cpu_has_work(CPUState *cs) +static bool tricore_cpu_has_work(const CPUState *cs) { /* Interrupts are not implemented */ return true; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 99c8bd4b5fb..1b299568776 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -140,9 +140,9 @@ static void xtensa_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool xtensa_cpu_has_work(CPUState *cs) +static bool xtensa_cpu_has_work(const CPUState *cs) { - CPUXtensaState *env =3D cpu_env(cs); + const CPUXtensaState *env =3D cpu_env(cs); =20 return !env->runstall && env->pending_irq_level; } --=20 2.53.0 From nobody Sat Sep 26 20:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Chinmay Rath , Nicholas Piggin , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 21/21] accel/tcg: Constify @cpu in cpu_mmu_index() and TCGCPUOps handlers Date: Tue, 1 Sep 2026 11:52:27 +0200 Message-ID: <20260901095229.72018-22-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901095229.72018-1-philmd@oss.qualcomm.com> References: <20260901095229.72018-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=f6p4wuyM c=1 sm=1 tr=0 ts=6a96a0ff cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=g_x95mRnQQNavG41apYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX5aS2/Rz0fhmD AiwpTx+hY8aNpl34Old9eq4IXSnAYAr29FX3F2DsmLz8M/WsT5evwesoOXa7BCiOZLjbODt4A7X cMVbKRxkJzlRpT5AlzpkS0ah5vm1IS5vy70CAhqAGAr6R/4u21o8cXvhut9z+tjOo0ssEALgQDp 5vYoUQxXpCejiwAzjRDjgZCfZvU8Azxzzb3nTQLrIx+7cMZAGYMXbCW9iYNIE7YGS1Ffp5LRNHA sk6DUPcCjaUNqD2vNm2pGeIzxY0VDG8QXP/sUj1vvWuKLlSqd/BidWPJ7waVkKZK+0DkFDJkkLz JyJRWsu8eY3xfz5YUKIutEXQpkOe3V2dLaiJNl8SE4ZGvBAVzuYZGL9QN2YFGq0b0z9rBIGKWy/ bWuWpMGT9vW/r1mQJUDWQaBh9YM6ELsBqyU/lBZZWqOXCyYTPyABEdAre4oyAaNzqcOCnjZXSR9 f3tO6CWTHOE2d4V3/rA== X-Proofpoint-ORIG-GUID: uVKceSmYN_xAoWmeDL1ifmPhM_VHIhlR X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX9EcTbmAwx4qB 6DTMgv0Sips2gux6G+d2FzF/6Ec00CDUbQWkzdLLBCPUokflJWLlx1JpFmBhHG++l/vXgewRM9/ RZYyESZ/UPwVJXdk0pjI3BoR6znAzhA= X-Proofpoint-GUID: uVKceSmYN_xAoWmeDL1ifmPhM_VHIhlR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_02,2026-08-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 priorityscore=1501 suspectscore=0 impostorscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010087 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1788256582458154100 All functions called by cpu_mmu_index() take a const @cpu argument. Propagate the constness to the caller (CPU state should not mutate when resolving the MMU index of the current translation regime). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- include/accel/tcg/cpu-mmu-index.h | 2 +- include/accel/tcg/cpu-ops.h | 2 +- target/alpha/cpu.h | 2 +- target/arm/internals.h | 4 ++-- target/i386/tcg/tcg-cpu.h | 2 +- target/ppc/cpu.h | 2 +- target/s390x/cpu.h | 2 +- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 6 +++--- target/hppa/cpu.c | 4 ++-- target/i386/tcg/tcg-cpu.c | 6 +++--- target/loongarch/tcg/tcg_cpu.c | 4 ++-- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 6 +++--- target/mips/cpu.c | 2 +- target/or1k/cpu.c | 4 ++-- target/ppc/cpu_init.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 4 ++-- target/sparc/cpu.c | 4 ++-- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 26 files changed, 38 insertions(+), 38 deletions(-) diff --git a/include/accel/tcg/cpu-mmu-index.h b/include/accel/tcg/cpu-mmu-= index.h index e0fb6ef91c8..01152075372 100644 --- a/include/accel/tcg/cpu-mmu-index.h +++ b/include/accel/tcg/cpu-mmu-index.h @@ -30,7 +30,7 @@ * Return the core mmu index for the current translation regime. * This function is used by generic TCG code paths. */ -static inline int cpu_mmu_index(CPUState *cs, bool ifetch) +static inline int cpu_mmu_index(const CPUState *cs, bool ifetch) { #ifdef COMPILING_PER_TARGET # ifdef CONFIG_USER_ONLY diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index a88cc4dc572..69d7ec29115 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -102,7 +102,7 @@ struct TCGCPUOps { void (*debug_excp_handler)(CPUState *cpu); =20 /** @mmu_index: Callback for choosing softmmu mmu index */ - int (*mmu_index)(CPUState *cpu, bool ifetch); + int (*mmu_index)(const CPUState *cpu, bool ifetch); =20 #ifdef CONFIG_USER_ONLY /** diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 378bd96d941..1c9f9fce20b 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -383,7 +383,7 @@ enum { =20 #define TB_FLAG_UNALIGN (1u << 1) =20 -static inline int alpha_env_mmu_index(CPUAlphaState *env) +static inline int alpha_env_mmu_index(const CPUAlphaState *env) { int ret =3D env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_= IDX; if (env->flags & ENV_FLAG_PAL_MODE) { diff --git a/target/arm/internals.h b/target/arm/internals.h index f1a80c890ee..d582cefcfa4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -55,7 +55,7 @@ static inline MemOp mo_endian(const CPUARMState *env) return EX_TBFLAG_ANY(env->hflags, BE_DATA) ? MO_BE : MO_LE; } =20 -static inline int arm_env_mmu_index(CPUARMState *env) +static inline int arm_env_mmu_index(const CPUARMState *env) { return EX_TBFLAG_ANY(env->hflags, MMUIDX); } @@ -431,7 +431,7 @@ void arm_restore_state_to_opc(CPUState *cs, #ifdef CONFIG_TCG TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); -int arm_cpu_mmu_index(CPUState *cs, bool ifetch); +int arm_cpu_mmu_index(const CPUState *cs, bool ifetch); #endif /* CONFIG_TCG */ =20 typedef enum ARMFPRounding { diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h index 85bcd61678f..1127861e337 100644 --- a/target/i386/tcg/tcg-cpu.h +++ b/target/i386/tcg/tcg-cpu.h @@ -82,6 +82,6 @@ extern const TCGCPUOps x86_tcg_ops; =20 bool tcg_cpu_realizefn(CPUState *cs, Error **errp); =20 -int x86_mmu_index_pl(CPUX86State *env, unsigned pl); +int x86_mmu_index_pl(const CPUX86State *env, unsigned pl); =20 #endif /* TCG_CPU_H */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 3fb51bbeb82..56264752c1b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1736,7 +1736,7 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint3= 2_t val); =20 /* MMU modes definitions */ #define MMU_USER_IDX 0 -static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch) +static inline int ppc_env_mmu_index(const CPUPPCState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_USER_IDX; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 998bbb0d7ff..cd5f9256b24 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -373,7 +373,7 @@ QEMU_BUILD_BUG_ON(FLAG_MASK_DAT !=3D PSW_MASK_DAT >> FL= AG_MASK_PSW_SHIFT); #define MMU_HOME_IDX 2 #define MMU_REAL_IDX 3 =20 -static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch) +static inline int s390x_env_mmu_index(const CPUS390XState *env, bool ifetc= h) { #ifdef CONFIG_USER_ONLY return MMU_USER_IDX; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 21d4f8ac23b..3bf88702dc1 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -93,7 +93,7 @@ static bool alpha_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch) +static int alpha_cpu_mmu_index(const CPUState *cs, bool ifetch) { return alpha_env_mmu_index(cpu_env(cs)); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ba66359d410..63ef00735ca 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -126,7 +126,7 @@ void arm_restore_state_to_opc(CPUState *cs, } } =20 -int arm_cpu_mmu_index(CPUState *cs, bool ifetch) +int arm_cpu_mmu_index(const CPUState *cs, bool ifetch) { return arm_env_mmu_index(cpu_env(cs)); } diff --git a/target/avr/cpu.c b/target/avr/cpu.c index a96bef46ff1..24a5a9debc9 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -50,7 +50,7 @@ static bool avr_cpu_has_work(const CPUState *cs) && cpu_interrupts_enabled(cpu_env(cs)); } =20 -static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) +static int avr_cpu_mmu_index(const CPUState *cs, bool ifetch) { return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 868aef0cde4..2bc58fc6305 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -482,11 +482,11 @@ static void hexagon_cpu_realize(DeviceState *dev, Err= or **errp) mcc->parent_realize(dev, errp); } =20 -static int hexagon_cpu_mmu_index(CPUState *cs, bool ifetch) +static int hexagon_cpu_mmu_index(const CPUState *cs, bool ifetch) { #ifndef CONFIG_USER_ONLY - CPUHexagonState *env =3D cpu_env(cs); - HexagonCPU *cpu =3D HEXAGON_CPU(cs); + const CPUHexagonState *env =3D cpu_env(cs); + const HexagonCPU *cpu =3D HEXAGON_CPU(cs); int cpu_mode; =20 BQL_LOCK_GUARD(); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index dbf58466c24..ec351302406 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -140,9 +140,9 @@ static bool hppa_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) +static int hppa_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPUHPPAState *env =3D cpu_env(cs); + const CPUHPPAState *env =3D cpu_env(cs); =20 if (env->psw & (ifetch ? PSW_C : PSW_D)) { return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e4fc212aca5..da1498ee45d 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -114,7 +114,7 @@ static void x86_restore_state_to_opc(CPUState *cs, } } =20 -int x86_mmu_index_pl(CPUX86State *env, unsigned pl) +int x86_mmu_index_pl(const CPUX86State *env, unsigned pl) { int mmu_index_32 =3D (env->hflags & HF_CS64_MASK) ? 0 : 1; int mmu_index_base =3D @@ -125,9 +125,9 @@ int x86_mmu_index_pl(CPUX86State *env, unsigned pl) return mmu_index_base + mmu_index_32; } =20 -static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) +static int x86_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPUX86State *env =3D cpu_env(cs); + const CPUX86State *env =3D cpu_env(cs); return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); } =20 diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c index 7ea2a1eb933..a26233d5eed 100644 --- a/target/loongarch/tcg/tcg_cpu.c +++ b/target/loongarch/tcg/tcg_cpu.c @@ -301,9 +301,9 @@ static void loongarch_restore_state_to_opc(CPUState *cs, set_pc(cpu_env(cs), data[0]); } =20 -static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) +static int loongarch_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPULoongArchState *env =3D cpu_env(cs); + const CPULoongArchState *env =3D cpu_env(cs); CPUSysState *sys =3D env_sys(env); =20 if (FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, PG)) { diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index da3681fab1f..f1fd2e6f14d 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -82,7 +82,7 @@ static bool m68k_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -static int m68k_cpu_mmu_index(CPUState *cs, bool ifetch) +static int m68k_cpu_mmu_index(const CPUState *cs, bool ifetch) { return cpu_env(cs)->sr & SR_S ? MMU_KERNEL_IDX : MMU_USER_IDX; } diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index d1d2f0ec7e3..524175d2236 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -133,10 +133,10 @@ static bool mb_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -static int mb_cpu_mmu_index(CPUState *cs, bool ifetch) +static int mb_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPUMBState *env =3D cpu_env(cs); - MicroBlazeCPU *cpu =3D env_archcpu(env); + const CPUMBState *env =3D cpu_env(cs); + const MicroBlazeCPU *cpu =3D env_archcpu(env); =20 /* Are we in nommu mode?. */ if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 0f39f8fe0a5..a428176d9e8 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -671,7 +671,7 @@ static const Property mips_cpu_properties[] =3D { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" =20 -static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) +static int mips_cpu_mmu_index(const CPUState *cs, bool ifunc) { return mips_env_mmu_index(cpu_env(cs)); } diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c index 10b13ae69cd..c9ab5c0f1c1 100644 --- a/target/or1k/cpu.c +++ b/target/or1k/cpu.c @@ -82,9 +82,9 @@ static bool openrisc_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) +static int openrisc_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPUOpenRISCState *env =3D cpu_env(cs); + const CPUOpenRISCState *env =3D cpu_env(cs); =20 if (env->sr & (ifetch ? SR_IME : SR_DME)) { /* The mmu is enabled; test supervisor state. */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c72a7168a23..a33a074b796 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7215,7 +7215,7 @@ static void ppc_restore_state_to_opc(CPUState *cs, cpu->env.nip =3D data[0]; } =20 -static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) +static int ppc_cpu_mmu_index(const CPUState *cs, bool ifetch) { return ppc_env_mmu_index(cpu_env(cs), ifetch); } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index cd303660f1f..a0210ca50e3 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -95,7 +95,7 @@ static const char *cpu_priv_ver_to_str(int priv_ver) return priv_spec_str; } =20 -static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) +static int riscv_cpu_mmu_index(const CPUState *cs, bool ifetch) { return riscv_env_mmu_index(cpu_env(cs), ifetch); } diff --git a/target/rx/cpu.c b/target/rx/cpu.c index dfa09a85bce..c5dfba8976a 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -78,7 +78,7 @@ static bool rx_cpu_has_work(const CPUState *cs) return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } =20 -static int rx_cpu_mmu_index(CPUState *cs, bool ifunc) +static int rx_cpu_mmu_index(const CPUState *cs, bool ifunc) { return 0; } diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index c34f4b23472..a043f1e7920 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -311,7 +311,7 @@ static const Property s390x_cpu_properties[] =3D { #include "accel/tcg/cpu-ops.h" #include "tcg/tcg_s390x.h" =20 -static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch) +static int s390x_cpu_mmu_index(const CPUState *cs, bool ifetch) { return s390x_env_mmu_index(cpu_env(cs), ifetch); } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index b0ed356d0f7..f8b33844d2a 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -113,9 +113,9 @@ static bool superh_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) +static int sh4_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPUSH4State *env =3D cpu_env(cs); + const CPUSH4State *env =3D cpu_env(cs); =20 /* * The instruction in a RTE delay slot is fetched in privileged mode, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 8dd9b0d5ee3..f1ae16c91e9 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -790,9 +790,9 @@ static bool sparc_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) +static int sparc_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPUSPARCState *env =3D cpu_env(cs); + const CPUSPARCState *env =3D cpu_env(cs); =20 #ifndef TARGET_SPARC64 if ((env->mmuregs[0] & MMU_E) =3D=3D 0) { /* MMU disabled */ diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 357f3737053..09d4270df60 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -117,7 +117,7 @@ static bool tricore_cpu_has_work(const CPUState *cs) return true; } =20 -static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch) +static int tricore_cpu_mmu_index(const CPUState *cs, bool ifetch) { return 0; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 1b299568776..8cf973632e7 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -148,7 +148,7 @@ static bool xtensa_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -static int xtensa_cpu_mmu_index(CPUState *cs, bool ifetch) +static int xtensa_cpu_mmu_index(const CPUState *cs, bool ifetch) { return xtensa_get_cring(cpu_env(cs)); } --=20 2.53.0