From nobody Sat Sep 26 20:51:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=bytedance.com ARC-Seal: i=1; a=rsa-sha256; t=1788183087; cv=none; d=zohomail.com; s=zohoarc; b=I6KXG1z4IfF+xeC17I9YEm0wobHW1DZG/sp53wB3Ij/AAdTcQ7CKiKYKSeHvvj+7Yh2qvoVHm5eOvTrstK/9co9zRbQyRWB66fVIbA40kGDkOvrkkP7ofRj/gCTlqMCxgFsWyeFNRiykypqebhiB97zOfnUTjA5ob6YJuRW3PHo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788183087; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hX7IoOxxELFt5FbNM4FyZkIsKQSlU0QuknZU3feXZe4=; b=Qfai3OkLUAYneUOsaGT9M1myzpKsC9vpniuY2ey0LEcQBUyCPKaNorMqQ1jybo07ByQH+BV6Val/qDlaOepHVLMZAZI1e6u+4w+UEx4MxpRYrafG7pi2x5qE22xapdngQCPX/eNBkrIqQppH1sXC2zjZ+NA/cMxQJhzWDhLKbeg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788183087263734.172151485218; Mon, 31 Aug 2026 06:31:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x126F-0006ZY-9Y; Mon, 31 Aug 2026 09:30:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x126C-0006WD-H1 for qemu-devel@nongnu.org; Mon, 31 Aug 2026 09:30:56 -0400 Received: from va-1-113.ptr.blmpb.com ([209.127.230.113]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x1269-0008Jn-ED for qemu-devel@nongnu.org; Mon, 31 Aug 2026 09:30:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=2212171451; d=bytedance.com; t=1788183048; h=from:subject: mime-version:from:date:message-id:subject:to:cc:reply-to:content-type: mime-version:in-reply-to:message-id; bh=hX7IoOxxELFt5FbNM4FyZkIsKQSlU0QuknZU3feXZe4=; b=RvagGaNTnoc4YSkbbRivjSYcJWfO76AXQiqxrbA4bBx2B9RtX/QkBSVTYNZ+8UYu3dSZnk Mjyk8IPhVa/2QTRGB6J9GFhHw9/Mpehm1C4FsyVWQPjIhc2uIueqDEYwig1ELHz1lbTDv9 polWTouzooMGWGtzQBRjLofnG9gau5I/UaHOsRIIzBlU9EXeYlgMz+9nJU8KJciitCPjCM zO7GnBUz0usoLI8kc9vF2aP4D1b0jvnMEkeMFQoq5Ic71gP0/KRHAqVmzG4XPygv9AhZ+N AUiJYYqFw+MlSAkcujMggt7hXuL5kn7kDff9zN0Vz5+CdCofPhOIMUk35qgk4A== X-Original-From: Mingliang Liu To: Content-Transfer-Encoding: quoted-printable Mime-Version: 1.0 Message-Id: <20260831133000.982059-2-liumingliang.dev@bytedance.com> In-Reply-To: <20260831133000.982059-1-liumingliang.dev@bytedance.com> Cc: , , , , , , , "Zhibo Hong" , "Mingliang Liu" Subject: [PATCH v2 1/3] target/riscv: Add experimental Zvabd extension support Date: Mon, 31 Aug 2026 21:29:58 +0800 References: <20260831133000.982059-1-liumingliang.dev@bytedance.com> X-Mailer: git-send-email 2.39.5 X-Lms-Return-Path: From: "Mingliang Liu" Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.127.230.113; envelope-from=liumingliang.dev@bytedance.com; helo=va-1-113.ptr.blmpb.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @bytedance.com) X-ZM-MESSAGEID: 1788183091138154100 Content-Type: text/plain; charset="utf-8" From: Zhibo Hong The draft Zvabd extension provides vector integer absolute-difference operations for image, video, and other data-processing workloads. It introduces eight new instructions: - vabd.vv, vabd.vx, vabdu.vv, and vabdu.vx support SEW values from 8 through ELEN, with SEW 64 requiring Zve64x. - vwabda.vv, vwabda.vx, vwabdau.vv, and vwabdau.vx support SEW 8 and 16 and accumulate into a double-width destination. This patch implement this instruction extension, including instruction decoder, TCG translation, and helpers, etc. The specification is under review at: https://github.com/riscv/riscv-isa-manual/pull/3279 Signed-off-by: Mingliang Liu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Joel Stanley --- disas/riscv-op.c.inc | 8 +++ disas/riscv.c | 8 +++ target/riscv/cpu.c | 1 + target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/helper.h | 26 ++++++++++ target/riscv/insn32.decode | 10 ++++ target/riscv/tcg/insn_trans/trans_rvv.c.inc | 45 +++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 6 +++ target/riscv/tcg/vector_helper.c | 56 +++++++++++++++++++++ 9 files changed, 161 insertions(+) diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc index 1d334e4857..07b56f5d52 100644 --- a/disas/riscv-op.c.inc +++ b/disas/riscv-op.c.inc @@ -490,6 +490,10 @@ OP(vaadd_vv, "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_v= s1_vm) OP(vaadd_vx, "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm) OP(vaaddu_vv, "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm) OP(vaaddu_vx, "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm) +OP(vabd_vv, "vabd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm) +OP(vabd_vx, "vabd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm) +OP(vabdu_vv, "vabdu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm) +OP(vabdu_vx, "vabdu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm) OP(vadc_vim, "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl) OP(vadc_vvm, "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl) OP(vadc_vxm, "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl) @@ -861,6 +865,10 @@ OP(vsuxei16_v, "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst= _vd_rs1_vs2_vm) OP(vsuxei32_v, "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm) OP(vsuxei64_v, "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm) OP(vsuxei8_v, "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm) +OP(vwabda_vv, "vwabda.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm) +OP(vwabda_vx, "vwabda.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm) +OP(vwabdau_vv, "vwabdau.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm) +OP(vwabdau_vx, "vwabdau.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm) OP(vwadd_vv, "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm) OP(vwadd_vx, "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm) OP(vwadd_wv, "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm) diff --git a/disas/riscv.c b/disas/riscv.c index b8099cbdf8..e0a8b3a756 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2022,6 +2022,8 @@ static const rv_opcode_data *decode_inst_opcode(rv_de= code *dec, rv_isa isa) case 48: return &op_vwredsumu_vs; case 49: return &op_vwredsum_vs; case 53: return &op_vwsll_vv; + case 61: return &op_vwabda_vv; + case 62: return &op_vwabdau_vv; } break; case 1: @@ -2164,6 +2166,8 @@ static const rv_opcode_data *decode_inst_opcode(rv_de= code *dec, rv_isa isa) break; } break; + case 21: return &op_vabd_vv; + case 22: return &op_vabdu_vv; case 23: if ((inst >> 25) & 1) { return &op_vcompress_vm; @@ -2349,6 +2353,8 @@ static const rv_opcode_data *decode_inst_opcode(rv_de= code *dec, rv_isa isa) case 46: return &op_vnclipu_wx; case 47: return &op_vnclip_wx; case 53: return &op_vwsll_vx; + case 61: return &op_vwabda_vx; + case 62: return &op_vwabdau_vx; } break; case 5: @@ -2417,6 +2423,8 @@ static const rv_opcode_data *decode_inst_opcode(rv_de= code *dec, rv_isa isa) case 13: return &op_vclmulh_vx; case 14: return &op_vslide1up_vx; case 15: return &op_vslide1down_vx; + case 21: return &op_vabd_vx; + case 22: return &op_vabdu_vx; case 16: switch ((inst >> 20) & 0b11111) { case 0: diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a13177b7b7..4b8944b051 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -220,6 +220,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), ISA_EXT_DATA_ENTRY(ztso, PRIV_VERSION_1_12_0, ext_ztso), + ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvabd, PRIV_VERSION_1_13_0, ext_zvabd), ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb), ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index f8c27a574f..6018e58195 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -83,6 +83,7 @@ BOOL_FIELD(ext_zve32x) BOOL_FIELD(ext_zve64f) BOOL_FIELD(ext_zve64d) BOOL_FIELD(ext_zve64x) +BOOL_FIELD(ext_zvabd) BOOL_FIELD(ext_zvbb) BOOL_FIELD(ext_zvbc) BOOL_FIELD(ext_zvkb) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 4fc2d3a155..3aef6e0e3e 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1350,6 +1350,32 @@ DEF_HELPER_5(vsm4k_vi, void, ptr, ptr, i32, env, i32) DEF_HELPER_4(vsm4r_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32) =20 +/* Zvabd Extension */ +DEF_HELPER_6(vabd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vabd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vabd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vabd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vabd_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vabd_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vabd_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vabd_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vabdu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vabdu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vabdu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vabdu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vabdu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vabdu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vabdu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vabdu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwabda_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwabda_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwabda_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwabda_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwabdau_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwabdau_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwabdau_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwabdau_vx_h, void, ptr, ptr, tl, ptr, env, i32) + /* CFI (zicfiss) helpers */ #ifndef CONFIG_USER_ONLY DEF_HELPER_1(ssamoswap_disabled, void, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 21272fdb50..1c991a6f42 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -1084,3 +1084,13 @@ sb_aqrl 00111 . . ..... ..... 000 ..... 0101111 @at= om_st sh_aqrl 00111 . . ..... ..... 001 ..... 0101111 @atom_st sw_aqrl 00111 . . ..... ..... 010 ..... 0101111 @atom_st sd_aqrl 00111 . . ..... ..... 011 ..... 0101111 @atom_st + +# *** Zvabd Extension *** +vabd_vv 010101 . ..... ..... 010 ..... 1010111 @r_vm +vabd_vx 010101 . ..... ..... 110 ..... 1010111 @r_vm +vabdu_vv 010110 . ..... ..... 010 ..... 1010111 @r_vm +vabdu_vx 010110 . ..... ..... 110 ..... 1010111 @r_vm +vwabda_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm +vwabda_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm +vwabdau_vv 111110 . ..... ..... 000 ..... 1010111 @r_vm +vwabdau_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg= /insn_trans/trans_rvv.c.inc index a22e2cae6c..14ef961607 100644 --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc @@ -4091,3 +4091,48 @@ GEN_INT_EXT_TRANS(vzext_vf8, 3, 2) GEN_INT_EXT_TRANS(vsext_vf2, 1, 3) GEN_INT_EXT_TRANS(vsext_vf4, 2, 4) GEN_INT_EXT_TRANS(vsext_vf8, 3, 5) + +/* Zvabd Extension */ +#define GEN_ABD_CHECK(NAME, CHECK_FN, MAX_SEW) \ +static bool NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + return CHECK_FN(s, a) && s->cfg_ptr->ext_zvabd && \ + s->sew <=3D MAX_SEW && \ + (s->sew !=3D MO_64 || s->cfg_ptr->ext_zve64x); \ +} +GEN_ABD_CHECK(vabd_vv_check, opivv_check, MO_64) +GEN_ABD_CHECK(vabd_vx_check, opivx_check, MO_64) +GEN_ABD_CHECK(vwabd_vv_check, opivv_overwrite_widen_check, MO_16) +GEN_ABD_CHECK(vwabd_vx_check, opivx_overwrite_widen_check, MO_16) + +GEN_OPIVV_TRANS(vabd_vv, vabd_vv_check) +GEN_OPIVX_TRANS(vabd_vx, vabd_vx_check) +GEN_OPIVV_TRANS(vabdu_vv, vabd_vv_check) +GEN_OPIVX_TRANS(vabdu_vx, vabd_vx_check) + +#define GEN_ABD_OPIVV_WIDEN_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + static gen_helper_gvec_4_ptr * const fns[2] =3D { \ + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ + }; \ + return s->sew <=3D MO_16 && do_opivv_widen(s, a, fns[s->sew], CHECK); \ +} + +#define GEN_ABD_OPIVX_WIDEN_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + static gen_helper_opivx * const fns[2] =3D { \ + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ + }; \ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \ + fns[s->sew], s); \ + } \ + return false; \ +} + +GEN_ABD_OPIVV_WIDEN_TRANS(vwabda_vv, vwabd_vv_check) +GEN_ABD_OPIVX_WIDEN_TRANS(vwabda_vx, vwabd_vx_check) +GEN_ABD_OPIVV_WIDEN_TRANS(vwabdau_vv, vwabd_vv_check) +GEN_ABD_OPIVX_WIDEN_TRANS(vwabdau_vx, vwabd_vx_check) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 9e3cc87f8a..4c2fb6f063 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -732,6 +732,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 + if ((cpu->cfg.ext_zvabd) && !cpu->cfg.ext_zve32x) { + error_setg(errp, + "Zvabd extensions require V or Zve* extensions"); + return; + } + if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { error_setg(errp, "zicntr requires zicsr"); diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_hel= per.c index e28d8a3d9f..bdb1efcebc 100644 --- a/target/riscv/tcg/vector_helper.c +++ b/target/riscv/tcg/vector_helper.c @@ -5906,3 +5906,59 @@ GEN_VEXT_INT_EXT(vsext_vf2_d, int64_t, int32_t, H8, = H4) GEN_VEXT_INT_EXT(vsext_vf4_w, int32_t, int8_t, H4, H1) GEN_VEXT_INT_EXT(vsext_vf4_d, int64_t, int16_t, H8, H2) GEN_VEXT_INT_EXT(vsext_vf8_d, int64_t, int8_t, H8, H1) + +/* Zvabd Extension */ +#define DO_ABD(N, M) (N > M ? N - M : M - N) +#define DO_ABDACC(N, M, D) (DO_ABD(N, M) + D) + +RVVCALL(OPIVV2, vabd_vv_b, OP_SSS_B, H1, H1, H1, DO_ABD) +RVVCALL(OPIVV2, vabd_vv_h, OP_SSS_H, H2, H2, H2, DO_ABD) +RVVCALL(OPIVV2, vabd_vv_w, OP_SSS_W, H4, H4, H4, DO_ABD) +RVVCALL(OPIVV2, vabd_vv_d, OP_SSS_D, H8, H8, H8, DO_ABD) +RVVCALL(OPIVX2, vabd_vx_b, OP_SSS_B, H1, H1, DO_ABD) +RVVCALL(OPIVX2, vabd_vx_h, OP_SSS_H, H2, H2, DO_ABD) +RVVCALL(OPIVX2, vabd_vx_w, OP_SSS_W, H4, H4, DO_ABD) +RVVCALL(OPIVX2, vabd_vx_d, OP_SSS_D, H8, H8, DO_ABD) +RVVCALL(OPIVV2, vabdu_vv_b, OP_UUU_B, H1, H1, H1, DO_ABD) +RVVCALL(OPIVV2, vabdu_vv_h, OP_UUU_H, H2, H2, H2, DO_ABD) +RVVCALL(OPIVV2, vabdu_vv_w, OP_UUU_W, H4, H4, H4, DO_ABD) +RVVCALL(OPIVV2, vabdu_vv_d, OP_UUU_D, H8, H8, H8, DO_ABD) +RVVCALL(OPIVX2, vabdu_vx_b, OP_UUU_B, H1, H1, DO_ABD) +RVVCALL(OPIVX2, vabdu_vx_h, OP_UUU_H, H2, H2, DO_ABD) +RVVCALL(OPIVX2, vabdu_vx_w, OP_UUU_W, H4, H4, DO_ABD) +RVVCALL(OPIVX2, vabdu_vx_d, OP_UUU_D, H8, H8, DO_ABD) + +RVVCALL(OPIVV3, vwabda_vv_b, WOP_SSS_B, H2, H1, H1, DO_ABDACC) +RVVCALL(OPIVV3, vwabda_vv_h, WOP_SSS_H, H4, H2, H2, DO_ABDACC) +RVVCALL(OPIVX3, vwabda_vx_b, WOP_SSS_B, H2, H1, DO_ABDACC) +RVVCALL(OPIVX3, vwabda_vx_h, WOP_SSS_H, H4, H2, DO_ABDACC) +RVVCALL(OPIVV3, vwabdau_vv_b, WOP_UUU_B, H2, H1, H1, DO_ABDACC) +RVVCALL(OPIVV3, vwabdau_vv_h, WOP_UUU_H, H4, H2, H2, DO_ABDACC) +RVVCALL(OPIVX3, vwabdau_vx_b, WOP_UUU_B, H2, H1, DO_ABDACC) +RVVCALL(OPIVX3, vwabdau_vx_h, WOP_UUU_H, H4, H2, DO_ABDACC) + +GEN_VEXT_VV(vabd_vv_b, 1) +GEN_VEXT_VV(vabd_vv_h, 2) +GEN_VEXT_VV(vabd_vv_w, 4) +GEN_VEXT_VV(vabd_vv_d, 8) +GEN_VEXT_VX(vabd_vx_b, 1) +GEN_VEXT_VX(vabd_vx_h, 2) +GEN_VEXT_VX(vabd_vx_w, 4) +GEN_VEXT_VX(vabd_vx_d, 8) +GEN_VEXT_VV(vabdu_vv_b, 1) +GEN_VEXT_VV(vabdu_vv_h, 2) +GEN_VEXT_VV(vabdu_vv_w, 4) +GEN_VEXT_VV(vabdu_vv_d, 8) +GEN_VEXT_VX(vabdu_vx_b, 1) +GEN_VEXT_VX(vabdu_vx_h, 2) +GEN_VEXT_VX(vabdu_vx_w, 4) +GEN_VEXT_VX(vabdu_vx_d, 8) + +GEN_VEXT_VV(vwabda_vv_b, 2) +GEN_VEXT_VV(vwabda_vv_h, 4) +GEN_VEXT_VX(vwabda_vx_b, 2) +GEN_VEXT_VX(vwabda_vx_h, 4) +GEN_VEXT_VV(vwabdau_vv_b, 2) +GEN_VEXT_VV(vwabdau_vv_h, 4) +GEN_VEXT_VX(vwabdau_vx_b, 2) +GEN_VEXT_VX(vwabdau_vx_h, 4) --=20 2.39.5 From nobody Sat Sep 26 20:51:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Aug 2026 09:31:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=2212171451; d=bytedance.com; t=1788183062; h=from:subject: mime-version:from:date:message-id:subject:to:cc:reply-to:content-type: mime-version:in-reply-to:message-id; bh=XWzz+bi5iJ9/n++MInW9EaBnenkOUaG+eKEP63MbxC4=; b=MfvUcoBi1ti7H7yc6RqGx1i5ONfsaQLti768TkGX7iDGUGeTuvL7Eiyz6qUoJhNGfeVPV+ XPJodb5bFO5vSz9UUgMf2oJadJyObvtbPT8qWLYA+/ZI++GkzWWXW/96sj3fBD1/4tnKwI FM0y97EqtZZ3ej0iaBT5fquwCIGWFQekJVop1vrOitYsUDi3FRWWKqF8i6e3oYPbkQMANK wm7LiJNut9cmoHLVOI1jdXsNIbLLcabi2shOLYqvhvOK0IMVvgcKssKzT6VZ94ksqEcA3g EMSGv+ZFbbxle9hJxdLUWY1i/C/lzV20CgVM5JoR+nlaX8P8PzJvnziBMv6JMA== X-Mailer: git-send-email 2.39.5 Message-Id: <20260831133000.982059-3-liumingliang.dev@bytedance.com> Subject: [PATCH v2 2/3] disas/riscv: Support vabs.v pseudo-instruction In-Reply-To: <20260831133000.982059-1-liumingliang.dev@bytedance.com> From: "Mingliang Liu" References: <20260831133000.982059-1-liumingliang.dev@bytedance.com> Cc: , , , , , , , "Mingliang Liu" Date: Mon, 31 Aug 2026 21:29:59 +0800 Mime-Version: 1.0 X-Lms-Return-Path: X-Original-From: Mingliang Liu Content-Transfer-Encoding: quoted-printable To: Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.127.230.111; envelope-from=liumingliang.dev@bytedance.com; helo=va-1-111.ptr.blmpb.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @bytedance.com) X-ZM-MESSAGEID: 1788183091472158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mingliang Liu Reviewed-by: Daniel Henrique Barboza --- disas/riscv-op.c.inc | 3 ++- disas/riscv.c | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc index 07b56f5d52..425473ee61 100644 --- a/disas/riscv-op.c.inc +++ b/disas/riscv-op.c.inc @@ -491,9 +491,10 @@ OP(vaadd_vx, "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_r= s1_vm) OP(vaaddu_vv, "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm) OP(vaaddu_vx, "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm) OP(vabd_vv, "vabd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm) -OP(vabd_vx, "vabd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm) +OP(vabd_vx, "vabd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, rvcp_vabd_vx) OP(vabdu_vv, "vabdu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm) OP(vabdu_vx, "vabdu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm) +OP(vabs_v, "vabs.v", rv_codec_illegal, rv_fmt_vd_vs2_vm) OP(vadc_vim, "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl) OP(vadc_vvm, "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl) OP(vadc_vxm, "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl) diff --git a/disas/riscv.c b/disas/riscv.c index e0a8b3a756..2aecaaa25a 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -103,6 +103,7 @@ static const rvc_constraint rvcc_j[] =3D { rvc_rd_eq_x0= , rvc_end }; static const rvc_constraint rvcc_ret[] =3D { rvc_rs1_eq_ra, rvc_end }; static const rvc_constraint rvcc_jr[] =3D { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end }; +static const rvc_constraint rvcc_vabs_v[] =3D { rvc_rs1_eq_x0, rvc_end }; static const rvc_constraint rvcc_true[] =3D { rvc_end }; =20 /* pseudo-instruction metadata */ @@ -242,6 +243,11 @@ static const rv_comp_data rvcp_fsgnjx_q[] =3D { { }, }; =20 +static const rv_comp_data rvcp_vabd_vx[] =3D { + { &op_vabs_v, rvcc_vabs_v }, + { }, +}; + /* Convert compressed insns into normal insns via pseudo expansion. */ #define DECOMP(X) &(const rv_comp_data){ &X, rvcc_true } =20 --=20 2.39.5 From nobody Sat Sep 26 20:51:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=bytedance.com ARC-Seal: i=1; a=rsa-sha256; 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dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788183108400861.2603781153941; Mon, 31 Aug 2026 06:31:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x126q-0007OP-B4; Mon, 31 Aug 2026 09:31:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x126m-0007Ex-1R for qemu-devel@nongnu.org; Mon, 31 Aug 2026 09:31:32 -0400 Received: from va-1-114.ptr.blmpb.com ([209.127.230.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x126i-0008QX-89 for qemu-devel@nongnu.org; Mon, 31 Aug 2026 09:31:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=2212171451; d=bytedance.com; t=1788183083; h=from:subject: mime-version:from:date:message-id:subject:to:cc:reply-to:content-type: mime-version:in-reply-to:message-id; bh=nBMgv9IpmIfH17xNKcX7Z1Fj11HQtpoyCmQsSm1AQjQ=; b=LDQA5d+ra91/kLdYZmDbAhcBTw1Kl9NowFztF/+u9uEUexQuzQnrGzf+2kd4EGhguhxrkk tUSIW3Yy08hzWMDdgmBReDnm3/Mi5Ntar1FG2GfEreK+3NtR/TtQqgcRapynNu+jyqhKtt b3MzoZqSDViVa2slrH1Yq2RHD7DoPr+fCUxaVdn2WMGtDqnKzp4A1EgLUPtJNA2g6tjNsw xTpxvWSKc76e/eD/QgmrCCiXJuaH9SV0o511/qP4piqE+YqzfIRUZ9/9LPtGF9vkiu7Ky4 ANEpc/Q99jKZsEq6uIapzLZNm2EJgaXn1Fht9bGy8SkqBPC2DkYStLH/MCM8OA== Cc: , , , , , , , "Mingliang Liu" Message-Id: <20260831133000.982059-4-liumingliang.dev@bytedance.com> Content-Transfer-Encoding: quoted-printable Subject: [PATCH v2 3/3] tests/tcg/riscv64: Add tests for Zvabd extension Mime-Version: 1.0 In-Reply-To: <20260831133000.982059-1-liumingliang.dev@bytedance.com> References: <20260831133000.982059-1-liumingliang.dev@bytedance.com> X-Original-From: Mingliang Liu To: From: "Mingliang Liu" Date: Mon, 31 Aug 2026 21:30:00 +0800 X-Lms-Return-Path: X-Mailer: git-send-email 2.39.5 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.127.230.114; envelope-from=liumingliang.dev@bytedance.com; helo=va-1-114.ptr.blmpb.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @bytedance.com) X-ZM-MESSAGEID: 1788183111111158500 Content-Type: text/plain; charset="utf-8" Co-Auther: Daniel Henrique Barboza Signed-off-by: Mingliang Liu Reviewed-by: Daniel Henrique Barboza --- tests/tcg/riscv64/Makefile.softmmu-target | 8 + tests/tcg/riscv64/test-zvabd.S | 659 ++++++++++++++++++++++ 2 files changed, 667 insertions(+) create mode 100644 tests/tcg/riscv64/test-zvabd.S diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/= Makefile.softmmu-target index 6a219c306c..787fdaab40 100644 --- a/tests/tcg/riscv64/Makefile.softmmu-target +++ b/tests/tcg/riscv64/Makefile.softmmu-target @@ -71,5 +71,13 @@ EXTRA_RUNS +=3D run-test-misa-w run-test-misa-w: test-misa-w $(call run-test, $<, $(QEMU) -cpu rv64$(comma)x-misa-w=3Dtrue$(comma)c=3D= true$(comma)v=3Dtrue $(QEMU_OPTS)$<) =20 +EXTRA_RUNS +=3D run-test-zvabd +ZVABD_CPU =3D rv64$(comma)v=3Dtrue$(comma)vlen=3D256$(comma)x-zvabd=3Dtrue +CLEANFILES +=3D test-zvabd +test-zvabd: test-zvabd.o $(LINK_SCRIPT) + $(LD) $(LDFLAGS) $< -o $@ +run-test-zvabd: test-zvabd + $(call run-test, $<, $(QEMU) -cpu $(ZVABD_CPU) $(QEMU_OPTS)$<) + # We don't currently support the multiarch system tests undefine MULTIARCH_TESTS diff --git a/tests/tcg/riscv64/test-zvabd.S b/tests/tcg/riscv64/test-zvabd.S new file mode 100644 index 0000000000..01db2fd7dc --- /dev/null +++ b/tests/tcg/riscv64/test-zvabd.S @@ -0,0 +1,659 @@ +/* + * Test the Zvabd vector absolute-difference instructions and the vabs.v + * pseudoinstruction. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + + .option arch, +v + .option norvc + + .text + + .global _start +_start: + /* Enable the vector unit (mstatus.VS =3D Initial). */ + li t0, 1 << 9 + csrs mstatus, t0 + + /* Route synchronous traps to trap_handler (mtvec direct mode). */ + la t0, trap_handler + csrw mtvec, t0 + + /* Run each test function. */ + call test_vabs_v + bnez a0, _exit + call test_vabs_v_mask + bnez a0, _exit + + call test_vabd_vv + bnez a0, _exit + call test_vabd_vv_mask + bnez a0, _exit + + call test_vabd_vx + bnez a0, _exit + call test_vabd_vx_mask + bnez a0, _exit + + call test_vabdu_vv + bnez a0, _exit + call test_vabdu_vv_mask + bnez a0, _exit + + call test_vabdu_vx + bnez a0, _exit + call test_vabdu_vx_mask + bnez a0, _exit + + call test_vwabda_vv + bnez a0, _exit + call test_vwabda_vv_mask + bnez a0, _exit + + call test_vwabda_vx + bnez a0, _exit + call test_vwabda_vx_mask + bnez a0, _exit + + call test_vwabdau_vv + bnez a0, _exit + call test_vwabdau_vv_mask + bnez a0, _exit + + call test_vwabdau_vx + bnez a0, _exit + call test_vwabdau_vx_mask + bnez a0, _exit + + j _exit + +test_vabs_v: + vsetivli zero, 2, e8, m1, ta, ma + + /* Load .arr_neg array in v1 */ + la t0,.arr_neg + vle8.v v1,0(t0) + + /* vabs.v v2, v1 (vabd.vx v2, v1, x0) raw opcode */ + .word 0x56106157 + + /* Load .arr_pos in v3 */ + la t1,.arr_pos + vle8.v v3,0(t1) + + /* Compare v2 and v3 into v0 */ + vmsne.vv v0,v2,v3 + vcpop.m a0,v0 + snez a0,a0 + + ret + +test_vabs_v_mask: + vsetivli zero, 2, e8, m1, ta, mu + + /* Load .arr_neg array in v1 */ + la t0, .arr_neg + vle8.v v1, 0(t0) + + /* Zero v2 using .arr_zero */ + la t0,.arr_zero + vle8.v v2,0(t0) + + /* Load .v0_mask array in v0 */ + la t1,.v0_mask + vle8.v v0,0(t1) + + /* vabs.v v2, v1, v0.t raw opcode */ + .word 0x54106157 + + /* Load .arr_masked in v3 */ + la t0,.arr_masked + vle8.v v3,0(t0) + + /* Compare v2 and v3 into v0 */ + vmsne.vv v0,v2,v3 + vcpop.m a0,v0 + snez a0,a0 + + ret + +test_vabd_vv: + /* + * Test signed vector-vector absolute difference: + * abs({-5, -7} - {5, 7}) =3D {10, 14}. + */ + vsetivli zero, 2, e8, m1, ta, mu + + /* Load the two signed source vectors into v1 and v3. */ + la t0, .arr_neg + vle8.v v1, 0(t0) + la t0, .arr_pos + vle8.v v3, 0(t0) + + /* Execute vabd.vv v2, v1, v3. */ + .word 0x5611a157 + + /* Load the expected result into v3. */ + la t0, .expect_vabd_vv + vle8.v v3, 0(t0) + + /* Compare v2 and v3 into v0 */ + vmsne.vv v0, v2, v3 + vcpop.m a0, v0 + snez a0, a0 + + ret + +test_vabd_vv_mask: + /* + * Test masked vabd.vv. Element 0 remains 9 and element 1 becomes + * abs(-7 - 7) =3D 14. + */ + vsetivli zero, 2, e8, m1, ta, mu + + /* Load the two signed source vectors into v1 and v3. */ + la t0, .arr_neg + vle8.v v1, 0(t0) + la t0, .arr_pos + vle8.v v3, 0(t0) + + /* Load original value into v2 */ + la t0, .arr_init + vle8.v v2, 0(t0) + + /* Load mask value into v0 */ + la t0, .v0_mask + vle8.v v0, 0(t0) + + .word 0x5411a157 + + /* Load the expected result into v3. */ + la t0, .expect_vabd_vv_masked + vle8.v v3, 0(t0) + + vmsne.vv v0, v2, v3 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vabd_vx: + /* + * Test signed vector-scalar absolute difference: + * abs({-5, -7} - 3) =3D {8, 10}. + */ + vsetivli zero, 2, e8, m1, ta, mu + la t0, .arr_neg + vle8.v v1, 0(t0) + li a2, 3 + + /* Execute vabd.vx v2, v1, a2. */ + .word 0x56166157 + + /* Load the expected result into v3. */ + la t0, .expect_vabd_vx + vle8.v v3, 0(t0) + + vmsne.vv v0, v2, v3 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vabd_vx_mask: + /* + * Test masked vabd.vx. Element 0 remains 9 and element 1 becomes + * abs(-7 - 3) =3D 10. + */ + vsetivli zero, 2, e8, m1, ta, mu + + la t0, .arr_neg + vle8.v v1, 0(t0) + li a2, 3 + + la t0, .arr_init + vle8.v v2, 0(t0) + + la t0, .v0_mask + vle8.v v0, 0(t0) + + .word 0x54166157 + + la t0, .expect_vabd_vx_masked + vle8.v v3, 0(t0) + + vmsne.vv v0, v2, v3 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vabdu_vv: + /* + * Test unsigned vector-vector absolute difference: + * abs({0, 255} - {255, 0}) =3D {255, 255}. + */ + vsetivli zero, 2, e8, m1, ta, mu + + /* Load the two unsigned source vectors into v1 and v3. */ + la t0, .arr_unsigned_lhs + vle8.v v1, 0(t0) + la t0, .arr_unsigned_rhs + vle8.v v3, 0(t0) + + /* Execute vabdu.vv v2, v1, v3. */ + .word 0x5a11a157 + + /* Load the expected result into v3. */ + la t0, .expect_vabdu_vv + vle8.v v3, 0(t0) + + vmsne.vv v0, v2, v3 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vabdu_vv_mask: + /* + * Test masked vabdu.vv. Element 0 remains 9 and element 1 becomes + * abs(255 - 0) =3D 255. + */ + vsetivli zero, 2, e8, m1, ta, mu + + la t0, .arr_unsigned_lhs + vle8.v v1, 0(t0) + la t0, .arr_unsigned_rhs + vle8.v v3, 0(t0) + + la t0, .arr_init + vle8.v v2, 0(t0) + + la t0, .v0_mask + vle8.v v0, 0(t0) + + .word 0x5811a157 + + la t0, .expect_vabdu_vv_masked + vle8.v v3, 0(t0) + + vmsne.vv v0, v2, v3 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vabdu_vx: + /* + * Test unsigned vector-scalar absolute difference: + * abs({0, 255} - 128) =3D {128, 127}. + */ + vsetivli zero, 2, e8, m1, ta, mu + + la t0, .arr_unsigned_lhs + vle8.v v1, 0(t0) + li a2, 128 + + /* Execute vabdu.vx v2, v1, a2. */ + .word 0x5a166157 + + la t0, .expect_vabdu_vx + vle8.v v3, 0(t0) + + vmsne.vv v0, v2, v3 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vabdu_vx_mask: + /* + * Test masked vabdu.vx. Element 0 remains 9 and element 1 becomes + * abs(255 - 128) =3D 127. + */ + vsetivli zero, 2, e8, m1, ta, mu + + la t0, .arr_unsigned_lhs + vle8.v v1, 0(t0) + li a2, 128 + + la t0, .arr_init + vle8.v v2, 0(t0) + + la t0, .v0_mask + vle8.v v0, 0(t0) + + .word 0x58166157 + + la t0, .expect_vabdu_vx_masked + vle8.v v3, 0(t0) + + vmsne.vv v0, v2, v3 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vwabda_vv: + /* + * Test signed widening vector-vector absolute difference and + * accumulation. Start with v4 =3D {1000, -1000}, and the expected + * widened result is {1000, -1000} + abs({-5, -7} - {5, 7}) =3D + * {1010, -986}. + */ + /* Load the 16-bit accumulator before selecting 8-bit operands. */ + vsetivli zero, 2, e16, m2, ta, mu + la t0, .arr_signed_acc + vle16.v v4, 0(t0) + + vsetivli zero, 2, e8, m1, ta, mu + la t0, .arr_neg + vle8.v v1, 0(t0) + la t0, .arr_pos + vle8.v v2, 0(t0) + + /* Execute vwabda.vv v4, v1, v2. */ + .word 0xf6110257 + + /* Select the widened EEW and compare v4 with the expected result. */ + vsetivli zero, 2, e16, m2, ta, mu + la t0, .expect_vwabda_vv + vle16.v v6, 0(t0) + + vmsne.vv v0, v4, v6 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vwabda_vv_mask: + /* + * Test masked vwabda.vv. + * Start with v4 =3D {1000, -1000}, v0 =3D {0, 1}, and the expected widen= ed + * result is {1000, -1000} + abs({-5, -7} - {5, 7}) =3D {1000, -986}. + */ + vsetivli zero, 2, e16, m2, ta, mu + la t0, .arr_signed_acc + vle16.v v4, 0(t0) + + vsetivli zero, 2, e8, m1, ta, mu + la t0, .arr_neg + vle8.v v1, 0(t0) + la t0, .arr_pos + vle8.v v2, 0(t0) + + la t0, .v0_mask + vle8.v v0, 0(t0) + + .word 0xf4110257 + + vsetivli zero, 2, e16, m2, ta, mu + la t0, .expect_vwabda_vv_masked + + vle16.v v6, 0(t0) + vmsne.vv v0, v4, v6 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vwabda_vx: + /* + * Test signed widening vector-scalar absolute difference and + * accumulation. With scalar 3, v4 becomes {1000 + 8, -1000 + 10}. + */ + /* Load the 16-bit accumulator before selecting 8-bit operands. */ + vsetivli zero, 2, e16, m2, ta, mu + la t0, .arr_signed_acc + vle16.v v4, 0(t0) + + vsetivli zero, 2, e8, m1, ta, mu + la t0, .arr_neg + vle8.v v1, 0(t0) + li a2, 3 + + /* Execute vwabda.vx v4, v1, a2. */ + .word 0xf6164257 + + /* Select the widened EEW and compare v4 with the expected result. */ + vsetivli zero, 2, e16, m2, ta, mu + la t0, .expect_vwabda_vx + vle16.v v6, 0(t0) + + vmsne.vv v0, v4, v6 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vwabda_vx_mask: + /* + * Test masked vwabda.vx. Element 0 remains 1000 while element 1 + * accumulates 10 and becomes -990. + */ + vsetivli zero, 2, e16, m2, ta, mu + + la t0, .arr_signed_acc + vle16.v v4, 0(t0) + + vsetivli zero, 2, e8, m1, ta, mu + la t0, .arr_neg + vle8.v v1, 0(t0) + li a2, 3 + + la t0, .v0_mask + vle8.v v0, 0(t0) + + .word 0xf4164257 + + vsetivli zero, 2, e16, m2, ta, mu + la t0, .expect_vwabda_vx_masked + vle16.v v6, 0(t0) + + vmsne.vv v0, v4, v6 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vwabdau_vv: + /* + * Test unsigned widening vector-vector absolute difference and + * accumulation. Start with v4 =3D {1000, 2000}, adding {255, 255} + * produces {1255, 2255}. + */ + /* Load the unsigned 16-bit accumulator and 8-bit source vectors. */ + vsetivli zero, 2, e16, m2, ta, mu + + la t0, .arr_unsigned_acc + vle16.v v4, 0(t0) + vsetivli zero, 2, e8, m1, ta, mu + + la t0, .arr_unsigned_lhs + vle8.v v1, 0(t0) + la t0, .arr_unsigned_rhs + vle8.v v2, 0(t0) + + /* Execute vwabdau.vv v4, v1, v2. */ + .word 0xfa110257 + + /* Select the widened EEW and compare v4 with the expected result. */ + vsetivli zero, 2, e16, m2, ta, mu + la t0, .expect_vwabdau_vv + vle16.v v6, 0(t0) + + vmsne.vv v0, v4, v6 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vwabdau_vv_mask: + /* + * Test masked vwabdau.vv. Element 0 remains 1000 while element 1 + * accumulates 255 and becomes 2255. + */ + vsetivli zero, 2, e16, m2, ta, mu + + la t0, .arr_unsigned_acc + vle16.v v4, 0(t0) + + vsetivli zero, 2, e8, m1, ta, mu + la t0, .arr_unsigned_lhs + vle8.v v1, 0(t0) + la t0, .arr_unsigned_rhs + vle8.v v2, 0(t0) + + la t0, .v0_mask + vle8.v v0, 0(t0) + + .word 0xf8110257 + + vsetivli zero, 2, e16, m2, ta, mu + la t0, .expect_vwabdau_vv_masked + vle16.v v6, 0(t0) + + vmsne.vv v0, v4, v6 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vwabdau_vx: + /* + * Test unsigned widening vector-scalar absolute difference and + * accumulation. With scalar 128, v4 becomes {1000 + 128, 2000 + 127}. + */ + /* Load the unsigned 16-bit accumulator and 8-bit source vector. */ + vsetivli zero, 2, e16, m2, ta, mu + + la t0, .arr_unsigned_acc + vle16.v v4, 0(t0) + + vsetivli zero, 2, e8, m1, ta, mu + la t0, .arr_unsigned_lhs + vle8.v v1, 0(t0) + li a2, 128 + + /* Execute vwabdau.vx v4, v1, a2. */ + .word 0xfa164257 + + /* Select the widened EEW and compare v4 with the expected result. */ + vsetivli zero, 2, e16, m2, ta, mu + la t0, .expect_vwabdau_vx + vle16.v v6, 0(t0) + + vmsne.vv v0, v4, v6 + vcpop.m a0, v0 + snez a0, a0 + ret + +test_vwabdau_vx_mask: + /* + * Test masked vwabdau.vx. Element 0 remains 1000 while element 1 + * accumulates 127 and becomes 2127. + */ + vsetivli zero, 2, e16, m2, ta, mu + + la t0, .arr_unsigned_acc + vle16.v v4, 0(t0) + + vsetivli zero, 2, e8, m1, ta, mu + la t0, .arr_unsigned_lhs + vle8.v v1, 0(t0) + li a2, 128 + + la t0, .v0_mask + vle8.v v0, 0(t0) + + .word 0xf8164257 + + vsetivli zero, 2, e16, m2, ta, mu + la t0, .expect_vwabdau_vx_masked + vle16.v v6, 0(t0) + + vmsne.vv v0, v4, v6 + vcpop.m a0, v0 + snez a0, a0 + ret + + +/* Exit through the semihosting SYS_EXIT_EXTENDED call with a0 as the code= . */ +_exit: + la a1, semiargs + li t0, 0x20026 /* ADP_Stopped_ApplicationExit */ + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 /* TARGET_SYS_EXIT_EXTENDED */ + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + .balign 4 +trap_handler: + csrr t4, mcause + la t5, trap_mcause + sd t4, 0(t5) + csrr t4, mtval + la t5, trap_mtval + sd t4, 0(t5) + li a0, 1 + j _exit + + .data + .balign 8 +semiargs: + .space 16 +trap_mcause: + .space 8 +trap_mtval: + .space 8 +.arr_neg: + .byte -5, -7 +.arr_pos: + .byte 5, 7 +.arr_zero: + .byte 0, 0 +.arr_init: + .byte 9, 9 +.v0_mask: + .byte 0b10 +.arr_masked: + .byte 0, 7 + +/* Unsigned input vectors used by vabdu and vwabdau. */ +.arr_unsigned_lhs: + .byte 0, 255 +.arr_unsigned_rhs: + .byte 255, 0 + .balign 2 + +/* Nonzero accumulators verify the add part of widening operations. */ +.arr_signed_acc: + .half 1000, -1000 +.arr_unsigned_acc: + .half 1000, 2000 + +/* Expected results for the unmasked and masked forms. */ +.expect_vabd_vv: + .byte 10, 14 +.expect_vabd_vv_masked: + .byte 9, 14 +.expect_vabd_vx: + .byte 8, 10 +.expect_vabd_vx_masked: + .byte 9, 10 +.expect_vabdu_vv: + .byte 255, 255 +.expect_vabdu_vv_masked: + .byte 9, 255 +.expect_vabdu_vx: + .byte 128, 127 +.expect_vabdu_vx_masked: + .byte 9, 127 +.expect_vwabda_vv: + .half 1010, -986 +.expect_vwabda_vv_masked: + .half 1000, -986 +.expect_vwabda_vx: + .half 1008, -990 +.expect_vwabda_vx_masked: + .half 1000, -990 +.expect_vwabdau_vv: + .half 1255, 2255 +.expect_vwabdau_vv_masked: + .half 1000, 2255 +.expect_vwabdau_vx: + .half 1128, 2127 +.expect_vwabdau_vx_masked: + .half 1000, 2127 --=20 2.39.5