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a="88499957" X-IronPort-AV: E=Sophos;i="6.25,252,1779174000"; d="scan'208";a="88499957" X-CSE-ConnectionGUID: 4vZD3kGuTGuZLfR47ImC6A== X-CSE-MsgGUID: 8Ube4THSTIynT0Pl5m8QZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,252,1779174000"; d="scan'208";a="272554340" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowangio@gmail.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, Zhenzhong Duan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 1/6] intel_iommu_accel: Guard VTDAccelPASIDCacheEntry definition Date: Mon, 31 Aug 2026 17:51:54 +0800 Message-ID: <20260831095200.1279366-2-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260831095200.1279366-1-zhenzhong.duan@intel.com> References: <20260831095200.1279366-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.19; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1788169987324154100 Move the VTDAccelPASIDCacheEntry typedef structure inside the CONFIG_VTD_ACCEL ifdef block. When CONFIG_VTD_ACCEL is disabled, this structure is entirely unused throughout the code. Moving the layout under the existing preprocessor guard prevents exposing dead type definitions and ensures the header remains clean when building without VTD acceleration support. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Zhenzhong Duan Reviewed-by: Clement Mathieu--Drif Reviewed-by: Yi Liu --- hw/i386/intel_iommu_accel.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 4a9003c92d..46c1a29409 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -12,6 +12,7 @@ #define HW_I386_INTEL_IOMMU_ACCEL_H #include CONFIG_DEVICES =20 +#ifdef CONFIG_VTD_ACCEL typedef struct VTDAccelPASIDCacheEntry { VTDHostIOMMUDevice *vtd_hiod; VTDPASIDEntry pasid_entry; @@ -20,7 +21,6 @@ typedef struct VTDAccelPASIDCacheEntry { QLIST_ENTRY(VTDAccelPASIDCacheEntry) next; } VTDAccelPASIDCacheEntry; =20 -#ifdef CONFIG_VTD_ACCEL bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp); VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as); --=20 2.52.0 From nobody Sat Sep 26 20:51:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="88499981" X-IronPort-AV: E=Sophos;i="6.25,252,1779174000"; d="scan'208";a="88499981" X-CSE-ConnectionGUID: S3GIe4nOT8qJTxRaVVzNow== X-CSE-MsgGUID: lbiIhG4WTwi3OcB+l7pE3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,252,1779174000"; d="scan'208";a="272554358" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowangio@gmail.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, Zhenzhong Duan , Xudong Hao Subject: [PATCH v5 2/6] backends/iommufd: Introduce iommufd_backend_alloc_faultq Date: Mon, 31 Aug 2026 17:51:55 +0800 Message-ID: <20260831095200.1279366-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260831095200.1279366-1-zhenzhong.duan@intel.com> References: <20260831095200.1279366-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.19; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1788169974347158500 Content-Type: text/plain; charset="utf-8" Add a new helper for IOMMU_FAULT_QUEUE_ALLOC ioctl to allocate a fault handling object which will be used in hwpt allocation. Signed-off-by: Zhenzhong Duan Reviewed-by: Clement Mathieu--Drif Tested-by: Xudong Hao Reviewed-by: Yi Liu --- include/system/iommufd.h | 3 +++ backends/iommufd.c | 21 +++++++++++++++++++++ backends/trace-events | 1 + 3 files changed, 25 insertions(+) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 17bf1a3727..36b34b4899 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -106,6 +106,9 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, = uint32_t viommu_id, uint32_t *out_veventq_id, uint32_t *out_veventq_fd, Error **errp); =20 +bool iommufd_backend_alloc_faultq(IOMMUFDBackend *be, uint32_t *out_fault_= id, + uint32_t *out_fault_fd, Error **errp); + bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, uint32_t queue_type, uint32_t index, uint64_t addr, uint64_t length, diff --git a/backends/iommufd.c b/backends/iommufd.c index 15f2a51350..2775eef741 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -554,6 +554,27 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be,= uint32_t viommu_id, return true; } =20 +bool iommufd_backend_alloc_faultq(IOMMUFDBackend *be, uint32_t *out_fault_= id, + uint32_t *out_fault_fd, Error **errp) +{ + int ret, fd =3D be->fd; + struct iommu_fault_alloc cmd =3D { + .size =3D sizeof(cmd), + }; + + ret =3D ioctl(fd, IOMMU_FAULT_QUEUE_ALLOC, &cmd); + trace_iommufd_backend_alloc_faultq(fd, cmd.out_fault_id, cmd.out_fault= _fd, + ret); + if (ret) { + error_setg_errno(errp, errno, "Failed to allocate fault queue"); + return false; + } + + *out_fault_id =3D cmd.out_fault_id; + *out_fault_fd =3D cmd.out_fault_fd; + return true; +} + bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, uint32_t queue_type, uint32_t index, uint64_t addr, uint64_t length, diff --git a/backends/trace-events b/backends/trace-events index 9b7b9b7d68..b1c1d89dd8 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -17,6 +17,7 @@ iommufd_backend_unmap_dma_non_exist(int iommufd, uint32_t= ioas, uint64_t iova, u iommufd_backend_unmap_dma(int iommufd, uint32_t ioas, uint64_t iova, uint6= 4_t size, int ret) " iommufd=3D%d ioas=3D%d iova=3D0x%"PRIx64" size=3D0x%"P= RIx64" (%d)" iommufd_backend_alloc_ioas(int iommufd, uint32_t ioas) " iommufd=3D%d ioas= =3D%d" iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, u= int32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_= t out_hwpt_id, int ret) " iommufd=3D%d dev_id=3D%u pt_id=3D%u flags=3D0x%x = hwpt_type=3D%u len=3D%u data_ptr=3D0x%"PRIx64" out_hwpt=3D%u (%d)" +iommufd_backend_alloc_faultq(int iommufd, uint32_t fault_id, uint32_t faul= t_fd, int ret) " iommufd=3D%d fault_id=3D%u fault_fd=3D%u (%d)" iommufd_backend_free_id(int iommufd, uint32_t id, int ret) " iommufd=3D%d = id=3D%d (%d)" iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) " iommufd= =3D%d hwpt=3D%u iova=3D0x%"PRIx64" size=3D0x%"PRIx64" flags=3D0x%"PRIx64" p= age_size=3D0x%"PRIx64" (%d)" --=20 2.52.0 From nobody Sat Sep 26 20:51:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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31 Aug 2026 02:52:27 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.229.148]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2026 02:52:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788169948; x=1819705948; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ANljbMPtLm3wIof2Yd4tWH9Bd4Cq/LlVMNDGpCgwtbA=; b=E3ji62uUQWYQiXcOS+nrkOqVa1SyKgq3d9m4VbwswSzB4OTdWxYCCBpl Rc5KsQcz1IeJ4k7mAgKsLnUXO4iQJWRWFyCMf2scW7p3g/pkDXXQoRjSZ zIBW10SHaxLAEkwWkmQzEQZxaaOOPwSbR+9lBFFoM/X9JPfC4PZI3qraZ kYMLRDTTUlLLaP48Mdbxny3ruy3yg+3ua4EoM4Vd/H/+3eWbnZb2NlqOU HfRhrRAJnvLf0kcXoi79SdNN1oHGzTSIaSJpy5RgYG1jYdfbP+wabGtQz yDTpS7xJy7BKJiwnHIWXibeT4nrLVVVPo7T7tMzjNvpW510grfy8wg3E8 A==; X-CSE-ConnectionGUID: dufSuEIgThyx/YJ0h566eA== X-CSE-MsgGUID: UxCD3RhBQyyCW4TMDvTcZQ== X-IronPort-AV: E=McAfee;i="6800,10657,11891"; a="88499991" X-IronPort-AV: E=Sophos;i="6.25,252,1779174000"; d="scan'208";a="88499991" X-CSE-ConnectionGUID: mA0We9kTSPCzge3mNrPMsw== X-CSE-MsgGUID: uMz4IwtsTImtlEpb6VLDuQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,252,1779174000"; d="scan'208";a="272554386" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowangio@gmail.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, Zhenzhong Duan , Xudong Hao , qemu-arm@nongnu.org Subject: [PATCH v5 3/6] backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id Date: Mon, 31 Aug 2026 17:51:56 +0800 Message-ID: <20260831095200.1279366-4-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260831095200.1279366-1-zhenzhong.duan@intel.com> References: <20260831095200.1279366-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.19; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1788169999345154100 Content-Type: text/plain; charset="utf-8" We should set flags IOMMU_HWPT_FAULT_ID_VALID when pass in a fault object id in the caller. Signed-off-by: Zhenzhong Duan Reviewed-by: Clement Mathieu--Drif Tested-by: Xudong Hao Reviewed-by: Yi Liu --- include/system/iommufd.h | 4 ++-- backends/iommufd.c | 7 ++++--- hw/arm/smmuv3-accel.c | 6 +++--- hw/i386/intel_iommu_accel.c | 2 +- hw/vfio/iommufd.c | 2 +- backends/trace-events | 2 +- 6 files changed, 12 insertions(+), 11 deletions(-) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 36b34b4899..79b8dabfb6 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -90,8 +90,8 @@ bool iommufd_backend_get_device_info(IOMMUFDBackend *be, = uint32_t devid, bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t data_type, uint32_t data_len, - void *data_ptr, uint32_t *out_hwpt, - Error **errp); + void *data_ptr, uint32_t fault_id, + uint32_t *out_hwpt, Error **errp); bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, void *data_ptr, uint32_t data_len, diff --git a/backends/iommufd.c b/backends/iommufd.c index 2775eef741..f46b3bfa7e 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -315,8 +315,8 @@ int iommufd_backend_unmap_dma(IOMMUFDBackend *be, uint3= 2_t ioas_id, bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t data_type, uint32_t data_len, - void *data_ptr, uint32_t *out_hwpt, - Error **errp) + void *data_ptr, uint32_t fault_id, + uint32_t *out_hwpt, Error **errp) { int ret, fd =3D be->fd; struct iommu_hwpt_alloc alloc_hwpt =3D { @@ -327,11 +327,12 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, u= int32_t dev_id, .data_type =3D data_type, .data_len =3D data_len, .data_uptr =3D (uintptr_t)data_ptr, + .fault_id =3D fault_id, }; =20 ret =3D ioctl(fd, IOMMU_HWPT_ALLOC, &alloc_hwpt); trace_iommufd_backend_alloc_hwpt(fd, dev_id, pt_id, flags, data_type, - data_len, (uintptr_t)data_ptr, + data_len, (uintptr_t)data_ptr, fault_= id, alloc_hwpt.out_hwpt_id, ret); if (ret) { error_setg_errno(errp, errno, "Failed to allocate hwpt"); diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 91aca1aa14..66e6a5011a 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -268,7 +268,7 @@ smmuv3_accel_dev_alloc_translate(SMMUv3AccelDevice *acc= el_dev, STE *ste, accel->viommu->viommu_id, flags, IOMMU_HWPT_DATA_ARM_SMMUV3, sizeof(nested_data), &nested_data, - &hwpt_id, errp)) { + 0, &hwpt_id, errp)) { return NULL; } =20 @@ -632,14 +632,14 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *hiodi, if (!iommufd_backend_alloc_hwpt(hiodi->iommufd, hiodi->devid, viommu_i= d, 0, IOMMU_HWPT_DATA_ARM_SMMUV3, sizeof(abort_data), &abort_data, - &accel->abort_hwpt_id, errp)) { + 0, &accel->abort_hwpt_id, errp)) { goto free_viommu; } =20 if (!iommufd_backend_alloc_hwpt(hiodi->iommufd, hiodi->devid, viommu_i= d, 0, IOMMU_HWPT_DATA_ARM_SMMUV3, sizeof(bypass_data), &bypass_data, - &accel->bypass_hwpt_id, errp)) { + 0, &accel->bypass_hwpt_id, errp)) { goto free_abort_hwpt; } =20 diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index c03435f8a2..d2f41f18f1 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -94,7 +94,7 @@ static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hi= od, return iommufd_backend_alloc_hwpt(hiodi->iommufd, hiodi->devid, hiodi->hwpt_id, flags, IOMMU_HWPT_DATA_VTD_S1, sizeof(vtd),= &vtd, - fs_hwpt_id, errp); + 0, fs_hwpt_id, errp); } =20 static void vtd_destroy_old_fs_hwpt(VTDAccelPASIDCacheEntry *vtd_pce) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 242644aa00..74a5d77dcc 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -476,7 +476,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, if (!iommufd_backend_alloc_hwpt(iommufd, vbasedev->devid, container->ioas_id, flags, IOMMU_HWPT_DATA_NONE, 0, NULL, - &hwpt_id, errp)) { + 0, &hwpt_id, errp)) { return false; } =20 diff --git a/backends/trace-events b/backends/trace-events index b1c1d89dd8..2f242feb78 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -16,7 +16,7 @@ iommufd_backend_map_file_dma(int iommufd, uint32_t ioas, = uint64_t iova, uint64_t iommufd_backend_unmap_dma_non_exist(int iommufd, uint32_t ioas, uint64_t i= ova, uint64_t size, int ret) " Unmap nonexistent mapping: iommufd=3D%d ioas= =3D%d iova=3D0x%"PRIx64" size=3D0x%"PRIx64" (%d)" iommufd_backend_unmap_dma(int iommufd, uint32_t ioas, uint64_t iova, uint6= 4_t size, int ret) " iommufd=3D%d ioas=3D%d iova=3D0x%"PRIx64" size=3D0x%"P= RIx64" (%d)" iommufd_backend_alloc_ioas(int iommufd, uint32_t ioas) " iommufd=3D%d ioas= =3D%d" -iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, u= int32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_= t out_hwpt_id, int ret) " iommufd=3D%d dev_id=3D%u pt_id=3D%u flags=3D0x%x = hwpt_type=3D%u len=3D%u data_ptr=3D0x%"PRIx64" out_hwpt=3D%u (%d)" +iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, u= int32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_= t fault_id, uint32_t out_hwpt_id, int ret) " iommufd=3D%d dev_id=3D%u pt_id= =3D%u flags=3D0x%x hwpt_type=3D%u len=3D%u data_ptr=3D0x%"PRIx64" fault_id= =3D%u out_hwpt=3D%u (%d)" iommufd_backend_alloc_faultq(int iommufd, uint32_t fault_id, uint32_t faul= t_fd, int ret) " iommufd=3D%d fault_id=3D%u fault_fd=3D%u (%d)" iommufd_backend_free_id(int iommufd, uint32_t id, int ret) " iommufd=3D%d = id=3D%d (%d)" iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" --=20 2.52.0 From nobody Sat Sep 26 20:51:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="88500002" X-IronPort-AV: E=Sophos;i="6.25,252,1779174000"; d="scan'208";a="88500002" X-CSE-ConnectionGUID: pdhQbjHOQJamYm7TsS61dQ== X-CSE-MsgGUID: M6rCEPMcRPayvXYa0dUpKQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,252,1779174000"; d="scan'208";a="272554403" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowangio@gmail.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, Zhenzhong Duan , Xudong Hao Subject: [PATCH v5 4/6] intel_iommu_accel: Add PRQ injection for passthrough device Date: Mon, 31 Aug 2026 17:51:57 +0800 Message-ID: <20260831095200.1279366-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260831095200.1279366-1-zhenzhong.duan@intel.com> References: <20260831095200.1279366-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.19; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1788169994195154100 Content-Type: text/plain; charset="utf-8" When the guest enables the PRQ in vIOMMU, allocate a FAULTQ object so that host-side recoverable fault events can be received and propagated back to the guest. Install an event handler on the FAULTQ fd to read and propagate host generated recoverable fault events to the guest. The handler runs in QEMU's main loop, using a non-blocking fd registered via qemu_set_fd_handler(). Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.h | 2 + hw/i386/intel_iommu_internal.h | 3 + hw/i386/intel_iommu.c | 9 +- hw/i386/intel_iommu_accel.c | 160 +++++++++++++++++++++++++++++++-- hw/i386/trace-events | 1 + 5 files changed, 164 insertions(+), 11 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 46c1a29409..e0319749a5 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -18,6 +18,8 @@ typedef struct VTDAccelPASIDCacheEntry { VTDPASIDEntry pasid_entry; uint32_t pasid; uint32_t fs_hwpt_id; + uint32_t fault_id; + int fault_fd; QLIST_ENTRY(VTDAccelPASIDCacheEntry) next; } VTDAccelPASIDCacheEntry; =20 diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 924e91cb8a..5ebc204e9a 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -786,4 +786,7 @@ int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_= t bus_num, VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid); int vtd_dev_get_pe_from_pasid(IntelIOMMUState *s, PCIBus *bus, uint8_t dev= fn, uint32_t pasid, VTDPASIDEntry *pe); +int vtd_pri_request_page(PCIBus *bus, void *opaque, int devfn, uint32_t pa= sid, + bool priv_req, bool exec_req, hwaddr addr, bool l= pig, + uint16_t prgi, bool is_read, bool is_write); #endif diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 82c3c3b2c3..dcf23924ef 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -5369,11 +5369,10 @@ static int vtd_pri_perform_implicit_invalidation(VT= DAddressSpace *vtd_as, return ret; } =20 -/* Page Request Descriptor : 7.4.1.1 */ -static int vtd_pri_request_page(PCIBus *bus, void *opaque, int devfn, - uint32_t pasid, bool priv_req, bool exec_r= eq, - hwaddr addr, bool lpig, uint16_t prgi, - bool is_read, bool is_write) +/* Accept the PCI PASID as input. Page Request Descriptor : 7.4.1.1 */ +int vtd_pri_request_page(PCIBus *bus, void *opaque, int devfn, uint32_t pa= sid, + bool priv_req, bool exec_req, hwaddr addr, bool l= pig, + uint16_t prgi, bool is_read, bool is_write) { IntelIOMMUState *s =3D opaque; VTDAddressSpace *vtd_as; diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index d2f41f18f1..3808112f79 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -9,6 +9,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "system/iommufd.h" #include "intel_iommu_internal.h" #include "intel_iommu_accel.h" @@ -77,14 +78,150 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSp= ace *as) return NULL; } =20 -static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod, - VTDPASIDEntry *pe, uint32_t *fs_hwpt_id, - Error **errp) +static void vtd_prq_report_fault(VTDAccelPASIDCacheEntry *vtd_pce, + struct iommu_hwpt_pgfault *fault, unsigne= d cnt) +{ + VTDHostIOMMUDevice *vtd_hiod =3D vtd_pce->vtd_hiod; + uint32_t pasid =3D + vtd_pce->pasid =3D=3D IOMMU_NO_PASID ? PCI_NO_PASID : vtd_pce->pas= id; + + for (; cnt--; fault++) { + bool last_page =3D fault->flags & IOMMU_PGFAULT_FLAGS_LAST_PAGE; + + vtd_pri_request_page(vtd_hiod->bus, vtd_hiod->iommu_state, + vtd_hiod->devfn, pasid, + fault->perm & IOMMU_PGFAULT_PERM_PRIV, + fault->perm & IOMMU_PGFAULT_PERM_EXEC, + fault->addr, last_page, fault->grpid, + fault->perm & IOMMU_PGFAULT_PERM_READ, + fault->perm & IOMMU_PGFAULT_PERM_WRITE); + } +} + +/* Batch size per read(); remaining faults trigger another callback */ +#define FAULTQ_BUF_SIZE 100 + +static void vtd_prq_read_fault(void *opaque) +{ + VTDAccelPASIDCacheEntry *vtd_pce =3D opaque; + struct iommu_hwpt_pgfault fault[FAULTQ_BUF_SIZE]; + uint32_t id =3D vtd_pce->fault_id; + int fd =3D vtd_pce->fault_fd; + ssize_t bytes, last_bytes; + + bytes =3D read(fd, fault, sizeof(fault)); + trace_vtd_prq_read_fault(id, fd, bytes); + if (bytes < 0) { + if (errno !=3D EAGAIN && errno !=3D EINTR) { + error_report_once("FAULTQ(id %u): read failed (%m)", id); + } + return; + } else if (!bytes) { + error_report_once("FAULTQ(id %u): fault group too big", id); + return; + } + + last_bytes =3D bytes % sizeof(fault[0]); + if (last_bytes) { + error_report_once("FAULTQ(id %u): discard partial fault data: %zd/= %zu", + id, last_bytes, sizeof(fault)); + } + + vtd_prq_report_fault(vtd_pce, fault, bytes / sizeof(fault[0])); +} + +static void vtd_destroy_fs_faultq(VTDHostIOMMUDevice *vtd_hiod, + uint32_t fault_id, int fault_fd) +{ + HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); + + if (fault_fd < 0) { + return; + } + + close(fault_fd); + iommufd_backend_free_id(hiodi->iommufd, fault_id); +} + +static bool vtd_create_fs_faultq(VTDHostIOMMUDevice *vtd_hiod, + uint32_t *fault_id_p, int *fault_fd_p, + Error **errp) +{ + HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); + IntelIOMMUState *s =3D vtd_hiod->iommu_state; + uint8_t bus_n =3D pci_bus_num(vtd_hiod->bus); + uint32_t fault_id, fault_fd; + VTDContextEntry ce; + int flags; + + if (!s->svm || + vtd_dev_to_context_entry(s, bus_n, vtd_hiod->devfn, &ce) || + !VTD_CE_GET_PRE(&ce)) { + *fault_id_p =3D 0; + *fault_fd_p =3D -1; + return true; + } + + if (!iommufd_backend_alloc_faultq(hiodi->iommufd, &fault_id, &fault_fd, + errp)) { + return false; + } + + flags =3D fcntl(fault_fd, F_GETFL); + if (flags < 0) { + error_setg_errno(errp, errno, "Failed to get flags for FAULTQ fd"); + goto free_faultq; + } + + if (fcntl(fault_fd, F_SETFL, flags | O_NONBLOCK) < 0) { + error_setg_errno(errp, errno, "Failed to set O_NONBLOCK on FAULTQ = fd"); + goto free_faultq; + } + + *fault_id_p =3D fault_id; + *fault_fd_p =3D fault_fd; + return true; + +free_faultq: + vtd_destroy_fs_faultq(vtd_hiod, fault_id, fault_fd); + return false; +} + +static void vtd_destroy_old_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce) +{ + if (vtd_pce->fault_fd < 0) { + return; + } + + qemu_set_fd_handler(vtd_pce->fault_fd, NULL, NULL, NULL); + vtd_destroy_fs_faultq(vtd_pce->vtd_hiod, vtd_pce->fault_id, + vtd_pce->fault_fd); + vtd_pce->fault_id =3D 0; + vtd_pce->fault_fd =3D -1; +} + +static void vtd_setup_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce, + uint32_t fault_id, int fault_fd) +{ + if (fault_fd < 0) { + return; + } + + vtd_pce->fault_id =3D fault_id; + vtd_pce->fault_fd =3D fault_fd; + qemu_set_fd_handler(fault_fd, vtd_prq_read_fault, NULL, vtd_pce); +} + +static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod, VTDPASIDEntry= *pe, + bool has_fault_id, uint32_t fault_id, + uint32_t *fs_hwpt_id, Error **errp) { HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); struct iommu_hwpt_vtd_s1 vtd =3D {}; uint32_t flags =3D vtd_hiod->iommu_state->pasid ? IOMMU_HWPT_ALLOC_PAS= ID : 0; =20 + flags |=3D has_fault_id ? IOMMU_HWPT_FAULT_ID_VALID : 0; + vtd.flags =3D (VTD_SM_PASID_ENTRY_SRE(pe) ? IOMMU_VTD_S1_SRE : 0) | (VTD_SM_PASID_ENTRY_WPE(pe) ? IOMMU_VTD_S1_WPE : 0) | (VTD_SM_PASID_ENTRY_EAFE(pe) ? IOMMU_VTD_S1_EAFE : 0); @@ -94,7 +231,7 @@ static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_h= iod, return iommufd_backend_alloc_hwpt(hiodi->iommufd, hiodi->devid, hiodi->hwpt_id, flags, IOMMU_HWPT_DATA_VTD_S1, sizeof(vtd),= &vtd, - 0, fs_hwpt_id, errp); + fault_id, fs_hwpt_id, errp); } =20 static void vtd_destroy_old_fs_hwpt(VTDAccelPASIDCacheEntry *vtd_pce) @@ -115,7 +252,8 @@ static bool vtd_device_attach_iommufd(VTDAccelPASIDCach= eEntry *vtd_pce, VTDHostIOMMUDevice *vtd_hiod =3D vtd_pce->vtd_hiod; HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); VTDPASIDEntry *pe =3D &vtd_pce->pasid_entry; - uint32_t hwpt_id =3D hiodi->hwpt_id, pasid =3D vtd_pce->pasid; + uint32_t hwpt_id =3D hiodi->hwpt_id, pasid =3D vtd_pce->pasid, fault_i= d =3D 0; + int fault_fd =3D -1; bool ret; =20 /* @@ -130,7 +268,12 @@ static bool vtd_device_attach_iommufd(VTDAccelPASIDCac= heEntry *vtd_pce, } =20 if (vtd_pe_pgtt_is_fst(pe)) { - if (!vtd_create_fs_hwpt(vtd_hiod, pe, &hwpt_id, errp)) { + if (!vtd_create_fs_faultq(vtd_hiod, &fault_id, &fault_fd, errp)) { + return false; + } + if (!vtd_create_fs_hwpt(vtd_hiod, pe, fault_fd >=3D 0, fault_id, + &hwpt_id, errp)) { + vtd_destroy_fs_faultq(vtd_hiod, fault_id, fault_fd); return false; } } @@ -140,11 +283,14 @@ static bool vtd_device_attach_iommufd(VTDAccelPASIDCa= cheEntry *vtd_pce, if (ret) { /* Destroy old fs_hwpt if it's a replacement */ vtd_destroy_old_fs_hwpt(vtd_pce); + vtd_destroy_old_fs_faultq(vtd_pce); if (vtd_pe_pgtt_is_fst(pe)) { vtd_pce->fs_hwpt_id =3D hwpt_id; + vtd_setup_fs_faultq(vtd_pce, fault_id, fault_fd); } } else if (vtd_pe_pgtt_is_fst(pe)) { iommufd_backend_free_id(hiodi->iommufd, hwpt_id); + vtd_destroy_fs_faultq(vtd_hiod, fault_id, fault_fd); } =20 return ret; @@ -177,6 +323,7 @@ static bool vtd_device_detach_iommufd(VTDAccelPASIDCach= eEntry *vtd_pce, =20 if (ret) { vtd_destroy_old_fs_hwpt(vtd_pce); + vtd_destroy_old_fs_faultq(vtd_pce); } =20 return ret; @@ -276,6 +423,7 @@ static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd_h= iod, uint32_t pasid, vtd_pce->vtd_hiod =3D vtd_hiod; vtd_pce->pasid =3D pasid; vtd_pce->pasid_entry =3D *pe; + vtd_pce->fault_fd =3D -1; QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next); =20 if (!vtd_device_attach_iommufd(vtd_pce, &local_err)) { diff --git a/hw/i386/trace-events b/hw/i386/trace-events index a1a50d0910..dca726c9b8 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -77,6 +77,7 @@ vtd_reset_exit(void) "" vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, = int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" +vtd_prq_read_fault(uint32_t fault_id, uint32_t fault_fd, ssize_t bytes) "f= ault_id %d fault_fd %d ret: %zd" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.52.0 From nobody Sat Sep 26 20:51:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Aug 2026 05:52:35 -0400 Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2026 02:52:34 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.229.148]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2026 02:52:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788169954; x=1819705954; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E0hWTO0G9FERxD7W5zOKzoEBNlee2yR6mAGawU5jeQg=; b=MUq3AygMNp7v4Vy+dbG3TJS/FP6KkopOnfbJSi8uvko6t+utSMAJLb4a PGQxm7IBWGnDiib8FoK4FR5JGkKpAdIx98vS5Cshr+X/f/eGwKE9hu5GU snFTyeBIERrgjWaDDo25Iv1ZXoSv2vq+ILoVOFvHtpo59kpF4UgVbN2th iAeKO6/PSS7JGKun2yBx0lj0kcHukavlGd+jVzjRCpElmrbD6caB0gl4y Zm3pDAyRZeleXNp9qEAgZ/86mkno9GVorgTTCXvjYH5PBNfhzCgI1LcZF CJc8iCo6iiEMrAW2Q4dcNlN3BFS1kHOt5wf4/NLnAyI7zA+UwgGSnmhU5 A==; X-CSE-ConnectionGUID: vZrLk+I+Rw2G/bQQKQofjw== X-CSE-MsgGUID: e1r4kkEDQ0ib7BAVVMm4mA== X-IronPort-AV: E=McAfee;i="6800,10657,11891"; a="88500021" X-IronPort-AV: E=Sophos;i="6.25,252,1779174000"; d="scan'208";a="88500021" X-CSE-ConnectionGUID: eczWQIyYR+ucVv3lbRSx4Q== X-CSE-MsgGUID: 8GeogcxhR9mbL0xODdmpAg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,252,1779174000"; d="scan'208";a="272554436" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowangio@gmail.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, Zhenzhong Duan , Xudong Hao Subject: [PATCH v5 5/6] intel_iommu_accel: Accept PRQ response for passthrough device Date: Mon, 31 Aug 2026 17:51:58 +0800 Message-ID: <20260831095200.1279366-6-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260831095200.1279366-1-zhenzhong.duan@intel.com> References: <20260831095200.1279366-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.19; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1788169987309154100 Content-Type: text/plain; charset="utf-8" Propagate guest's PRQ response to host by writing to fault_fd. Create a new VTDPRQEntry to cache cookie for each fault group, this cookie is used to mark the fault group on host side. If there is either PRQ overflow or full error condition, propagate a success response to host for LPIG request with the PRQ requests dropped. For other error conditions, propagate response of invalid request. Signed-off-by: Zhenzhong Duan Reviewed-by: Clement Mathieu--Drif Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.h | 12 +++++ include/hw/i386/intel_iommu.h | 6 +++ hw/i386/intel_iommu.c | 4 ++ hw/i386/intel_iommu_accel.c | 98 ++++++++++++++++++++++++++++++++--- hw/i386/trace-events | 1 + 5 files changed, 114 insertions(+), 7 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index e0319749a5..0cc22b2cbb 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -20,6 +20,7 @@ typedef struct VTDAccelPASIDCacheEntry { uint32_t fs_hwpt_id; uint32_t fault_id; int fault_fd; + QLIST_HEAD(, VTDPRQEntry) vtd_prq_list; QLIST_ENTRY(VTDAccelPASIDCacheEntry) next; } VTDAccelPASIDCacheEntry; =20 @@ -31,6 +32,9 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s,= uint16_t domain_id, uint64_t npages, bool ih); void vtd_accel_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_= info); void vtd_accel_pasid_cache_reset(IntelIOMMUState *s); +bool vtd_accel_propagate_page_group_response(IntelIOMMUState *s, + uint16_t rid, uint32_t pasid, + IOMMUPRIResponse *response); void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, @@ -69,6 +73,14 @@ static inline void vtd_accel_pasid_cache_reset(IntelIOMM= UState *s) { } =20 +static inline +bool vtd_accel_propagate_page_group_response(IntelIOMMUState *s, + uint16_t rid, uint32_t pasid, + IOMMUPRIResponse *response) +{ + return false; +} + static inline void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops) { } diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 1842ba5840..5d44eac0ed 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -100,6 +100,12 @@ typedef struct VTDPASIDCacheEntry { bool valid; } VTDPASIDCacheEntry; =20 +typedef struct VTDPRQEntry { + uint32_t grpid; + uint32_t cookie; + QLIST_ENTRY(VTDPRQEntry) next; +} VTDPRQEntry; + struct VTDAddressSpace { PCIBus *bus; uint8_t devfn; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index dcf23924ef..4e54c38c7e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3380,6 +3380,10 @@ static bool vtd_process_page_group_response_desc(Int= elIOMMUState *s, response.response_code =3D IOMMU_PRI_RESP_FAILURE; } =20 + if (vtd_accel_propagate_page_group_response(s, rid, pasid, &response))= { + return true; + } + if (vtd_dev_as->pri_notifier) { vtd_dev_as->pri_notifier->notify(vtd_dev_as->pri_notifier, &respon= se); } diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 3808112f79..7d54ce12e9 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -78,6 +78,61 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpac= e *as) return NULL; } =20 +static void vtd_prq_write_response(VTDAccelPASIDCacheEntry *vtd_pce, + uint32_t cookie, uint32_t code) +{ + struct iommu_hwpt_page_response resp =3D {cookie, code}; + uint32_t id =3D vtd_pce->fault_id; + int fd =3D vtd_pce->fault_fd; + ssize_t bytes; + + bytes =3D write(fd, &resp, sizeof(resp)); + trace_vtd_prq_write_response(id, fd, cookie, code, bytes); + if (bytes < 0) { + error_report_once("FAULTQ(id %u): write failed " + "[cookie 0x%x code 0x%x] (%m)", id, cookie, code= ); + } +} + +static void vtd_prq_response_notify(VTDAccelPASIDCacheEntry *vtd_pce, + IOMMUPRIResponse *response) +{ + VTDPRQEntry *prqe, *tmp; + + QLIST_FOREACH_SAFE(prqe, &vtd_pce->vtd_prq_list, next, tmp) { + if (prqe->grpid !=3D response->prgi) { + continue; + } + + vtd_prq_write_response(vtd_pce, prqe->cookie, response->response_c= ode); + + QLIST_REMOVE(prqe, next); + g_free(prqe); + } +} + +bool vtd_accel_propagate_page_group_response(IntelIOMMUState *s, + uint16_t rid, uint32_t pasid, + IOMMUPRIResponse *response) +{ + VTDAddressSpace *vtd_as =3D vtd_get_as_by_sid(s, rid); + VTDAccelPASIDCacheEntry *vtd_pce; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(vtd_as); + + if (!vtd_hiod) { + return false; + } + + QLIST_FOREACH(vtd_pce, &vtd_hiod->pasid_cache_list, next) { + if (vtd_pce->pasid =3D=3D pasid) { + vtd_prq_response_notify(vtd_pce, response); + return true; + } + } + + return false; +} + static void vtd_prq_report_fault(VTDAccelPASIDCacheEntry *vtd_pce, struct iommu_hwpt_pgfault *fault, unsigne= d cnt) { @@ -87,14 +142,42 @@ static void vtd_prq_report_fault(VTDAccelPASIDCacheEnt= ry *vtd_pce, =20 for (; cnt--; fault++) { bool last_page =3D fault->flags & IOMMU_PGFAULT_FLAGS_LAST_PAGE; + int ret; + + ret =3D vtd_pri_request_page(vtd_hiod->bus, vtd_hiod->iommu_state, + vtd_hiod->devfn, pasid, + fault->perm & IOMMU_PGFAULT_PERM_PRIV, + fault->perm & IOMMU_PGFAULT_PERM_EXEC, + fault->addr, last_page, fault->grpid, + fault->perm & IOMMU_PGFAULT_PERM_READ, + fault->perm & IOMMU_PGFAULT_PERM_WRITE); + if (!last_page) { + continue; + } + + if (!ret) { + VTDPRQEntry *prqe =3D g_malloc0(sizeof(*prqe)); + + prqe->grpid =3D fault->grpid; + prqe->cookie =3D fault->cookie; + QLIST_INSERT_HEAD(&vtd_pce->vtd_prq_list, prqe, next); + continue; + } =20 - vtd_pri_request_page(vtd_hiod->bus, vtd_hiod->iommu_state, - vtd_hiod->devfn, pasid, - fault->perm & IOMMU_PGFAULT_PERM_PRIV, - fault->perm & IOMMU_PGFAULT_PERM_EXEC, - fault->addr, last_page, fault->grpid, - fault->perm & IOMMU_PGFAULT_PERM_READ, - fault->perm & IOMMU_PGFAULT_PERM_WRITE); + /* + * vt-d spec 7.4.1: + * + * Hardware generates page group response with code of success for + * PRQ overflow and PRQ full, with code of invalid request for + * other error conditions. + */ + if (ret =3D=3D -ENOSPC) { + vtd_prq_write_response(vtd_pce, fault->cookie, + IOMMUFD_PAGE_RESP_SUCCESS); + } else { + vtd_prq_write_response(vtd_pce, fault->cookie, + IOMMUFD_PAGE_RESP_INVALID); + } } } =20 @@ -424,6 +507,7 @@ static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd_h= iod, uint32_t pasid, vtd_pce->pasid =3D pasid; vtd_pce->pasid_entry =3D *pe; vtd_pce->fault_fd =3D -1; + QLIST_INIT(&vtd_pce->vtd_prq_list); QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next); =20 if (!vtd_device_attach_iommufd(vtd_pce, &local_err)) { diff --git a/hw/i386/trace-events b/hw/i386/trace-events index dca726c9b8..bfdb100e8d 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -78,6 +78,7 @@ vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, u= int32_t hwpt_id, int re vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" vtd_prq_read_fault(uint32_t fault_id, uint32_t fault_fd, ssize_t bytes) "f= ault_id %d fault_fd %d ret: %zd" +vtd_prq_write_response(uint32_t fault_id, uint32_t fault_fd, uint32_t cook= ie, uint32_t code, ssize_t bytes) "fault_id %d fault_fd %d cookie %d code %= d ret: %zd" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.52.0 From nobody Sat Sep 26 20:51:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="88500037" X-IronPort-AV: E=Sophos;i="6.25,252,1779174000"; d="scan'208";a="88500037" X-CSE-ConnectionGUID: Eaom/2bvTRmcxBaPIoez4w== X-CSE-MsgGUID: QTHsoa5NSS2MqDyUP/ADWQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,252,1779174000"; d="scan'208";a="272554471" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowangio@gmail.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, Zhenzhong Duan , Xudong Hao Subject: [PATCH v5 6/6] intel_iommu_accel: teardown FAULTQ resources in bottom half Date: Mon, 31 Aug 2026 17:51:59 +0800 Message-ID: <20260831095200.1279366-7-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260831095200.1279366-1-zhenzhong.duan@intel.com> References: <20260831095200.1279366-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.19; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1788169975469158500 Content-Type: text/plain; charset="utf-8" When a pasid entry becomes invalid, we need to release all resources allocated for that entry including FAULTQ object and fault_fd. We call qemu_set_fd_handler() to detach fault_fd's io_read handler and wakes up main thread from poll(), but there could still be a small window we call iommufd_backend_free_id(fault_id) before poll() exit and release fault_id file reference. In this rare case, FAULTQ object free return -EBUSY because opened fault_id file keeps reference of FAULTQ object. Teardown FAULTQ resources in bottom half to ensure poll() has released fault_id file reference. Suggested-by: Shameer Kolothum Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.c | 40 ++++++++++++++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 7d54ce12e9..ff63ef8300 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -270,17 +270,51 @@ free_faultq: return false; } =20 +typedef struct IOMMUFaultQueue { + IOMMUFDBackend *iommufd; + uint32_t id; + int fd; + QLIST_HEAD(, VTDPRQEntry) vtd_prq_list; +} IOMMUFaultQueue; + +static void faultq_teardown_bh(void *opaque) +{ + IOMMUFaultQueue *fq =3D opaque; + VTDPRQEntry *prqe, *next; + + QLIST_FOREACH_SAFE(prqe, &fq->vtd_prq_list, next, next) { + QLIST_REMOVE(prqe, next); + g_free(prqe); + } + + qemu_set_fd_handler(fq->fd, NULL, NULL, NULL); + close(fq->fd); + iommufd_backend_free_id(fq->iommufd, fq->id); + + g_free(fq); +} + static void vtd_destroy_old_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce) { + HostIOMMUDeviceIOMMUFD *idev =3D + HOST_IOMMU_DEVICE_IOMMUFD(vtd_pce->vtd_hiod->hiod); + IOMMUFaultQueue *fq; + if (vtd_pce->fault_fd < 0) { return; } =20 - qemu_set_fd_handler(vtd_pce->fault_fd, NULL, NULL, NULL); - vtd_destroy_fs_faultq(vtd_pce->vtd_hiod, vtd_pce->fault_id, - vtd_pce->fault_fd); + fq =3D g_malloc(sizeof(IOMMUFaultQueue)); + fq->iommufd =3D idev->iommufd; + fq->fd =3D vtd_pce->fault_fd; + fq->id =3D vtd_pce->fault_id; vtd_pce->fault_id =3D 0; vtd_pce->fault_fd =3D -1; + fq->vtd_prq_list.lh_first =3D vtd_pce->vtd_prq_list.lh_first; + QLIST_INIT(&vtd_pce->vtd_prq_list); + + aio_bh_schedule_oneshot(iohandler_get_aio_context(), + faultq_teardown_bh, fq); } =20 static void vtd_setup_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce, --=20 2.52.0