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Mon, 31 Aug 2026 07:22:37 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6945F20040; Mon, 31 Aug 2026 07:22:34 +0000 (GMT) Received: from Narayanas-MacBook-Pro.bl1-in.ibm.com (unknown [9.123.3.199]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 07:22:34 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=allVduVGsPWQkc6j4 JKlUIUvGuRhvY6VPgVwnFjqutw=; b=m7HnHdFsbjEa4NcKM5OJ7Ma4j2Qar3EcN KaMg+42kZWIM2YgoMAYmXE+llt8h0YXduWbW2Hm6+OzCf8d60wTbQgEM5WkY8b4P PN1xSp+DxLLdylphPT0PiQH99QpHiUvVMA8IGp3nswzAuC1RuBjvSWjs8BZNjRmt Wxf30YsrvQkBh93s2z0UQLUfsMS7CfXcGxU+2pWmjrebok762Js5clDqv8jpzRZL R6SooynZtiVQWXA9/fvc4TKFSKhN9FuOF1kVaY8X5r+Pf3hQ5kg5JVtUb59F0DOX 0tVuvA3UdF9mKDFgRMsDNRvnxv2J7kunDtYfbW80osqmSmTUNY8jg== From: Narayana Murty N To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, mahesh@linux.ibm.com, sbhat@linux.ibm.com, anushree.mathur@linux.vnet.ibm.com, clg@redhat.com, sourabhjain@linux.ibm.com, adityag@linux.ibm.com, nikhilks@linux.ibm.com Cc: pierrick.bouvier@oss.qualcomm.com, rathc@linux.ibm.com, npiggin@gmail.com, harshpb@linux.ibm.com, amachhiw@linux.ibm.com, hbathini@linux.ibm.com, shivangu@linux.ibm.com Subject: [PATCH v4 1/6] ppc/spapr: Add VFIO EEH error injection backend Date: Mon, 31 Aug 2026 12:49:53 +0530 Message-ID: <20260831071958.58824-2-nnmlinux@linux.ibm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260831071958.58824-1-nnmlinux@linux.ibm.com> References: <20260831071958.58824-1-nnmlinux@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=EIc2FVZC c=1 sm=1 tr=0 ts=6a952bc5 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=0fC1r5mNT4k1lSFpsBYA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA1OSBTYWx0ZWRfXy1eyyPkuMir5 Jq7ZqhXCBw9//PuAW0fGNoMHzQpWNSDeFgSgxDVRmldqYq7FJLVaCwGve2imWBcw9IiLurLtWNO s2T96J66utXEg5eER++n7e9NSolu9/yLCiOUcSQ/ucx9yZFS98af4/NCq0lBcYxOfW3oZRveCnI pAFlH1w6vqXh1TSOWwTADpcOCkEzQ2sDgxEiSlXasF4Gr81FG22a4A8QJ1L363oOpEnoRFSTCh8 mygFELxHCubZtcss4EkSskFfRXOIwKNOZhMlhiHLqxHSUXbulsKGtglknLpIeyrXN4X2AvYcEQz rt8xlTu8YgB8GZPbMKV2rgn0gcExEff1/xZknUWBYNZudTvwUnu9JNz60a1N35eZQ+E7kAZpMkU p0RqrCYqZRYhbaJzTPPc24Zm5sbcX82rphh9mlRfj0KsC1IFtwsOoC/ZQjpMn9mUla5jzDN/vHn P1rywcoWmdNchJEVoFw== X-Proofpoint-GUID: 6LQaR8Ypn5Ul0eQFQy9oJSZzMMc2VtdE X-Proofpoint-ORIG-GUID: i1JXXCu9fVOGtIFf7Mwr3mnGGYWcavqM X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA1OSBTYWx0ZWRfXzCrRuWVWEkRF AvkzUtNsvHlZJd3/cxD4wHJGJAhNN7qWntqd9KdRDOIBKYMswqi6tB6bRCTv/d7Hl4G9LcZGM8y upoRjjn5Mvo+NCACpD2cM9/0AmPVXoE= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_02,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 phishscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310059 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=nnmlinux@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1788160989885154100 Content-Type: text/plain; charset="utf-8" Add spapr_phb_vfio_errinjct() to the VFIO EEH backend in spapr_pci_vfio.c. The function maps guest RTAS IOA bus-error types to the corresponding VFIO EEH ioctl error types: RTAS_ERR_TYPE_IOA_BUS_ERROR -> EEH_ERR_TYPE_32 RTAS_ERR_TYPE_IOA_BUS_ERROR_64 -> EEH_ERR_TYPE_64 EEH_ERR_TYPE_32 / EEH_ERR_TYPE_64 are imported from the powerpc UAPI EEH header where available; fallback numeric definitions are provided to guard against older build environments. The backend consumes type, func, addr, and mask from the caller. It does not accept or interpret config_addr; PHB/PE selection is the caller's responsibility via the sphb pointer. Supporting type definitions are added to include/hw/ppc/spapr.h: - EEH_ERR_FUNC_* and EEH_ERR_FUNC_MAX - EEH_ERR_TYPE_32 / EEH_ERR_TYPE_64 (with #ifndef guards) - enum rtas_err_type (RTAS ibm,errinjct error token values) - RTAS_IBM_ERRINJCT token The function prototype is added to include/hw/pci-host/spapr.h inside the CONFIG_LINUX ifdef block alongside the other EEH hooks. Signed-off-by: Narayana Murty N --- hw/ppc/spapr_pci_vfio.c | 75 +++++++++++++++++++++++++++++++++++++ include/hw/pci-host/spapr.h | 8 ++++ include/hw/ppc/spapr.h | 60 ++++++++++++++++++++++++++++- 3 files changed, 142 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c index a748a0bf4c..7afca0cec6 100644 --- a/hw/ppc/spapr_pci_vfio.c +++ b/hw/ppc/spapr_pci_vfio.c @@ -26,6 +26,7 @@ #include "hw/pci/pci_device.h" #include "hw/vfio/vfio-container-legacy.h" #include "qemu/error-report.h" +#include "hw/vfio/pci.h" #include CONFIG_DEVICES /* CONFIG_VFIO_PCI */ =20 /* @@ -317,6 +318,74 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) return RTAS_OUT_SUCCESS; } =20 +static int spapr_vfio_errinjct_rtas_type_to_vfio(uint32_t rtas_type) +{ + switch (rtas_type) { + case RTAS_ERR_TYPE_IOA_BUS_ERROR: + return EEH_ERR_TYPE_32; + case RTAS_ERR_TYPE_IOA_BUS_ERROR_64: + return EEH_ERR_TYPE_64; + default: + return -1; + } +} + +static bool spapr_vfio_errinjct_func_valid(uint32_t func) +{ + return func <=3D EEH_ERR_FUNC_MAX; +} + +int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, + uint32_t func, uint64_t addr, uint64_t mask) +{ + VFIOLegacyContainer *container; + struct vfio_eeh_pe_op op =3D { + .op =3D VFIO_EEH_PE_INJECT_ERR, + .argsz =3D sizeof(op), + }; + int vfio_type; + + if (!sphb) { + return RTAS_OUT_PARAM_ERROR; + } + + if (!spapr_vfio_errinjct_func_valid(func)) { + return RTAS_OUT_PARAM_ERROR; + } + + vfio_type =3D spapr_vfio_errinjct_rtas_type_to_vfio(type); + if (vfio_type < 0) { + return RTAS_OUT_NOT_SUPPORTED; + } + + container =3D vfio_eeh_as_container(&sphb->iommu_as); + if (!container) { + error_report("vfio/eeh errinjct: no VFIO EEH container for PHB"); + return RTAS_OUT_NOT_SUPPORTED; + } + + op.err.type =3D vfio_type; + op.err.func =3D func; + op.err.addr =3D addr; + op.err.mask =3D mask; + + if (ioctl(container->fd, VFIO_EEH_PE_OP, &op) < 0) { + error_report("vfio/eeh errinjct: VFIO_EEH_PE_OP failed: %s", + strerror(errno)); + switch (errno) { + case EINVAL: + return RTAS_OUT_PARAM_ERROR; + case ENOTTY: + case EOPNOTSUPP: + return RTAS_OUT_NOT_SUPPORTED; + default: + return RTAS_OUT_HW_ERROR; + } + } + + return RTAS_OUT_SUCCESS; +} + #else =20 bool spapr_phb_eeh_available(SpaprPhbState *sphb) @@ -349,4 +418,10 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) return RTAS_OUT_NOT_SUPPORTED; } =20 +int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, + uint32_t func, uint64_t addr, uint64_t mask) +{ + return RTAS_OUT_NOT_SUPPORTED; +} + #endif /* CONFIG_VFIO_PCI */ diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 0db87f1281..24109409f4 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -125,6 +125,8 @@ int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, i= nt *state); int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option); int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb); void spapr_phb_vfio_reset(DeviceState *qdev); +int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, + uint32_t func, uint64_t addr, uint64_t mask); #else static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb) { @@ -151,6 +153,12 @@ static inline int spapr_phb_vfio_eeh_configure(SpaprPh= bState *sphb) static inline void spapr_phb_vfio_reset(DeviceState *qdev) { } +static inline int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t ty= pe, + uint32_t func, uint64_t addr, + uint64_t mask) +{ + return RTAS_OUT_NOT_SUPPORTED; +} #endif =20 void spapr_phb_dma_reset(SpaprPhbState *sphb); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 9acda15d4f..253dc0e862 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -682,6 +682,63 @@ void push_sregs_to_kvm_pr(SpaprMachineState *spapr); #define RTAS_EEH_PE_UNAVAIL_INFO 1000 #define RTAS_EEH_PE_RECOVER_INFO 0 =20 +/* EEH error injection types and functions */ +#define EEH_ERR_FUNC_MIN 0 +#define EEH_ERR_FUNC_LD_MEM_ADDR 0 /* Memory load */ +#define EEH_ERR_FUNC_LD_MEM_DATA 1 +#define EEH_ERR_FUNC_LD_IO_ADDR 2 /* IO load */ +#define EEH_ERR_FUNC_LD_IO_DATA 3 +#define EEH_ERR_FUNC_LD_CFG_ADDR 4 /* Config load */ +#define EEH_ERR_FUNC_LD_CFG_DATA 5 +#define EEH_ERR_FUNC_ST_MEM_ADDR 6 /* Memory store */ +#define EEH_ERR_FUNC_ST_MEM_DATA 7 +#define EEH_ERR_FUNC_ST_IO_ADDR 8 /* IO store */ +#define EEH_ERR_FUNC_ST_IO_DATA 9 +#define EEH_ERR_FUNC_ST_CFG_ADDR 10 /* Config store */ +#define EEH_ERR_FUNC_ST_CFG_DATA 11 +#define EEH_ERR_FUNC_DMA_RD_ADDR 12 /* DMA read */ +#define EEH_ERR_FUNC_DMA_RD_DATA 13 +#define EEH_ERR_FUNC_DMA_RD_MASTER 14 +#define EEH_ERR_FUNC_DMA_RD_TARGET 15 +#define EEH_ERR_FUNC_DMA_WR_ADDR 16 /* DMA write */ +#define EEH_ERR_FUNC_DMA_WR_DATA 17 +#define EEH_ERR_FUNC_DMA_WR_MASTER 18 +#define EEH_ERR_FUNC_DMA_WR_TARGET 19 +#define EEH_ERR_FUNC_MAX EEH_ERR_FUNC_DMA_WR_TARGET + +/* + * RTAS ibm,errinjct error type byte values. These are RTAS ABI token + * numbers, not the same as the VFIO EEH ABI type values consumed by + * VFIO_EEH_PE_INJECT_ERR. An explicit mapping is required. + */ +/* Use powerpc EEH UAPI constants where available; define locally otherwis= e. */ +#ifndef EEH_ERR_TYPE_32 +#define EEH_ERR_TYPE_32 0 +#endif +#ifndef EEH_ERR_TYPE_64 +#define EEH_ERR_TYPE_64 1 +#endif + +/* RTAS PCI Error Injection Token Types */ +enum rtas_err_type { + RTAS_ERR_TYPE_FATAL =3D 0x1, + RTAS_ERR_TYPE_RECOVERED_RANDOM_EVENT =3D 0x2, + RTAS_ERR_TYPE_RECOVERED_SPECIAL_EVENT =3D 0x3, + RTAS_ERR_TYPE_CORRUPTED_PAGE =3D 0x4, + RTAS_ERR_TYPE_CORRUPTED_SLB =3D 0x5, + RTAS_ERR_TYPE_TRANSLATOR_FAILURE =3D 0x6, + RTAS_ERR_TYPE_IOA_BUS_ERROR =3D 0x7, + RTAS_ERR_TYPE_PLATFORM_SPECIFIC =3D 0x8, + RTAS_ERR_TYPE_CORRUPTED_DCACHE_START =3D 0x9, + RTAS_ERR_TYPE_CORRUPTED_DCACHE_END =3D 0xA, + RTAS_ERR_TYPE_CORRUPTED_ICACHE_START =3D 0xB, + RTAS_ERR_TYPE_CORRUPTED_ICACHE_END =3D 0xC, + RTAS_ERR_TYPE_CORRUPTED_TLB_START =3D 0xD, + RTAS_ERR_TYPE_CORRUPTED_TLB_END =3D 0xE, + RTAS_ERR_TYPE_IOA_BUS_ERROR_64 =3D 0xF, + RTAS_ERR_TYPE_UPSTREAM_IO_ERROR =3D 0x10 +}; + /* ibm,set-slot-reset */ #define RTAS_SLOT_RESET_DEACTIVATE 0 #define RTAS_SLOT_RESET_HOT 1 @@ -764,8 +821,9 @@ void push_sregs_to_kvm_pr(SpaprMachineState *spapr); #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) #define RTAS_CONFIGURE_KERNEL_DUMP (RTAS_TOKEN_BASE + 0x2D) +#define RTAS_IBM_ERRINJCT (RTAS_TOKEN_BASE + 0x2E) =20 -#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2E) +#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2F) =20 /* RTAS ibm,get-system-parameter token values */ #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 --=20 2.54.0 From nobody Sat Sep 26 20:50:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1788161026; cv=none; d=zohomail.com; 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Mon, 31 Aug 2026 07:22:37 +0000 (GMT) Received: from Narayanas-MacBook-Pro.bl1-in.ibm.com (unknown [9.123.3.199]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 07:22:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=CU9SRv925/IFyKdv8 epUtzAo+rNFHtg8dPkLjY8QfDY=; b=GmdhcICjphB7OAQFMLdRlpriSoGFedpVa +E8/vlnVzQPPAgjHESDafQDporvpDZrV6XwGFC1f974SkMH6Kmu20gRvN4N6pEwX UqHCoboT00d28k3tpxjATZttRDSUu/nbGYR5J9dyzRq8+mj0dNv/aPDbNkTB3ZEt KkPLDTKkOT5y2LcWDy244A+p9rGo3M4ndnWhpHrgaTxE7bbjE0Cvmu2pnBWvz/sI 7QhD8H7qKwybd1h4e3G44bskdADTqGTrMOxt9d/crxAcsEqOzhgGDhr8bJ0T2z1K 5GDjunKdu6Jgl5NQerkAODS8a8ss1l3rLOOBhbTMQDn6mhFc5a69w== From: Narayana Murty N To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, mahesh@linux.ibm.com, sbhat@linux.ibm.com, anushree.mathur@linux.vnet.ibm.com, clg@redhat.com, sourabhjain@linux.ibm.com, adityag@linux.ibm.com, nikhilks@linux.ibm.com Cc: pierrick.bouvier@oss.qualcomm.com, rathc@linux.ibm.com, npiggin@gmail.com, harshpb@linux.ibm.com, amachhiw@linux.ibm.com, hbathini@linux.ibm.com, shivangu@linux.ibm.com Subject: [PATCH v4 2/6] ppc/spapr: Add ibm,errinjct RTAS call handler Date: Mon, 31 Aug 2026 12:49:54 +0530 Message-ID: <20260831071958.58824-3-nnmlinux@linux.ibm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260831071958.58824-1-nnmlinux@linux.ibm.com> References: <20260831071958.58824-1-nnmlinux@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=bc1bluPB c=1 sm=1 tr=0 ts=6a952bc6 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=ckvBqbd_4HPzd86GAI0A:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA1OSBTYWx0ZWRfXwhWoC0FM67IK mxTrUIM5p8WPBObloQWFFIZ5fRl7FBkWhter9DoSeV4yko+dkfFQ2Bi4qaIPXPs5HxenvJYW9g3 oMAR/Bya3spVUZiu1vNEjgy5tyoQ/yM= X-Proofpoint-ORIG-GUID: koZsECWiNJyVBAEODctH_IDt1IB0abOQ X-Proofpoint-GUID: SNuzuASgw3WF3fezcmOzUAuHme5G0GBt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA1OSBTYWx0ZWRfXzwi1dbnY9+V2 U8UV7mTh0F4h4aF1S5ciOEZ+cYPdBshhnS7sW79/Xh2jFztqmA30Ft+ubjRqalUmq4288cMHPN3 vP7YwmG3qcLaJ3pkM356PRk8h1hpgflJFgpXkOWcOts36Ni62gBoumGxlKihLlNRrpjFJ5/XLzM VpolQVlOBUUXq8H/FVXZczDjWmtteJgxsP9BlLa1xCaUxAhjZtL3tuhVWGprU/p3sRdu0u/xI8c usH8N8IWFvW85I/6CJipimS9YHclHJXSHnAP8KjxavVn/ZIn43EnT07VTsxuFS5ft2nLJAlxO5I VgT5ScUZ25ciaFaW6pXDXQJoNK/Zyvu30Nxl8/AC1T6C4C7F1DAjRLymNHfMQJOtWgDWqNBTa6N AWqU0ARkRF7ajpRwp4RrJQKpo6cTa+eGj3L6SW6XSicnmi1MYdVUvd3tkJE0W9y8v9uYZ94vR7Q vQYi5Asu8MGLp4kBhxg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_02,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 adultscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310059 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=nnmlinux@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1788161028328154100 Content-Type: text/plain; charset="utf-8" Implement the 'ibm,errinjct' RTAS call for PHB-level PCI error injection via firmware. The handler decodes the RTAS parameter buffer, validates arguments, selects the target PHB by BUID, and delegates the injection to the VFIO EEH backend. IOA bus-error injection (types 0x7 and 0xF) is fully supported: - The BUID field in the RTAS parameter block selects the target PHB via spapr_pci_find_phb(); =20 - For addr !=3D 0 or mask !=3D 0 the guest BAR address is translated to the corresponding host resource base address before calling the VFIO backend. Translation matches the guest BAR layout under the selected PHB, computes offset =3D guest_addr - guest_bar, reads the host sysfs resource file for the matching BAR, and yields host_addr =3D host_bar + offset. - For addr =3D=3D 0 and mask =3D=3D 0 translation is skipped and zero addr/mask are forwarded directly (powerpc-utils errinjct -a 0 -m 0). Non-IOA error types (corrupted-page, dcache, icache, tlb, recovered-special-event) are decoded and validated, then rejected with RTAS_OUT_NOT_SUPPORTED because their RTAS work buffers do not carry a BUID, making safe VFIO PHB/PE selection impossible. The translation helpers added to spapr_pci_vfio.c: - spapr_phb_vfio_translate_errinjct_addr() - public entry point - spapr_vfio_errinjct_find_bar_cb() - per-device BAR scan - spapr_vfio_errinjct_get_host_bar() - host sysfs BAR reader config_addr is retained as a logging/debug parameter only; PHB selection relies on BUID. Signed-off-by: Narayana Murty N --- hw/ppc/spapr_pci.c | 135 ++++++++++++++++++++++++ hw/ppc/spapr_pci_vfio.c | 203 ++++++++++++++++++++++++++++++++++++ include/hw/pci-host/spapr.h | 11 ++ include/hw/ppc/spapr.h | 3 + 4 files changed, 352 insertions(+) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index c1d4b7806e..cff12ef268 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -704,6 +704,138 @@ param_error_exit: rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); } =20 +static int spapr_errinjct_parse_ioa_bus_error(target_ulong param_buf, + bool is_64bit, + uint64_t *addr, uint64_t *ma= sk, + uint32_t *config_addr, + uint64_t *buid, uint32_t *fu= nc) +{ + if (is_64bit) { + *addr =3D ((uint64_t)rtas_ld(param_buf, 0) << 32) | + rtas_ld(param_buf, 1); + *mask =3D ((uint64_t)rtas_ld(param_buf, 2) << 32) | + rtas_ld(param_buf, 3); + *config_addr =3D rtas_ld(param_buf, 4); + *buid =3D ((uint64_t)rtas_ld(param_buf, 5) << 32) | + rtas_ld(param_buf, 6); + *func =3D rtas_ld(param_buf, 7); + } else { + *addr =3D rtas_ld(param_buf, 0); + *mask =3D rtas_ld(param_buf, 1); + *config_addr =3D rtas_ld(param_buf, 2); + *buid =3D ((uint64_t)rtas_ld(param_buf, 3) << 32) | + rtas_ld(param_buf, 4); + *func =3D rtas_ld(param_buf, 5); + } + return RTAS_OUT_SUCCESS; +} + +/* + * Non-IOA RTAS error types (page corrupt, dcache, icache, tlb, special + * event) are validated but not supported for VFIO injection. VFIO EEH + * is PE/PHB-scoped and those work buffers do not carry a BUID, so QEMU + * cannot select the right VFIO container safely. + */ +static void spapr_errinjct_return_non_ioa_unsupported(target_ulong rets) +{ + rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); +} + +static void rtas_ibm_errinjct(PowerPCCPU *cpu, SpaprMachineState *spapr, + uint32_t token, uint32_t nargs, + target_ulong args, uint32_t nret, + target_ulong rets) +{ + SpaprPhbState *sphb =3D NULL; + target_ulong param_buf; + uint64_t addr =3D 0, mask =3D 0, buid =3D 0; + uint64_t inject_addr =3D 0; + uint32_t config_addr =3D 0; + uint32_t func =3D 0; + uint32_t type, o_token; + bool is_64bit; + int ret; + + if (nargs !=3D 3 || nret !=3D 1) { + goto param_error_exit; + } + + type =3D rtas_ld(args, 0); + o_token =3D rtas_ld(args, 1); + param_buf =3D rtas_ld(args, 2); + + if (!param_buf) { + goto param_error_exit; + } + + if (!spapr->errinjct_token || o_token !=3D spapr->errinjct_token) { + goto param_error_exit; + } + + switch (type) { + case RTAS_ERR_TYPE_IOA_BUS_ERROR: + case RTAS_ERR_TYPE_IOA_BUS_ERROR_64: + is_64bit =3D (type =3D=3D RTAS_ERR_TYPE_IOA_BUS_ERROR_64); + ret =3D spapr_errinjct_parse_ioa_bus_error(param_buf, is_64bit, + &addr, &mask, + &config_addr, &buid, &fun= c); + if (ret !=3D RTAS_OUT_SUCCESS) { + goto param_error_exit; + } + break; + + case RTAS_ERR_TYPE_RECOVERED_SPECIAL_EVENT: + case RTAS_ERR_TYPE_CORRUPTED_PAGE: + case RTAS_ERR_TYPE_CORRUPTED_DCACHE_START: + case RTAS_ERR_TYPE_CORRUPTED_DCACHE_END: + case RTAS_ERR_TYPE_CORRUPTED_ICACHE_START: + case RTAS_ERR_TYPE_CORRUPTED_ICACHE_END: + case RTAS_ERR_TYPE_CORRUPTED_TLB_START: + case RTAS_ERR_TYPE_CORRUPTED_TLB_END: + spapr_errinjct_return_non_ioa_unsupported(rets); + return; + + default: + goto param_error_exit; + } + + /* IOA path: BUID selects the target PHB */ + if (!buid) { + goto param_error_exit; + } + + sphb =3D spapr_pci_find_phb(spapr, buid); + if (!sphb) { + error_report("ibm,errinjct: no PHB for BUID=3D0x%016" PRIx64, buid= ); + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); + return; + } + + inject_addr =3D addr; + + /* + * addr=3D0, mask=3D0 means a non-address-scoped IOA injection. This + * matches powerpc-utils errinjct -a 0 -m 0 behaviour; skip translation + * and forward addr/mask as zero. + */ + if (addr || mask) { + ret =3D spapr_phb_vfio_translate_errinjct_addr(sphb, config_addr, + addr, &inject_addr); + if (ret) { + rtas_st(rets, 0, ret =3D=3D -EOPNOTSUPP ? RTAS_OUT_NOT_SUPPORT= ED + : RTAS_OUT_PARAM_ERROR); + return; + } + } + + ret =3D spapr_phb_vfio_errinjct(sphb, type, func, inject_addr, mask); + rtas_st(rets, 0, ret); + return; + +param_error_exit: + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); +} + static void pci_spapr_set_irq(void *opaque, int irq_num, int level) { /* @@ -2380,6 +2512,9 @@ void spapr_pci_rtas_init(void) spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, "ibm,slot-error-detail", rtas_ibm_slot_error_detail); + spapr_rtas_register(RTAS_IBM_ERRINJCT, + "ibm,errinjct", + rtas_ibm_errinjct); } =20 static void spapr_pci_register_types(void) diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c index 7afca0cec6..2f428531cc 100644 --- a/hw/ppc/spapr_pci_vfio.c +++ b/hw/ppc/spapr_pci_vfio.c @@ -318,6 +318,201 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) return RTAS_OUT_SUCCESS; } =20 +typedef struct SpaprVFIOErrinjctBarMatch { + uint64_t guest_addr; + + PCIDevice *pdev; + VFIOPCIDevice *vdev; + int bar; + + uint64_t guest_bar_start; + uint64_t bar_size; + uint64_t offset; +} SpaprVFIOErrinjctBarMatch; + +static VFIOPCIDevice *spapr_vfio_errinjct_pci_to_vfio(PCIDevice *pdev) +{ + if (!object_dynamic_cast(OBJECT(pdev), TYPE_VFIO_PCI)) { + return NULL; + } + + return container_of(pdev, VFIOPCIDevice, parent_obj); +} + +static void spapr_vfio_errinjct_find_bar_cb(PCIBus *bus, + PCIDevice *pdev, + void *opaque) +{ + SpaprVFIOErrinjctBarMatch *ctx =3D opaque; + VFIOPCIDevice *vdev; + int bar; + + if (ctx->pdev) { + return; + } + + vdev =3D spapr_vfio_errinjct_pci_to_vfio(pdev); + if (!vdev) { + return; + } + + for (bar =3D 0; bar < PCI_STD_NUM_BARS; bar++) { + pcibus_t guest_bar_start; + uint64_t bar_size; + uint64_t offset; + + bar_size =3D vdev->bars[bar].region.size; + if (!bar_size) { + continue; + } + + guest_bar_start =3D pci_get_bar_addr(pdev, bar); + if (guest_bar_start =3D=3D PCI_BAR_UNMAPPED) { + continue; + } + + if (ctx->guest_addr < guest_bar_start || + ctx->guest_addr - guest_bar_start >=3D bar_size) { + if (vdev->bars[bar].mem64) { + bar++; + } + continue; + } + + offset =3D ctx->guest_addr - guest_bar_start; + + ctx->pdev =3D pdev; + ctx->vdev =3D vdev; + ctx->bar =3D bar; + ctx->guest_bar_start =3D guest_bar_start; + ctx->bar_size =3D bar_size; + ctx->offset =3D offset; + + return; + } +} + +static int spapr_vfio_errinjct_get_host_bar(VFIOPCIDevice *vdev, + int bar, + uint64_t *host_bar_start) +{ + g_autofree char *path =3D NULL; + g_autofree char *contents =3D NULL; + char *line; + char *saveptr =3D NULL; + unsigned long long start; + unsigned long long end; + unsigned long long flags; + int i; + + if (!vdev || !host_bar_start || bar < 0 || bar >=3D PCI_STD_NUM_BARS) { + return -EINVAL; + } + + /* + * Read the host Linux sysfs resource file for the BAR. Do not use a + * VFIO PCI config-space read because that may return the + * guest-programmed BAR value rather than the host resource address. + */ + path =3D g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%u/resou= rce", + vdev->host.domain, + vdev->host.bus, + vdev->host.slot, + vdev->host.function); + + if (!g_file_get_contents(path, &contents, NULL, NULL)) { + error_report("vfio/eeh errinjct: failed to read %s", path); + return -ENOENT; + } + + line =3D strtok_r(contents, "\n", &saveptr); + + for (i =3D 0; line; i++, line =3D strtok_r(NULL, "\n", &saveptr)) { + if (i !=3D bar) { + continue; + } + + if (sscanf(line, "%llx %llx %llx", &start, &end, &flags) !=3D 3) { + error_report("vfio/eeh errinjct: malformed %s BAR%d", + path, bar); + return -EINVAL; + } + + if (!start || end < start) { + error_report("vfio/eeh errinjct: invalid host resource BAR%d " + "start=3D0x%llx end=3D0x%llx flags=3D0x%llx", + bar, start, end, flags); + return -EINVAL; + } + + *host_bar_start =3D start; + return 0; + } + + return -EINVAL; +} + +int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, + uint32_t config_addr, + uint64_t guest_addr, + uint64_t *host_pci_bus_addr) +{ + PCIHostState *phb; + SpaprVFIOErrinjctBarMatch ctx =3D { + .guest_addr =3D guest_addr, + .pdev =3D NULL, + .vdev =3D NULL, + .bar =3D -1, + }; + uint64_t host_bar_start; + int rc; + + if (!sphb || !host_pci_bus_addr) { + return -EINVAL; + } + + phb =3D PCI_HOST_BRIDGE(sphb); + + /* + * BUID has already selected @sphb before this helper is called. + * config_addr is retained for logging/debug only. Do not rely on it + * to find the target device; some RTAS IOA buffers may not carry a + * valid guest BDF-style config address. Scan VFIO BARs under this + * PHB and match guest_addr against the guest BAR layout instead. + */ + pci_for_each_device_under_bus(phb->bus, + spapr_vfio_errinjct_find_bar_cb, + &ctx); + + if (!ctx.pdev) { + error_report("vfio/eeh errinjct: guest addr 0x%" PRIx64 + " not within any VFIO BAR under BUID=3D0x%016" PRIx64 + " config_addr=3D0x%08x", + guest_addr, sphb->buid, config_addr); + return -ENODEV; + } + + rc =3D spapr_vfio_errinjct_get_host_bar(ctx.vdev, ctx.bar, &host_bar_s= tart); + if (rc) { + error_report("vfio/eeh errinjct: failed to get host BAR%d for " + "dev=3D%s BUID=3D0x%016" PRIx64 " config_addr=3D0x%08= x rc=3D%d", + ctx.bar, ctx.pdev->name, sphb->buid, config_addr, rc); + return rc; + } + + if (host_bar_start =3D=3D ctx.guest_bar_start) { + error_report("vfio/eeh errinjct: refusing guest BAR as host BAR: " + "dev=3D%s BAR%d guest_bar=3D0x%" PRIx64 + " host_bar=3D0x%" PRIx64, + ctx.pdev->name, ctx.bar, + ctx.guest_bar_start, host_bar_start); + return -EOPNOTSUPP; + } + + *host_pci_bus_addr =3D host_bar_start + ctx.offset; + return 0; +} + static int spapr_vfio_errinjct_rtas_type_to_vfio(uint32_t rtas_type) { switch (rtas_type) { @@ -424,4 +619,12 @@ int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint3= 2_t type, return RTAS_OUT_NOT_SUPPORTED; } =20 +int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, + uint32_t config_addr, + uint64_t guest_addr, + uint64_t *host_pci_bus_addr) +{ + return -ENOTSUP; +} + #endif /* CONFIG_VFIO_PCI */ diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 24109409f4..492f66e1ef 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -127,6 +127,10 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb); void spapr_phb_vfio_reset(DeviceState *qdev); int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, uint32_t func, uint64_t addr, uint64_t mask); +int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, + uint32_t config_addr, + uint64_t guest_addr, + uint64_t *host_pci_bus_addr); #else static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb) { @@ -159,6 +163,13 @@ static inline int spapr_phb_vfio_errinjct(SpaprPhbStat= e *sphb, uint32_t type, { return RTAS_OUT_NOT_SUPPORTED; } +static inline int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sp= hb, + uint32_t config_a= ddr, + uint64_t guest_ad= dr, + uint64_t *host_ad= dr) +{ + return -ENOTSUP; +} #endif =20 void spapr_phb_dma_reset(SpaprPhbState *sphb); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 253dc0e862..47791c71bd 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -274,6 +274,9 @@ struct SpaprMachineState { bool fadump_registered; bool fadump_dump_active; FadumpMemStruct registered_fdm; + + /* ibm,errinjct session token (0 =3D no session open) */ + uint32_t errinjct_token; }; =20 #define H_SUCCESS 0 --=20 2.54.0 From nobody Sat Sep 26 20:50:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=reject dis=none) header.from=linux.ibm.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788161014282222.85477733881044; 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Mon, 31 Aug 2026 07:22:40 +0000 (GMT) Received: from Narayanas-MacBook-Pro.bl1-in.ibm.com (unknown [9.123.3.199]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 07:22:40 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=cbDk0a1jyPnCj3SFj X4OC5xdxPHFWGFz3zijWFE2jcE=; b=iLbELb0/PsbT6CS2s8NnwrOiCDACQKCJ5 JcrU7CElFLvzOHPaFW325FpqcsziVlob04Gw/l0T5K3C4CLL80ESNVa21Wb8WqLF fs3XVegc/VQtD99UojadEooepw88ezCqDmTT37PJ41bMcedppzcf3RSCJ92q7XCe WpAE3c5ucvitYC5ck71LTcSI+4akYb6V1/4rrq52I3b8LwikDgUSvEYCqcyaYOqf PgR9ijJ50ahnYFZllCSqcE5O+eW5KLUnAa82nKDeZqCBmpBjy3D87xa/X+aOKRoR 2M7aeQ9xa6j5JQI+KS0ZpJeBnKMmchO+NGf0WxIhwK71YiROg8XJQ== From: Narayana Murty N To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, mahesh@linux.ibm.com, sbhat@linux.ibm.com, anushree.mathur@linux.vnet.ibm.com, clg@redhat.com, sourabhjain@linux.ibm.com, adityag@linux.ibm.com, nikhilks@linux.ibm.com Cc: pierrick.bouvier@oss.qualcomm.com, rathc@linux.ibm.com, npiggin@gmail.com, harshpb@linux.ibm.com, amachhiw@linux.ibm.com, hbathini@linux.ibm.com, shivangu@linux.ibm.com Subject: [PATCH v4 3/6] ppc/spapr: Add support for ibm, open-errinjct and ibm, close-errinjct Date: Mon, 31 Aug 2026 12:49:55 +0530 Message-ID: <20260831071958.58824-4-nnmlinux@linux.ibm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260831071958.58824-1-nnmlinux@linux.ibm.com> References: <20260831071958.58824-1-nnmlinux@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=bc1bluPB c=1 sm=1 tr=0 ts=6a952bc9 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=iw8L5VQ-6e4m0g-3eYQA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA1OSBTYWx0ZWRfX71e2ggG6nqR/ 4FyIKo1QvC4zBL8EiceRDAs+tgYkXYHWFjoPY0XizXj5M/taIgFlt7LQmQxPdIJx3RxcYHgKvsB QFVeESdUn8P/ZgVgF6UK9veDbRoEU6I= X-Proofpoint-ORIG-GUID: nmtjUE9yN7WxShFwRLaL05lsQWMeR-xY X-Proofpoint-GUID: 4LZHTjjy0gisDW3p05d1ElyihS0mztY6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA1OSBTYWx0ZWRfXyokN2qLAUDAa Ms6Z1rM8YEMFE6WT+9zSfH1nA6sO8zXgJfHaEFZbW/MkgXhgKq261zUpFwT/PzvTp5+KIc6SbHM wuGSp7L9EOQjb4nvvqbtr0vXAYWM81r7YTU6Kum6KFfV+S3XWzpYn/f+lUBv8hkI616bzwR5r/i yA5vxK50pSnJ63C5z6I/ONNgOIHcv88BlEvQNNp5lGEwEKhjD1Wkdnn6O0WI10Q2IXXj2Jqrwxf 05R1IaytGa+Vij8P6NAlWlwUdfMzyBcQIhqCfBUf2VwbmIEOIQIDWe+OilCgWsMAw1tM45wEF9S sTr4hlEGBmb46hLuodWBDfAwM8uSIy8AnRy+a/ftIe8b38nRhXVi7wpwZeLW7tEOakjl05awALw WQqoYxUqfSvV/N3n/NwqvKBx2aO8U2QQ2ws2XjcHPFwsPWAAbPjysDOfGm0+BnyRVUceH061vng K/x58G8xHJofcI8PRAA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_02,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 adultscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310059 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=nnmlinux@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1788161015854154100 Content-Type: text/plain; charset="utf-8" Add RTAS handlers for ibm,open-errinjct and ibm,close-errinjct. These calls manage exclusive access to the error-injection facility through a simple session token mechanism: only one session may be open at a time. ibm,open-errinjct (nargs=3D0, nret=3D2): Returns rets[0]=3Dtoken, rets[1]=3Dstatus. On success: token=3D1, status=3DRTAS_OUT_SUCCESS. Already-open: token=3D0, status=3DRTAS_OUT_ALREADY_OPEN. Bad args: token=3D0, status=3DRTAS_OUT_PARAM_ERROR. ibm,close-errinjct (nargs=3D1, nret=3D1): Takes the session token in args[0]. Returns RTAS_OUT_SUCCESS on a matching open token. Returns RTAS_OUT_NOT_OPEN if the token is invalid or no session exists. RTAS_IBM_OPEN_ERRINJCT and RTAS_IBM_CLOSE_ERRINJCT token values and RTAS_OUT_ALREADY_OPEN / RTAS_OUT_NOT_OPEN return codes are added to include/hw/ppc/spapr.h. Signed-off-by: Narayana Murty N --- hw/ppc/spapr_pci.c | 57 ++++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/spapr.h | 8 +++++- 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index cff12ef268..20cb913f12 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -836,6 +836,57 @@ param_error_exit: rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); } =20 +static void rtas_ibm_open_errinjct(PowerPCCPU *cpu, SpaprMachineState *spa= pr, + uint32_t token, uint32_t nargs, + target_ulong args, uint32_t nret, + target_ulong rets) +{ + if (nargs !=3D 0 || nret !=3D 2) { + rtas_st(rets, 0, 0); + rtas_st(rets, 1, RTAS_OUT_PARAM_ERROR); + return; + } + + if (spapr->errinjct_token) { + /* Session already open: return token=3D0, status=3DALREADY_OPEN */ + rtas_st(rets, 0, 0); + rtas_st(rets, 1, RTAS_OUT_ALREADY_OPEN); + return; + } + + spapr->errinjct_token =3D 1; + + /* + * ibm,open-errinjct has an unusual return convention: rets[0] is the + * session token and rets[1] is the status code. + */ + rtas_st(rets, 0, spapr->errinjct_token); + rtas_st(rets, 1, RTAS_OUT_SUCCESS); +} + +static void rtas_ibm_close_errinjct(PowerPCCPU *cpu, SpaprMachineState *sp= apr, + uint32_t token, uint32_t nargs, + target_ulong args, uint32_t nret, + target_ulong rets) +{ + uint32_t o_token; + + if (nargs !=3D 1 || nret !=3D 1) { + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); + return; + } + + o_token =3D rtas_ld(args, 0); + + if (!spapr->errinjct_token || o_token !=3D spapr->errinjct_token) { + rtas_st(rets, 0, RTAS_OUT_NOT_OPEN); + return; + } + + spapr->errinjct_token =3D 0; + rtas_st(rets, 0, RTAS_OUT_SUCCESS); +} + static void pci_spapr_set_irq(void *opaque, int irq_num, int level) { /* @@ -2515,6 +2566,12 @@ void spapr_pci_rtas_init(void) spapr_rtas_register(RTAS_IBM_ERRINJCT, "ibm,errinjct", rtas_ibm_errinjct); + spapr_rtas_register(RTAS_IBM_OPEN_ERRINJCT, + "ibm,open-errinjct", + rtas_ibm_open_errinjct); + spapr_rtas_register(RTAS_IBM_CLOSE_ERRINJCT, + "ibm,close-errinjct", + rtas_ibm_close_errinjct); } =20 static void spapr_pci_register_types(void) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 47791c71bd..bcb1da5fab 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -825,8 +825,14 @@ enum rtas_err_type { #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) #define RTAS_CONFIGURE_KERNEL_DUMP (RTAS_TOKEN_BASE + 0x2D) #define RTAS_IBM_ERRINJCT (RTAS_TOKEN_BASE + 0x2E) +#define RTAS_IBM_OPEN_ERRINJCT (RTAS_TOKEN_BASE + 0x2F) +#define RTAS_IBM_CLOSE_ERRINJCT (RTAS_TOKEN_BASE + 0x30) =20 -#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2F) +#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x31) + +/* ibm,open-errinjct/ibm,close-errinjct return codes */ +#define RTAS_OUT_ALREADY_OPEN -4 +#define RTAS_OUT_NOT_OPEN -5 =20 /* RTAS ibm,get-system-parameter token values */ #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 --=20 2.54.0 From nobody Sat Sep 26 20:50:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Aug 2026 07:22:46 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DC74220040; Mon, 31 Aug 2026 07:22:43 +0000 (GMT) Received: from Narayanas-MacBook-Pro.bl1-in.ibm.com (unknown [9.123.3.199]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 07:22:43 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=dNhRB15h6DtzkOqHf OMafOVUbQ/3UhWActHPrWHYlxs=; b=Y0pLz5u13G2bZioqoJ6jglWYWI/fxRzw9 XlC8M+DAt0OQ9WKAABIM6e6VPM4Qp8TevhE/swa/fOiEoxOodEDCR6g8sfeTL4hl waA0rtPG2CHlrjfBUj4hJQhnjPXmFzZNlqqCvSBHEm/LIyvKqjNJoVycVK9LMICN 1qcKpHNUfrXbxacrza56R9AeJxI3Hzo7pfW43XPfHudJPNKa2SxbuFGLbDsxCg2m WAyxhm/c0nVOm+7zTnq4KQ7U+QEQQCgyxf+lgC22fEQHozU35u8XRdNlc8AkGt/+ aB6Mv5VCJRqXalqZtsVZjCXhsCaFB1JlqWpNS9v1ufUeMjpZpmFmQ== From: Narayana Murty N To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, mahesh@linux.ibm.com, sbhat@linux.ibm.com, anushree.mathur@linux.vnet.ibm.com, clg@redhat.com, sourabhjain@linux.ibm.com, adityag@linux.ibm.com, nikhilks@linux.ibm.com Cc: pierrick.bouvier@oss.qualcomm.com, rathc@linux.ibm.com, npiggin@gmail.com, harshpb@linux.ibm.com, amachhiw@linux.ibm.com, hbathini@linux.ibm.com, shivangu@linux.ibm.com Subject: [PATCH v4 4/6] ppc/spapr: Advertise RTAS error injection call support via FDT property Date: Mon, 31 Aug 2026 12:49:56 +0530 Message-ID: <20260831071958.58824-5-nnmlinux@linux.ibm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260831071958.58824-1-nnmlinux@linux.ibm.com> References: <20260831071958.58824-1-nnmlinux@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=bc1bluPB c=1 sm=1 tr=0 ts=6a952bcc cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=LnazUrRgPASutW5i7uYA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA1OSBTYWx0ZWRfX8nsjJ433OOjL YSAq69OodUEDXNoIKV2iJo8+ioEkUP+937A21WhXL0JgBOas5ybOUM7XtD/9SA9VXw3kxMbYnpl TPNA9y8k0XUMjk7lUC238EM95ndWPkE= X-Proofpoint-ORIG-GUID: bl52ieHqQ9V8yLsEO25-oe2jDP74XybG X-Proofpoint-GUID: nmIZ3uPmAAgoU1HSYTZNkJLPQr8gFsc4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA1OSBTYWx0ZWRfXwHpvZvl5IlR3 KkgrKFpks5CxCEDYlbmIX2qSqObxRv8wKjTbAK86Q5xOsfru0r8e1vsatG8lsKVlGdkb/higU1p rLWn3fdUSMIAKBEj0Dor8kyUMJrBo9heL+SY2Gmdv4D+4Jun+FxMDe+/dwSJYhdN26wN6HJzgDO /6mFbllJq5W6K/w+tUsIsowGihhjHNoaMbQ3r+oLA+2HDJpMzy4HZtSt8UtVqkm+GgvjBvrok4r fY6XWvKZYL+0ERcC4ghwONpab+f4+TBQ6HkY60NCsi1+p4SnESHpbk4s3+0qM1MaKve6g2o6CzH 3DJezZcdpXAJMQz9PUEPm60SVn9vr2asEfxcVpsQPSzgFyUtAN+4OAzPFwVY7+X50GNoiLC/OIK f7ojymDVPpY/ZHgkrnh2DdkE0S1TxlLLOBlbJ6pcgFHJS1vhwhlZZIjlH5SjfdQRRaG1ZPQluu8 T08fHJXBHUeFhCN4icA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_02,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 adultscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310059 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=nnmlinux@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1788161001839154100 Content-Type: text/plain; charset="utf-8" Advertise the supported ibm,errinjct token types to the guest through the "ibm,errinjct-tokens" property under the RTAS node in the device tree. The property blob is built directly from a QEMU-side static table. No host /proc/device-tree/rtas/ibm,errinjct-tokens probing is done QEMU presents the same token set regardless of the host platform, which avoids host-specific dependencies. Each entry in the blob is a NUL-terminated token name string followed by a big-endian uint32 type value, matching the PAPR specification for ibm,errinjct-tokens. "ibm,open-errinjct" and "ibm,close-errinjct" string properties are also added to advertise the session-management calls. Signed-off-by: Narayana Murty N --- hw/ppc/spapr.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 20e024907b..4c5b06d03d 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -116,6 +116,8 @@ =20 #define PHANDLE_INTC 0x00001111 =20 +#define ERRINJCT_BLOB_MAX 512 + /* These two functions implement the VCPU id numbering: one to compute them * all and one to identify thread 0 of a VCORE. Any change to the first one * is likely to have an impact on the second one, so let's keep them close. @@ -1081,6 +1083,65 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, = void *fdt) */ _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); =20 + /* + * Advertise supported ibm,errinjct token types to the guest via the + * "ibm,errinjct-tokens" RTAS FDT property. The blob is built locally + * from the QEMU-side token table; no /proc/device-tree probing is don= e. + * Each entry is: NUL-terminated name string || big-endian uint32 type. + */ + { + static const struct { + const char *name; + uint32_t type; + } tok_table[] =3D { + { "recovered-special-event", + RTAS_ERR_TYPE_RECOVERED_SPECIAL_EVENT }, + { "corrupted-page", RTAS_ERR_TYPE_CORRUPTED_PAGE = }, + { "ioa-bus-error", RTAS_ERR_TYPE_IOA_BUS_ERROR = }, + { "corrupted-dcache-start", + RTAS_ERR_TYPE_CORRUPTED_DCACHE_START }, + { "corrupted-dcache-end", + RTAS_ERR_TYPE_CORRUPTED_DCACHE_END }, + { "corrupted-icache-start", + RTAS_ERR_TYPE_CORRUPTED_ICACHE_START }, + { "corrupted-icache-end", + RTAS_ERR_TYPE_CORRUPTED_ICACHE_END }, + { "corrupted-tlb-start", + RTAS_ERR_TYPE_CORRUPTED_TLB_START }, + { "corrupted-tlb-end", RTAS_ERR_TYPE_CORRUPTED_TLB_END = }, + { "ioa-bus-error-64", RTAS_ERR_TYPE_IOA_BUS_ERROR_64 = }, + }; + g_autofree char *errinject_tokens =3D NULL; + uint8_t blob[ERRINJCT_BLOB_MAX]; + size_t blen =3D 0; + bool ok =3D true; + + for (int i =3D 0; i < G_N_ELEMENTS(tok_table) && ok; i++) { + size_t slen =3D strlen(tok_table[i].name) + 1; + uint32_t be_type; + + if (blen + slen + sizeof(be_type) > ERRINJCT_BLOB_MAX) { + ok =3D false; + break; + } + memcpy(blob + blen, tok_table[i].name, slen); + blen +=3D slen; + be_type =3D cpu_to_be32(tok_table[i].type); + memcpy(blob + blen, &be_type, sizeof(be_type)); + blen +=3D sizeof(be_type); + } + + if (ok) { + errinject_tokens =3D g_memdup2(blob, blen); + _FDT(fdt_setprop(fdt, rtas, "ibm,errinjct-tokens", + errinject_tokens, blen)); + _FDT(fdt_setprop_string(fdt, rtas, "ibm,open-errinjct", + "ibm,open-errinjct")); + _FDT(fdt_setprop_string(fdt, rtas, "ibm,close-errinjct", + "ibm,close-errinjct")); + } + } + _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", lrdr_capacity, sizeof(lrdr_capacity))); =20 --=20 2.54.0 From nobody Sat Sep 26 20:50:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=nnmlinux@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1788161014890158500 Content-Type: text/plain; charset="utf-8" Move all EEH and error-injection functions from spapr_pci_vfio.c into a dedicated hw/ppc/spapr_eeh.c. spapr_eeh.c is compiled only when CONFIG_VFIO_PCI is enabled; spapr_pci_vfio.c is retained as a stub-only file compiled on Linux when CONFIG_VFIO_PCI is not available, providing the non-functional fallback implementations needed for Linux/pseries builds that do not include VFIO PCI. meson.build: replace the single spapr_pci_vfio.c entry with an if_true/if_false pair keyed on CONFIG_VFIO_PCI: CONFIG_VFIO_PCI=3Dy -> spapr_eeh.c (real implementation) CONFIG_VFIO_PCI=3Dn -> spapr_pci_vfio.c (stubs) No functional change to the EEH state machine. Reviewed-by: Pierrick Bouvier Signed-off-by: Narayana Murty N --- hw/ppc/meson.build | 6 +- hw/ppc/spapr_eeh.c | 572 +++++++++++++++++++++++++++++++++++++++ hw/ppc/spapr_pci_vfio.c | 573 +--------------------------------------- 3 files changed, 583 insertions(+), 568 deletions(-) create mode 100644 hw/ppc/spapr_eeh.c diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index 37aa535db2..cd3a8ab904 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -34,9 +34,9 @@ ppc_ss.add(when: ['CONFIG_PSERIES', 'CONFIG_TCG'], if_tru= e: files( )) ppc_ss.add(when: 'CONFIG_SPAPR_RNG', if_true: files('spapr_rng.c')) if host_os =3D=3D 'linux' - ppc_ss.add(when: 'CONFIG_PSERIES', if_true: files( - 'spapr_pci_vfio.c', - )) + ppc_ss.add(when: ['CONFIG_PSERIES', 'CONFIG_VFIO_PCI'], + if_true: files('spapr_eeh.c'), + if_false: files('spapr_pci_vfio.c')) endif =20 # IBM PowerNV diff --git a/hw/ppc/spapr_eeh.c b/hw/ppc/spapr_eeh.c new file mode 100644 index 0000000000..92b947cfd1 --- /dev/null +++ b/hw/ppc/spapr_eeh.c @@ -0,0 +1,572 @@ +/* + * QEMU sPAPR EEH (Enhanced Error Handling) support + * + * Copyright (c) 2011-2014 Alexey Kardashevskiy, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include +#include +#include "hw/ppc/spapr.h" +#include "hw/pci-host/spapr.h" +#include "hw/pci/msix.h" +#include "hw/pci/pci_device.h" +#include "hw/vfio/vfio-container-legacy.h" +#include "qemu/error-report.h" +#include "hw/vfio/pci.h" + +/* + * Interfaces for IBM EEH (Enhanced Error Handling) + * Compiled only when CONFIG_VFIO_PCI is enabled (build system guard). + * No #include CONFIG_DEVICES is required here. + */ + +static bool vfio_eeh_container_ok(VFIOLegacyContainer *container) +{ + /* + * As of 2016-03-04 (linux-4.5) the host kernel EEH/VFIO + * implementation is broken if there are multiple groups in a + * container. The hardware works in units of Partitionable + * Endpoints (=3D=3D IOMMU groups) and the EEH operations naively + * iterate across all groups in the container, without any logic + * to make sure the groups have their state synchronized. For + * certain operations (ENABLE) that might be ok, until an error + * occurs, but for others (GET_STATE) it's clearly broken. + */ + + /* + * XXX Once fixed kernels exist, test for them here + */ + + if (QLIST_EMPTY(&container->group_list)) { + return false; + } + + if (QLIST_NEXT(QLIST_FIRST(&container->group_list), container_next)) { + return false; + } + + return true; +} + +static int vfio_eeh_container_op(VFIOLegacyContainer *container, uint32_t = op) +{ + struct vfio_eeh_pe_op pe_op =3D { + .argsz =3D sizeof(pe_op), + .op =3D op, + }; + int ret; + + if (!vfio_eeh_container_ok(container)) { + error_report("vfio/eeh: EEH_PE_OP 0x%x: " + "kernel requires a container with exactly one group",= op); + return -EPERM; + } + + ret =3D ioctl(container->fd, VFIO_EEH_PE_OP, &pe_op); + if (ret < 0) { + error_report("vfio/eeh: EEH_PE_OP 0x%x failed: %m", op); + return -errno; + } + + return ret; +} + +static VFIOLegacyContainer *vfio_eeh_as_container(AddressSpace *as) +{ + VFIOAddressSpace *space =3D vfio_address_space_get(as); + VFIOContainer *bcontainer =3D NULL; + + if (QLIST_EMPTY(&space->containers)) { + /* No containers to act on */ + goto out; + } + + bcontainer =3D QLIST_FIRST(&space->containers); + + if (QLIST_NEXT(bcontainer, next)) { + /* + * We don't yet have logic to synchronize EEH state across + * multiple containers + */ + bcontainer =3D NULL; + goto out; + } + +out: + vfio_address_space_put(space); + return VFIO_IOMMU_LEGACY(bcontainer); +} + +static bool vfio_eeh_as_ok(AddressSpace *as) +{ + VFIOLegacyContainer *container =3D vfio_eeh_as_container(as); + + return (container !=3D NULL) && vfio_eeh_container_ok(container); +} + +static int vfio_eeh_as_op(AddressSpace *as, uint32_t op) +{ + VFIOLegacyContainer *container =3D vfio_eeh_as_container(as); + + if (!container) { + return -ENODEV; + } + return vfio_eeh_container_op(container, op); +} + +bool spapr_phb_eeh_available(SpaprPhbState *sphb) +{ + return vfio_eeh_as_ok(&sphb->iommu_as); +} + +static void spapr_phb_vfio_eeh_reenable(SpaprPhbState *sphb) +{ + vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_ENABLE); +} + +void spapr_phb_vfio_reset(DeviceState *qdev) +{ + /* + * The PE might be in frozen state. To reenable the EEH + * functionality on it will clean the frozen state, which + * ensures that the contained PCI devices will work properly + * after reboot. + */ + spapr_phb_vfio_eeh_reenable(SPAPR_PCI_HOST_BRIDGE(qdev)); +} + +static void spapr_eeh_pci_find_device(PCIBus *bus, PCIDevice *pdev, + void *opaque) +{ + bool *found =3D opaque; + + if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { + *found =3D true; + } +} + +int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, + unsigned int addr, int option) +{ + uint32_t op; + int ret; + + switch (option) { + case RTAS_EEH_DISABLE: + op =3D VFIO_EEH_PE_DISABLE; + break; + case RTAS_EEH_ENABLE: { + PCIHostState *phb; + bool found =3D false; + + /* + * The EEH functionality is enabled per sphb level instead of + * per PCI device. We have already identified this specific sphb + * based on buid passed as argument to ibm,set-eeh-option rtas + * call. Now we just need to check the validity of the PCI + * pass-through devices (vfio-pci) under this sphb bus. + * We have already validated that all the devices under this sphb + * are from same iommu group (within same PE) before coming here. + * + * Prior to linux commit 98ba956f6a389 ("powerpc/pseries/eeh: + * Rework device EEH PE determination") kernel would call + * eeh-set-option for each device in the PE using the device's + * config_address as the argument rather than the PE address. + * Hence if we check validity of supplied config_addr whether + * it matches to this PHB will cause issues with older kernel + * versions v5.9 and older. If we return an error from + * eeh-set-option when the argument isn't a valid PE address + * then older kernels (v5.9 and older) will interpret that as + * EEH not being supported. + */ + phb =3D PCI_HOST_BRIDGE(sphb); + pci_for_each_device(phb->bus, (addr >> 16) & 0xFF, + spapr_eeh_pci_find_device, &found); + + if (!found) { + return RTAS_OUT_PARAM_ERROR; + } + + op =3D VFIO_EEH_PE_ENABLE; + break; + } + case RTAS_EEH_THAW_IO: + op =3D VFIO_EEH_PE_UNFREEZE_IO; + break; + case RTAS_EEH_THAW_DMA: + op =3D VFIO_EEH_PE_UNFREEZE_DMA; + break; + default: + return RTAS_OUT_PARAM_ERROR; + } + + ret =3D vfio_eeh_as_op(&sphb->iommu_as, op); + if (ret < 0) { + return RTAS_OUT_HW_ERROR; + } + + return RTAS_OUT_SUCCESS; +} + +int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state) +{ + int ret; + + ret =3D vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_GET_STATE); + if (ret < 0) { + return RTAS_OUT_PARAM_ERROR; + } + + *state =3D ret; + return RTAS_OUT_SUCCESS; +} + +static void spapr_phb_vfio_eeh_clear_dev_msix(PCIBus *bus, + PCIDevice *pdev, + void *opaque) +{ + /* Check if the device is VFIO PCI device */ + if (!object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { + return; + } + + /* + * The MSIx table will be cleaned out by reset. We need + * disable it so that it can be reenabled properly. Also, + * the cached MSIx table should be cleared as it's not + * reflecting the contents in hardware. + */ + if (msix_enabled(pdev)) { + uint16_t flags; + + flags =3D pci_host_config_read_common(pdev, + pdev->msix_cap + PCI_MSIX_FLAG= S, + pci_config_size(pdev), 2); + flags &=3D ~PCI_MSIX_FLAGS_ENABLE; + pci_host_config_write_common(pdev, + pdev->msix_cap + PCI_MSIX_FLAGS, + pci_config_size(pdev), flags, 2); + } + + msix_reset(pdev); +} + +static void spapr_phb_vfio_eeh_clear_bus_msix(PCIBus *bus, void *opaque) +{ + pci_for_each_device_under_bus(bus, spapr_phb_vfio_eeh_clear_dev_msi= x, + NULL); +} + +static void spapr_phb_vfio_eeh_pre_reset(SpaprPhbState *sphb) +{ + PCIHostState *phb =3D PCI_HOST_BRIDGE(sphb); + + pci_for_each_bus(phb->bus, spapr_phb_vfio_eeh_clear_bus_msix, NULL); +} + +int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option) +{ + uint32_t op; + int ret; + + switch (option) { + case RTAS_SLOT_RESET_DEACTIVATE: + op =3D VFIO_EEH_PE_RESET_DEACTIVATE; + break; + case RTAS_SLOT_RESET_HOT: + spapr_phb_vfio_eeh_pre_reset(sphb); + op =3D VFIO_EEH_PE_RESET_HOT; + break; + case RTAS_SLOT_RESET_FUNDAMENTAL: + spapr_phb_vfio_eeh_pre_reset(sphb); + op =3D VFIO_EEH_PE_RESET_FUNDAMENTAL; + break; + default: + return RTAS_OUT_PARAM_ERROR; + } + + ret =3D vfio_eeh_as_op(&sphb->iommu_as, op); + if (ret < 0) { + return RTAS_OUT_HW_ERROR; + } + + return RTAS_OUT_SUCCESS; +} + +int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) +{ + int ret; + + ret =3D vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_CONFIGURE); + if (ret < 0) { + return RTAS_OUT_PARAM_ERROR; + } + + return RTAS_OUT_SUCCESS; +} + +typedef struct SpaprVFIOErrinjctBarMatch { + uint64_t guest_addr; + + PCIDevice *pdev; + VFIOPCIDevice *vdev; + int bar; + + uint64_t guest_bar_start; + uint64_t bar_size; + uint64_t offset; +} SpaprVFIOErrinjctBarMatch; + +static VFIOPCIDevice *spapr_vfio_errinjct_pci_to_vfio(PCIDevice *pdev) +{ + if (!object_dynamic_cast(OBJECT(pdev), TYPE_VFIO_PCI)) { + return NULL; + } + + return container_of(pdev, VFIOPCIDevice, parent_obj); +} + +static void spapr_vfio_errinjct_find_bar_cb(PCIBus *bus, + PCIDevice *pdev, + void *opaque) +{ + SpaprVFIOErrinjctBarMatch *ctx =3D opaque; + VFIOPCIDevice *vdev; + int bar; + + if (ctx->pdev) { + return; + } + + vdev =3D spapr_vfio_errinjct_pci_to_vfio(pdev); + if (!vdev) { + return; + } + + for (bar =3D 0; bar < PCI_STD_NUM_BARS; bar++) { + pcibus_t guest_bar_start; + uint64_t bar_size; + uint64_t offset; + + bar_size =3D vdev->bars[bar].region.size; + if (!bar_size) { + continue; + } + + guest_bar_start =3D pci_get_bar_addr(pdev, bar); + if (guest_bar_start =3D=3D PCI_BAR_UNMAPPED) { + continue; + } + + if (ctx->guest_addr < guest_bar_start || + ctx->guest_addr - guest_bar_start >=3D bar_size) { + if (vdev->bars[bar].mem64) { + bar++; + } + continue; + } + + offset =3D ctx->guest_addr - guest_bar_start; + + ctx->pdev =3D pdev; + ctx->vdev =3D vdev; + ctx->bar =3D bar; + ctx->guest_bar_start =3D guest_bar_start; + ctx->bar_size =3D bar_size; + ctx->offset =3D offset; + + return; + } +} + +static int spapr_vfio_errinjct_get_host_bar(VFIOPCIDevice *vdev, + int bar, + uint64_t *host_bar_start) +{ + g_autofree char *path =3D NULL; + g_autofree char *contents =3D NULL; + char *line; + char *saveptr =3D NULL; + unsigned long long start; + unsigned long long end; + unsigned long long flags; + int i; + + if (!vdev || !host_bar_start || bar < 0 || bar >=3D PCI_STD_NUM_BARS) { + return -EINVAL; + } + + /* + * Read the host Linux sysfs resource file for the BAR. Do not use a + * VFIO PCI config-space read because that may return the + * guest-programmed BAR value rather than the host resource address. + */ + path =3D g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%u/resou= rce", + vdev->host.domain, + vdev->host.bus, + vdev->host.slot, + vdev->host.function); + + if (!g_file_get_contents(path, &contents, NULL, NULL)) { + error_report("vfio/eeh errinjct: failed to read %s", path); + return -ENOENT; + } + + line =3D strtok_r(contents, "\n", &saveptr); + + for (i =3D 0; line; i++, line =3D strtok_r(NULL, "\n", &saveptr)) { + if (i !=3D bar) { + continue; + } + + if (sscanf(line, "%llx %llx %llx", &start, &end, &flags) !=3D 3) { + error_report("vfio/eeh errinjct: malformed %s BAR%d", + path, bar); + return -EINVAL; + } + + if (!start || end < start) { + error_report("vfio/eeh errinjct: invalid host resource BAR%d " + "start=3D0x%llx end=3D0x%llx flags=3D0x%llx", + bar, start, end, flags); + return -EINVAL; + } + + *host_bar_start =3D start; + return 0; + } + + return -EINVAL; +} + +int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, + uint32_t config_addr, + uint64_t guest_addr, + uint64_t *host_pci_bus_addr) +{ + PCIHostState *phb; + SpaprVFIOErrinjctBarMatch ctx =3D { + .guest_addr =3D guest_addr, + .pdev =3D NULL, + .vdev =3D NULL, + .bar =3D -1, + }; + uint64_t host_bar_start; + int rc; + + if (!sphb || !host_pci_bus_addr) { + return -EINVAL; + } + + phb =3D PCI_HOST_BRIDGE(sphb); + + /* + * BUID has already selected @sphb before this helper is called. + * config_addr is retained for logging/debug only. Do not rely on it + * to find the target device; some RTAS IOA buffers may not carry a + * valid guest BDF-style config address. Scan VFIO BARs under this + * PHB and match guest_addr against the guest BAR layout instead. + */ + pci_for_each_device_under_bus(phb->bus, + spapr_vfio_errinjct_find_bar_cb, + &ctx); + + if (!ctx.pdev) { + error_report("vfio/eeh errinjct: guest addr 0x%" PRIx64 + " not within any VFIO BAR under BUID=3D0x%016" PRIx64 + " config_addr=3D0x%08x", + guest_addr, sphb->buid, config_addr); + return -ENODEV; + } + + rc =3D spapr_vfio_errinjct_get_host_bar(ctx.vdev, ctx.bar, &host_bar_s= tart); + if (rc) { + error_report("vfio/eeh errinjct: failed to get host BAR%d for " + "dev=3D%s BUID=3D0x%016" PRIx64 " config_addr=3D0x%08= x rc=3D%d", + ctx.bar, ctx.pdev->name, sphb->buid, config_addr, rc); + return rc; + } + + if (host_bar_start =3D=3D ctx.guest_bar_start) { + error_report("vfio/eeh errinjct: refusing guest BAR as host BAR: " + "dev=3D%s BAR%d guest_bar=3D0x%" PRIx64 + " host_bar=3D0x%" PRIx64, + ctx.pdev->name, ctx.bar, + ctx.guest_bar_start, host_bar_start); + return -EOPNOTSUPP; + } + + *host_pci_bus_addr =3D host_bar_start + ctx.offset; + return 0; +} + +static int spapr_vfio_errinjct_rtas_type_to_vfio(uint32_t rtas_type) +{ + switch (rtas_type) { + case RTAS_ERR_TYPE_IOA_BUS_ERROR: + return EEH_ERR_TYPE_32; + case RTAS_ERR_TYPE_IOA_BUS_ERROR_64: + return EEH_ERR_TYPE_64; + default: + return -1; + } +} + +static bool spapr_vfio_errinjct_func_valid(uint32_t func) +{ + return func <=3D EEH_ERR_FUNC_MAX; +} + +int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, + uint32_t func, uint64_t addr, uint64_t mask) +{ + VFIOLegacyContainer *container; + struct vfio_eeh_pe_op op =3D { + .op =3D VFIO_EEH_PE_INJECT_ERR, + .argsz =3D sizeof(op), + }; + int vfio_type; + + if (!sphb) { + return RTAS_OUT_PARAM_ERROR; + } + + if (!spapr_vfio_errinjct_func_valid(func)) { + return RTAS_OUT_PARAM_ERROR; + } + + vfio_type =3D spapr_vfio_errinjct_rtas_type_to_vfio(type); + if (vfio_type < 0) { + return RTAS_OUT_NOT_SUPPORTED; + } + + container =3D vfio_eeh_as_container(&sphb->iommu_as); + if (!container) { + error_report("vfio/eeh errinjct: no VFIO EEH container for PHB"); + return RTAS_OUT_NOT_SUPPORTED; + } + + op.err.type =3D vfio_type; + op.err.func =3D func; + op.err.addr =3D addr; + op.err.mask =3D mask; + + if (ioctl(container->fd, VFIO_EEH_PE_OP, &op) < 0) { + error_report("vfio/eeh errinjct: VFIO_EEH_PE_OP failed: %s", + strerror(errno)); + switch (errno) { + case EINVAL: + return RTAS_OUT_PARAM_ERROR; + case ENOTTY: + case EOPNOTSUPP: + return RTAS_OUT_NOT_SUPPORTED; + default: + return RTAS_OUT_HW_ERROR; + } + } + + return RTAS_OUT_SUCCESS; +} diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c index 2f428531cc..b3acf5388d 100644 --- a/hw/ppc/spapr_pci_vfio.c +++ b/hw/ppc/spapr_pci_vfio.c @@ -1,5 +1,5 @@ /* - * QEMU sPAPR PCI host for VFIO + * QEMU sPAPR PCI host for VFIO - non-EEH stubs * * Copyright (c) 2011-2014 Alexey Kardashevskiy, IBM Corporation. * @@ -17,571 +17,16 @@ * along with this program; if not, see . */ =20 -#include "qemu/osdep.h" -#include -#include -#include "hw/ppc/spapr.h" -#include "hw/pci-host/spapr.h" -#include "hw/pci/msix.h" -#include "hw/pci/pci_device.h" -#include "hw/vfio/vfio-container-legacy.h" -#include "qemu/error-report.h" -#include "hw/vfio/pci.h" -#include CONFIG_DEVICES /* CONFIG_VFIO_PCI */ - /* - * Interfaces for IBM EEH (Enhanced Error Handling) + * This file provides stub implementations of the sPAPR EEH/errinjct + * functions for Linux builds where CONFIG_VFIO_PCI is not enabled. + * The real implementations live in spapr_eeh.c, which is compiled + * only when CONFIG_VFIO_PCI is enabled. */ -#ifdef CONFIG_VFIO_PCI -static bool vfio_eeh_container_ok(VFIOLegacyContainer *container) -{ - /* - * As of 2016-03-04 (linux-4.5) the host kernel EEH/VFIO - * implementation is broken if there are multiple groups in a - * container. The hardware works in units of Partitionable - * Endpoints (=3D=3D IOMMU groups) and the EEH operations naively - * iterate across all groups in the container, without any logic - * to make sure the groups have their state synchronized. For - * certain operations (ENABLE) that might be ok, until an error - * occurs, but for others (GET_STATE) it's clearly broken. - */ - - /* - * XXX Once fixed kernels exist, test for them here - */ - - if (QLIST_EMPTY(&container->group_list)) { - return false; - } - - if (QLIST_NEXT(QLIST_FIRST(&container->group_list), container_next)) { - return false; - } - - return true; -} - -static int vfio_eeh_container_op(VFIOLegacyContainer *container, uint32_t = op) -{ - struct vfio_eeh_pe_op pe_op =3D { - .argsz =3D sizeof(pe_op), - .op =3D op, - }; - int ret; - - if (!vfio_eeh_container_ok(container)) { - error_report("vfio/eeh: EEH_PE_OP 0x%x: " - "kernel requires a container with exactly one group",= op); - return -EPERM; - } - - ret =3D ioctl(container->fd, VFIO_EEH_PE_OP, &pe_op); - if (ret < 0) { - error_report("vfio/eeh: EEH_PE_OP 0x%x failed: %m", op); - return -errno; - } - - return ret; -} - -static VFIOLegacyContainer *vfio_eeh_as_container(AddressSpace *as) -{ - VFIOAddressSpace *space =3D vfio_address_space_get(as); - VFIOContainer *bcontainer =3D NULL; - - if (QLIST_EMPTY(&space->containers)) { - /* No containers to act on */ - goto out; - } - - bcontainer =3D QLIST_FIRST(&space->containers); - - if (QLIST_NEXT(bcontainer, next)) { - /* - * We don't yet have logic to synchronize EEH state across - * multiple containers - */ - bcontainer =3D NULL; - goto out; - } - -out: - vfio_address_space_put(space); - return VFIO_IOMMU_LEGACY(bcontainer); -} - -static bool vfio_eeh_as_ok(AddressSpace *as) -{ - VFIOLegacyContainer *container =3D vfio_eeh_as_container(as); - - return (container !=3D NULL) && vfio_eeh_container_ok(container); -} - -static int vfio_eeh_as_op(AddressSpace *as, uint32_t op) -{ - VFIOLegacyContainer *container =3D vfio_eeh_as_container(as); - - if (!container) { - return -ENODEV; - } - return vfio_eeh_container_op(container, op); -} - -bool spapr_phb_eeh_available(SpaprPhbState *sphb) -{ - return vfio_eeh_as_ok(&sphb->iommu_as); -} - -static void spapr_phb_vfio_eeh_reenable(SpaprPhbState *sphb) -{ - vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_ENABLE); -} - -void spapr_phb_vfio_reset(DeviceState *qdev) -{ - /* - * The PE might be in frozen state. To reenable the EEH - * functionality on it will clean the frozen state, which - * ensures that the contained PCI devices will work properly - * after reboot. - */ - spapr_phb_vfio_eeh_reenable(SPAPR_PCI_HOST_BRIDGE(qdev)); -} - -static void spapr_eeh_pci_find_device(PCIBus *bus, PCIDevice *pdev, - void *opaque) -{ - bool *found =3D opaque; - - if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { - *found =3D true; - } -} - -int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, - unsigned int addr, int option) -{ - uint32_t op; - int ret; - - switch (option) { - case RTAS_EEH_DISABLE: - op =3D VFIO_EEH_PE_DISABLE; - break; - case RTAS_EEH_ENABLE: { - PCIHostState *phb; - bool found =3D false; - - /* - * The EEH functionality is enabled per sphb level instead of - * per PCI device. We have already identified this specific sphb - * based on buid passed as argument to ibm,set-eeh-option rtas - * call. Now we just need to check the validity of the PCI - * pass-through devices (vfio-pci) under this sphb bus. - * We have already validated that all the devices under this sphb - * are from same iommu group (within same PE) before coming here. - * - * Prior to linux commit 98ba956f6a389 ("powerpc/pseries/eeh: - * Rework device EEH PE determination") kernel would call - * eeh-set-option for each device in the PE using the device's - * config_address as the argument rather than the PE address. - * Hence if we check validity of supplied config_addr whether - * it matches to this PHB will cause issues with older kernel - * versions v5.9 and older. If we return an error from - * eeh-set-option when the argument isn't a valid PE address - * then older kernels (v5.9 and older) will interpret that as - * EEH not being supported. - */ - phb =3D PCI_HOST_BRIDGE(sphb); - pci_for_each_device(phb->bus, (addr >> 16) & 0xFF, - spapr_eeh_pci_find_device, &found); - - if (!found) { - return RTAS_OUT_PARAM_ERROR; - } - - op =3D VFIO_EEH_PE_ENABLE; - break; - } - case RTAS_EEH_THAW_IO: - op =3D VFIO_EEH_PE_UNFREEZE_IO; - break; - case RTAS_EEH_THAW_DMA: - op =3D VFIO_EEH_PE_UNFREEZE_DMA; - break; - default: - return RTAS_OUT_PARAM_ERROR; - } - - ret =3D vfio_eeh_as_op(&sphb->iommu_as, op); - if (ret < 0) { - return RTAS_OUT_HW_ERROR; - } - - return RTAS_OUT_SUCCESS; -} - -int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state) -{ - int ret; - - ret =3D vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_GET_STATE); - if (ret < 0) { - return RTAS_OUT_PARAM_ERROR; - } - - *state =3D ret; - return RTAS_OUT_SUCCESS; -} - -static void spapr_phb_vfio_eeh_clear_dev_msix(PCIBus *bus, - PCIDevice *pdev, - void *opaque) -{ - /* Check if the device is VFIO PCI device */ - if (!object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { - return; - } - - /* - * The MSIx table will be cleaned out by reset. We need - * disable it so that it can be reenabled properly. Also, - * the cached MSIx table should be cleared as it's not - * reflecting the contents in hardware. - */ - if (msix_enabled(pdev)) { - uint16_t flags; - - flags =3D pci_host_config_read_common(pdev, - pdev->msix_cap + PCI_MSIX_FLAG= S, - pci_config_size(pdev), 2); - flags &=3D ~PCI_MSIX_FLAGS_ENABLE; - pci_host_config_write_common(pdev, - pdev->msix_cap + PCI_MSIX_FLAGS, - pci_config_size(pdev), flags, 2); - } - - msix_reset(pdev); -} - -static void spapr_phb_vfio_eeh_clear_bus_msix(PCIBus *bus, void *opaque) -{ - pci_for_each_device_under_bus(bus, spapr_phb_vfio_eeh_clear_dev_msi= x, - NULL); -} - -static void spapr_phb_vfio_eeh_pre_reset(SpaprPhbState *sphb) -{ - PCIHostState *phb =3D PCI_HOST_BRIDGE(sphb); - - pci_for_each_bus(phb->bus, spapr_phb_vfio_eeh_clear_bus_msix, NULL); -} - -int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option) -{ - uint32_t op; - int ret; - - switch (option) { - case RTAS_SLOT_RESET_DEACTIVATE: - op =3D VFIO_EEH_PE_RESET_DEACTIVATE; - break; - case RTAS_SLOT_RESET_HOT: - spapr_phb_vfio_eeh_pre_reset(sphb); - op =3D VFIO_EEH_PE_RESET_HOT; - break; - case RTAS_SLOT_RESET_FUNDAMENTAL: - spapr_phb_vfio_eeh_pre_reset(sphb); - op =3D VFIO_EEH_PE_RESET_FUNDAMENTAL; - break; - default: - return RTAS_OUT_PARAM_ERROR; - } - - ret =3D vfio_eeh_as_op(&sphb->iommu_as, op); - if (ret < 0) { - return RTAS_OUT_HW_ERROR; - } - - return RTAS_OUT_SUCCESS; -} - -int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) -{ - int ret; - - ret =3D vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_CONFIGURE); - if (ret < 0) { - return RTAS_OUT_PARAM_ERROR; - } - - return RTAS_OUT_SUCCESS; -} - -typedef struct SpaprVFIOErrinjctBarMatch { - uint64_t guest_addr; - - PCIDevice *pdev; - VFIOPCIDevice *vdev; - int bar; - - uint64_t guest_bar_start; - uint64_t bar_size; - uint64_t offset; -} SpaprVFIOErrinjctBarMatch; - -static VFIOPCIDevice *spapr_vfio_errinjct_pci_to_vfio(PCIDevice *pdev) -{ - if (!object_dynamic_cast(OBJECT(pdev), TYPE_VFIO_PCI)) { - return NULL; - } - - return container_of(pdev, VFIOPCIDevice, parent_obj); -} - -static void spapr_vfio_errinjct_find_bar_cb(PCIBus *bus, - PCIDevice *pdev, - void *opaque) -{ - SpaprVFIOErrinjctBarMatch *ctx =3D opaque; - VFIOPCIDevice *vdev; - int bar; - - if (ctx->pdev) { - return; - } - - vdev =3D spapr_vfio_errinjct_pci_to_vfio(pdev); - if (!vdev) { - return; - } - - for (bar =3D 0; bar < PCI_STD_NUM_BARS; bar++) { - pcibus_t guest_bar_start; - uint64_t bar_size; - uint64_t offset; - - bar_size =3D vdev->bars[bar].region.size; - if (!bar_size) { - continue; - } - - guest_bar_start =3D pci_get_bar_addr(pdev, bar); - if (guest_bar_start =3D=3D PCI_BAR_UNMAPPED) { - continue; - } - - if (ctx->guest_addr < guest_bar_start || - ctx->guest_addr - guest_bar_start >=3D bar_size) { - if (vdev->bars[bar].mem64) { - bar++; - } - continue; - } - - offset =3D ctx->guest_addr - guest_bar_start; - - ctx->pdev =3D pdev; - ctx->vdev =3D vdev; - ctx->bar =3D bar; - ctx->guest_bar_start =3D guest_bar_start; - ctx->bar_size =3D bar_size; - ctx->offset =3D offset; - - return; - } -} - -static int spapr_vfio_errinjct_get_host_bar(VFIOPCIDevice *vdev, - int bar, - uint64_t *host_bar_start) -{ - g_autofree char *path =3D NULL; - g_autofree char *contents =3D NULL; - char *line; - char *saveptr =3D NULL; - unsigned long long start; - unsigned long long end; - unsigned long long flags; - int i; - - if (!vdev || !host_bar_start || bar < 0 || bar >=3D PCI_STD_NUM_BARS) { - return -EINVAL; - } - - /* - * Read the host Linux sysfs resource file for the BAR. Do not use a - * VFIO PCI config-space read because that may return the - * guest-programmed BAR value rather than the host resource address. - */ - path =3D g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%u/resou= rce", - vdev->host.domain, - vdev->host.bus, - vdev->host.slot, - vdev->host.function); - - if (!g_file_get_contents(path, &contents, NULL, NULL)) { - error_report("vfio/eeh errinjct: failed to read %s", path); - return -ENOENT; - } - - line =3D strtok_r(contents, "\n", &saveptr); - - for (i =3D 0; line; i++, line =3D strtok_r(NULL, "\n", &saveptr)) { - if (i !=3D bar) { - continue; - } - - if (sscanf(line, "%llx %llx %llx", &start, &end, &flags) !=3D 3) { - error_report("vfio/eeh errinjct: malformed %s BAR%d", - path, bar); - return -EINVAL; - } - - if (!start || end < start) { - error_report("vfio/eeh errinjct: invalid host resource BAR%d " - "start=3D0x%llx end=3D0x%llx flags=3D0x%llx", - bar, start, end, flags); - return -EINVAL; - } =20 - *host_bar_start =3D start; - return 0; - } - - return -EINVAL; -} - -int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState *sphb, - uint32_t config_addr, - uint64_t guest_addr, - uint64_t *host_pci_bus_addr) -{ - PCIHostState *phb; - SpaprVFIOErrinjctBarMatch ctx =3D { - .guest_addr =3D guest_addr, - .pdev =3D NULL, - .vdev =3D NULL, - .bar =3D -1, - }; - uint64_t host_bar_start; - int rc; - - if (!sphb || !host_pci_bus_addr) { - return -EINVAL; - } - - phb =3D PCI_HOST_BRIDGE(sphb); - - /* - * BUID has already selected @sphb before this helper is called. - * config_addr is retained for logging/debug only. Do not rely on it - * to find the target device; some RTAS IOA buffers may not carry a - * valid guest BDF-style config address. Scan VFIO BARs under this - * PHB and match guest_addr against the guest BAR layout instead. - */ - pci_for_each_device_under_bus(phb->bus, - spapr_vfio_errinjct_find_bar_cb, - &ctx); - - if (!ctx.pdev) { - error_report("vfio/eeh errinjct: guest addr 0x%" PRIx64 - " not within any VFIO BAR under BUID=3D0x%016" PRIx64 - " config_addr=3D0x%08x", - guest_addr, sphb->buid, config_addr); - return -ENODEV; - } - - rc =3D spapr_vfio_errinjct_get_host_bar(ctx.vdev, ctx.bar, &host_bar_s= tart); - if (rc) { - error_report("vfio/eeh errinjct: failed to get host BAR%d for " - "dev=3D%s BUID=3D0x%016" PRIx64 " config_addr=3D0x%08= x rc=3D%d", - ctx.bar, ctx.pdev->name, sphb->buid, config_addr, rc); - return rc; - } - - if (host_bar_start =3D=3D ctx.guest_bar_start) { - error_report("vfio/eeh errinjct: refusing guest BAR as host BAR: " - "dev=3D%s BAR%d guest_bar=3D0x%" PRIx64 - " host_bar=3D0x%" PRIx64, - ctx.pdev->name, ctx.bar, - ctx.guest_bar_start, host_bar_start); - return -EOPNOTSUPP; - } - - *host_pci_bus_addr =3D host_bar_start + ctx.offset; - return 0; -} - -static int spapr_vfio_errinjct_rtas_type_to_vfio(uint32_t rtas_type) -{ - switch (rtas_type) { - case RTAS_ERR_TYPE_IOA_BUS_ERROR: - return EEH_ERR_TYPE_32; - case RTAS_ERR_TYPE_IOA_BUS_ERROR_64: - return EEH_ERR_TYPE_64; - default: - return -1; - } -} - -static bool spapr_vfio_errinjct_func_valid(uint32_t func) -{ - return func <=3D EEH_ERR_FUNC_MAX; -} - -int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t type, - uint32_t func, uint64_t addr, uint64_t mask) -{ - VFIOLegacyContainer *container; - struct vfio_eeh_pe_op op =3D { - .op =3D VFIO_EEH_PE_INJECT_ERR, - .argsz =3D sizeof(op), - }; - int vfio_type; - - if (!sphb) { - return RTAS_OUT_PARAM_ERROR; - } - - if (!spapr_vfio_errinjct_func_valid(func)) { - return RTAS_OUT_PARAM_ERROR; - } - - vfio_type =3D spapr_vfio_errinjct_rtas_type_to_vfio(type); - if (vfio_type < 0) { - return RTAS_OUT_NOT_SUPPORTED; - } - - container =3D vfio_eeh_as_container(&sphb->iommu_as); - if (!container) { - error_report("vfio/eeh errinjct: no VFIO EEH container for PHB"); - return RTAS_OUT_NOT_SUPPORTED; - } - - op.err.type =3D vfio_type; - op.err.func =3D func; - op.err.addr =3D addr; - op.err.mask =3D mask; - - if (ioctl(container->fd, VFIO_EEH_PE_OP, &op) < 0) { - error_report("vfio/eeh errinjct: VFIO_EEH_PE_OP failed: %s", - strerror(errno)); - switch (errno) { - case EINVAL: - return RTAS_OUT_PARAM_ERROR; - case ENOTTY: - case EOPNOTSUPP: - return RTAS_OUT_NOT_SUPPORTED; - default: - return RTAS_OUT_HW_ERROR; - } - } - - return RTAS_OUT_SUCCESS; -} - -#else +#include "qemu/osdep.h" +#include "hw/ppc/spapr.h" +#include "hw/pci-host/spapr.h" =20 bool spapr_phb_eeh_available(SpaprPhbState *sphb) { @@ -626,5 +71,3 @@ int spapr_phb_vfio_translate_errinjct_addr(SpaprPhbState= *sphb, { return -ENOTSUP; } - -#endif /* CONFIG_VFIO_PCI */ --=20 2.54.0 From nobody Sat Sep 26 20:50:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 31 Aug 2026 07:22:50 +0000 (GMT) Received: from Narayanas-MacBook-Pro.bl1-in.ibm.com (unknown [9.123.3.199]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 31 Aug 2026 07:22:49 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=XJjAnixP4HBQQxpay xHuWnPscaiP4Q6HZXptSYnysDU=; b=r4B9tHSQmIJcHEJdrQ1XD480tVVS53zTA ZNXWi4eN9DK3z6ogJTSeGrojQm1EkSBOQuOp7RkcodrBtP80eY9At1YYpx8UhiUA ko/IbWuzM1kvLMdx4rTaWX1On3rrghR4MbtCxCzDMp5frPXRdqok7pntkjDwty5r YbtaZ1vFtaYcAVVJZ2NE7C9VPyaqE7g2A3kgS2aLYFWgYfyWuMyJThhNe/UIxky0 TZmQCyBUAZSeF+xsJpYfm3NhA3XhuCNpbXCnoHJGdoREi5gVV32NYdFGqPA1rn3Y PgZ6ohRnyThDV0tzhnDM1o00jMal9/iFbCRigqpc0kQLTGKuEOn4Q== From: Narayana Murty N To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, mahesh@linux.ibm.com, sbhat@linux.ibm.com, anushree.mathur@linux.vnet.ibm.com, clg@redhat.com, sourabhjain@linux.ibm.com, adityag@linux.ibm.com, nikhilks@linux.ibm.com Cc: pierrick.bouvier@oss.qualcomm.com, rathc@linux.ibm.com, npiggin@gmail.com, harshpb@linux.ibm.com, amachhiw@linux.ibm.com, hbathini@linux.ibm.com, shivangu@linux.ibm.com Subject: [PATCH v4 6/6] MAINTAINERS: Add self as sPAPR EEH reviewer under PPC RAS Date: Mon, 31 Aug 2026 12:49:58 +0530 Message-ID: <20260831071958.58824-7-nnmlinux@linux.ibm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260831071958.58824-1-nnmlinux@linux.ibm.com> References: <20260831071958.58824-1-nnmlinux@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=bc1bluPB c=1 sm=1 tr=0 ts=6a952bd4 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=69wJf7TsAAAA:8 a=uPrgHAJC8kndP_WudMUA:9 a=Fg1AiH1G6rFz08G2ETeA:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA1OSBTYWx0ZWRfX9voYtAp87Szm jTWuo8J8uulIZgGastTjUms6fBGZ0VzaSpBnkFL19W/0DmLYXUcTR2lTOCfXwwOPR0dnWoIg6k4 h1KVA+/dY+YsSPgBAD8eDpko5pqSdP8= X-Proofpoint-ORIG-GUID: KOQ55Vy81MP1h1dSE3RC-F7uzDhzdBL- X-Proofpoint-GUID: gY6gdkQ58foK2xR_UtFB8E4MvY1f8sBZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA1OSBTYWx0ZWRfX7DvBKjhIYhgL wJMfs2eH/ooFJCVVplJ538ptrAidGd99ffDdLw18ghz8mU6JK93WbXQH/K92/O4xuvR++RrS0yb nIDNk4Y07c27fLpuocUY7M9HiDzw8sZdF/SetXaaJRNJhi2L1iKn2MvIvpU0rKqb711G3vhWLVc 7VjgomwAi2XUKAED3sX7pIBg4rSy2S43grW+/c83LDqvEzOgbnNM25TMxkhc9NoTAg1KYABdbaL CazVRc/+Fmi+zraHDrzudoGC9o6M5MJLteqhVhjB3+2sF8IGcaySPaojUvozmbss4jOAq54Tqd6 wIGz6Hvf5ugTtVcmWuy4U479nmw4AWk7YExKvReeK1rneK7vBq/yaZ3M73I3qWzad6QGY+ux+gl HieYlryqOPrBP7E6qD2TEufyA8qzrApPGWJre8MhaWLEIz0/miABwCxtTt1qVoVb3yNBKVXZjCK WXnUawRxpB3jO958bmQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_02,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 adultscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310059 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=nnmlinux@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1788161028757158500 Content-Type: text/plain; charset="utf-8" Adding self as reviewer for the sPAPR EEH under PPC RAS. Updating the EEH specific file name as got updated in previous patches. Signed-off-by: Narayana Murty N --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4a49a40294..9271d849b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1770,11 +1770,12 @@ M: Aditya Gupta R: Sourabh Jain R: Hari Bathini R: Shivang Upadhyay +R: Narayana Murty N L: qemu-ppc@nongnu.org S: Maintained F: hw/ppc/spapr_events.c F: hw/ppc/spapr_fadump.c -F: hw/ppc/spapr_pci_vfio.c +F: hw/ppc/spapr_eeh.c F: hw/ppc/spapr_rtas.c F: hw/ppc/pnv_mpipl.c F: include/hw/ppc/spapr_fadump.h --=20 2.54.0