From nobody Sat Sep 26 21:35:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1787977270; cv=none; d=zohomail.com; s=zohoarc; b=jvzxVj1xzSLyjG5ee/FmCxXIbAAvqi8fqeFl/Vpp6BtsHm87E0PYvQ9zz4WBCse5wibIWxTWPzcPl2ViPmHYjhmdbLjBf/7CIHzAhI5oQy6CH0yJw8jY5kODunBI5rLtX9MDFaGmWFC+AbraQBsTZa8iBEKy3XD/G0Hs6rC/iMw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787977270; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7R5WDd0jmooDcW5HPp0cRFbEdNBKPJFny5PovUq6WAE=; b=ZDAO8027RBWSbmS3M9240apgQhsDNIXdAFCmNtl+1rOGnaNBh9ZlPS2KTvTFhMHCMVG8amMYZqBo2JzXGh/daiRagvrsWZ1NfV2+MLajllUn5b8Q+52PfetSGnkChz3pwJArdvRGPFCTWluesgLRbkhGJdjfNMIN7r+a8eddga8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178797727026383.62796036140435; Fri, 28 Aug 2026 21:21:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0AY7-0008Up-0a; Sat, 29 Aug 2026 00:20:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x08Rj-0004nQ-CC for qemu-devel@nongnu.org; Fri, 28 Aug 2026 22:05:27 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x08Rg-0007nF-Vx for qemu-devel@nongnu.org; Fri, 28 Aug 2026 22:05:27 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-2caced6038eso16916625ad.0 for ; Fri, 28 Aug 2026 19:05:24 -0700 (PDT) Received: from localhost.localdomain ([180.213.79.228]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d759869aeesm10592695ad.46.2026.08.28.19.05.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 19:05:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787969123; x=1788573923; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=7R5WDd0jmooDcW5HPp0cRFbEdNBKPJFny5PovUq6WAE=; b=fspzbclDtvbh2BJ/IKBhiIU3e3p1gvLYKQ13oSsZeAit6i+rfFtRrIJz0dsQK2Jxwh qw/GcyMH9R1+Z67inugn057qAlaBl6gwLDA38wau9hidLth3hmIWxNmZyDUP3Ty/BIw7 GzqiUiRcYkv+FGnoMMy1cvK6kpE4FJkA7oheNcVAPCIe4uaVrA1VZhLqbOJOpssh+RGx Y9uW36tq4OrLz4s8VTzXXd6hVSX32z5MdQNgrXHtZ62adVmdhxbp/52MzAhDLZQ1dSbj rX7V+a8clbwMi5ok/BxZ6xNc7J9xQtDCAdo7FrPYFiGvyWmfZtt0npedarRy/X46YAG6 odCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787969123; x=1788573923; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=7R5WDd0jmooDcW5HPp0cRFbEdNBKPJFny5PovUq6WAE=; b=JK3LW/o0i19UZZNUDK8NslnFwF30vWpgKy9e2cWTrTfKMAqvtrtkWPGc6zHyau9UN9 nZeLoKfwcCY9FG16rZma985j9D4zGfvUDeYw7eqCmy6z78qy5bbn26gv3SVpq8Q7Qqsw u1SKXTwPoGWxZ/c7vJGmBJS/eGlEC2aJN+EAcwnbgR6diNrT6bD3rwmf5AqTQ3icwXR5 Pjrj2d7JKql+GhK2VWafzAKTAYF5e1w2xedbjUbB0tvARv5ZYb+fVYuSoOk9bjpOlScS yobDkOPl0wvWrXuBWA2nAxw6qVLRL2tj4IXAh1jmyBJ9j81MAHoVMmLK3DAPvSLR6Th8 2RBg== X-Gm-Message-State: AFuF++mskxmCMZ1csQSnwTvu12y91K/Ie6DKf3itfgZ8TNnSsWt3bBrn z/klvPNuKrgA+BPk5Bx5NYa92ipwR+QhBxKbz1E5KvNtYyuoUUUEv+OjMj7O0Tbz X-Gm-Gg: AYBFou0XrFmGF49MOsTzsH/nYTLvg3OisE+/tjWGRljIuuKtWdeKVVtLgu5+4ReZwjq t+wxakCEgnV7Ys42H3SVOBVEG5QxivXSLPt2z3oXAZRyicAZIjCIix3LdGnOvUuMxUYzFri/KR4 hFM3zgPA93dX01g04AlgH97GD27s9zuRd8W2eaPyValGKx3INrqsMdbqjVv5g3ZAhDxD1R4iq1Z 0hj8GUWP6GkDAUq4Zl7MHE/3K3xl9bkzyAgZOxAeZf3EcvbqxYBtWu7G0LBYrEsiYJKJPjG9hLj 3WJdV3E/Mb8LPeGX1kyxqrSzG2sLUUdfY/WNpb6q0S80wCfnghOlkNazqDHVLbg62V74kPaHVEo bmgSA7XQDBLYxHhh4vRs/kFYuCwm0gR6Aw1nUhciQ3IXpSq5bX8YtEu60TB2ZTT/4S6QZSRX/y0 0S+2n99UHbdtnAilujBOgs5GNrUcDNAK84gSTi5oovrASTheidZ/AvGptYZHNCFmvZ2QjF68Veq Xb+1RpU X-Received: by 2002:a17:903:2ec5:b0:2d6:fddf:a890 with SMTP id d9443c01a7336-2d72634612dmr244738765ad.6.1787969123178; Fri, 28 Aug 2026 19:05:23 -0700 (PDT) From: JunWei Li To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, chenhuacai@canaan-creative.com, JunWei Li Subject: [PATCH 1/3] hw/misc: add K230 PMU device Date: Sat, 29 Aug 2026 10:02:27 +0800 Message-Id: <20260829020229.389742-2-vae1207@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20260829020229.389742-1-vae1207@gmail.com> References: <20260829020229.389742-1-vae1207@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=vae1207@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sat, 29 Aug 2026 00:20:10 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787977271880158500 Content-Type: text/plain; charset="utf-8" Add a model of the K230 power management unit with the APB register bank, i= nterrupt detection state and the two PMIC output pads, based on the K230 Te= chnical Reference Manual V0.3.1 chapter 14. The PMU registers keep their reset values and write masks from the TRM. PAD= 64..PAD69 inputs set the matching PMU_INT_STATE bit when the corresponding = detection is enabled, and the interrupt line follows PMU_INT_STATE & PMU_IN= T0_TO_CPU. Writing PMU_SYSCTRL_REG drives the PAD70/PAD71 outputs. Long/sho= rt press timing, edge counting and debounce are not modelled yet. Signed-off-by: JunWei Li --- MAINTAINERS | 3 + hw/misc/Kconfig | 3 + hw/misc/k230_pmu.c | 242 +++++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + include/hw/misc/k230_pmu.h | 71 +++++++++++ 5 files changed, 320 insertions(+) create mode 100644 hw/misc/k230_pmu.c create mode 100644 include/hw/misc/k230_pmu.h diff --git a/MAINTAINERS b/MAINTAINERS index 6171cc7494..49c165f71e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1824,10 +1824,13 @@ M: Chao Liu L: qemu-riscv@nongnu.org S: Maintained F: docs/system/riscv/k230.rst +F: hw/misc/k230_pmu.c F: hw/riscv/k230.c F: hw/watchdog/k230_wdt.c +F: include/hw/misc/k230_pmu.h F: include/hw/riscv/k230.h F: include/hw/watchdog/k230_wdt.h +F: tests/qtest/k230-pmu-test.c F: tests/qtest/k230-wdt-test.c =20 RX Machines diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 1543ee6653..98a2ab3709 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -135,6 +135,9 @@ config RISCV_MIPS_CPC config RISCV_MIPS_CPS bool =20 +config K230_PMU + bool + config MPS2_FPGAIO bool select LED diff --git a/hw/misc/k230_pmu.c b/hw/misc/k230_pmu.c new file mode 100644 index 0000000000..14a955dbd1 --- /dev/null +++ b/hw/misc/k230_pmu.c @@ -0,0 +1,242 @@ +/* + * K230 PMU device + * + * Copyright (c) 2026 LiJunWei + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * K230 Technical Reference Manual V0.3.1 (2024-11-18): + * https://github.com/revyos/external-docs/blob/master/K230/en-us/K230_Tec= hnical_Reference_Manual_V0.3.1_20241118.pdf + * + * Minimal model of the PMU (TRM chapter 14): the APB register bank, + * the interrupt detection state and the two PMIC output pads. The + * long/short press timing, edge counting and debounce units are not + * modelled yet. + */ +#include "qemu/osdep.h" + +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/core/irq.h" +#include "hw/core/sysbus.h" +#include "hw/misc/k230_pmu.h" + +/* PMU_INT_DETECT_CLR bit i clears PMU_INT_STATE bit state_bit[i] */ +static const uint8_t state_bit[10] =3D { + [0] =3D 3, [1] =3D 4, [2] =3D 5, [3] =3D 6, [4] =3D 7, + [5] =3D 8, [6] =3D 9, [7] =3D 10, [8] =3D 0, [9] =3D 11, +}; + +/* + * PAD64..PAD69 edge/level detection. For these inputs the + * PMU_INT_DETECT_EN enable bit and the PMU_INT_STATE state bit + * coincide. + */ +static const uint8_t input_bit[K230_PMU_INPUTS] =3D { 9, 7, 6, 5, 4, 3 }; + +static void k230_pmu_update_irq(K230PmuState *s) +{ + qemu_set_irq(s->irq, + (s->regs[R_INT_STATE] & + s->regs[R_INT0_TO_CPU] & 0xfff) !=3D 0); +} + +static void k230_pmu_gpio_in(void *opaque, int n, int level) +{ + K230PmuState *s =3D opaque; + uint32_t bit =3D BIT(input_bit[n]); + + if (level && (s->regs[R_INT_DETECT_EN] & bit)) { + s->regs[R_INT_STATE] |=3D bit; + k230_pmu_update_irq(s); + } +} + +static uint64_t k230_pmu_read(void *opaque, hwaddr offset, unsigned size) +{ + K230PmuState *s =3D opaque; + + if (offset >=3D K230_PMU_REG_COUNT * 4) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", + TYPE_K230_PMU, offset); + return 0; + } + + return s->regs[offset / 4]; +} + +static void k230_pmu_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + K230PmuState *s =3D opaque; + uint32_t mask; + + if (offset >=3D K230_PMU_REG_COUNT * 4) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", + TYPE_K230_PMU, offset); + return; + } + + switch (offset / 4) { + case R_INT_DETECT_CLR: /* W1C */ + for (unsigned int i =3D 0; i < ARRAY_SIZE(state_bit); i++) { + if (value & BIT(i)) { + s->regs[R_INT_STATE] &=3D ~BIT(state_bit[i]); + } + } + k230_pmu_update_irq(s); + return; + case R_INT_STATE: /* RO */ + return; + case R_SYSCTRL: /* drives PAD70/71 */ + s->regs[R_SYSCTRL] =3D value & 0x3; + qemu_set_irq(s->pad[0], s->regs[R_SYSCTRL] & BIT(0)); + qemu_set_irq(s->pad[1], s->regs[R_SYSCTRL] & BIT(1)); + return; + case R_INT0_TO_CTL: + case R_INT1_TO_CTL: + case R_INT0_TO_CPU: + case R_INT_DETECT_EN: + case R_OUT_EVENT_CTRL: + mask =3D 0x1fff; /* [12:0] */ + break; + case R_INT_DETECT_TYP: + mask =3D 0x1fffff; /* [20:0] */ + break; + case R_LONG_PRESS_TRIGGER: + case R_LONG_PRESS_SHUTDOWN: + mask =3D 0xfffff; /* [19:0] */ + break; + case R_SHORT_PRESS_TRIGGER: + case R_NORMAL_TIMER_VAL: + mask =3D 0xffff; /* [15:0] */ + break; + case R_LEVEL_DEBOUNCE: + case R_INT1_LEVEL_DEBOUNCE: + case R_INT2_LEVEL_DEBOUNCE: + case R_INT3_LEVEL_DEBOUNCE: + mask =3D 0xfff; /* [11:0] */ + break; + case R_EDGE_NUMBER: + mask =3D 0x3ff; /* [9:0] */ + break; + case R_OUT_DELAY_SET: + mask =3D 0x3ffffff; /* [25:0] */ + break; + case R_IO_CFG0: + case R_IO_CFG0 + 1: + case R_IO_CFG0 + 2: + case R_IO_CFG0 + 3: + case R_IO_CFG0 + 4: + case R_IO_CFG0 + 5: + case R_IO_CFG6: + case R_IO_CFG7: + mask =3D 0x3def; /* [9] and [4] are reserved */ + break; + default: + mask =3D 0xffffffff; + break; + } + + s->regs[offset / 4] =3D (s->regs[offset / 4] & ~mask) | (value & mask); + k230_pmu_update_irq(s); +} + +static void k230_pmu_reset(Object *obj, ResetType type) +{ + K230PmuState *s =3D K230_PMU(obj); + + memset(s->regs, 0, sizeof(s->regs)); + s->regs[R_INT0_TO_CTL] =3D 0xfff; + s->regs[R_INT1_TO_CTL] =3D 0xfff; + s->regs[R_INT_DETECT_EN] =3D 0x810; + s->regs[R_LONG_PRESS_TRIGGER] =3D 0x17700; + s->regs[R_LONG_PRESS_SHUTDOWN] =3D 0x4e200; + s->regs[R_SHORT_PRESS_TRIGGER] =3D 0x3e800; + s->regs[R_LEVEL_DEBOUNCE] =3D 0x100; + s->regs[R_EDGE_NUMBER] =3D 0x1; + s->regs[R_INT1_LEVEL_DEBOUNCE] =3D 0x100; + s->regs[R_INT2_LEVEL_DEBOUNCE] =3D 0x100; + s->regs[R_INT3_LEVEL_DEBOUNCE] =3D 0x100; + s->regs[R_SYSCTRL] =3D 0x1; + s->regs[R_OUT_DELAY_SET] =3D 0x1100640; + for (unsigned int i =3D 0; i < 6; i++) { + s->regs[R_IO_CFG0 + i] =3D 0x1124; + } + s->regs[R_IO_CFG6] =3D 0x10a4; + s->regs[R_IO_CFG7] =3D 0x1084; + s->regs[R_NORMAL_TIMER_VAL] =3D 0x780; + s->regs[R_OUT_EVENT_CTRL] =3D 0x5c; + s->regs[R_OUT_LOGIC_CTRL] =3D 0x2; + + k230_pmu_update_irq(s); + qemu_set_irq(s->pad[0], s->regs[R_SYSCTRL] & BIT(0)); + qemu_set_irq(s->pad[1], s->regs[R_SYSCTRL] & BIT(1)); +} + +static const MemoryRegionOps k230_pmu_ops =3D { + .read =3D k230_pmu_read, + .write =3D k230_pmu_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static const VMStateDescription vmstate_k230_pmu =3D { + .name =3D TYPE_K230_PMU, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, K230PmuState, K230_PMU_REG_COUNT), + VMSTATE_END_OF_LIST() + }, +}; + +static void k230_pmu_init(Object *obj) +{ + K230PmuState *s =3D K230_PMU(obj); + + memory_region_init_io(&s->iomem, obj, &k230_pmu_ops, s, + TYPE_K230_PMU, K230_PMU_MMIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->pad[0]); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->pad[1]); + + qdev_init_gpio_in(DEVICE(obj), k230_pmu_gpio_in, K230_PMU_INPUTS); +} + +static void k230_pmu_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->desc =3D "K230 PMU"; + dc->vmsd =3D &vmstate_k230_pmu; + rc->phases.enter =3D k230_pmu_reset; +} + +static const TypeInfo k230_pmu_type_info =3D { + .name =3D TYPE_K230_PMU, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(K230PmuState), + .instance_init =3D k230_pmu_init, + .class_init =3D k230_pmu_class_init, +}; + +static void k230_pmu_register_types(void) +{ + type_register_static(&k230_pmu_type_info); +} + +type_init(k230_pmu_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 23265f6035..7eaff69081 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -28,6 +28,7 @@ system_ss.add(when: 'CONFIG_IOSB', if_true: files('iosb.c= ')) system_ss.add(when: 'CONFIG_VIRT_CTRL', if_true: files('virt_ctrl.c')) =20 # RISC-V devices +system_ss.add(when: 'CONFIG_K230_PMU', if_true: files('k230_pmu.c')) system_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dm= c.c')) system_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_= ioscb.c')) system_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc= _sysreg.c')) diff --git a/include/hw/misc/k230_pmu.h b/include/hw/misc/k230_pmu.h new file mode 100644 index 0000000000..48f5052f61 --- /dev/null +++ b/include/hw/misc/k230_pmu.h @@ -0,0 +1,71 @@ +/* + * K230 PMU device + * + * Copyright (c) 2026 LiJunWei + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MISC_K230_PMU_H +#define HW_MISC_K230_PMU_H + +#include "hw/core/registerfields.h" +#include "hw/core/sysbus.h" + +REG32(LOGGER, 0x000) +REG32(INT0_TO_CTL, 0x040) +REG32(INT1_TO_CTL, 0x044) +REG32(INT0_TO_CPU, 0x048) +REG32(INT_DETECT_EN, 0x04c) + FIELD(INT_DETECT_EN, INT1_EDGE_NUM_TICK_EN, 0, 1) + FIELD(INT_DETECT_EN, INT7_EN, 1, 1) + FIELD(INT_DETECT_EN, INT6_EN, 2, 1) + FIELD(INT_DETECT_EN, INT5_EDGE_LEVEL_EN, 3, 1) + FIELD(INT_DETECT_EN, INT4_EDGE_LEVEL_EN, 4, 1) + FIELD(INT_DETECT_EN, INT3_EDGE_LEVEL_EN, 5, 1) + FIELD(INT_DETECT_EN, INT2_EDGE_LEVEL_EN, 6, 1) + FIELD(INT_DETECT_EN, INT1_EDGE_LEVEL_EN, 7, 1) + FIELD(INT_DETECT_EN, INT1_EDGE_NUM_EN, 8, 1) + FIELD(INT_DETECT_EN, INT0_EDGE_LEVEL_EN, 9, 1) + FIELD(INT_DETECT_EN, INT0_SHORT_PRESS_EN, 10, 1) + FIELD(INT_DETECT_EN, INT0_LONG_PRESS_EN, 11, 1) + FIELD(INT_DETECT_EN, INT0_SHUTDOWN_PRESS_EN, 12, 1) +REG32(INT_DETECT_TYP, 0x050) +REG32(INT_DETECT_CLR, 0x054) +REG32(LONG_PRESS_TRIGGER, 0x058) +REG32(LONG_PRESS_SHUTDOWN, 0x05c) +REG32(SHORT_PRESS_TRIGGER, 0x060) +REG32(LEVEL_DEBOUNCE, 0x064) +REG32(EDGE_NUMBER, 0x068) +REG32(INT1_LEVEL_DEBOUNCE, 0x06c) +REG32(INT2_LEVEL_DEBOUNCE, 0x070) +REG32(INT3_LEVEL_DEBOUNCE, 0x074) +REG32(SYSCTRL, 0x078) +REG32(OUT_DELAY_SET, 0x07c) +REG32(IO_CFG0, 0x080) +REG32(IO_CFG6, 0x098) +REG32(IO_CFG7, 0x09c) +REG32(NORMAL_TIMER_VAL, 0x0a0) +REG32(OUT_EVENT_CTRL, 0x0a4) +REG32(OUT_LOGIC_CTRL, 0x0a8) +REG32(INT_STATE, 0x0ac) + +#define K230_PMU_MMIO_SIZE 0xc00 +#define K230_PMU_REG_COUNT (R_INT_STATE + 1) +#define K230_PMU_INPUTS 6 +#define K230_PMU_OUTPUTS 2 + +#define TYPE_K230_PMU "riscv.k230.pmu" +OBJECT_DECLARE_SIMPLE_TYPE(K230PmuState, K230_PMU) + +struct K230PmuState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + qemu_irq pad[K230_PMU_OUTPUTS]; + + uint32_t regs[K230_PMU_REG_COUNT]; +}; + +#endif /* HW_MISC_K230_PMU_H */ --=20 2.20.1 From nobody Sat Sep 26 21:35:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1787977254; cv=none; d=zohomail.com; s=zohoarc; b=Gg9+RkIScaaaPK2G0WmPcAr5gkkxjwMFhfBgtyfVuAB3UaNNghwEevq0CfS+ccwlh1ioHygoApKr1VB+By+OzvvjRuqA7zRoqtHreckFM74mjRl//NsOJZrvDH7kCn9JfNZvXpVtwzchOcY9UaajoFvIzQBCL0Sy+FuJZznYOCw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787977254; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OA4bHmPtn+iullfuGa/YjjBRxuLIb477GMmwLjWacJY=; b=fm6d688VzA4cuBWjA7MLQh5+CKpihsYb+9HzLjNURAsfpn6kwG3/HFQllSQrESBBf+6FbF0sJ6P2N95g/uKybQFp25ZkV7Lxx3e1IFFznwqM7FyT92P+h9bHAziT5hiU9NGVC1HOpnRwQqkKaBlRsPTTyX2gJ4NslRcKRBkk6t4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787977254470993.1359419910667; Fri, 28 Aug 2026 21:20:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0AY8-0008W2-Cz; Sat, 29 Aug 2026 00:20:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x08Rm-0004o8-Ki for qemu-devel@nongnu.org; Fri, 28 Aug 2026 22:05:30 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x08Rl-0007oA-0a for qemu-devel@nongnu.org; Fri, 28 Aug 2026 22:05:30 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-2caced6038eso16916785ad.0 for ; Fri, 28 Aug 2026 19:05:28 -0700 (PDT) Received: from localhost.localdomain ([180.213.79.228]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d759869aeesm10592695ad.46.2026.08.28.19.05.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 19:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787969127; x=1788573927; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=OA4bHmPtn+iullfuGa/YjjBRxuLIb477GMmwLjWacJY=; b=LniXM8cdudDs7UWINmqPuQkpyhnvnHiH1boQgJhT06n3YqHU/jD686zZIRTcHsKqKa nfGUiePoj5NZQ2LTULC8E5ViGcg9TelJIq+DeamP8bMLCOPjqu0jfxJBXN9ngMrVBl/P OmOCIimI9eaLOxFnTlpvpgOZqb8vE6wsdCP44w5dvssgZVhXiksUK5Bf/6jon6DqYCGt ++Db0WC9oTg8qp9F/lPZfMD1WHXXNiMvg4BCRLXLZiRN/DB0+PZyFutu7Y0q+Id+V9ax Ip/F6Muf5XGhLYVlBzvJJE+EVUI7ODlw0ZP8FY8hG3DhMfka1JTrGNxCJIBCa3mYkcdU 7LNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787969127; x=1788573927; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=OA4bHmPtn+iullfuGa/YjjBRxuLIb477GMmwLjWacJY=; b=EnZjaS34XKvUONEi4K/MIWysCHvJ2JVVqNK4iMbtdefFtVPCh8DCGmSpdyZkMkNWLv 7Sc0woWZuYRpdFV/O0dgK7tk9n+ZfqLdgb9DQJJajH0kkLCn5uLbrNyMCbQa5xEjGujn l6wis3vTAfx+uy4GJ7HWrhOnCt10FBAreSpw0YbDOPC4asYOCqyiQ3rFbQBngGYewrVv /1lPKiso5588y1jSXumDQ/7miDNXXYNZ8Rt/p0W5ItHlSo9samjrWkCMhAE5o36rycUG Cv6uU68zhqef2q6szm+ar7D99YHcumzw3Adfz0B3dLFUA2FuGXob5sOudfbRz5edd5/V ky9g== X-Gm-Message-State: AFuF++l0fho9lH1RrFKl5/3xZ0LH65c5g1v5XYOfWP42Qv51s/w3xDiV mGedTK158MBUmJrKJNUfNwXcvafSs/GWJjCcl6oPs2RzoXy185UYp1P4KCuIAdGM X-Gm-Gg: AYBFou2tZoMuXQBz+TR/IHGHQQbgR0gffmQlQMARED6p3IekPnb6Sl/L16dnhnJ2hbl ESXQ3T4UGERuS7y6DpgaX0ZJYLTN4KzDy3rkCqvFueqfxtmwBiie+Ku+1HpRdOs5w2s/xA78P3m fEyLYDQRZgURPJpTwvxjtgZ4YVJI31jQaoSxUIYIQ/use2J2nsPsSJk3IFwg5V/Z9SrI0sjvqRi ePCV73eaWYl8AeBq0E3VgxRGgDym93eLx+PJR4v/hEKpdOk/+4zbXqH2WkijFQvIAbXR2BCyPMx 2XfleI3vuRQxXILOfrRuZqYaZzGLyhjvst1KMl9ev1kiRVz1Ru3hRD8pr6pIejafS47Gf5wU7ow k5y4vHsDC30JGNunF77OeNcYL9/6QPJYzbd8PBpiDa0rnvhSadG4Dte77WOymuXk4sM69KFuGby Xo1Y6dTBzz2O3g9wKTuRgkmXN7U7wPF2yJrBE0jjo+pkrVA71OCeV7OYfnoNf1uve8/J7lgA== X-Received: by 2002:a17:903:2cf:b0:2d8:d4d2:d138 with SMTP id d9443c01a7336-2d8d4d2dd47mr35785725ad.20.1787969127292; Fri, 28 Aug 2026 19:05:27 -0700 (PDT) From: JunWei Li To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, chenhuacai@canaan-creative.com, JunWei Li Subject: [PATCH 2/3] hw/riscv: wire up K230 PMU in the SoC Date: Sat, 29 Aug 2026 10:02:28 +0800 Message-Id: <20260829020229.389742-3-vae1207@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20260829020229.389742-1-vae1207@gmail.com> References: <20260829020229.389742-1-vae1207@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=vae1207@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sat, 29 Aug 2026 00:20:10 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787977258311154100 Content-Type: text/plain; charset="utf-8" Instantiate the PMU device, map its MMIO region at 0x91000000 and connect i= ts interrupt line to the small-core PLIC source 81 (TRM 2.4 interrupt bit 6= 5 + 16). Replace the previous unimplemented PMU window. Signed-off-by: JunWei Li --- hw/riscv/Kconfig | 1 + hw/riscv/k230.c | 12 +++++++++--- include/hw/riscv/k230.h | 3 +++ 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index de37c08cae..0e61e6be3d 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -162,3 +162,4 @@ config K230 select SERIAL_MM select UNIMP select K230_WDT + select K230_PMU diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c index 656f28190c..906a5c1240 100644 --- a/hw/riscv/k230.c +++ b/hw/riscv/k230.c @@ -110,6 +110,7 @@ static void k230_soc_init(Object *obj) object_initialize_child(obj, "c908-cpu", cpu0, TYPE_RISCV_HART_ARRAY); object_initialize_child(obj, "k230-wdt0", &s->wdt[0], TYPE_K230_WDT); object_initialize_child(obj, "k230-wdt1", &s->wdt[1], TYPE_K230_WDT); + object_initialize_child(obj, "k230-pmu", &s->pmu, TYPE_K230_PMU); =20 qdev_prop_set_uint32(DEVICE(cpu0), "hartid-base", 0); qdev_prop_set_string(DEVICE(cpu0), "cpu-type", TYPE_RISCV_CPU_THEAD_C9= 08); @@ -191,6 +192,14 @@ static void k230_soc_realize(DeviceState *dev, Error *= *errp) k230_create_uart(sys_mem, DEVICE(s->c908_plic), i); } =20 + /* PMU */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pmu), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pmu), 0, memmap[K230_DEV_PMU].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmu), 0, + qdev_get_gpio_in(DEVICE(s->c908_plic), K230_PMU_IRQ= )); + /* Watchdog */ for (int i =3D 0; i < 2; i++) { if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { @@ -259,9 +268,6 @@ static void k230_soc_realize(DeviceState *dev, Error **= errp) create_unimplemented_device("3d-engine", memmap[K230_DEV_3D_ENGINE].ba= se, memmap[K230_DEV_3D_ENGINE].size); =20 - create_unimplemented_device("pmu", memmap[K230_DEV_PMU].base, - memmap[K230_DEV_PMU].size); - create_unimplemented_device("rtc", memmap[K230_DEV_RTC].base, memmap[K230_DEV_RTC].size); =20 diff --git a/include/hw/riscv/k230.h b/include/hw/riscv/k230.h index 592e1c26bf..5e4845a274 100644 --- a/include/hw/riscv/k230.h +++ b/include/hw/riscv/k230.h @@ -16,6 +16,7 @@ #define HW_K230_H =20 #include "hw/core/boards.h" +#include "hw/misc/k230_pmu.h" #include "hw/riscv/riscv_hart.h" #include "hw/watchdog/k230_wdt.h" =20 @@ -37,6 +38,7 @@ typedef struct K230SoCState { MemoryRegion bootrom; =20 DeviceState *c908_plic; + K230PmuState pmu; } K230SoCState; =20 #define TYPE_RISCV_K230_MACHINE MACHINE_TYPE_NAME("k230") @@ -127,6 +129,7 @@ enum { K230_UART2_IRQ =3D 18, K230_UART3_IRQ =3D 19, K230_UART4_IRQ =3D 20, + K230_PMU_IRQ =3D 81, K230_WDT0_IRQ =3D 107, K230_WDT1_IRQ =3D 108, }; --=20 2.20.1 From nobody Sat Sep 26 21:35:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1787977254; cv=none; d=zohomail.com; s=zohoarc; b=QLuW9IVtxAUTgPGIDBj7KuXcB9SNDFXmLBAR7dDd5eSwxwevOQ/QURnHwEdfe5vbwmWay1lVXkUI3qS+7X+qanw3h25NGrG8B/88HMn6lGKOccYzMCn4aRbxfpQEcpuFBAjqzOIjQkpikwhpoUkIESdpXZc0Y9TP2QA1zvMbO5c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787977254; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lt9h49RURpF5cpPX/SYI3haQspCU9BJRLrs+VVb4Avk=; b=KOXKVtexrHk3wVl7KMkrlActqn+jaukc3S0qEFaDaB9wErv+F+xccU+N53k3LP2x4gFxuit5Z9n5lpXCGmiUyi5eplu9MTiy8HCOU4aAiCDtPritz7uKZoQmNJ/hY+HvvdTioWdL6WwVZ3sH1wLabH0D3bwMvaWHNs9btudtb7s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178797725496557.35280448677054; Fri, 28 Aug 2026 21:20:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0AY7-0008VR-Fh; Sat, 29 Aug 2026 00:20:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x08Rs-0004ou-8G for qemu-devel@nongnu.org; Fri, 28 Aug 2026 22:05:38 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x08Ro-0007pH-UG for qemu-devel@nongnu.org; Fri, 28 Aug 2026 22:05:34 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-2d58efc7356so18747735ad.1 for ; Fri, 28 Aug 2026 19:05:32 -0700 (PDT) Received: from localhost.localdomain ([180.213.79.228]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d759869aeesm10592695ad.46.2026.08.28.19.05.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 19:05:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787969131; x=1788573931; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=lt9h49RURpF5cpPX/SYI3haQspCU9BJRLrs+VVb4Avk=; b=IF+fnZi7Xej6rRGAyf7nLi3Q5iOf+Xf+opr1PDrBQKQNVIduMrW2u487Wmz9TGB6+H qZlKiwTUQdrwSpPO+hIr+2obG9LOpooTg28tIgLTALzTeb11oW18/gIJOFWkY395PUAR CvhDUinO2/M4VMN1lxA1I/ziXPU3G1nusPEi0fFX09zszC7VZK/oDxn+6uLDokhjmWX6 LPgFYe4+E+zSaY7NTG/uKq9op/cwD94kQghFDeNIEIVJA+j5LkpDAAaPgWd6AjXA81fp lAnwrmw7aI45tiWtAQoT5YGLKxg79SEg00E5mqodqzdEA1bttnfIGCCqPsm54DhNiznu TRDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787969131; x=1788573931; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=lt9h49RURpF5cpPX/SYI3haQspCU9BJRLrs+VVb4Avk=; b=JAo6TV30qkTEx0HYzjbnBd6YR777MzfA44M6M95605TpoRFLo9eYlXx8FGz7qA5UPR FG4ZfINn4UAQls53V1HsPW/Kcuh0vhXKw/W90gDMUWJxV/lNZAaY3SE4WDXVrxpzeQr1 9HGuLDRx00gffsYtQc+0ngWSN9zU5FBCgXZMygmlb/LZL+zT7pCGDuDwBxDYl/S468zY Ss84+rihXSm7eLKgE+oJbUi45gf7Nsyaq0taBbzOtp2FxQG4IUWMRmW8PQLMuc0SSi3/ K8WzoOeGL/EoHWunrBmdeCZ7M5Jk9vbG2YuHSz8lU6z9IjB2nMfffvk53qLOpNUHZMHb QnWw== X-Gm-Message-State: AFuF++kMRH6augzuKX8L5H7EE84hss9ozCbPOYJws1K8Zj6IFcgQDT3N xXvafjXAmqNAjfmUVC/LGcFXmKK4ixrTqArT5J/txmnIa05PFZEBiI8C931lyZsH X-Gm-Gg: AYBFou1KuR8+GdJq8tB0Na8MuowGGL58S2i9En/RruzFKKIo1dFVpIMhCkIuDG6NOrQ yD2YBVyKHd0EwjFzaD0KaGwaUIV69hQIfJFXgKBCOSAe2jyuj9+OGdzzRUHYPG7wsIK8DCDXUd9 jQ3vPnpbe/Z3ZCY+/nuWaYg6w2LyBW0da4mS//zQAb1sn2cTzMkOr+KraDF0q4Ra8ykhsi+VSHE IuR92cUCTdsda56niNf8z9M1LvmDLESByjeTADYZjQ4MIqJHMm6OSVFjpScDSHtHjWtIcnPHFak geBXxMiu3jzR0NRczCOxTL0IFx03bmwQZgITIajBVpJXKf/YkHKkP322/kbpUH5vZL/VC4B1oCx WrADIKM0KBTIAi72I2bNni+HYonAjqCXGAn53SWpxWXWb6MQ4N5/qVZziFHkZz/gbC/qgUeX3c7 v9sClysvw/AcD4KKLt6zT9d6nSkwr0cim/FJ4u9Amb4L71WAJ5Nw/HnkM0AWee/ZYcxmXwrg== X-Received: by 2002:a17:902:cf4b:b0:2d7:71e:575d with SMTP id d9443c01a7336-2d74df04c8amr202211195ad.9.1787969131305; Fri, 28 Aug 2026 19:05:31 -0700 (PDT) From: JunWei Li To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, chenhuacai@canaan-creative.com, JunWei Li Subject: [PATCH 3/3] tests/qtest: add k230-pmu-test Date: Sat, 29 Aug 2026 10:02:29 +0800 Message-Id: <20260829020229.389742-4-vae1207@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20260829020229.389742-1-vae1207@gmail.com> References: <20260829020229.389742-1-vae1207@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=vae1207@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sat, 29 Aug 2026 00:20:10 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787977258590158500 Content-Type: text/plain; charset="utf-8" Add qtest coverage for the K230 PMU: register reset values, write masks, in= terrupt triggering and W1C clearing through the input pads, and PAD70/PAD71= output behaviour. Signed-off-by: JunWei Li --- tests/qtest/k230-pmu-test.c | 136 ++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 3 +- 2 files changed, 138 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/k230-pmu-test.c diff --git a/tests/qtest/k230-pmu-test.c b/tests/qtest/k230-pmu-test.c new file mode 100644 index 0000000000..9f24b18f19 --- /dev/null +++ b/tests/qtest/k230-pmu-test.c @@ -0,0 +1,136 @@ +/* + * QTest for the K230 PMU Unit. + * + * Copyright (c) 2026 LiJunWei + * SPDX-License-Identifier: GPL-2.0-or-later + * + * K230 Technical Reference Manual V0.3.1 (2024-11-18): + * https://github.com/revyos/external-docs/blob/master/K230/en-us/K230_Tec= hnical_Reference_Manual_V0.3.1_20241118.pdf + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "hw/misc/k230_pmu.h" + +#define PMU_BASE 0x91000000 + +static void test_reset_values(void) +{ + QTestState *qts =3D qtest_init("-machine k230"); + + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT0_TO_CTL * 4), =3D=3D, + 0xfff); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT1_TO_CTL * 4), =3D=3D, + 0xfff); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT0_TO_CPU * 4), =3D=3D= , 0); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_DETECT_EN * 4), =3D= =3D, + 0x810); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_DETECT_TYP * 4), =3D= =3D, 0); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_DETECT_CLR * 4), =3D= =3D, 0); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_LONG_PRESS_TRIGGER * 4), + =3D=3D, 0x17700); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_LONG_PRESS_SHUTDOWN * 4), + =3D=3D, 0x4e200); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_SHORT_PRESS_TRIGGER * 4), + =3D=3D, 0x3e800); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_LEVEL_DEBOUNCE * 4), =3D= =3D, + 0x100); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_EDGE_NUMBER * 4), =3D=3D= , 0x1); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_SYSCTRL * 4), =3D=3D, 0x= 1); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_OUT_DELAY_SET * 4), =3D= =3D, + 0x1100640); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_IO_CFG0 * 4), =3D=3D, 0x= 1124); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_IO_CFG6 * 4), =3D=3D, 0x= 10a4); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_IO_CFG7 * 4), =3D=3D, 0x= 1084); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_NORMAL_TIMER_VAL * 4), = =3D=3D, + 0x780); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_OUT_EVENT_CTRL * 4), =3D= =3D, + 0x5c); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_OUT_LOGIC_CTRL * 4), =3D= =3D, + 0x2); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_STATE * 4), =3D=3D, = 0); + + qtest_quit(qts); +} + +static void test_write_masks(void) +{ + QTestState *qts =3D qtest_init("-machine k230"); + + /* Reserved bits are write-ignored and read as zero. */ + qtest_writel(qts, PMU_BASE + R_INT_DETECT_EN * 4, 0xffffffff); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_DETECT_EN * 4), =3D= =3D, + 0x1fff); + qtest_writel(qts, PMU_BASE + R_INT_DETECT_TYP * 4, 0xffffffff); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_DETECT_TYP * 4), =3D= =3D, + 0x1fffff); + qtest_writel(qts, PMU_BASE + R_IO_CFG0 * 4, 0xffffffff); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_IO_CFG0 * 4), =3D=3D, 0x= 3def); + qtest_writel(qts, PMU_BASE + R_SYSCTRL * 4, 0xffffffff); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_SYSCTRL * 4), =3D=3D, 0x= 3); + + /* PMU_INT_STATE_REG is read-only. */ + qtest_writel(qts, PMU_BASE + R_INT_STATE * 4, 0xffffffff); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_STATE * 4), =3D=3D, = 0); + + qtest_quit(qts); +} + +static void test_interrupt_clear(void) +{ + QTestState *qts =3D qtest_init("-machine k230"); + + qtest_irq_intercept_out_named(qts, "/machine/soc/k230-pmu", + "sysbus-irq"); + + /* + * PAD68 (input 4) edge/level detection is enabled by default + * (PMU_INT_DETECT_EN bit 4). Raise the input and gate the + * corresponding interrupt through PMU_INT0_TO_CPU. + */ + qtest_writel(qts, PMU_BASE + R_INT0_TO_CPU * 4, BIT(4)); + qtest_set_irq_in(qts, "/machine/soc/k230-pmu", NULL, 4, 1); + + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_STATE * 4) & BIT(4), + =3D=3D, BIT(4)); + g_assert_cmpuint(qtest_get_irq(qts, 0), =3D=3D, 1); + + /* CLR bit 1 clears the int4 edge/level state (W1C). */ + qtest_writel(qts, PMU_BASE + R_INT_DETECT_CLR * 4, BIT(1)); + g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_STATE * 4) & BIT(4), + =3D=3D, 0); + g_assert_cmpuint(qtest_get_irq(qts, 0), =3D=3D, 0); + + qtest_quit(qts); +} + +static void test_pad_outputs(void) +{ + QTestState *qts =3D qtest_init("-machine k230"); + + qtest_irq_intercept_out_named(qts, "/machine/soc/k230-pmu", + "sysbus-irq"); + + /* PAD70/PAD71 follow the PMU_SYSCTRL_REG to_ctrl bits. */ + qtest_writel(qts, PMU_BASE + R_SYSCTRL * 4, 0x0); + g_assert_cmpuint(qtest_get_irq(qts, 1), =3D=3D, 0); + g_assert_cmpuint(qtest_get_irq(qts, 2), =3D=3D, 0); + + qtest_writel(qts, PMU_BASE + R_SYSCTRL * 4, 0x3); + g_assert_cmpuint(qtest_get_irq(qts, 1), =3D=3D, 1); + g_assert_cmpuint(qtest_get_irq(qts, 2), =3D=3D, 1); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/k230/pmu/reset-values", test_reset_values); + qtest_add_func("/k230/pmu/write-masks", test_write_masks); + qtest_add_func("/k230/pmu/interrupt-clear", test_interrupt_clear); + qtest_add_func("/k230/pmu/pad-outputs", test_pad_outputs); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 56ff860e21..daa5b6a284 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -297,7 +297,8 @@ qtests_riscv64 =3D ['riscv-csr-test'] + \ (config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') and config_all_devices.has_key('CONFIG_RISCV_IOMMU') ? ['iommu-riscv-test'] : []) + \ - (config_all_devices.has_key('CONFIG_K230') ? ['k230-wdt-test'] : []) + (config_all_devices.has_key('CONFIG_K230') ? + ['k230-wdt-test', 'k230-pmu-test'] : []) =20 qtests_hexagon =3D ['boot-serial-test'] =20 --=20 2.20.1