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[71.212.39.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-398a2f5187fsm427594a91.1.2026.08.28.15.44.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 15:44:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787957095; x=1788561895; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=XwNZK85bMoLoLObkEGMhYdQROE/xOCTLBXQLC6qU6n4=; b=VsQSZUk2e7letJZFa8Q4GTx9GtO/1yUtwWVeMqXvHV0gY/XjvXEiOU5/BQCjHZbeNM +v+yntF73lb5v3zgaiff91EdUI3AFLo0sgcCPrfhbkxry3WcyREWRrAo3Gmm/tgduyTw p6qHZUkYtffePhPmhLG2eIkPRNrOh2FTwP/+9q6yL39uzyDG6aVQdKxd4iVRuWtnVmGz bzrZJmd2n8AN86BT7fiaPyzfj23szpdRK+dZD5Va9UDoOHIDUw5ETLLooHvpxdJicZUh SW0JUeMKOw8WEyuHuUTJbbqvvF4MAnUpefBa0BeC+WKWWHfONHjj4HZMrnL2qQFPFfLO iCRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787957095; x=1788561895; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=XwNZK85bMoLoLObkEGMhYdQROE/xOCTLBXQLC6qU6n4=; b=ZVGC2pjuIDIlbEd7IZ2zaMVXgCxio1ZSJ7Ig0wyDwWBEmOLN9SZ5AT4O7HtnUSP//r 5d1eOKt+EgNQl0pwA6cQotTBqh+Zer1MLgGcn+ScJg66rCXe/5fWBQIebMevf5L5vRgI KYzV5hsZNgN0dLIGYEIh5BczcIWdWJH+GTYTVugcQ8v6tCqrxKxGh8kcsZHrYPtSAy3u nbAFjMDjw6bv7og08MR19LJHytpC98tu4Eqormqskpo0y0EOmCBqlgg+Q7BUvpnon86I McOut4o5E9rVg9hVfV81iUE5XDvdwjyDvWgDvOhDrClYb9Q+t8Gi/wz3+iGvozvIc6/t 8tYA== X-Gm-Message-State: AFuF++k4Qm7MvHduCWGL91ZkrUvIQmL9dg7xBS+QiS2ydwcFY4GkD091 dza7OGyayNq/DTiIMoh2CMmanqZP1KnI4KQo/J0NJSn0keJNOBC71/invr/f4yZw57ZuuFGc2Qx vj+rUfhA= X-Gm-Gg: AYBFou2fMUu15vmLKjCGDDGVrSajLshGFPboWQRzW6wMAXxlUFSlEhyB5VglzpOhlQN CMsojWqdKYlKklRQBQnGY58c1AGhNbXCkPfZ3yZ4L9aKVG/qBSbYXq5yf5yYw1EYOv2WaG89oRx S3tbbrQaySFPqvRaWVNtRvsqifa7W66gHLGJAhZ+4M0r+4RGtXIdfmpHpt6iKRYkDNPzkXb4nlN vamTrS+ci3IK6KrejV303dSfv4VBrNo4YaXv9IcW8RovsGHIsvAV/8XBCQKQDJEcfNyS2Y74Qba DRsq0p7dJhfUlFX/jxr3WBm3fx408J5bU7RYpYFT8ax4VE5T+P/EO346LSZMsKvEViKom9cQUCj hMY8rM08VAegYCoC8J0mOyMcwedQQ+3Ohk1Qd+kHLpe5Xck5Ga4ZYZl/mlYSw8i+xKk30PguPeg 0xucECiFgB+lyQUCmmHqTWTEdzSqr/jn/59ynJN24pGcoHa6oDA38+O03t/61shD5lnjUi+surK TM2hc0OQgArldDHVcKs X-Received: by 2002:a17:90b:3fcf:b0:398:9be5:b419 with SMTP id 98e67ed59e1d1-3989be5b4camr4575825a91.20.1787957094495; Fri, 28 Aug 2026 15:44:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 01/16] tcg: Sort all_outop[] by INDEX name Date: Fri, 28 Aug 2026 15:44:36 -0700 Message-ID: <20260828224451.1564072-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957181970154100 Content-Type: text/plain; charset="utf-8" Most of the opcodes were already sorted, but then there were a set at the bottom that were left over from the split between 32 and 64-bit hosts. Signed-off-by: Richard Henderson Reviewed-by: Matt Turner Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 489df0e7386..ecc1f54c1bf 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1158,32 +1158,39 @@ static const TCGOutOpLoad outop_ld =3D { /* Register allocation descriptions for every TCGOpcode. */ static const TCGOutOp * const all_outop[NB_OPS] =3D { OUTOP(INDEX_op_add, TCGOutOpBinary, outop_add), + /* addc1o is implemented with set_carry + addcio */ + OUTOP(INDEX_op_addc1o, TCGOutOpBinary, outop_addcio), OUTOP(INDEX_op_addci, TCGOutOpAddSubCarry, outop_addci), OUTOP(INDEX_op_addcio, TCGOutOpBinary, outop_addcio), OUTOP(INDEX_op_addco, TCGOutOpBinary, outop_addco), - /* addc1o is implemented with set_carry + addcio */ - OUTOP(INDEX_op_addc1o, TCGOutOpBinary, outop_addcio), OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and), OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc), OUTOP(INDEX_op_brcond, TCGOutOpBrcond, outop_brcond), OUTOP(INDEX_op_bswap16, TCGOutOpBswap, outop_bswap16), OUTOP(INDEX_op_bswap32, TCGOutOpBswap, outop_bswap32), + OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64), OUTOP(INDEX_op_clz, TCGOutOpBinary, outop_clz), OUTOP(INDEX_op_ctpop, TCGOutOpUnary, outop_ctpop), OUTOP(INDEX_op_ctz, TCGOutOpBinary, outop_ctz), OUTOP(INDEX_op_deposit, TCGOutOpDeposit, outop_deposit), OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs), - OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu), OUTOP(INDEX_op_divs2, TCGOutOpDivRem, outop_divs2), + OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu), OUTOP(INDEX_op_divu2, TCGOutOpDivRem, outop_divu2), OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv), OUTOP(INDEX_op_extract, TCGOutOpExtract, outop_extract), OUTOP(INDEX_op_extract2, TCGOutOpExtract2, outop_extract2), - OUTOP(INDEX_op_ld8u, TCGOutOpLoad, outop_ld8u), - OUTOP(INDEX_op_ld8s, TCGOutOpLoad, outop_ld8s), - OUTOP(INDEX_op_ld16u, TCGOutOpLoad, outop_ld16u), - OUTOP(INDEX_op_ld16s, TCGOutOpLoad, outop_ld16s), + OUTOP(INDEX_op_ext_i32_i64, TCGOutOpUnary, outop_exts_i32_i64), + OUTOP(INDEX_op_extrh_i64_i32, TCGOutOpUnary, outop_extrh_i64_i32), + OUTOP(INDEX_op_extrl_i64_i32, TCGOutOpUnary, outop_extrl_i64_i32), + OUTOP(INDEX_op_extu_i32_i64, TCGOutOpUnary, outop_extu_i32_i64), OUTOP(INDEX_op_ld, TCGOutOpLoad, outop_ld), + OUTOP(INDEX_op_ld8s, TCGOutOpLoad, outop_ld8s), + OUTOP(INDEX_op_ld8u, TCGOutOpLoad, outop_ld8u), + OUTOP(INDEX_op_ld16s, TCGOutOpLoad, outop_ld16s), + OUTOP(INDEX_op_ld16u, TCGOutOpLoad, outop_ld16u), + OUTOP(INDEX_op_ld32s, TCGOutOpLoad, outop_ld32s), + OUTOP(INDEX_op_ld32u, TCGOutOpLoad, outop_ld32u), OUTOP(INDEX_op_movcond, TCGOutOpMovcond, outop_movcond), OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul), OUTOP(INDEX_op_muls2, TCGOutOpMul2, outop_muls2), @@ -1203,7 +1210,9 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D { OUTOP(INDEX_op_qemu_st2, TCGOutOpQemuLdSt2, outop_qemu_st2), OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems), OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu), + OUTOP(INDEX_op_revbit8, TCGOutOpUnary, outop_revbit8), OUTOP(INDEX_op_revbit32, TCGOutOpBswap, outop_revbit32), + OUTOP(INDEX_op_revbit64, TCGOutOpUnary, outop_revbit64), OUTOP(INDEX_op_rotl, TCGOutOpBinary, outop_rotl), OUTOP(INDEX_op_rotr, TCGOutOpBinary, outop_rotr), OUTOP(INDEX_op_sar, TCGOutOpBinary, outop_sar), @@ -1216,28 +1225,18 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D= { OUTOP(INDEX_op_st, TCGOutOpStore, outop_st), OUTOP(INDEX_op_st8, TCGOutOpStore, outop_st8), OUTOP(INDEX_op_st16, TCGOutOpStore, outop_st16), + OUTOP(INDEX_op_st32, TCGOutOpStore, outop_st), OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub), + /* subb1o is implemented with set_borrow + subbio */ + OUTOP(INDEX_op_subb1o, TCGOutOpAddSubCarry, outop_subbio), OUTOP(INDEX_op_subbi, TCGOutOpAddSubCarry, outop_subbi), OUTOP(INDEX_op_subbio, TCGOutOpAddSubCarry, outop_subbio), OUTOP(INDEX_op_subbo, TCGOutOpAddSubCarry, outop_subbo), - /* subb1o is implemented with set_borrow + subbio */ - OUTOP(INDEX_op_subb1o, TCGOutOpAddSubCarry, outop_subbio), OUTOP(INDEX_op_umax, TCGOutOpBinary, outop_umax), OUTOP(INDEX_op_umin, TCGOutOpBinary, outop_umin), OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor), =20 [INDEX_op_goto_ptr] =3D &outop_goto_ptr, - - OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64), - OUTOP(INDEX_op_ext_i32_i64, TCGOutOpUnary, outop_exts_i32_i64), - OUTOP(INDEX_op_extu_i32_i64, TCGOutOpUnary, outop_extu_i32_i64), - OUTOP(INDEX_op_extrl_i64_i32, TCGOutOpUnary, outop_extrl_i64_i32), - OUTOP(INDEX_op_extrh_i64_i32, TCGOutOpUnary, outop_extrh_i64_i32), - OUTOP(INDEX_op_ld32u, TCGOutOpLoad, outop_ld32u), - OUTOP(INDEX_op_ld32s, TCGOutOpLoad, outop_ld32s), - OUTOP(INDEX_op_revbit8, TCGOutOpUnary, outop_revbit8), - OUTOP(INDEX_op_revbit64, TCGOutOpUnary, outop_revbit64), - OUTOP(INDEX_op_st32, TCGOutOpStore, outop_st), }; =20 #undef OUTOP --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787957180; cv=none; d=zohomail.com; s=zohoarc; b=f7WchNiWTGkw1JlhJ/3QY7nKYFQXo2d4mtd4vCgiflO6bjSNFck+vHRskxqskI3TDReZzkGZqJ8/ls9Dpjm7hBv7nd22nVxXl2L8fd0dKEqkAzkGKFQxrKi67ZZo+ddr2DEtOgl3rljttCEbB4eSj0GKDTBfUHLr22RLWACpYWY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787957180; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZIRC0JScoH9896L1OJzf3rQzLn6ug+3UA6NiOF3ZVbI=; b=lb1ZIn3fRsKfO/7BMuUb68h7NGoilkE8FNLiZ1FN4eiY1fMc9Rd3koinn0LUwk35U+JdklCRDsYlqgoWCZ12bfOrS4LE7mMazrD+nKZIJql+bEFseQoEnXJS3RIbBCuKZhnAC4OigpiuZ5RCjbaO8/Hd93jiwqq1lUrbqGerwPQ= ARC-Authentication-Results: i=1; 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Signed-off-by: Richard Henderson Reviewed-by: Matt Turner Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg-opc.h | 1 + tcg/aarch64/tcg-target-has.h | 3 +++ tcg/loongarch64/tcg-target-has.h | 3 +++ tcg/ppc64/tcg-target-has.h | 3 +++ tcg/riscv64/tcg-target-has.h | 3 +++ tcg/s390x/tcg-target-has.h | 3 +++ tcg/sparc64/tcg-target-has.h | 3 +++ tcg/tci/tcg-target-has.h | 3 +++ tcg/x86_64/tcg-target-has.h | 3 +++ tcg/tcg.c | 22 ++++++++++++++++++++++ docs/devel/tcg-ops.rst | 4 ++++ tcg/aarch64/tcg-target.c.inc | 4 ++++ tcg/loongarch64/tcg-target.c.inc | 4 ++++ tcg/ppc64/tcg-target.c.inc | 3 +++ tcg/riscv64/tcg-target.c.inc | 3 +++ tcg/s390x/tcg-target.c.inc | 3 +++ tcg/sparc64/tcg-target.c.inc | 3 +++ tcg/tci/tcg-target.c.inc | 4 ++++ tcg/x86_64/tcg-target.c.inc | 4 ++++ 19 files changed, 79 insertions(+) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index f3a81d5d7fb..884345afe56 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -64,6 +64,7 @@ DEF(ld16s, 1, 1, 1, TCG_OPF_INT) DEF(ld32u, 1, 1, 1, TCG_OPF_INT) DEF(ld32s, 1, 1, 1, TCG_OPF_INT) DEF(ld, 1, 1, 1, TCG_OPF_INT) +DEF(lea, 1, 2, 2, TCG_OPF_INT) DEF(movcond, 1, 4, 1, TCG_OPF_INT) DEF(mul, 1, 2, 0, TCG_OPF_INT) DEF(muls2, 2, 2, 0, TCG_OPF_INT) diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h index 69e83efb69d..86672b2eab4 100644 --- a/tcg/aarch64/tcg-target-has.h +++ b/tcg/aarch64/tcg-target-has.h @@ -57,4 +57,7 @@ #define TCG_TARGET_sextract_valid(type, ofs, len) 1 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-= has.h index 32abc6f4574..31e6ea9632d 100644 --- a/tcg/loongarch64/tcg-target-has.h +++ b/tcg/loongarch64/tcg-target-has.h @@ -54,4 +54,7 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, uns= igned len) } #define TCG_TARGET_sextract_valid tcg_target_sextract_valid =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/ppc64/tcg-target-has.h b/tcg/ppc64/tcg-target-has.h index a3711feeae2..d11d82f1844 100644 --- a/tcg/ppc64/tcg-target-has.h +++ b/tcg/ppc64/tcg-target-has.h @@ -66,4 +66,7 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, uns= igned len) } #define TCG_TARGET_sextract_valid tcg_target_sextract_valid =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/riscv64/tcg-target-has.h b/tcg/riscv64/tcg-target-has.h index aef10c2d9d6..93f8baad09f 100644 --- a/tcg/riscv64/tcg-target-has.h +++ b/tcg/riscv64/tcg-target-has.h @@ -69,4 +69,7 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, uns= igned len) =20 #define TCG_TARGET_deposit_valid(type, ofs, len) 0 =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h index 0aeb5ba01a9..58e3afe5266 100644 --- a/tcg/s390x/tcg-target-has.h +++ b/tcg/s390x/tcg-target-has.h @@ -77,4 +77,7 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, uns= igned len) } #define TCG_TARGET_sextract_valid tcg_target_sextract_valid =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/sparc64/tcg-target-has.h b/tcg/sparc64/tcg-target-has.h index b29fd177f69..4182a7c1aae 100644 --- a/tcg/sparc64/tcg-target-has.h +++ b/tcg/sparc64/tcg-target-has.h @@ -19,4 +19,7 @@ =20 #define TCG_TARGET_deposit_valid(type, ofs, len) 0 =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h index 64742cf0b71..f4f9ddf595f 100644 --- a/tcg/tci/tcg-target-has.h +++ b/tcg/tci/tcg-target-has.h @@ -17,4 +17,7 @@ #define TCG_TARGET_sextract_valid(type, ofs, len) 1 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/x86_64/tcg-target-has.h b/tcg/x86_64/tcg-target-has.h index d249c1b3e7f..6ffae51f923 100644 --- a/tcg/x86_64/tcg-target-has.h +++ b/tcg/x86_64/tcg-target-has.h @@ -105,4 +105,7 @@ tcg_target_extract_valid(TCGType type, unsigned ofs, un= signed len) } #define TCG_TARGET_extract_valid tcg_target_extract_valid =20 +#define TCG_TARGET_lea_sh_valid(type, sh) 0 +#define TCG_TARGET_lea_imm_valid(type, imm) 0 + #endif diff --git a/tcg/tcg.c b/tcg/tcg.c index ecc1f54c1bf..c0e149e7eab 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1095,6 +1095,12 @@ typedef struct TCGOutOpSubtract { TCGReg a0, tcg_target_long a1, TCGReg a2); } TCGOutOpSubtract; =20 +typedef struct TCGOutOpLea { + TCGOutOp base; + void (*out)(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + TCGReg a2, unsigned sh, tcg_target_long imm); +} TCGOutOpLea; + #include "tcg-target.c.inc" =20 #ifndef CONFIG_TCG_INTERPRETER @@ -1191,6 +1197,7 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D { OUTOP(INDEX_op_ld16u, TCGOutOpLoad, outop_ld16u), OUTOP(INDEX_op_ld32s, TCGOutOpLoad, outop_ld32s), OUTOP(INDEX_op_ld32u, TCGOutOpLoad, outop_ld32u), + OUTOP(INDEX_op_lea, TCGOutOpLea, outop_lea), OUTOP(INDEX_op_movcond, TCGOutOpMovcond, outop_movcond), OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul), OUTOP(INDEX_op_muls2, TCGOutOpMul2, outop_muls2), @@ -5788,6 +5795,21 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) } break; =20 + case INDEX_op_lea: + { + const TCGOutOpLea *out =3D &outop_lea; + int sh =3D new_args[3]; + tcg_target_long imm =3D new_args[4]; + + tcg_debug_assert(!const_args[1]); + tcg_debug_assert(!const_args[2]); + tcg_debug_assert(TCG_TARGET_lea_sh_valid(type, sh)); + tcg_debug_assert(TCG_TARGET_lea_imm_valid(type, imm)); + + out->out(s, type, new_args[0], new_args[1], new_args[2], sh, i= mm); + } + break; + case INDEX_op_goto_ptr: tcg_debug_assert(!const_args[0]); tcg_out_goto_ptr(s, new_args[0]); diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index 88d48a1f99a..51fa183e911 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -524,6 +524,10 @@ Misc =20 - | Reverse the 64 bits of input *t1* with output in *dest*. =20 + * - lea *dest*, *t1*, *t2*, *sh*, *imm* + + - | *dest* =3D *t1* + (*t2* << *sh*) + *imm*. + Conditional moves ----------------- =20 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 4ebdef7e077..76adb2256f9 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -3081,6 +3081,10 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; + static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg args[TCG_MAX_OP_ARGS], diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 69e76807d6e..17784d8bbe2 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -2098,6 +2098,10 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; + static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg rd, TCGReg rs) { diff --git a/tcg/ppc64/tcg-target.c.inc b/tcg/ppc64/tcg-target.c.inc index cd1c2343672..99f4469f4b9 100644 --- a/tcg/ppc64/tcg-target.c.inc +++ b/tcg/ppc64/tcg-target.c.inc @@ -3633,6 +3633,9 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; =20 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index 2ce9d47a633..df4c4a9789b 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -2725,6 +2725,9 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 4d1a779c47c..2fd7012d047 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -3187,6 +3187,9 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; =20 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 35cd14a5b65..cb457453ff9 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -2120,6 +2120,9 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; =20 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 4cd1c1431ce..6942fdbb4e0 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -1220,6 +1220,10 @@ static inline bool tcg_out_sti(TCGContext *s, TCGTyp= e type, TCGArg val, return false; } =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; + /* Test if a constant matches the constraint. */ static bool tcg_target_const_match(int64_t val, int ct, TCGType type, TCGCond cond, int vece) diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc index 2c8f1f3e580..660350b963d 100644 --- a/tcg/x86_64/tcg-target.c.inc +++ b/tcg/x86_64/tcg-target.c.inc @@ -3327,6 +3327,10 @@ static const TCGOutOpStore outop_st =3D { .out_i =3D tgen_st_i, }; =20 +static const TCGOutOpLea outop_lea =3D { + .base.static_constraint =3D C_NotImplemented, +}; + static int const umin_insn[4] =3D { OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_VPMINUQ }; --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Fri, 28 Aug 2026 15:44:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 03/16] tcg: Add tcg_gen_lea_{i32,i64,tl} Date: Fri, 28 Aug 2026 15:44:38 -0700 Message-ID: <20260828224451.1564072-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957189711158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 4 ++ include/tcg/tcg-op.h | 2 + tcg/tcg-op.c | 90 +++++++++++++++++++++++++++++++++++++ 3 files changed, 96 insertions(+) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 9b321f959c0..b06445b8031 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -167,6 +167,8 @@ void tcg_gen_ussub_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i3= 2 arg2); void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); void tcg_gen_revbit8_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_lea_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b, + int32_t sh, int32_t imm); =20 /* Replicate a value of size @vece from @in to all the lanes in @out */ void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); @@ -282,6 +284,8 @@ void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); void tcg_gen_revbit8_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_lea_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b, + int64_t sh, int64_t imm); =20 /* Replicate a value of size @vece from @in to all the lanes in @out */ void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in); diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 37211642365..a7d001c959c 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -83,6 +83,7 @@ typedef TCGv_i64 TCGv; #define tcg_gen_shri_tl tcg_gen_shri_i64 #define tcg_gen_sar_tl tcg_gen_sar_i64 #define tcg_gen_sari_tl tcg_gen_sari_i64 +#define tcg_gen_lea_tl tcg_gen_lea_i64 #define tcg_gen_brcond_tl tcg_gen_brcond_i64 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 #define tcg_gen_setcond_tl tcg_gen_setcond_i64 @@ -209,6 +210,7 @@ typedef TCGv_i64 TCGv; #define tcg_gen_shri_tl tcg_gen_shri_i32 #define tcg_gen_sar_tl tcg_gen_sar_i32 #define tcg_gen_sari_tl tcg_gen_sari_i32 +#define tcg_gen_lea_tl tcg_gen_lea_i32 #define tcg_gen_brcond_tl tcg_gen_brcond_i32 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 #define tcg_gen_setcond_tl tcg_gen_setcond_i32 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 2c88f4f7ca9..fb5fef9422d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -498,6 +498,51 @@ void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int= 32_t arg2) } } =20 +void tcg_gen_lea_i32(TCGv_i32 ret, TCGv_i32 a1, TCGv_i32 a2, + int32_t sh, int32_t imm) +{ + TCGv_i32 t =3D tcg_temp_ebb_new_i32(); + + if (imm !=3D 0) { + if (TCG_TARGET_lea_imm_valid(TCG_TYPE_I32, imm)) { + /* + * The immediate is non-zero and valid. + * If the shift is out of range, perform the shift first + * so that we can still emit (a1 + t + imm) as one insn. + */ + if (!TCG_TARGET_lea_sh_valid(TCG_TYPE_I32, sh)) { + tcg_gen_shli_i32(t, a2, sh); + a2 =3D t; + sh =3D 0; + } + tcg_gen_op5ii_i32(INDEX_op_lea, ret, a1, a2, sh, imm); + goto done; + } + + /* + * If we can make the immediate smaller by folding it + * into a2 before the shift, do so. + */ + if (sh !=3D 0 && imm =3D=3D (imm >> sh) << sh) { + tcg_gen_addi_i32(t, a2, imm >> sh); + a2 =3D t; + imm =3D 0; + } + } + + if (sh =3D=3D 0) { + tcg_gen_add_i32(ret, a1, a2); + } else if (TCG_TARGET_lea_sh_valid(TCG_TYPE_I32, sh)) { + tcg_gen_op5ii_i32(INDEX_op_lea, ret, a1, a2, sh, 0); + } else { + tcg_gen_shli_i32(t, a2, sh); + tcg_gen_add_i32(ret, a1, t); + } + tcg_gen_addi_i32(ret, ret, imm); + done: + tcg_temp_free_i32(t); +} + void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLab= el *l) { if (cond =3D=3D TCG_COND_ALWAYS) { @@ -1623,6 +1668,51 @@ void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, i= nt64_t arg2) } } =20 +void tcg_gen_lea_i64(TCGv_i64 ret, TCGv_i64 a1, TCGv_i64 a2, + int64_t sh, int64_t imm) +{ + TCGv_i64 t =3D tcg_temp_ebb_new_i64(); + + if (imm !=3D 0) { + if (TCG_TARGET_lea_imm_valid(TCG_TYPE_I64, imm)) { + /* + * The immediate is non-zero and valid. + * If the shift is out of range, perform the shift first + * so that we can still emit (a1 + t + imm) as one insn. + */ + if (!TCG_TARGET_lea_sh_valid(TCG_TYPE_I64, sh)) { + tcg_gen_shli_i64(t, a2, sh); + a2 =3D t; + sh =3D 0; + } + tcg_gen_op5ii_i64(INDEX_op_lea, ret, a1, a2, sh, imm); + goto done; + } + + /* + * If we can make the immediate smaller by folding it + * into a2 before the shift, do so. + */ + if (sh !=3D 0 && imm =3D=3D (imm >> sh) << sh) { + tcg_gen_addi_i64(t, a2, imm >> sh); + a2 =3D t; + imm =3D 0; + } + } + + if (sh =3D=3D 0) { + tcg_gen_add_i64(ret, a1, a2); + } else if (TCG_TARGET_lea_sh_valid(TCG_TYPE_I64, sh)) { + tcg_gen_op5ii_i64(INDEX_op_lea, ret, a1, a2, sh, 0); + } else { + tcg_gen_shli_i64(t, a2, sh); + tcg_gen_add_i64(ret, a1, t); + } + tcg_gen_addi_i64(ret, ret, imm); + done: + tcg_temp_free_i64(t); +} + void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLab= el *l) { if (cond =3D=3D TCG_COND_ALWAYS) { --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 28 Aug 2026 15:44:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 04/16] tcg/optimize: Handle INDEX_op_lea Date: Fri, 28 Aug 2026 15:44:39 -0700 Message-ID: <20260828224451.1564072-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957170451154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/optimize.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index d291c844ca8..83f95e26643 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2101,6 +2101,68 @@ static bool fold_extu(OptContext *ctx, TCGOp *op) return fold_masks_zo(ctx, op, z_mask, o_mask); } =20 +static bool fold_shift(OptContext *ctx, TCGOp *op); +static bool fold_lea(OptContext *ctx, TCGOp *op) +{ + TCGArg sh =3D op->args[3]; + TCGArg imm =3D op->args[4]; + int var_mask =3D 0; + + if (arg_is_const(op->args[1])) { + imm +=3D arg_const_val(op->args[1]); + } else { + var_mask |=3D 1; + } + if (arg_is_const(op->args[2])) { + imm +=3D arg_const_val(op->args[2]) << sh; + } else { + var_mask |=3D 2; + } + + switch (var_mask) { + case 0: + return tcg_opt_gen_movi(ctx, op, op->args[0], imm); + + case 1: + if (imm =3D=3D 0) { + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); + } + op->opc =3D INDEX_op_add; + op->args[2] =3D arg_new_constant(ctx, imm); + break; + + case 2: + if (sh =3D=3D 0) { + if (imm =3D=3D 0) { + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]); + } + op->opc =3D INDEX_op_add; + op->args[1] =3D op->args[2]; + op->args[2] =3D arg_new_constant(ctx, imm); + break; + } + if (imm =3D=3D 0) { + op->opc =3D INDEX_op_shl; + op->args[1] =3D op->args[2]; + op->args[2] =3D arg_new_constant(ctx, sh); + return fold_shift(ctx, op); + } + + /* If arg1 was not already 0, fold the immediates. */ + if (arg_const_val(op->args[1]) !=3D 0) { + if (TCG_TARGET_lea_imm_valid(ctx->type, imm)) { + op->args[1] =3D arg_new_constant(ctx, 0); + op->args[4] =3D imm; + } else { + op->args[1] =3D arg_new_constant(ctx, imm); + op->args[4] =3D 0; + } + } + break; + } + return finish_folding(ctx, op); +} + static bool fold_mb(OptContext *ctx, TCGOp *op) { /* Eliminate duplicate and redundant fence instructions. */ @@ -3209,6 +3271,9 @@ void tcg_optimize(TCGContext *s) case INDEX_op_st_vec: done =3D fold_tcg_st_memcopy(&ctx, op); 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Fri, 28 Aug 2026 15:44:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 05/16] target/alpha: Use tcg_gen_lea_i64 for S{4,8}ADD{L,Q} Date: Fri, 28 Aug 2026 15:44:40 -0700 Message-ID: <20260828224451.1564072-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957193906154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/translate.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index c66e3f9c146..6f18b8d1af6 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -1474,10 +1474,8 @@ static DisasJumpType translate_one(DisasContext *ctx= , uint32_t insn) break; case 0x02: /* S4ADDL */ - tmp =3D tcg_temp_new_i64(); - tcg_gen_shli_i64(tmp, va, 2); - tcg_gen_add_i64(tmp, tmp, vb); - tcg_gen_ext32s_i64(vc, tmp); + tcg_gen_lea_i64(vc, vb, va, 2, 0); + tcg_gen_ext32s_i64(vc, vc); break; case 0x09: /* SUBL */ @@ -1502,10 +1500,8 @@ static DisasJumpType translate_one(DisasContext *ctx= , uint32_t insn) break; case 0x12: /* S8ADDL */ - tmp =3D tcg_temp_new_i64(); - tcg_gen_shli_i64(tmp, va, 3); - tcg_gen_add_i64(tmp, tmp, vb); - tcg_gen_ext32s_i64(vc, tmp); + tcg_gen_lea_i64(vc, vb, va, 3, 0); + tcg_gen_ext32s_i64(vc, vc); break; case 0x1B: /* S8SUBL */ @@ -1524,9 +1520,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) break; case 0x22: /* S4ADDQ */ - tmp =3D tcg_temp_new_i64(); - tcg_gen_shli_i64(tmp, va, 2); - tcg_gen_add_i64(vc, tmp, vb); + tcg_gen_lea_i64(vc, vb, va, 2, 0); break; case 0x29: /* SUBQ */ @@ -1544,9 +1538,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) break; case 0x32: /* S8ADDQ */ - tmp =3D tcg_temp_new_i64(); - tcg_gen_shli_i64(tmp, va, 3); - tcg_gen_add_i64(vc, tmp, vb); + tcg_gen_lea_i64(vc, vb, va, 3, 0); break; case 0x3B: /* S8SUBQ */ --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Fri, 28 Aug 2026 15:44:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 06/16] target/loongarch: Use tcg_gen_lea_tl for ALSL Date: Fri, 28 Aug 2026 15:44:41 -0700 Message-ID: <20260828224451.1564072-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957171664154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/loongarch/tcg/insn_trans/trans_arith.c.inc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/loongarch/tcg/insn_trans/trans_arith.c.inc b/target/loo= ngarch/tcg/insn_trans/trans_arith.c.inc index 2be057e9320..c358e642649 100644 --- a/target/loongarch/tcg/insn_trans/trans_arith.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_arith.c.inc @@ -188,9 +188,7 @@ static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2) =20 static void gen_alsl(TCGv dest, TCGv src1, TCGv src2, target_long sa) { - TCGv t0 =3D tcg_temp_new(); - tcg_gen_shli_tl(t0, src1, sa); - tcg_gen_add_tl(dest, t0, src2); + tcg_gen_lea_tl(dest, src2, src1, sa, 0); } =20 static bool trans_lu32i_d(DisasContext *ctx, arg_lu32i_d *a) --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 28 Aug 2026 15:44:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 07/16] target/riscv: Use tcg_gen_lea_tl for SH*ADD Date: Fri, 28 Aug 2026 15:44:42 -0700 Message-ID: <20260828224451.1564072-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957199680158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/tcg/insn_trans/trans_rvb.c.inc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/riscv/tcg/insn_trans/trans_rvb.c.inc b/target/riscv/tcg= /insn_trans/trans_rvb.c.inc index 3e74be223b0..82e715c7b73 100644 --- a/target/riscv/tcg/insn_trans/trans_rvb.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvb.c.inc @@ -336,10 +336,7 @@ static bool trans_orc_b(DisasContext *ctx, arg_orc_b *= a) #define GEN_SHADD(SHAMT) \ static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \ { \ - TCGv t =3D tcg_temp_new(); \ - \ - tcg_gen_shli_tl(t, arg1, SHAMT); \ - tcg_gen_add_tl(ret, t, arg2); \ + tcg_gen_lea_tl(ret, arg2, arg1, SHAMT, 0); \ } =20 GEN_SHADD(1) --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[71.212.39.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-398a2f5187fsm427594a91.1.2026.08.28.15.44.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 15:44:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787957099; x=1788561899; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=wqyWqrNHgCEd77o3WFnPquFGCTdKezfyPjVR9D6xPB0=; b=a/wi0unMDjLpPZpCNrWDMU3dkFyGrPcMjY/kTy+A4HkuCXZbPVI9LH745eVLloiHG2 h6QMu9JRmTGTwfW/+QcJey/PWbhdWHLfqFMJvRTC0Vcyy0Sya8/Nln9NKMFZOfd1U1Mj bCqto2MogBX/e0kSVRETkgNQjwYfOKTpdHZ4S6lciNJbhUga3stjqAK7NOnXbQFbm3WZ zLgpW2xFO1i4mLeFaIAa4tpktO92oIzi3LHZkiO/BPbvfPjjTfo1qecOjmuJLYxRwzp3 1t22X2L5VWIbpmwyaBrkVIwJCTHGl4Tgk4L/M2Nqn8SYoUlYQIczk4lOEyoSY6HcWYlK GMNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787957099; x=1788561899; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=wqyWqrNHgCEd77o3WFnPquFGCTdKezfyPjVR9D6xPB0=; b=ANmuoA5OwMz2SyoRZ9hNb5hfSq2GHXHWPXt9ee3VS8Xi3faupZtSb58qQnBwM8jjGT b0IyPv4WIgWFYIZpdxijU5aPbnG4McKzRkq+TWK0cSCMmNNUPSzHgKikpGn9w5pPqUKH WM6Fjzz8ah+SdpytliJS54gvtUSZPxlFSb0XQJXDxvNS20/XDzrUWm1r8LgFw/gDb1vg lh/skD7CJ0JE3Of+AhfyekJSrKr4ThP57tkwwowqH+++vOGpk7F70JYTJcpUKf1WeQLN vx1qRpEvAfraqMlR4KtgzyRh4qRt4hb/yySTRXTaUsdR9lKeefFCss8uJ0gK5Tbeddad H7Eg== X-Gm-Message-State: AFuF++n/lpf2jvcUo705vltcGvSDIWS1AK3B4oWBE/rTXe9DP+fy7cZ6 nOihDTagsdIl6cjrJxwVBaacrgYsqjJOdBrcd5wxZ9JrnPpnaXMp4CXtjO1I/8dMzsAU2PDBbay CCoOik3w= X-Gm-Gg: AYBFou2CQ53YD469T30Fw9W6eSjowKWh2RG97Qqnf6Ha9fBUcXWVlJQAc8wAPh6VFDW 7n977R5T2PfpN7/eTuUuPHLZjm+DapAW6VUHFxOLhDtpFi7tzLiw2n45RHNj/ILvS3mben0X6np +49eLmdBPpRiW7izXWjEpWSA9hOLz/QdRosS2HlLYnfQfPwfz3t8JdXBQi5EFROgFwSPOGiaRQK EWD9UU9n3VJkAWofsxxw01nwN3ce11HKFkd1a598fWlwSI3DRmZ6NvrvdAHiidGZiBU/aL/Xi00 FL55mWUj2l9her9qN7BdkakMLaPeK7qkUYXUZATlKM1dehKjhHlnxP6AT65DHi71F2iBpUqkors ExUwlavsNFIjyHwcc+pG9bjKOiWLWSXf9VnKhnTTLWfppFKsUpCeXV17N3mdFhqB83nLG6eJ2bH IYYMd8aMCISTXcy7Mb9hGGr97OwvboA8BbYr84JRzyJ27bywMpov8etDVQN9gn551RrgdSbUtcR cryNUErTbZsUVsKOLpV X-Received: by 2002:a17:90a:e710:b0:381:528a:808c with SMTP id 98e67ed59e1d1-396d10085b8mr20699264a91.12.1787957099247; Fri, 28 Aug 2026 15:44:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 08/16] target/s390x: Use tcg_gen_lea_i64 in get_address Date: Fri, 28 Aug 2026 15:44:43 -0700 Message-ID: <20260828224451.1564072-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957171610154100 Content-Type: text/plain; charset="utf-8" While there's no actual shift, use the compound function to add two registers and an immediate in one step. Signed-off-by: Richard Henderson Reviewed-by: Matt Turner Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/s390x/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 1b6023168bb..4eb2eba5e45 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -460,8 +460,8 @@ static TCGv_i64 get_address(DisasContext *s, int x2, in= t b2, int d2) * displacements early we create larger immediate addends. */ if (b2 && x2) { - tcg_gen_add_i64(tmp, regs[b2], regs[x2]); - gen_addi_and_wrap_i64(s, tmp, tmp, d2); + tcg_gen_lea_i64(tmp, regs[b2], regs[x2], 0, d2); + gen_addi_and_wrap_i64(s, tmp, tmp, 0); } else if (b2) { gen_addi_and_wrap_i64(s, tmp, regs[b2], d2); } else if (x2) { --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787957202; cv=none; d=zohomail.com; s=zohoarc; b=dT6cOZJPBCJSj+FOhAOcf8QbP6cE9Gi5tnduSdh3iEn1eno4ZTNrQlODGoau0lsLREPJygShyWwRpbbucGM2Eocw2HaijXMxk9ffD2eGS4rJY4nYan+TWPSbRDShpjk2fh9yKFUiG7FEY1wV1OmRNAY++92cY3zipdmWmJKTQoQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787957202; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kjM1/d/rZ39I6QxObJ8R61I/A1eoAPQ0NqTmgqOA2NE=; b=PlUUi5mrE4Jx3Rd6L1nL/mJCXDYD45Dfxr7N/Y+Wzgr5yX+N1du4Vsb3ywJZFxtw73fJSnuzbHbKLCtUy/Ky34f+U3GgA9HzJsX2yuKVyY8VNjCAcwVZAG/uhWm2fP2LVuLAVKL9bqZB0D32hIhoHmFtPNrp0womps53gnCVU90= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787957202537835.66407693415; Fri, 28 Aug 2026 15:46:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x05Jr-00015A-J7; Fri, 28 Aug 2026 18:45:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x05Jm-00010u-VQ for qemu-devel@nongnu.org; Fri, 28 Aug 2026 18:45:02 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x05Jl-0004Mw-DR for qemu-devel@nongnu.org; Fri, 28 Aug 2026 18:45:02 -0400 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-38dc69c74b8so1275084a91.0 for ; Fri, 28 Aug 2026 15:45:01 -0700 (PDT) Received: from stoup (71-212-39-143.tukw.qwest.net. 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cpu_regs[a.base] : NULL); =20 if (a.index >=3D 0 && !is_vsib) { + TCGv index =3D cpu_regs[a.index]; + + if (ea) { + tcg_gen_lea_tl(s->A0, ea, index, a.scale, a.disp); + return s->A0; + } if (a.scale =3D=3D 0) { - ea =3D cpu_regs[a.index]; + ea =3D index; } else { - tcg_gen_shli_tl(s->A0, cpu_regs[a.index], a.scale); + tcg_gen_shli_tl(s->A0, index, a.scale); ea =3D s->A0; } - if (a.base >=3D 0) { - tcg_gen_add_tl(s->A0, ea, cpu_regs[a.base]); - ea =3D s->A0; - } - } else if (a.base >=3D 0) { - ea =3D cpu_regs[a.base]; - } - if (!ea) { + } else if (!ea) { if (tb_cflags(s->base.tb) & CF_PCREL && a.base =3D=3D -2) { /* With cpu_eip ~=3D pc_save, the expression is pc-relative. */ tcg_gen_addi_tl(s->A0, cpu_eip, a.disp - s->pc_save); } else { tcg_gen_movi_tl(s->A0, a.disp); } - ea =3D s->A0; - } else if (a.disp !=3D 0) { + return s->A0; + } + + if (a.disp !=3D 0) { tcg_gen_addi_tl(s->A0, ea, a.disp); ea =3D s->A0; } --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787957176; cv=none; d=zohomail.com; s=zohoarc; b=dxMME90q68CgpNMP0vRYobSseu2xi8vL9tJrvN2QMy1yU3mbshXFzVD/ezxwzPSVxiN2iUPtO30xe3VGs5gHdPZ+nA8W9ffYfWWDBb+BfO20zD9gITNFXlEUvlI7SxP4HloSwbYBeInbu3dIf1R7VIu5c79tX5Y0RxOldjN0xLk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787957176; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IGVbaoEVsWIydAAkJGpVk0FOSYkkpsgqDdITVO8oMWQ=; b=Mi2gbkg4sxl7Th7G9bXeQ3kikji4ekYpOsWF3faUQYWiPqapUn+bGKOuVUs/fLRruiOLNSSxEbEouOLy5d1yVYuaEUUUPQtJMcj9eLoHJxRGNF2Wdjaz9fplbjvoSqAJvx+j7te9Jn3TDXEEUMoK6PP9eo8RXr3p84ElPqxYyMo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787957176977385.54966687111255; Fri, 28 Aug 2026 15:46:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x05Jp-00013P-Ay; Fri, 28 Aug 2026 18:45:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x05Jo-00012G-4i for qemu-devel@nongnu.org; Fri, 28 Aug 2026 18:45:04 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x05Jm-0004NC-1N for qemu-devel@nongnu.org; Fri, 28 Aug 2026 18:45:03 -0400 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-3964e480f76so1915742a91.1 for ; Fri, 28 Aug 2026 15:45:01 -0700 (PDT) Received: from stoup (71-212-39-143.tukw.qwest.net. [71.212.39.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-398a2f5187fsm427594a91.1.2026.08.28.15.45.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 15:45:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787957101; x=1788561901; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=IGVbaoEVsWIydAAkJGpVk0FOSYkkpsgqDdITVO8oMWQ=; b=JeUSknt+5AOPJS1cetoThswAhwz2FKv2+6s1dJ+Ph/Wh+meSK1rqVm9H4fWHhF7Ohq CcDD0UnmvrPERp1JvOSckMKBUfhjJsslAU4RzWdSlT+QsjiqY+QjD+0XweILp7ZUrvPj IVWC8jH07WWoX/iO9iaa6syZci+6hv+Iebh0GcB3p9a969LuFhGjlCryhm37JQqG+HJ7 em8JS2e870rtih0un33Ydo6gOZOFGIvWTNHHf4kGnEYNAraeNYg62NbqptCJDC8pNEjd +CswXvYJAo0H7koL+gGw+3embyl+kN39woM3jWDcLJCJ27rct96K/VmoT5VZbLiF46kh 0CsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787957101; x=1788561901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=IGVbaoEVsWIydAAkJGpVk0FOSYkkpsgqDdITVO8oMWQ=; b=d0HuoHXnDwPrENFutx8ErJhFxIfVbpStJgiq0vOqplb73T3RKPTbDKtOGLmBZCvU/x 1wdDIRUDcOyQCSrcnj9/lcmII5pLvbxKFhxkQV+SpCqZ0GUrre/GdwzX+RxbQLpypUYk bQiPBHiYMFQeEZq2C14p1baB29eAwQEL6vGJrcFbSkM6Mm4vV/HCz73l7ep+Lyd4Fc6z J4zVYH1KmqMg5kWCeKhhVpKh7qww2tS/BRQEWSQcWhDB6cCVmk6qLqpAM5Lq1MTKn8mZ ssnRE2inC9yR6NGiWnlobfsBiEZnqt75FXWvfy+su+je2KL0/ndB5g25SR96x92BHy2t xNSQ== X-Gm-Message-State: AFuF++mE/8nI3eHCfyGsBRfMa20S25k1eBtulZ8wTwf+MWUqGICzjJNT 9X6Cmqh8aNYPBGjLG6XCb3o4Al4yzv1bm7+seLPx6rDJU00VUiyqYnACrdsIab64967lB2jTG/6 ptQnyiQw= X-Gm-Gg: AYBFou3ObGQxeEl0qGF7CBFsSzu09wCtrW8GWKJesngpAzPKMnf+kWd9vGodmHLOiFn aR1WBnAOhQK5LZzAUjm2anhYOVMC5DtU9PlXpGazAggGTeVm5hBYxST5tYaj074iuw96hrWatzn 5CQMTQUlcelXjcDWB95Jo+wXL/RNgEVzhNTp18vwj8MIm7DE2pMEr4huND4zun3Tlg1mqRk91SC T7ukucxoYRvrP+SFVlotckTF+4Uphrebr0BuUxkHu4/VMfk3tJFZ9f6qZ36sDVE5Hk1ebQJMXz8 5RWx/gLarpVY01Jgkq9YuE1YCUj18L9YoeWSR0UEPScGDsnrWWoOkGmzzyrX0BnhnmPdF8ldyOq KtErDdXOeR++cd/K313SjztzRzaQwZ1U1sBUIQJYK6ag7lwDs3DODgAGuxJhl4i2ddudcOj5JHq ++nUIJDXPzBtjeUOjzgA0SX9E0q1yIY1MdebPq0OAREP8toCcT+egl3q77OSMoCSlr0KgZBeeGM 4yvmoAdeBkpgEgc5jtR X-Received: by 2002:a17:90b:2b90:b0:38a:c3f:3b87 with SMTP id 98e67ed59e1d1-396d0fce294mr20370427a91.12.1787957100629; Fri, 28 Aug 2026 15:45:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 10/16] tcg/x86_64: Introduce TCG_REG_NONE Date: Fri, 28 Aug 2026 15:44:45 -0700 Message-ID: <20260828224451.1564072-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957177925158500 Content-Type: text/plain; charset="utf-8" Rather than hard-code -1, or compare < 0, use something more descriptive. This also allows more use of TCGReg. Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/x86_64/tcg-target.h | 1 + tcg/x86_64/tcg-target.c.inc | 66 ++++++++++++++++++++----------------- 2 files changed, 36 insertions(+), 31 deletions(-) diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h index 7ebae56a7d7..7109722f240 100644 --- a/tcg/x86_64/tcg-target.h +++ b/tcg/x86_64/tcg-target.h @@ -31,6 +31,7 @@ #define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB) =20 typedef enum { + TCG_REG_NONE =3D -1, TCG_REG_EAX =3D 0, TCG_REG_ECX, TCG_REG_EDX, diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc index 660350b963d..ec397e287c0 100644 --- a/tcg/x86_64/tcg-target.c.inc +++ b/tcg/x86_64/tcg-target.c.inc @@ -210,7 +210,8 @@ static bool tcg_target_const_match(int64_t val, int ct, return 0; } =20 -# define LOWREGMASK(x) ((x) & 7) +#define LOWREGMASK(x) ((x) & 7) +#define REGOR0(x) ((x) =3D=3D TCG_REG_NONE ? 0 : (x)) =20 #define P_EXT 0x100 /* 0x0f opcode prefix */ #define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ @@ -524,7 +525,7 @@ static const uint8_t tcg_cond_to_jcc[] =3D { [TCG_COND_TSTNE] =3D JCC_JNE, }; =20 -static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) +static void tcg_out_opc(TCGContext *s, int opc, TCGReg r, TCGReg rm, TCGRe= g x) { int rex; =20 @@ -572,14 +573,14 @@ static void tcg_out_opc(TCGContext *s, int opc, int r= , int rm, int x) tcg_out8(s, opc); } =20 -static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) +static void tcg_out_modrm(TCGContext *s, int opc, TCGReg r, TCGReg rm) { tcg_out_opc(s, opc, r, rm, 0); tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } =20 -static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, - int rm, int index) +static void tcg_out_vex_opc(TCGContext *s, int opc, TCGReg r, TCGReg v, + TCGReg rm, TCGReg index) { int tmp; =20 @@ -630,8 +631,8 @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int= r, int v, tcg_out8(s, opc); } =20 -static void tcg_out_evex_opc(TCGContext *s, int opc, int r, int v, - int rm, int index, int aaa, bool z) +static void tcg_out_evex_opc(TCGContext *s, int opc, TCGReg r, TCGReg v, + TCGReg rm, TCGReg index, int aaa, bool z) { /* The entire 4-byte evex prefix; with R' and V' set. */ uint32_t p =3D 0x08041062; @@ -676,7 +677,8 @@ static void tcg_out_evex_opc(TCGContext *s, int opc, in= t r, int v, tcg_out8(s, opc); } =20 -static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) +static void tcg_out_vex_modrm(TCGContext *s, int opc, TCGReg r, + TCGReg v, TCGReg rm) { if (opc & P_EVEX) { tcg_out_evex_opc(s, opc, r, v, rm, 0, 0, false); @@ -687,7 +689,7 @@ static void tcg_out_vex_modrm(TCGContext *s, int opc, i= nt r, int v, int rm) } =20 static void tcg_out_vex_modrm_type(TCGContext *s, int opc, - int r, int v, int rm, TCGType type) + TCGReg r, TCGReg v, TCGReg rm, TCGType = type) { if (type =3D=3D TCG_TYPE_V256) { opc |=3D P_VEXL; @@ -695,8 +697,8 @@ static void tcg_out_vex_modrm_type(TCGContext *s, int o= pc, tcg_out_vex_modrm(s, opc, r, v, rm); } =20 -static void tcg_out_evex_modrm_type(TCGContext *s, int opc, int r, int v, - int rm, int aaa, bool z, TCGType type) +static void tcg_out_evex_modrm_type(TCGContext *s, int opc, TCGReg r, TCGR= eg v, + TCGReg rm, int aaa, bool z, TCGType ty= pe) { if (type =3D=3D TCG_TYPE_V256) { opc |=3D P_VEXL; @@ -710,12 +712,12 @@ static void tcg_out_evex_modrm_type(TCGContext *s, in= t opc, int r, int v, mode for absolute addresses, ~RM is the size of the immediate operand that will follow the instruction. */ =20 -static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, +static void tcg_out_sib_offset(TCGContext *s, TCGReg r, TCGReg rm, TCGReg = index, int shift, intptr_t offset) { int mod, len; =20 - if (index < 0 && rm < 0) { + if (index =3D=3D TCG_REG_NONE && rm =3D=3D TCG_REG_NONE) { /* * Try for a rip-relative addressing mode. This has replaced * the 32-bit-mode absolute addressing encoding. @@ -746,7 +748,7 @@ static void tcg_out_sib_offset(TCGContext *s, int r, in= t rm, int index, =20 /* Find the length of the immediate addend. Note that the encoding that would be used for (%ebp) indicates absolute addressing. */ - if (rm < 0) { + if (rm =3D=3D TCG_REG_NONE) { mod =3D 0, len =3D 4, rm =3D 5; } else if (offset =3D=3D 0 && LOWREGMASK(rm) !=3D TCG_REG_EBP) { mod =3D 0, len =3D 0; @@ -758,7 +760,7 @@ static void tcg_out_sib_offset(TCGContext *s, int r, in= t rm, int index, =20 /* Use a single byte MODRM format if possible. Note that the encoding that would be used for %esp is the escape to the two byte form. */ - if (index < 0 && LOWREGMASK(rm) !=3D TCG_REG_ESP) { + if (index =3D=3D TCG_REG_NONE && LOWREGMASK(rm) !=3D TCG_REG_ESP) { /* Single byte MODRM format. */ tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } else { @@ -767,7 +769,7 @@ static void tcg_out_sib_offset(TCGContext *s, int r, in= t rm, int index, /* Note that the encoding that would place %esp into the index field indicates no index register. In 64-bit mode, the REX.X bit counts, so %r12 can be used as the index. */ - if (index < 0) { + if (index =3D=3D TCG_REG_NONE) { index =3D 4; } else { tcg_debug_assert(index !=3D TCG_REG_ESP); @@ -784,32 +786,34 @@ static void tcg_out_sib_offset(TCGContext *s, int r, = int rm, int index, } } =20 -static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, - int index, int shift, intptr_t offset) +static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, TCGReg r, + TCGReg rm, TCGReg index, + int shift, intptr_t offset) { - tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index); + tcg_out_opc(s, opc, r, REGOR0(rm), REGOR0(index)); tcg_out_sib_offset(s, r, rm, index, shift, offset); } =20 -static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, in= t v, - int rm, int index, int shift, +static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, + TCGReg r, TCGReg v, TCGReg rm, + TCGReg index, int shift, intptr_t offset) { - tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index); + tcg_out_vex_opc(s, opc, r, v, REGOR0(rm), REGOR0(index)); tcg_out_sib_offset(s, r, rm, index, shift, offset); } =20 /* A simplification of the above with no index or shift. */ -static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, - int rm, intptr_t offset) +static void tcg_out_modrm_offset(TCGContext *s, int opc, TCGReg r, + TCGReg rm, intptr_t offset) { - tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset); + tcg_out_modrm_sib_offset(s, opc, r, rm, TCG_REG_NONE, 0, offset); } =20 -static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r, - int v, int rm, intptr_t offset) +static void tcg_out_vex_modrm_offset(TCGContext *s, int opc, TCGReg r, + TCGReg v, TCGReg rm, intptr_t offset) { - tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset); + tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, TCG_REG_NONE, 0, offset= ); } =20 /* Output an opcode with an expected reference to the constant pool. */ @@ -1889,7 +1893,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 #ifdef CONFIG_USER_ONLY static HostAddress x86_guest_base =3D { - .index =3D -1 + .index =3D TCG_REG_NONE }; =20 #if defined(__linux__) @@ -2173,7 +2177,7 @@ static void tgen_qemu_ld(TCGContext *s, TCGType type,= TCGReg data, HostAddress h; =20 ldst =3D prepare_host_addr(s, &h, addr, oi, true); - tcg_out_qemu_ld_direct(s, data, -1, h, type, get_memop(oi)); + tcg_out_qemu_ld_direct(s, data, TCG_REG_NONE, h, type, get_memop(oi)); =20 if (ldst) { ldst->type =3D type; @@ -2311,7 +2315,7 @@ static void tgen_qemu_st(TCGContext *s, TCGType type,= TCGReg data, HostAddress h; =20 ldst =3D prepare_host_addr(s, &h, addr, oi, false); - tcg_out_qemu_st_direct(s, data, -1, h, get_memop(oi)); + tcg_out_qemu_st_direct(s, data, TCG_REG_NONE, h, get_memop(oi)); =20 if (ldst) { ldst->type =3D type; --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787957169; cv=none; d=zohomail.com; s=zohoarc; b=Ic0Rf4sUFGMHvXj5ktuLXylPJNa2uxi3xmWRSTCK7sxz02lNqSYQwPfBn/MZRvnxlZuF8lYe9VvjN+i8qvbbnq1LE7fOGGpEf204BZY/2TXiNw9kzCKkd8M1Vdh6GLVozloOPO85U9Ojagw3xfvVn2ACda+HA3OA+VRqTOVAWCg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787957169; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=k7apDi5G/qgt0uMemM+43oBLUrsOqwhkU7pSrCFTWHc=; b=NlfGJdgygyFC54wQF2LEagfmUfnHOXo8R6rrnyvbiWQcvRvbyePe0LNeMU0vFhg1cXKMAO2v72CBS4mHz3A674j8EZP3qpqDF603HBgo/xUdm99WyfwmaFifXaUtZ7mcCjArUzXYgimRP4WFraf/WzokF/I8JFFYHap1tfjwMUA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787957169176647.541519175273; Fri, 28 Aug 2026 15:46:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x05Jq-00014F-6y; Fri, 28 Aug 2026 18:45:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x05Jo-00012w-OR for qemu-devel@nongnu.org; Fri, 28 Aug 2026 18:45:04 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x05Jn-0004Nh-7f for qemu-devel@nongnu.org; Fri, 28 Aug 2026 18:45:04 -0400 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-382ef647e20so1517077a91.1 for ; Fri, 28 Aug 2026 15:45:02 -0700 (PDT) Received: from stoup (71-212-39-143.tukw.qwest.net. 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Fri, 28 Aug 2026 15:45:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 11/16] tcg/x86_64: Implement INDEX_op_lea Date: Fri, 28 Aug 2026 15:44:46 -0700 Message-ID: <20260828224451.1564072-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957171606158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/x86_64/tcg-target-con-set.h | 1 + tcg/x86_64/tcg-target-has.h | 4 ++-- tcg/x86_64/tcg-target.h | 2 ++ tcg/x86_64/tcg-target.c.inc | 11 ++++++++++- 4 files changed, 15 insertions(+), 3 deletions(-) diff --git a/tcg/x86_64/tcg-target-con-set.h b/tcg/x86_64/tcg-target-con-se= t.h index 458d69c3c07..5af8c1cb2cd 100644 --- a/tcg/x86_64/tcg-target-con-set.h +++ b/tcg/x86_64/tcg-target-con-set.h @@ -46,6 +46,7 @@ C_O1_I2(r, r, r) C_O1_I2(r, r, re) C_O1_I2(r, r, ri) C_O1_I2(r, rO, re) +C_O1_I2(r, rz, r) C_O1_I2(x, x, x) C_N1_I2(r, r, r) C_N1_I2(r, r, rW) diff --git a/tcg/x86_64/tcg-target-has.h b/tcg/x86_64/tcg-target-has.h index 6ffae51f923..4f06b395de4 100644 --- a/tcg/x86_64/tcg-target-has.h +++ b/tcg/x86_64/tcg-target-has.h @@ -105,7 +105,7 @@ tcg_target_extract_valid(TCGType type, unsigned ofs, un= signed len) } #define TCG_TARGET_extract_valid tcg_target_extract_valid =20 -#define TCG_TARGET_lea_sh_valid(type, sh) 0 -#define TCG_TARGET_lea_imm_valid(type, imm) 0 +#define TCG_TARGET_lea_sh_valid(type, sh) ((sh) >=3D 0 && (sh) <= =3D 3) +#define TCG_TARGET_lea_imm_valid(type, imm) ((imm) =3D=3D (int32_t)= (imm)) =20 #endif diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h index 7109722f240..3444bcdca0a 100644 --- a/tcg/x86_64/tcg-target.h +++ b/tcg/x86_64/tcg-target.h @@ -80,4 +80,6 @@ typedef enum { TCG_REG_CALL_STACK =3D TCG_REG_ESP } TCGReg; =20 +#define TCG_REG_ZERO TCG_REG_NONE + #endif diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc index ec397e287c0..a41252782e1 100644 --- a/tcg/x86_64/tcg-target.c.inc +++ b/tcg/x86_64/tcg-target.c.inc @@ -3331,8 +3331,17 @@ static const TCGOutOpStore outop_st =3D { .out_i =3D tgen_st_i, }; =20 +static void tgen_lea(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + TCGReg a2, unsigned sh, tcg_target_long imm) +{ + int rexw =3D type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW; + tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, sh, imm); +} + static const TCGOutOpLea outop_lea =3D { - .base.static_constraint =3D C_NotImplemented, + /* Allow "lea imm(, a2, sh), a0" via TCG_REG_ZERO constraint */ + .base.static_constraint =3D C_O1_I2(r, rz, r), + .out =3D tgen_lea, }; =20 static int const umin_insn[4] =3D { --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 28 Aug 2026 15:45:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 12/16] tcg/loongarch64: Import SLADD insns Date: Fri, 28 Aug 2026 15:44:47 -0700 Message-ID: <20260828224451.1564072-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957202201154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/loongarch64/tcg-insn-defs.c.inc | 30 ++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc b/tcg/loongarch64/tcg-insn= -defs.c.inc index e907fc755f5..ececc6a3dd5 100644 --- a/tcg/loongarch64/tcg-insn-defs.c.inc +++ b/tcg/loongarch64/tcg-insn-defs.c.inc @@ -4,7 +4,7 @@ * * This file is auto-generated by genqemutcgdefs from * https://github.com/loongson-community/loongarch-opcodes, - * from commit 1b95bb8c443ad71e266120fd97bd227df2d8ecfc. + * from commit 2d84c975e8894afc8b3ee9b8559f10308a658440. * DO NOT EDIT. */ =20 @@ -24,6 +24,7 @@ typedef enum { OPC_REVBIT_D =3D 0x00005400, OPC_SEXT_H =3D 0x00005800, OPC_SEXT_B =3D 0x00005c00, + OPC_SLADD_W =3D 0x00040000, OPC_ADD_W =3D 0x00100000, OPC_ADD_D =3D 0x00108000, OPC_SUB_W =3D 0x00110000, @@ -62,6 +63,7 @@ typedef enum { OPC_MOD_D =3D 0x00228000, OPC_DIV_DU =3D 0x00230000, OPC_MOD_DU =3D 0x00238000, + OPC_SLADD_D =3D 0x002c0000, OPC_SLLI_W =3D 0x00408000, OPC_SLLI_D =3D 0x00410000, OPC_SRLI_W =3D 0x00448000, @@ -619,6 +621,18 @@ encode_djk_insn(LoongArchInsn opc, TCGReg d, TCGReg j,= TCGReg k) return encode_djk_slots(opc, d, j, k); } =20 +static int32_t __attribute__((unused)) encode_djkua2_insn(LoongArchInsn op= c, + TCGReg d, TCGReg= j, + TCGReg k, + uint32_t ua2) +{ + tcg_debug_assert(d >=3D 0 && d <=3D 0x1f); + tcg_debug_assert(j >=3D 0 && j <=3D 0x1f); + tcg_debug_assert(k >=3D 0 && k <=3D 0x1f); + tcg_debug_assert(ua2 <=3D 0x3); + return encode_djka_slots(opc, d, j, k, ua2); +} + static int32_t __attribute__((unused)) encode_djsk12_insn(LoongArchInsn opc, TCGReg d, TCGReg j, int32_t sk12) { @@ -1426,6 +1440,13 @@ static void __attribute__((unused)) tcg_out_opc_sext= _b(TCGContext *s, TCGReg d, tcg_out32(s, encode_dj_insn(OPC_SEXT_B, d, j)); } =20 +/* Emits the `sladd.w d, j, k, ua2` instruction. */ +static void __attribute__((unused)) +tcg_out_opc_sladd_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k, uint32_t = ua2) +{ + tcg_out32(s, encode_djkua2_insn(OPC_SLADD_W, d, j, k, ua2)); +} + /* Emits the `add.w d, j, k` instruction. */ static void __attribute__((unused)) tcg_out_opc_add_w(TCGContext *s, TCGRe= g d, TCGReg j, TCGReg k) @@ -1692,6 +1713,13 @@ static void __attribute__((unused)) tcg_out_opc_mod_= du(TCGContext *s, TCGReg d, tcg_out32(s, encode_djk_insn(OPC_MOD_DU, d, j, k)); } =20 +/* Emits the `sladd.d d, j, k, ua2` instruction. */ +static void __attribute__((unused)) +tcg_out_opc_sladd_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k, uint32_t = ua2) +{ + tcg_out32(s, encode_djkua2_insn(OPC_SLADD_D, d, j, k, ua2)); +} + /* Emits the `slli.w d, j, uk5` instruction. */ static void __attribute__((unused)) tcg_out_opc_slli_w(TCGContext *s, TCGR= eg d, TCGReg j, uint32_t = uk5) --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787957181; cv=none; d=zohomail.com; s=zohoarc; b=RCdnQXA+tpGpRUKUKBicCswLNmscoYExkW9W9Ovc8cZqxEDxpZblfCvxMIdr76uhU4LKiwgV8H8M+semN4iu7aHEg+NeVt2iErX2+11+CMY22x16JDV+ZkG8p8u0Ssweey17YaUeOOJ9PAb+QyHyjFKmgjT6qgnYKuM2D13VE2E= ARC-Message-Signature: i=1; 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Fri, 28 Aug 2026 15:45:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 13/16] tcg/loongarch64: Implement INDEX_op_lea Date: Fri, 28 Aug 2026 15:44:48 -0700 Message-ID: <20260828224451.1564072-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957181601158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/loongarch64/tcg-target-has.h | 4 ++-- tcg/loongarch64/tcg-target.c.inc | 13 ++++++++++++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-= has.h index 31e6ea9632d..53b7ca40571 100644 --- a/tcg/loongarch64/tcg-target-has.h +++ b/tcg/loongarch64/tcg-target-has.h @@ -54,7 +54,7 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, uns= igned len) } #define TCG_TARGET_sextract_valid tcg_target_sextract_valid =20 -#define TCG_TARGET_lea_sh_valid(type, sh) 0 -#define TCG_TARGET_lea_imm_valid(type, imm) 0 +#define TCG_TARGET_lea_sh_valid(type, sh) ((sh) >=3D 1 && (sh) <= =3D 4) +#define TCG_TARGET_lea_imm_valid(type, imm) ((imm) =3D=3D 0) =20 #endif diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 17784d8bbe2..377cd9ec08d 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -2098,8 +2098,19 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static void tgen_lea(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + TCGReg a2, unsigned sh, tcg_target_long imm) +{ + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_opc_sladd_w(s, a0, a2, a1, sh - 1); + } else { + tcg_out_opc_sladd_d(s, a0, a2, a1, sh - 1); + } +} + static const TCGOutOpLea outop_lea =3D { - .base.static_constraint =3D C_NotImplemented, + .base.static_constraint =3D C_O1_I2(r, r, r), + .out =3D tgen_lea, }; =20 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787957168; cv=none; d=zohomail.com; s=zohoarc; b=ayz4+pRHrLPIAIKq9Ien0NGS4T9SwTCcg2I/12sdV86LES+brI8B2wFGwjBoWBa3Zc/XqUlJHsM4EWDhXxro1dRx1BycabDW72GOnRfjSbNPIFSLLmlf2xHQW/S3Vka6iW70wbsYQ1up9JgH4CTjMAMNgiou7p/A1hPQ2FEYpoA= ARC-Message-Signature: i=1; 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Fri, 28 Aug 2026 15:45:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 14/16] tcg/aarch64: Implement INDEX_op_lea Date: Fri, 28 Aug 2026 15:44:49 -0700 Message-ID: <20260828224451.1564072-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957171621154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/aarch64/tcg-target-has.h | 5 +++-- tcg/aarch64/tcg-target.c.inc | 9 ++++++++- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h index 86672b2eab4..6327c5215a2 100644 --- a/tcg/aarch64/tcg-target-has.h +++ b/tcg/aarch64/tcg-target-has.h @@ -57,7 +57,8 @@ #define TCG_TARGET_sextract_valid(type, ofs, len) 1 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 =20 -#define TCG_TARGET_lea_sh_valid(type, sh) 0 -#define TCG_TARGET_lea_imm_valid(type, imm) 0 +#define TCG_TARGET_lea_sh_valid(type, sh) \ + ((sh) >=3D 0 && (sh) < tcg_type_size(type) * 8) +#define TCG_TARGET_lea_imm_valid(type, imm) ((imm) =3D=3D 0) =20 #endif diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 76adb2256f9..6836c0dd94f 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -3081,8 +3081,15 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static void tgen_lea(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + TCGReg a2, unsigned sh, tcg_target_long imm) +{ + tcg_out_insn(s, addsub_realshift, ADD_LSL, type, a0, a1, a2, sh); +} + static const TCGOutOpLea outop_lea =3D { - .base.static_constraint =3D C_NotImplemented, + .base.static_constraint =3D C_O1_I2(r, r, r), + .out =3D tgen_lea, }; =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787957169; cv=none; d=zohomail.com; s=zohoarc; b=cEg6VL/WWXd3wAb+CzpHTjt3iYsYgp9ynpTuXEr+px7fIAgPjL/kcqNDYUveRD42mSpzq6LLhm8rq3IPuRxxFAoiuCJgc3ofLrwFYbkMeYMxT5J48FB5UAZNpBEdvW+hx5Vr9b+0Lja9UY0xTXIwvZQ3Nl0MeqVgcB53x1xFgWA= ARC-Message-Signature: i=1; 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Fri, 28 Aug 2026 15:45:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 15/16] tcg/riscv64: Implement INDEX_op_lea Date: Fri, 28 Aug 2026 15:44:50 -0700 Message-ID: <20260828224451.1564072-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957171689158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/riscv64/tcg-target-has.h | 12 ++++++++++-- tcg/riscv64/tcg-target.c.inc | 16 +++++++++++++++- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/tcg/riscv64/tcg-target-has.h b/tcg/riscv64/tcg-target-has.h index 93f8baad09f..3cdeb5c3900 100644 --- a/tcg/riscv64/tcg-target-has.h +++ b/tcg/riscv64/tcg-target-has.h @@ -69,7 +69,15 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, un= signed len) =20 #define TCG_TARGET_deposit_valid(type, ofs, len) 0 =20 -#define TCG_TARGET_lea_sh_valid(type, sh) 0 -#define TCG_TARGET_lea_imm_valid(type, imm) 0 +/* + * The SH*ADD instructions only operate on full register width. + * To allow TCG_TYPE_I32, we'd need a subsequent extension, + * with the result no better than the separate shift+add insns. + */ +#define TCG_TARGET_lea_sh_valid(type, sh) \ + (cpuinfo & CPUINFO_ZBA && \ + (type) =3D=3D TCG_TYPE_REG && \ + (sh) >=3D 1 && (sh) <=3D 3) +#define TCG_TARGET_lea_imm_valid(type, imm) ((imm) =3D=3D 0) =20 #endif diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index df4c4a9789b..ba7aab9246c 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -224,6 +224,7 @@ typedef enum { =20 /* Zba: Bit manipulation extension, address generation */ OPC_ADD_UW =3D 0x0800003b, + OPC_SHxADD =3D 0x20000033, /* plus sh << 13 */ =20 /* Zbb: Bit manipulation extension, basic bit manipulation */ OPC_ANDN =3D 0x40007033, @@ -2725,8 +2726,21 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static void tgen_lea(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + TCGReg a2, unsigned sh, tcg_target_long imm) +{ + tcg_out32(s, encode_r(OPC_SHxADD, a0, a2, a1) | (sh << 13)); +} + +static TCGConstraintSetIndex cset_zba_rrr(TCGType type, unsigned flags) +{ + return cpuinfo & CPUINFO_ZBA ? C_O1_I2(r, r, r) : C_NotImplemented; +} + static const TCGOutOpLea outop_lea =3D { - .base.static_constraint =3D C_NotImplemented, + .base.static_constraint =3D C_Dynamic, + .base.dynamic_constraint =3D cset_zba_rrr, + .out =3D tgen_lea, }; =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, --=20 2.53.0 From nobody Sat Sep 26 21:37:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787957169; cv=none; d=zohomail.com; s=zohoarc; b=N9YPudPpKryEMGyG5bFgig8R5N0MqmAYsSqUChfiNtiQvOBmiyJIBys+U8RYfd2P2g8knn8rd0cdM9xioPtwtY5/zk4UsURuiICKkdaJETXWwDnNqwzfer15H8YZnudqzEiovMhbeAD4OHBjt6L/KugD6iVmYBPwR6xWc2/sUQs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787957169; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=yXJmpQg5IQ+bnTObTQiSFuhs75H1FKJyV3yjSgBcfNk=; b=A+ZxxBK28dklgftp2Ia7RlWb7vD9MsxBwXU1u+8fzGNyoheONAAYCXHaj3gTpZLlK7UlXog/JYjpQoo0OQXrG7mu8Jr70Sf8Ip3KEPi8e1qOkQQ9bhPmSCnKqRXg4kV7jH4LerRVU1s2LlTtcg8y2611CM6N9w3xpKPpL94FQIE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787957169073555.4606659514408; Fri, 28 Aug 2026 15:46:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x05Jw-0001DY-4E; Fri, 28 Aug 2026 18:45:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x05Ju-00019W-0b for qemu-devel@nongnu.org; Fri, 28 Aug 2026 18:45:10 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x05Js-0004Zl-EM for qemu-devel@nongnu.org; Fri, 28 Aug 2026 18:45:09 -0400 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-3969e82ff8fso1711736a91.0 for ; Fri, 28 Aug 2026 15:45:08 -0700 (PDT) Received: from stoup (71-212-39-143.tukw.qwest.net. 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Fri, 28 Aug 2026 15:45:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH 16/16] tcg/s390x: Implement INDEX_op_lea Date: Fri, 28 Aug 2026 15:44:51 -0700 Message-ID: <20260828224451.1564072-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828224451.1564072-1-richard.henderson@linaro.org> References: <20260828224451.1564072-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787957169990158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/s390x/tcg-target-has.h | 5 +++-- tcg/s390x/tcg-target.c.inc | 13 ++++++++++++- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h index 58e3afe5266..33a3b72318e 100644 --- a/tcg/s390x/tcg-target-has.h +++ b/tcg/s390x/tcg-target-has.h @@ -77,7 +77,8 @@ tcg_target_sextract_valid(TCGType type, unsigned ofs, uns= igned len) } #define TCG_TARGET_sextract_valid tcg_target_sextract_valid =20 -#define TCG_TARGET_lea_sh_valid(type, sh) 0 -#define TCG_TARGET_lea_imm_valid(type, imm) 0 +#define TCG_TARGET_lea_sh_valid(type, sh) ((sh) =3D=3D 0) +#define TCG_TARGET_lea_imm_valid(type, imm) \ + ((imm) >=3D -0x80000 && (imm) < 0x80000) =20 #endif diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 2fd7012d047..db3b2fc3c92 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -3187,8 +3187,19 @@ static const TCGOutOpStore outop_st =3D { .out_r =3D tcg_out_st, }; =20 +static void tgen_lea(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + TCGReg a2, unsigned sh, tcg_target_long imm) +{ + if (imm >=3D 0 && imm < 0x1000) { + tcg_out_insn(s, RX, LA, a0, a1, a2, imm); + } else { + tcg_out_insn(s, RXY, LAY, a0, a1, a2, imm); + } +} + static const TCGOutOpLea outop_lea =3D { - .base.static_constraint =3D C_NotImplemented, + .base.static_constraint =3D C_O1_I2(r, r, r), + .out =3D tgen_lea, }; =20 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, --=20 2.53.0