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Fri, 28 Aug 2026 23:13:29 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1787930010; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=7kYP1SmE4po1NHX60o1wn5jt4JN1ovNWLbqMRiHorT8=; b=DrO81/OmIeOjWZ3WZR4s/dYAbw8QZtElWxEUnZlf/gQ0cOpV+ymBDkWrak/LoMUqBfBNVl2ObCyyP0/jCaGyHyGmyapdWTi9AFaYoDOf63L6ql36YHdHfAe9J7dcJ0fs49xAGD38h1aeHdH/qrgJ+Z1GlSlMb+bCMwo9SjFFCm8= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R201e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037026112; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=19; SR=0; TI=SMTPD_---0X9md4xv_1787930008; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH v4 1/6] hw/riscv/virt: Add CXL support to the RISC-V virt machine Date: Fri, 28 Aug 2026 23:13:00 +0800 Message-ID: <20260828151317.815-2-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260828151317.815-1-cp0613@linux.alibaba.com> References: <20260828151317.815-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.131 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Enable CXL support on the RISC-V virt machine following the same approach used by the ARM virt machine: - Add PXB and ACPI_CXL Kconfig selections - Add CXLState and PCIBus pointer to RISCVVirtState - Register CXL machine properties via cxl_machine_init() - Create CXL host register region above the PCIe high MMIO region - Call cxl_hook_up_pxb_registers() and cxl_fmws_link_targets() at machine_done time - Map Fixed Memory Windows above the CXL host register region - Add ACPI0017 device in DSDT and build CEDT table in virt-acpi-build.c Signed-off-by: Chen Pei --- hw/riscv/Kconfig | 2 ++ hw/riscv/virt-acpi-build.c | 20 ++++++++++++++++++++ hw/riscv/virt.c | 37 +++++++++++++++++++++++++++++++++++++ include/hw/riscv/virt.h | 3 +++ 4 files changed, 62 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index de37c08cae..0ba3cd9e15 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -66,8 +66,10 @@ config RISCV_VIRT select VIRTIO_MMIO select FW_CFG_DMA select PLATFORM_BUS + select PXB select ACPI select ACPI_PCI + select ACPI_CXL =20 config SHAKTI_C bool diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 59c454f4f9..3188cdc5bf 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -29,12 +29,16 @@ #include "hw/acpi/aml-build.h" #include "hw/acpi/pci.h" #include "hw/acpi/utils.h" +#include "hw/acpi/cxl.h" #include "hw/intc/riscv_aclint.h" #include "hw/nvram/fw_cfg_acpi.h" #include "hw/pci-host/gpex.h" +#include "hw/pci/pci_bus.h" #include "hw/riscv/virt.h" #include "hw/riscv/numa.h" #include "hw/virtio/virtio-acpi.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "kvm/kvm_riscv.h" #include "migration/vmstate.h" #include "qapi/error.h" @@ -514,6 +518,17 @@ static void build_dsdt(GArray *table_data, acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + s->num_sources * 2); } =20 + if (s->cxl_devices_state.is_enabled) { + Aml *cxl_dev =3D aml_device("CXLM"); + aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + Aml *method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0x0B))); + aml_append(cxl_dev, method); + build_cxl_dsm_method(cxl_dev); + + aml_append(scope, cxl_dev); + } + aml_append(dsdt, scope); =20 /* copy AML table into ACPI tables blob and patch header there */ @@ -921,6 +936,11 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBui= ldTables *tables) s->oem_table_id); } =20 + if (s->cxl_devices_state.is_enabled) { + cxl_build_cedt(table_offsets, tables_blob, tables->linker, + s->oem_id, s->oem_table_id, &s->cxl_devices_state); + } + if (ms->numa_state->num_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, s); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 51bac47a91..e08c76af4d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -55,6 +55,8 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "hw/acpi/aml-build.h" #include "qapi/qapi-visit-common.h" #include "hw/virtio/virtio-iommu.h" @@ -1101,9 +1103,33 @@ static inline DeviceState *gpex_pcie_init(MemoryRegi= on *sys_mem, } =20 GPEX_HOST(dev)->gpex_cfg.bus =3D PCI_HOST_BRIDGE(dev)->bus; + s->pci_bus =3D PCI_HOST_BRIDGE(dev)->bus; return dev; } =20 +static void cxl_host_state_init(RISCVVirtState *s) +{ + MemoryRegion *sysmem =3D get_system_memory(); + MemoryRegion *mr =3D &s->cxl_devices_state.host_mr; + hwaddr base; + + if (!s->cxl_devices_state.is_enabled) { + return; + } + + base =3D virt_high_pcie_memmap.base + virt_high_pcie_memmap.size; + base =3D ROUND_UP(base, 64 * KiB); + + memory_region_init(mr, OBJECT(s), "cxl_host_reg", 64 * KiB * 16); + memory_region_add_subregion(sysmem, base, mr); + + /* Map the Fixed Memory Windows above the CXL host register region. */ + base +=3D memory_region_size(mr); + base =3D ROUND_UP(base, 256 * MiB); + cxl_fmws_set_memmap(base, UINT64_MAX); + cxl_fmws_update_mmio(); +} + static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) { FWCfgState *fw_cfg; @@ -1205,6 +1231,13 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) machine_done); MachineState *machine =3D MACHINE(s); hwaddr start_addr =3D s->memmap[VIRT_DRAM].base; + + cxl_hook_up_pxb_registers(s->pci_bus, &s->cxl_devices_state, + &error_fatal); + + if (s->cxl_devices_state.is_enabled) { + cxl_fmws_link_targets(&error_fatal); + } hwaddr firmware_end_addr; vaddr kernel_start_addr; const char *firmware_name =3D riscv_default_firmware_name(&s->soc[0]); @@ -1451,6 +1484,8 @@ static void virt_machine_init(MachineState *machine) ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.siz= e); } =20 + cxl_host_state_init(s); + /* register system main memory (actual RAM) */ memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base, machine->ram); @@ -1558,6 +1593,8 @@ static void virt_machine_instance_init(Object *obj) s->acpi =3D ON_OFF_AUTO_AUTO; s->iommu_sys =3D ON_OFF_AUTO_AUTO; s->num_sources =3D VIRT_IRQCHIP_NUM_SOURCES; + + cxl_machine_init(obj, &s->cxl_devices_state); } =20 static char *virt_get_aia_guests(Object *obj, Error **errp) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 36a2def410..4cf930ab9f 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -24,6 +24,7 @@ #include "hw/core/sysbus.h" #include "hw/block/flash.h" #include "hw/intc/riscv_imsic.h" +#include "hw/cxl/cxl.h" =20 #define VIRT_CPUS_MAX_BITS 9 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) @@ -65,6 +66,8 @@ struct RISCVVirtState { OnOffAuto iommu_sys; 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RN=20; SR=0; TI=SMTPD_---0X9md4yK_1787930010; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, Sunil V L Subject: [PATCH v4 2/6] hw/riscv/virt-acpi-build: Add _DEP to ACPI0017 for CXL host bridge dependency Date: Fri, 28 Aug 2026 23:13:01 +0800 Message-ID: <20260828151317.815-3-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260828151317.815-1-cp0613@linux.alibaba.com> References: <20260828151317.815-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.124 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" On RISC-V QEMU virt platform with CXL enabled, the probe ordering of acpi_pci_root (ACPI0016) and cxl_acpi (ACPI0017) is not guaranteed. If cxl_acpi probes before acpi_pci_root has attached the CXL host bridges, the CXL port topology will be incomplete because to_cxl_host_bridge() silently skips devices whose PCI root is not yet ready. Add a _DEP object to the ACPI0017 device in the DSDT, declaring its dependency on the ACPI0016 CXL host bridge devices. This tells the OS to defer ACPI0017 enumeration until all ACPI0016 devices have been attached by acpi_pci_root. This pairs with kernel commit 3a59c3b772e5 ("ACPI: PCI: Clear _DEP dependencies after PCI root bridge attach"), which calls acpi_dev_clear_dependencies() in acpi_pci_root_add(). Note on kernel compatibility: this is a "new QEMU feature requires a sufficiently new kernel" situation. Kernels that process _DEP but lack the acpi_dev_clear_dependencies() call will leave the CXLM device deferred, so CXL memory is unusable there; kernels old enough to ignore _DEP entirely behave exactly as before this change. In neither case is existing (non-CXL) PCIe affected. The resulting DSDT fragment (iasl -d output) for a single CXL host bridge at bus 0x0C looks like: Device (CXLM) { Name (_HID, "ACPI0017") Name (_DEP, Package (0x01) { \_SB.PC0C }) Method (_STA, 0, NotSerialized) { Return (0x0B) } ... } Reviewed-by: Sunil V L Signed-off-by: Chen Pei --- hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 3188cdc5bf..56292f04a7 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -521,6 +521,38 @@ static void build_dsdt(GArray *table_data, if (s->cxl_devices_state.is_enabled) { Aml *cxl_dev =3D aml_device("CXLM"); aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + + /* + * Declare a _DEP on every ACPI0016 CXL host bridge so the OS + * defers ACPI0017 enumeration until acpi_pci_root has attached + * the CXL host bridges. Without this, cxl_acpi may probe before + * to_cxl_host_bridge() can resolve the PCI root and the CXL + * port topology comes up empty. + */ + if (s->pci_bus) { + PCIBus *bus; + uint32_t num_cxl_hbs =3D 0; + + QLIST_FOREACH(bus, &s->pci_bus->child, sibling) { + if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) { + num_cxl_hbs++; + } + } + + if (num_cxl_hbs > 0) { + Aml *dep_pkg =3D aml_package(num_cxl_hbs); + + QLIST_FOREACH(bus, &s->pci_bus->child, sibling) { + if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) { + aml_append(dep_pkg, + aml_name("\\_SB.PC%.02X", + pci_bus_num(bus))); + } + } + aml_append(cxl_dev, aml_name_decl("_DEP", dep_pkg)); + } + } + Aml *method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); aml_append(method, aml_return(aml_int(0x0B))); aml_append(cxl_dev, method); --=20 2.50.1 From nobody Sun Sep 27 23:08:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1787930013; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=2BGAPnrAKlRIHgW6wkUwX/JJgCvR6yPAhtJ/W6cGgpg=; b=eA8ADPRy4gC6Xxw6GlB/SxkakXwRmw2SajAgGtoyRMIhTpwVMDCyd+jYQBSe2S/vRMBJChP2AvJzMEwsVk1ijMW4a5jPJQhWyIzqmGQ0jVOVjyat9IKCWGMfT6u1YYleLTp39iCLLnfCe6knTTey6APaRtyVHAELoAXz6DGveC4= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R171e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam011083073210; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=19; SR=0; TI=SMTPD_---0X9md4yW_1787930011; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH v4 3/6] hw/riscv/virt: Advertise the CXL host bridge to firmware via extra-pci-roots Date: Fri, 28 Aug 2026 23:13:02 +0800 Message-ID: <20260828151317.815-4-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260828151317.815-1-cp0613@linux.alibaba.com> References: <20260828151317.815-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.118 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The pxb-cxl expander bridge presents as a class 0x0600 host bridge with a type-0 header, so EDK2's PciBusDxe never recurses into it and never assigns the CXL root port a memory window or bus numbers. As a result build_crs() produces an empty _CRS for the ACPI0016 host bridge and the CXL devices behind it are not enumerated by the OS. Advertise the pxb-cxl expander root buses to firmware via the etc/extra-pci-roots fw_cfg file, the same way arm/virt and x86 do, by calling pci_bus_add_fw_cfg_extra_pci_roots() from virt_machine_done(). EDK2's PciBusDxe then enumerates behind the CXL host bridge and assigns the root-port window and bus numbers. The ACPI tables are rebuilt when the guest reads them (after that firmware enumeration), so build_crs() then emits a correct _CRS for the ACPI0016 host bridge. This approach also scales to multiple pxb-cxl host bridges (each gets its own window from the shared aperture) and lets firmware size the window to what is actually behind the bridge, rather than reserving a fixed carve-out. Verified by booting an RVA22 guest: the CXL root port and Type3 device enumerate, and 'cxl enable-memdev' / 'cxl create-region' / 'daxctl online-memory' bring the CXL memory online as system RAM. Signed-off-by: Chen Pei Reviewed-by: Junjie Cao Tested-by: Junjie Cao --- v4: - Replaces the v3 QEMU-side firmware simulation with pci_bus_add_fw_cfg_extra_pci_roots(), advertising the pxb-cxl expander root buses to firmware via etc/extra-pci-roots. EDK2 then enumerates behind the CXL host bridge and assigns the root-port window and bus numbers, and build_crs() emits a correct _CRS. This scales to multiple pxb-cxl and lets firmware size the window. hw/riscv/virt.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e08c76af4d..67f512cde1 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1237,6 +1237,14 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) =20 if (s->cxl_devices_state.is_enabled) { cxl_fmws_link_targets(&error_fatal); + + /* + * Let firmware enumerate the pxb-cxl root buses and assign bus + * numbers and windows; build_crs() builds the ACPI0016 _CRS from + * the resulting state when the guest reads the ACPI tables. + */ + pci_bus_add_fw_cfg_extra_pci_roots(s->fw_cfg, s->pci_bus, + &error_abort); } hwaddr firmware_end_addr; vaddr kernel_start_addr; --=20 2.50.1 From nobody Sun Sep 27 23:08:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1787930016; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=UQbJXq6uKESS/KbL945Kj00dHUab8gFhyfT/6+OH6JE=; b=W0VDK9vscAktUca4iH68Tnb34gSgkw6ODLqOY3QGGdDI248NJZOmL5GXlmL1Ludbu357llHH2c/OB4vBxt0291WfC8e3QvctyjBoMYBhec8+/V/ZzmsWTYoOAm7lmXyCO/wpWGiqxZThD6gBJ3q6ltYVnjiRi5ZFitXKgadb3BQ= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R871e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045098064; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=19; SR=0; TI=SMTPD_---0X9md4yg_1787930012; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH v4 4/6] tests/qtest: Prepare golden files for the RISC-V CXL ACPI test Date: Fri, 28 Aug 2026 23:13:03 +0800 Message-ID: <20260828151317.815-5-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260828151317.815-1-cp0613@linux.alibaba.com> References: <20260828151317.815-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.101 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Add empty DSDT.cxl and CEDT.cxl golden files and list them in bios-tables-test-allowed-diff.h, in preparation for the RISC-V CXL bios-tables test added in the following patch. The populated golden master binaries are committed separately in a final patch, following the bios-tables-test update process. Signed-off-by: Chen Pei Reviewed-by: Junjie Cao --- v4: - Split the CXL bios-tables test into the staged flow documented in bios-tables-test.c: empty golden files + allowed-diff.h, then the test code, then the populated golden master binaries with an emptied allowed-diff.h in a final patch (matching how the riscv64 goldens were originally added upstream). tests/data/acpi/riscv64/virt/CEDT.cxl | 0 tests/data/acpi/riscv64/virt/DSDT.cxl | 0 tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 3 files changed, 2 insertions(+) create mode 100644 tests/data/acpi/riscv64/virt/CEDT.cxl create mode 100644 tests/data/acpi/riscv64/virt/DSDT.cxl diff --git a/tests/data/acpi/riscv64/virt/CEDT.cxl b/tests/data/acpi/riscv6= 4/virt/CEDT.cxl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/riscv64/virt/DSDT.cxl b/tests/data/acpi/riscv6= 4/virt/DSDT.cxl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..c05fb697a5 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"riscv64/virt/DSDT.cxl", +"riscv64/virt/CEDT.cxl", --=20 2.50.1 From nobody Sun Sep 27 23:08:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 28 Aug 2026 23:13:34 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1787930015; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=h9pooA5aBA96lNnW7CUv7B9YADSvf/FDW4PI23kWFUI=; b=NEGBnXVP517fiakY5XKv3Lbeb8UCBsyCOKIwONfpXmwYeXKhzVOWMTrEeplSjYTGPaDGGFqyWeXx6dtkFg8mDk0+pmrAiy04cihA14AW9BuCt1epWtwun6aLYng7cC4vbBGB8bFRysdbroR7hx7pnpvUtRg/AeUDF216hZ1V6MA= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R551e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037026112; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=19; SR=0; TI=SMTPD_---0X9md4yo_1787930013; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH v4 5/6] tests/qtest: Add RISC-V ACPI bios tables test for CXL Date: Fri, 28 Aug 2026 23:13:04 +0800 Message-ID: <20260828151317.815-6-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260828151317.815-1-cp0613@linux.alibaba.com> References: <20260828151317.815-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.97 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Add test_acpi_riscv64_virt_tcg_cxl() to verify that enabling CXL on the RISC-V virt machine produces correct ACPI tables, including the ACPI0017 CXLM device with _DEP in the DSDT and the CEDT table. The test boots with cxl=3Don, one pxb-cxl bus (bus_nr=3D12), a CXL root port, a cxl-type3 device and a fixed memory window, mirroring the existing x86 q35 CXL test pattern. Since pxb-cxl is a root bus, using -cdrom causes QEMU to auto-plug the cdrom drive into pxb-cxl, triggering "Only PCI/PCIe bridges can be plugged into pxb-cxl". The ISO is instead attached explicitly via a virtio-scsi-pci controller on pcie.0, following the same approach as test_acpi_aarch64_virt_tcg_pxb(). Acked-by: Alistair Francis Signed-off-by: Chen Pei Reviewed-by: Junjie Cao Tested-by: Junjie Cao --- tests/qtest/bios-tables-test.c | 54 ++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 5cc526510a..d2b18d8ecb 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -2214,6 +2214,56 @@ static void test_acpi_riscv64_virt_tcg(void) free_test_data(&data); } =20 +#ifdef CONFIG_POSIX +static void test_acpi_riscv64_virt_tcg_cxl(void) +{ + gchar *tmp_path =3D g_dir_make_tmp("qemu-test-cxl.XXXXXX", NULL); + gchar *params; + + test_data data =3D { + .machine =3D "virt", + .arch =3D "riscv64", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-riscv-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-riscv-vars.fd", + .ram_start =3D 0x80000000ULL, + .scan_len =3D 128ULL * MiB, + .variant =3D ".cxl", + }; + + /* + * While using -cdrom, the cdrom would auto-plug into pxb-cxl because + * its bus is also a root bus, triggering "Only PCI/PCIe bridges can be + * plugged into pxb-cxl". Attach the ISO explicitly to a scsi control= ler + * on pcie.0 instead, following the same pattern as + * test_acpi_aarch64_virt_tcg_pxb(). + */ + params =3D g_strdup_printf("-cpu rva22s64" + " -machine cxl=3Don" + " -device pcie-root-port,chassis=3D1,id=3Dpci= .1,bus=3Dpcie.0" + " -device virtio-scsi-pci,id=3Dscsi0,bus=3Dpc= i.1" + " -drive file=3Dtests/data/uefi-boot-images/" + "bios-tables-test.riscv64.iso.qcow2," + "if=3Dnone,media=3Dcdrom,id=3Ddrive-scsi0-0-0= -1,readonly=3Don" + " -device scsi-cd,bus=3Dscsi0.0,scsi-id=3D0," + "drive=3Ddrive-scsi0-0-0-1,id=3Dscsi0-0-0-1,b= ootindex=3D1" + " -object memory-backend-file,id=3Dcxl-mem1,m= em-path=3D%s,size=3D256M" + " -object memory-backend-file,id=3Dlsa1,mem-p= ath=3D%s,size=3D256M" + " -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id= =3Dcxl.1" + " -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Drp= 1,chassis=3D0,slot=3D2" + " -device cxl-type3,bus=3Drp1,persistent-memd= ev=3Dcxl-mem1,lsa=3Dlsa1" + " -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.si= ze=3D4G," + "cxl-fmw.0.interleave-granularity=3D8k", + tmp_path, tmp_path); + test_acpi_one(params, &data); + + g_free(params); + g_assert(g_rmdir(tmp_path) =3D=3D 0); + g_free(tmp_path); + free_test_data(&data); +} +#endif /* CONFIG_POSIX */ + static void test_acpi_aarch64_virt_tcg(void) { test_data data =3D { @@ -2963,6 +3013,10 @@ int main(int argc, char *argv[]) test_acpi_riscv64_virt_tcg_numamem); qtest_add_func("acpi/virt/acpispcr", test_acpi_riscv64_virt_tcg_acpi_spcr); +#ifdef CONFIG_POSIX + qtest_add_func("acpi/virt/cxl", + test_acpi_riscv64_virt_tcg_cxl); +#endif } } else if (strcmp(arch, "loongarch64") =3D=3D 0) { if (has_tcg && qtest_has_machine("virt")) { --=20 2.50.1 From nobody Sun Sep 27 23:08:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1787930104; cv=none; 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b=c65ChS6niY/kKNbphyU/uUp3P+HEgBt+yq7rEXe01S5UparQ2ZHYd9/ggMxf/Ud26HcsNCbq3ZqBOfT8Q51ak0my+9duOOytNrKgUuEbuHT3x4Z3Tbl8kDoWhCFqrP4nzGYN8F+mhxbJP9Ds+NKTelLmmkjm2W9ll2INOx61dZk= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R841e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033032089153; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=19; SR=0; TI=SMTPD_---0X9md4z4_1787930015; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH v4 6/6] tests/qtest: Update RISC-V CXL ACPI golden master binaries Date: Fri, 28 Aug 2026 23:13:05 +0800 Message-ID: <20260828151317.815-7-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260828151317.815-1-cp0613@linux.alibaba.com> References: <20260828151317.815-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.131 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Populate the DSDT.cxl and CEDT.cxl golden master binaries for the RISC-V CXL bios-tables test and empty bios-tables-test-allowed-diff.h, following the bios-tables-test update process. The expected AML added by this series is: DSDT.cxl: Device (PC0C) // ACPI0016 CXL host bridge (pxb-cxl, bus 0x0C) Name (_CRS, ResourceTemplate () { DWordMemory (... 0x40400000 .. 0x405FFFFF ...) // 32-bit MMIO QWordMemory (... 0x400100000 .. 0x40020FFFF ...) // 64-bit MMIO WordBusNumber (... 0x000C .. 0x000D ...) }) Method (_OSC, ...) // PCI host bridge + CXL UUIDs Device (CXLM) // ACPI0017 CXL memory controller Name (_HID, "ACPI0017") Name (_DEP, Package () { \_SB.PC0C }) Method (_STA, ...) / Method (_DSM, ...) CEDT.cxl: CHBS : CXL Host Bridge Structure, Register base 0x800000000 CFMWS: CXL Fixed Memory Window, base 0x810000000, size 4G Signed-off-by: Chen Pei --- tests/data/acpi/riscv64/virt/CEDT.cxl | Bin 0 -> 108 bytes tests/data/acpi/riscv64/virt/DSDT.cxl | Bin 0 -> 6331 bytes tests/qtest/bios-tables-test-allowed-diff.h | 2 -- 3 files changed, 2 deletions(-) diff --git a/tests/data/acpi/riscv64/virt/CEDT.cxl b/tests/data/acpi/riscv6= 4/virt/CEDT.cxl index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..81d746dfb09ccb147e26bb64060= 404ca3191d097 100644 GIT binary patch literal 108 zc-nJzbqUE~U|?VjaPoKd2v%^42yj*a0!E-1hz+6{7!(+IKx!BefCEf2LP-snumA^? O0aMEg#QH!C(hmS*@&^F` literal 0 Hc-jL100001 diff --git a/tests/data/acpi/riscv64/virt/DSDT.cxl b/tests/data/acpi/riscv6= 4/virt/DSDT.cxl index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c42c37a6a25998a70c42098b500= a5e7163ae1513 100644 GIT binary patch literal 6331 zc-pO*%WoS+9LHzv^&{)GV>{0K-B#j&ioTAUrk5(V*J*1MC&rsTL@L=3DLO4T-~q`X8y zh^mJ|BZO#!dg0=3DVsQd$*pa>+maI1t62qZZ5!VwM#3CYat+RlE{t<*zYX?DgtzwgXv zyRkpnle&&K(v0UT#6U0 zYFQ5EM6`aoT#{|2u#$SlI5c!f6ROPn+B;soaqPrd>x3Kh!b0V=3D44RP<_DaEsMeCMT z&}3V)Qz;{HvqzODlX92hnyj2FTb(V`Z0n4y%yzeM(k_ZUg~Ak~;S^dCYq`Rexo)MZ z88HUiHA&Up3JXm$oK>Usl3hyA1X6uQGV@F8*DtSpSlPP$;L~rO|4d7dYU!aseC_2| z);11bcy;~i8|zoruE}Nd$K;{~{YQYtqPjqjNs;o^IF=3Dzf%`!2K| zdoL5N+cjHjM`eAYG>)3~iJIo9=3DT+2mX+>d|b6) zc|U!!M^#0+lr{rq;h_;#jm#|;mkiTg#Z(_EwbZaNuqoaWFUg;dl2{jSic4Zm9!2+u zuv%N`TYSy9o{s6UR!gY=3D7UA|abzMc;RDC0$u1seTRA?d{*G)M~2zOq4q`4Cl?#QXj z?GA%(zB4!ARL*oqnrCXjt;Fsy=3DvgJ`ROY%P%`-LVR%UmHLC-3>5S|_ALi0@3MTfF8 z^m2xXGen#r<_s}sm^j148D`Efb4G|WLYxuij4)@EIHSZFWzHyb_7Gh%-T)3Fb^NXD@N~5@#=3DS z_A+OZIFrPgWX>dWrie2|oGIo^F=3Dv`M)5Mu(&NOrO5oaH9_AzH4b7qJ$L!24r%rIv^ zarP5uKXdjo=3DKygI5a$4M4lw5+aSjsaAaf2f=3DMZrY5$6zd4l(C2aSjvbFmnzw=3DLm6* z5a$SUjxgsaagGw_D07Z7=3DNNI05$70ljxpyragGz`ICG9O=3DLB(15a$GQPB7;raZVEF zBy&!7INdMqrI7LB`|@@$+rppEw_5eQ+n*9!&+eWPj%6z^Y_+DG(Jpz;ygw zenyFak^}p6wJM_4N^Q~UTTb5+nZ-nX*|zkp4PlkeW}8dq?d^+7)mJOO<^Gu*%ilfw zdg0sSKVNX)js5i3#Y^9BRlYv{$w+ek$N#oA3|-dE$YWFhwxtST%~mYz5ze=3DxR?fGzGEZk3@=3DWVJx8IzX zXEZa|(MtK{tX@I&IC`&&infaO?orXC)9#%;-Jb1y!FXPOwA_cKnZ*bTX~^G4pJ<*F zPidZxXWlbO5HpACCA*?Gr`l++u|u(y2cYloqOKQ#=3D2h`a6PpikIn85BtTA v5zEY}{hCd<`@R3~`rp5Qel>sp@)u@o`J-BQzgjb~eOcQ{M*~_~m$LIeRS7jr literal 0 Hc-jL100001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index c05fb697a5..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,3 +1 @@ /* List of comma-separated changed AML files to ignore */ -"riscv64/virt/DSDT.cxl", -"riscv64/virt/CEDT.cxl", --=20 2.50.1