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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897273612154100 Content-Type: text/plain; charset="utf-8" From: Amit Machhiwal Sync linux headers from Linux kernel commit 1200d84f4c0a ("Merge tag 'powerpc-7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/gi= t/powerpc/linux"). This picks up the new KVM_CAP_PPC_COMPAT_CAPS capability for powerpc, which introduces: - struct kvm_ppc_compat_caps: reports processor compatibility modes supported by the host (POWER9, POWER10, POWER11) - KVM_PPC_GET_COMPAT_CAPS ioctl (KVMIO 0xb8) - KVM_CAP_PPC_COMPAT_CAPS (cap #250) in linux/kvm.h The sync is needed to get the corresponding Qemu series[1] merged. [1]: https://lore.kernel.org/all/20260812170854.58709-1-amachhiw@linux.ibm.= com/ Signed-off-by: Amit Machhiwal Link: https://lore.kernel.org/qemu-devel/20260819045924.11732-1-amachhiw@li= nux.ibm.com Signed-off-by: Harsh Prateek Bora --- include/standard-headers/linux/const.h | 4 ++-- linux-headers/asm-arm64/unistd_64.h | 1 + linux-headers/asm-generic/unistd.h | 6 +++++- linux-headers/asm-loongarch/unistd_64.h | 1 + linux-headers/asm-mips/unistd_n32.h | 1 + linux-headers/asm-mips/unistd_n64.h | 1 + linux-headers/asm-mips/unistd_o32.h | 1 + linux-headers/asm-powerpc/kvm.h | 18 ++++++++++++++++++ linux-headers/asm-powerpc/unistd_32.h | 1 + linux-headers/asm-powerpc/unistd_64.h | 1 + linux-headers/asm-riscv/unistd_32.h | 1 + linux-headers/asm-riscv/unistd_64.h | 1 + linux-headers/asm-s390/unistd_64.h | 1 + linux-headers/asm-x86/unistd_32.h | 1 + linux-headers/asm-x86/unistd_64.h | 1 + linux-headers/asm-x86/unistd_x32.h | 1 + linux-headers/linux/const.h | 4 ++-- linux-headers/linux/kvm.h | 3 +++ 18 files changed, 43 insertions(+), 5 deletions(-) diff --git a/include/standard-headers/linux/const.h b/include/standard-head= ers/linux/const.h index c6a9d0c983..92635cec4a 100644 --- a/include/standard-headers/linux/const.h +++ b/include/standard-headers/linux/const.h @@ -13,7 +13,7 @@ * leave it unchanged in asm. */ =20 -#ifdef __ASSEMBLY__ +#ifdef __ASSEMBLER__ #define _AC(X,Y) X #define _AT(T,X) X #else @@ -28,7 +28,7 @@ #define _BITUL(x) (_UL(1) << (x)) #define _BITULL(x) (_ULL(1) << (x)) =20 -#if !defined(__ASSEMBLY__) +#if !defined(__ASSEMBLER__) /* * Missing __asm__ support * diff --git a/linux-headers/asm-arm64/unistd_64.h b/linux-headers/asm-arm64/= unistd_64.h index 70b3754a42..4329a2ad54 100644 --- a/linux-headers/asm-arm64/unistd_64.h +++ b/linux-headers/asm-arm64/unistd_64.h @@ -328,6 +328,7 @@ #define __NR_file_setattr 469 #define __NR_listns 470 #define __NR_rseq_slice_yield 471 +#define __NR_fchroot 472 =20 =20 #endif /* _ASM_UNISTD_64_H */ diff --git a/linux-headers/asm-generic/unistd.h b/linux-headers/asm-generic= /unistd.h index a627acc8fb..5b7e77a7c7 100644 --- a/linux-headers/asm-generic/unistd.h +++ b/linux-headers/asm-generic/unistd.h @@ -863,8 +863,12 @@ __SYSCALL(__NR_listns, sys_listns) #define __NR_rseq_slice_yield 471 __SYSCALL(__NR_rseq_slice_yield, sys_rseq_slice_yield) =20 +/* fs/open.c */ +#define __NR_fchroot 472 +__SYSCALL(__NR_fchroot, sys_fchroot) + #undef __NR_syscalls -#define __NR_syscalls 472 +#define __NR_syscalls 473 =20 /* * 32 bit systems traditionally used different diff --git a/linux-headers/asm-loongarch/unistd_64.h b/linux-headers/asm-lo= ongarch/unistd_64.h index 3a29d86e1d..b525f2d7b8 100644 --- a/linux-headers/asm-loongarch/unistd_64.h +++ b/linux-headers/asm-loongarch/unistd_64.h @@ -325,6 +325,7 @@ #define __NR_file_setattr 469 #define __NR_listns 470 #define __NR_rseq_slice_yield 471 +#define __NR_fchroot 472 =20 =20 #endif /* _ASM_UNISTD_64_H */ diff --git a/linux-headers/asm-mips/unistd_n32.h b/linux-headers/asm-mips/u= nistd_n32.h index 5fa1ee0cb4..f883da76c9 100644 --- a/linux-headers/asm-mips/unistd_n32.h +++ b/linux-headers/asm-mips/unistd_n32.h @@ -400,5 +400,6 @@ #define __NR_file_setattr (__NR_Linux + 469) #define __NR_listns (__NR_Linux + 470) #define __NR_rseq_slice_yield (__NR_Linux + 471) +#define __NR_fchroot (__NR_Linux + 472) =20 #endif /* _ASM_UNISTD_N32_H */ diff --git a/linux-headers/asm-mips/unistd_n64.h b/linux-headers/asm-mips/u= nistd_n64.h index e1f873d83a..59837eb866 100644 --- a/linux-headers/asm-mips/unistd_n64.h +++ b/linux-headers/asm-mips/unistd_n64.h @@ -376,5 +376,6 @@ #define __NR_file_setattr (__NR_Linux + 469) #define __NR_listns (__NR_Linux + 470) #define __NR_rseq_slice_yield (__NR_Linux + 471) +#define __NR_fchroot (__NR_Linux + 472) =20 #endif /* _ASM_UNISTD_N64_H */ diff --git a/linux-headers/asm-mips/unistd_o32.h b/linux-headers/asm-mips/u= nistd_o32.h index 8207e9ca4f..485872076e 100644 --- a/linux-headers/asm-mips/unistd_o32.h +++ b/linux-headers/asm-mips/unistd_o32.h @@ -446,5 +446,6 @@ #define __NR_file_setattr (__NR_Linux + 469) #define __NR_listns (__NR_Linux + 470) #define __NR_rseq_slice_yield (__NR_Linux + 471) +#define __NR_fchroot (__NR_Linux + 472) =20 #endif /* _ASM_UNISTD_O32_H */ diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kv= m.h index 077c5437f5..913a64b901 100644 --- a/linux-headers/asm-powerpc/kvm.h +++ b/linux-headers/asm-powerpc/kvm.h @@ -437,6 +437,24 @@ struct kvm_ppc_cpu_char { __u64 behaviour_mask; /* valid bits in behaviour */ }; =20 +/* For KVM_PPC_GET_COMPAT_CAPS */ +struct kvm_ppc_compat_caps { + __u64 size; /* Size of this structure */ + __u64 flags; /* Reserved for future use */ + __u64 compat_capabilities; /* Capabilities supported by the host */ +}; +#define KVM_PPC_COMPAT_CAPS_SIZE_VER0 24 /* sizeof first published struct = */ + +/* + * Capability bits for compat_capabilities field in kvm_ppc_compat_caps. + * These bits indicate which processor compatibility modes are supported. + */ +#define KVM_PPC_COMPAT_CAP_POWER9 (1ULL << 62) +#define KVM_PPC_COMPAT_CAP_POWER10 (1ULL << 61) +#define KVM_PPC_COMPAT_CAP_POWER11 (1ULL << 60) +#define KVM_PPC_COMPAT_BITMASK (KVM_PPC_COMPAT_CAP_POWER9 | \ + KVM_PPC_COMPAT_CAP_POWER10 | \ + KVM_PPC_COMPAT_CAP_POWER11) /* * Values for character and character_mask. * These are identical to the values used by H_GET_CPU_CHARACTERISTICS. diff --git a/linux-headers/asm-powerpc/unistd_32.h b/linux-headers/asm-powe= rpc/unistd_32.h index 1f63360120..2677c54903 100644 --- a/linux-headers/asm-powerpc/unistd_32.h +++ b/linux-headers/asm-powerpc/unistd_32.h @@ -453,6 +453,7 @@ #define __NR_file_setattr 469 #define __NR_listns 470 #define __NR_rseq_slice_yield 471 +#define __NR_fchroot 472 =20 =20 #endif /* _ASM_UNISTD_32_H */ diff --git a/linux-headers/asm-powerpc/unistd_64.h b/linux-headers/asm-powe= rpc/unistd_64.h index 87439c53c1..6fc19ccccd 100644 --- a/linux-headers/asm-powerpc/unistd_64.h +++ b/linux-headers/asm-powerpc/unistd_64.h @@ -425,6 +425,7 @@ #define __NR_file_setattr 469 #define __NR_listns 470 #define __NR_rseq_slice_yield 471 +#define __NR_fchroot 472 =20 =20 #endif /* _ASM_UNISTD_64_H */ diff --git a/linux-headers/asm-riscv/unistd_32.h b/linux-headers/asm-riscv/= unistd_32.h index 828f3c2b9d..1039bdc6cf 100644 --- a/linux-headers/asm-riscv/unistd_32.h +++ b/linux-headers/asm-riscv/unistd_32.h @@ -319,6 +319,7 @@ #define __NR_file_setattr 469 #define __NR_listns 470 #define __NR_rseq_slice_yield 471 +#define __NR_fchroot 472 =20 =20 #endif /* _ASM_UNISTD_32_H */ diff --git a/linux-headers/asm-riscv/unistd_64.h b/linux-headers/asm-riscv/= unistd_64.h index 8fa59835a3..72040a5498 100644 --- a/linux-headers/asm-riscv/unistd_64.h +++ b/linux-headers/asm-riscv/unistd_64.h @@ -329,6 +329,7 @@ #define __NR_file_setattr 469 #define __NR_listns 470 #define __NR_rseq_slice_yield 471 +#define __NR_fchroot 472 =20 =20 #endif /* _ASM_UNISTD_64_H */ diff --git a/linux-headers/asm-s390/unistd_64.h b/linux-headers/asm-s390/un= istd_64.h index 01f674c1bc..3d3747e3ca 100644 --- a/linux-headers/asm-s390/unistd_64.h +++ b/linux-headers/asm-s390/unistd_64.h @@ -391,6 +391,7 @@ #define __NR_file_setattr 469 #define __NR_listns 470 #define __NR_rseq_slice_yield 471 +#define __NR_fchroot 472 =20 =20 #endif /* _ASM_UNISTD_64_H */ diff --git a/linux-headers/asm-x86/unistd_32.h b/linux-headers/asm-x86/unis= td_32.h index e945468829..7f298247f8 100644 --- a/linux-headers/asm-x86/unistd_32.h +++ b/linux-headers/asm-x86/unistd_32.h @@ -462,6 +462,7 @@ #define __NR_file_setattr 469 #define __NR_listns 470 #define __NR_rseq_slice_yield 471 +#define __NR_fchroot 472 =20 =20 #endif /* _ASM_UNISTD_32_H */ diff --git a/linux-headers/asm-x86/unistd_64.h b/linux-headers/asm-x86/unis= td_64.h index 3c49b00ed1..fbddeb4bc3 100644 --- a/linux-headers/asm-x86/unistd_64.h +++ b/linux-headers/asm-x86/unistd_64.h @@ -386,6 +386,7 @@ #define __NR_file_setattr 469 #define __NR_listns 470 #define __NR_rseq_slice_yield 471 +#define __NR_fchroot 472 =20 =20 #endif /* _ASM_UNISTD_64_H */ diff --git a/linux-headers/asm-x86/unistd_x32.h b/linux-headers/asm-x86/uni= std_x32.h index bd2af9ad08..629770ed4b 100644 --- a/linux-headers/asm-x86/unistd_x32.h +++ b/linux-headers/asm-x86/unistd_x32.h @@ -339,6 +339,7 @@ #define __NR_file_setattr (__X32_SYSCALL_BIT + 469) #define __NR_listns (__X32_SYSCALL_BIT + 470) #define __NR_rseq_slice_yield (__X32_SYSCALL_BIT + 471) +#define __NR_fchroot (__X32_SYSCALL_BIT + 472) #define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512) #define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513) #define __NR_ioctl (__X32_SYSCALL_BIT + 514) diff --git a/linux-headers/linux/const.h b/linux-headers/linux/const.h index c6a9d0c983..92635cec4a 100644 --- a/linux-headers/linux/const.h +++ b/linux-headers/linux/const.h @@ -13,7 +13,7 @@ * leave it unchanged in asm. */ =20 -#ifdef __ASSEMBLY__ +#ifdef __ASSEMBLER__ #define _AC(X,Y) X #define _AT(T,X) X #else @@ -28,7 +28,7 @@ #define _BITUL(x) (_UL(1) << (x)) #define _BITULL(x) (_ULL(1) << (x)) =20 -#if !defined(__ASSEMBLY__) +#if !defined(__ASSEMBLER__) /* * Missing __asm__ support * diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index dd52e2a65b..aea4ab5c69 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -986,6 +986,7 @@ struct kvm_enable_cap { #define KVM_CAP_S390_KEYOP 247 #define KVM_CAP_S390_VSIE_ESAMODE 248 #define KVM_CAP_S390_HPAGE_2G 249 +#define KVM_CAP_PPC_COMPAT_CAPS 250 =20 struct kvm_irq_routing_irqchip { __u32 irqchip; @@ -1330,6 +1331,8 @@ struct kvm_s390_keyop { /* Available with KVM_CAP_COUNTER_OFFSET */ #define KVM_ARM_SET_COUNTER_OFFSET _IOW(KVMIO, 0xb5, struct kvm_arm_count= er_offset) #define KVM_ARM_GET_REG_WRITABLE_MASKS _IOR(KVMIO, 0xb6, struct reg_mask_= range) +/* Available with KVM_CAP_PPC_COMPAT_CAPS */ +#define KVM_PPC_GET_COMPAT_CAPS _IO(KVMIO, 0xb8) =20 /* ioctl for vm fd */ #define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device) --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897325; cv=none; d=zohomail.com; s=zohoarc; b=Ai1yNkiUiYu3ue6lxBn9S2qH2jcfXuabBsSjr0LtPYhD7PUv+qc14GEwtEdcs9SWCjtxx6upCk23DV9FUCvhFUDwq/eaWtBn3SRKNlZPqetTCWMJmXoW7mSJej4U6oIOaQQNHA5CAhUxaSMrkh/6KxW+VwNrSj3uJebEmtA9QKU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787897325; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=u+Ma1ynAQwemef+k6 VSAddALpVI9wmQW+ejGk1rywXE=; b=mnXH4El3wPYmG7XdskxnVacdb0VKzUF5+ 4ZC8FPpfjSK3gnsVlkaW1z6wQBAoJm5Zs9+SAjETtvYh8URtPQlGkiLRCo4oK6Uj IYbti9bm23oxdvbA92pgOGHdbHUEvCRRRCXYJEZjp/x2mx2Q9crErcStKS5Fxbhi pm28CkjESebfYbzUHw/CLopa3lUAr1ramkbzVkxcL6CrlssybV9T0rIUJNTq8ZDR ZQXc/MX2ds6/tA4sH2EXjz8sWa5UNC+YWt87bbS584ZjYmnvKuaassKcasCoFxmT cPJD/ffNoIiSDDEZldPZ2zsGlTv8kdFwmfwYm/fjP6Gd5fGEBjGZQ== From: Harsh Prateek Bora To: qemu-devel@nongnu.org Cc: Amit Machhiwal , Gautam Menghani , Anushree Mathur Subject: [PULL 02/41] target/ppc/kvm: Add support for querying host compatibility mode Date: Fri, 28 Aug 2026 11:36:37 +0530 Message-ID: <20260828060716.91672-3-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com> References: <20260828060716.91672-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=TfimcxQh c=1 sm=1 tr=0 ts=6a9125a7 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=Sv0fKeRqtYgA:10 a=f7IdgyKtn90A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=R_9d5M2Ok3QZz6TfjUMA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX/+RJsI62W/+N zsfhhKD6RcWk6IeqReCZKFfpb9C90Id4dwEoVZ5wGtsATkERF8QzGy77fePr0TEe/fg678R+fF6 V0js9QEh+HlOuQpIwI98F8xlkXmEMxE= X-Proofpoint-GUID: dzSvSncGLMAZtbrVJlcx-eQAoEtsBwil X-Proofpoint-ORIG-GUID: dzSvSncGLMAZtbrVJlcx-eQAoEtsBwil X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX1CQaPuQ6Xv/g TiVN6h5HEm9pJPgZt2d/aF3DVphDq9YfZP5mbXtUQ2nlBJ+TCYQB6RUDWkKOtMKp+mgYm1XQtIf cZLxbw/k3FnjNYJIrYkgf5GMmqrtBVFanG73OUaVwK0v5iGGFBjHDz3i3IAFKlYObEOa91cr7tH /5PKf7xi095mKI0Gz4LLQmS5o2HvLkKSQlt+kcsdl/mqA0ypthh6TeOC+WiA7G5EDEEByYQMaq3 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helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897326478158500 Content-Type: text/plain; charset="utf-8" From: Amit Machhiwal Add infrastructure to query the host CPU compatibility mode via the KVM_PPC_GET_COMPAT_CAPS ioctl. This allows QEMU to determine if the host is running in a compatibility mode (e.g., a Power11 processor operating in Power10 compatibility mode). The kvmppc_get_compat_caps() function issues the ioctl and returns the compat_capabilities bitmap. The kvm_ppc_host_compat_pvr() function derives the effective PVR from the bitmap using ctz64() to find the lowest set bit (highest supported compat level in IBM MSB-0 numbering). The struct kvm_ppc_compat_caps places 'size' first and userspace sets it to sizeof(struct kvm_ppc_compat_caps) before calling the ioctl. The kernel uses copy_struct_from/to_user() to handle forward and backward ABI compatibility: an older userspace with a smaller struct gets trailing fields zero-padded. When newer userspace passes a larger struct to an older kernel (usize > ksize), the kernel unconditionally returns -E2BIG and writes its own ksize back into host_compat.size. QEMU detects this, validates the returned size against KVM_PPC_COMPAT_CAPS_SIZE_VER0, and retries with that size. Additionally, cas_check_pvr() in hw/ppc/spapr_hcall.c is updated to prevent fallback to raw mode when the host is running in compatibility mode. This ensures that nested guests cannot exceed the host's compatibility level. The call is guarded with kvm_enabled() since kvm_ppc_host_compat_pvr() invokes kvm_vm_ioctl() which dereferences kvm_state; without the guard, a TCG guest on a CONFIG_KVM=3Dy binary would segfault. If the capability is not supported or the query fails, the functions return 0, allowing fallback to existing behavior. Tested-by: Gautam Menghani Reviewed-by: Gautam Menghani Tested-by: Anushree Mathur Signed-off-by: Amit Machhiwal Link: https://lore.kernel.org/qemu-devel/20260812170854.58709-3-amachhiw@li= nux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/kvm_ppc.h | 7 +++++ hw/ppc/spapr_hcall.c | 14 +++++++++ target/ppc/kvm.c | 75 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 96 insertions(+) diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 742881231e..195dbaac5e 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -81,6 +81,8 @@ bool kvmppc_supports_ail_3(void); int kvmppc_enable_hwrng(void); int kvmppc_put_books_sregs(PowerPCCPU *cpu); PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void); + +uint32_t kvm_ppc_host_compat_pvr(void); void kvmppc_check_papr_resize_hpt(Error **errp); int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shi= ft); int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shif= t); @@ -440,6 +442,11 @@ static inline PowerPCCPUClass *kvm_ppc_get_host_cpu_cl= ass(void) return NULL; } =20 +static inline uint32_t kvm_ppc_host_compat_pvr(void) +{ + return 0; +} + static inline void kvmppc_check_papr_resize_hpt(Error **errp) { } diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 23bcd788da..708902934c 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1136,6 +1136,7 @@ static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32= _t max_compat, { bool explicit_match =3D false; /* Matched the CPU's real PVR */ uint32_t best_compat =3D 0; + uint32_t compat_host_pvr =3D 0; int i; =20 /* @@ -1163,6 +1164,19 @@ static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint3= 2_t max_compat, } } =20 + if (explicit_match && kvm_enabled()) { + compat_host_pvr =3D kvm_ppc_host_compat_pvr(); + /* + * If the host is booted in a compatibility mode, do not try booti= ng in + * the raw mode as it may allow KVM guests to boot with a higher C= PU + * version compared to what host was booted with; which should not= be + * allowed. + */ + if (compat_host_pvr) { + explicit_match =3D false; + } + } + *raw_mode_supported =3D explicit_match; =20 /* Parsing finished */ diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 116b39a00f..d4c5601a00 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -2602,6 +2602,81 @@ bool kvmppc_supports_ail_3(void) return cap_ail_mode_3; } =20 +#if defined(TARGET_PPC64) +static target_ulong kvmppc_get_compat_caps(void) +{ + struct kvm_ppc_compat_caps host_compat; + int ret; + + if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_COMPAT_CAPS)) { + return 0; + } + + /* + * Set size to sizeof(struct kvm_ppc_compat_caps) so the kernel applies + * copy_struct_from/to_user() versioning. size must be >=3D VER0. + */ + memset(&host_compat, 0, sizeof(host_compat)); + host_compat.size =3D sizeof(host_compat); + + ret =3D kvm_vm_ioctl(kvm_state, KVM_PPC_GET_COMPAT_CAPS, &host_compat); + if (ret =3D=3D -E2BIG && host_compat.size >=3D KVM_PPC_COMPAT_CAPS_SIZ= E_VER0) { + /* + * Kernel is older and knows only a smaller struct version. It + * wrote back its ksize into host_compat.size. Retry with that + * size so the kernel accepts the call. + * + * When a VER1 struct is introduced, add a check here: + * if (host_compat.size >=3D KVM_PPC_COMPAT_CAPS_SIZE_VER1) { ..= . } + */ + uint64_t ksize =3D host_compat.size; + memset(&host_compat, 0, sizeof(host_compat)); + host_compat.size =3D ksize; + ret =3D kvm_vm_ioctl(kvm_state, KVM_PPC_GET_COMPAT_CAPS, &host_com= pat); + } + + if (ret < 0) { + error_report("KVM: failed to get host CPU compat capabilities: %s", + strerror(-ret)); + return 0; + } + + return host_compat.compat_capabilities & KVM_PPC_COMPAT_BITMASK; +} + +/* + * Return the effective host PVR based on the CPU compatibility mode + * reported by KVM. Returns 0 if no compat mode is active or the + * capability is not supported, in which case the caller falls back + * to the raw hardware PVR. + */ +uint32_t kvm_ppc_host_compat_pvr(void) +{ + uint32_t compat_host_pvr =3D 0; + uint64_t cap_idx =3D 0; + target_ulong host_caps =3D kvmppc_get_compat_caps(); + + if (host_caps) { + cap_idx =3D 1ULL << ctz64(host_caps); + switch (cap_idx) { + case KVM_PPC_COMPAT_CAP_POWER9: + compat_host_pvr =3D CPU_POWERPC_POWER9_DD22; + break; + case KVM_PPC_COMPAT_CAP_POWER10: + compat_host_pvr =3D CPU_POWERPC_POWER10_DD20; + break; + case KVM_PPC_COMPAT_CAP_POWER11: + compat_host_pvr =3D CPU_POWERPC_POWER11_DD20; + break; + default: + break; + } + } + + return compat_host_pvr; +} +#endif /* TARGET_PPC64 */ + PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void) { uint32_t host_pvr =3D mfpvr(); --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897440782158500 Content-Type: text/plain; charset="utf-8" From: Amit Machhiwal On POWER systems, the host CPU may run in a compatibility mode (e.g., a Power11 processor operating in Power10 compatibility mode). When running nested KVM guests, QEMU currently derives the host CPU type using mfpvr(), which reflects the physical processor version. This can result in a mismatch between the CPU model used by QEMU and the compatibility mode enforced by the host, leading to guest boot failures such as "KVM-NESTEDv2: couldn't set guest wide elements". Update kvm_ppc_get_host_cpu_class() to check if the host is running in a compatibility mode using kvm_ppc_host_compat_pvr(). When available, use the compatibility PVR instead of the raw hardware PVR when selecting the CPU model. This ensures that QEMU selects a CPU model consistent with the host compatibility mode, allowing nested guests to boot correctly. The guard uses #if defined(TARGET_PPC64) to prevent build breakage on ppc32 targets where the POWER9/10/11 PVR constants are not defined. Tested-by: Gautam Menghani Reviewed-by: Gautam Menghani Tested-by: Anushree Mathur Signed-off-by: Amit Machhiwal Link: https://lore.kernel.org/qemu-devel/20260812170854.58709-4-amachhiw@li= nux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/kvm.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index d4c5601a00..8e89a6c665 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -2682,6 +2682,15 @@ PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void) uint32_t host_pvr =3D mfpvr(); PowerPCCPUClass *pvr_pcc; =20 +#if defined(TARGET_PPC64) + uint32_t compat_host_pvr; + + compat_host_pvr =3D kvm_ppc_host_compat_pvr(); + if (compat_host_pvr) { + host_pvr =3D compat_host_pvr; + } +#endif /* TARGET_PPC64 */ + pvr_pcc =3D ppc_cpu_class_by_pvr(host_pvr); if (pvr_pcc =3D=3D NULL) { pvr_pcc =3D ppc_cpu_class_by_pvr_mask(host_pvr); --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897305933154100 Content-Type: text/plain; charset="utf-8" From: Gautam Menghani When a KVM guest is migrated to another LPAR while a stress-ng workload is running, lockups are seen when the guest resumes on the destination LPAR. This root cause is that if there was a pending interrupt for a cpu on the source machine but it was not presented yet when the migration started, the interrupt is not retriggered on the destination LPAR. This is evident when running 'info pic' on the destination LPAR: $ virsh qemu-monitor-command --hmp migrate 'info pic' | grep -e OS -e MSI CPU[0000]: OS 00 ff 00 ff ff 00 ff ff 80000400 CPU[0001]: OS 00 ff 00 ff ff 00 ff ff 80000401 CPU[0002]: OS 00 ff 00 ff ff 00 ff ff 80000402 CPU[0003]: OS 00 ff 00 ff ff 00 ff ff 80000403 CPU[0004]: OS 00 ff 00 ff ff 00 ff ff 80000404 CPU[0005]: OS 00 ff 00 ff ff 00 ff ff 80000405 CPU[0006]: OS 80 ff 02 ff ff 00 ff 06 80000406 CPU[0007]: OS 00 ff 00 ff ff 00 ff ff 80000407 00000000 MSI -- 00000010 0/6 3071/16384 @3710000 ^1 [ 80000010 800= 00010 80000010 80000010 80000010 ^00000000 ] 00000001 MSI -- 00000010 1/6 1852/16384 @3980000 ^1 [ 80000010 800= 00033 80000033 80000033 80000033 ^00000000 ] 00000002 MSI -- 00000010 2/6 4424/16384 @40c0000 ^1 [ 80000020 800= 00020 80000020 80000010 80000010 ^00000000 ] 00000003 MSI -- 00000010 3/6 1913/16384 @4220000 ^1 [ 80000010 800= 00032 80000010 80000010 80000010 ^00000000 ] 00000004 MSI -- 00000010 4/6 2946/16384 @4360000 ^1 [ 80000010 800= 00010 80000010 80000010 80000010 ^00000000 ] 00000005 MSI -- 00000010 5/6 2313/16384 @44a0000 ^1 [ 80000010 800= 00010 80000010 80000010 80000010 ^00000000 ] 00000006 MSI P- 00000010 6/6 5825/16384 @45f0000 ^1 [ 80000024 800= 00024 80000024 80000010 80000016 ^00000000 ] 00000007 MSI -- 00000010 7/6 2346/16384 @4760000 ^1 [ 80000032 800= 00032 80000010 80000032 80000032 ^00000000 ] Fix this by calling xive_tctx_pipr_set() in vmstate_xive_tctx_post_load(), which ends up calling qemu_irq_raise() to present the interrupt. This fix is relevant only for setups where KVM guests rely on emulated XIVE provided by QEMU, since the native XIVE case is already handled. Cc: qemu-stable@nongnu.org Reported-by: Anushree Mathur Tested-by: Anushree Mathur Reviewed-by: Nikhil Kumar Singh Reviewed-by: Michael Kowal Signed-off-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20260826060217.24978-1-gautam@linu= x.ibm.com Signed-off-by: Harsh Prateek Bora --- hw/intc/xive.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index f473e6ac77..712498d4af 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1080,6 +1080,9 @@ static int vmstate_xive_tctx_post_load(void *opaque, = int version_id) error_report_err(local_err); return ret; } + } else { + uint8_t pipr =3D tctx->regs[TM_QW1_OS + TM_PIPR]; + xive_tctx_pipr_set(tctx, TM_QW1_OS, pipr, 0); } =20 return 0; --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897527166154100 Content-Type: text/plain; charset="utf-8" From: Nikhil Kumar Singh Move EXTSWSLI to decodetree using the XS-form layout with a custom %xs_sh field to represent the fractured shift encoding. This replaces legacy GEN_HANDLER-based implementations with a single trans_EXTSWSLI() handler. The implementation intentionally operates directly on the destination GPR to preserve exact TCG output and avoid introducing temporary variables, matching legacy behavior. Testing: - Verified TCG equivalence with legacy implementation. Signed-off-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-2-rathc@linu= x.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 8 ++++++++ target/ppc/translate.c | 43 ++++++++++++++-------------------------- 2 files changed, 23 insertions(+), 28 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 0e9c68f2fb..342e65dadf 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -117,6 +117,11 @@ &X_sa_rc rs ra rc @X_sa_rc ...... rs:5 ra:5 ..... .......... rc:1 &X_sa_rc =20 +# XS-form with fractured shift amount +%xs_sh 1:1 11:5 +&XS rs ra sh rc +@XS ...... rs:5 ra:5 ..... ......... . rc:1 &XS sh=3D%= xs_sh + %x_frtp 22:4 !function=3Dtimes_2 %x_frap 17:4 !function=3Dtimes_2 %x_frbp 12:4 !function=3Dtimes_2 @@ -1301,6 +1306,9 @@ XVF64GERPN 111011 ... -- .... 0 ..... 10111010 .= .- @XX3_at xa=3D%xx_xa_pair XVF64GERNP 111011 ... -- .... 0 ..... 01111010 ..- @XX3_at xa=3D%xx_= xa_pair XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=3D%xx_= xa_pair =20 +##Extend Sign Word and Shift Left Immediate XS-form +EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS + ## Vector Division Instructions =20 VDIVSW 000100 ..... ..... ..... 00110001011 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 06ed2adf10..e627f48f9e 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2470,30 +2470,6 @@ static void gen_sradi1(DisasContext *ctx) gen_sradi(ctx, 1); } =20 -/* extswsli & extswsli. */ -static inline void gen_extswsli(DisasContext *ctx, int n) -{ - int sh =3D SH(ctx->opcode) + (n << 5); - TCGv dst =3D cpu_gpr[rA(ctx->opcode)]; - TCGv src =3D cpu_gpr[rS(ctx->opcode)]; - - tcg_gen_ext32s_tl(dst, src); - tcg_gen_shli_tl(dst, dst, sh); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, dst); - } -} - -static void gen_extswsli0(DisasContext *ctx) -{ - gen_extswsli(ctx, 0); -} - -static void gen_extswsli1(DisasContext *ctx) -{ - gen_extswsli(ctx, 1); -} - /* srd & srd. */ static void gen_srd(DisasContext *ctx) { @@ -5750,6 +5726,21 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *= d, arg_PLS_D *a) return true; } =20 +static bool trans_EXTSWSLI(DisasContext *ctx, arg_XS *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + + /* Mimic legacy behavior: operate directly on dst */ + tcg_gen_ext32s_tl(cpu_gpr[a->ra], cpu_gpr[a->rs]); + tcg_gen_shli_tl(cpu_gpr[a->ra], cpu_gpr[a->ra], a->sh); + + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } + return true; +} + #include "translate/fixedpoint-impl.c.inc" =20 #include "translate/fp-impl.c.inc" @@ -5850,10 +5841,6 @@ GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_= 64B), GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), -GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, - PPC_NONE, PPC2_ISA300), -GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, - PPC_NONE, PPC2_ISA300), #endif /* handles lfdp, lxsd, lxssp */ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897302240154100 Content-Type: text/plain; charset="utf-8" From: Nikhil Kumar Singh Migrate load-and-reserve instructions (lbarx, lharx, lwarx, ldarx, lqarx) to decodetree using the X-form layout. A shared helper (do_load_locked) is introduced for standard-width variants, while LQARX is handled separately due to its 128-bit semantics and register pairing constraints. The implementation preserves legacy behavior, including: - Reservation granularity and overwrite semantics - Alignment requirements - Invalid instruction cases for LQARX Testing: - Verified TCG equivalence with legacy implementation Signed-off-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Reviewed-by: Amit Machhiwal Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-3-rathc@linu= x.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 7 +++ target/ppc/translate.c | 118 +++++++++++++++++++-------------------- 2 files changed, 63 insertions(+), 62 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 342e65dadf..26948e08a7 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1309,6 +1309,13 @@ XVF64GERNN 111011 ... -- .... 0 ..... 11111010 = ..- @XX3_at xa=3D%xx_xa_pair ##Extend Sign Word and Shift Left Immediate XS-form EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS =20 +## Load and Reserve Instructions +LBARX 011111 ..... ..... ..... 0000110100 . @X_rc +LHARX 011111 ..... ..... ..... 0001110100 . @X_rc +LWARX 011111 ..... ..... ..... 0000010100 . @X_rc +LDARX 011111 ..... ..... ..... 0001010100 . @X_rc +LQARX 011111 ..... ..... ..... 0100010100 . @X_rc + ## Vector Division Instructions =20 VDIVSW 000100 ..... ..... ..... 00110001011 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e627f48f9e..69c4443dda 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2947,30 +2947,6 @@ static void gen_isync(DisasContext *ctx) ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } =20 -static void gen_load_locked(DisasContext *ctx, MemOp memop) -{ - TCGv gpr =3D cpu_gpr[rD(ctx->opcode)]; - TCGv t0 =3D tcg_temp_new(); - - gen_set_access_type(ctx, ACCESS_RES); - gen_addr_reg_index(ctx, t0); - tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN); - tcg_gen_mov_tl(cpu_reserve, t0); - tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); - tcg_gen_mov_tl(cpu_reserve_val, gpr); -} - -#define LARX(name, memop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - gen_load_locked(ctx, memop); \ -} - -/* lwarx */ -LARX(lbarx, MO_UB) -LARX(lharx, MO_UW) -LARX(lwarx, MO_UL) - static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, TCGv EA, TCGCond cond, int addend) { @@ -3219,42 +3195,9 @@ STCX(sthcx_, MO_UW) STCX(stwcx_, MO_UL) =20 #if defined(TARGET_PPC64) -/* ldarx */ -LARX(ldarx, MO_UQ) /* stdcx. */ STCX(stdcx_, MO_UQ) =20 -/* lqarx */ -static void gen_lqarx(DisasContext *ctx) -{ - int rd =3D rD(ctx->opcode); - TCGv EA, hi, lo; - TCGv_i128 t16; - - if (unlikely((rd & 1) || (rd =3D=3D rA(ctx->opcode)) || - (rd =3D=3D rB(ctx->opcode)))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - - gen_set_access_type(ctx, ACCESS_RES); - EA =3D tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - - /* Note that the low part is always in RD+1, even in LE mode. */ - lo =3D cpu_gpr[rd + 1]; - hi =3D cpu_gpr[rd]; - - t16 =3D tcg_temp_new_i128(); - tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIG= N)); - tcg_gen_extr_i128_i64(lo, hi, t16); - - tcg_gen_mov_tl(cpu_reserve, EA); - tcg_gen_movi_tl(cpu_reserve_length, 16); - tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val)); - tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2)); -} - /* stqcx. */ static void gen_stqcx_(DisasContext *ctx) { @@ -5741,6 +5684,62 @@ static bool trans_EXTSWSLI(DisasContext *ctx, arg_XS= *a) return true; } =20 +/* + * Load-and-reserve core + */ +static bool do_load_locked(DisasContext *ctx, arg_X_rc *a, MemOp memop) +{ + TCGv EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + TCGv gpr =3D cpu_gpr[a->rt]; + + gen_set_access_type(ctx, ACCESS_RES); + + tcg_gen_qemu_ld_tl(gpr, EA, ctx->mem_idx, memop | MO_ALIGN); + + tcg_gen_mov_tl(cpu_reserve, EA); + tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); + + tcg_gen_mov_tl(cpu_reserve_val, gpr); + + return true; +} + +TRANS_FLAGS2(ATOMIC_ISA206, LBARX, do_load_locked, DEF_MEMOP(MO_UB)) +TRANS_FLAGS2(ATOMIC_ISA206, LHARX, do_load_locked, DEF_MEMOP(MO_UW)) +TRANS(LWARX, do_load_locked, DEF_MEMOP(MO_UL)) +TRANS64(LDARX, do_load_locked, DEF_MEMOP(MO_UQ)) + +static bool trans_LQARX(DisasContext *ctx, arg_LQARX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA207S); +#if defined(TARGET_PPC64) + TCGv EA; + TCGv_i128 t16; + /* Must use even register and avoid overlap */ + if (unlikely((a->rt & 1) || (a->rt =3D=3D a->ra) || (a->rt =3D=3D a->r= b))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + gen_set_access_type(ctx, ACCESS_RES); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + t16 =3D tcg_temp_new_i128(); + + tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIG= N)); + tcg_gen_extr_i128_i64(cpu_gpr[a->rt + 1], cpu_gpr[a->rt], t16); + tcg_gen_mov_tl(cpu_reserve, EA); + tcg_gen_movi_tl(cpu_reserve_length, 16); + tcg_gen_st_i64(cpu_gpr[a->rt], tcg_env, + offsetof(CPUPPCState, reserve_val)); + tcg_gen_st_i64(cpu_gpr[a->rt + 1], tcg_env, + offsetof(CPUPPCState, reserve_val2)); +#else + qemu_build_not_reached(); +#endif + return true; +} + #include "translate/fixedpoint-impl.c.inc" =20 #include "translate/fp-impl.c.inc" @@ -5853,9 +5852,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_S= TRING), GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), -GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), @@ -5864,8 +5860,6 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00= 000000, PPC_RES), #if defined(TARGET_PPC64) GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), -GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), #endif --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897285775154100 Content-Type: text/plain; charset="utf-8" From: Nikhil Kumar Singh Convert cache management instructions to decodetree using custom X-form layouts (@X_ea, @X_l, @X_th) and dedicated translation functions. This ensures reserved bits are accurately represented and ignored by the decoder (using '-' in the patterns), rather than being erroneously parsed into instruction fields. Legacy GEN_HANDLER-based implementations are removed. The implementation preserves legacy semantics, including: - MMU-visible accesses for instructions treated as loads (e.g. dcbt, dcbtst, dcbtep, dcbtstep) - Supervisor and BookE-specific constraints - Effective address computation via do_ea_calc() Instructions that were defined as no-ops in the legacy implementation remain no-ops here. Note on intentional behavior changes: - dcbf now validates the L field against the Power ISA v3.1 set of legal values (0, 1, 3, 4, 6). - Reserved bits that were previously encoded as part of the opcode mask (and trapped if set) are now properly decoded as "don't care" ('-' in the pattern). Testing: - Verified TCG equivalence for all cache operations Signed-off-by: Nikhil Kumar Singh Tested-by: Tasmiya Nalatwad Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Reviewed-by: Amit Machhiwal Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-4-rathc@linu= x.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/helper.h | 4 +- target/ppc/insn32.decode | 33 ++++ target/ppc/mem_helper.c | 4 +- target/ppc/translate.c | 409 ++++++++++++++++++++------------------- 4 files changed, 249 insertions(+), 201 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6b2d19a3ad..82ec3a471b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -52,8 +52,8 @@ DEF_HELPER_FLAGS_3(dcbz, TCG_CALL_NO_WG, void, env, tl, i= nt) #ifdef TARGET_PPC64 DEF_HELPER_FLAGS_2(dcbzl, TCG_CALL_NO_WG, void, env, tl) #endif -DEF_HELPER_FLAGS_2(icbi, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_FLAGS_2(icbiep, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(ICBI, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(ICBIEP, TCG_CALL_NO_WG, void, env, tl) =20 #if defined(TARGET_PPC64) DEF_HELPER_4(DIVDEU, i64, env, i64, i64, i32) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 26948e08a7..92706e2097 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1306,6 +1306,39 @@ XVF64GERPN 111011 ... -- .... 0 ..... 10111010 = ..- @XX3_at xa=3D%xx_xa_pair XVF64GERNP 111011 ... -- .... 0 ..... 01111010 ..- @XX3_at xa=3D%xx_= xa_pair XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=3D%xx_= xa_pair =20 +## Cache Management Instructions + +&X_ea ra rb +@X_ea ...... ..... ra:5 rb:5 .......... . &X_ea + +&X_l l ra rb +@X_l ...... .. l:3 ra:5 rb:5 .......... . &X_l + +&X_th th ra rb +@X_th ...... th:5 ra:5 rb:5 .......... . &X_th + +DCBF 011111 -- ... ..... ..... 0001010110 - @X_l +DCBFEP 011111 ----- ..... ..... 0001111111 - @X_ea +DCBI 011111 ----- ..... ..... 0111010110 - @X_ea +DCBST 011111 ----- ..... ..... 0000110110 - @X_ea +DCBSTEP 011111 ----- ..... ..... 0000111111 - @X_ea +DCBA 011111 ----- ..... ..... 1011110110 - @X_ea + +DCBT 011111 ..... ..... ..... 0100010110 - @X_th +DCBTEP 011111 ----- ..... ..... 0100111111 - @X_ea +DCBTST 011111 ..... ..... ..... 0011110110 - @X_th +DCBTSTEP 011111 ----- ..... ..... 0011111111 - @X_ea + +DCBTLS 011111 ..... ..... ..... 0010100110 - @X_th +DCBLC 011111 ..... ..... ..... 0110000110 - @X_th + +ICBI 011111 ----- ..... ..... 1111010110 - @X_ea +ICBIEP 011111 ----- ..... ..... 1111011111 - @X_ea + +DST 011111 ----- ..... ..... 0101010110 - @X_ea +DSTST 011111 ----- ..... ..... 0101110110 - @X_ea +DSS 011111 ----- ..... ..... 1100110110 - @X_ea + ##Extend Sign Word and Shift Left Immediate XS-form EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS =20 diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 787ba2cdec..8ad6945590 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -341,7 +341,7 @@ void helper_dcbzl(CPUPPCState *env, target_ulong addr) } #endif =20 -void helper_icbi(CPUPPCState *env, target_ulong addr) +void helper_ICBI(CPUPPCState *env, target_ulong addr) { unsigned mmu_idx =3D cpu_mmu_index(env_cpu(env), false); MemOpIdx oi =3D make_memop_idx(MO_UL | MO_UNALN, mmu_idx); @@ -357,7 +357,7 @@ void helper_icbi(CPUPPCState *env, target_ulong addr) cpu_ldl_mmu(env, addr, oi, GETPC()); } =20 -void helper_icbiep(CPUPPCState *env, target_ulong addr) +void helper_ICBIEP(CPUPPCState *env, target_ulong addr) { #if !defined(CONFIG_USER_ONLY) MemOpIdx oi =3D make_memop_idx(MO_UL | MO_UNALN, PPC_TLB_EPID_LOAD); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 69c4443dda..4bd7f44b3c 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4298,128 +4298,6 @@ static void gen_setb(DisasContext *ctx) =20 /*** Cache management = ***/ =20 -/* dcbf */ -static void gen_dcbf(DisasContext *ctx) -{ - /* XXX: specification says this is treated as a load by the MMU */ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_qemu_ld8u(ctx, t0, t0); -} - -/* dcbfep (external PID dcbf) */ -static void gen_dcbfep(DisasContext *ctx) -{ - /* XXX: specification says this is treated as a load by the MMU */ - TCGv t0; - CHK_SV(ctx); - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); -} - -/* dcbi (Supervisor only) */ -static void gen_dcbi(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv EA, val; - - CHK_SV(ctx); - EA =3D tcg_temp_new(); - gen_set_access_type(ctx, ACCESS_CACHE); - gen_addr_reg_index(ctx, EA); - val =3D tcg_temp_new(); - /* XXX: specification says this should be treated as a store by the MM= U */ - gen_qemu_ld8u(ctx, val, EA); - gen_qemu_st8(ctx, val, EA); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -/* dcdst */ -static void gen_dcbst(DisasContext *ctx) -{ - /* XXX: specification say this is treated as a load by the MMU */ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_qemu_ld8u(ctx, t0, t0); -} - -/* dcbstep (dcbstep External PID version) */ -static void gen_dcbstep(DisasContext *ctx) -{ - /* XXX: specification say this is treated as a load by the MMU */ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); -} - -/* dcbt */ -static void gen_dcbt(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a load by the MMU but - * does not generate any exception - */ -} - -/* dcbtep */ -static void gen_dcbtep(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a load by the MMU but - * does not generate any exception - */ -} - -/* dcbtst */ -static void gen_dcbtst(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a load by the MMU but - * does not generate any exception - */ -} - -/* dcbtstep */ -static void gen_dcbtstep(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a load by the MMU but - * does not generate any exception - */ -} - -/* dcbtls */ -static void gen_dcbtls(DisasContext *ctx) -{ - /* Always fails locking the cache */ - TCGv t0 =3D tcg_temp_new(); - gen_load_spr(t0, SPR_Exxx_L1CSR0); - tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); - gen_store_spr(SPR_Exxx_L1CSR0, t0); -} - -/* dcblc */ -static void gen_dcblc(DisasContext *ctx) -{ - /* - * interpreted as no-op - */ -} - /* dcbz */ static void gen_dcbz(DisasContext *ctx) { @@ -4448,64 +4326,6 @@ static void gen_dcbzep(DisasContext *ctx) gen_helper_dcbz(tcg_env, tcgv_addr, tcg_constant_i32(PPC_TLB_EPID_STOR= E)); } =20 -/* dst / dstt */ -static void gen_dst(DisasContext *ctx) -{ - if (rA(ctx->opcode) =3D=3D 0) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - } else { - /* interpreted as no-op */ - } -} - -/* dstst /dststt */ -static void gen_dstst(DisasContext *ctx) -{ - if (rA(ctx->opcode) =3D=3D 0) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - } else { - /* interpreted as no-op */ - } - -} - -/* dss / dssall */ -static void gen_dss(DisasContext *ctx) -{ - /* interpreted as no-op */ -} - -/* icbi */ -static void gen_icbi(DisasContext *ctx) -{ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_helper_icbi(tcg_env, t0); -} - -/* icbiep */ -static void gen_icbiep(DisasContext *ctx) -{ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_helper_icbiep(tcg_env, t0); -} - -/* Optional: */ -/* dcba */ -static void gen_dcba(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a store by the MMU - * but does not generate any exception - */ -} - /*** Segment register manipulation = ***/ /* Supervisor only: */ =20 @@ -5740,6 +5560,218 @@ static bool trans_LQARX(DisasContext *ctx, arg_LQAR= X *a) return true; } =20 +/* + * Cache Management Instructions (decodetree) + */ + +static bool trans_DCBA(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS(ctx, CACHE_DCBA); + return true; +} + +static bool trans_DCBT(DisasContext *ctx, arg_X_th *a) +{ + REQUIRE_INSNS_FLAGS(ctx, CACHE); + return true; +} + +static bool trans_DCBTEP(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + return true; +} + +static bool trans_DCBTST(DisasContext *ctx, arg_X_th *a) +{ + REQUIRE_INSNS_FLAGS(ctx, CACHE); + return true; +} + +static bool trans_DCBTSTEP(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + return true; +} + +static bool trans_DCBLC(DisasContext *ctx, arg_X_th *a) +{ + /* Requires either PPC_BOOKE or PPC2_BOOKE206 */ + if (!(ctx->insns_flags & PPC_BOOKE) && + !(ctx->insns_flags2 & PPC2_BOOKE206)) { + return false; + } + return true; +} + +static bool trans_DSS(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); + return true; +} + +static bool trans_DCBTLS(DisasContext *ctx, arg_X_th *a) +{ + TCGv t0 =3D tcg_temp_new(); + + /* Requires either PPC_BOOKE or PPC2_BOOKE206 */ + if (!(ctx->insns_flags & PPC_BOOKE) && + !(ctx->insns_flags2 & PPC2_BOOKE206)) { + return false; + } + + gen_load_spr(t0, SPR_Exxx_L1CSR0); + tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); + gen_store_spr(SPR_Exxx_L1CSR0, t0); + + return true; +} + +static bool trans_DST(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); + + if (a->ra =3D=3D 0) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + } + + return true; +} + +static bool trans_DSTST(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); + + if (a->ra =3D=3D 0) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + } + + return true; +} + +static bool trans_DCBF(DisasContext *ctx, arg_X_l *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS(ctx, CACHE); + + /* + * As per PowerISA v3.1, the L field can have values 0, 1, 3, 4, or 6. + * Other values are Undefined Behavior (UB). + */ + switch (a->l) { + case 0: /* dcbf */ + case 1: /* dcbfl */ + case 3: /* dcbflp */ + case 4: /* dcbfps */ + case 6: /* dcbstps */ + break; + default: + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + gen_qemu_ld8u(ctx, EA, EA); + + return true; +} + +static bool trans_DCBST(DisasContext *ctx, arg_X_ea *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS(ctx, CACHE); + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + gen_qemu_ld8u(ctx, EA, EA); + + return true; +} + +static bool trans_DCBFEP(DisasContext *ctx, arg_X_ea *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + + REQUIRE_SV(ctx); + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + + tcg_gen_qemu_ld_tl(EA, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); + + return true; +} + +static bool trans_DCBSTEP(DisasContext *ctx, arg_X_ea *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + + tcg_gen_qemu_ld_tl(EA, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); + + return true; +} + +static bool trans_DCBI(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS(ctx, CACHE); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); + return true; +#else + TCGv EA, val; + + REQUIRE_SV(ctx); + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + val =3D tcg_temp_new(); + + gen_qemu_ld8u(ctx, val, EA); + gen_qemu_st8(ctx, val, EA); + + return true; +#endif +} + +static bool trans_ICBI(DisasContext *ctx, arg_X_ea *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS(ctx, CACHE_ICBI); + + gen_set_access_type(ctx, ACCESS_CACHE); + + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + gen_helper_ICBI(tcg_env, EA); + + return true; +} + +static bool trans_ICBIEP(DisasContext *ctx, arg_X_ea *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + REQUIRE_SV(ctx); + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + + gen_helper_ICBIEP(tcg_env, EA); + return true; +} + #include "translate/fixedpoint-impl.c.inc" =20 #include "translate/fp-impl.c.inc" @@ -5904,25 +5936,8 @@ GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, = PPC_NONE, PPC2_ISA300), #endif GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), -GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), -GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE20= 6), -GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), -GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), -GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE2= 06), -GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), -GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE20= 6), -GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), -GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE= 206), -GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE2= 06), -GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE20= 6), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE20= 6), -GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), -GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), -GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), -GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), -GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE20= 6), -GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897354781154100 Content-Type: text/plain; charset="utf-8" From: Aboorva Devarajan Move below instructions to decodetree specification: vmrg{hb, hh, hw, lb, lh, lw} : VX-form The individual gen_vmrg* functions generated by GEN_VXFORM are replaced by a shared do_vmrg() helper dispatching to the existing gen_helper_VMRG* TCG helpers via the TRANS_FLAGS() macro, which also handles the ALTIVEC facility check. The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Aboorva Devarajan Reviewed-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-5-rathc@linu= x.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/helper.h | 12 ++++++------ target/ppc/insn32.decode | 9 +++++++++ target/ppc/int_helper.c | 12 ++++++------ target/ppc/translate/vmx-impl.c.inc | 25 +++++++++++++++++++------ target/ppc/translate/vmx-ops.c.inc | 6 ------ 5 files changed, 40 insertions(+), 24 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 82ec3a471b..5517d2950f 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -173,12 +173,12 @@ DEF_HELPER_4(vcmpeqfp_dot, void, env, avr, avr, avr) DEF_HELPER_4(vcmpgefp_dot, void, env, avr, avr, avr) DEF_HELPER_4(vcmpgtfp_dot, void, env, avr, avr, avr) DEF_HELPER_4(vcmpbfp_dot, void, env, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrglb, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrglh, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrglw, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrghb, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrghh, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrghw, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGLB, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGLH, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGLW, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGHB, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGHH, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGHW, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_FLAGS_3(VMULESB, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_FLAGS_3(VMULESH, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_FLAGS_3(VMULESW, TCG_CALL_NO_RWG, void, avr, avr, avr) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 92706e2097..99f7421e77 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -795,6 +795,15 @@ VNOR 000100 ..... ..... ..... 10100000100 = @VX VXOR 000100 ..... ..... ..... 10011000100 @VX VEQV 000100 ..... ..... ..... 11010000100 @VX =20 +## Vector Merge Instructions + +VMRGHB 000100 ..... ..... ..... 00000001100 @VX +VMRGHH 000100 ..... ..... ..... 00001001100 @VX +VMRGHW 000100 ..... ..... ..... 00010001100 @VX +VMRGLB 000100 ..... ..... ..... 00100001100 @VX +VMRGLH 000100 ..... ..... ..... 00101001100 @VX +VMRGLW 000100 ..... ..... ..... 00110001100 @VX + ## Vector Integer Average Instructions =20 VAVGSB 000100 ..... ..... ..... 10100000010 @VX diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index ef4b2e75d6..a3adf746bd 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -950,7 +950,7 @@ void helper_VMLADDUHM(ppc_avr_t *r, ppc_avr_t *a, ppc_a= vr_t *b, ppc_avr_t *c, } =20 #define VMRG_DO(name, element, access, ofs) = \ - void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) = \ + void helper_V##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) = \ { = \ ppc_avr_t result; = \ int i, half =3D ARRAY_SIZE(r->element) / 2; = \ @@ -963,11 +963,11 @@ void helper_VMLADDUHM(ppc_avr_t *r, ppc_avr_t *a, ppc= _avr_t *b, ppc_avr_t *c, } =20 #define VMRG(suffix, element, access) \ - VMRG_DO(mrgl##suffix, element, access, half) \ - VMRG_DO(mrgh##suffix, element, access, 0) -VMRG(b, u8, VsrB) -VMRG(h, u16, VsrH) -VMRG(w, u32, VsrW) + VMRG_DO(MRGL##suffix, element, access, half) \ + VMRG_DO(MRGH##suffix, element, access, 0) +VMRG(B, u8, VsrB) +VMRG(H, u16, VsrH) +VMRG(W, u32, VsrW) #undef VMRG_DO #undef VMRG =20 diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 92d6e8c603..00b359f031 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -350,12 +350,25 @@ GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16); GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17); GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18); GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19); -GEN_VXFORM(vmrghb, 6, 0); -GEN_VXFORM(vmrghh, 6, 1); -GEN_VXFORM(vmrghw, 6, 2); -GEN_VXFORM(vmrglb, 6, 4); -GEN_VXFORM(vmrglh, 6, 5); -GEN_VXFORM(vmrglw, 6, 6); + +static bool do_vmrg(DisasContext *ctx, arg_VX *a, + void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr)) +{ + TCGv_ptr ra, rb, rd; + REQUIRE_VECTOR(ctx); + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + helper(rd, ra, rb); + return true; +} + +TRANS_FLAGS(ALTIVEC, VMRGHB, do_vmrg, gen_helper_VMRGHB); +TRANS_FLAGS(ALTIVEC, VMRGHH, do_vmrg, gen_helper_VMRGHH); +TRANS_FLAGS(ALTIVEC, VMRGHW, do_vmrg, gen_helper_VMRGHW); +TRANS_FLAGS(ALTIVEC, VMRGLB, do_vmrg, gen_helper_VMRGLB); +TRANS_FLAGS(ALTIVEC, VMRGLH, do_vmrg, gen_helper_VMRGLH); +TRANS_FLAGS(ALTIVEC, VMRGLW, do_vmrg, gen_helper_VMRGLW); =20 static void trans_vmrgew(DisasContext *ctx) { diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-= ops.c.inc index e28958a126..b8f77d3d2c 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -33,12 +33,6 @@ GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC= _NONE), GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300), GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300), GEN_VXFORM_300(bcds, 0, 27), -GEN_VXFORM(vmrghb, 6, 0), -GEN_VXFORM(vmrghh, 6, 1), -GEN_VXFORM(vmrghw, 6, 2), -GEN_VXFORM(vmrglb, 6, 4), -GEN_VXFORM(vmrglh, 6, 5), -GEN_VXFORM(vmrglw, 6, 6), GEN_VXFORM_300(vextublx, 6, 24), GEN_VXFORM_300(vextuhlx, 6, 25), GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207), --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897393159154100 Content-Type: text/plain; charset="utf-8" From: Aboorva Devarajan Move below instructions to decodetree specification: vpkuhum, vpkuwum, vpkuhus, vpkuwus : VX-form (PPC_ALTIVEC) vpkshus, vpkswus, vpkshss, vpkswss : VX-form (PPC_ALTIVEC) vpkpx : VX-form (PPC_ALTIVEC) vpkudum, vpkudus, vpksdus, vpksdss : VX-form (PPC2_ALTIVEC_207) The legacy GEN_VXFORM_ENV/GEN_VXFORM macros that generated gen_vpk*() functions reading register fields from ctx->opcode are replaced by new do_vpk_env()/do_vpk() helpers in vmx-impl.c.inc that use the pre-extracted decodetree argument fields (a->vrt, a->vra, a->vrb) directly. The existing gen_helper_vpk*() implementations in int_helper.c are reused without changes. The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' option before and after the patch. Signed-off-by: Aboorva Devarajan Reviewed-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-6-rathc@linu= x.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/helper.h | 26 +++++++-------- target/ppc/insn32.decode | 16 +++++++++ target/ppc/int_helper.c | 28 ++++++++-------- target/ppc/translate/vmx-impl.c.inc | 51 +++++++++++++++++++++-------- target/ppc/translate/vmx-ops.c.inc | 13 -------- 5 files changed, 81 insertions(+), 53 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 5517d2950f..a0d08d6192 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -249,19 +249,19 @@ DEF_HELPER_FLAGS_4(VMSUMUBM, TCG_CALL_NO_RWG, void, a= vr, avr, avr, avr) DEF_HELPER_FLAGS_4(VMSUMMBM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) DEF_HELPER_FLAGS_4(VPERM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) DEF_HELPER_FLAGS_4(VPERMR, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) -DEF_HELPER_4(vpkshss, void, env, avr, avr, avr) -DEF_HELPER_4(vpkshus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkswss, void, env, avr, avr, avr) -DEF_HELPER_4(vpkswus, void, env, avr, avr, avr) -DEF_HELPER_4(vpksdss, void, env, avr, avr, avr) -DEF_HELPER_4(vpksdus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkuhus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkuwus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkudus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkuhum, void, env, avr, avr, avr) -DEF_HELPER_4(vpkuwum, void, env, avr, avr, avr) -DEF_HELPER_4(vpkudum, void, env, avr, avr, avr) -DEF_HELPER_FLAGS_3(vpkpx, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_4(VPKSHSS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSHUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSWSS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSWUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSDSS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSDUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUHUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUWUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUDUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUHUM, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUWUM, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUDUM, void, env, avr, avr, avr) +DEF_HELPER_FLAGS_3(VPKPX, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_5(VMHADDSHS, void, env, avr, avr, avr, avr) DEF_HELPER_5(VMHRADDSHS, void, env, avr, avr, avr, avr) DEF_HELPER_FLAGS_4(VMSUMUHM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 99f7421e77..d6f1875532 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1054,6 +1054,22 @@ VSTRIHR 000100 ..... 00011 ..... . 000000110= 1 @VX_tb_rc VCLRLB 000100 ..... ..... ..... 00110001101 @VX VCLRRB 000100 ..... ..... ..... 00111001101 @VX =20 +## Vector Pack Instructions + +VPKUHUM 000100 ..... ..... ..... 0000000111 0 @VX +VPKUWUM 000100 ..... ..... ..... 0000100111 0 @VX +VPKUDUM 000100 ..... ..... ..... 1000100111 0 @VX +VPKUHUS 000100 ..... ..... ..... 0001000111 0 @VX +VPKUWUS 000100 ..... ..... ..... 0001100111 0 @VX +VPKUDUS 000100 ..... ..... ..... 1001100111 0 @VX +VPKSHUS 000100 ..... ..... ..... 0010000111 0 @VX +VPKSWUS 000100 ..... ..... ..... 0010100111 0 @VX +VPKSDUS 000100 ..... ..... ..... 1010100111 0 @VX +VPKSHSS 000100 ..... ..... ..... 0011000111 0 @VX +VPKSWSS 000100 ..... ..... ..... 0011100111 0 @VX +VPKSDSS 000100 ..... ..... ..... 1011100111 0 @VX +VPKPX 000100 ..... ..... ..... 0110000111 0 @VX + # VSX Load/Store Instructions =20 LXSD 111001 ..... ..... .............. 10 @DS diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index a3adf746bd..dc55ccadf7 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -1465,7 +1465,7 @@ void helper_VPMSUMD(ppc_avr_t *r, ppc_avr_t *a, ppc_a= vr_t *b) #else #define PKBIG 0 #endif -void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_VPKPX(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) { int i, j; ppc_avr_t result; @@ -1488,7 +1488,7 @@ void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr= _t *b) } =20 #define VPK(suffix, from, to, cvt, dosat) \ - void helper_vpk##suffix(CPUPPCState *env, ppc_avr_t *r, \ + void helper_VPK##suffix(CPUPPCState *env, ppc_avr_t *r, \ ppc_avr_t *a, ppc_avr_t *b) \ { \ int i; \ @@ -1507,18 +1507,18 @@ void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_a= vr_t *b) } \ } #define I(x, y) (x) -VPK(shss, s16, s8, cvtshsb, 1) -VPK(shus, s16, u8, cvtshub, 1) -VPK(swss, s32, s16, cvtswsh, 1) -VPK(swus, s32, u16, cvtswuh, 1) -VPK(sdss, s64, s32, cvtsdsw, 1) -VPK(sdus, s64, u32, cvtsduw, 1) -VPK(uhus, u16, u8, cvtuhub, 1) -VPK(uwus, u32, u16, cvtuwuh, 1) -VPK(udus, u64, u32, cvtuduw, 1) -VPK(uhum, u16, u8, I, 0) -VPK(uwum, u32, u16, I, 0) -VPK(udum, u64, u32, I, 0) +VPK(SHSS, s16, s8, cvtshsb, 1) +VPK(SHUS, s16, u8, cvtshub, 1) +VPK(SWSS, s32, s16, cvtswsh, 1) +VPK(SWUS, s32, u16, cvtswuh, 1) +VPK(SDSS, s64, s32, cvtsdsw, 1) +VPK(SDUS, s64, u32, cvtsduw, 1) +VPK(UHUS, u16, u8, cvtuhub, 1) +VPK(UWUS, u32, u16, cvtuwuh, 1) +VPK(UDUS, u64, u32, cvtuduw, 1) +VPK(UHUM, u16, u8, I, 0) +VPK(UWUM, u32, u16, I, 0) +VPK(UDUM, u64, u32, I, 0) #undef I #undef VPK #undef PKBIG diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 00b359f031..65230f3461 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1070,19 +1070,44 @@ TRANS(VRLQMI, do_vector_rotl_quad, false, true) =20 GEN_VXFORM_TRANS(vsl, 2, 7); GEN_VXFORM_TRANS(vsr, 2, 11); -GEN_VXFORM_ENV(vpkuhum, 7, 0); -GEN_VXFORM_ENV(vpkuwum, 7, 1); -GEN_VXFORM_ENV(vpkudum, 7, 17); -GEN_VXFORM_ENV(vpkuhus, 7, 2); -GEN_VXFORM_ENV(vpkuwus, 7, 3); -GEN_VXFORM_ENV(vpkudus, 7, 19); -GEN_VXFORM_ENV(vpkshus, 7, 4); -GEN_VXFORM_ENV(vpkswus, 7, 5); -GEN_VXFORM_ENV(vpksdus, 7, 21); -GEN_VXFORM_ENV(vpkshss, 7, 6); -GEN_VXFORM_ENV(vpkswss, 7, 7); -GEN_VXFORM_ENV(vpksdss, 7, 23); -GEN_VXFORM(vpkpx, 7, 12); +static bool do_vpk_env(DisasContext *ctx, arg_VX *a, + void (*gen_helper)(TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_ptr)) +{ + TCGv_ptr ra, rb, rd; + REQUIRE_VECTOR(ctx); + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + gen_helper(tcg_env, rd, ra, rb); + return true; +} + +static bool do_vpk(DisasContext *ctx, arg_VX *a, + void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr)) +{ + TCGv_ptr ra, rb, rd; + REQUIRE_VECTOR(ctx); + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + gen_helper(rd, ra, rb); + return true; +} + +TRANS_FLAGS(ALTIVEC, VPKUHUM, do_vpk_env, gen_helper_VPKUHUM) +TRANS_FLAGS(ALTIVEC, VPKUWUM, do_vpk_env, gen_helper_VPKUWUM) +TRANS_FLAGS2(ALTIVEC_207, VPKUDUM, do_vpk_env, gen_helper_VPKUDUM) +TRANS_FLAGS(ALTIVEC, VPKUHUS, do_vpk_env, gen_helper_VPKUHUS) +TRANS_FLAGS(ALTIVEC, VPKUWUS, do_vpk_env, gen_helper_VPKUWUS) +TRANS_FLAGS2(ALTIVEC_207, VPKUDUS, do_vpk_env, gen_helper_VPKUDUS) +TRANS_FLAGS(ALTIVEC, VPKSHUS, do_vpk_env, gen_helper_VPKSHUS) +TRANS_FLAGS(ALTIVEC, VPKSWUS, do_vpk_env, gen_helper_VPKSWUS) +TRANS_FLAGS2(ALTIVEC_207, VPKSDUS, do_vpk_env, gen_helper_VPKSDUS) +TRANS_FLAGS(ALTIVEC, VPKSHSS, do_vpk_env, gen_helper_VPKSHSS) +TRANS_FLAGS(ALTIVEC, VPKSWSS, do_vpk_env, gen_helper_VPKSWSS) +TRANS_FLAGS2(ALTIVEC_207, VPKSDSS, do_vpk_env, gen_helper_VPKSDSS) +TRANS_FLAGS(ALTIVEC, VPKPX, do_vpk, gen_helper_VPKPX) GEN_VXFORM_ENV(vsum4ubs, 4, 24); GEN_VXFORM_ENV(vsum4sbs, 4, 28); GEN_VXFORM_ENV(vsum4shs, 4, 25); diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-= ops.c.inc index b8f77d3d2c..2820976c0f 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -59,19 +59,6 @@ GEN_VXFORM_300(bcdtrunc, 0, 20), GEN_VXFORM_300(bcdutrunc, 0, 21), GEN_VXFORM(vsl, 2, 7), GEN_VXFORM(vsr, 2, 11), -GEN_VXFORM(vpkuhum, 7, 0), -GEN_VXFORM(vpkuwum, 7, 1), -GEN_VXFORM_207(vpkudum, 7, 17), -GEN_VXFORM(vpkuhus, 7, 2), -GEN_VXFORM(vpkuwus, 7, 3), -GEN_VXFORM_207(vpkudus, 7, 19), -GEN_VXFORM(vpkshus, 7, 4), -GEN_VXFORM(vpkswus, 7, 5), -GEN_VXFORM_207(vpksdus, 7, 21), -GEN_VXFORM(vpkshss, 7, 6), -GEN_VXFORM(vpkswss, 7, 7), -GEN_VXFORM_207(vpksdss, 7, 23), -GEN_VXFORM(vpkpx, 7, 12), GEN_VXFORM(vsum4ubs, 4, 24), GEN_VXFORM(vsum4sbs, 4, 28), GEN_VXFORM(vsum4shs, 4, 25), --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897486533154100 Content-Type: text/plain; charset="utf-8" From: Utkarsh Verma Move the following store conditional instructions to decodetree specification: stbcx. : X-form sthcx. : X-form stwcx. : X-form stdcx. : X-form stqcx. : X-form The changes were verified by checking that the generated TCG ops remain semantically identical to the legacy translation, using logs captured with the -d in_asm,op flag. Signed-off-by: Utkarsh Verma Reviewed-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-7-rathc@linu= x.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 8 ++ target/ppc/translate.c | 103 --------------------- target/ppc/translate/fixedpoint-impl.c.inc | 84 +++++++++++++++++ 3 files changed, 92 insertions(+), 103 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index d6f1875532..824181eb4e 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -732,6 +732,14 @@ DSCLIQ 111111 ..... ..... ...... 001000010 . = @Z22_tap_sh_rc DSCRI 111011 ..... ..... ...... 001100010 . @Z22_ta_sh_rc DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc =20 +### Store Conditional Instructions + +STBCX 011111 ..... ..... ..... 1010110110 1 @X +STHCX 011111 ..... ..... ..... 1011010110 1 @X +STWCX 011111 ..... ..... ..... 0010010110 1 @X +STDCX 011111 ..... ..... ..... 0011010110 1 @X +STQCX 011111 ..... ..... ..... 0010110110 1 @X + ## Vector Exclusive-OR-based Instructions =20 VPMSUMD 000100 ..... ..... ..... 10011001000 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4bd7f44b3c..821363e7fb 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3153,104 +3153,6 @@ static void gen_stdat(DisasContext *ctx) } #endif =20 -static void gen_conditional_store(DisasContext *ctx, MemOp memop) -{ - TCGLabel *lfail; - TCGv EA; - TCGv cr0; - TCGv t0; - int rs =3D rS(ctx->opcode); - - lfail =3D gen_new_label(); - EA =3D tcg_temp_new(); - cr0 =3D tcg_temp_new(); - t0 =3D tcg_temp_new(); - - tcg_gen_mov_tl(cr0, cpu_so); - gen_set_access_type(ctx, ACCESS_RES); - gen_addr_reg_index(ctx, EA); - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop),= lfail); - - tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, - cpu_gpr[rs], ctx->mem_idx, - DEF_MEMOP(memop) | MO_ALIGN); - tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); - tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); - tcg_gen_or_tl(cr0, cr0, t0); - - gen_set_label(lfail); - tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); - tcg_gen_movi_tl(cpu_reserve, -1); -} - -#define STCX(name, memop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - gen_conditional_store(ctx, memop); \ -} - -STCX(stbcx_, MO_UB) -STCX(sthcx_, MO_UW) -STCX(stwcx_, MO_UL) - -#if defined(TARGET_PPC64) -/* stdcx. */ -STCX(stdcx_, MO_UQ) - -/* stqcx. */ -static void gen_stqcx_(DisasContext *ctx) -{ - TCGLabel *lfail; - TCGv EA, t0, t1; - TCGv cr0; - TCGv_i128 cmp, val; - int rs =3D rS(ctx->opcode); - - if (unlikely(rs & 1)) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - - lfail =3D gen_new_label(); - EA =3D tcg_temp_new(); - cr0 =3D tcg_temp_new(); - - tcg_gen_mov_tl(cr0, cpu_so); - gen_set_access_type(ctx, ACCESS_RES); - gen_addr_reg_index(ctx, EA); - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); - - cmp =3D tcg_temp_new_i128(); - val =3D tcg_temp_new_i128(); - - tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); - - /* Note that the low part is always in RS+1, even in LE mode. */ - tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); - - tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, - DEF_MEMOP(MO_128 | MO_ALIGN)); - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - tcg_gen_extr_i128_i64(t1, t0, val); - - tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); - tcg_gen_xor_tl(t0, t0, cpu_reserve_val); - tcg_gen_or_tl(t0, t0, t1); - - tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); - tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); - tcg_gen_or_tl(cr0, cr0, t0); - - gen_set_label(lfail); - tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); - tcg_gen_movi_tl(cpu_reserve, -1); -} -#endif /* defined(TARGET_PPC64) */ - /* wait */ static void gen_wait(DisasContext *ctx) { @@ -5886,14 +5788,9 @@ GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC= _STRING), GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), #if defined(TARGET_PPC64) GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), -GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), #endif /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index fa0191e866..91f9c6c391 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -204,6 +204,90 @@ TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_UQ) TRANS64(STQ, do_ldst_quad, true, false); TRANS64(PSTQ, do_ldst_quad_PLS_D, true); =20 +/* Store Conditional Instructions */ + +static bool do_store_cond(DisasContext *ctx, arg_X *a, MemOp mop) +{ + TCGLabel *lfail =3D gen_new_label(); + TCGv ea =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + TCGv cr0 =3D tcg_temp_new(); + TCGv t0 =3D tcg_temp_new(); + + tcg_gen_mov_tl(cr0, cpu_so); + gen_set_access_type(ctx, ACCESS_RES); + + tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_reserve, lfail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(mop), l= fail); + + tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, + cpu_gpr[a->rt], ctx->mem_idx, + DEF_MEMOP(mop) | MO_ALIGN); + tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); + tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); + tcg_gen_or_tl(cr0, cr0, t0); + + gen_set_label(lfail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); + tcg_gen_movi_tl(cpu_reserve, -1); + return true; +} + +TRANS_FLAGS2(ATOMIC_ISA206, STBCX, do_store_cond, MO_UB); +TRANS_FLAGS2(ATOMIC_ISA206, STHCX, do_store_cond, MO_UW); +TRANS(STWCX, do_store_cond, MO_UL); +TRANS64(STDCX, do_store_cond, MO_UQ); + +static bool trans_STQCX(DisasContext *ctx, arg_STQCX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, LSQ_ISA207); +#if defined(TARGET_PPC64) + TCGLabel *lfail =3D gen_new_label(); + TCGv ea =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv cr0 =3D tcg_temp_new(); + TCGv_i128 cmp =3D tcg_temp_new_i128(); + TCGv_i128 val =3D tcg_temp_new_i128(); + + if (unlikely(a->rt & 1)) { + gen_invalid(ctx); + return true; + } + + tcg_gen_mov_tl(cr0, cpu_so); + gen_set_access_type(ctx, ACCESS_RES); + + tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_reserve, lfail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); + + tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); + + /* Note that the low part is always in RS+1, even in LE mode. */ + tcg_gen_concat_i64_i128(val, cpu_gpr[a->rt + 1], cpu_gpr[a->rt]); + + tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, + DEF_MEMOP(MO_128 | MO_ALIGN)); + + tcg_gen_extr_i128_i64(t1, t0, val); + + tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); + tcg_gen_xor_tl(t0, t0, cpu_reserve_val); + tcg_gen_or_tl(t0, t0, t1); + + tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); + tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); + tcg_gen_or_tl(cr0, cr0, t0); + + gen_set_label(lfail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); + tcg_gen_movi_tl(cpu_reserve, -1); +#else + qemu_build_not_reached(); +#endif + return true; +} + /* * Fixed-Point Compare Instructions */ --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897426; cv=none; d=zohomail.com; s=zohoarc; b=SrZHtCkiAZY34mOJyKX4jIXEQF2rchVzddGb3+SoI7fnb5b+FV5LIDBz4Qrc1BIyWH+UkVsHyYoCCrgfEjSlQax0b1nG+xU2a/V8VVEh6JSqcdOLWE0lqtwKYAqNtO8xmEDCz/0B3Qzbf+TS1xUtqF7XQpudx+FELCZfju7HvjU= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=UUbMOZ7MRiAulERyw ObL8UdDAT4Hu2mpjdCMVTJMDF8=; b=hwBnSztRVInkc3+zJizN9Lnd2oa2dsdUG bEyw+7C4u5uupbrdqcF9QRyPbrooTn/pJ1i9CeyovMCmjOXKU8uauydMaL5m+ve5 31BP3sr8BnAExemh1OirDQBZK7MXQ0IrDpdwg+NVaHuD8Wpa2EuNrt7yjZ99zdC1 htaIH60xFJ5dwNfDk1CRLs+RtZe9xGbdatGROh+7CcstbDY6AwElA099pOa0UbGm kc5nyobGVwwDELvUPVRrfgy6vyIoKPCvy6zQhGb5U8UfC7dl5IwLHuY0PFf3lWdi CtXanlLJS2LLl+9pu99+4NDSbt+NApVdRP4Wpd/ux/7KprIngSKdQ== From: Harsh Prateek Bora To: qemu-devel@nongnu.org Cc: "Mukesh Kumar Chaurasiya (IBM)" , Glenn Miles , Amit Machhiwal , Chinmay Rath , Aniket Sahu Subject: [PULL 11/41] target/ppc: convert slw, srw instruction via decode spec Date: Fri, 28 Aug 2026 11:36:46 +0530 Message-ID: <20260828060716.91672-12-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com> References: <20260828060716.91672-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX5g+psMpB/5P2 1+3i1yqgEJYk0nVfQYqPn5Tm+zVXur1VgqCbcu+4buQmZ1K/H6K871oThBnGg5gunwGTvEeGSZr 6yVPI9jDuftNPrvTeoFd1GjgIf2Oih8= X-Authority-Analysis: v=2.4 cv=AYuB2XXG c=1 sm=1 tr=0 ts=6a9125bf cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=Sv0fKeRqtYgA:10 a=f7IdgyKtn90A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=pGLkceISAAAA:8 a=xO4CFU3ef3RllDxvDoMA:9 X-Proofpoint-ORIG-GUID: d_EwjYifPMqpcuN3Z3oxDktGJ7ggBWwz X-Proofpoint-GUID: 0OiShLVE4ezlCiM9vZ_8P-KZli7bR-mq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX77XgVqNGYT4O TfDugACbWhohbgFTYwyh6R/xhu6OtiTRIrr+7aqKsO/8SL0J6I/e3KY76f9kVo0S7wPSq0j8Eua JaBBTw1ZU7JaphTLn0cah41emAwtxwVvYzX4yzobpiC9UbjeWsThV4hzXYeZNkA7gGEwsYeCFmU xXaH4k0ZFQwR9Om8N7CCKx6nIyRfU1kOj6u3USNT3NiAj9mPSPAIjX3NWXeHg4j9nTOikGD3+y+ OsQQnAdLUedwa6ME3z+IqH/Q95dAGHsfjEkyR1SACM8JEvSj6aPykG2SzibnjC2EN1d5jgqcTly PSs6UQ2rwhOsFoXlO39UcjbFez0YAxHE4FwlNbBJSgScPh+p2D6H4smZRopMad0lycbjuWZSF+H qAI+vjZLD+7t2wssr9LbTEKgMvswUgqGdeKZf6JHCHyZbMgoQzIMQh/bJz5xuVrqb2nuq866JE9 XyhBAY87HlhQBJuSYkA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_01,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280050 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897428730158500 Content-Type: text/plain; charset="utf-8" From: "Mukesh Kumar Chaurasiya (IBM)" Move slw and srw to decodetree specification using the @X_rc format. The existing shift-masking logic from gen_slw/gen_srw is preserved verbatim in the new trans_SLW/trans_SRW handlers. Signed-off-by: Mukesh Kumar Chaurasiya (IBM) Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-8-rathc@linu= x.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 5 +++ target/ppc/translate.c | 49 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 48 +++++++++++++++++++++ 3 files changed, 53 insertions(+), 49 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 824181eb4e..189f9c6fe7 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -505,6 +505,11 @@ HASHCHK 011111 ..... ..... ..... 1011110010 . = @X_DW HASHSTP 011111 ..... ..... ..... 1010010010 . @X_DW HASHCHKP 011111 ..... ..... ..... 1010110010 . @X_DW =20 +# Fixed-Point Shift Instructions + +SLW 011111 ..... ..... ..... 0000011000 . @X_rc +SRW 011111 ..... ..... ..... 1000011000 . @X_rc + ## BCD Assist =20 ADDG6S 011111 ..... ..... ..... - 001001010 - @X diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 821363e7fb..3d26e1144e 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2315,29 +2315,6 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06); =20 /*** Integer shift = ***/ =20 -/* slw & slw. */ -static void gen_slw(DisasContext *ctx) -{ - TCGv t0, t1; - - t0 =3D tcg_temp_new(); - /* AND rS with a mask that is 0 when rB >=3D 0x20 */ -#if defined(TARGET_PPC64) - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); - tcg_gen_sari_tl(t0, t0, 0x3f); -#else - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); - tcg_gen_sari_tl(t0, t0, 0x1f); -#endif - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); - t1 =3D tcg_temp_new(); - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); - tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} =20 /* sraw & sraw. */ static void gen_sraw(DisasContext *ctx) @@ -2379,30 +2356,6 @@ static void gen_srawi(DisasContext *ctx) } } =20 -/* srw & srw. */ -static void gen_srw(DisasContext *ctx) -{ - TCGv t0, t1; - - t0 =3D tcg_temp_new(); - /* AND rS with a mask that is 0 when rB >=3D 0x20 */ -#if defined(TARGET_PPC64) - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); - tcg_gen_sari_tl(t0, t0, 0x3f); -#else - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); - tcg_gen_sari_tl(t0, t0, 0x1f); -#endif - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); - tcg_gen_ext32u_tl(t0, t0); - t1 =3D tcg_temp_new(); - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); - tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} - #if defined(TARGET_PPC64) /* sld & sld. */ static void gen_sld(DisasContext *ctx) @@ -5764,10 +5717,8 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, P= PC_NONE, PPC2_ISA300), GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), -GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), #if defined(TARGET_PPC64) GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 91f9c6c391..9d04b96316 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1406,3 +1406,51 @@ TRANS(HASHST, do_hash, false, gen_helper_HASHST) TRANS(HASHCHK, do_hash, false, gen_helper_HASHCHK) TRANS(HASHSTP, do_hash, true, gen_helper_HASHSTP) TRANS(HASHCHKP, do_hash, true, gen_helper_HASHCHKP) + +static bool trans_SLW(DisasContext *ctx, arg_SLW *a) +{ + TCGv t0, t1; + + t0 =3D tcg_temp_new(); + /* AND rt with a mask that is 0 when rB >=3D 0x20 */ +#if defined(TARGET_PPC64) + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x3a); + tcg_gen_sari_tl(t0, t0, 0x3f); +#else + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x1a); + tcg_gen_sari_tl(t0, t0, 0x1f); +#endif + tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0); + t1 =3D tcg_temp_new(); + tcg_gen_andi_tl(t1, cpu_gpr[a->rb], 0x1f); + tcg_gen_shl_tl(cpu_gpr[a->ra], t0, t1); + tcg_gen_ext32u_tl(cpu_gpr[a->ra], cpu_gpr[a->ra]); + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } + return true; +} + +static bool trans_SRW(DisasContext *ctx, arg_SRW *a) +{ + TCGv t0, t1; + + t0 =3D tcg_temp_new(); + /* AND rt with a mask that is 0 when rB >=3D 0x20 */ +#if defined(TARGET_PPC64) + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x3a); + tcg_gen_sari_tl(t0, t0, 0x3f); +#else + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x1a); + tcg_gen_sari_tl(t0, t0, 0x1f); +#endif + tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0); + tcg_gen_ext32u_tl(t0, t0); + t1 =3D tcg_temp_new(); + tcg_gen_andi_tl(t1, cpu_gpr[a->rb], 0x1f); + tcg_gen_shr_tl(cpu_gpr[a->ra], t0, t1); + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } + return true; +} --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897528; cv=none; d=zohomail.com; s=zohoarc; b=Xefw7a9bxbcykONRqqbaGCga5PR/zC2gNpHTtCPLQZd9KW8tyWihLES6CUSN+PVCd9DKQGT2QeJICOodw2bA7uW6gzLuEDkGqvxvRYw2v+zrVQT80rvW55oJvVfhIi/ozPtAOxbo51YrspiQfKKeymQE7qje9HsA/nZUudEOSW4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787897528; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897529190158500 Content-Type: text/plain; charset="utf-8" From: "Mukesh Kumar Chaurasiya (IBM)" Move sraw and srawi to decodetree specification using the @X_rc format. The existing shift-masking logic from gen_sraw/gen_srawi is preserved verbatim in the new trans_SRAW/trans_SRAWI handlers. Signed-off-by: Mukesh Kumar Chaurasiya (IBM) Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-9-rathc@linu= x.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/helper.h | 2 +- target/ppc/insn32.decode | 2 ++ target/ppc/int_helper.c | 2 +- target/ppc/translate.c | 42 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 41 +++++++++++++++++++++ 5 files changed, 45 insertions(+), 44 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index a0d08d6192..d4a9334ce8 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -64,7 +64,7 @@ DEF_HELPER_4(DIVWE, tl, env, tl, tl, i32) =20 DEF_HELPER_FLAGS_1(POPCNTB, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(CMPB, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_3(sraw, tl, env, tl, tl) +DEF_HELPER_3(SRAW, tl, env, tl, tl) DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 189f9c6fe7..ef0fe12959 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -509,6 +509,8 @@ HASHCHKP 011111 ..... ..... ..... 1010110010 . = @X_DW =20 SLW 011111 ..... ..... ..... 0000011000 . @X_rc SRW 011111 ..... ..... ..... 1000011000 . @X_rc +SRAW 011111 ..... ..... ..... 1100011000 . @X_rc +SRAWI 011111 ..... ..... ..... 1100111000 . @X_rc =20 ## BCD Assist =20 diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index dc55ccadf7..b161f930ec 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -235,7 +235,7 @@ target_ulong helper_CMPB(target_ulong rs, target_ulong = rb) } =20 /* shift right arithmetic helper */ -target_ulong helper_sraw(CPUPPCState *env, target_ulong value, +target_ulong helper_SRAW(CPUPPCState *env, target_ulong value, target_ulong shift) { int32_t ret; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3d26e1144e..53acd54ad4 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2316,46 +2316,6 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06); /*** Integer shift = ***/ =20 =20 -/* sraw & sraw. */ -static void gen_sraw(DisasContext *ctx) -{ - gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env, - cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} - -/* srawi & srawi. */ -static void gen_srawi(DisasContext *ctx) -{ - int sh =3D SH(ctx->opcode); - TCGv dst =3D cpu_gpr[rA(ctx->opcode)]; - TCGv src =3D cpu_gpr[rS(ctx->opcode)]; - if (sh =3D=3D 0) { - tcg_gen_ext32s_tl(dst, src); - tcg_gen_movi_tl(cpu_ca, 0); - if (is_isa300(ctx)) { - tcg_gen_movi_tl(cpu_ca32, 0); - } - } else { - TCGv t0; - tcg_gen_ext32s_tl(dst, src); - tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); - t0 =3D tcg_temp_new(); - tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); - tcg_gen_and_tl(cpu_ca, cpu_ca, t0); - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); - if (is_isa300(ctx)) { - tcg_gen_mov_tl(cpu_ca32, cpu_ca); - } - tcg_gen_sari_tl(dst, dst, sh); - } - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, dst); - } -} - #if defined(TARGET_PPC64) /* sld & sld. */ static void gen_sld(DisasContext *ctx) @@ -5717,8 +5677,6 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PP= C_NONE, PPC2_ISA300), GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), -GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), #if defined(TARGET_PPC64) GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 9d04b96316..234404e459 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1454,3 +1454,44 @@ static bool trans_SRW(DisasContext *ctx, arg_SRW *a) } return true; } + +/* sraw & sraw. */ +static bool trans_SRAW(DisasContext *ctx, arg_SRAW *a) +{ + gen_helper_SRAW(cpu_gpr[a->ra], tcg_env, + cpu_gpr[a->rt], cpu_gpr[a->rb]); + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } + return true; +} + +/* srawi & srawi. */ +static bool trans_SRAWI(DisasContext *ctx, arg_SRAWI *a) +{ + TCGv dst =3D cpu_gpr[a->ra]; + TCGv src =3D cpu_gpr[a->rt]; + if (a->rb =3D=3D 0) { + tcg_gen_ext32s_tl(dst, src); + tcg_gen_movi_tl(cpu_ca, 0); + if (is_isa300(ctx)) { + tcg_gen_movi_tl(cpu_ca32, 0); + } + } else { + TCGv t0; + tcg_gen_ext32s_tl(dst, src); + tcg_gen_andi_tl(cpu_ca, dst, (1ULL << a->rb) - 1); + t0 =3D tcg_temp_new(); + tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); + tcg_gen_and_tl(cpu_ca, cpu_ca, t0); + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); + if (is_isa300(ctx)) { + tcg_gen_mov_tl(cpu_ca32, cpu_ca); + } + tcg_gen_sari_tl(dst, dst, a->rb); + } + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, dst); + } + return true; +} --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897298299158500 Content-Type: text/plain; charset="utf-8" From: Shivani Nittor Convert mcrf to decode tree specification. The functionality was tested by comparing the qemu -D log -d op,in_asm output as well as single stepping gdb. Signed-off-by: Shivani Nittor Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-10-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 6 ++++++ target/ppc/translate.c | 7 ------- target/ppc/translate/misc-impl.c.inc | 6 ++++++ 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index ef0fe12959..f928cd6602 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1452,6 +1452,12 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 - SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync EIEIO 011111 ----- ----- ----- 1101010110 - =20 +# Condition Register Field Instruction + +&XL_bfa bf bfa +@XL_bfa ...... bf:3 .. bfa:3 .. ..... ..... ..... . +MCRF 010011 ... -- ... -- ----- 00000 00000 - @XL_bfa + # Branch History Rolling Buffer (BHRB) Instructions =20 &XFX_bhrbe rt bhrbe diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 53acd54ad4..7e7ef4e32d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3642,12 +3642,6 @@ GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); /* crxor */ GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); =20 -/* mcrf */ -static void gen_mcrf(DisasContext *ctx) -{ - tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]= ); -} - /*** System linkage = ***/ =20 /* rfi (supervisor only) */ @@ -5709,7 +5703,6 @@ GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLO= W), GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_IS= A207), -GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), diff --git a/target/ppc/translate/misc-impl.c.inc b/target/ppc/translate/mi= sc-impl.c.inc index cbf82b1ea0..890fbb209e 100644 --- a/target/ppc/translate/misc-impl.c.inc +++ b/target/ppc/translate/misc-impl.c.inc @@ -155,3 +155,9 @@ static bool trans_ATTN(DisasContext *ctx, arg_ATTN *a) return false; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897511168158500 Content-Type: text/plain; charset="utf-8" From: Amit Machhiwal Move the below instructions to decodetree specification: s{r,l}d, and srad[i] : X-form The changes were verified by validating that the TCG ops generated by these instructions remain the same after these changes. The TCG micro-ops were captured with the '-d op,in_asm' QEMU flag. Move all shift insntructions to one place in insn32.decode Signed-off-by: Sathvika Vasireddy Signed-off-by: Amit Machhiwal Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-11-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/helper.h | 2 +- target/ppc/insn32.decode | 12 ++- target/ppc/int_helper.c | 2 +- target/ppc/translate.c | 96 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 72 ++++++++++++++++ 5 files changed, 82 insertions(+), 102 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index d4a9334ce8..e7bf43bf4b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -74,7 +74,7 @@ DEF_HELPER_FLAGS_1(CBCDTD, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(CMPEQB, TCG_CALL_NO_RWG_SE, i32, tl, tl) DEF_HELPER_FLAGS_1(POPCNTW, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(BPERMD, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_3(srad, tl, env, tl, tl) +DEF_HELPER_3(SRAD, tl, env, tl, tl) DEF_HELPER_FLAGS_0(DARN32, TCG_CALL_NO_RWG, tl) DEF_HELPER_FLAGS_0(DARN64, TCG_CALL_NO_RWG, tl) #endif diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index f928cd6602..12fb4974e4 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -119,7 +119,7 @@ =20 # XS-form with fractured shift amount %xs_sh 1:1 11:5 -&XS rs ra sh rc +&XS rs ra sh rc:bool @XS ...... rs:5 ra:5 ..... ......... . rc:1 &XS sh=3D%= xs_sh =20 %x_frtp 22:4 !function=3Dtimes_2 @@ -512,6 +512,13 @@ SRW 011111 ..... ..... ..... 1000011000 . = @X_rc SRAW 011111 ..... ..... ..... 1100011000 . @X_rc SRAWI 011111 ..... ..... ..... 1100111000 . @X_rc =20 +SLD 011111 ..... ..... ..... 0000011011 . @X_rc +SRD 011111 ..... ..... ..... 1000011011 . @X_rc +SRAD 011111 ..... ..... ..... 1100011010 . @X_rc +SRADI 011111 ..... ..... ..... 110011101 . . @XS + +EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS + ## BCD Assist =20 ADDG6S 011111 ..... ..... ..... - 001001010 - @X @@ -1379,9 +1386,6 @@ DST 011111 ----- ..... ..... 0101010110 -= @X_ea DSTST 011111 ----- ..... ..... 0101110110 - @X_ea DSS 011111 ----- ..... ..... 1100110110 - @X_ea =20 -##Extend Sign Word and Shift Left Immediate XS-form -EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS - ## Load and Reserve Instructions LBARX 011111 ..... ..... ..... 0000110100 . @X_rc LHARX 011111 ..... ..... ..... 0001110100 . @X_rc diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index b161f930ec..8e8076a92c 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -261,7 +261,7 @@ target_ulong helper_SRAW(CPUPPCState *env, target_ulong= value, } =20 #if defined(TARGET_PPC64) -target_ulong helper_srad(CPUPPCState *env, target_ulong value, +target_ulong helper_SRAD(CPUPPCState *env, target_ulong value, target_ulong shift) { int64_t ret; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7e7ef4e32d..45418b4de5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2313,95 +2313,6 @@ static void gen_rldimi(DisasContext *ctx, int mbn, i= nt shn) GEN_PPC64_R4(rldimi, 0x1E, 0x06); #endif =20 -/*** Integer shift = ***/ - - -#if defined(TARGET_PPC64) -/* sld & sld. */ -static void gen_sld(DisasContext *ctx) -{ - TCGv t0, t1; - - t0 =3D tcg_temp_new(); - /* AND rS with a mask that is 0 when rB >=3D 0x40 */ - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); - tcg_gen_sari_tl(t0, t0, 0x3f); - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); - t1 =3D tcg_temp_new(); - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); - tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} - -/* srad & srad. */ -static void gen_srad(DisasContext *ctx) -{ - gen_helper_srad(cpu_gpr[rA(ctx->opcode)], tcg_env, - cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} -/* sradi & sradi. */ -static inline void gen_sradi(DisasContext *ctx, int n) -{ - int sh =3D SH(ctx->opcode) + (n << 5); - TCGv dst =3D cpu_gpr[rA(ctx->opcode)]; - TCGv src =3D cpu_gpr[rS(ctx->opcode)]; - if (sh =3D=3D 0) { - tcg_gen_mov_tl(dst, src); - tcg_gen_movi_tl(cpu_ca, 0); - if (is_isa300(ctx)) { - tcg_gen_movi_tl(cpu_ca32, 0); - } - } else { - TCGv t0; - tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); - t0 =3D tcg_temp_new(); - tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); - tcg_gen_and_tl(cpu_ca, cpu_ca, t0); - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); - if (is_isa300(ctx)) { - tcg_gen_mov_tl(cpu_ca32, cpu_ca); - } - tcg_gen_sari_tl(dst, src, sh); - } - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, dst); - } -} - -static void gen_sradi0(DisasContext *ctx) -{ - gen_sradi(ctx, 0); -} - -static void gen_sradi1(DisasContext *ctx) -{ - gen_sradi(ctx, 1); -} - -/* srd & srd. */ -static void gen_srd(DisasContext *ctx) -{ - TCGv t0, t1; - - t0 =3D tcg_temp_new(); - /* AND rS with a mask that is 0 when rB >=3D 0x40 */ - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); - tcg_gen_sari_tl(t0, t0, 0x3f); - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); - t1 =3D tcg_temp_new(); - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); - tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} -#endif - /*** Addressing modes = ***/ /* Register indirect with immediate index : EA =3D (rA|0) + SIMM */ static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, @@ -5671,13 +5582,6 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, P= PC_NONE, PPC2_ISA300), GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -#if defined(TARGET_PPC64) -GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), -GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), -GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), -GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), -GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), -#endif /* handles lfdp, lxsd, lxssp */ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), /* handles stfdp, stxsd, stxssp */ diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 234404e459..9f669894a3 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -486,6 +486,76 @@ static bool do_add_const_XO(DisasContext *ctx, arg_XO_= ta *a, TCGv const_val, return true; } =20 +static bool do_shift_X_rc(DisasContext *ctx, arg_X_rc *a, + void(*op)(TCGv, TCGv, TCGv)) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + /* AND rt with a mask that is 0 when rb >=3D 0x40 */ + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x39); + tcg_gen_sari_tl(t0, t0, 0x3f); + tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0); + tcg_gen_andi_tl(t1, cpu_gpr[a->rb], 0x3f); + op(cpu_gpr[a->ra], t0, t1); + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_SRAD(DisasContext *ctx, arg_SRAD *a) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + gen_helper_SRAD(cpu_gpr[a->ra], tcg_env, cpu_gpr[a->rt], cpu_gpr[a->rb= ]); + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_SRADI(DisasContext *ctx, arg_SRADI *a) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + int sh =3D a->sh; + TCGv dst =3D cpu_gpr[a->ra]; + TCGv src =3D cpu_gpr[a->rs]; + if (sh =3D=3D 0) { + tcg_gen_mov_tl(dst, src); + tcg_gen_movi_tl(cpu_ca, 0); + if (is_isa300(ctx)) { + tcg_gen_movi_tl(cpu_ca32, 0); + } + } else { + TCGv t0 =3D tcg_temp_new(); + tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); + tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); + tcg_gen_and_tl(cpu_ca, cpu_ca, t0); + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); + if (is_isa300(ctx)) { + tcg_gen_mov_tl(cpu_ca32, cpu_ca); + } + tcg_gen_sari_tl(dst, src, sh); + } + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, dst); + } +#else + qemu_build_not_reached(); +#endif + return true; +} + TRANS(ADD, do_add_XO, false, false); TRANS(ADDC, do_add_XO, false, true); TRANS(ADDE, do_add_XO, true, true); @@ -493,6 +563,8 @@ TRANS(ADDME, do_add_const_XO, tcg_constant_tl(-1LL), tr= ue, true); TRANS(ADDZE, do_add_const_XO, tcg_constant_tl(0), true, true); TRANS(ADDIC, do_add_D, false, true, false, false); TRANS(ADDIC_, do_add_D, false, true, false, true); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897365094154100 Content-Type: text/plain; charset="utf-8" From: Amit Machhiwal Move the below PPC instructions to decodetree specification: st{d,h,w}brx, st{d,w,h,b}cix : X-form The changes were verified by validating that the TCG micro-ops generated by those insns remain the same. These TCG micro-ops were captured with the `-d op,in_asm` QEMU flag. Additionally, remove GEN_STX and GEN_STX_E macros as they are no longer used anywhere else. Signed-off-by: Amit Machhiwal Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-12-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 8 +++ target/ppc/translate.c | 52 +++----------- target/ppc/translate/fixedpoint-impl.c.inc | 79 ++++++++++++++++++++++ 3 files changed, 95 insertions(+), 44 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 12fb4974e4..37f508a5c2 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -372,6 +372,14 @@ STVDX 011111 ..... ..... ..... 0010010001 - = @X STSKU 111110 ..... ..... ............. 0 11 @DD STCXU 111110 ..... ..... ............. 1 11 @DD =20 +STDBRX 011111 ..... ..... ..... 1010010100 - @X +STDCIX 011111 ..... ..... ..... 1111110101 - @X +STWCIX 011111 ..... ..... ..... 1110010101 - @X +STHCIX 011111 ..... ..... ..... 1110110101 - @X +STBCIX 011111 ..... ..... ..... 1111010101 - @X +STHBRX 011111 ..... ..... ..... 1110010110 - @X +STWBRX 011111 ..... ..... ..... 1010010110 - @X + ### Fixed-Point Compare Instructions =20 CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 45418b4de5..749ae56cdf 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2529,23 +2529,6 @@ GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) #endif =20 -/*** Integer store = ***/ -#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) = \ -static void glue(gen_, name##x)(DisasContext *ctx) = \ -{ = \ - TCGv EA; = \ - chk(ctx); = \ - gen_set_access_type(ctx, ACCESS_INT); = \ - EA =3D tcg_temp_new(); = \ - gen_addr_reg_index(ctx, EA); = \ - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); = \ -} -#define GEN_STX(name, stop, opc2, opc3, type) = \ - GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) - -#define GEN_STX_HVRM(name, stop, opc2, opc3, type) = \ - GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) - #define GEN_STEPX(name, stop, opc2, opc3) = \ static void glue(gen_, name##epx)(DisasContext *ctx) = \ { = \ @@ -2565,12 +2548,6 @@ GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) #endif =20 -#if defined(TARGET_PPC64) -GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) -GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) -GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) -GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) -#endif /*** Integer load and store with byte reverse = ***/ =20 /* lhbrx */ @@ -2582,15 +2559,8 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); #if defined(TARGET_PPC64) /* ldbrx */ GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); -/* stdbrx */ -GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); #endif /* TARGET_PPC64 */ =20 -/* sthbrx */ -GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); -/* stwbrx */ -GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); - /*** Integer load and store multiple = ***/ =20 /* lmw */ @@ -5147,9 +5117,17 @@ static int64_t dw_compose_ea(DisasContext *ctx, int = x) return true; \ } \ } while (0) +#define REQUIRE_HVRM(CTX) \ + do { \ + if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ + gen_priv_opc(CTX); \ + return true; \ + } \ + } while (0) #else #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) +#define REQUIRE_HVRM(CTX) do { gen_priv_opc(CTX); return true; } while (0) #endif =20 /* @@ -5756,20 +5734,6 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) #endif =20 -#undef GEN_STX_E -#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) = \ -GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), - -#if defined(TARGET_PPC64) -GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) -GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) -GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) -GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) -GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) -#endif -GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) -GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) - #undef GEN_STEPX #define GEN_STEPX(name, ldop, opc2, opc3) = \ GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, = \ diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 9f669894a3..25a60d3d3a 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -566,6 +566,85 @@ TRANS(ADDIC_, do_add_D, false, true, false, true); TRANS(SLD, do_shift_X_rc, tcg_gen_shl_tl); TRANS(SRD, do_shift_X_rc, tcg_gen_shr_tl); =20 +static bool do_stxx(DisasContext *ctx, arg_X *a, + void(*op)(DisasContext *, TCGv, TCGv), bool is_hvrm) +{ + TCGv ea; + + if (is_hvrm) { + REQUIRE_HVRM(ctx); + } + + gen_set_access_type(ctx, ACCESS_INT); + ea =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + op(ctx, cpu_gpr[a->rt], ea); + + return true; +} + +TRANS(STHBRX, do_stxx, gen_qemu_st16r, 0); +TRANS(STWBRX, do_stxx, gen_qemu_st32r, 0); + +static bool trans_STDBRX(DisasContext *ctx, arg_STDBRX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, DBRX); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st64r_i64, false); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STDCIX(DisasContext *ctx, arg_STDCIX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, CILDST); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st64_i64, true); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STWCIX(DisasContext *ctx, arg_STWCIX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, CILDST); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st32, true); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STHCIX(DisasContext *ctx, arg_STHCIX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, CILDST); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st16, true); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STBCIX(DisasContext *ctx, arg_STBCIX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, CILDST); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st8, true); +#else + qemu_build_not_reached(); +#endif + return true; +} + static bool trans_SUBFIC(DisasContext *ctx, arg_D *a) { gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897356549158500 Content-Type: text/plain; charset="utf-8" From: Aboorva Devarajan Move below instructions to decodetree specification: lwat, stwat : X-form (word atomic, ISA 3.0) ldat, stdat : X-form (doubleword atomic, ISA 3.0) The legacy gen_ld_atomic()/gen_st_atomic() functions that read register fields and the function code from ctx->opcode are replaced by new do_ld_atomic()/do_st_atomic() helpers in fixedpoint-impl.c.inc that use the pre-extracted decodetree argument fields (a->rt, a->ra, a->rb) directly. The RB field carries the Function Code (FC) selecting the atomic operation. gen_fetch_inc_conditional() is similarly moved and refactored to accept the destination register number as an explicit parameter instead of extracting it from ctx->opcode. Checked with '-d in_asm,op'. The printed TCG ops may differ from the pre-refactor log because EA now uses do_ea_calc(ctx, ra, 0), which lowers as GPR[ra] + 0 (then narrow in 32-bit mode) instead of mov/ext32u from ra alone. Signed-off-by: Aboorva Devarajan Reviewed-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-13-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 7 + target/ppc/translate.c | 212 -------------------- target/ppc/translate/fixedpoint-impl.c.inc | 214 +++++++++++++++++++++ 3 files changed, 221 insertions(+), 212 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 37f508a5c2..e8326a9d0b 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -343,6 +343,13 @@ LSKU 111010 ..... ..... ............. 0 11 = @DD LCXU 111010 ..... ..... ............. 1 11 @DD =20 =20 +### Fixed-Point Atomic Load/Store Instructions + +LWAT 011111 ..... ..... ..... 1001000110 - @X +STWAT 011111 ..... ..... ..... 1011000110 - @X +LDAT 011111 ..... ..... ..... 1001100110 - @X +STDAT 011111 ..... ..... ..... 1011100110 - @X + ### Fixed-Point Store Instructions =20 STB 100110 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 749ae56cdf..c44cffb5e8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2741,212 +2741,6 @@ static void gen_isync(DisasContext *ctx) ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } =20 -static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, - TCGv EA, TCGCond cond, int addend) -{ - TCGv t =3D tcg_temp_new(); - TCGv t2 =3D tcg_temp_new(); - TCGv u =3D tcg_temp_new(); - - tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); - tcg_gen_addi_tl(t2, EA, memop_size(memop)); - tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); - tcg_gen_addi_tl(u, t, addend); - - /* E.g. for fetch and increment bounded... */ - /* mem(EA,s) =3D (t !=3D t2 ? u =3D t + 1 : t) */ - tcg_gen_movcond_tl(cond, u, t, t2, u, t); - tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); - - /* RT =3D (t !=3D t2 ? t : u =3D 1<<(s*8-1)) */ - tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, - tcg_constant_tl(1 << (memop_size(memop) * 8 - 1))); -} - -static void gen_ld_atomic(DisasContext *ctx, MemOp memop) -{ - uint32_t gpr_FC =3D FC(ctx->opcode); - TCGv EA =3D tcg_temp_new(); - int rt =3D rD(ctx->opcode); - bool need_serial; - TCGv src, dst; - - gen_addr_register(ctx, EA); - dst =3D cpu_gpr[rt]; - src =3D cpu_gpr[(rt + 1) & 31]; - - need_serial =3D false; - memop |=3D MO_ALIGN; - switch (gpr_FC) { - case 0: /* Fetch and add */ - tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 1: /* Fetch and xor */ - tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 2: /* Fetch and or */ - tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 3: /* Fetch and 'and' */ - tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 4: /* Fetch and max unsigned */ - tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 5: /* Fetch and max signed */ - tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 6: /* Fetch and min unsigned */ - tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 7: /* Fetch and min signed */ - tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 8: /* Swap */ - tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); - break; - - case 16: /* Compare and swap not equal */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - need_serial =3D true; - } else { - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); - if ((memop & MO_SIZE) =3D=3D MO_64 || TARGET_LONG_BITS =3D=3D = 32) { - tcg_gen_mov_tl(t1, src); - } else { - tcg_gen_ext32u_tl(t1, src); - } - tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, - cpu_gpr[(rt + 2) & 31], t0); - tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); - tcg_gen_mov_tl(dst, t0); - } - break; - - case 24: /* Fetch and increment bounded */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - need_serial =3D true; - } else { - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); - } - break; - case 25: /* Fetch and increment equal */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - need_serial =3D true; - } else { - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); - } - break; - case 28: /* Fetch and decrement bounded */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - need_serial =3D true; - } else { - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); - } - break; - - default: - /* invoke data storage error handler */ - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); - } - - if (need_serial) { - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(tcg_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - } -} - -static void gen_lwat(DisasContext *ctx) -{ - gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); -} - -#ifdef TARGET_PPC64 -static void gen_ldat(DisasContext *ctx) -{ - gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); -} -#endif - -static void gen_st_atomic(DisasContext *ctx, MemOp memop) -{ - uint32_t gpr_FC =3D FC(ctx->opcode); - TCGv EA =3D tcg_temp_new(); - TCGv src, discard; - - gen_addr_register(ctx, EA); - src =3D cpu_gpr[rD(ctx->opcode)]; - discard =3D tcg_temp_new(); - - memop |=3D MO_ALIGN; - switch (gpr_FC) { - case 0: /* add and Store */ - tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); - break; - case 1: /* xor and Store */ - tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); - break; - case 2: /* Or and Store */ - tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); - break; - case 3: /* 'and' and Store */ - tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); - break; - case 4: /* Store max unsigned */ - tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); - break; - case 5: /* Store max signed */ - tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); - break; - case 6: /* Store min unsigned */ - tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); - break; - case 7: /* Store min signed */ - tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); - break; - case 24: /* Store twin */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(tcg_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - } else { - TCGv t =3D tcg_temp_new(); - TCGv t2 =3D tcg_temp_new(); - TCGv s =3D tcg_temp_new(); - TCGv s2 =3D tcg_temp_new(); - TCGv ea_plus_s =3D tcg_temp_new(); - - tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); - tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop)); - tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); - tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); - tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); - tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); - tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); - } - break; - default: - /* invoke data storage error handler */ - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); - } -} - -static void gen_stwat(DisasContext *ctx) -{ - gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); -} - -#ifdef TARGET_PPC64 -static void gen_stdat(DisasContext *ctx) -{ - gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); -} -#endif - /* wait */ static void gen_wait(DisasContext *ctx) { @@ -5571,12 +5365,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_= STRING), GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), -GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), -#if defined(TARGET_PPC64) -GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), -#endif /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 25a60d3d3a..f9435f4a00 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1646,3 +1646,217 @@ static bool trans_SRAWI(DisasContext *ctx, arg_SRAW= I *a) } return true; } + +static void do_fetch_inc_conditional(DisasContext *ctx, MemOp memop, + TCGv EA, int rt, + TCGCond cond, int addend) +{ + TCGv t =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_new(); + TCGv u =3D tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); + tcg_gen_addi_tl(t2, EA, memop_size(memop)); + tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); + tcg_gen_addi_tl(u, t, addend); + + /* mem(EA,s) =3D (t cond t2 ? u =3D t + addend : t) */ + tcg_gen_movcond_tl(cond, u, t, t2, u, t); + tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); + + /* RT =3D (t cond t2 ? t : 1<<(s*8-1)) */ + tcg_gen_movcond_tl(cond, cpu_gpr[rt], t, t2, t, + tcg_constant_tl(1 << (memop_size(memop) * 8 - 1))); +} + +/* + * Fixed-Point Atomic Load/Store Instructions + * + * In the X-form encoding the RB field carries the Function Code (FC) + * that selects the atomic operation. EA is computed from RA alone. + */ +static bool do_ld_atomic(DisasContext *ctx, arg_X *a, MemOp memop) +{ + TCGv EA, dst, src; + bool need_serial; + + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + + EA =3D do_ea_calc(ctx, a->ra, tcg_constant_tl(0)); + dst =3D cpu_gpr[a->rt]; + src =3D cpu_gpr[(a->rt + 1) & 31]; + + need_serial =3D false; + memop |=3D MO_ALIGN; + switch (a->rb) { + case 0: /* Fetch and add */ + tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 1: /* Fetch and xor */ + tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 2: /* Fetch and or */ + tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 3: /* Fetch and 'and' */ + tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 4: /* Fetch and max unsigned */ + tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 5: /* Fetch and max signed */ + tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 6: /* Fetch and min unsigned */ + tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 7: /* Fetch and min signed */ + tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 8: /* Swap */ + tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); + break; + + case 16: /* Compare and swap not equal */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); + if ((memop & MO_SIZE) =3D=3D MO_64 || TARGET_LONG_BITS =3D=3D = 32) { + tcg_gen_mov_tl(t1, src); + } else { + tcg_gen_ext32u_tl(t1, src); + } + tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, + cpu_gpr[(a->rt + 2) & 31], t0); + tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); + tcg_gen_mov_tl(dst, t0); + } + break; + + case 24: /* Fetch and increment bounded */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_NE, 1= ); + } + break; + case 25: /* Fetch and increment equal */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_EQ, 1= ); + } + break; + case 28: /* Fetch and decrement bounded */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_NE, -= 1); + } + break; + + default: + /* invoke data storage error handler */ + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); + } + + if (need_serial) { + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(tcg_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + } + return true; +} + +static bool do_st_atomic(DisasContext *ctx, arg_X *a, MemOp memop) +{ + TCGv EA, src, discard; + + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + + EA =3D do_ea_calc(ctx, a->ra, tcg_constant_tl(0)); + src =3D cpu_gpr[a->rt]; + discard =3D tcg_temp_new(); + + memop |=3D MO_ALIGN; + switch (a->rb) { + case 0: /* add and Store */ + tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 1: /* xor and Store */ + tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 2: /* Or and Store */ + tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 3: /* 'and' and Store */ + tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 4: /* Store max unsigned */ + tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; + case 5: /* Store max signed */ + tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; + case 6: /* Store min unsigned */ + tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; + case 7: /* Store min signed */ + tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; + case 24: /* Store twin */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(tcg_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + } else { + TCGv t =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_new(); + TCGv s =3D tcg_temp_new(); + TCGv s2 =3D tcg_temp_new(); + TCGv ea_plus_s =3D tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); + tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop)); + tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); + tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); + tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); + tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); + tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); + } + break; + default: + /* invoke data storage error handler */ + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); + } + return true; +} + +TRANS(LWAT, do_ld_atomic, DEF_MEMOP(MO_UL)) +TRANS(STWAT, do_st_atomic, DEF_MEMOP(MO_UL)) + +static bool trans_LDAT(DisasContext *ctx, arg_LDAT *a) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + return do_ld_atomic(ctx, a, DEF_MEMOP(MO_UQ)); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STDAT(DisasContext *ctx, arg_STDAT *a) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + return do_st_atomic(ctx, a, DEF_MEMOP(MO_UQ)); +#else + qemu_build_not_reached(); +#endif + return true; +} --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897336; cv=none; d=zohomail.com; s=zohoarc; b=UL/eI80xl2Zw3a0pCaI8Wdgg5ez4bZ3pdkPLomQkIU+suwXdVELZwAj95jHp+YUpjjP6vgOHRDOmkv2zsj/UQ8Dj/8HP907SumGU8TL3FmeZrm48amDTjmz5xh3D+FIXFgiazLroGebcZ+uavxKRCVUC088uEbaOI1MwDVunuV0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787897336; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897338420158500 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Moving the following instructions to decodetree specification : isync The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Ojaswin Mujoo Reviewed-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-14-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 1 + target/ppc/translate.c | 15 --------------- target/ppc/translate/storage-ctrl-impl.c.inc | 17 +++++++++++++++++ 3 files changed, 18 insertions(+), 15 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index e8326a9d0b..6fb7754566 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1470,6 +1470,7 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 - @X_sync ...... .. l:3 ... sc:2 ..... .......... . &X_sync SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync EIEIO 011111 ----- ----- ----- 1101010110 - +ISYNC 010011 ----- ----- ----- 0010010110 - =20 # Condition Register Field Instruction =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c44cffb5e8..84589716b3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2727,20 +2727,6 @@ static inline void gen_check_tlb_flush(DisasContext = *ctx, bool global) static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } #endif =20 -/* isync */ -static void gen_isync(DisasContext *ctx) -{ - /* - * We need to check for a pending TLB flush. This can only happen in - * kernel mode however so check MSR_PR - */ - if (!ctx->pr) { - gen_check_tlb_flush(ctx, false); - } - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; -} - /* wait */ static void gen_wait(DisasContext *ctx) { @@ -5364,7 +5350,6 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_S= TRING), GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), -GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/tran= slate/storage-ctrl-impl.c.inc index b8b4454663..943229c438 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -155,6 +155,23 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE= *a) return true; } =20 +static bool trans_ISYNC(DisasContext *ctx, arg_ISYNC *a) +{ + REQUIRE_INSNS_FLAGS(ctx, MEM); + + /* + * We need to check for a pending TLB flush. This can only happen in + * kernel mode however so check MSR_PR + */ + if (!ctx->pr) { + gen_check_tlb_flush(ctx, false); + } + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; + + return true; +} + static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a) { REQUIRE_64BIT(ctx); --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897336; cv=none; d=zohomail.com; s=zohoarc; b=XFPTdAEbjsf5nT5BRmpZ2fDiyFm5oDKwJ6EscpUgx3C+Pg+hzyJSbxpUsh2QdsUGGv5CxDEqNrk54OwYlyFj+eS2qwIipttYo9OwScQyTxgD2FGtry+71jtfWTiLUqCnR6wIOsPJWq78eHrrcwzI7fsrk+y/S4x7Zk9SJftUCt0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=vmbFi2FtwFYQipr7p a0CPlFTwUI16OAIoQBLZc/wJwI=; b=BpMWkroqWF6TjsNijuZueicWwoHaBKS3m w/zNIp7X/TRbmM9zAgEPMuICjMlDUAYTEUvkyxq0k6DGczwYIG7jhx8CdIVSASVy vpTejs6fJOLj4GywJvBA2c0pYTlEc6PSZfL+25eb6wRG23v92xbaO0BEGfOMUTj/ j3tbIBwshGHH0JGPmOSbP1wW6bMmWmkW3hS4us8/mdCTVrWzEkzdBy+nsE71qZRZ Nb2m+nMvcDwvaAhBnzYhi/CaxROoDW1SFHJy7Tywnl36g9CVB0vkrWFejSKOKtR9 4wHdYY38gefJYLYU5J+zirKsRMtvd7eVioPrumJcI7jR6WUUAJdJQ== From: Harsh Prateek Bora To: qemu-devel@nongnu.org Cc: Ojaswin Mujoo , Nikhil Kumar Singh , Glenn Miles , Amit Machhiwal , Chinmay Rath , Aniket Sahu Subject: [PULL 18/41] target/ppc: Convert b{a, l, la} to decode tree Date: Fri, 28 Aug 2026 11:36:53 +0530 Message-ID: <20260828060716.91672-19-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com> References: <20260828060716.91672-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Dy3obSkPSLh1Q8yXD-vbBjcx9yW_yiml X-Proofpoint-ORIG-GUID: Dy3obSkPSLh1Q8yXD-vbBjcx9yW_yiml X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX/uQjyrM9qw+a ORj7y6HCuuO8diaxprpaEQssfiIN6RuSRI8AETAxma1DBKABmYuznqgnQCG+jJujZ3DlFUJ/83D 7MrrsCOV9nictQf4PWY2Q0G0t5HGzN3IsmVi2VrxOQBlX4RlWGOw/1ibeZyWC2Ndg0t9y58v1U3 q9E9NXBrwANtPfF3/OBV5ayEBqW8pIx1R88jxzVEL2e7MoZ0/2GZyReZ5rwKmkwp7xVSjkeVgVP gHrF6BUeO1L+ynkKPlBCUV6VLpJC9HmBRMV/LLY46cXJ6ex0sMIrqwoiddUPxAFamZ+a8/s1e3I 20E6QGPndPGG/DAwGn51ruqHLOkuLRPNyyzzSh70Qkz/Eit9WwfPkdLZSW+cV9P9t1SBJHT1zPf rNywMHbwg9bp968Zh7icg9yDJFJ/EQLVRjynFJ4HecbEAJ1bX0JpgX6USavSBIWpbR5X/xgGCrn /ujL9Wg8tQIFdOxBjdw== X-Authority-Analysis: v=2.4 cv=QsRuG1yd c=1 sm=1 tr=0 ts=6a9125d2 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=Sv0fKeRqtYgA:10 a=f7IdgyKtn90A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=8uLd_aw9J8tj_XdJNvAA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX5MeV/eKxFCSH ZFCRTSdWHXZeWq1DSndqVxkkD1QkJu7M3WY7jBs6dQmGIFa+h+aqfay7RnmReFr6dj6F5bbALO9 ygvYHfq1abgrhtce3gJiF4glXKX5Oeo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_01,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280050 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897338432158500 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Convert b, ba, bl and bla to decode tree specification. The functionality was tested by comparing the qemu -D log -d op,in_asm output as well as single stepping gdb to confirm LR was correctly populated only when LK is set. Signed-off-by: Ojaswin Mujoo Reviewed-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-15-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/internal.h | 7 ------- target/ppc/insn32.decode | 7 +++++++ target/ppc/translate.c | 24 ------------------------ target/ppc/translate/branch-impl.c.inc | 24 ++++++++++++++++++++++++ 4 files changed, 31 insertions(+), 31 deletions(-) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index a3bb12afd9..a20a0f9f7e 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -197,13 +197,6 @@ EXTRACT_HELPER(L, 16, 2); EXTRACT_HELPER(WC, 21, 2); EXTRACT_HELPER(PL, 16, 2); =20 -/*** Jump target decoding = ***/ -/* Immediate address */ -static inline target_ulong LI(uint32_t opcode) -{ - return (opcode >> 0) & 0x03FFFFFC; -} - static inline uint32_t BD(uint32_t opcode) { return (opcode >> 0) & 0xFFFC; diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 6fb7754566..0c58899429 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1486,6 +1486,13 @@ MCRF 010011 ... -- ... -- ----- 00000 000= 00 - @XL_bfa MFBHRBE 011111 ..... ..... ..... 0100101110 - @XFX_bhrbe CLRBHRB 011111 ----- ----- ----- 0110101110 - =20 +# Branch Instructions +%li 2:24 !function=3Dtimes_4 +&I_b li aa:bool lk:bool +@I_b ...... ........................ aa:1 lk:1 &I_b li=3D%li + +B 010010 ........................ . . @I_b + ## Misc POWER instructions =20 ATTN 000000 00000 00000 00000 0100000000 0 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 84589716b3..3c6e2da8ce 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3089,29 +3089,6 @@ static inline void gen_setlr(DisasContext *ctx, targ= et_ulong nip) tcg_gen_movi_tl(cpu_lr, nip); } =20 -/* b ba bl bla */ -static void gen_b(DisasContext *ctx) -{ - target_ulong li, target; - - /* sign extend LI */ - li =3D LI(ctx->opcode); - li =3D (li ^ 0x02000000) - 0x02000000; - if (likely(AA(ctx->opcode) =3D=3D 0)) { - target =3D ctx->cia + li; - } else { - target =3D li; - } - if (LK(ctx->opcode)) { - gen_setlr(ctx, ctx->base.pc_next); - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL); - } else { - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER); - } - gen_goto_tb(ctx, 0, target); - ctx->base.is_jmp =3D DISAS_NORETURN; -} - #define BCOND_IM 0 #define BCOND_LR 1 #define BCOND_CTR 2 @@ -5353,7 +5330,6 @@ GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_= STRING), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), -GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc index 9ade0c659a..745f71afd1 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -31,3 +31,27 @@ static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) return true; } #endif + +static bool trans_B(DisasContext *ctx, arg_I_b *a) +{ + target_ulong target, li; + + /* sign extend LI */ + li =3D (a->li ^ 0x02000000) - 0x02000000; + + if (likely(a->aa =3D=3D 0)) { + target =3D ctx->cia + li; + } else { + target =3D li; + } + if (a->lk) { + gen_setlr(ctx, ctx->base.pc_next); + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL); + } else { + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER); + } + gen_goto_tb(ctx, 0, target); + ctx->base.is_jmp =3D DISAS_NORETURN; + + return true; +} --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897360; cv=none; d=zohomail.com; s=zohoarc; b=bjFg/o3AWuS/Eg7ttghMpgVXg3VbbYpvKAwfF6Gj49V8xZP1VuIWtXFlzQ4+KJQIKpVN2Bm6chOqL+t2ZFCY8hM+8a7CBdLd1XbVvfKdYQ0VTLmqIZLWYM5qfR2uIJMvHxpr1gyNUti5FqEgBzFFa+JiTBNcxiR01W9ts/xtRYo= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=VYr9YHIiy2spLOcFy Pdk84VfDo1lfbww0FFqlGoUMco=; b=rCL4Bp6rJJYMuQyXOsPvBzmqXECus76s6 fQoE6fxs4xqNiJFxmKBeR07fXsn3s4b0hgKwzSY55gpQ7FU+Qsx5utCB0ap8tk1n IudIgGBXE8j1lXpEf6JdrpTplnfmRwAZ0JbywLQyjoS/210XHIxBXirJkfELhhyt 3LaswO+RjSiBgdCfkS8XkDBXW4ro0UoEGpbu6hI3fVYM/ldl1Z0EbdeRs/qh8MUO GvdRIZkQPUPo0Bn+eeGPP8ygQeGB2Vr8+CWt+fWVGhkM+R0nti2YB5CDhuKl3xVf P5oyFzUpFF0Y4tY5ZeXhhzpzd6S5h0BzYQd5WuBoYsCb34v6NM+Fg== From: Harsh Prateek Bora To: qemu-devel@nongnu.org Cc: Ojaswin Mujoo , Glenn Miles , Amit Machhiwal , Chinmay Rath , Aniket Sahu Subject: [PULL 19/41] target/ppc: move various conditional branch insns to decodetree Date: Fri, 28 Aug 2026 11:36:54 +0530 Message-ID: <20260828060716.91672-20-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com> References: <20260828060716.91672-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX0Hx+IDXUJuNq 1KasXeggEZFpFFWYcgGwCIip5u2MWTfjtxCIEwfUIMWIsKOdJ6PuRh+RFV6RGkr4rIaX9Sa5JT2 YE/5Mnn/G2az9paSwgEpdpoGtS5tSpI= X-Proofpoint-GUID: lmVmnu4wd_-m1RGaOaqNSlCAdKxF3GC_ X-Proofpoint-ORIG-GUID: lmVmnu4wd_-m1RGaOaqNSlCAdKxF3GC_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX9ZFvq+01SPcn 1qw4hhe59OYehgCjbY6nxCpOWRpWx4HOuurWZrKGpYFo+9TivMTCu2P6DMCPcwpgtqkguSq2M4+ jrqafkZJH28sz40/2sL4mXZWDxyhVN2wxuvQKv7A+COJOHZrJWqf94k8S/OiaGby5ul+Nh7/lfe tdManf0qkW2DQTgkMgxuowtJ3jDNWOpn8GA6rTgKEAc79FcW7OG4uYZ+05VtPaR3laXy5hAuy2D xXW6x94P9lU3/Y4+Hdbhn4O1gBn3JcU4pzpQ5NSrDU2Kldp96ufkuIm6qeRCej7qHHVFhLzxUSG 02ORyC1Wbe1OrxCiXYO5eJzSyameFV3GuZcCbqwYicTUH6nTyxe22hnedaSCyLAf9E0039z/V2L hbhFiXI4DLZVL/S4tSObNvbLPTeytKz0umJfVQkz4ORdVtZciTSC1oE8vwI66U8Kfq4CwpOtkvl CQwTct7ufqNvglYCxLA== X-Authority-Analysis: v=2.4 cv=H7brBeYi c=1 sm=1 tr=0 ts=6a9125d4 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=Sv0fKeRqtYgA:10 a=f7IdgyKtn90A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=CKxRzG1O2kzciCs865QA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_01,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 bulkscore=0 adultscore=0 priorityscore=1501 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280050 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897360549158500 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Convert the following instructions to decodetree specification: bc bca bcl bcla bclr bclrl bcctr bcctrl bctar bctarl The branch was tested by comparing the qemu -D log -d op,in_asm output for each instruction and also for the various combinations of branch option (BO) bits for the conditional branch instructions. Additionally, gdb was used to confirm the LR and other register's behavior is consistent to legacy behavior. Further, the changes also pass a boot test into Fedora distro. Signed-off-by: Ojaswin Mujoo Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-16-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 13 +++ target/ppc/translate.c | 148 ----------------------- target/ppc/translate/branch-impl.c.inc | 156 +++++++++++++++++++++++++ 3 files changed, 169 insertions(+), 148 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 0c58899429..e7cc36bd6c 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1493,6 +1493,19 @@ CLRBHRB 011111 ----- ----- ----- 0110101110 - =20 B 010010 ........................ . . @I_b =20 +%bd 2:14 !function=3Dtimes_4 +&bcond bo:uint32_t bi bd aa:bool lk:bool +@B_bcond ...... bo:5 bi:5 .............. aa:1 lk:1 &bcond bd=3D%bd + +BC 010000 ..... ..... .............. . . @B_bcond + +&bclr bo bi bh lk:bool +@XL_bclr ...... bo:5 bi:5 --- bh:2 .......... lk:1 &bclr + +BCLR 010011 ..... ..... ---.. 0000010000 . @XL_bclr +BCCTR 010011 ..... ..... ---.. 1000010000 . @XL_bclr +BCTAR 010011 ..... ..... ---.. 1000110000 . @XL_bclr + ## Misc POWER instructions =20 ATTN 000000 00000 00000 00000 0100000000 0 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3c6e2da8ce..f5b1446d7a 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3089,150 +3089,6 @@ static inline void gen_setlr(DisasContext *ctx, tar= get_ulong nip) tcg_gen_movi_tl(cpu_lr, nip); } =20 -#define BCOND_IM 0 -#define BCOND_LR 1 -#define BCOND_CTR 2 -#define BCOND_TAR 3 - -static void gen_bcond(DisasContext *ctx, int type) -{ - uint32_t bo =3D BO(ctx->opcode); - TCGLabel *l1; - TCGv target; - target_long bhrb_type =3D BHRB_TYPE_OTHER; - - if (type =3D=3D BCOND_LR || type =3D=3D BCOND_CTR || type =3D=3D BCOND= _TAR) { - target =3D tcg_temp_new(); - if (type =3D=3D BCOND_CTR) { - tcg_gen_mov_tl(target, cpu_ctr); - } else if (type =3D=3D BCOND_TAR) { - gen_load_spr(target, SPR_TAR); - } else { - tcg_gen_mov_tl(target, cpu_lr); - } - if (!LK(ctx->opcode)) { - bhrb_type |=3D BHRB_TYPE_INDIRECT; - } - bhrb_type |=3D BHRB_TYPE_XL_FORM; - } else { - target =3D NULL; - } - if (LK(ctx->opcode)) { - gen_setlr(ctx, ctx->base.pc_next); - bhrb_type |=3D BHRB_TYPE_CALL; - } - l1 =3D gen_new_label(); - if ((bo & 0x4) =3D=3D 0) { - /* Decrement and test CTR */ - TCGv temp =3D tcg_temp_new(); - - if (type =3D=3D BCOND_CTR) { - /* - * All ISAs up to v3 describe this form of bcctr as invalid but - * some processors, ie. 64-bit server processors compliant with - * arch 2.x, do implement a "test and decrement" logic instead, - * as described in their respective UMs. This logic involves C= TR - * to act as both the branch target and a counter, which makes - * it basically useless and thus never used in real code. - * - * This form was hence chosen to trigger extra micro-architect= ural - * side-effect on real HW needed for the Spectre v2 workaround. - * It is up to guests that implement such workaround, ie. linu= x, to - * use this form in a way it just triggers the side-effect wit= hout - * doing anything else harmful. - */ - if (unlikely(!is_book3s_arch2x(ctx))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - - if (NARROW_MODE(ctx)) { - tcg_gen_ext32u_tl(temp, cpu_ctr); - } else { - tcg_gen_mov_tl(temp, cpu_ctr); - } - if (bo & 0x2) { - tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); - } else { - tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); - } - tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); - } else { - tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); - if (NARROW_MODE(ctx)) { - tcg_gen_ext32u_tl(temp, cpu_ctr); - } else { - tcg_gen_mov_tl(temp, cpu_ctr); - } - if (bo & 0x2) { - tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); - } else { - tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); - } - } - bhrb_type |=3D BHRB_TYPE_COND; - } - if ((bo & 0x10) =3D=3D 0) { - /* Test CR */ - uint32_t bi =3D BI(ctx->opcode); - uint32_t mask =3D 0x08 >> (bi & 0x03); - TCGv_i32 temp =3D tcg_temp_new_i32(); - - if (bo & 0x8) { - tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); - tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); - } else { - tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); - tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); - } - bhrb_type |=3D BHRB_TYPE_COND; - } - - gen_update_branch_history(ctx, ctx->cia, target, bhrb_type); - - if (type =3D=3D BCOND_IM) { - target_ulong li =3D (target_long)((int16_t)(BD(ctx->opcode))); - if (likely(AA(ctx->opcode) =3D=3D 0)) { - gen_goto_tb(ctx, 0, ctx->cia + li); - } else { - gen_goto_tb(ctx, 0, li); - } - } else { - if (NARROW_MODE(ctx)) { - tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); - } else { - tcg_gen_andi_tl(cpu_nip, target, ~3); - } - gen_lookup_and_goto_ptr(ctx); - } - if ((bo & 0x14) !=3D 0x14) { - /* fallthrough case */ - gen_set_label(l1); - gen_goto_tb(ctx, 1, ctx->base.pc_next); - } - ctx->base.is_jmp =3D DISAS_NORETURN; -} - -static void gen_bc(DisasContext *ctx) -{ - gen_bcond(ctx, BCOND_IM); -} - -static void gen_bcctr(DisasContext *ctx) -{ - gen_bcond(ctx, BCOND_CTR); -} - -static void gen_bclr(DisasContext *ctx) -{ - gen_bcond(ctx, BCOND_LR); -} - -static void gen_bctar(DisasContext *ctx) -{ - gen_bcond(ctx, BCOND_TAR); -} - /*** Condition register logical = ***/ #define GEN_CRLOGIC(name, tcg_op, opc) = \ static void glue(gen_, name)(DisasContext *ctx) = \ @@ -5330,10 +5186,6 @@ GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC= _STRING), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), -GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), -GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), -GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), -GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_IS= A207), GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc index 745f71afd1..c51fd9b13e 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -55,3 +55,159 @@ static bool trans_B(DisasContext *ctx, arg_I_b *a) =20 return true; } + +#define BCOND_IM 0 +#define BCOND_LR 1 +#define BCOND_CTR 2 +#define BCOND_TAR 3 + +static bool bcond_helper(DisasContext *ctx, int type, uint32_t bo, int bi, + int bd, int bh, bool aa, bool lk) +{ + TCGLabel *l1; + TCGv target; + target_long bhrb_type =3D BHRB_TYPE_OTHER; + + if (type =3D=3D BCOND_IM && bh !=3D -1) { + /* BCOND_IM should never use bh */ + return false; + } else if (type !=3D BCOND_IM && (bd !=3D -1 || aa !=3D 0)) { + /* Other BCOND types should never use bd or aa */ + return false; + } + + if (type =3D=3D BCOND_LR || type =3D=3D BCOND_CTR || type =3D=3D BCOND= _TAR) { + target =3D tcg_temp_new(); + if (type =3D=3D BCOND_CTR) { + tcg_gen_mov_tl(target, cpu_ctr); + } else if (type =3D=3D BCOND_TAR) { + gen_load_spr(target, SPR_TAR); + } else { + tcg_gen_mov_tl(target, cpu_lr); + } + if (!lk) { + bhrb_type |=3D BHRB_TYPE_INDIRECT; + } + bhrb_type |=3D BHRB_TYPE_XL_FORM; + } else { + target =3D NULL; + } + if (lk) { + gen_setlr(ctx, ctx->base.pc_next); + bhrb_type |=3D BHRB_TYPE_CALL; + } + l1 =3D gen_new_label(); + if ((bo & 0x4) =3D=3D 0) { + /* Decrement and test CTR */ + TCGv temp =3D tcg_temp_new(); + + if (type =3D=3D BCOND_CTR) { + /* + * All ISAs up to v3 describe this form of bcctr as invalid but + * some processors, ie. 64-bit server processors compliant with + * arch 2.x, do implement a "test and decrement" logic instead, + * as described in their respective UMs. This logic involves C= TR + * to act as both the branch target and a counter, which makes + * it basically useless and thus never used in real code. + * + * This form was hence chosen to trigger extra micro-architect= ural + * side-effect on real HW needed for the Spectre v2 workaround. + * It is up to guests that implement such workaround, ie. linu= x, to + * use this form in a way it just triggers the side-effect wit= hout + * doing anything else harmful. + */ + if (unlikely(!is_book3s_arch2x(ctx))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + if (NARROW_MODE(ctx)) { + tcg_gen_ext32u_tl(temp, cpu_ctr); + } else { + tcg_gen_mov_tl(temp, cpu_ctr); + } + if (bo & 0x2) { + tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); + } else { + tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); + } + tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); + } else { + tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); + if (NARROW_MODE(ctx)) { + tcg_gen_ext32u_tl(temp, cpu_ctr); + } else { + tcg_gen_mov_tl(temp, cpu_ctr); + } + if (bo & 0x2) { + tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); + } else { + tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); + } + } + bhrb_type |=3D BHRB_TYPE_COND; + } + if ((bo & 0x10) =3D=3D 0) { + /* Test CR */ + uint32_t mask =3D 0x08 >> (bi & 0x03); + TCGv_i32 temp =3D tcg_temp_new_i32(); + + if (bo & 0x8) { + tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); + tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); + } else { + tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); + tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); + } + bhrb_type |=3D BHRB_TYPE_COND; + } + + gen_update_branch_history(ctx, ctx->cia, target, bhrb_type); + + if (type =3D=3D BCOND_IM) { + target_ulong li =3D (target_long)((int16_t)(bd)); + if (likely(aa =3D=3D 0)) { + gen_goto_tb(ctx, 0, ctx->cia + li); + } else { + gen_goto_tb(ctx, 0, li); + } + } else { + if (NARROW_MODE(ctx)) { + tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); + } else { + tcg_gen_andi_tl(cpu_nip, target, ~3); + } + gen_lookup_and_goto_ptr(ctx); + } + if ((bo & 0x14) !=3D 0x14) { + /* fallthrough case */ + gen_set_label(l1); + gen_goto_tb(ctx, 1, ctx->base.pc_next); + } + ctx->base.is_jmp =3D DISAS_NORETURN; + + return true; +} + +static bool trans_BC(DisasContext *ctx, arg_bcond *a) +{ + /* + * bh is not used for bc variants hence we pass -1 + */ + return bcond_helper(ctx, BCOND_IM, a->bo, a->bi, a->bd, -1, a->aa, a->= lk); +} + +/* + * This helper is shared by bclr, bcctr and bctar. + */ +static bool bclr_helper(DisasContext *ctx, arg_bclr *a, int type) +{ + /* + * bd and aa is not used for bc variants hence we pass -1 and 0 respec= tively + */ + return bcond_helper(ctx, type, a->bo, a->bi, -1, a->bh, 0, a->lk); +} + +TRANS(BCLR, bclr_helper, BCOND_LR) +TRANS(BCCTR, bclr_helper, BCOND_CTR) +TRANS_FLAGS2(BCTAR_ISA207, BCTAR, bclr_helper, BCOND_TAR) --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897628; cv=none; d=zohomail.com; s=zohoarc; b=eIsoYkumznuCvsQFH4m5IX46RIM77RQBJgyRcH1BjpviEvvlmam4iYcBn5b1lf9Gdwwny7XxjtoHFX3Gj/aDKwlRb7yt/ydtc0gsdiagJSZWO/Ctvptz2wjPWzh16tSUnbxts3HAMWZwAWVmcudkV72s8bkBX9bO1YzzyP94kBc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787897628; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897630973154100 From: Ojaswin Mujoo Use ##__VA_ARGS__ in TRANS* macros to allow variadic arguments to be optional instead of mandatory. "##" removes the preceding comma when __VA_ARGS__ is empty, enabling macros to work with functions that don't need extra parameters. This avoid compilation errors when using a pattern like below: static bool do_wait(DisasContext *ctx, arg_X_wait *a) {...} TRANS_FLAGS(WAIT, WAIT_ISA_2_X, do_wait) Compilation Error: ../target/ppc/translate.c:5526:40: error: expected expression before =E2=80= =98)=E2=80=99 token 5526 | return FUNC(ctx, a, __VA_ARGS__); \ | ^ ../target/ppc/translate/storage-ctrl-impl.c.inc:368:1: note: in expansion o= f macro =E2=80=98TRANS_FLAGS=E2=80=99 368 | TRANS_FLAGS(WAIT, WAIT_ISA_2_X, do_wait) Signed-off-by: Ojaswin Mujoo Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-17-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f5b1446d7a..322870dc0d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4749,29 +4749,29 @@ static int64_t dw_compose_ea(DisasContext *ctx, int= x) */ #define TRANS(NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ - { return FUNC(ctx, a, __VA_ARGS__); } + { return FUNC(ctx, a, ##__VA_ARGS__); } #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ - return FUNC(ctx, a, __VA_ARGS__); \ + return FUNC(ctx, a, ##__VA_ARGS__); \ } #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ - return FUNC(ctx, a, __VA_ARGS__); \ + return FUNC(ctx, a, ##__VA_ARGS__); \ } =20 #define TRANS64(NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ - { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } + { REQUIRE_64BIT(ctx); return FUNC(ctx, a, ##__VA_ARGS__); } #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ REQUIRE_64BIT(ctx); \ REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ - return FUNC(ctx, a, __VA_ARGS__); \ + return FUNC(ctx, a, ##__VA_ARGS__); \ } =20 /* TODO: More TRANS* helpers for extra insn_flags checks. */ --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897362574158500 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Implement wait instruction using decodetree with proper handling of WC and PL fields across different ISA versions. Since the opcode changed between ISA 2.x and 3.x we have defined 2 different decodetree instructions that are handled by the same helper. The changes have been tested by comparing the tcg generated before and after the change for wait instruction. The test was repeated for 2 types of machines: Power10 - which should use the newer wait implementation e500mc - which should use older PPC_WAIT implementation Both generated the same tcg ops with and without the change. Further, with the changes we were able to boot into Fedora distro as well. Signed-off-by: Ojaswin Mujoo Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-18-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 15 +++ target/ppc/translate.c | 91 ------------------ target/ppc/translate/storage-ctrl-impl.c.inc | 99 ++++++++++++++++++++ 3 files changed, 114 insertions(+), 91 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index e7cc36bd6c..da32ac1d28 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1478,6 +1478,21 @@ ISYNC 010011 ----- ----- ----- 0010010110 - @XL_bfa ...... bf:3 .. bfa:3 .. ..... ..... ..... . MCRF 010011 ... -- ... -- ----- 00000 00000 - @XL_bfa =20 +# Wait Instructions + +# We can use the same X_wait argument set for both WAIT and older ISA2.x +# compliant WAIT_2_x. Depending on the version, we may or may not use the +# arguments. For more information, check do_wait() helper. + +&X_wait wc pl +@X_wait ...... ..- wc:2 --- pl:2 ----- .......... - &X_wait + +# According to ISA v3.1, bit 6 and 7 are implementation dependent and "unl= ess +# the intention is to use the implementation-dependent field, these bits m= ust be +# coded zero". Hence, we code them to 0. +WAIT 011111 00-.. ---.. ----- 0000011110 - @X_wait +WAIT_ISA_2_X 011111 ---.. ---.. ----- 0000111110 - @X_wait + # Branch History Rolling Buffer (BHRB) Instructions =20 &XFX_bhrbe rt bhrbe diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 322870dc0d..e5ed4d2cc4 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2727,95 +2727,6 @@ static inline void gen_check_tlb_flush(DisasContext = *ctx, bool global) static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } #endif =20 -/* wait */ -static void gen_wait(DisasContext *ctx) -{ - uint32_t wc; - - if (ctx->insns_flags & PPC_WAIT) { - /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ - - if (ctx->insns_flags2 & PPC2_PM_ISA206) { - /* v2.06 introduced the WC field. WC > 0 may be treated as no-= op. */ - wc =3D WC(ctx->opcode); - } else { - wc =3D 0; - } - - } else if (ctx->insns_flags2 & PPC2_ISA300) { - /* v3.0 defines a new 'wait' encoding. */ - wc =3D WC(ctx->opcode); - if (ctx->insns_flags2 & PPC2_ISA310) { - uint32_t pl =3D PL(ctx->opcode); - - /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ - if (wc =3D=3D 3) { - gen_invalid(ctx); - return; - } - - /* PL 1-3 are reserved. If WC=3D2 then the insn is treated as = noop. */ - if (pl > 0 && wc !=3D 2) { - gen_invalid(ctx); - return; - } - - } else { /* ISA300 */ - /* WC 1-3 are reserved */ - if (wc > 0) { - gen_invalid(ctx); - return; - } - } - - } else { - warn_report("wait instruction decoded with wrong ISA flags."); - gen_invalid(ctx); - return; - } - - /* - * wait without WC field or with WC=3D0 waits for an exception / inter= rupt - * to occur. - */ - if (wc =3D=3D 0) { - TCGv_i32 t0 =3D tcg_constant_i32(1); - tcg_gen_st_i32(t0, tcg_env, - -offsetof(PowerPCCPU, env) + offsetof(CPUState, hal= ted)); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); - } - - /* - * Other wait types must not just wait until an exception occurs becau= se - * ignoring their other wake-up conditions could cause a hang. - * - * For v2.06 and 2.07, wc=3D1,2,3 are architected but may be implement= ed as - * no-ops. - * - * wc=3D1 and wc=3D3 explicitly allow the instruction to be treated as= a no-op. - * - * wc=3D2 waits for an implementation-specific condition, such could be - * always true, so it can be implemented as a no-op. - * - * For v3.1, wc=3D1,2 are architected but may be implemented as no-ops. - * - * wc=3D1 (waitrsv) waits for an exception or a reservation to be lost. - * Reservation-loss may have implementation-specific conditions, so it - * can be implemented as a no-op. - * - * wc=3D2 waits for an exception or an amount of time to pass. This - * amount is implementation-specific so it can be implemented as a - * no-op. - * - * ISA v3.1 allows for execution to resume "in the rare case of - * an implementation-dependent event", so in any case software must - * not depend on the architected resumption condition to become - * true, so no-op implementations should be architecturally correct - * (if suboptimal). - */ -} - #if defined(TARGET_PPC64) static void gen_doze(DisasContext *ctx) { @@ -5184,8 +5095,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_S= TRING), GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), /* ISA v3.0 changed the extended opcode from 62 to 30 */ -GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), -GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/tran= slate/storage-ctrl-impl.c.inc index 943229c438..d4d6ab765a 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -270,3 +270,102 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *= a, bool local) =20 TRANS_FLAGS(MEM_TLBIE, TLBIE, do_tlbie, false) TRANS_FLAGS(MEM_TLBIE, TLBIEL, do_tlbie, true) + +/* + * Decodetree populates a->wc and a->pl based on ISA v3.1, however they may + * or may not be used based on the ISA: + * For ISA < 2.06 - both wc and pl are ignored + * For ISA =3D=3D 2.06, 2.07, 3.0 - wc is used and pl is ignored + * For ISA 3.1 - both wc and pl are used + */ +static bool do_wait(DisasContext *ctx, arg_X_wait *a) +{ + uint32_t wc; + + if (ctx->insns_flags & PPC_WAIT) { + /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ + + if (ctx->insns_flags2 & PPC2_PM_ISA206) { + /* v2.06 introduced the WC field. WC > 0 may be treated as no-= op. */ + wc =3D a->wc; + } else { + wc =3D 0; + } + + } else if (ctx->insns_flags2 & PPC2_ISA300) { + /* v3.0 defines a new 'wait' encoding. */ + wc =3D a->wc; + if (ctx->insns_flags2 & PPC2_ISA310) { + uint32_t pl =3D a->pl; + + /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ + if (wc =3D=3D 3) { + gen_invalid(ctx); + return true; + } + + /* PL 1-3 are reserved. If WC=3D2 then the insn is treated as = noop. */ + if (pl > 0 && wc !=3D 2) { + gen_invalid(ctx); + return true; + } + + } else { /* ISA300 */ + /* WC 1-3 are reserved */ + if (wc > 0) { + gen_invalid(ctx); + return true; + } + } + + } else { + warn_report("wait instruction decoded with wrong ISA flags."); + gen_invalid(ctx); + return true; + } + + /* + * wait without WC field or with WC=3D0 waits for an exception / inter= rupt + * to occur. + */ + if (wc =3D=3D 0) { + TCGv_i32 t0 =3D tcg_constant_i32(1); + tcg_gen_st_i32(t0, tcg_env, + -offsetof(PowerPCCPU, env) + offsetof(CPUState, hal= ted)); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); + } + + /* + * Other wait types must not just wait until an exception occurs becau= se + * ignoring their other wake-up conditions could cause a hang. + * + * For v2.06 and 2.07, wc=3D1,2,3 are architected but may be implement= ed as + * no-ops. + * + * wc=3D1 and wc=3D3 explicitly allow the instruction to be treated as= a no-op. + * + * wc=3D2 waits for an implementation-specific condition, such could be + * always true, so it can be implemented as a no-op. + * + * For v3.1, wc=3D1,2 are architected but may be implemented as no-ops. + * + * wc=3D1 (waitrsv) waits for an exception or a reservation to be lost. + * Reservation-loss may have implementation-specific conditions, so it + * can be implemented as a no-op. + * + * wc=3D2 waits for an exception or an amount of time to pass. This + * amount is implementation-specific so it can be implemented as a + * no-op. + * + * ISA v3.1 allows for execution to resume "in the rare case of + * an implementation-dependent event", so in any case software must + * not depend on the architected resumption condition to become + * true, so no-op implementations should be architecturally correct + * (if suboptimal). + */ + return true; +} + +TRANS_FLAGS(WAIT, WAIT_ISA_2_X, do_wait) +TRANS_FLAGS2(ISA300, WAIT, do_wait) --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897390; cv=none; d=zohomail.com; s=zohoarc; b=eZwi1DOaGUkrQMTgCVIKDIp+JIRB+PRsykpa5hDRMI+WuQSIcGYLCirKwl40CiFHKCU5gVsVllgre313LqgM3BW+24YCGAOQQHAVawajR4/1oNSyJsuCpXU+ML6fD7ATGdyx0WJRjAJVQ6b9I7LT9PnmDuaa7rP518Qc4c/GNBA= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=Bfwb75bVXDwZmbxcO vuPs7tka6wHjQBIB3EtDH3dVMw=; b=mDih9kcizqtQxBmkOPPRlKTB6rb+X5zuA MV0myiT5xPYbbstUiMFDoEjWkcPInmj1WaKb98AM/dXgkRZoYTfL8MWWwlUYBS5n LCnReyi3AASPJpmBVIbh/5IWjfIbrew4vLxqwKSuSKZdSxU76+0i4brkgvI9qR0U nwsNhb8TE7KNELdoNwJuTQV2qx4gFc3xIjjHO09ktYOgWBwo4lilhh+8WjT34M/2 DhSUSayjuz6yQ+iuNBJMGfnkjUglvfG+hnWi/30G3w1wxL4ikctfTTUxejRvR1Qc g3Bc0rwXd0vA7RD1ovqpVPPvLkmW7YIYgyr6S008FcsTlJfP0O9BA== From: Harsh Prateek Bora To: qemu-devel@nongnu.org Cc: Ojaswin Mujoo , Glenn Miles , Amit Machhiwal , Chinmay Rath , Aniket Sahu Subject: [PULL 22/41] target/ppc: Move sleep & friends to decodetree Date: Fri, 28 Aug 2026 11:36:57 +0530 Message-ID: <20260828060716.91672-23-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com> References: <20260828060716.91672-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: OgLTGEer1ajrNe7Pe7zw_BOgvbK9JhEY X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfXyx+R5FRDsnCd noee3IHT4aAGuKY9yW2b1UvFypG4nXhuap3W0nUlE5vq0LmtKPOiwdsEk7OafxwvdEeMHL2M1Q6 MJd0O3ScjnoXWslxsz/4v6+NtaXC/Kk= X-Proofpoint-GUID: OgLTGEer1ajrNe7Pe7zw_BOgvbK9JhEY X-Authority-Analysis: v=2.4 cv=JZyMa0KV c=1 sm=1 tr=0 ts=6a9125dc cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=Sv0fKeRqtYgA:10 a=f7IdgyKtn90A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=lazmSyS9DYsNBvc1uWIA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX6ym8tQLEQJn8 kzr1cynlpzZDnXFubpZH3HmKdxj94L6yFhkDkN5b1mjtnPdagkw7yp0oqwR/lQCUSTtAteLuaJG IxIcLRvN+taA5eQRzAp//vfDvWA6hbdQ7PtiEQMWdpxbahkDC43h29Yi5/CPXg+XCOKV3PThSU1 wNP7raHgqrVDpo3/RDBaP2Qqum94TSp+kk2rKghfEQwFe5ZO62MBQoTy67Pdeidsn8Quf5U16o7 7rRdvPdXSiEB0peETX0chNp4mtH5JO4VkINTky/buky2dBnQOue7PvfHa+TxW6hOcMY8Rs8fUs0 JYzIroDSxB0nap1VPVPwIAtpdsqc+3JVb3r1Yw7w5Kk4Gna93QZd77k6UF11r2fssQWeBoDWw9R 5EzpbzHnj4zcqzsX57SR+gF+B+L6QdQCc/kBJ85P1W2iil+0i1fklyhkTx6GrhZmwP76jttKFJ9 xyUAbxI7XCmKRrWnm/w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_01,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 adultscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280050 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897393213154100 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Convert the following instructions to decode tree specification: doze nap sleep rvwinkle stop The functionality was tested by comparing the qemu -D log -d op,in_asm output as well as single stepping gdb to confirm behavior was not changed for ISA3.x (stop) as well as ISA206 (doze, nap, sleep, rvwinkle). Signed-off-by: Ojaswin Mujoo Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-19-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 8 ++ target/ppc/translate.c | 85 --------------- .../ppc/translate/processor-ctrl-impl.c.inc | 100 ++++++++++++++++++ 3 files changed, 108 insertions(+), 85 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index da32ac1d28..b833244932 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -913,6 +913,14 @@ VPERMR 000100 ..... ..... ..... ..... 111011 = @VA =20 VSEL 000100 ..... ..... ..... ..... 101010 @VA =20 +## Power Management Instructions + +DOZE 010011 ----- ----- ----- 0110010010 - +NAP 010011 ----- ----- ----- 0110110010 - +SLEEP 010011 ----- ----- ----- 0111010010 - +RVWINKLE 010011 ----- ----- ----- 0111110010 - +STOP 010011 ----- ----- ----- 0101110010 - + ## Vector Integer Shift Instruction =20 VSLB 000100 ..... ..... ..... 00100000100 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e5ed4d2cc4..9d9823f92d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2728,86 +2728,6 @@ static inline void gen_check_tlb_flush(DisasContext = *ctx, bool global) { } #endif =20 #if defined(TARGET_PPC64) -static void gen_doze(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_DOZE); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_nap(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_NAP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_stop(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_STOP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_sleep(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_SLEEP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_rvwinkle(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_RVWINKLE); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, T= CGv value) { TCGv_ptr tmp =3D tcg_temp_new_ptr(); @@ -5104,11 +5024,6 @@ GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC= _NONE, PPC2_ISA300), GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), #endif -GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206= ), -GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), -GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA20= 6), -GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_IS= A206), GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), #endif /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/tr= anslate/processor-ctrl-impl.c.inc index 8abbb89630..a96c9c87ce 100644 --- a/target/ppc/translate/processor-ctrl-impl.c.inc +++ b/target/ppc/translate/processor-ctrl-impl.c.inc @@ -103,3 +103,103 @@ static bool trans_MSGSYNC(DisasContext *ctx, arg_MSGS= YNC *a) /* interpreted as no-op */ return true; } + +static bool do_doze(DisasContext *ctx, arg_DOZE *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_DOZE); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + return true; +} +TRANS_FLAGS2(PM_ISA206, DOZE, do_doze); + +static bool do_nap(DisasContext *ctx, arg_NAP *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_NAP); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + return true; +} +TRANS_FLAGS2(PM_ISA206, NAP, do_nap); + +static bool do_sleep(DisasContext *ctx, arg_SLEEP *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_SLEEP); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + return true; +} +TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep); + +static bool do_rvwinkle(DisasContext *ctx, arg_RVWINKLE *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_RVWINKLE); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + return true; +} +TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_rvwinkle); + +static bool do_stop(DisasContext *ctx, arg_STOP *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_STOP); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + return true; +} +TRANS_FLAGS2(ISA300, STOP, do_stop); --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897548; cv=none; d=zohomail.com; s=zohoarc; b=XA4yvNBopgUy4aWytWfTVry5d1RVOUN1z/DjmhyhfpdU4N1BVjUy5q2Ng+icDlzIdegj/xVnwwRpPMwam2coTkpq5c6piUdf+6zs21i8niuYEv2OBH2IIk8Ema/JqNX9YlV1mgIjSMdvwHBF2Zo3cmiucI/6ITZzVcF0zC2tcqQ= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=sw9q9ogDOP5PDgir7 8SPadWAWqHkUoEC+BupL5vdE1E=; b=ctJoCVWaSP80UqGTQ8xR2KYd2lv59CX2d MTYR0wNhZiBlSTsewlm/53YQ1aiQ7QOs0QULKN6+SEfxO4VE6TqLomFGuhJ/0h5H BMV5B2jXr+egop8Of+fUAhkBlJFUaAAqroCVV29X6T2RB+oh/9p0Pu7160ihlU5E XmnornrGbYdU+9mKodVKXYlP3E2qblU3LBEToo9++iqDwbdG1gxHzKSSHzzDzw5W 7jVpWpO1Of+zFjH6ziDj8t+zrXbhY6NpPi6I2x35dDN6plAzqW/Ea8qtBKaTRoMA rIpDRVx3aQjWoDATsi9yUbUiLntUuQoRuj1MzR5G5T+c6JsRfVRsA== From: Harsh Prateek Bora To: qemu-devel@nongnu.org Cc: Ojaswin Mujoo , Glenn Miles , Amit Machhiwal , Chinmay Rath , Aniket Sahu Subject: [PULL 23/41] target/ppc: Refactor sleep and its variants to use a common helper Date: Fri, 28 Aug 2026 11:36:58 +0530 Message-ID: <20260828060716.91672-24-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com> References: <20260828060716.91672-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=TfimcxQh c=1 sm=1 tr=0 ts=6a9125df cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=Sv0fKeRqtYgA:10 a=f7IdgyKtn90A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=AYO248uK6yRxx-YkPnAA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX3kcJa2mv3cjn qWogqGs+swiQxzbFLC7jzEhzXnk5x2/psJlDaCNpxzcNe/U9mn/t9W09u2Wn9TUTNoah+T5jjeY tJh1ASHGJeNwYEul8CJZKmtWAhwBCoc= X-Proofpoint-GUID: iHJq6D06fsnQLoaTv1gAjLl1oDMyuiOV X-Proofpoint-ORIG-GUID: iHJq6D06fsnQLoaTv1gAjLl1oDMyuiOV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX/ic8dbpYrI9t FDz34YEAZM0iWannl2Fgzre/iI0z5HIQgs936PstaD0z+NbcSdUV9rsNx5dJ17Fhsxoz8JP4Zun AHgsA4eBJ5VX94O/R0afcS4iATHfpeAtuSBYSnNXNL9YWUSl+DgBuSwbcZ8F/JgwrrjqNpge1QJ Ay2HgQJaJYLtwkBUl+RkFZXZAcbZXX0CIbHP5H+nIYLGKj/HF6sMjfI7MOayvNYOpb20sJG4WKa m9+E4/laHblSiDmn7AZ7cAynt4mZohA6Rrn4jVyAHU1CWUAu7Sm68AA32xL+qEP0nRewe7JOmJH YDgXSOtIH2aSWOwcsTOrc8CNxP1yDPHdIVKAi2h+aO798vWisNFtAqVoy0sE2zwMuslgSqf86CK dOEsfcLZNgkAUbwnEViFH14eD+nKTAEWsTcRFOmgmmGuYuQBr1cbjxU9nPS1ezDb2PC5xXmO39r 4Dvhpm9wHLmp1LXV/Bw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_01,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 phishscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280050 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897549278158500 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo With sleep, doze, nap, rvwinkle and stop instructions moved to decodetree, the helper these instructions used : gen_helper_pminsn, should now be renamed to gen_helper_PMINSN, abiding by the decodetree standards. Do the same. Also refactor their translation routine to use a common do_sleep routine since they share majority of the code. Signed-off-by: Ojaswin Mujoo Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-20-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/helper.h | 2 +- target/ppc/tcg-excp_helper.c | 2 +- .../ppc/translate/processor-ctrl-impl.c.inc | 99 +++---------------- 3 files changed, 17 insertions(+), 86 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index e7bf43bf4b..6e14f02598 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -18,7 +18,7 @@ DEF_HELPER_1(rfdi, void, env) DEF_HELPER_1(rfmci, void, env) #if defined(TARGET_PPC64) DEF_HELPER_2(scv, noreturn, env, i32) -DEF_HELPER_2(pminsn, void, env, i32) +DEF_HELPER_2(PMINSN, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index b04f07a637..c4ffa2dfbb 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -459,7 +459,7 @@ void helper_scv(CPUPPCState *env, uint32_t lev) } } =20 -void helper_pminsn(CPUPPCState *env, uint32_t insn) +void helper_PMINSN(CPUPPCState *env, uint32_t insn) { CPUState *cs =3D env_cpu(env); =20 diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/tr= anslate/processor-ctrl-impl.c.inc index a96c9c87ce..cfcca28267 100644 --- a/target/ppc/translate/processor-ctrl-impl.c.inc +++ b/target/ppc/translate/processor-ctrl-impl.c.inc @@ -104,102 +104,33 @@ static bool trans_MSGSYNC(DisasContext *ctx, arg_MSG= SYNC *a) return true; } =20 -static bool do_doze(DisasContext *ctx, arg_DOZE *a) -{ - REQUIRE_64BIT(ctx); - -#if defined(CONFIG_USER_ONLY) - gen_priv_opc(ctx); -#else - TCGv_i32 t; - - REQUIRE_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_DOZE); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ - return true; -} -TRANS_FLAGS2(PM_ISA206, DOZE, do_doze); - -static bool do_nap(DisasContext *ctx, arg_NAP *a) +/* + * Helper to handle DOZE, NAP, SLEEP, RVWINKLE & STOP. Since none of them = use + * any arguments just use a placeholder arg_SLEEP. + */ +static bool do_sleep(DisasContext *ctx, arg_SLEEP *a, powerpc_pm_insn_t ty= pe) { REQUIRE_64BIT(ctx); =20 #if defined(CONFIG_USER_ONLY) gen_priv_opc(ctx); -#else +#elif defined(TARGET_PPC64) TCGv_i32 t; =20 REQUIRE_HV(ctx); translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_NAP); - gen_helper_pminsn(tcg_env, t); + t =3D tcg_constant_i32(type); + gen_helper_PMINSN(tcg_env, t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ - return true; -} -TRANS_FLAGS2(PM_ISA206, NAP, do_nap); - -static bool do_sleep(DisasContext *ctx, arg_SLEEP *a) -{ - REQUIRE_64BIT(ctx); - -#if defined(CONFIG_USER_ONLY) - gen_priv_opc(ctx); #else - TCGv_i32 t; - - REQUIRE_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_SLEEP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ - return true; -} -TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep); - -static bool do_rvwinkle(DisasContext *ctx, arg_RVWINKLE *a) -{ - REQUIRE_64BIT(ctx); - -#if defined(CONFIG_USER_ONLY) - gen_priv_opc(ctx); -#else - TCGv_i32 t; - - REQUIRE_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_RVWINKLE); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ + qemu_build_not_reached(); +#endif return true; } -TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_rvwinkle); - -static bool do_stop(DisasContext *ctx, arg_STOP *a) -{ - REQUIRE_64BIT(ctx); =20 -#if defined(CONFIG_USER_ONLY) - gen_priv_opc(ctx); -#else - TCGv_i32 t; - - REQUIRE_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_STOP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ - return true; -} -TRANS_FLAGS2(ISA300, STOP, do_stop); +TRANS_FLAGS2(PM_ISA206, DOZE, do_sleep, PPC_PM_DOZE); +TRANS_FLAGS2(PM_ISA206, NAP, do_sleep, PPC_PM_NAP); +TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep, PPC_PM_SLEEP); +TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_sleep, PPC_PM_RVWINKLE); +TRANS_FLAGS2(ISA300, STOP, do_sleep, PPC_PM_STOP); --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897538; cv=none; d=zohomail.com; s=zohoarc; b=YXS4uHAPzh1YfqRCaVP9jmJSb4yy0TIWPaODWRS/7BBUsp5uOSzSvHwJ2UFQN6qBqNewbVkuEODkkC70U1Swbm+hvgZ3r5uTKs8UaDJ99Z82tTEilTbfpCtA1W0U/Fhr9rX2e+ZQC9C6MDXG3lWamQgAF6X1xg+q251HnXsxOow= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=5zOCKbrZTz2AJ4tek sfNPyty7ZQ2fVPJeChH+NPt4HU=; b=dKIET7M0WiUwDiintH8OHq6lbjNYUXQ1m uLm90qx6M10ELzOVbrT5NyGDnQlYxGbpgRmQELbPrlYkOM5Ahr0DSK5PxibM5k0b v+rNv5Lm1cINHmeaXCObbC6kR1xAGKxmtKeTaCp0QtnNTG5n9WBBS7qW8nt+xaDz uQbHmu898pd1VOUisa6GO1DkuXP1+zy0ahCvcGwvI719zpQwHri8SCjiV+719fMY 0OeOsjLTXoy6LV5vZ4c2oWvLfoQkYozz66qL15m2GF/QSXLa0JH453HOGTbiFo/U FBAtE7x5zXJGz6VULwk1KwjVZ1urOto62T4W1RuMuqQl+Gk8dDXUA== From: Harsh Prateek Bora To: qemu-devel@nongnu.org Cc: Shivang Upadhyay , Glenn Miles , Amit Machhiwal , Chinmay Rath , Aniket Sahu Subject: [PULL 24/41] target/ppc: Move Condition Register access instructions to decodetree. Date: Fri, 28 Aug 2026 11:36:59 +0530 Message-ID: <20260828060716.91672-25-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com> References: <20260828060716.91672-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: FVDcH6nbRje3RPH1maNKclCR7nqneme0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX8mAF7Gw+hCsI xVUuBYcZAdoEB5XCkO1YcCQdP6bJ8t6CyvtlplnW8Z2AEFDOClFAGeqabtHFMXzNO8NERMvNHuZ 1PNSedupiPOlUv3gvp99hVB2WFHzgrZBAD6MLlqkOTjDzKjMflD2f9Sytimok5cCGwicQCzoQvs YjkNZpriJu1gJy7KXBrD2G8XKdzCzjGsXTSlrB+hzL2z/fQxPcfAZMWS254iSDs+AuONc/6zJWa LqA68DRbArSa2jB4UbP3+KgKCJpNIFpByxbhJ0BRQ8crxCYzQ/c4mcF9zUzOKT4/b1+bH89MXDA UAeZdQHloxrAIQ3Mw2xN0ST7Icsxn9G7Wcl9fwGxCW/aDiqiP/B2u3uDMECD1A9okpLR0/Iw3wX 8gAiNiJGLputAUHC+rXCM9jYIOvxDJ09sKfhLFYNkG2GPdsOpL27xJy016kNjHn9WAPBdnhZGAl juVTec9CibCGeut29+g== X-Authority-Analysis: v=2.4 cv=Y/nIdBeN c=1 sm=1 tr=0 ts=6a9125e2 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=Sv0fKeRqtYgA:10 a=f7IdgyKtn90A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=pKujU25TKs9URF08bPwA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX6g1QExiV+8q3 xfrMySS4UJiHg30En9Thk0yBYB6kURAg+EHO6w7p7Yst7mtpQbOy1K4Ya5vI17VXikGrGf5m1o7 9FPRzDcPoEdK/dVUXeep8QVpbj6PoWo= X-Proofpoint-ORIG-GUID: FVDcH6nbRje3RPH1maNKclCR7nqneme0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_01,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280050 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897539242154100 Content-Type: text/plain; charset="utf-8" From: Shivang Upadhyay Move below instructions to decodetree specification : mfcr, mfocr, mtcrf, mtocrf : XFX-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Shivang Upadhyay Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-21-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 8 +++ target/ppc/translate.c | 62 ----------------- target/ppc/translate/fixedpoint-impl.c.inc | 78 ++++++++++++++++++++++ 3 files changed, 86 insertions(+), 62 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index b833244932..137432ed96 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -70,6 +70,9 @@ %dx_d 6:s10 16:5 0:1 @DX ...... rt:5 ..... .......... ..... . &DX d=3D%d= x_d =20 +&XFX rt fxm +@XFX ...... rt:5 . fxm:8 ...... ..... . &XFX + %md_sh 1:1 11:5 %md_mb 5:1 6:5 &MD rs ra sh mb rc @@ -648,6 +651,11 @@ FSEL 111111 ..... ..... ..... ..... 10111 .= @A =20 ### Move To/From System Register Instructions =20 +MFCR 011111 ..... 0.... ....- 0000010011 - @XFX +MFOCR 011111 ..... 1.... ....- 0000010011 - @XFX +MTCRF 011111 ..... 0.... ....- 0010010000 - @XFX +MTOCRF 011111 ..... 1.... ....- 0010010000 - @XFX + SETBC 011111 ..... ..... ----- 0110000000 - @X_bi SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 9d9823f92d..59e8ecb262 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3131,40 +3131,6 @@ static void gen_mcrxrx(DisasContext *ctx) } #endif =20 -/* mfcr mfocrf */ -static void gen_mfcr(DisasContext *ctx) -{ - uint32_t crm, crn; - - if (likely(ctx->opcode & 0x00100000)) { - crm =3D CRM(ctx->opcode); - if (likely(crm && ((crm & (crm - 1)) =3D=3D 0))) { - crn =3D ctz32(crm); - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]= ); - tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rD(ctx->opcode)], crn * 4); - } - } else { - TCGv_i32 t0 =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(t0, cpu_crf[0]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[1]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[2]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[3]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[4]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[5]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[6]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[7]); - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); - } -} - /* mfmsr */ static void gen_mfmsr(DisasContext *ctx) { @@ -3245,32 +3211,6 @@ static void gen_mftb(DisasContext *ctx) gen_op_mfspr(ctx); } =20 -/* mtcrf mtocrf*/ -static void gen_mtcrf(DisasContext *ctx) -{ - uint32_t crm, crn; - - crm =3D CRM(ctx->opcode); - if (likely((ctx->opcode & 0x00100000))) { - if (crm && ((crm & (crm - 1)) =3D=3D 0)) { - TCGv_i32 temp =3D tcg_temp_new_i32(); - crn =3D ctz32(crm); - tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); - tcg_gen_shri_i32(temp, temp, crn * 4); - tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); - } - } else { - TCGv_i32 temp =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); - for (crn =3D 0 ; crn < 8 ; crn++) { - if (crm & (1 << crn)) { - tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); - tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0= xf); - } - } - } -} - /* mtmsr */ #if defined(TARGET_PPC64) static void gen_mtmsrd(DisasContext *ctx) @@ -5030,11 +4970,9 @@ GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC= _64H), GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), -GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), -GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), #if defined(TARGET_PPC64) GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index f9435f4a00..11d919a21a 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -461,6 +461,84 @@ static bool trans_ADDEX(DisasContext *ctx, arg_X *a) return true; } =20 +static bool trans_MTCRF(DisasContext *ctx, arg_MTCRF *a) +{ + TCGv_i32 temp; + uint32_t crm, crn; + + crm =3D a->fxm; + + temp =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(temp, cpu_gpr[a->rt]); + + for (crn =3D 0 ; crn < 8 ; crn++) { + if (crm & (1 << crn)) { + tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); + tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); + } + } + + return true; +} + +static bool trans_MTOCRF(DisasContext *ctx, arg_MTOCRF *a) +{ + uint32_t crm, crn; + + crm =3D a->fxm; + + /* Checking crm > 0 and set_bits(crm) =3D=3D 1 */ + if (crm && ((crm & (crm - 1)) =3D=3D 0)) { + TCGv_i32 temp =3D tcg_temp_new_i32(); + crn =3D ctz32(crm); + tcg_gen_trunc_tl_i32(temp, cpu_gpr[a->rt]); + tcg_gen_shri_i32(temp, temp, crn * 4); + tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); + } + + return true; +} + +static bool trans_MFOCR(DisasContext *ctx, arg_MFOCR *a) +{ + uint32_t crm, crn; + + crm =3D a->fxm; + + /* Checking crm > 0 and set_bits(crm) =3D=3D 1 */ + if (likely(crm && ((crm & (crm - 1)) =3D=3D 0))) { + crn =3D ctz32(crm); + tcg_gen_extu_i32_tl(cpu_gpr[a->rt], cpu_crf[7 - crn]); + tcg_gen_shli_tl(cpu_gpr[a->rt], + cpu_gpr[a->rt], crn * 4); + } + + return true; +} + +static bool trans_MFCR(DisasContext *ctx, arg_MFCR *a) +{ + TCGv_i32 t0 =3D tcg_temp_new_i32(); + tcg_gen_mov_i32(t0, cpu_crf[0]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[1]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[2]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[3]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[4]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[5]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[6]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[7]); + tcg_gen_extu_i32_tl(cpu_gpr[a->rt], t0); + + return true; +} + static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool comput= e_ca, bool compute_ov, bool compute_rc0) { --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Shivang Upadhyay Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-22-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 11 ++++ target/ppc/translate.c | 59 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 45 +++++++++++++++++ 3 files changed, 56 insertions(+), 59 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 137432ed96..5e5490b169 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -516,6 +516,17 @@ CFUGED 011111 ..... ..... ..... 0011011100 - = @X PDEPD 011111 ..... ..... ..... 0010011100 - @X PEXTD 011111 ..... ..... ..... 0010111100 - @X =20 +## Condition Register Instructions + +CRAND 010011 ..... ..... ..... 0100000001 - @X +CROR 010011 ..... ..... ..... 0111000001 - @X +CRNAND 010011 ..... ..... ..... 0011100001 - @X +CRXOR 010011 ..... ..... ..... 0011000001 - @X +CRNOR 010011 ..... ..... ..... 0000100001 - @X +CREQV 010011 ..... ..... ..... 0100100001 - @X +CRANDC 010011 ..... ..... ..... 0010000001 - @X +CRORC 010011 ..... ..... ..... 0110100001 - @X + # Fixed-Point Hash Instructions =20 HASHST 011111 ..... ..... ..... 1011010010 . @X_DW diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 59e8ecb262..c5361d8db5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2920,53 +2920,6 @@ static inline void gen_setlr(DisasContext *ctx, targ= et_ulong nip) tcg_gen_movi_tl(cpu_lr, nip); } =20 -/*** Condition register logical = ***/ -#define GEN_CRLOGIC(name, tcg_op, opc) = \ -static void glue(gen_, name)(DisasContext *ctx) = \ -{ = \ - uint8_t bitmask; = \ - int sh; = \ - TCGv_i32 t0, t1; = \ - sh =3D (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); = \ - t0 =3D tcg_temp_new_i32(); = \ - if (sh > 0) = \ - tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); = \ - else if (sh < 0) = \ - tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); = \ - else = \ - tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); = \ - t1 =3D tcg_temp_new_i32(); = \ - sh =3D (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); = \ - if (sh > 0) = \ - tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); = \ - else if (sh < 0) = \ - tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); = \ - else = \ - tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); = \ - tcg_op(t0, t0, t1); = \ - bitmask =3D 0x08 >> (crbD(ctx->opcode) & 0x03); = \ - tcg_gen_andi_i32(t0, t0, bitmask); = \ - tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); = \ - tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); = \ -} - -/* crand */ -GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); -/* crandc */ -GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); -/* creqv */ -GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); -/* crnand */ -GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); -/* crnor */ -GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); -/* cror */ -GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); -/* crorc */ -GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); -/* crxor */ -GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); - /*** System linkage = ***/ =20 /* rfi (supervisor only) */ @@ -5109,18 +5062,6 @@ GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) #endif =20 -#undef GEN_CRLOGIC -#define GEN_CRLOGIC(name, tcg_op, opc) = \ -GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) -GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), -GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), -GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), -GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), -GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), -GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), -GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), -GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), - #undef GEN_MAC_HANDLER #define GEN_MAC_HANDLER(name, opc2, opc3) = \ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 11d919a21a..d0b3bda97f 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -539,6 +539,51 @@ static bool trans_MFCR(DisasContext *ctx, arg_MFCR *a) return true; } =20 +static bool cr_logic_common(DisasContext *ctx, arg_X *a, + void (*tcg_op)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + uint8_t bitmask; + int sh; + TCGv_i32 t0, t1; + sh =3D (a->rt & 0x03) - (a->ra & 0x03); + t0 =3D tcg_temp_new_i32(); + t1 =3D tcg_temp_new_i32(); + + if (sh > 0) { + tcg_gen_shri_i32(t0, cpu_crf[a->ra >> 2], sh); + } else if (sh < 0) { + tcg_gen_shli_i32(t0, cpu_crf[a->ra >> 2], -sh); + } else { + tcg_gen_mov_i32(t0, cpu_crf[a->ra >> 2]); + } + + sh =3D (a->rt & 0x03) - (a->rb & 0x03); + if (sh > 0) { + tcg_gen_shri_i32(t1, cpu_crf[a->rb >> 2], sh); + } else if (sh < 0) { + tcg_gen_shli_i32(t1, cpu_crf[a->rb >> 2], -sh); + } else { + tcg_gen_mov_i32(t1, cpu_crf[a->rb >> 2]); + } + tcg_op(t0, t0, t1); + + bitmask =3D 0x08 >> (a->rt & 0x03); + tcg_gen_andi_i32(t0, t0, bitmask); + tcg_gen_andi_i32(t1, cpu_crf[a->rt >> 2], ~bitmask); + tcg_gen_or_i32(cpu_crf[a->rt >> 2], t0, t1); + + return true; +} + +TRANS(CRAND, cr_logic_common, tcg_gen_and_i32); +TRANS(CROR, cr_logic_common, tcg_gen_or_i32); +TRANS(CRXOR, cr_logic_common, tcg_gen_xor_i32); +TRANS(CRNAND, cr_logic_common, tcg_gen_nand_i32); +TRANS(CRNOR, cr_logic_common, tcg_gen_nor_i32); +TRANS(CRANDC, cr_logic_common, tcg_gen_andc_i32); +TRANS(CREQV, cr_logic_common, tcg_gen_eqv_i32); +TRANS(CRORC, cr_logic_common, tcg_gen_orc_i32); + static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool comput= e_ca, bool compute_ov, bool compute_rc0) { --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897489; cv=none; d=zohomail.com; s=zohoarc; b=HJ3qN3gQk3xyIQ+p+abTd9VqDtEWuFcadakla58EmZiZIlD4UROZJgZkey23cH3bJEO7dmIj9Dnk3wAYWPvPoN769zL+Rf93JoMdosYR3wYa4AQB+dIi4ZlQUFJrJdTQl66VtsG95Fd7YcS9P0D6ytnJ44bol3de8LcupZ/yo7o= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=tJOPf5WbdkLXk++Df 5PfKNl2a09Dtnvx0Ohj3tbMq3M=; b=SLEWS8ntzHKr405Hq7TMZuVNFDTXyMaTU cz4Gb96sRoKV7EtTO1W7e92Du6gBfFDVLqJYCWUYYTupndos56rU8hZ5N8ZE5xuh DQ2+1iqZJLeMiNK8XiNbhgAO8FVzUOR7TbgwlOY9lMUsplNBnVUyKstKNOMcmIos 023suDL89PK/uujbQ/VRW3cd3bqhiO59SjHfSWLDmJVy78RtTvFGt2aEFP/4hOVV NkHeTiWucE5qfEaTVSsYc+Kmq5VtnRxqUSEcB5KpXz1xHSNz3i2q5JAZEw1xfb17 cxFh2/jCUYjUKQwoIQu2qOZZfhytwC/cGlyJGZRB4L19wZbsSl/dw== From: Harsh Prateek Bora To: qemu-devel@nongnu.org Cc: Chinmay Rath , Glenn Miles , Amit Machhiwal , Aniket Sahu Subject: [PULL 26/41] target/ppc: make do_ea_calc_ra available for 32 bit builds Date: Fri, 28 Aug 2026 11:37:01 +0530 Message-ID: <20260828060716.91672-27-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com> References: <20260828060716.91672-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: _zZrpnhSjhyU1jSfXeD_bOYAFvTlsnLd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX/8UuR5iZ3Ire icYIPq5S0wWhrVZdKx3zCccMCgKhlC7efwvAeMoNG9TAYtS5nn+ZD3CplFyiXSoWG2AioQp/8ny KNJsbft2JOrUSPywOf8Ivc0XhAp52q4zHH3J9pFqWmrZsSn7XbyPePyS10zpqa9ctqmZIcuSnia Rsh2YQW373ordwA6rUKN/Sw1GphjC4T/NW2ITov+WJibit7lHv44NBfaj8kifpXdrsTkpSHkO1n DBxFn491dFkcO/RD8JMdW2pJwPJbVkVoDq6oGGII5b5JPewuvYfKuoIFU65a8h5szi0xfQqz3gl iBOggV5Dnx12fCAoVSxxokG8nkwWd+RaF6idLNhKK4ITySvO7shNCRmFj3evw/OrdHTZR5M9baW 6md+IJKi/QyJeG+s+iKYjDG1YvpfLuYk40Cs/Jtdi/8WnbVejmg2uN1HlWbkQNdscYxSXQGHHQy 7NvV7NBeR8rHZjEYkag== X-Authority-Analysis: v=2.4 cv=Y/nIdBeN c=1 sm=1 tr=0 ts=6a9125e6 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=Sv0fKeRqtYgA:10 a=f7IdgyKtn90A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=tTuln9y6vRRPCHsaWd0A:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX6WkKq15Z+DGE nk2qFYKTMiXvfFnh2/XIP8jVb7B9btpbXXCYxThJQPqO/tyS9zKTXJV0wuBy5aKGUXagQ0oRMms GDI5Z3fnVBtewejjV0VVhC78yS6bRWM= X-Proofpoint-ORIG-GUID: _zZrpnhSjhyU1jSfXeD_bOYAFvTlsnLd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_01,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280050 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897490956158500 Content-Type: text/plain; charset="utf-8" From: Chinmay Rath There is no reason to keep do_ea_calc_ra exclusive to TARGET_PPC64. Make it available for PPC32 builds. Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-23-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c5361d8db5..c45883ac30 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2397,7 +2397,6 @@ static TCGv do_ea_calc(DisasContext *ctx, int ra, TCG= v displ) return ea; } =20 -#if defined(TARGET_PPC64) /* EA <- (ra =3D=3D 0) ? 0 : GPR[ra] */ static TCGv do_ea_calc_ra(DisasContext *ctx, int ra) { @@ -2411,7 +2410,6 @@ static TCGv do_ea_calc_ra(DisasContext *ctx, int ra) } return EA; } -#endif =20 /*** Integer load = ***/ #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Shivang Upadhyay Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-24-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/helper.h | 6 +- target/ppc/insn32.decode | 7 ++ target/ppc/mem_helper.c | 6 +- target/ppc/translate.c | 102 --------------------- target/ppc/translate/fixedpoint-impl.c.inc | 102 +++++++++++++++++++++ 5 files changed, 115 insertions(+), 108 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6e14f02598..18ef7786a4 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -45,9 +45,9 @@ DEF_HELPER_1(check_tlb_flush_global, void, env) =20 DEF_HELPER_3(lmw, void, env, tl, i32) DEF_HELPER_FLAGS_3(stmw, TCG_CALL_NO_WG, void, env, tl, i32) -DEF_HELPER_4(lsw, void, env, tl, i32, i32) -DEF_HELPER_5(lswx, void, env, tl, i32, i32, i32) -DEF_HELPER_FLAGS_4(stsw, TCG_CALL_NO_WG, void, env, tl, i32, i32) +DEF_HELPER_4(LSW, void, env, tl, i32, i32) +DEF_HELPER_5(LSWX, void, env, tl, i32, i32, i32) +DEF_HELPER_FLAGS_4(STSW, TCG_CALL_NO_WG, void, env, tl, i32, i32) DEF_HELPER_FLAGS_3(dcbz, TCG_CALL_NO_WG, void, env, tl, int) #ifdef TARGET_PPC64 DEF_HELPER_FLAGS_2(dcbzl, TCG_CALL_NO_WG, void, env, tl) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 5e5490b169..a88ba1fce1 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -527,6 +527,13 @@ CREQV 010011 ..... ..... ..... 0100100001 - = @X CRANDC 010011 ..... ..... ..... 0010000001 - @X CRORC 010011 ..... ..... ..... 0110100001 - @X =20 +# Fixed Point Move Assist Instructions + +LSWI 011111 ..... ..... ..... 1 001010101 - @X +LSWX 011111 ..... ..... ..... 1 000010101 - @X +STSWI 011111 ..... ..... ..... 1 011010101 - @X +STSWX 011111 ..... ..... ..... 1 010010101 - @X + # Fixed-Point Hash Instructions =20 HASHST 011111 ..... ..... ..... 1011010010 . @X_DW diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 8ad6945590..10c648cf06 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -190,7 +190,7 @@ static void do_lsw(CPUPPCState *env, target_ulong addr,= uint32_t nb, env->gpr[reg] =3D val; } =20 -void helper_lsw(CPUPPCState *env, target_ulong addr, +void helper_LSW(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg) { do_lsw(env, addr, nb, reg, GETPC()); @@ -202,7 +202,7 @@ void helper_lsw(CPUPPCState *env, target_ulong addr, * this is valid, but rA won't be loaded. For now, I'll follow the * spec... */ -void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg, +void helper_LSWX(CPUPPCState *env, target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb) { if (likely(xer_bc !=3D 0)) { @@ -218,7 +218,7 @@ void helper_lswx(CPUPPCState *env, target_ulong addr, u= int32_t reg, } } =20 -void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb, +void helper_STSW(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg) { uintptr_t raddr =3D GETPC(); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c45883ac30..d17d77a9d9 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2595,104 +2595,6 @@ static void gen_stmw(DisasContext *ctx) gen_helper_stmw(tcg_env, t0, t1); } =20 -/*** Integer load and store strings = ***/ - -/* lswi */ -/* - * PowerPC32 specification says we must generate an exception if rA is - * in the range of registers to be loaded. In an other hand, IBM says - * this is valid, but rA won't be loaded. For now, I'll follow the - * spec... - */ -static void gen_lswi(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1, t2; - int nb =3D NB(ctx->opcode); - int start =3D rD(ctx->opcode); - int ra =3D rA(ctx->opcode); - int nr; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - if (nb =3D=3D 0) { - nb =3D 32; - } - nr =3D DIV_ROUND_UP(nb, 4); - if (unlikely(lsw_reg_in_range(start, nr, ra))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - gen_addr_register(ctx, t0); - t1 =3D tcg_constant_i32(nb); - t2 =3D tcg_constant_i32(start); - gen_helper_lsw(tcg_env, t0, t1, t2); -} - -/* lswx */ -static void gen_lswx(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1, t2, t3; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - t1 =3D tcg_constant_i32(rD(ctx->opcode)); - t2 =3D tcg_constant_i32(rA(ctx->opcode)); - t3 =3D tcg_constant_i32(rB(ctx->opcode)); - gen_helper_lswx(tcg_env, t0, t1, t2, t3); -} - -/* stswi */ -static void gen_stswi(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1, t2; - int nb =3D NB(ctx->opcode); - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - gen_addr_register(ctx, t0); - if (nb =3D=3D 0) { - nb =3D 32; - } - t1 =3D tcg_constant_i32(nb); - t2 =3D tcg_constant_i32(rS(ctx->opcode)); - gen_helper_stsw(tcg_env, t0, t1, t2); -} - -/* stswx */ -static void gen_stswx(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1, t2; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - t1 =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t1, cpu_xer); - tcg_gen_andi_i32(t1, t1, 0x7F); - t2 =3D tcg_constant_i32(rS(ctx->opcode)); - gen_helper_stsw(tcg_env, t0, t1, t2); -} =20 #if !defined(CONFIG_USER_ONLY) static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) @@ -4901,10 +4803,6 @@ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000,= PPC_NONE, PPC2_ISA205), GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), -GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), -GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), -GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index d0b3bda97f..4b79e24f6f 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -584,6 +584,108 @@ TRANS(CRANDC, cr_logic_common, tcg_gen_andc_i32); TRANS(CREQV, cr_logic_common, tcg_gen_eqv_i32); TRANS(CRORC, cr_logic_common, tcg_gen_orc_i32); =20 +/*** Integer load and store strings = ***/ + +/* lswi */ +static bool trans_LSWI(DisasContext *ctx, arg_LSWI *a) +{ + TCGv t0; + TCGv_i32 t1, t2; + int nb =3D a->rb; + int start =3D a->rt; + int ra =3D a->ra; + int nr; + + REQUIRE_INSNS_FLAGS(ctx, STRING); + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + if (nb =3D=3D 0) { + nb =3D 32; + } + nr =3D DIV_ROUND_UP(nb, 4); + if (unlikely(lsw_reg_in_range(start, nr, ra))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + t0 =3D do_ea_calc_ra(ctx, ra); + t1 =3D tcg_constant_i32(nb); + t2 =3D tcg_constant_i32(start); + gen_helper_LSW(tcg_env, t0, t1, t2); + + return true; +} + +/* lswx */ +static bool trans_LSWX(DisasContext *ctx, arg_LSWX *a) +{ + TCGv t0; + TCGv_i32 t1, t2, t3; + + REQUIRE_INSNS_FLAGS(ctx, STRING); + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + + gen_set_access_type(ctx, ACCESS_INT); + t0 =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + t1 =3D tcg_constant_i32(a->rt); + t2 =3D tcg_constant_i32(a->ra); + t3 =3D tcg_constant_i32(a->rb); + gen_helper_LSWX(tcg_env, t0, t1, t2, t3); + + return true; +} + +/* stswi */ +static bool trans_STSWI(DisasContext *ctx, arg_STSWI *a) +{ + TCGv t0; + TCGv_i32 t1, t2; + int nb =3D a->rb; + + REQUIRE_INSNS_FLAGS(ctx, STRING); + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + t0 =3D do_ea_calc_ra(ctx, a->ra); + if (nb =3D=3D 0) { + nb =3D 32; + } + t1 =3D tcg_constant_i32(nb); + t2 =3D tcg_constant_i32(a->rt); + gen_helper_STSW(tcg_env, t0, t1, t2); + + return true; +} + +/* stswx */ +static bool trans_STSWX(DisasContext *ctx, arg_STSWX *a) +{ + TCGv t0; + TCGv_i32 t1, t2; + + REQUIRE_INSNS_FLAGS(ctx, STRING); + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + t0 =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 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Signed-off-by: Shivang Upadhyay Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-25-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/helper.h | 30 +-- target/ppc/insn32.decode | 39 ++++ target/ppc/int_helper.c | 32 +-- target/ppc/translate/vmx-impl.c.inc | 299 ++++++++++++---------------- target/ppc/translate/vmx-ops.c.inc | 22 -- 5 files changed, 199 insertions(+), 223 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 18ef7786a4..7da752c69b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -349,21 +349,21 @@ DEF_HELPER_FLAGS_3(vshasigmaw, TCG_CALL_NO_RWG, void,= avr, avr, i32) DEF_HELPER_FLAGS_3(vshasigmad, TCG_CALL_NO_RWG, void, avr, avr, i32) DEF_HELPER_FLAGS_4(vpermxor, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) =20 -DEF_HELPER_FLAGS_4(bcdadd, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdsub, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdcfn, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdctn, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdcfz, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdctz, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdcfsq, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdctsq, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdcpsgn, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdsetsgn, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcds, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdus, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdsr, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdtrunc, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdutrunc, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDADD, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDSUB, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCFN, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCTN, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCFZ, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCTZ, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCFSQ, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCTSQ, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDCPSGN, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDSETSGN, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDS, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDUS, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDSR, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDTRUNC, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDUTRUNC, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) =20 DEF_HELPER_4(XSADDDP, void, env, vsr, vsr, vsr) DEF_HELPER_5(xsaddqp, void, env, i32, vsr, vsr, vsr) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index a88ba1fce1..69d60605bd 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -90,6 +90,9 @@ &VX vrt vra vrb @VX ...... vrt:5 vra:5 vrb:5 .......... . &VX =20 +&VX_ps vrt vra vrb ps +@VX_ps ...... vrt:5 vra:5 vrb:5 . ps:1 ........ . &VX_ps + &VX_bf bf vra vrb @VX_bf ...... bf:3 .. vra:5 vrb:5 ........... &VX_bf =20 @@ -108,6 +111,9 @@ &VX_tb vrt vrb @VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb =20 +&VX_tb_ps vrt vrb ps +@VX_tb_ps ...... vrt:5 ..... vrb:5 . ps:1 ......... &VX_t= b_ps + &X rt ra rb @X ...... rt:5 ra:5 rb:5 .......... . &X =20 @@ -991,6 +997,10 @@ VADDSBS 000100 ..... ..... ..... 01100000000 = @VX VADDSHS 000100 ..... ..... ..... 01101000000 @VX VADDSWS 000100 ..... ..... ..... 01110000000 @VX =20 +VADDUBM 000100 ..... ..... ..... 00000000000 @VX +VADDUHM 000100 ..... ..... ..... 00001000000 @VX +VADDUWM 000100 ..... ..... ..... 00010000000 @VX +VADDUDM 000100 ..... ..... ..... 00011000000 @VX VADDUBS 000100 ..... ..... ..... 01000000000 @VX VADDUHS 000100 ..... ..... ..... 01001000000 @VX VADDUWS 000100 ..... ..... ..... 01010000000 @VX @@ -1006,6 +1016,10 @@ VSUBSBS 000100 ..... ..... ..... 11100000000= @VX VSUBSHS 000100 ..... ..... ..... 11101000000 @VX VSUBSWS 000100 ..... ..... ..... 11110000000 @VX =20 +VSUBUBM 000100 ..... ..... ..... 10000000000 @VX +VSUBUHM 000100 ..... ..... ..... 10001000000 @VX +VSUBUWM 000100 ..... ..... ..... 10010000000 @VX +VSUBUDM 000100 ..... ..... ..... 10011000000 @VX VSUBUBS 000100 ..... ..... ..... 11000000000 @VX VSUBUHS 000100 ..... ..... ..... 11001000000 @VX VSUBUWS 000100 ..... ..... ..... 11010000000 @VX @@ -1099,6 +1113,13 @@ VMULHSD 000100 ..... ..... ..... 01111001001= @VX VMULHUD 000100 ..... ..... ..... 01011001001 @VX VMULLD 000100 ..... ..... ..... 00111001001 @VX =20 +VMULUWM 000100 ..... ..... ..... 00010001001 @VX + +VMUL10UQ 000100 ..... ..... ..... 01000000001 @VX +VMUL10EUQ 000100 ..... ..... ..... 01001000001 @VX +VMUL10ECUQ 000100 ..... ..... ..... 00001000001 @VX +VMUL10CUQ 000100 ..... ..... ..... 00000000001 @VX + ## Vector Multiply-Sum Instructions =20 VMSUMUBM 000100 ..... ..... ..... ..... 100100 @VA @@ -1141,6 +1162,24 @@ VPKSWSS 000100 ..... ..... ..... 0011100111 = 0 @VX VPKSDSS 000100 ..... ..... ..... 1011100111 0 @VX VPKPX 000100 ..... ..... ..... 0110000111 0 @VX =20 +## Decimal Integer Arithmetic Instructions + +BCDADD 000100 ..... ..... ..... 1.000000001 @VX_ps +BCDSUB 000100 ..... ..... ..... 1.001000001 @VX_ps +BCDUS 000100 ..... ..... ..... 10010000001 @VX +BCDS 000100 ..... ..... ..... 1.011000001 @VX_ps +BCDCTSQ 000100 ..... 00000 ..... 10110000001 @VX_tb +BCDCTN 000100 ..... 00101 ..... 10110000001 @VX_tb +BCDCFSQ 000100 ..... 00010 ..... 1.110000001 @VX_tb_ps +BCDCTZ 000100 ..... 00100 ..... 1.110000001 @VX_tb_ps +BCDCFZ 000100 ..... 00110 ..... 1.110000001 @VX_tb_ps +BCDCFN 000100 ..... 00111 ..... 1.110000001 @VX_tb_ps +BCDSETSGN 000100 ..... 11111 ..... 1.110000001 @VX_tb_ps +BCDCPSGN 000100 ..... ..... ..... 01101000001 @VX +BCDSR 000100 ..... ..... ..... 1.111000001 @VX_ps +BCDTRUNC 000100 ..... ..... ..... 1.100000001 @VX_ps +BCDUTRUNC 000100 ..... ..... ..... 10101000001 @VX + # VSX Load/Store Instructions =20 LXSD 111001 ..... ..... .............. 10 @DS diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 8e8076a92c..86346f5b9a 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -2348,7 +2348,7 @@ static void bcd_sub_mag(ppc_avr_t *t, ppc_avr_t *a, p= pc_avr_t *b, int *invalid, *overflow =3D carry; } =20 -uint32_t helper_bcdadd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t= ps) +uint32_t helper_BCDADD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t= ps) { =20 int sgna =3D bcd_get_sgn(a); @@ -2395,7 +2395,7 @@ uint32_t helper_bcdadd(ppc_avr_t *r, ppc_avr_t *a, p= pc_avr_t *b, uint32_t ps) return cr; } =20 -uint32_t helper_bcdsub(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t= ps) +uint32_t helper_BCDSUB(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t= ps) { ppc_avr_t bcopy =3D *b; int sgnb =3D bcd_get_sgn(b); @@ -2406,10 +2406,10 @@ uint32_t helper_bcdsub(ppc_avr_t *r, ppc_avr_t *a,= ppc_avr_t *b, uint32_t ps) } /* else invalid ... defer to bcdadd code for proper handling */ =20 - return helper_bcdadd(r, a, &bcopy, ps); + return helper_BCDADD(r, a, &bcopy, ps); } =20 -uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCFN(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr =3D 0; @@ -2445,7 +2445,7 @@ uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, ui= nt32_t ps) return cr; } =20 -uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCTN(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr =3D 0; @@ -2479,7 +2479,7 @@ uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, ui= nt32_t ps) return cr; } =20 -uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCFZ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr =3D 0; @@ -2523,7 +2523,7 @@ uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, ui= nt32_t ps) return cr; } =20 -uint32_t helper_bcdctz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCTZ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr =3D 0; @@ -2582,7 +2582,7 @@ static inline int ucmp128(uint64_t alo, uint64_t ahi, (ahi > bhi ? 1 : -1); } =20 -uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCFSQ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr; @@ -2640,7 +2640,7 @@ uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, u= int32_t ps) return cr; } =20 -uint32_t helper_bcdctsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCTSQ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { uint8_t i; int cr; @@ -2680,7 +2680,7 @@ uint32_t helper_bcdctsq(ppc_avr_t *r, ppc_avr_t *b, u= int32_t ps) return cr; } =20 -uint32_t helper_bcdcpsgn(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_= t ps) +uint32_t helper_BCDCPSGN(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_= t ps) { int i; int invalid =3D 0; @@ -2703,7 +2703,7 @@ uint32_t helper_bcdcpsgn(ppc_avr_t *r, ppc_avr_t *a, = ppc_avr_t *b, uint32_t ps) return bcd_cmp_zero(r); } =20 -uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDSETSGN(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int sgnb =3D bcd_get_sgn(b); =20 @@ -2717,7 +2717,7 @@ uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b,= uint32_t ps) return bcd_cmp_zero(r); } =20 -uint32_t helper_bcds(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDS(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps) { int cr; int i =3D a->VsrSB(7); @@ -2753,7 +2753,7 @@ uint32_t helper_bcds(ppc_avr_t *r, ppc_avr_t *a, ppc_= avr_t *b, uint32_t ps) return cr; } =20 -uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t p= s) +uint32_t helper_BCDUS(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t p= s) { int cr; int i; @@ -2790,7 +2790,7 @@ uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc= _avr_t *b, uint32_t ps) return cr; } =20 -uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t p= s) +uint32_t helper_BCDSR(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t p= s) { int cr; int unused =3D 0; @@ -2836,7 +2836,7 @@ uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc= _avr_t *b, uint32_t ps) return cr; } =20 -uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_= t ps) +uint32_t helper_BCDTRUNC(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_= t ps) { uint64_t mask; uint32_t ox_flag =3D 0; @@ -2869,7 +2869,7 @@ uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, = ppc_avr_t *b, uint32_t ps) return bcd_cmp_zero(&ret) | ox_flag; } =20 -uint32_t helper_bcdutrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32= _t ps) +uint32_t helper_BCDUTRUNC(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32= _t ps) { int i; uint64_t mask; diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 65230f3461..4e7fe22156 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -142,7 +142,8 @@ static void gen_mtvscr(DisasContext *ctx) gen_helper_mtvscr(tcg_env, val); } =20 -static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry) +static bool do_vx_vmul10(DisasContext *ctx, arg_VX *a, + bool add_cin, bool ret_carry) { TCGv_i64 t0; TCGv_i64 t1; @@ -150,10 +151,7 @@ static void gen_vx_vmul10(DisasContext *ctx, bool add_= cin, bool ret_carry) TCGv_i64 avr; TCGv_i64 ten, z; =20 - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } + REQUIRE_VECTOR(ctx); =20 t0 =3D tcg_temp_new_i64(); t1 =3D tcg_temp_new_i64(); @@ -163,54 +161,32 @@ static void gen_vx_vmul10(DisasContext *ctx, bool add= _cin, bool ret_carry) z =3D tcg_constant_i64(0); =20 if (add_cin) { - get_avr64(avr, rA(ctx->opcode), false); + get_avr64(avr, a->vra, false); tcg_gen_mulu2_i64(t0, t1, avr, ten); - get_avr64(avr, rB(ctx->opcode), false); + get_avr64(avr, a->vrb, false); tcg_gen_andi_i64(t2, avr, 0xF); tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); - set_avr64(rD(ctx->opcode), avr, false); + set_avr64(a->vrt, avr, false); } else { - get_avr64(avr, rA(ctx->opcode), false); + get_avr64(avr, a->vra, false); tcg_gen_mulu2_i64(avr, t2, avr, ten); - set_avr64(rD(ctx->opcode), avr, false); + set_avr64(a->vrt, avr, false); } =20 if (ret_carry) { - get_avr64(avr, rA(ctx->opcode), true); + get_avr64(avr, a->vra, true); tcg_gen_mulu2_i64(t0, t1, avr, ten); tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); - set_avr64(rD(ctx->opcode), avr, false); - set_avr64(rD(ctx->opcode), z, true); + set_avr64(a->vrt, avr, false); + set_avr64(a->vrt, z, true); } else { - get_avr64(avr, rA(ctx->opcode), true); + get_avr64(avr, a->vra, true); tcg_gen_mul_i64(t0, avr, ten); tcg_gen_add_i64(avr, t0, t2); - set_avr64(rD(ctx->opcode), avr, true); + set_avr64(a->vrt, avr, true); } -} - -#define GEN_VX_VMUL10(name, add_cin, ret_carry) \ - static void glue(gen_, name)(DisasContext *ctx) \ - { gen_vx_vmul10(ctx, add_cin, ret_carry); } - -GEN_VX_VMUL10(vmul10uq, 0, 0); -GEN_VX_VMUL10(vmul10euq, 1, 0); -GEN_VX_VMUL10(vmul10cuq, 0, 1); -GEN_VX_VMUL10(vmul10ecuq, 1, 1); =20 -#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - tcg_op(vece, \ - avr_full_offset(rD(ctx->opcode)), \ - avr_full_offset(rA(ctx->opcode)), \ - avr_full_offset(rB(ctx->opcode)), \ - 16, 16); \ + return true; } =20 #define GEN_VXFORM(name, opc2, opc3) \ @@ -338,19 +314,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], = rb); \ } =20 -GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0); -GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \ - vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800) -GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1); -GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \ - vmul10ecuq, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2); -GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3); -GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16); -GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17); -GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18); -GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19); - static bool do_vmrg(DisasContext *ctx, arg_VX *a, void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr)) { @@ -370,6 +333,38 @@ TRANS_FLAGS(ALTIVEC, VMRGLB, do_vmrg, gen_helper_VMRGL= B); TRANS_FLAGS(ALTIVEC, VMRGLH, do_vmrg, gen_helper_VMRGLH); TRANS_FLAGS(ALTIVEC, VMRGLW, do_vmrg, gen_helper_VMRGLW); =20 +static bool do_vx_vaddsubm(DisasContext *ctx, arg_VX *a, MemOp vece, + void (*gen_op)(unsigned, uint32_t, uint32_t, + uint32_t, uint32_t, uint32_t)) +{ + REQUIRE_VECTOR(ctx); + + gen_op(vece, + avr_full_offset(a->vrt), + avr_full_offset(a->vra), + avr_full_offset(a->vrb), + 16, 16); + + return true; +} + +TRANS_FLAGS(ALTIVEC, VADDUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_add) +TRANS_FLAGS(ALTIVEC, VADDUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_add) +TRANS_FLAGS(ALTIVEC, VADDUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_add) +TRANS_FLAGS2(ALTIVEC_207, VADDUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_add) + +TRANS_FLAGS(ALTIVEC, VSUBUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_sub) +TRANS_FLAGS(ALTIVEC, VSUBUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_sub) +TRANS_FLAGS(ALTIVEC, VSUBUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_sub) +TRANS_FLAGS2(ALTIVEC_207, VSUBUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_sub) + +TRANS_FLAGS2(ALTIVEC_207, VMULUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_mul) + +TRANS_FLAGS2(ISA300, VMUL10CUQ, do_vx_vmul10, false, true) +TRANS_FLAGS2(ISA300, VMUL10ECUQ, do_vx_vmul10, true, true) +TRANS_FLAGS2(ISA300, VMUL10UQ, do_vx_vmul10, false, false) +TRANS_FLAGS2(ISA300, VMUL10EUQ, do_vx_vmul10, true, false) + static void trans_vmrgew(DisasContext *ctx) { int VT =3D rD(ctx->opcode); @@ -684,7 +679,6 @@ static void trans_vclzd(DisasContext *ctx) set_avr64(VT, avr, false); } =20 -GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2); GEN_VXFORM(vsrv, 2, 28); GEN_VXFORM(vslv, 2, 29); GEN_VXFORM(vslo, 6, 16); @@ -2523,126 +2517,93 @@ GEN_VXFORM(vpmsumb, 4, 16) GEN_VXFORM(vpmsumh, 4, 17) GEN_VXFORM(vpmsumw, 4, 18) =20 -#define GEN_BCD(op) \ -static void gen_##op(DisasContext *ctx) \ -{ \ - TCGv_ptr ra, rb, rd; \ - TCGv_i32 ps; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - ra =3D gen_avr_ptr(rA(ctx->opcode)); \ - rb =3D gen_avr_ptr(rB(ctx->opcode)); \ - rd =3D gen_avr_ptr(rD(ctx->opcode)); \ - \ - ps =3D tcg_constant_i32((ctx->opcode & 0x200) !=3D 0); \ - \ - gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \ -} - -#define GEN_BCD2(op) \ -static void gen_##op(DisasContext *ctx) \ -{ \ - TCGv_ptr rd, rb; \ - TCGv_i32 ps; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - rb =3D gen_avr_ptr(rB(ctx->opcode)); \ - rd =3D gen_avr_ptr(rD(ctx->opcode)); \ - \ - ps =3D tcg_constant_i32((ctx->opcode & 0x200) !=3D 0); \ - \ - gen_helper_##op(cpu_crf[6], rd, rb, ps); \ -} - -GEN_BCD(bcdadd) -GEN_BCD(bcdsub) -GEN_BCD2(bcdcfn) -GEN_BCD2(bcdctn) -GEN_BCD2(bcdcfz) -GEN_BCD2(bcdctz) -GEN_BCD2(bcdcfsq) -GEN_BCD2(bcdctsq) -GEN_BCD2(bcdsetsgn) -GEN_BCD(bcdcpsgn); -GEN_BCD(bcds); -GEN_BCD(bcdus); -GEN_BCD(bcdsr); -GEN_BCD(bcdtrunc); -GEN_BCD(bcdutrunc); - -static void gen_xpnd04_1(DisasContext *ctx) -{ - switch (opc4(ctx->opcode)) { - case 0: - gen_bcdctsq(ctx); - break; - case 2: - gen_bcdcfsq(ctx); - break; - case 4: - gen_bcdctz(ctx); - break; - case 5: - gen_bcdctn(ctx); - break; - case 6: - gen_bcdcfz(ctx); - break; - case 7: - gen_bcdcfn(ctx); - break; - case 31: - gen_bcdsetsgn(ctx); - break; - default: - gen_invalid(ctx); - break; - } +static bool do_bcd_ps(DisasContext *ctx, arg_VX_ps *a, + void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32)) +{ + TCGv_ptr ra, rb, rd; + TCGv_i32 ps; + + REQUIRE_VECTOR(ctx); + + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + ps =3D tcg_constant_i32(a->ps); + + helper(cpu_crf[6], rd, ra, rb, ps); + return true; } =20 -static void gen_xpnd04_2(DisasContext *ctx) -{ - switch (opc4(ctx->opcode)) { - case 0: - gen_bcdctsq(ctx); - break; - case 2: - gen_bcdcfsq(ctx); - break; - case 4: - gen_bcdctz(ctx); - break; - case 6: - gen_bcdcfz(ctx); - break; - case 7: - gen_bcdcfn(ctx); - break; - case 31: - gen_bcdsetsgn(ctx); - break; - default: - gen_invalid(ctx); - break; - } +static bool do_bcd(DisasContext *ctx, arg_VX *a, + void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32)) +{ + TCGv_ptr ra, rb, rd; + TCGv_i32 ps; + + REQUIRE_VECTOR(ctx); + + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + ps =3D tcg_constant_i32(0); + + helper(cpu_crf[6], rd, ra, rb, ps); + return true; } =20 -GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \ - bcdadd, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \ - bcdsub, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \ - bcds, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \ - bcdus, PPC_NONE, PPC2_ISA300) +static bool do_bcd_tb(DisasContext *ctx, arg_VX_tb *a, + void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32)) +{ + TCGv_ptr rd, rb; + TCGv_i32 ps; + + REQUIRE_VECTOR(ctx); + + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + + ps =3D tcg_constant_i32(0); + + helper(cpu_crf[6], rd, rb, ps); + + return true; +} + +static bool do_bcd_tb_ps(DisasContext *ctx, arg_VX_tb_ps *a, + void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32)) +{ + TCGv_ptr rd, rb; + TCGv_i32 ps; + + REQUIRE_VECTOR(ctx); + + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + + ps =3D tcg_constant_i32(a->ps); + + helper(cpu_crf[6], rd, rb, ps); + + return true; +} + +TRANS_FLAGS2(ALTIVEC_207, BCDADD, do_bcd_ps, gen_helper_BCDADD) +TRANS_FLAGS2(ALTIVEC_207, BCDSUB, do_bcd_ps, gen_helper_BCDSUB) +TRANS_FLAGS2(ISA300, BCDUS, do_bcd, gen_helper_BCDUS) +TRANS_FLAGS2(ISA300, BCDS, do_bcd_ps, gen_helper_BCDS) +TRANS_FLAGS2(ISA300, BCDCFN, do_bcd_tb_ps, gen_helper_BCDCFN) +TRANS_FLAGS2(ISA300, BCDCTN, do_bcd_tb, gen_helper_BCDCTN) +TRANS_FLAGS2(ISA300, BCDCFZ, do_bcd_tb_ps, gen_helper_BCDCFZ) +TRANS_FLAGS2(ISA300, BCDCTZ, do_bcd_tb_ps, gen_helper_BCDCTZ) +TRANS_FLAGS2(ISA300, BCDCFSQ, do_bcd_tb_ps, gen_helper_BCDCFSQ) +TRANS_FLAGS2(ISA300, BCDCTSQ, do_bcd_tb, gen_helper_BCDCTSQ) +TRANS_FLAGS2(ISA300, BCDSETSGN, do_bcd_tb_ps, gen_helper_BCDSETSGN) +TRANS_FLAGS2(ISA300, BCDCPSGN, do_bcd, gen_helper_BCDCPSGN) +TRANS_FLAGS2(ISA300, BCDTRUNC, do_bcd_ps, gen_helper_BCDTRUNC) +TRANS_FLAGS2(ISA300, BCDUTRUNC, do_bcd, gen_helper_BCDUTRUNC) +TRANS_FLAGS2(ISA300, BCDSR, do_bcd_ps, gen_helper_BCDSR) =20 static void gen_vsbox(DisasContext *ctx) { @@ -3502,5 +3463,3 @@ TRANS_FLAGS2(ISA310, VMODUQ, do_vx_helper, gen_helper= _VMODUQ) #undef GEN_VXFORM_NOA #undef GEN_VXFORM_UIMM #undef GEN_VAFORM_PAIRED - -#undef GEN_BCD2 diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-= ops.c.inc index 2820976c0f..c1951c6975 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -24,39 +24,17 @@ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000= 000, type0, type1) GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, = tp1), =20 -GEN_VXFORM_DUAL(vaddubm, vmul10cuq, 0, 0, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vadduhm, vmul10ecuq, 0, 1, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM(vadduwm, 0, 2), -GEN_VXFORM_207(vaddudm, 0, 3), -GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300), -GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300), -GEN_VXFORM_300(bcds, 0, 27), GEN_VXFORM_300(vextublx, 6, 24), GEN_VXFORM_300(vextuhlx, 6, 25), GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207), GEN_VXFORM_300(vextubrx, 6, 28), GEN_VXFORM_300(vextuhrx, 6, 29), GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_207(vmuluwm, 4, 2), GEN_VXFORM_300(vsrv, 2, 28), GEN_VXFORM_300(vslv, 2, 29), GEN_VXFORM(vslo, 6, 16), GEN_VXFORM(vsro, 6, 17), =20 -GEN_VXFORM(xpnd04_1, 0, 22), -GEN_VXFORM_300(bcdsr, 0, 23), -GEN_VXFORM_300(bcdsr, 0, 31), -GEN_VXFORM_300_EXT(vmul10uq, 0, 8, 0x0000F800), -GEN_VXFORM_300(vmul10euq, 0, 9), -GEN_VXFORM_300(bcdcpsgn, 0, 13), -GEN_VXFORM_207(bcdadd, 0, 24), -GEN_VXFORM_207(bcdsub, 0, 25), -GEN_VXFORM_300(bcdtrunc, 0, 28), -GEN_VXFORM_300(xpnd04_2, 0, 30), -GEN_VXFORM_300(bcdtrunc, 0, 20), -GEN_VXFORM_300(bcdutrunc, 0, 21), GEN_VXFORM(vsl, 2, 7), GEN_VXFORM(vsr, 2, 11), GEN_VXFORM(vsum4ubs, 4, 24), --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897488; cv=none; d=zohomail.com; s=zohoarc; b=HBg9iuie+JTXz4CoYaH2UTqmbk4ul5rH6yJmJZM9LQ1WSPsBkKMV1TQxwANIash9UtWQ28u3+wcatKf7JcdHhvVB7Jq757y25W7You9x4fc5xz5gAojAew1AMBDs29S6WOBRpbGR0f2nXXapGwBtojtDzIqRqwIu7HlenYbSPmY= ARC-Message-Signature: i=1; a=rsa-sha256; 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Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897489034158500 Content-Type: text/plain; charset="utf-8" From: Tanushree Shah -Moving the following instructions to decodetree specification: rlwimi : M-form rlwimi. : M-form rlwinm : M-form rlwinm. : M-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the "-d in_asm,op" flag. Additionally, validated using small assembly tests confirming the destination register is correctly updated based on rotated and masked source values and confirmed that the value was same before and after the change Signed-off-by: Tanushree Shah Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Reviewed-by: Amit Machhiwal Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-26-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 6 ++ target/ppc/translate.c | 106 --------------------- target/ppc/translate/fixedpoint-impl.c.inc | 102 ++++++++++++++++++++ 3 files changed, 108 insertions(+), 106 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 69d60605bd..92ee278f63 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -312,6 +312,9 @@ =20 @Z23_te_tbp ...... ....0 te:5 ....0 rmc:2 ........ rc:1 &Z23_te_tb= frt=3D%z23_frtp frb=3D%z23_frbp =20 +&M ra rs sh mb me rc:bool +@M ...... rs:5 ra:5 sh:5 mb:5 me:5 rc:1 &M + ### Fixed-Point Load Instructions =20 LBZ 100010 ..... ..... ................ @D @@ -561,6 +564,9 @@ SRADI 011111 ..... ..... ..... 110011101 . . = @XS =20 EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS =20 +RLWIMI 010100 ..... ..... ..... ..... ...... @M +RLWINM 010101 ..... ..... ..... ..... ...... @M + ## BCD Assist =20 ADDG6S 011111 ..... ..... ..... - 001001010 - @X diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d17d77a9d9..ce94f9e4e6 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2012,110 +2012,6 @@ static void gen_pause(DisasContext *ctx) =20 /*** Integer rotate = ***/ =20 -/* rlwimi & rlwimi. */ -static void gen_rlwimi(DisasContext *ctx) -{ - TCGv t_ra =3D cpu_gpr[rA(ctx->opcode)]; - TCGv t_rs =3D cpu_gpr[rS(ctx->opcode)]; - uint32_t sh =3D SH(ctx->opcode); - uint32_t mb =3D MB(ctx->opcode); - uint32_t me =3D ME(ctx->opcode); - - if (sh =3D=3D (31 - me) && mb <=3D me) { - tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); - } else { - target_ulong mask; - bool mask_in_32b =3D true; - TCGv t1; - -#if defined(TARGET_PPC64) - mb +=3D 32; - me +=3D 32; -#endif - mask =3D MASK(mb, me); - -#if defined(TARGET_PPC64) - if (mask > 0xffffffffu) { - mask_in_32b =3D false; - } -#endif - t1 =3D tcg_temp_new(); - if (mask_in_32b) { - TCGv_i32 t0 =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t0, t_rs); - tcg_gen_rotli_i32(t0, t0, sh); - tcg_gen_extu_i32_tl(t1, t0); - } else { -#if defined(TARGET_PPC64) - tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); - tcg_gen_rotli_i64(t1, t1, sh); -#else - g_assert_not_reached(); -#endif - } - - tcg_gen_andi_tl(t1, t1, mask); - tcg_gen_andi_tl(t_ra, t_ra, ~mask); - tcg_gen_or_tl(t_ra, t_ra, t1); - } - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, t_ra); - } -} - -/* rlwinm & rlwinm. */ -static void gen_rlwinm(DisasContext *ctx) -{ - TCGv t_ra =3D cpu_gpr[rA(ctx->opcode)]; - TCGv t_rs =3D cpu_gpr[rS(ctx->opcode)]; - int sh =3D SH(ctx->opcode); - int mb =3D MB(ctx->opcode); - int me =3D ME(ctx->opcode); - int len =3D me - mb + 1; - int rsh =3D (32 - sh) & 31; - - if (sh !=3D 0 && len > 0 && me =3D=3D (31 - sh)) { - tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); - } else if (me =3D=3D 31 && rsh + len <=3D 32) { - tcg_gen_extract_tl(t_ra, t_rs, rsh, len); - } else { - target_ulong mask; - bool mask_in_32b =3D true; -#if defined(TARGET_PPC64) - mb +=3D 32; - me +=3D 32; -#endif - mask =3D MASK(mb, me); -#if defined(TARGET_PPC64) - if (mask > 0xffffffffu) { - mask_in_32b =3D false; - } -#endif - if (mask_in_32b) { - if (sh =3D=3D 0) { - tcg_gen_andi_tl(t_ra, t_rs, mask); - } else { - TCGv_i32 t0 =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t0, t_rs); - tcg_gen_rotli_i32(t0, t0, sh); - tcg_gen_andi_i32(t0, t0, mask); - tcg_gen_extu_i32_tl(t_ra, t0); - } - } else { -#if defined(TARGET_PPC64) - tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); - tcg_gen_rotli_i64(t_ra, t_ra, sh); - tcg_gen_andi_i64(t_ra, t_ra, mask); -#else - g_assert_not_reached(); -#endif - } - } - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, t_ra); - } -} - /* rlwnm & rlwnm. */ static void gen_rlwnm(DisasContext *ctx) { @@ -4794,8 +4690,6 @@ GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PP= C_NONE), GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA30= 0), GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), -GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), /* handles lfdp, lxsd, lxssp */ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 4b79e24f6f..efef56a119 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1872,6 +1872,108 @@ static bool trans_SRAWI(DisasContext *ctx, arg_SRAW= I *a) return true; } =20 +static bool trans_RLWIMI(DisasContext *ctx, arg_RLWIMI *a) +{ + TCGv t_ra =3D cpu_gpr[a->ra]; + TCGv t_rs =3D cpu_gpr[a->rs]; + int mb =3D a->mb; + int me =3D a->me; + + if (a->sh =3D=3D (31 - me) && mb <=3D me) { + tcg_gen_deposit_tl(t_ra, t_ra, t_rs, a->sh, me - mb + 1); + } else { + target_ulong mask; + bool mask_in_32b =3D true; + TCGv t1; + +#if defined(TARGET_PPC64) + mb +=3D 32; + me +=3D 32; +#endif + mask =3D MASK(mb, me); + +#if defined(TARGET_PPC64) + if (mask > 0xffffffffu) { + mask_in_32b =3D false; + } +#endif + t1 =3D tcg_temp_new(); + if (mask_in_32b) { + TCGv_i32 t0 =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t0, t_rs); + tcg_gen_rotli_i32(t0, t0, a->sh); + tcg_gen_extu_i32_tl(t1, t0); + } else { +#if defined(TARGET_PPC64) + tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); + tcg_gen_rotli_i64(t1, t1, a->sh); +#else + g_assert_not_reached(); +#endif + } + + tcg_gen_andi_tl(t1, t1, mask); + tcg_gen_andi_tl(t_ra, t_ra, ~mask); + tcg_gen_or_tl(t_ra, t_ra, t1); + } + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, t_ra); + } + return true; +} + +static bool trans_RLWINM(DisasContext *ctx, arg_RLWINM *a) +{ + TCGv t_ra =3D cpu_gpr[a->ra]; + TCGv t_rs =3D cpu_gpr[a->rs]; + int me =3D a->me; + int mb =3D a->mb; + int len =3D me - mb + 1; + int rsh =3D (32 - a->sh) & 31; + + if (a->sh !=3D 0 && len > 0 && me =3D=3D (31 - a->sh)) { + tcg_gen_deposit_z_tl(t_ra, t_rs, a->sh, len); + } else if (me =3D=3D 31 && rsh + len <=3D 32) { + tcg_gen_extract_tl(t_ra, t_rs, rsh, len); + } else { + target_ulong mask; + bool mask_in_32b =3D true; +#if defined(TARGET_PPC64) + mb +=3D 32; + me +=3D 32; +#endif + mask =3D MASK(mb, me); +#if defined(TARGET_PPC64) + if (mask > 0xffffffffu) { + mask_in_32b =3D false; + } +#endif + if (mask_in_32b) { + if (a->sh =3D=3D 0) { + tcg_gen_andi_tl(t_ra, t_rs, mask); + } else { + TCGv_i32 t0 =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t0, t_rs); + tcg_gen_rotli_i32(t0, t0, a->sh); + tcg_gen_andi_i32(t0, t0, mask); + tcg_gen_extu_i32_tl(t_ra, t0); + } + } else { +#if defined(TARGET_PPC64) + tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=NDD1OvGTonqXoO4Dj +D+3OXUHZJ958y4Uq7qPsRJ878=; b=O73jiJ3GyZpbW2HmTZqkQJAzSP15ILDFU i2KzX5DjMLnuWJqVcyOIzcorjLS5sbf3HZgPcdjGadSnBLRiX8GZaQNGPNVViFE4 VabO19BVxMH4XTI0TSYv1lN8x4/wzOt03LsdkX10rhkiyxElJZ6/d+0VBsD+Gyn5 18t+eQjcbzTXCbyzaHEoa8A2XoCCYnerFBY3tqRqqJUqeQyyvTt4B82YfYkNOp7i Bb/YXBJfnnnWh+9Kze0ZMW+LbNQn4zw/opXV1s0BxKgYNRwrWtVorRTXbEHFD5B2 VR1pHgZdzEE+M9qbQkUfQBMbgGUjG+X/tTXouFl/F9JEzJiFv770w== From: Harsh Prateek Bora To: qemu-devel@nongnu.org Cc: Tanushree Shah , Glenn Miles , Amit Machhiwal , Chinmay Rath , Aniket Sahu Subject: [PULL 30/41] target/ppc: Move lmw, stmw instructions to decodetree Date: Fri, 28 Aug 2026 11:37:05 +0530 Message-ID: <20260828060716.91672-31-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com> References: <20260828060716.91672-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: wi0hAo6PrDxu5F8ElKKyYaMIj6_P9M5R X-Proofpoint-ORIG-GUID: wi0hAo6PrDxu5F8ElKKyYaMIj6_P9M5R X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX0OVvNYsfS0Gx xxSuMed6aQUqBLkBs7fK6eyd2Jlzk5wJq6hnv6ZCrzvnm5g+4cYLxhDPSNrGEj1XZ0aVXMmxjdg ryx/+SDP6rOzg24QGOIy3rZz27Ldulbt54en0j8kOPAuN/gAkFSInem6sXrzACcNabWSyraZV5d nRxOp0X9ymwd7bHpIW/6x070Wn6ZBP03mQsoySNArdMAqgDNNsP596AWH2PLSoWigrB9I7lcRZj 0DU8aZwk9ZO+3/FoupGHH11PrwIFlZrtPJPA8OOgL6thb1VAyKmoCf1s5bnF5qCoM3mdy1TPDD9 9ROEVpIrZbZ6mD5DY5H/3CEeXH5vqwGI5cLl/P3UiZdr/Ye0DUc42nalXKj4h/fJlSYLNUG/ndT dKdwnzMcNgNvE+H2ZcQ7yC1w4Mwu0luc5ZAWkxPyIen8M5VuuL0sYKnA/HdmAO0g9yJK6WuEqdm be1lvJ/UmfYhTRMgLlA== X-Authority-Analysis: v=2.4 cv=QsRuG1yd c=1 sm=1 tr=0 ts=6a9125f2 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=Sv0fKeRqtYgA:10 a=f7IdgyKtn90A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=EKBDPzd3v7EvMxvHOJ8A:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX+llc9R4idPLu rAbY5k40WUG9rryzOXKMcDVwH+m9J2hhN7f47faQa+yzTmO+SfnW2qOKlVM5HrA5M4sAmxACvYI QfJLvYm2TEZb5duIN622Z+wE6LjdIYI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_01,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280050 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897356678154100 Content-Type: text/plain; charset="utf-8" From: Tanushree Shah Moving the following instructions to decodetree specification: lmw : D-form stmw : D-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the "-d in_asm,op" flag. Additionally, validated using small assembly tests confirming the the correct register store/load behavior. Also, confirmed the register values are same before and after the change. Signed-off-by: Tanushree Shah Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-27-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/helper.h | 4 +-- target/ppc/insn32.decode | 3 ++ target/ppc/mem_helper.c | 4 +-- target/ppc/translate.c | 39 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 32 ++++++++++++++++++ 5 files changed, 39 insertions(+), 43 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 7da752c69b..ec3350fee8 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -43,8 +43,8 @@ DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) #endif =20 -DEF_HELPER_3(lmw, void, env, tl, i32) -DEF_HELPER_FLAGS_3(stmw, TCG_CALL_NO_WG, void, env, tl, i32) +DEF_HELPER_3(LMW, void, env, tl, i32) +DEF_HELPER_FLAGS_3(STMW, TCG_CALL_NO_WG, void, env, tl, i32) DEF_HELPER_4(LSW, void, env, tl, i32, i32) DEF_HELPER_5(LSWX, void, env, tl, i32, i32, i32) DEF_HELPER_FLAGS_4(STSW, TCG_CALL_NO_WG, void, env, tl, i32, i32) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 92ee278f63..ef128f63c1 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -354,6 +354,7 @@ LVDX 011111 ..... ..... ..... 0000010001 - = @X LSKU 111010 ..... ..... ............. 0 11 @DD LCXU 111010 ..... ..... ............. 1 11 @DD =20 +LMW 101110 ..... ..... ................ @D =20 ### Fixed-Point Atomic Load/Store Instructions =20 @@ -399,6 +400,8 @@ STBCIX 011111 ..... ..... ..... 1111010101 - = @X STHBRX 011111 ..... ..... ..... 1110010110 - @X STWBRX 011111 ..... ..... ..... 1010010110 - @X =20 +STMW 101111 ..... ..... ................ @D + ### Fixed-Point Compare Instructions =20 CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 10c648cf06..dc5eab8c76 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -73,7 +73,7 @@ static void *probe_contiguous(CPUPPCState *env, target_ul= ong addr, uint32_t nb, return NULL; } =20 -void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) +void helper_LMW(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr =3D GETPC(); int mmu_idx =3D ppc_env_mmu_index(env, false); @@ -98,7 +98,7 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, uint= 32_t reg) } } =20 -void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) +void helper_STMW(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr =3D GETPC(); int mmu_idx =3D ppc_env_mmu_index(env, false); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ce94f9e4e6..880915f3da 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2455,43 +2455,6 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); #endif /* TARGET_PPC64 */ =20 -/*** Integer load and store multiple = ***/ - -/* lmw */ -static void gen_lmw(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - t1 =3D tcg_constant_i32(rD(ctx->opcode)); - gen_addr_imm_index(ctx, t0, 0); - gen_helper_lmw(tcg_env, t0, t1); -} - -/* stmw */ -static void gen_stmw(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - t1 =3D tcg_constant_i32(rS(ctx->opcode)); - gen_addr_imm_index(ctx, t0, 0); - gen_helper_stmw(tcg_env, t0, t1); -} - - #if !defined(CONFIG_USER_ONLY) static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { @@ -4695,8 +4658,6 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_= INTEGER), GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), /* handles stfdp, stxsd, stxssp */ GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), -GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index efef56a119..8475205f14 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -288,6 +288,38 @@ static bool trans_STQCX(DisasContext *ctx, arg_STQCX *= a) return true; } =20 +/* Load/Store Multiple Word */ +static bool do_ldst_multiple(DisasContext *ctx, arg_D *a, bool store) +{ + TCGv ea; + TCGv_i32 reg; + + REQUIRE_INSNS_FLAGS(ctx, INTEGER); + + /* Little-endian mode is not supported for multiple word operations */ + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + + gen_set_access_type(ctx, ACCESS_INT); + + reg =3D tcg_constant_i32(a->rt); + ea =3D do_ea_calc(ctx, a->ra, tcg_constant_tl(a->si)); + + /* Call the appropriate helper function */ + if (store) { + gen_helper_STMW(tcg_env, ea, reg); + } else { + gen_helper_LMW(tcg_env, ea, reg); + } + + return true; +} + +TRANS(LMW, do_ldst_multiple, false) +TRANS(STMW, do_ldst_multiple, true) + /* * Fixed-Point Compare Instructions */ --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897498728154100 Content-Type: text/plain; charset="utf-8" From: Vishal Chourasia Moving the following instructions to decodetree specification: mfmsr : X-form mtmsr[d] : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the `-d in_asm,op` flag. This also includes improvements from review feedback: - Gate MFMSR/MTMSR on PPC_MISC via TRANS_FLAGS() - Use UINT32_MAX instead of 0xFFFFFFFF for clarity Signed-off-by: Vishal Chourasia Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-28-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 5 ++ target/ppc/translate.c | 97 ---------------------------- target/ppc/translate/misc-impl.c.inc | 64 ++++++++++++++++++ 3 files changed, 69 insertions(+), 97 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index ef128f63c1..1e263449a5 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -315,6 +315,11 @@ &M ra rs sh mb me rc:bool @M ...... rs:5 ra:5 sh:5 mb:5 me:5 rc:1 &M =20 +### MSR +MFMSR 011111 ..... ----- ----- 0001010011 - @X_t +MTMSR 011111 ..... ---- . ----- 0010010010 - @X_rs_l +MTMSRD 011111 ..... ---- . ----- 0010110010 - @X_rs_l + ### Fixed-Point Load Instructions =20 LBZ 100010 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 880915f3da..1d069c5250 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2843,13 +2843,6 @@ static void gen_mcrxrx(DisasContext *ctx) } #endif =20 -/* mfmsr */ -static void gen_mfmsr(DisasContext *ctx) -{ - CHK_SV(ctx); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); -} - /* mfspr */ static inline void gen_op_mfspr(DisasContext *ctx) { @@ -2923,93 +2916,6 @@ static void gen_mftb(DisasContext *ctx) gen_op_mfspr(ctx); } =20 -/* mtmsr */ -#if defined(TARGET_PPC64) -static void gen_mtmsrd(DisasContext *ctx) -{ - if (unlikely(!is_book3s_arch2x(ctx))) { - gen_invalid(ctx); - return; - } - - CHK_SV(ctx); - -#if !defined(CONFIG_USER_ONLY) - TCGv t0, t1; - target_ulong mask; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - - translator_io_start(&ctx->base); - - if (ctx->opcode & 0x00010000) { - /* L=3D1 form only updates EE and RI */ - mask =3D (1ULL << MSR_RI) | (1ULL << MSR_EE); - } else { - /* mtmsrd does not alter HV, S, ME, or LE */ - mask =3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | - (1ULL << MSR_HV)); - /* - * XXX: we need to update nip before the store if we enter - * power saving mode, we will exit the loop directly from - * ppc_store_msr - */ - gen_update_nip(ctx, ctx->base.pc_next); - } - - tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); - tcg_gen_andi_tl(t1, cpu_msr, ~mask); - tcg_gen_or_tl(t0, t0, t1); - - gen_helper_store_msr(tcg_env, t0); - - /* Must stop the translation as machine state (may have) changed */ - ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; -#endif /* !defined(CONFIG_USER_ONLY) */ -} -#endif /* defined(TARGET_PPC64) */ - -static void gen_mtmsr(DisasContext *ctx) -{ - CHK_SV(ctx); - -#if !defined(CONFIG_USER_ONLY) - TCGv t0, t1; - target_ulong mask =3D 0xFFFFFFFF; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - - translator_io_start(&ctx->base); - if (ctx->opcode & 0x00010000) { - /* L=3D1 form only updates EE and RI */ - mask &=3D (1ULL << MSR_RI) | (1ULL << MSR_EE); - } else { - if (likely(!(ctx->insns_flags2 & PPC2_PPE42))) { - /* mtmsr does not alter S, ME, or LE */ - mask &=3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR= _S)); - } - - /* - * XXX: we need to update nip before the store if we enter - * power saving mode, we will exit the loop directly from - * ppc_store_msr - */ - gen_update_nip(ctx, ctx->base.pc_next); - } - - tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); - tcg_gen_andi_tl(t1, cpu_msr, ~mask); - tcg_gen_or_tl(t0, t0, t1); - - gen_helper_store_msr(tcg_env, t0); - - /* Must stop the translation as machine state (may have) changed */ - ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; -#endif -} - /* mtspr */ static void gen_mtspr(DisasContext *ctx) { @@ -4674,15 +4580,12 @@ GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PP= C_64H), GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), -GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), #if defined(TARGET_PPC64) -GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), #endif -GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE20= 6), diff --git a/target/ppc/translate/misc-impl.c.inc b/target/ppc/translate/mi= sc-impl.c.inc index 890fbb209e..54712f9b73 100644 --- a/target/ppc/translate/misc-impl.c.inc +++ b/target/ppc/translate/misc-impl.c.inc @@ -161,3 +161,67 @@ static bool trans_MCRF(DisasContext *ctx, arg_MCRF *a) tcg_gen_mov_i32(cpu_crf[a->bf], cpu_crf[a->bfa]); return true; } + +static bool do_mfmsr(DisasContext *ctx, arg_X_t *a) +{ + REQUIRE_SV(ctx); + tcg_gen_mov_tl(cpu_gpr[a->rt], cpu_msr); + return true; +} +TRANS_FLAGS(MISC, MFMSR, do_mfmsr) + +static bool do_mtmsr(DisasContext *ctx, arg_X_rs_l *a, bool is_mtmsrd) +{ + REQUIRE_SV(ctx); +#if !defined(CONFIG_USER_ONLY) + TCGv t0, t1; + target_ulong mask; + + if (is_mtmsrd) { + if (unlikely(!is_book3s_arch2x(ctx))) { + gen_invalid(ctx); + return true; + } + mask =3D ~(target_ulong)0; + } else { + mask =3D UINT32_MAX; + } + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + translator_io_start(&ctx->base); + + if (a->l) { + /* L=3D1 form only updates EE and RI */ + mask &=3D (1ULL << MSR_RI) | (1ULL << MSR_EE); + } else { + if (is_mtmsrd) { + /* mtmsrd does not alter HV, S, ME, or LE */ + mask &=3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | + (1ULL << MSR_S) | (1ULL << MSR_HV)); + } else if (likely(!(ctx->insns_flags2 & PPC2_PPE42))) { + /* mtmsr does not alter S, ME, or LE */ + mask &=3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR= _S)); + } + /* + * XXX: we need to update nip before the store if we enter + * power saving mode, we will exit the loop directly from + * ppc_store_msr + */ + gen_update_nip(ctx, ctx->base.pc_next); + } + + tcg_gen_andi_tl(t0, cpu_gpr[a->rs], mask); + tcg_gen_andi_tl(t1, cpu_msr, ~mask); + tcg_gen_or_tl(t0, t0, t1); + + gen_helper_store_msr(tcg_env, t0); + + /* Must stop the translation as machine state (may have) changed */ + ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; +#endif /* !CONFIG_USER_ONLY */ + return true; +} + +TRANS_FLAGS(MISC, MTMSR, do_mtmsr, false) +TRANS64(MTMSRD, do_mtmsr, true) --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897377; cv=none; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897378884158500 Content-Type: text/plain; charset="utf-8" From: Vishal Chourasia Moving the following instructions to decodetree specification: brd, brw, brh : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the `-d in_asm,op` flag. This also includes improvements from review feedback: - Add TARGET_PPC64 guards with qemu_build_not_reached() for 32-bit builds Signed-off-by: Vishal Chourasia Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Reviewed-by: Amit Machhiwal Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-29-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/insn32.decode | 5 +++ target/ppc/translate.c | 35 ---------------- target/ppc/translate/fixedpoint-impl.c.inc | 48 ++++++++++++++++++++++ 3 files changed, 53 insertions(+), 35 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 1e263449a5..7bbe1f8838 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -320,6 +320,11 @@ MFMSR 011111 ..... ----- ----- 0001010011 - = @X_t MTMSR 011111 ..... ---- . ----- 0010010010 - @X_rs_l MTMSRD 011111 ..... ---- . ----- 0010110010 - @X_rs_l =20 +### Fixed-Point Byte-Reverse Instructions +BRW 011111 ..... ..... ----- 0010011011 - @X_sa +BRD 011111 ..... ..... ----- 0010111011 - @X_sa +BRH 011111 ..... ..... ----- 0011011011 - @X_sa + ### Fixed-Point Load Instructions =20 LBZ 100010 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 1d069c5250..20d3e7c1ab 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4519,42 +4519,7 @@ static void gen_dform3D(DisasContext *ctx) return gen_invalid(ctx); } =20 -#if defined(TARGET_PPC64) -/* brd */ -static void gen_brd(DisasContext *ctx) -{ - tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]= ); -} - -/* brw */ -static void gen_brw(DisasContext *ctx) -{ - tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]= ); - tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], = 32); - -} - -/* brh */ -static void gen_brh(DisasContext *ctx) -{ - TCGv_i64 mask =3D tcg_constant_i64(0x00ff00ff00ff00ffull); - TCGv_i64 t1 =3D tcg_temp_new_i64(); - TCGv_i64 t2 =3D tcg_temp_new_i64(); - - tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); - tcg_gen_and_i64(t2, t1, mask); - tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); - tcg_gen_shli_i64(t1, t1, 8); - tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); -} -#endif - static opcode_t opcodes[] =3D { -#if defined(TARGET_PPC64) -GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), -GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), -GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), -#endif GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA30= 0), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 8475205f14..0e1960a272 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -17,6 +17,54 @@ * License along with this library; if not, see . */ =20 +/* + * Byte-Reverse Instructions + */ +static bool trans_BRD(DisasContext *ctx, arg_BRD *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA310); +#if defined(TARGET_PPC64) + tcg_gen_bswap64_i64(cpu_gpr[a->ra], cpu_gpr[a->rs]); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_BRW(DisasContext *ctx, arg_BRW *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA310); +#if defined(TARGET_PPC64) + tcg_gen_bswap64_i64(cpu_gpr[a->ra], cpu_gpr[a->rs]); + tcg_gen_rotli_i64(cpu_gpr[a->ra], cpu_gpr[a->ra], 32); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_BRH(DisasContext *ctx, arg_BRH *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA310); +#if defined(TARGET_PPC64) + TCGv_i64 mask =3D tcg_constant_i64(0x00ff00ff00ff00ffull); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2 =3D tcg_temp_new_i64(); + + tcg_gen_shri_i64(t1, cpu_gpr[a->rs], 8); + tcg_gen_and_i64(t2, t1, mask); + tcg_gen_and_i64(t1, cpu_gpr[a->rs], mask); + tcg_gen_shli_i64(t1, t1, 8); + tcg_gen_or_i64(cpu_gpr[a->ra], t1, t2); +#else + qemu_build_not_reached(); +#endif + return true; +} + /* * Fixed-Point Load/Store Instructions */ --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897353; cv=none; d=zohomail.com; s=zohoarc; b=VfQcSkeiKzQPsvOGVHBlQD/n8Ny2sJAeygrYa/8IEdOmRv1sUjn6ka6n7+F7mNgGZpXi611BPL216pE+WZyde9wiwzdeFcbS44TzRT1S4cElc3WLMcNxeRS5g3rEjt6qRAZw/MW1mI6yfUbi33kJyn6kpQkv+Yrs2Sv3g6Ii5k8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787897353; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897354613158500 Content-Type: text/plain; charset="utf-8" From: Vishal Chourasia Moving the following instructions to decodetree specification: sc, scv : SC-form rfi, rfid, rfscv, hrfid : XL-form This builds upon the previous work that moved mfmsr and mtmsr[d] instructions to decodetree. The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the `-d in_asm,op` flag, and also by booting a pseries qemu guest. This also includes improvements from review feedback: - Rename helpers to uppercase (RFI/RFID/RFSCV/HRFID) to match ISA mnemonics - Add TRANS64_FLAGS() macro variants - Add REQUIRE_INSNS_FLAGS_NOT() check for flag exclusion - Specify lev field as uint8_t in SC instruction format - Remove redundant masking in SCV since lev is already 7-bit - Replace TARGET_PPC64 ifdefs with REQUIRE_64BIT() macro - Gate SC, SCV, RFI, RFID, RFSCV, and HRFID with appropriate flags - Consolidate CONFIG_USER_ONLY guards into single block Signed-off-by: Vishal Chourasia Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Reviewed-by: Amit Machhiwal Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-30-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/helper.h | 8 +- target/ppc/insn32.decode | 11 +++ target/ppc/tcg-excp_helper.c | 8 +- target/ppc/translate.c | 126 ++------------------------- target/ppc/translate/misc-impl.c.inc | 102 ++++++++++++++++++++++ 5 files changed, 128 insertions(+), 127 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index ec3350fee8..80d6616bab 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -11,7 +11,7 @@ DEF_HELPER_4(HASHCHKP, void, env, tl, tl, tl) #if !defined(CONFIG_USER_ONLY) DEF_HELPER_2(store_msr, void, env, tl) DEF_HELPER_1(ppc_maybe_interrupt, void, env) -DEF_HELPER_1(rfi, void, env) +DEF_HELPER_1(RFI, void, env) DEF_HELPER_1(40x_rfci, void, env) DEF_HELPER_1(rfci, void, env) DEF_HELPER_1(rfdi, void, env) @@ -19,9 +19,9 @@ DEF_HELPER_1(rfmci, void, env) #if defined(TARGET_PPC64) DEF_HELPER_2(scv, noreturn, env, i32) DEF_HELPER_2(PMINSN, void, env, i32) -DEF_HELPER_1(rfid, void, env) -DEF_HELPER_1(rfscv, void, env) -DEF_HELPER_1(hrfid, void, env) +DEF_HELPER_1(RFID, void, env) +DEF_HELPER_1(RFSCV, void, env) +DEF_HELPER_1(HRFID, void, env) DEF_HELPER_2(rfebb, void, env, tl) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 7bbe1f8838..6563dc4f64 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -199,6 +199,9 @@ &X_rs_l rs l:bool @X_rs_l ...... rs:5 .... l:1 ..... .......... . &X_rs_l =20 +&SC lev:uint8_t +@SC ...... ..... ..... .... lev:7 ... . . &SC + &X_uim5 xt uim:uint8_t @X_uim5 ...... ..... ..... uim:5 .......... . &X_uim5 xt= =3D%x_xt =20 @@ -320,6 +323,14 @@ MFMSR 011111 ..... ----- ----- 0001010011 - = @X_t MTMSR 011111 ..... ---- . ----- 0010010010 - @X_rs_l MTMSRD 011111 ..... ---- . ----- 0010110010 - @X_rs_l =20 +### System Call and Return from Interrupt +SC 010001 ----- ----- ---- ....... --- 1 - @SC +SCV 010001 ----- ----- ---- ....... --- 0 1 @SC +RFI 010011 ----- ----- ----- 0000110010 - +RFID 010011 ----- ----- ----- 0000010010 - +RFSCV 010011 ----- ----- ----- 0001010010 - +HRFID 010011 ----- ----- ----- 0100010010 - + ### Fixed-Point Byte-Reverse Instructions BRW 011111 ..... ..... ----- 0010011011 - @X_sa BRD 011111 ..... ..... ----- 0010111011 - @X_sa diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index c4ffa2dfbb..d06d3f8642 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -528,13 +528,13 @@ static void do_rfi(CPUPPCState *env, target_ulong nip= , target_ulong msr) check_tlb_flush(env, false); } =20 -void helper_rfi(CPUPPCState *env) +void helper_RFI(CPUPPCState *env) { do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); } =20 #ifdef TARGET_PPC64 -void helper_rfid(CPUPPCState *env) +void helper_RFID(CPUPPCState *env) { /* * The architecture defines a number of rules for which bits can @@ -545,12 +545,12 @@ void helper_rfid(CPUPPCState *env) do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); } =20 -void helper_rfscv(CPUPPCState *env) +void helper_RFSCV(CPUPPCState *env) { do_rfi(env, env->lr, env->ctr); } =20 -void helper_hrfid(CPUPPCState *env) +void helper_HRFID(CPUPPCState *env) { do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 20d3e7c1ab..f93af662f3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2679,110 +2679,6 @@ static inline void gen_setlr(DisasContext *ctx, tar= get_ulong nip) tcg_gen_movi_tl(cpu_lr, nip); } =20 -/*** System linkage = ***/ - -/* rfi (supervisor only) */ -static void gen_rfi(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - /* - * This instruction doesn't exist anymore on 64-bit server - * processors compliant with arch 2.x - */ - if (is_book3s_arch2x(ctx)) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - /* Restore CPU state */ - CHK_SV(ctx); - translator_io_start(&ctx->base); - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); - gen_helper_rfi(tcg_env); - ctx->base.is_jmp =3D DISAS_EXIT; -#endif -} - -#if defined(TARGET_PPC64) -static void gen_rfid(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - /* Restore CPU state */ - CHK_SV(ctx); - translator_io_start(&ctx->base); - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); - gen_helper_rfid(tcg_env); - ctx->base.is_jmp =3D DISAS_EXIT; -#endif -} - -#if !defined(CONFIG_USER_ONLY) -static void gen_rfscv(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - /* Restore CPU state */ - CHK_SV(ctx); - translator_io_start(&ctx->base); - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); - gen_helper_rfscv(tcg_env); - ctx->base.is_jmp =3D DISAS_EXIT; -#endif -} -#endif - -static void gen_hrfid(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - /* Restore CPU state */ - CHK_HV(ctx); - translator_io_start(&ctx->base); - gen_helper_hrfid(tcg_env); - ctx->base.is_jmp =3D DISAS_EXIT; -#endif -} -#endif - -/* sc */ -#if defined(CONFIG_USER_ONLY) -#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER -#else -#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL -#endif -static void gen_sc(DisasContext *ctx) -{ - uint32_t lev; - - /* - * LEV is a 7-bit field, but the top 6 bits are treated as a reserved - * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is - * for Ultravisor which TCG does not support, so just ignore the top 6. - */ - lev =3D (ctx->opcode >> 5) & 0x1; - gen_exception_err(ctx, POWERPC_SYSCALL, lev); -} - -#if defined(TARGET_PPC64) -#if !defined(CONFIG_USER_ONLY) -static void gen_scv(DisasContext *ctx) -{ - uint32_t lev =3D (ctx->opcode >> 5) & 0x7F; - - /* Set the PC back to the faulting instruction. */ - gen_update_nip(ctx, ctx->cia); - gen_helper_scv(tcg_env, tcg_constant_i32(lev)); - - ctx->base.is_jmp =3D DISAS_NORETURN; -} -#endif -#endif - /*** Trap = ***/ =20 /* Check for unconditional traps (always or never) */ @@ -4155,6 +4051,13 @@ static int64_t dw_compose_ea(DisasContext *ctx, int = x) #define TRANS64(NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { REQUIRE_64BIT(ctx); return FUNC(ctx, a, ##__VA_ARGS__); } +#define TRANS64_FLAGS(FLAGS, NAME, FUNC, ...) \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ + { \ + REQUIRE_64BIT(ctx); \ + REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ + return FUNC(ctx, a, ##__VA_ARGS__); \ + } #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ @@ -4529,21 +4432,6 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC= _INTEGER), GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), /* handles stfdp, stxsd, stxssp */ GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), -/* ISA v3.0 changed the extended opcode from 62 to 30 */ -GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), -#if defined(TARGET_PPC64) -GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), -#if !defined(CONFIG_USER_ONLY) -/* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ -GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), -#endif -GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), -#endif -/* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ -GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), -GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), diff --git a/target/ppc/translate/misc-impl.c.inc b/target/ppc/translate/mi= sc-impl.c.inc index 54712f9b73..8144dbb1a1 100644 --- a/target/ppc/translate/misc-impl.c.inc +++ b/target/ppc/translate/misc-impl.c.inc @@ -225,3 +225,105 @@ static bool do_mtmsr(DisasContext *ctx, arg_X_rs_l *a= , bool is_mtmsrd) =20 TRANS_FLAGS(MISC, MTMSR, do_mtmsr, false) TRANS64(MTMSRD, do_mtmsr, true) + +/* + * System Call and Return from Interrupt Instructions + */ + +static bool do_SC(DisasContext *ctx, arg_SC *a, uint32_t excp) +{ + uint32_t lev; + + /* + * LEV is a 7-bit field, but the top 6 bits are treated as a reserved + * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is + * for Ultravisor which TCG does not support, so just ignore the top 6. + */ + lev =3D a->lev & 0x1; + gen_exception_err(ctx, excp, lev); + return true; +} + +static bool do_SCV(DisasContext *ctx, arg_SC *a) +{ +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + /* Set the PC back to the faulting instruction. */ + gen_update_nip(ctx, ctx->cia); + gen_helper_scv(tcg_env, tcg_constant_i32(a->lev)); + + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +#else + gen_invalid(ctx); + return true; +#endif +} + +/* + * Common helper for return-from-interrupt instructions + */ +enum { + RFI_KIND_RFI =3D 0, + RFI_KIND_RFID =3D 1, + RFI_KIND_HRFID =3D 2, + RFI_KIND_RFSCV =3D 3, +}; + +static bool do_rfi(DisasContext *ctx, arg_RFID *a, int kind) +{ +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); + return true; +#else + void (*helper)(TCGv_ptr); + + switch (kind) { + case RFI_KIND_RFI: + if (is_book3s_arch2x(ctx)) { + gen_invalid(ctx); + return true; + } + REQUIRE_SV(ctx); + helper =3D gen_helper_RFI; + break; +#if defined(TARGET_PPC64) + case RFI_KIND_HRFID: + REQUIRE_HV(ctx); + helper =3D gen_helper_HRFID; + break; + case RFI_KIND_RFID: + REQUIRE_SV(ctx); + helper =3D gen_helper_RFID; + break; + case RFI_KIND_RFSCV: + REQUIRE_SV(ctx); + helper =3D gen_helper_RFSCV; + break; +#endif + default: + gen_invalid(ctx); + return true; + } + + translator_io_start(&ctx->base); + if (kind !=3D RFI_KIND_HRFID) { + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); + } + helper(tcg_env); + ctx->base.is_jmp =3D DISAS_EXIT; + return true; +#endif +} + +#if defined(CONFIG_USER_ONLY) +TRANS_FLAGS(FLOW, SC, do_SC, POWERPC_EXCP_SYSCALL_USER) +#else +TRANS_FLAGS(FLOW, SC, do_SC, POWERPC_EXCP_SYSCALL) +#endif + +TRANS64_FLAGS2(ISA300, SCV, do_SCV) + +TRANS_FLAGS(FLOW, RFI, do_rfi, RFI_KIND_RFI) +TRANS64(RFID, do_rfi, RFI_KIND_RFID) +TRANS64_FLAGS(64H, HRFID, do_rfi, RFI_KIND_HRFID) +TRANS64_FLAGS2(ISA300, RFSCV, do_rfi, RFI_KIND_RFSCV) --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897521108158500 Content-Type: text/plain; charset="utf-8" From: Chinmay Rath There are several flags for Power ISA 2.07 currently in use, namely : PPC2_VSX207, PPC2_BCTAR_ISA207, PPC2_LSQ_ISA207, etc, but most of them are used together without any individual use. Create a generic ISA 2.07 flag and switch usage of PPC2_VSX207 to it instead. Next commits would consolidate the remaining flags. Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-31-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/cpu.h | 6 ++-- target/ppc/cpu_init.h | 2 +- target/ppc/cpu_init.c | 2 +- target/ppc/translate/fp-impl.c.inc | 4 +-- target/ppc/translate/vsx-impl.c.inc | 56 ++++++++++++++--------------- target/ppc/translate/vsx-ops.c.inc | 24 ++++++------- 6 files changed, 47 insertions(+), 47 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index cbd5964b1a..91ef34cb21 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2565,8 +2565,8 @@ enum { PPC2_DBRX =3D 0x0000000000000010ULL, /* Book I 2.05 PowerPC specification = */ PPC2_ISA205 =3D 0x0000000000000020ULL, - /* VSX additions in ISA 2.07 = */ - PPC2_VSX207 =3D 0x0000000000000040ULL, + /* POWER ISA 2.07 = */ + PPC2_ISA207 =3D 0x0000000000000040ULL, /* ISA 2.06B bpermd = */ PPC2_PERM_ISA206 =3D 0x0000000000000080ULL, /* ISA 2.06B divide extended variants = */ @@ -2607,7 +2607,7 @@ enum { PPC2_PPE42XM =3D 0x0000000002000000ULL, =20 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX= | \ - PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ + PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index f8fd6ff5cd..1c41c0d349 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -15,7 +15,7 @@ #define PPC_INSNS_FLAGS_POWER11 PPC_INSNS_FLAGS_POWER10 =20 #define PPC_INSNS_FLAGS2_POWER_COMMON \ - (PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \ + (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | \ PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index e2533481d8..b913edd243 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6346,7 +6346,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *d= ata) PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD | PPC_CILDST; - pcc->insns_flags2 =3D PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | + pcc->insns_flags2 =3D PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-i= mpl.c.inc index 464fb1d90f..e0d9fa2e24 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -342,7 +342,7 @@ static bool trans_FCPSGN(DisasContext *ctx, arg_FCPSGN = *a) static bool trans_FMRGEW(DisasContext *ctx, arg_FMRGEW *a) { TCGv_i64 t0, t1, t2; - REQUIRE_INSNS_FLAGS2(ctx, VSX207); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); REQUIRE_FPU(ctx); t0 =3D tcg_temp_new_i64(); t1 =3D tcg_temp_new_i64(); @@ -358,7 +358,7 @@ static bool trans_FMRGEW(DisasContext *ctx, arg_FMRGEW = *a) static bool trans_FMRGOW(DisasContext *ctx, arg_FMRGOW *a) { TCGv_i64 t0, t1, t2; - REQUIRE_INSNS_FLAGS2(ctx, VSX207); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); REQUIRE_FPU(ctx); t0 =3D tcg_temp_new_i64(); t1 =3D tcg_temp_new_i64(); diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index 00ad57c628..78311dcba9 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -50,11 +50,11 @@ static bool do_lxs(DisasContext *ctx, arg_X *a, } =20 TRANS_FLAGS2(VSX, LXSDX, do_lxs, gen_qemu_ld64_i64); -TRANS_FLAGS2(VSX207, LXSIWAX, do_lxs, gen_qemu_ld32s_i64); +TRANS_FLAGS2(ISA207, LXSIWAX, do_lxs, gen_qemu_ld32s_i64); TRANS_FLAGS2(ISA300, LXSIBZX, do_lxs, gen_qemu_ld8u_i64); TRANS_FLAGS2(ISA300, LXSIHZX, do_lxs, gen_qemu_ld16u_i64); -TRANS_FLAGS2(VSX207, LXSIWZX, do_lxs, gen_qemu_ld32u_i64); -TRANS_FLAGS2(VSX207, LXSSPX, do_lxs, gen_qemu_ld32fs); +TRANS_FLAGS2(ISA207, LXSIWZX, do_lxs, gen_qemu_ld32u_i64); +TRANS_FLAGS2(ISA207, LXSSPX, do_lxs, gen_qemu_ld32fs); =20 static bool trans_LXVD2X(DisasContext *ctx, arg_LXVD2X *a) { @@ -304,8 +304,8 @@ static bool do_stxs(DisasContext *ctx, arg_X *a, TRANS_FLAGS2(VSX, STXSDX, do_stxs, gen_qemu_st64_i64); TRANS_FLAGS2(ISA300, STXSIBX, do_stxs, gen_qemu_st8_i64); TRANS_FLAGS2(ISA300, STXSIHX, do_stxs, gen_qemu_st16_i64); -TRANS_FLAGS2(VSX207, STXSIWX, do_stxs, gen_qemu_st32_i64); -TRANS_FLAGS2(VSX207, STXSSPX, do_stxs, gen_qemu_st32fs); +TRANS_FLAGS2(ISA207, STXSIWX, do_stxs, gen_qemu_st32_i64); +TRANS_FLAGS2(ISA207, STXSSPX, do_stxs, gen_qemu_st32fs); =20 static bool trans_STXVD2X(DisasContext *ctx, arg_STXVD2X *a) { @@ -988,7 +988,7 @@ GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) -GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207) +GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_ISA207) GEN_VSX_HELPER_R2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300) GEN_VSX_HELPER_R2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300) GEN_VSX_HELPER_R2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300) @@ -1185,7 +1185,7 @@ bool trans_XSCVSPDPN(DisasContext *ctx, arg_XX2 *a) { TCGv_i64 tmp; =20 - REQUIRE_INSNS_FLAGS2(ctx, VSX207); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); REQUIRE_VSX(ctx); =20 tmp =3D tcg_temp_new_i64(); @@ -1210,16 +1210,16 @@ GEN_VSX_HELPER_X2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207) +GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_ISA207) GEN_VSX_HELPER_R2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300) GEN_VSX_HELPER_R2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300) GEN_VSX_HELPER_R2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300) GEN_VSX_HELPER_R3(xssubqp, 0x04, 0x10, 0, PPC2_ISA300) -GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) +GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_ISA207) +GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_ISA207) +GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_ISA207) +GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_ISA207) +GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_ISA207) =20 GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) @@ -1409,14 +1409,14 @@ TRANS_FLAGS2(VSX, XSNMADDADP, do_xsmadd_XX3, true, = gen_helper_XSNMADDDP) TRANS_FLAGS2(VSX, XSNMADDMDP, do_xsmadd_XX3, false, gen_helper_XSNMADDDP) TRANS_FLAGS2(VSX, XSNMSUBADP, do_xsmadd_XX3, true, gen_helper_XSNMSUBDP) TRANS_FLAGS2(VSX, XSNMSUBMDP, do_xsmadd_XX3, false, gen_helper_XSNMSUBDP) -TRANS_FLAGS2(VSX207, XSMADDASP, do_xsmadd_XX3, true, gen_helper_XSMADDSP) -TRANS_FLAGS2(VSX207, XSMADDMSP, do_xsmadd_XX3, false, gen_helper_XSMADDSP) -TRANS_FLAGS2(VSX207, XSMSUBASP, do_xsmadd_XX3, true, gen_helper_XSMSUBSP) -TRANS_FLAGS2(VSX207, XSMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSMSUBSP) -TRANS_FLAGS2(VSX207, XSNMADDASP, do_xsmadd_XX3, true, gen_helper_XSNMADDSP) -TRANS_FLAGS2(VSX207, XSNMADDMSP, do_xsmadd_XX3, false, gen_helper_XSNMADDS= P) -TRANS_FLAGS2(VSX207, XSNMSUBASP, do_xsmadd_XX3, true, gen_helper_XSNMSUBSP) -TRANS_FLAGS2(VSX207, XSNMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSNMSUBS= P) +TRANS_FLAGS2(ISA207, XSMADDASP, do_xsmadd_XX3, true, gen_helper_XSMADDSP) +TRANS_FLAGS2(ISA207, XSMADDMSP, do_xsmadd_XX3, false, gen_helper_XSMADDSP) +TRANS_FLAGS2(ISA207, XSMSUBASP, do_xsmadd_XX3, true, gen_helper_XSMSUBSP) +TRANS_FLAGS2(ISA207, XSMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSMSUBSP) +TRANS_FLAGS2(ISA207, XSNMADDASP, do_xsmadd_XX3, true, gen_helper_XSNMADDSP) +TRANS_FLAGS2(ISA207, XSNMADDMSP, do_xsmadd_XX3, false, gen_helper_XSNMADDS= P) +TRANS_FLAGS2(ISA207, XSNMSUBASP, do_xsmadd_XX3, true, gen_helper_XSNMSUBSP) +TRANS_FLAGS2(ISA207, XSNMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSNMSUBS= P) =20 static bool do_xsmadd_X(DisasContext *ctx, arg_X_rc *a, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_pt= r), @@ -1590,9 +1590,9 @@ TRANS_FLAGS2(VSX, XXLANDC, do_logical_op, MO_64, tcg_= gen_gvec_andc); TRANS_FLAGS2(VSX, XXLOR, do_logical_op, MO_64, tcg_gen_gvec_or); TRANS_FLAGS2(VSX, XXLXOR, do_logical_op, MO_64, tcg_gen_gvec_xor); TRANS_FLAGS2(VSX, XXLNOR, do_logical_op, MO_64, tcg_gen_gvec_nor); -TRANS_FLAGS2(VSX207, XXLEQV, do_logical_op, MO_64, tcg_gen_gvec_eqv); -TRANS_FLAGS2(VSX207, XXLNAND, do_logical_op, MO_64, tcg_gen_gvec_nand); -TRANS_FLAGS2(VSX207, XXLORC, do_logical_op, MO_64, tcg_gen_gvec_orc); +TRANS_FLAGS2(ISA207, XXLEQV, do_logical_op, MO_64, tcg_gen_gvec_eqv); +TRANS_FLAGS2(ISA207, XXLNAND, do_logical_op, MO_64, tcg_gen_gvec_nand); +TRANS_FLAGS2(ISA207, XXLORC, do_logical_op, MO_64, tcg_gen_gvec_orc); =20 #define VSX_XXMRG(name, high) \ static void glue(gen_, name)(DisasContext *ctx) \ @@ -2682,10 +2682,10 @@ TRANS_FLAGS2(ISA300, XSMINCDP, do_helper_XX3, gen_h= elper_XSMINCDP) TRANS_FLAGS2(ISA300, XSMAXJDP, do_helper_XX3, gen_helper_XSMAXJDP) TRANS_FLAGS2(ISA300, XSMINJDP, do_helper_XX3, gen_helper_XSMINJDP) =20 -TRANS_FLAGS2(VSX207, XSADDSP, do_helper_XX3, gen_helper_XSADDSP) -TRANS_FLAGS2(VSX207, XSSUBSP, do_helper_XX3, gen_helper_XSSUBSP) -TRANS_FLAGS2(VSX207, XSMULSP, do_helper_XX3, gen_helper_XSMULSP) -TRANS_FLAGS2(VSX207, XSDIVSP, do_helper_XX3, gen_helper_XSDIVSP) +TRANS_FLAGS2(ISA207, XSADDSP, do_helper_XX3, gen_helper_XSADDSP) +TRANS_FLAGS2(ISA207, XSSUBSP, do_helper_XX3, gen_helper_XSSUBSP) +TRANS_FLAGS2(ISA207, XSMULSP, do_helper_XX3, gen_helper_XSMULSP) +TRANS_FLAGS2(ISA207, XSDIVSP, do_helper_XX3, gen_helper_XSDIVSP) =20 TRANS_FLAGS2(VSX, XSADDDP, do_helper_XX3, gen_helper_XSADDDP) TRANS_FLAGS2(VSX, XSSUBDP, do_helper_XX3, gen_helper_XSSUBDP) diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-= ops.c.inc index e553b5b8fa..ae3df2c13d 100644 --- a/target/ppc/translate/vsx-ops.c.inc +++ b/target/ppc/translate/vsx-ops.c.inc @@ -1,9 +1,9 @@ -GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207= ), -GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207= ), -GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207= ), +GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_ISA207= ), +GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_ISA207= ), +GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_ISA207= ), #if defined(TARGET_PPC64) -GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207), -GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_ISA207), +GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_ISA207), GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300= ), GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300= ), @@ -127,7 +127,7 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001), GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001), GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300), GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX), -GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207), +GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_ISA207), GEN_XX2FORM_EO(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300), GEN_VSX_XFORM_300_EO(xscvsdqp, 0x04, 0x1A, 0x0A, 0x00000001), GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX), @@ -145,12 +145,12 @@ GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX), GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX), =20 GEN_VSX_XFORM_300(xsdivqp, 0x04, 0x11, 0x0), -GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207), -GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207), -GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207), -GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207), -GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207), -GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207), +GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_ISA207), +GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_ISA207), +GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_ISA207), +GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_ISA207), +GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_ISA207), +GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_ISA207), =20 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX), GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX), --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897392709158500 Content-Type: text/plain; charset="utf-8" From: Chinmay Rath PPC2_BCTAR_ISA207 is only ever set in the CPUPPCState's insns_flags2 alongside PPC2_ISA207. Checks made by PPC2_BCTAR_ISA207 could be replaced with PPC2_ISA207, hence rendering it useless and apt for removal. This patch does the same. Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-32-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/cpu.h | 4 +--- target/ppc/cpu_init.h | 2 +- linux-user/ppc/elfload.c | 7 +++---- target/ppc/cpu_init.c | 2 +- target/ppc/translate/branch-impl.c.inc | 2 +- 5 files changed, 7 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 91ef34cb21..df1e943d8d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2577,8 +2577,6 @@ enum { PPC2_FP_CVT_ISA206 =3D 0x0000000000000400ULL, /* ISA 2.06B floating point test instructions = */ PPC2_FP_TST_ISA206 =3D 0x0000000000000800ULL, - /* ISA 2.07 bctar instruction = */ - PPC2_BCTAR_ISA207 =3D 0x0000000000001000ULL, /* ISA 2.07 load/store quadword = */ PPC2_LSQ_ISA207 =3D 0x0000000000002000ULL, /* ISA 2.07 Altivec = */ @@ -2610,7 +2608,7 @@ enum { PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ + PPC2_LSQ_ISA207 | \ PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \ diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index 1c41c0d349..7dd587908e 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -17,7 +17,7 @@ #define PPC_INSNS_FLAGS2_POWER_COMMON \ (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ - PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | \ + PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \ PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206) diff --git a/linux-user/ppc/elfload.c b/linux-user/ppc/elfload.c index 0d54da9803..5c6065e08a 100644 --- a/linux-user/ppc/elfload.c +++ b/linux-user/ppc/elfload.c @@ -116,10 +116,9 @@ abi_ulong get_elf_hwcap2(CPUState *cs) do { if (cpu->env.insns_flags2 & flag) { features |=3D feature; } } wh= ile (0) =20 GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL); - GET_FEATURE2(PPC2_BCTAR_ISA207, QEMU_PPC_FEATURE2_HAS_TAR); - GET_FEATURE2((PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA207S), QEMU_PPC_FEATURE2_ARCH_2_07 | - QEMU_PPC_FEATURE2_VEC_CRYPTO); + GET_FEATURE2((PPC2_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 | + QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR= )); GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 | QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128); GET_FEATURE2(PPC2_ISA310, QEMU_PPC_FEATURE2_ARCH_3_1 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index b913edd243..c250f805a7 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6349,7 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *d= ata) pcc->insns_flags2 =3D PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | + PPC2_FP_TST_ISA206 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc index c51fd9b13e..e5b64ca84e 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -210,4 +210,4 @@ static bool bclr_helper(DisasContext *ctx, arg_bclr *a,= int type) =20 TRANS(BCLR, bclr_helper, BCOND_LR) TRANS(BCCTR, bclr_helper, BCOND_CTR) -TRANS_FLAGS2(BCTAR_ISA207, BCTAR, bclr_helper, BCOND_TAR) +TRANS_FLAGS2(ISA207, BCTAR, bclr_helper, BCOND_TAR) --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897468245154100 Content-Type: text/plain; charset="utf-8" From: Chinmay Rath PPC2_LSQ_ISA207 is only ever set in the CPUPPCState's insns_flags2 alongside PPC2_ISA207. Checks made by PPC2_LSQ_ISA207 could be replaced with PPC2_ISA207, hence rendering it useless and apt for removal. This patch does the same. Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-33-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/cpu.h | 3 --- target/ppc/cpu_init.h | 2 +- linux-user/ppc/elfload.c | 2 +- target/ppc/cpu_init.c | 3 +-- target/ppc/translate/fixedpoint-impl.c.inc | 4 ++-- 5 files changed, 5 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index df1e943d8d..b3cd8d85df 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2577,8 +2577,6 @@ enum { PPC2_FP_CVT_ISA206 =3D 0x0000000000000400ULL, /* ISA 2.06B floating point test instructions = */ PPC2_FP_TST_ISA206 =3D 0x0000000000000800ULL, - /* ISA 2.07 load/store quadword = */ - PPC2_LSQ_ISA207 =3D 0x0000000000002000ULL, /* ISA 2.07 Altivec = */ PPC2_ALTIVEC_207 =3D 0x0000000000004000ULL, /* PowerISA 2.07 Book3s specification = */ @@ -2608,7 +2606,6 @@ enum { PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_LSQ_ISA207 | \ PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \ diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index 7dd587908e..6961007926 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -18,7 +18,7 @@ (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \ + PPC2_ALTIVEC_207 | PPC2_ISA205 | \ PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206) =20 diff --git a/linux-user/ppc/elfload.c b/linux-user/ppc/elfload.c index 5c6065e08a..76ab9f43de 100644 --- a/linux-user/ppc/elfload.c +++ b/linux-user/ppc/elfload.c @@ -116,7 +116,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) do { if (cpu->env.insns_flags2 & flag) { features |=3D feature; } } wh= ile (0) =20 GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL); - GET_FEATURE2((PPC2_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + GET_FEATURE2((PPC2_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 | QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR= )); GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c250f805a7..4cc8b93dca 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6349,8 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *d= ata) pcc->insns_flags2 =3D PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_FP_TST_ISA206 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 0e1960a272..c3d8bbf267 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -124,7 +124,7 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, b= ool store, bool prefixed) =20 REQUIRE_INSNS_FLAGS(ctx, 64BX); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897577966154100 Content-Type: text/plain; charset="utf-8" From: Chinmay Rath PPC2_ALTIVEC_207 is only ever set in the CPUPPCState's insns_flags2 alongside PPC2_ISA207. Checks made by PPC2_ALTIVEC_207 could be replaced with PPC2_ISA207, hence rendering it useless and apt for removal. This patch does the same. Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-34-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/cpu.h | 4 +- target/ppc/cpu_init.h | 3 +- linux-user/ppc/elfload.c | 3 +- target/ppc/cpu_init.c | 2 +- target/ppc/translate/vmx-impl.c.inc | 102 ++++++++++++++-------------- target/ppc/translate/vmx-ops.c.inc | 18 ++--- 6 files changed, 64 insertions(+), 68 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b3cd8d85df..00676cea2b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2577,8 +2577,6 @@ enum { PPC2_FP_CVT_ISA206 =3D 0x0000000000000400ULL, /* ISA 2.06B floating point test instructions = */ PPC2_FP_TST_ISA206 =3D 0x0000000000000800ULL, - /* ISA 2.07 Altivec = */ - PPC2_ALTIVEC_207 =3D 0x0000000000004000ULL, /* PowerISA 2.07 Book3s specification = */ PPC2_ISA207S =3D 0x0000000000008000ULL, /* Double precision floating point conversion for signed integer 64 = */ @@ -2606,7 +2604,7 @@ enum { PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ + PPC2_ISA207S | PPC2_DFP | \ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \ PPC2_BCDA_ISA206 | PPC2_PPE42 | PPC2_PPE42X | \ diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index 6961007926..73f014c82a 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -17,8 +17,7 @@ #define PPC_INSNS_FLAGS2_POWER_COMMON \ (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ - PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_ALTIVEC_207 | PPC2_ISA205 | \ + PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_ISA205 | \ PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206) =20 diff --git a/linux-user/ppc/elfload.c b/linux-user/ppc/elfload.c index 76ab9f43de..8c40f1a663 100644 --- a/linux-user/ppc/elfload.c +++ b/linux-user/ppc/elfload.c @@ -116,8 +116,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) do { if (cpu->env.insns_flags2 & flag) { features |=3D feature; } } wh= ile (0) =20 GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL); - GET_FEATURE2((PPC2_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 | + GET_FEATURE2((PPC2_ISA207 | PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_0= 7 | QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR= )); GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 | QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 4cc8b93dca..c251426b2e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6349,7 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *d= ata) pcc->insns_flags2 =3D PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_ALTIVEC_207 | + PPC2_FP_TST_ISA206 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 4e7fe22156..486f5c2151 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -351,14 +351,14 @@ static bool do_vx_vaddsubm(DisasContext *ctx, arg_VX = *a, MemOp vece, TRANS_FLAGS(ALTIVEC, VADDUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_add) TRANS_FLAGS(ALTIVEC, VADDUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_add) TRANS_FLAGS(ALTIVEC, VADDUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_add) -TRANS_FLAGS2(ALTIVEC_207, VADDUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_add) +TRANS_FLAGS2(ISA207, VADDUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_add) =20 TRANS_FLAGS(ALTIVEC, VSUBUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_sub) TRANS_FLAGS(ALTIVEC, VSUBUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_sub) TRANS_FLAGS(ALTIVEC, VSUBUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_sub) -TRANS_FLAGS2(ALTIVEC_207, VSUBUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_sub) +TRANS_FLAGS2(ISA207, VSUBUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_sub) =20 -TRANS_FLAGS2(ALTIVEC_207, VMULUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_mul) +TRANS_FLAGS2(ISA207, VMULUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_mul) =20 TRANS_FLAGS2(ISA300, VMUL10CUQ, do_vx_vmul10, false, true) TRANS_FLAGS2(ISA300, VMUL10ECUQ, do_vx_vmul10, true, true) @@ -699,22 +699,22 @@ static bool do_vector_gvec3_VX(DisasContext *ctx, arg= _VX *a, int vece, TRANS_FLAGS(ALTIVEC, VSLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shlv); TRANS_FLAGS(ALTIVEC, VSLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shlv); TRANS_FLAGS(ALTIVEC, VSLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shlv); -TRANS_FLAGS2(ALTIVEC_207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sh= lv); +TRANS_FLAGS2(ISA207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shlv); =20 TRANS_FLAGS(ALTIVEC, VSRB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shrv); TRANS_FLAGS(ALTIVEC, VSRH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shrv); TRANS_FLAGS(ALTIVEC, VSRW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shrv); -TRANS_FLAGS2(ALTIVEC_207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sh= rv); +TRANS_FLAGS2(ISA207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shrv); =20 TRANS_FLAGS(ALTIVEC, VSRAB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_sarv); TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv); TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv); -TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_s= arv); +TRANS_FLAGS2(ISA207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv); =20 TRANS_FLAGS(ALTIVEC, VRLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_rotlv) TRANS_FLAGS(ALTIVEC, VRLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_rotlv) TRANS_FLAGS(ALTIVEC, VRLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_rotlv) -TRANS_FLAGS2(ALTIVEC_207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_ro= tlv) +TRANS_FLAGS2(ISA207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_rotlv) =20 /* Logical operations */ TRANS_FLAGS(ALTIVEC, VAND, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_and); @@ -722,30 +722,30 @@ TRANS_FLAGS(ALTIVEC, VANDC, do_vector_gvec3_VX, MO_64= , tcg_gen_gvec_andc); TRANS_FLAGS(ALTIVEC, VOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_or); TRANS_FLAGS(ALTIVEC, VXOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_xor); TRANS_FLAGS(ALTIVEC, VNOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_nor); -TRANS_FLAGS2(ALTIVEC_207, VEQV, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_eq= v); -TRANS_FLAGS2(ALTIVEC_207, VNAND, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_n= and); -TRANS_FLAGS2(ALTIVEC_207, VORC, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_or= c); +TRANS_FLAGS2(ISA207, VEQV, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_eqv); +TRANS_FLAGS2(ISA207, VNAND, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_nand); +TRANS_FLAGS2(ISA207, VORC, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_orc); =20 /* Integer Max/Min operations */ TRANS_FLAGS(ALTIVEC, VMAXUB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_umax); TRANS_FLAGS(ALTIVEC, VMAXUH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_umax); TRANS_FLAGS(ALTIVEC, VMAXUW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_umax); -TRANS_FLAGS2(ALTIVEC_207, VMAXUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_= umax); +TRANS_FLAGS2(ISA207, VMAXUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_umax); =20 TRANS_FLAGS(ALTIVEC, VMAXSB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_smax); TRANS_FLAGS(ALTIVEC, VMAXSH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_smax); TRANS_FLAGS(ALTIVEC, VMAXSW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_smax); -TRANS_FLAGS2(ALTIVEC_207, VMAXSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_= smax); +TRANS_FLAGS2(ISA207, VMAXSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_smax); =20 TRANS_FLAGS(ALTIVEC, VMINUB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_umin); TRANS_FLAGS(ALTIVEC, VMINUH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_umin); TRANS_FLAGS(ALTIVEC, VMINUW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_umin); -TRANS_FLAGS2(ALTIVEC_207, VMINUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_= umin); +TRANS_FLAGS2(ISA207, VMINUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_umin); =20 TRANS_FLAGS(ALTIVEC, VMINSB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_smin); TRANS_FLAGS(ALTIVEC, VMINSH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_smin); TRANS_FLAGS(ALTIVEC, VMINSW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_smin); -TRANS_FLAGS2(ALTIVEC_207, VMINSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_= smin); +TRANS_FLAGS2(ISA207, VMINSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_smin); =20 static TCGv_vec do_vrl_mask_vec(unsigned vece, TCGv_vec vrb) { @@ -1091,16 +1091,16 @@ static bool do_vpk(DisasContext *ctx, arg_VX *a, =20 TRANS_FLAGS(ALTIVEC, VPKUHUM, do_vpk_env, gen_helper_VPKUHUM) TRANS_FLAGS(ALTIVEC, VPKUWUM, do_vpk_env, gen_helper_VPKUWUM) -TRANS_FLAGS2(ALTIVEC_207, VPKUDUM, do_vpk_env, gen_helper_VPKUDUM) +TRANS_FLAGS2(ISA207, VPKUDUM, do_vpk_env, gen_helper_VPKUDUM) TRANS_FLAGS(ALTIVEC, VPKUHUS, do_vpk_env, gen_helper_VPKUHUS) TRANS_FLAGS(ALTIVEC, VPKUWUS, do_vpk_env, gen_helper_VPKUWUS) -TRANS_FLAGS2(ALTIVEC_207, VPKUDUS, do_vpk_env, gen_helper_VPKUDUS) +TRANS_FLAGS2(ISA207, VPKUDUS, do_vpk_env, gen_helper_VPKUDUS) TRANS_FLAGS(ALTIVEC, VPKSHUS, do_vpk_env, gen_helper_VPKSHUS) TRANS_FLAGS(ALTIVEC, VPKSWUS, do_vpk_env, gen_helper_VPKSWUS) -TRANS_FLAGS2(ALTIVEC_207, VPKSDUS, do_vpk_env, gen_helper_VPKSDUS) +TRANS_FLAGS2(ISA207, VPKSDUS, do_vpk_env, gen_helper_VPKSDUS) TRANS_FLAGS(ALTIVEC, VPKSHSS, do_vpk_env, gen_helper_VPKSHSS) TRANS_FLAGS(ALTIVEC, VPKSWSS, do_vpk_env, gen_helper_VPKSWSS) -TRANS_FLAGS2(ALTIVEC_207, VPKSDSS, do_vpk_env, gen_helper_VPKSDSS) +TRANS_FLAGS2(ISA207, VPKSDSS, do_vpk_env, gen_helper_VPKSDSS) TRANS_FLAGS(ALTIVEC, VPKPX, do_vpk, gen_helper_VPKPX) GEN_VXFORM_ENV(vsum4ubs, 4, 24); GEN_VXFORM_ENV(vsum4sbs, 4, 28); @@ -1114,12 +1114,12 @@ GEN_VXFORM_ENV(vminfp, 5, 17); GEN_VXFORM_HETRO(vextublx, 6, 24) GEN_VXFORM_HETRO(vextuhlx, 6, 25) GEN_VXFORM_HETRO(vextuwlx, 6, 26) -GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207, +GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ISA207, vextuwlx, PPC_NONE, PPC2_ISA300) GEN_VXFORM_HETRO(vextubrx, 6, 28) GEN_VXFORM_HETRO(vextuhrx, 6, 29) GEN_VXFORM_HETRO(vextuwrx, 6, 30) -GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, +GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ISA207, vextuwrx, PPC_NONE, PPC2_ISA300) =20 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ @@ -1209,16 +1209,16 @@ static bool do_vcmp(DisasContext *ctx, arg_VC *a, T= CGCond cond, int vece) TRANS_FLAGS(ALTIVEC, VCMPEQUB, do_vcmp, TCG_COND_EQ, MO_8) TRANS_FLAGS(ALTIVEC, VCMPEQUH, do_vcmp, TCG_COND_EQ, MO_16) TRANS_FLAGS(ALTIVEC, VCMPEQUW, do_vcmp, TCG_COND_EQ, MO_32) -TRANS_FLAGS2(ALTIVEC_207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64) +TRANS_FLAGS2(ISA207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64) =20 TRANS_FLAGS(ALTIVEC, VCMPGTSB, do_vcmp, TCG_COND_GT, MO_8) TRANS_FLAGS(ALTIVEC, VCMPGTSH, do_vcmp, TCG_COND_GT, MO_16) TRANS_FLAGS(ALTIVEC, VCMPGTSW, do_vcmp, TCG_COND_GT, MO_32) -TRANS_FLAGS2(ALTIVEC_207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64) +TRANS_FLAGS2(ISA207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64) TRANS_FLAGS(ALTIVEC, VCMPGTUB, do_vcmp, TCG_COND_GTU, MO_8) TRANS_FLAGS(ALTIVEC, VCMPGTUH, do_vcmp, TCG_COND_GTU, MO_16) TRANS_FLAGS(ALTIVEC, VCMPGTUW, do_vcmp, TCG_COND_GTU, MO_32) -TRANS_FLAGS2(ALTIVEC_207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64) +TRANS_FLAGS2(ISA207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64) =20 TRANS_FLAGS2(ISA300, VCMPNEB, do_vcmp, TCG_COND_NE, MO_8) TRANS_FLAGS2(ISA300, VCMPNEH, do_vcmp, TCG_COND_NE, MO_16) @@ -2330,11 +2330,11 @@ static bool do_va_helper(DisasContext *ctx, arg_VA = *a, return true; } =20 -TRANS_FLAGS2(ALTIVEC_207, VADDECUQ, do_va_helper, gen_helper_VADDECUQ) -TRANS_FLAGS2(ALTIVEC_207, VADDEUQM, do_va_helper, gen_helper_VADDEUQM) +TRANS_FLAGS2(ISA207, VADDECUQ, do_va_helper, gen_helper_VADDECUQ) +TRANS_FLAGS2(ISA207, VADDEUQM, do_va_helper, gen_helper_VADDEUQM) =20 -TRANS_FLAGS2(ALTIVEC_207, VSUBEUQM, do_va_helper, gen_helper_VSUBEUQM) -TRANS_FLAGS2(ALTIVEC_207, VSUBECUQ, do_va_helper, gen_helper_VSUBECUQ) +TRANS_FLAGS2(ISA207, VSUBEUQM, do_va_helper, gen_helper_VSUBEUQM) +TRANS_FLAGS2(ISA207, VSUBECUQ, do_va_helper, gen_helper_VSUBECUQ) =20 TRANS_FLAGS(ALTIVEC, VPERM, do_va_helper, gen_helper_VPERM) TRANS_FLAGS2(ISA300, VPERMR, do_va_helper, gen_helper_VPERMR) @@ -2502,14 +2502,14 @@ GEN_VXFORM_NOA(vpopcntb, 1, 28) GEN_VXFORM_NOA(vpopcnth, 1, 29) GEN_VXFORM_NOA(vpopcntw, 1, 30) GEN_VXFORM_NOA(vpopcntd, 1, 31) -GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \ - vpopcntb, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \ - vpopcnth, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \ - vpopcntw, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \ - vpopcntd, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ISA207, \ + vpopcntb, PPC_NONE, PPC2_ISA207) +GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ISA207, \ + vpopcnth, PPC_NONE, PPC2_ISA207) +GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ISA207, \ + vpopcntw, PPC_NONE, PPC2_ISA207) +GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ISA207, \ + vpopcntd, PPC_NONE, PPC2_ISA207) GEN_VXFORM(vbpermd, 6, 23); GEN_VXFORM(vbpermq, 6, 21); GEN_VXFORM_TRANS(vgbbd, 6, 20); @@ -2589,8 +2589,8 @@ static bool do_bcd_tb_ps(DisasContext *ctx, arg_VX_tb= _ps *a, return true; } =20 -TRANS_FLAGS2(ALTIVEC_207, BCDADD, do_bcd_ps, gen_helper_BCDADD) -TRANS_FLAGS2(ALTIVEC_207, BCDSUB, do_bcd_ps, gen_helper_BCDSUB) +TRANS_FLAGS2(ISA207, BCDADD, do_bcd_ps, gen_helper_BCDADD) +TRANS_FLAGS2(ISA207, BCDSUB, do_bcd_ps, gen_helper_BCDSUB) TRANS_FLAGS2(ISA300, BCDUS, do_bcd, gen_helper_BCDUS) TRANS_FLAGS2(ISA300, BCDS, do_bcd_ps, gen_helper_BCDS) TRANS_FLAGS2(ISA300, BCDCFN, do_bcd_tb_ps, gen_helper_BCDCFN) @@ -2622,10 +2622,10 @@ GEN_VXFORM(vcipherlast, 4, 20) GEN_VXFORM(vncipher, 4, 21) GEN_VXFORM(vncipherlast, 4, 21) =20 -GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207, - vcipherlast, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207, - vncipherlast, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ISA207, + vcipherlast, PPC_NONE, PPC2_ISA207) +GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ISA207, + vncipherlast, PPC_NONE, PPC2_ISA207) =20 #define VSHASIGMA(op) \ static void gen_##op(DisasContext *ctx) \ @@ -2647,7 +2647,7 @@ VSHASIGMA(vshasigmad) =20 GEN_VXFORM3(vpermxor, 22, 0xFF) GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, - vpermxor, PPC_NONE, PPC2_ALTIVEC_207) + vpermxor, PPC_NONE, PPC2_ISA207) =20 static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a) { @@ -2815,13 +2815,13 @@ static bool do_vx_helper(DisasContext *ctx, arg_VX = *a, return true; } =20 -TRANS_FLAGS2(ALTIVEC_207, VADDCUQ, do_vx_helper, gen_helper_VADDCUQ) -TRANS_FLAGS2(ALTIVEC_207, VADDUQM, do_vx_helper, gen_helper_VADDUQM) +TRANS_FLAGS2(ISA207, VADDCUQ, do_vx_helper, gen_helper_VADDCUQ) +TRANS_FLAGS2(ISA207, VADDUQM, do_vx_helper, gen_helper_VADDUQM) =20 -TRANS_FLAGS2(ALTIVEC_207, VPMSUMD, do_vx_helper, gen_helper_VPMSUMD) +TRANS_FLAGS2(ISA207, VPMSUMD, do_vx_helper, gen_helper_VPMSUMD) =20 -TRANS_FLAGS2(ALTIVEC_207, VSUBCUQ, do_vx_helper, gen_helper_VSUBCUQ) -TRANS_FLAGS2(ALTIVEC_207, VSUBUQM, do_vx_helper, gen_helper_VSUBUQM) +TRANS_FLAGS2(ISA207, VSUBCUQ, do_vx_helper, gen_helper_VSUBCUQ) +TRANS_FLAGS2(ISA207, VSUBUQM, do_vx_helper, gen_helper_VSUBUQM) =20 static void gen_VADDCUW_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_ve= c b) { @@ -3092,10 +3092,10 @@ TRANS_FLAGS(ALTIVEC, VMULESH, do_vx_helper, gen_hel= per_VMULESH) TRANS_FLAGS(ALTIVEC, VMULOSH, do_vx_helper, gen_helper_VMULOSH) TRANS_FLAGS(ALTIVEC, VMULEUH, do_vx_helper, gen_helper_VMULEUH) TRANS_FLAGS(ALTIVEC, VMULOUH, do_vx_helper, gen_helper_VMULOUH) -TRANS_FLAGS2(ALTIVEC_207, VMULESW, do_vx_helper, gen_helper_VMULESW) -TRANS_FLAGS2(ALTIVEC_207, VMULOSW, do_vx_helper, gen_helper_VMULOSW) -TRANS_FLAGS2(ALTIVEC_207, VMULEUW, do_vx_helper, gen_helper_VMULEUW) -TRANS_FLAGS2(ALTIVEC_207, VMULOUW, do_vx_helper, gen_helper_VMULOUW) +TRANS_FLAGS2(ISA207, VMULESW, do_vx_helper, gen_helper_VMULESW) +TRANS_FLAGS2(ISA207, VMULOSW, do_vx_helper, gen_helper_VMULOSW) +TRANS_FLAGS2(ISA207, VMULEUW, do_vx_helper, gen_helper_VMULEUW) +TRANS_FLAGS2(ISA207, VMULOUW, do_vx_helper, gen_helper_VMULOUW) TRANS_FLAGS2(ISA310, VMULESD, do_vx_vmuleo, true , tcg_gen_muls2_i64) TRANS_FLAGS2(ISA310, VMULOSD, do_vx_vmuleo, false, tcg_gen_muls2_i64) TRANS_FLAGS2(ISA310, VMULEUD, do_vx_vmuleo, true , tcg_gen_mulu2_i64) diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-= ops.c.inc index c1951c6975..2facbc7cb4 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -2,7 +2,7 @@ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) =20 #define GEN_VXFORM_207(name, opc2, opc3) \ -GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_2= 07) +GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA207) =20 #define GEN_VXFORM_300(name, opc2, opc3) \ GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300) @@ -26,10 +26,10 @@ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10)= , 0x00000000, tp0, tp1), =20 GEN_VXFORM_300(vextublx, 6, 24), GEN_VXFORM_300(vextuhlx, 6, 25), -GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ISA207), GEN_VXFORM_300(vextubrx, 6, 28), GEN_VXFORM_300(vextuhrx, 6, 29), -GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ISA207), GEN_VXFORM_300(vsrv, 2, 28), GEN_VXFORM_300(vslv, 2, 29), GEN_VXFORM(vslo, 6, 16), @@ -113,10 +113,10 @@ GEN_VXFORM_UIMM(vctsxs, 5, 15), GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), =20 -GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ISA207), +GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ISA207), +GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ISA207), +GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ISA207), =20 GEN_VXFORM_300(vbpermd, 6, 23), GEN_VXFORM_207(vbpermq, 6, 21), @@ -127,8 +127,8 @@ GEN_VXFORM_207(vpmsumw, 4, 18), =20 GEN_VXFORM_207(vsbox, 4, 23), =20 -GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ISA207), +GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ISA207), =20 GEN_VXFORM_207(vshasigmaw, 1, 26), GEN_VXFORM_207(vshasigmad, 1, 27), --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897375006154100 Content-Type: text/plain; charset="utf-8" From: Chinmay Rath PPC2_ISA207S is only ever set in the CPUPPCState's insns_flags2 alongside PPC2_ISA207. Checks made by PPC2_ISA207S could be replaced with PPC2_ISA207, hence rendering it useless and apt for removal. This patch does the same. Reviewed-by: Amit Machhiwal Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-35-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/cpu.h | 5 +---- target/ppc/cpu_init.h | 2 +- hw/ppc/spapr_caps.c | 2 +- linux-user/ppc/elfload.c | 2 +- target/ppc/cpu_init.c | 3 +-- target/ppc/tcg-excp_helper.c | 8 ++++---- target/ppc/translate.c | 6 +++--- target/ppc/translate/bhrb-impl.c.inc | 4 ++-- target/ppc/translate/branch-impl.c.inc | 2 +- target/ppc/translate/processor-ctrl-impl.c.inc | 8 ++++---- 10 files changed, 19 insertions(+), 23 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 00676cea2b..4a77607f80 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2577,8 +2577,6 @@ enum { PPC2_FP_CVT_ISA206 =3D 0x0000000000000400ULL, /* ISA 2.06B floating point test instructions = */ PPC2_FP_TST_ISA206 =3D 0x0000000000000800ULL, - /* PowerISA 2.07 Book3s specification = */ - PPC2_ISA207S =3D 0x0000000000008000ULL, /* Double precision floating point conversion for signed integer 64 = */ PPC2_FP_CVT_S64 =3D 0x0000000000010000ULL, /* Transactional Memory (ISA 2.07, Book II) = */ @@ -2603,8 +2601,7 @@ enum { #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX= | \ PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ - PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_ISA207S | PPC2_DFP | \ + PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_DFP= | \ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \ PPC2_BCDA_ISA206 | PPC2_PPE42 | PPC2_PPE42X | \ diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index 73f014c82a..4ba559d8af 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -18,7 +18,7 @@ (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_ISA205 | \ - PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ + PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206) =20 #define PPC_INSNS_FLAGS2_POWER9 \ diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index f4a26a85b5..0d659e9b02 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -676,7 +676,7 @@ static void cap_ail_mode_3_apply(SpaprMachineState *spa= pr, =20 if (tcg_enabled()) { /* AIL-3 is only supported on POWER8 and above CPUs. */ - if (!(pcc->insns_flags2 & PPC2_ISA207S)) { + if (!(pcc->insns_flags2 & PPC2_ISA207)) { error_setg(errp, "TCG only supports cap-ail-mode-3 on POWER8 a= nd later CPUs"); error_append_hint(errp, "Try appending -machine cap-ail-mode-3= =3Doff\n"); return; diff --git a/linux-user/ppc/elfload.c b/linux-user/ppc/elfload.c index 8c40f1a663..7bf49e7c0b 100644 --- a/linux-user/ppc/elfload.c +++ b/linux-user/ppc/elfload.c @@ -116,7 +116,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) do { if (cpu->env.insns_flags2 & flag) { features |=3D feature; } } wh= ile (0) =20 GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL); - GET_FEATURE2((PPC2_ISA207 | PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_0= 7 | + GET_FEATURE2(PPC2_ISA207, (QEMU_PPC_FEATURE2_ARCH_2_07 | QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR= )); GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 | QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c251426b2e..6c626843c9 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6349,8 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *d= ata) pcc->insns_flags2 =3D PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_FP_TST_ISA206 | PPC2_ISA205 | PPC2_FP_CVT_S64= | PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; pcc->msr_mask =3D (1ull << MSR_SF) | diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index d06d3f8642..93aedb0c8e 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -314,7 +314,7 @@ void ppc_cpu_debug_excp_handler(CPUState *cs) #if defined(TARGET_PPC64) CPUPPCState *env =3D cpu_env(cs); =20 - if (env->insns_flags2 & PPC2_ISA207S) { + if (env->insns_flags2 & PPC2_ISA207) { if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { env->spr[SPR_DAR] =3D cs->watchpoint_hit->hitaddr; @@ -336,7 +336,7 @@ bool ppc_cpu_debug_check_breakpoint(CPUState *cs) #if defined(TARGET_PPC64) CPUPPCState *env =3D cpu_env(cs); =20 - if (env->insns_flags2 & PPC2_ISA207S) { + if (env->insns_flags2 & PPC2_ISA207) { target_ulong priv; =20 priv =3D env->spr[SPR_CIABR] & PPC_BITMASK(62, 63); @@ -365,7 +365,7 @@ bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWa= tchpoint *wp) bool wt, wti, hv, sv, pr; uint32_t dawrx; =20 - if ((env->insns_flags2 & PPC2_ISA207S) && + if ((env->insns_flags2 & PPC2_ISA207) && (wp =3D=3D env->dawr_watchpoint[0])) { dawrx =3D env->spr[SPR_DAWRX0]; } else if ((env->insns_flags2 & PPC2_ISA310) && @@ -849,7 +849,7 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulo= ng rb) void helper_book3s_trace(CPUPPCState *env, target_ulong prev_ip) { uint32_t error_code =3D 0; - if (env->insns_flags2 & PPC2_ISA207S) { + if (env->insns_flags2 & PPC2_ISA207) { /* Load/store reporting, SRR1[35, 36] and SDAR, are not implemente= d. */ env->spr[SPR_POWER_SIAR] =3D prev_ip; error_code =3D PPC_BIT(33); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f93af662f3..023935c10e 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2775,7 +2775,7 @@ static inline void gen_op_mfspr(DisasContext *ctx) } } else { /* ISA 2.07 defines these as no-ops */ - if ((ctx->insns_flags2 & PPC2_ISA207S) && + if ((ctx->insns_flags2 & PPC2_ISA207) && (sprn >=3D 808 && sprn <=3D 811)) { /* This is a nop */ return; @@ -2841,7 +2841,7 @@ static void gen_mtspr(DisasContext *ctx) } } else { /* ISA 2.07 defines these as no-ops */ - if ((ctx->insns_flags2 & PPC2_ISA207S) && + if ((ctx->insns_flags2 & PPC2_ISA207) && (sprn >=3D 808 && sprn <=3D 811)) { /* This is a nop */ return; @@ -4135,7 +4135,7 @@ TRANS64(LDARX, do_load_locked, DEF_MEMOP(MO_UQ)) static bool trans_LQARX(DisasContext *ctx, arg_LQARX *a) { REQUIRE_64BIT(ctx); - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); #if defined(TARGET_PPC64) TCGv EA; TCGv_i128 t16; diff --git a/target/ppc/translate/bhrb-impl.c.inc b/target/ppc/translate/bh= rb-impl.c.inc index 3a19bc4555..4b3914a1f6 100644 --- a/target/ppc/translate/bhrb-impl.c.inc +++ b/target/ppc/translate/bhrb-impl.c.inc @@ -14,7 +14,7 @@ =20 static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrbe *arg) { - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); TCGv_i32 bhrbe =3D tcg_constant_i32(arg->bhrbe); gen_helper_mfbhrbe(cpu_gpr[arg->rt], tcg_env, bhrbe); return true; @@ -22,7 +22,7 @@ static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrb= e *arg) =20 static bool trans_CLRBHRB(DisasContext *ctx, arg_CLRBHRB *arg) { - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); gen_helper_clrbhrb(tcg_env); return true; } diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc index e5b64ca84e..51fcabff63 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -14,7 +14,7 @@ =20 static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) { - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); =20 translator_io_start(&ctx->base); gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/tr= anslate/processor-ctrl-impl.c.inc index cfcca28267..cb125cfa72 100644 --- a/target/ppc/translate/processor-ctrl-impl.c.inc +++ b/target/ppc/translate/processor-ctrl-impl.c.inc @@ -23,7 +23,7 @@ =20 static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a) { - if (!(ctx->insns_flags2 & PPC2_ISA207S)) { + if (!(ctx->insns_flags2 & PPC2_ISA207)) { /* * Before Power ISA 2.07, processor control instructions were only * implemented in the "Embedded.Processor Control" category. @@ -47,7 +47,7 @@ static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a) =20 static bool trans_MSGSND(DisasContext *ctx, arg_X_rb *a) { - if (!(ctx->insns_flags2 & PPC2_ISA207S)) { + if (!(ctx->insns_flags2 & PPC2_ISA207)) { /* * Before Power ISA 2.07, processor control instructions were only * implemented in the "Embedded.Processor Control" category. @@ -72,7 +72,7 @@ static bool trans_MSGSND(DisasContext *ctx, arg_X_rb *a) static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a) { REQUIRE_64BIT(ctx); - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); REQUIRE_SV(ctx); #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) gen_helper_book3s_msgclrp(tcg_env, cpu_gpr[a->rb]); @@ -85,7 +85,7 @@ static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a) static bool trans_MSGSNDP(DisasContext *ctx, arg_X_rb *a) { REQUIRE_64BIT(ctx); - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); REQUIRE_SV(ctx); #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) gen_helper_book3s_msgsndp(tcg_env, cpu_gpr[a->rb]); --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787897388; cv=none; d=zohomail.com; s=zohoarc; b=GTCWUPKdoz9NjLoet2PcxC2BSqHF65VJAK1Wc/Qf3g7qqH6I3CWRgPSQkKXcxZ31Zg0B8nESLgsyneGkljX3cp5Q2SKXdVQO1don5BThw0SbnTi0zgVZosxfQYCOJD+LUTNSGxbuBPQdofykBTmjDuOGQ5PEFCv+OJ6cRvuTBRc= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=ebFzdhOHIeg/L+KHY NbNsDTAWodqmNQcU9yqNDNZEaM=; b=EvIaXvIu/iBE7rWKDuFu9xwgBltcds188 I4zus/DYFLPsL8IU+GhfZpIeGXXZ1AKy45b8qt1UlWsFbyLmLin+VDlGbEwLQjH1 clSEJPuTuNNOKKxJYACyMLc4FOHBF/h3XdLRn+9te0TqtfAJ9ey4oVhtd7rKBaTB Ck0/NYfGqvdnXHJvdFj0kqOjsPnhlNbjMFNHRmn36utXDbsKCsJnglxSbQwiwhdN +t32rexHE+/kFRgT5/62X8D5Idc05a23ThVjOAPIa4Jjqd6VjlexAJN0y1l59F2/ uHw2TV39PsC0hY8935QPM9AxijnrQ6P0KjMHvefPJ7a3+TdcURZWA== From: Harsh Prateek Bora To: qemu-devel@nongnu.org Cc: Chinmay Rath , Amit Machhiwal , Glenn Miles , Richard Henderson , Aniket Sahu Subject: [PULL 39/41] target/ppc: Reorder PPC2 flags Date: Fri, 28 Aug 2026 11:37:14 +0530 Message-ID: <20260828060716.91672-40-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com> References: <20260828060716.91672-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 7ma61gf6ZNXWK9I4pyMbmWd4qHATUXuZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX7V6TD44b4L0R wF+jcZKN2p7U91bwxDn84YKpEZJL6ZvK4kGc4SLdaAejGm+vI3OZKsVYnSJIdTi7iKqqIOzkUea xiUU1Vs5BZ2nrTs2QcqMpUHt/AN5hP30EXjuW4/bAXGjqRePIC+1Yzuk/u7/1kWNOwvgY573VsR y4S4j+t2XDoSJn10DkP5hZT4ICp2a7YMn6wxuVIupUNxmPFV+2KopiCSbJLqnAFjGf+Gdixp+1C Tn1JPYZAieHjaglGftsgi0LD3UJX1ZvdCkOk/wxlfmHyVtWy4tNULrKvUef3S89AV3Qt9EOb1sy Qsjsdc1YYAg0lZiPJNlu3iNKBGDalvGF//rdaVodNUxianGojkBrgWqhD3YKmQSXExyTw168cZM aIgRg9UbYL9l7AFujurySxA6j/a7ExLIRxqZD1kDYLzvfB0KZusKJ9FlXz5Pv2v1ByadFlNpUBd q2t0799/vH+FH1LIIaQ== X-Authority-Analysis: v=2.4 cv=Y/nIdBeN c=1 sm=1 tr=0 ts=6a91260a cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=Sv0fKeRqtYgA:10 a=f7IdgyKtn90A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=KKAkSRfTAAAA:8 a=fk2NG-Jcr9xy3FZPRKoA:9 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI4MDA1MCBTYWx0ZWRfX19IUoH9BR4h4 3YrjrRTEahWuBIyRvRrH80zn2G0j1A2CdKDTeal3A9ToekE2A+JnJrom0CPjCLlrCM9Xnif9XMT KxT/TAWEXZsdk7J5Fdz5K+zlkmr1Uok= X-Proofpoint-ORIG-GUID: 7ma61gf6ZNXWK9I4pyMbmWd4qHATUXuZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-28_01,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608280050 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897391142154100 Content-Type: text/plain; charset="utf-8" From: Chinmay Rath Consolidation of different variations of Power ISA 2.07 flags into the PPC2_ISA207 flag has left gaps in the flag encoding. This patch reorders them, restoring the expected incremental order without any gaps, freeing up bits for future use. Reviewed-by: Amit Machhiwal Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-36-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/cpu.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 4a77607f80..3fb51bbeb8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2578,25 +2578,25 @@ enum { /* ISA 2.06B floating point test instructions = */ PPC2_FP_TST_ISA206 =3D 0x0000000000000800ULL, /* Double precision floating point conversion for signed integer 64 = */ - PPC2_FP_CVT_S64 =3D 0x0000000000010000ULL, + PPC2_FP_CVT_S64 =3D 0x0000000000001000ULL, /* Transactional Memory (ISA 2.07, Book II) = */ - PPC2_TM =3D 0x0000000000020000ULL, + PPC2_TM =3D 0x0000000000002000ULL, /* Server PM instructgions (ISA 2.06, Book III) = */ - PPC2_PM_ISA206 =3D 0x0000000000040000ULL, + PPC2_PM_ISA206 =3D 0x0000000000004000ULL, /* POWER ISA 3.0 = */ - PPC2_ISA300 =3D 0x0000000000080000ULL, + PPC2_ISA300 =3D 0x0000000000008000ULL, /* POWER ISA 3.1 = */ - PPC2_ISA310 =3D 0x0000000000100000ULL, + PPC2_ISA310 =3D 0x0000000000010000ULL, /* lwsync instruction = */ - PPC2_MEM_LWSYNC =3D 0x0000000000200000ULL, + PPC2_MEM_LWSYNC =3D 0x0000000000020000ULL, /* ISA 2.06 BCD assist instructions = */ - PPC2_BCDA_ISA206 =3D 0x0000000000400000ULL, + PPC2_BCDA_ISA206 =3D 0x0000000000040000ULL, /* PPE42 instructions = */ - PPC2_PPE42 =3D 0x0000000000800000ULL, + PPC2_PPE42 =3D 0x0000000000080000ULL, /* PPE42X instructions = */ - PPC2_PPE42X =3D 0x0000000001000000ULL, + PPC2_PPE42X =3D 0x0000000000100000ULL, /* PPE42XM instructions = */ - PPC2_PPE42XM =3D 0x0000000002000000ULL, + PPC2_PPE42XM =3D 0x0000000000200000ULL, =20 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX= | \ PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897472900158500 Content-Type: text/plain; charset="utf-8" From: Chinmay Rath The summary of changes in Power ISA version 2.07B mentions : "ICBT instruction has been moved from the Embedded category to the Base category". Updating ICBT flag for the same. While we are at it, correct the invalid mask as per the ISA as well. Reviewed-by: Amit Machhiwal Tested-by: Tasmiya Nalatwad Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-37-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- target/ppc/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 023935c10e..467b8f3d4e 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4498,8 +4498,8 @@ GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12,= 0x00, 0x03800001, GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), -GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, - PPC_BOOKE, PPC2_BOOKE206), +GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x02000001, + PPC_BOOKE, (PPC2_BOOKE206 | PPC2_ISA207)), GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_440_SPEC), GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), --=20 2.52.0 From nobody Sat Sep 26 21:35:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787897478901158500 Content-Type: text/plain; charset="utf-8" From: Chinmay Rath I have been contributing and reviewing code in the PowerPC TCG CPUs module for a long time now. Stepping up as an active maintainer to better reflect the current status. Acked-by: Aditya Gupta Acked-by: Gautam Menghani Acked-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-38-rathc@lin= ux.ibm.com Signed-off-by: Harsh Prateek Bora --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 6c18b8a419..4a49a40294 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -337,8 +337,8 @@ F: tests/functional/or1k/meson.build F: tests/tcg/or1k/ =20 PowerPC TCG CPUs +M: Chinmay Rath M: Nicholas Piggin -R: Chinmay Rath R: Glenn Miles R: Harsh Prateek Bora L: qemu-ppc@nongnu.org --=20 2.52.0