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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837495499158500 Content-Type: text/plain; charset="utf-8" From: Nikhil Kumar Singh Move EXTSWSLI to decodetree using the XS-form layout with a custom %xs_sh field to represent the fractured shift encoding. This replaces legacy GEN_HANDLER-based implementations with a single trans_EXTSWSLI() handler. The implementation intentionally operates directly on the destination GPR to preserve exact TCG output and avoid introducing temporary variables, matching legacy behavior. Testing: - Verified TCG equivalence with legacy implementation. Signed-off-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 8 ++++++++ target/ppc/translate.c | 43 ++++++++++++++-------------------------- 2 files changed, 23 insertions(+), 28 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 0e9c68f2fb..342e65dadf 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -117,6 +117,11 @@ &X_sa_rc rs ra rc @X_sa_rc ...... rs:5 ra:5 ..... .......... rc:1 &X_sa_rc =20 +# XS-form with fractured shift amount +%xs_sh 1:1 11:5 +&XS rs ra sh rc +@XS ...... rs:5 ra:5 ..... ......... . rc:1 &XS sh=3D%= xs_sh + %x_frtp 22:4 !function=3Dtimes_2 %x_frap 17:4 !function=3Dtimes_2 %x_frbp 12:4 !function=3Dtimes_2 @@ -1301,6 +1306,9 @@ XVF64GERPN 111011 ... -- .... 0 ..... 10111010 .= .- @XX3_at xa=3D%xx_xa_pair XVF64GERNP 111011 ... -- .... 0 ..... 01111010 ..- @XX3_at xa=3D%xx_= xa_pair XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=3D%xx_= xa_pair =20 +##Extend Sign Word and Shift Left Immediate XS-form +EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS + ## Vector Division Instructions =20 VDIVSW 000100 ..... ..... ..... 00110001011 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 06ed2adf10..e627f48f9e 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2470,30 +2470,6 @@ static void gen_sradi1(DisasContext *ctx) gen_sradi(ctx, 1); } =20 -/* extswsli & extswsli. */ -static inline void gen_extswsli(DisasContext *ctx, int n) -{ - int sh =3D SH(ctx->opcode) + (n << 5); - TCGv dst =3D cpu_gpr[rA(ctx->opcode)]; - TCGv src =3D cpu_gpr[rS(ctx->opcode)]; - - tcg_gen_ext32s_tl(dst, src); - tcg_gen_shli_tl(dst, dst, sh); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, dst); - } -} - -static void gen_extswsli0(DisasContext *ctx) -{ - gen_extswsli(ctx, 0); -} - -static void gen_extswsli1(DisasContext *ctx) -{ - gen_extswsli(ctx, 1); -} - /* srd & srd. */ static void gen_srd(DisasContext *ctx) { @@ -5750,6 +5726,21 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *= d, arg_PLS_D *a) return true; } =20 +static bool trans_EXTSWSLI(DisasContext *ctx, arg_XS *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + + /* Mimic legacy behavior: operate directly on dst */ + tcg_gen_ext32s_tl(cpu_gpr[a->ra], cpu_gpr[a->rs]); + tcg_gen_shli_tl(cpu_gpr[a->ra], cpu_gpr[a->ra], a->sh); + + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } + return true; +} + #include "translate/fixedpoint-impl.c.inc" =20 #include "translate/fp-impl.c.inc" @@ -5850,10 +5841,6 @@ GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_= 64B), GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), -GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, - PPC_NONE, PPC2_ISA300), -GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, - PPC_NONE, PPC2_ISA300), #endif /* handles lfdp, lxsd, lxssp */ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837487494158500 Content-Type: text/plain; charset="utf-8" From: Nikhil Kumar Singh Migrate load-and-reserve instructions (lbarx, lharx, lwarx, ldarx, lqarx) to decodetree using the X-form layout. A shared helper (do_load_locked) is introduced for standard-width variants, while LQARX is handled separately due to its 128-bit semantics and register pairing constraints. The implementation preserves legacy behavior, including: - Reservation granularity and overwrite semantics - Alignment requirements - Invalid instruction cases for LQARX Testing: - Verified TCG equivalence with legacy implementation Signed-off-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Reviewed-by: Amit Machhiwal Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 7 +++ target/ppc/translate.c | 118 +++++++++++++++++++-------------------- 2 files changed, 63 insertions(+), 62 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 342e65dadf..26948e08a7 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1309,6 +1309,13 @@ XVF64GERNN 111011 ... -- .... 0 ..... 11111010 = ..- @XX3_at xa=3D%xx_xa_pair ##Extend Sign Word and Shift Left Immediate XS-form EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS =20 +## Load and Reserve Instructions +LBARX 011111 ..... ..... ..... 0000110100 . @X_rc +LHARX 011111 ..... ..... ..... 0001110100 . @X_rc +LWARX 011111 ..... ..... ..... 0000010100 . @X_rc +LDARX 011111 ..... ..... ..... 0001010100 . @X_rc +LQARX 011111 ..... ..... ..... 0100010100 . @X_rc + ## Vector Division Instructions =20 VDIVSW 000100 ..... ..... ..... 00110001011 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e627f48f9e..69c4443dda 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2947,30 +2947,6 @@ static void gen_isync(DisasContext *ctx) ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } =20 -static void gen_load_locked(DisasContext *ctx, MemOp memop) -{ - TCGv gpr =3D cpu_gpr[rD(ctx->opcode)]; - TCGv t0 =3D tcg_temp_new(); - - gen_set_access_type(ctx, ACCESS_RES); - gen_addr_reg_index(ctx, t0); - tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN); - tcg_gen_mov_tl(cpu_reserve, t0); - tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); - tcg_gen_mov_tl(cpu_reserve_val, gpr); -} - -#define LARX(name, memop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - gen_load_locked(ctx, memop); \ -} - -/* lwarx */ -LARX(lbarx, MO_UB) -LARX(lharx, MO_UW) -LARX(lwarx, MO_UL) - static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, TCGv EA, TCGCond cond, int addend) { @@ -3219,42 +3195,9 @@ STCX(sthcx_, MO_UW) STCX(stwcx_, MO_UL) =20 #if defined(TARGET_PPC64) -/* ldarx */ -LARX(ldarx, MO_UQ) /* stdcx. */ STCX(stdcx_, MO_UQ) =20 -/* lqarx */ -static void gen_lqarx(DisasContext *ctx) -{ - int rd =3D rD(ctx->opcode); - TCGv EA, hi, lo; - TCGv_i128 t16; - - if (unlikely((rd & 1) || (rd =3D=3D rA(ctx->opcode)) || - (rd =3D=3D rB(ctx->opcode)))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - - gen_set_access_type(ctx, ACCESS_RES); - EA =3D tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - - /* Note that the low part is always in RD+1, even in LE mode. */ - lo =3D cpu_gpr[rd + 1]; - hi =3D cpu_gpr[rd]; - - t16 =3D tcg_temp_new_i128(); - tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIG= N)); - tcg_gen_extr_i128_i64(lo, hi, t16); - - tcg_gen_mov_tl(cpu_reserve, EA); - tcg_gen_movi_tl(cpu_reserve_length, 16); - tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val)); - tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2)); -} - /* stqcx. */ static void gen_stqcx_(DisasContext *ctx) { @@ -5741,6 +5684,62 @@ static bool trans_EXTSWSLI(DisasContext *ctx, arg_XS= *a) return true; } =20 +/* + * Load-and-reserve core + */ +static bool do_load_locked(DisasContext *ctx, arg_X_rc *a, MemOp memop) +{ + TCGv EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + TCGv gpr =3D cpu_gpr[a->rt]; + + gen_set_access_type(ctx, ACCESS_RES); + + tcg_gen_qemu_ld_tl(gpr, EA, ctx->mem_idx, memop | MO_ALIGN); + + tcg_gen_mov_tl(cpu_reserve, EA); + tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); + + tcg_gen_mov_tl(cpu_reserve_val, gpr); + + return true; +} + +TRANS_FLAGS2(ATOMIC_ISA206, LBARX, do_load_locked, DEF_MEMOP(MO_UB)) +TRANS_FLAGS2(ATOMIC_ISA206, LHARX, do_load_locked, DEF_MEMOP(MO_UW)) +TRANS(LWARX, do_load_locked, DEF_MEMOP(MO_UL)) +TRANS64(LDARX, do_load_locked, DEF_MEMOP(MO_UQ)) + +static bool trans_LQARX(DisasContext *ctx, arg_LQARX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA207S); +#if defined(TARGET_PPC64) + TCGv EA; + TCGv_i128 t16; + /* Must use even register and avoid overlap */ + if (unlikely((a->rt & 1) || (a->rt =3D=3D a->ra) || (a->rt =3D=3D a->r= b))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + gen_set_access_type(ctx, ACCESS_RES); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + t16 =3D tcg_temp_new_i128(); + + tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIG= N)); + tcg_gen_extr_i128_i64(cpu_gpr[a->rt + 1], cpu_gpr[a->rt], t16); + tcg_gen_mov_tl(cpu_reserve, EA); + tcg_gen_movi_tl(cpu_reserve_length, 16); + tcg_gen_st_i64(cpu_gpr[a->rt], tcg_env, + offsetof(CPUPPCState, reserve_val)); + tcg_gen_st_i64(cpu_gpr[a->rt + 1], tcg_env, + offsetof(CPUPPCState, reserve_val2)); +#else + qemu_build_not_reached(); +#endif + return true; +} + #include "translate/fixedpoint-impl.c.inc" =20 #include "translate/fp-impl.c.inc" @@ -5853,9 +5852,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_S= TRING), GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), -GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), @@ -5864,8 +5860,6 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00= 000000, PPC_RES), #if defined(TARGET_PPC64) GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), -GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), #endif --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 27 Aug 2026 13:30:50 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5146920043; Thu, 27 Aug 2026 13:30:44 +0000 (GMT) Received: from li-18a0a34c-33fc-11b2-a85c-d9f1631c5692.ibm.com (unknown [9.111.12.1]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 27 Aug 2026 13:30:44 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=Pig9Ri2uLFzTWN9kz frQc0XmQqLOZxy/WBJDjn6rYP4=; b=TKerUJkg2ScKVSEREd2AIFPHLv65P6HSM 50CWjKdAYU6WApXkS/Rf0eJxC6YYPf0sOgs/cMZJFJto7vnDqUNMbCdCdO9jKmkO R9POpbA+dZhBGm775y4nBS8y1NablzBvJzAOh2HyxPUH4ALi4r7d1hY4Y8FhkfhH pi7Dlokw/WoIs/N7KtkptAh1hVTkhhuwOyFf9D2oodOoqUP7ZQyt68124er/YMA8 rKqYe0vNKg1CopeYtjDHNdR9ceLN0uAjDFF6RHJm8iaR038jmiKqUtm9MrNck3HS dscpaf0yr6JNC8KUzHpmOcRphmtnOzkQFkRPylCPTJyz6rM0yZSxA== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Tasmiya Nalatwad , Chinmay Rath Subject: [PATCH v3 03/37] target/ppc: Convert cache instructions to decodetree Date: Thu, 27 Aug 2026 18:59:18 +0530 Message-ID: <20260827133010.278889-4-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: _uhaXPuXgFqIZaA6CNW2YKLvL8RH84MM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDEwOSBTYWx0ZWRfXyu9zmFPxIKkW rva+wWfGcdo3OZMlqPgxIMR5oEU9TusAQSpRscV6PzhSqL1tMRwEKPdZU6PmwFGBD3eIbwU8Jyd QUfCZOveTba8ndFF/gaMpQAocGei5YvYekcHwsCyh/rDMXVm7VYNTypX/3YaygJF4HPzkmg+bqO c0Vi8KklXJHsknA5bY19jGz5jORDCg9jslsGG8QLSUdid41EM0bGiwf/T0lXYgotde0/CaEHoIv 02kus34Ggg4m2TkieX2kf+U+Fs6Tks4WWmkpgJ623vy+DvDK4R/Jjt5j3/mYrEi0TBFoJxOBuOf 7wUAF6T7ht2yTOBGx+DFaC/wfEuQ+hT+KSBFou4jM7tcsFP/629dKY1S8bT4ylNvEsFb/qhsbsp 1B+Wy9/UjwVSX+Xk66UFaqLnQx4cZR2w0r/aEeKBLDnrl59HWPzRrTq0jScvCihlWy3yrlU5Dqo p9zfe9KC6kUL//4K4qw== X-Authority-Analysis: v=2.4 cv=Y/nIdBeN c=1 sm=1 tr=0 ts=6a903c19 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=Lmgfs3a3K7fV6kfGSZAA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDEwOSBTYWx0ZWRfX9HMsRAtTIlgX aXjUdZ9qWhdCrXMB+B0BFcnNQ4tcldmciLq2uBG8hvC9EdWEWibWw27MLwVCNPgWMTdo65dCrr7 ufZVAu5qg/Da56Ey3C8CpUSz8k47d6w= X-Proofpoint-ORIG-GUID: A6j8D2AXgiUaEqF_3N0HmT-GLlZyvpun X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270109 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837511698158500 Content-Type: text/plain; charset="utf-8" From: Nikhil Kumar Singh Convert cache management instructions to decodetree using custom X-form layouts (@X_ea, @X_l, @X_th) and dedicated translation functions. This ensures reserved bits are accurately represented and ignored by the decoder (using '-' in the patterns), rather than being erroneously parsed into instruction fields. Legacy GEN_HANDLER-based implementations are removed. The implementation preserves legacy semantics, including: - MMU-visible accesses for instructions treated as loads (e.g. dcbt, dcbtst, dcbtep, dcbtstep) - Supervisor and BookE-specific constraints - Effective address computation via do_ea_calc() Instructions that were defined as no-ops in the legacy implementation remain no-ops here. Note on intentional behavior changes: - dcbf now validates the L field against the Power ISA v3.1 set of legal values (0, 1, 3, 4, 6). - Reserved bits that were previously encoded as part of the opcode mask (and trapped if set) are now properly decoded as "don't care" ('-' in the pattern). Testing: - Verified TCG equivalence for all cache operations Signed-off-by: Nikhil Kumar Singh Tested-by: Tasmiya Nalatwad Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Reviewed-by: Amit Machhiwal Tested-by: Aniket Sahu --- target/ppc/helper.h | 4 +- target/ppc/insn32.decode | 33 ++++ target/ppc/mem_helper.c | 4 +- target/ppc/translate.c | 409 ++++++++++++++++++++------------------- 4 files changed, 249 insertions(+), 201 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6b2d19a3ad..82ec3a471b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -52,8 +52,8 @@ DEF_HELPER_FLAGS_3(dcbz, TCG_CALL_NO_WG, void, env, tl, i= nt) #ifdef TARGET_PPC64 DEF_HELPER_FLAGS_2(dcbzl, TCG_CALL_NO_WG, void, env, tl) #endif -DEF_HELPER_FLAGS_2(icbi, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_FLAGS_2(icbiep, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(ICBI, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(ICBIEP, TCG_CALL_NO_WG, void, env, tl) =20 #if defined(TARGET_PPC64) DEF_HELPER_4(DIVDEU, i64, env, i64, i64, i32) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 26948e08a7..92706e2097 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1306,6 +1306,39 @@ XVF64GERPN 111011 ... -- .... 0 ..... 10111010 = ..- @XX3_at xa=3D%xx_xa_pair XVF64GERNP 111011 ... -- .... 0 ..... 01111010 ..- @XX3_at xa=3D%xx_= xa_pair XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=3D%xx_= xa_pair =20 +## Cache Management Instructions + +&X_ea ra rb +@X_ea ...... ..... ra:5 rb:5 .......... . &X_ea + +&X_l l ra rb +@X_l ...... .. l:3 ra:5 rb:5 .......... . &X_l + +&X_th th ra rb +@X_th ...... th:5 ra:5 rb:5 .......... . &X_th + +DCBF 011111 -- ... ..... ..... 0001010110 - @X_l +DCBFEP 011111 ----- ..... ..... 0001111111 - @X_ea +DCBI 011111 ----- ..... ..... 0111010110 - @X_ea +DCBST 011111 ----- ..... ..... 0000110110 - @X_ea +DCBSTEP 011111 ----- ..... ..... 0000111111 - @X_ea +DCBA 011111 ----- ..... ..... 1011110110 - @X_ea + +DCBT 011111 ..... ..... ..... 0100010110 - @X_th +DCBTEP 011111 ----- ..... ..... 0100111111 - @X_ea +DCBTST 011111 ..... ..... ..... 0011110110 - @X_th +DCBTSTEP 011111 ----- ..... ..... 0011111111 - @X_ea + +DCBTLS 011111 ..... ..... ..... 0010100110 - @X_th +DCBLC 011111 ..... ..... ..... 0110000110 - @X_th + +ICBI 011111 ----- ..... ..... 1111010110 - @X_ea +ICBIEP 011111 ----- ..... ..... 1111011111 - @X_ea + +DST 011111 ----- ..... ..... 0101010110 - @X_ea +DSTST 011111 ----- ..... ..... 0101110110 - @X_ea +DSS 011111 ----- ..... ..... 1100110110 - @X_ea + ##Extend Sign Word and Shift Left Immediate XS-form EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS =20 diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 787ba2cdec..8ad6945590 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -341,7 +341,7 @@ void helper_dcbzl(CPUPPCState *env, target_ulong addr) } #endif =20 -void helper_icbi(CPUPPCState *env, target_ulong addr) +void helper_ICBI(CPUPPCState *env, target_ulong addr) { unsigned mmu_idx =3D cpu_mmu_index(env_cpu(env), false); MemOpIdx oi =3D make_memop_idx(MO_UL | MO_UNALN, mmu_idx); @@ -357,7 +357,7 @@ void helper_icbi(CPUPPCState *env, target_ulong addr) cpu_ldl_mmu(env, addr, oi, GETPC()); } =20 -void helper_icbiep(CPUPPCState *env, target_ulong addr) +void helper_ICBIEP(CPUPPCState *env, target_ulong addr) { #if !defined(CONFIG_USER_ONLY) MemOpIdx oi =3D make_memop_idx(MO_UL | MO_UNALN, PPC_TLB_EPID_LOAD); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 69c4443dda..4bd7f44b3c 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4298,128 +4298,6 @@ static void gen_setb(DisasContext *ctx) =20 /*** Cache management = ***/ =20 -/* dcbf */ -static void gen_dcbf(DisasContext *ctx) -{ - /* XXX: specification says this is treated as a load by the MMU */ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_qemu_ld8u(ctx, t0, t0); -} - -/* dcbfep (external PID dcbf) */ -static void gen_dcbfep(DisasContext *ctx) -{ - /* XXX: specification says this is treated as a load by the MMU */ - TCGv t0; - CHK_SV(ctx); - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); -} - -/* dcbi (Supervisor only) */ -static void gen_dcbi(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv EA, val; - - CHK_SV(ctx); - EA =3D tcg_temp_new(); - gen_set_access_type(ctx, ACCESS_CACHE); - gen_addr_reg_index(ctx, EA); - val =3D tcg_temp_new(); - /* XXX: specification says this should be treated as a store by the MM= U */ - gen_qemu_ld8u(ctx, val, EA); - gen_qemu_st8(ctx, val, EA); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -/* dcdst */ -static void gen_dcbst(DisasContext *ctx) -{ - /* XXX: specification say this is treated as a load by the MMU */ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_qemu_ld8u(ctx, t0, t0); -} - -/* dcbstep (dcbstep External PID version) */ -static void gen_dcbstep(DisasContext *ctx) -{ - /* XXX: specification say this is treated as a load by the MMU */ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); -} - -/* dcbt */ -static void gen_dcbt(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a load by the MMU but - * does not generate any exception - */ -} - -/* dcbtep */ -static void gen_dcbtep(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a load by the MMU but - * does not generate any exception - */ -} - -/* dcbtst */ -static void gen_dcbtst(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a load by the MMU but - * does not generate any exception - */ -} - -/* dcbtstep */ -static void gen_dcbtstep(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a load by the MMU but - * does not generate any exception - */ -} - -/* dcbtls */ -static void gen_dcbtls(DisasContext *ctx) -{ - /* Always fails locking the cache */ - TCGv t0 =3D tcg_temp_new(); - gen_load_spr(t0, SPR_Exxx_L1CSR0); - tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); - gen_store_spr(SPR_Exxx_L1CSR0, t0); -} - -/* dcblc */ -static void gen_dcblc(DisasContext *ctx) -{ - /* - * interpreted as no-op - */ -} - /* dcbz */ static void gen_dcbz(DisasContext *ctx) { @@ -4448,64 +4326,6 @@ static void gen_dcbzep(DisasContext *ctx) gen_helper_dcbz(tcg_env, tcgv_addr, tcg_constant_i32(PPC_TLB_EPID_STOR= E)); } =20 -/* dst / dstt */ -static void gen_dst(DisasContext *ctx) -{ - if (rA(ctx->opcode) =3D=3D 0) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - } else { - /* interpreted as no-op */ - } -} - -/* dstst /dststt */ -static void gen_dstst(DisasContext *ctx) -{ - if (rA(ctx->opcode) =3D=3D 0) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - } else { - /* interpreted as no-op */ - } - -} - -/* dss / dssall */ -static void gen_dss(DisasContext *ctx) -{ - /* interpreted as no-op */ -} - -/* icbi */ -static void gen_icbi(DisasContext *ctx) -{ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_helper_icbi(tcg_env, t0); -} - -/* icbiep */ -static void gen_icbiep(DisasContext *ctx) -{ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_helper_icbiep(tcg_env, t0); -} - -/* Optional: */ -/* dcba */ -static void gen_dcba(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a store by the MMU - * but does not generate any exception - */ -} - /*** Segment register manipulation = ***/ /* Supervisor only: */ =20 @@ -5740,6 +5560,218 @@ static bool trans_LQARX(DisasContext *ctx, arg_LQAR= X *a) return true; } =20 +/* + * Cache Management Instructions (decodetree) + */ + +static bool trans_DCBA(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS(ctx, CACHE_DCBA); + return true; +} + +static bool trans_DCBT(DisasContext *ctx, arg_X_th *a) +{ + REQUIRE_INSNS_FLAGS(ctx, CACHE); + return true; +} + +static bool trans_DCBTEP(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + return true; +} + +static bool trans_DCBTST(DisasContext *ctx, arg_X_th *a) +{ + REQUIRE_INSNS_FLAGS(ctx, CACHE); + return true; +} + +static bool trans_DCBTSTEP(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + return true; +} + +static bool trans_DCBLC(DisasContext *ctx, arg_X_th *a) +{ + /* Requires either PPC_BOOKE or PPC2_BOOKE206 */ + if (!(ctx->insns_flags & PPC_BOOKE) && + !(ctx->insns_flags2 & PPC2_BOOKE206)) { + return false; + } + return true; +} + +static bool trans_DSS(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); + return true; +} + +static bool trans_DCBTLS(DisasContext *ctx, arg_X_th *a) +{ + TCGv t0 =3D tcg_temp_new(); + + /* Requires either PPC_BOOKE or PPC2_BOOKE206 */ + if (!(ctx->insns_flags & PPC_BOOKE) && + !(ctx->insns_flags2 & PPC2_BOOKE206)) { + return false; + } + + gen_load_spr(t0, SPR_Exxx_L1CSR0); + tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); + gen_store_spr(SPR_Exxx_L1CSR0, t0); + + return true; +} + +static bool trans_DST(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); + + if (a->ra =3D=3D 0) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + } + + return true; +} + +static bool trans_DSTST(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); + + if (a->ra =3D=3D 0) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + } + + return true; +} + +static bool trans_DCBF(DisasContext *ctx, arg_X_l *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS(ctx, CACHE); + + /* + * As per PowerISA v3.1, the L field can have values 0, 1, 3, 4, or 6. + * Other values are Undefined Behavior (UB). + */ + switch (a->l) { + case 0: /* dcbf */ + case 1: /* dcbfl */ + case 3: /* dcbflp */ + case 4: /* dcbfps */ + case 6: /* dcbstps */ + break; + default: + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + gen_qemu_ld8u(ctx, EA, EA); + + return true; +} + +static bool trans_DCBST(DisasContext *ctx, arg_X_ea *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS(ctx, CACHE); + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + gen_qemu_ld8u(ctx, EA, EA); + + return true; +} + +static bool trans_DCBFEP(DisasContext *ctx, arg_X_ea *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + + REQUIRE_SV(ctx); + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + + tcg_gen_qemu_ld_tl(EA, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); + + return true; +} + +static bool trans_DCBSTEP(DisasContext *ctx, arg_X_ea *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + + tcg_gen_qemu_ld_tl(EA, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); + + return true; +} + +static bool trans_DCBI(DisasContext *ctx, arg_X_ea *a) +{ + REQUIRE_INSNS_FLAGS(ctx, CACHE); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); + return true; +#else + TCGv EA, val; + + REQUIRE_SV(ctx); + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + val =3D tcg_temp_new(); + + gen_qemu_ld8u(ctx, val, EA); + gen_qemu_st8(ctx, val, EA); + + return true; +#endif +} + +static bool trans_ICBI(DisasContext *ctx, arg_X_ea *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS(ctx, CACHE_ICBI); + + gen_set_access_type(ctx, ACCESS_CACHE); + + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + gen_helper_ICBI(tcg_env, EA); + + return true; +} + +static bool trans_ICBIEP(DisasContext *ctx, arg_X_ea *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + REQUIRE_SV(ctx); + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + + gen_helper_ICBIEP(tcg_env, EA); + return true; +} + #include "translate/fixedpoint-impl.c.inc" =20 #include "translate/fp-impl.c.inc" @@ -5904,25 +5936,8 @@ GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, = PPC_NONE, PPC2_ISA300), #endif GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), -GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), -GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE20= 6), -GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), -GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), -GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE2= 06), -GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), -GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE20= 6), -GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), -GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE= 206), -GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE2= 06), -GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE20= 6), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE20= 6), -GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), -GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), -GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), -GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), -GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE20= 6), -GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837521602158500 Content-Type: text/plain; charset="utf-8" From: Aboorva Devarajan Move below instructions to decodetree specification: vmrg{hb, hh, hw, lb, lh, lw} : VX-form The individual gen_vmrg* functions generated by GEN_VXFORM are replaced by a shared do_vmrg() helper dispatching to the existing gen_helper_VMRG* TCG helpers via the TRANS_FLAGS() macro, which also handles the ALTIVEC facility check. The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Aboorva Devarajan Reviewed-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/helper.h | 12 ++++++------ target/ppc/insn32.decode | 9 +++++++++ target/ppc/int_helper.c | 12 ++++++------ target/ppc/translate/vmx-impl.c.inc | 25 +++++++++++++++++++------ target/ppc/translate/vmx-ops.c.inc | 6 ------ 5 files changed, 40 insertions(+), 24 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 82ec3a471b..5517d2950f 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -173,12 +173,12 @@ DEF_HELPER_4(vcmpeqfp_dot, void, env, avr, avr, avr) DEF_HELPER_4(vcmpgefp_dot, void, env, avr, avr, avr) DEF_HELPER_4(vcmpgtfp_dot, void, env, avr, avr, avr) DEF_HELPER_4(vcmpbfp_dot, void, env, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrglb, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrglh, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrglw, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrghb, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrghh, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrghw, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGLB, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGLH, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGLW, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGHB, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGHH, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGHW, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_FLAGS_3(VMULESB, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_FLAGS_3(VMULESH, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_FLAGS_3(VMULESW, TCG_CALL_NO_RWG, void, avr, avr, avr) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 92706e2097..99f7421e77 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -795,6 +795,15 @@ VNOR 000100 ..... ..... ..... 10100000100 = @VX VXOR 000100 ..... ..... ..... 10011000100 @VX VEQV 000100 ..... ..... ..... 11010000100 @VX =20 +## Vector Merge Instructions + +VMRGHB 000100 ..... ..... ..... 00000001100 @VX +VMRGHH 000100 ..... ..... ..... 00001001100 @VX +VMRGHW 000100 ..... ..... ..... 00010001100 @VX +VMRGLB 000100 ..... ..... ..... 00100001100 @VX +VMRGLH 000100 ..... ..... ..... 00101001100 @VX +VMRGLW 000100 ..... ..... ..... 00110001100 @VX + ## Vector Integer Average Instructions =20 VAVGSB 000100 ..... ..... ..... 10100000010 @VX diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index ef4b2e75d6..a3adf746bd 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -950,7 +950,7 @@ void helper_VMLADDUHM(ppc_avr_t *r, ppc_avr_t *a, ppc_a= vr_t *b, ppc_avr_t *c, } =20 #define VMRG_DO(name, element, access, ofs) = \ - void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) = \ + void helper_V##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) = \ { = \ ppc_avr_t result; = \ int i, half =3D ARRAY_SIZE(r->element) / 2; = \ @@ -963,11 +963,11 @@ void helper_VMLADDUHM(ppc_avr_t *r, ppc_avr_t *a, ppc= _avr_t *b, ppc_avr_t *c, } =20 #define VMRG(suffix, element, access) \ - VMRG_DO(mrgl##suffix, element, access, half) \ - VMRG_DO(mrgh##suffix, element, access, 0) -VMRG(b, u8, VsrB) -VMRG(h, u16, VsrH) -VMRG(w, u32, VsrW) + VMRG_DO(MRGL##suffix, element, access, half) \ + VMRG_DO(MRGH##suffix, element, access, 0) +VMRG(B, u8, VsrB) +VMRG(H, u16, VsrH) +VMRG(W, u32, VsrW) #undef VMRG_DO #undef VMRG =20 diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 92d6e8c603..00b359f031 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -350,12 +350,25 @@ GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16); GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17); GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18); GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19); -GEN_VXFORM(vmrghb, 6, 0); -GEN_VXFORM(vmrghh, 6, 1); -GEN_VXFORM(vmrghw, 6, 2); -GEN_VXFORM(vmrglb, 6, 4); -GEN_VXFORM(vmrglh, 6, 5); -GEN_VXFORM(vmrglw, 6, 6); + +static bool do_vmrg(DisasContext *ctx, arg_VX *a, + void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr)) +{ + TCGv_ptr ra, rb, rd; + REQUIRE_VECTOR(ctx); + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + helper(rd, ra, rb); + return true; +} + +TRANS_FLAGS(ALTIVEC, VMRGHB, do_vmrg, gen_helper_VMRGHB); +TRANS_FLAGS(ALTIVEC, VMRGHH, do_vmrg, gen_helper_VMRGHH); +TRANS_FLAGS(ALTIVEC, VMRGHW, do_vmrg, gen_helper_VMRGHW); +TRANS_FLAGS(ALTIVEC, VMRGLB, do_vmrg, gen_helper_VMRGLB); +TRANS_FLAGS(ALTIVEC, VMRGLH, do_vmrg, gen_helper_VMRGLH); +TRANS_FLAGS(ALTIVEC, VMRGLW, do_vmrg, gen_helper_VMRGLW); =20 static void trans_vmrgew(DisasContext *ctx) { diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-= ops.c.inc index e28958a126..b8f77d3d2c 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -33,12 +33,6 @@ GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC= _NONE), GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300), GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300), GEN_VXFORM_300(bcds, 0, 27), -GEN_VXFORM(vmrghb, 6, 0), -GEN_VXFORM(vmrghh, 6, 1), -GEN_VXFORM(vmrghw, 6, 2), -GEN_VXFORM(vmrglb, 6, 4), -GEN_VXFORM(vmrglh, 6, 5), -GEN_VXFORM(vmrglw, 6, 6), GEN_VXFORM_300(vextublx, 6, 24), GEN_VXFORM_300(vextuhlx, 6, 25), GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207), --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837539731158500 Content-Type: text/plain; charset="utf-8" From: Aboorva Devarajan Move below instructions to decodetree specification: vpkuhum, vpkuwum, vpkuhus, vpkuwus : VX-form (PPC_ALTIVEC) vpkshus, vpkswus, vpkshss, vpkswss : VX-form (PPC_ALTIVEC) vpkpx : VX-form (PPC_ALTIVEC) vpkudum, vpkudus, vpksdus, vpksdss : VX-form (PPC2_ALTIVEC_207) The legacy GEN_VXFORM_ENV/GEN_VXFORM macros that generated gen_vpk*() functions reading register fields from ctx->opcode are replaced by new do_vpk_env()/do_vpk() helpers in vmx-impl.c.inc that use the pre-extracted decodetree argument fields (a->vrt, a->vra, a->vrb) directly. The existing gen_helper_vpk*() implementations in int_helper.c are reused without changes. The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' option before and after the patch. Signed-off-by: Aboorva Devarajan Reviewed-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/helper.h | 26 +++++++-------- target/ppc/insn32.decode | 16 +++++++++ target/ppc/int_helper.c | 28 ++++++++-------- target/ppc/translate/vmx-impl.c.inc | 51 +++++++++++++++++++++-------- target/ppc/translate/vmx-ops.c.inc | 13 -------- 5 files changed, 81 insertions(+), 53 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 5517d2950f..a0d08d6192 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -249,19 +249,19 @@ DEF_HELPER_FLAGS_4(VMSUMUBM, TCG_CALL_NO_RWG, void, a= vr, avr, avr, avr) DEF_HELPER_FLAGS_4(VMSUMMBM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) DEF_HELPER_FLAGS_4(VPERM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) DEF_HELPER_FLAGS_4(VPERMR, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) -DEF_HELPER_4(vpkshss, void, env, avr, avr, avr) -DEF_HELPER_4(vpkshus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkswss, void, env, avr, avr, avr) -DEF_HELPER_4(vpkswus, void, env, avr, avr, avr) -DEF_HELPER_4(vpksdss, void, env, avr, avr, avr) -DEF_HELPER_4(vpksdus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkuhus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkuwus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkudus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkuhum, void, env, avr, avr, avr) -DEF_HELPER_4(vpkuwum, void, env, avr, avr, avr) -DEF_HELPER_4(vpkudum, void, env, avr, avr, avr) -DEF_HELPER_FLAGS_3(vpkpx, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_4(VPKSHSS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSHUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSWSS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSWUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSDSS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSDUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUHUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUWUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUDUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUHUM, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUWUM, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUDUM, void, env, avr, avr, avr) +DEF_HELPER_FLAGS_3(VPKPX, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_5(VMHADDSHS, void, env, avr, avr, avr, avr) DEF_HELPER_5(VMHRADDSHS, void, env, avr, avr, avr, avr) DEF_HELPER_FLAGS_4(VMSUMUHM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 99f7421e77..d6f1875532 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1054,6 +1054,22 @@ VSTRIHR 000100 ..... 00011 ..... . 000000110= 1 @VX_tb_rc VCLRLB 000100 ..... ..... ..... 00110001101 @VX VCLRRB 000100 ..... ..... ..... 00111001101 @VX =20 +## Vector Pack Instructions + +VPKUHUM 000100 ..... ..... ..... 0000000111 0 @VX +VPKUWUM 000100 ..... ..... ..... 0000100111 0 @VX +VPKUDUM 000100 ..... ..... ..... 1000100111 0 @VX +VPKUHUS 000100 ..... ..... ..... 0001000111 0 @VX +VPKUWUS 000100 ..... ..... ..... 0001100111 0 @VX +VPKUDUS 000100 ..... ..... ..... 1001100111 0 @VX +VPKSHUS 000100 ..... ..... ..... 0010000111 0 @VX +VPKSWUS 000100 ..... ..... ..... 0010100111 0 @VX +VPKSDUS 000100 ..... ..... ..... 1010100111 0 @VX +VPKSHSS 000100 ..... ..... ..... 0011000111 0 @VX +VPKSWSS 000100 ..... ..... ..... 0011100111 0 @VX +VPKSDSS 000100 ..... ..... ..... 1011100111 0 @VX +VPKPX 000100 ..... ..... ..... 0110000111 0 @VX + # VSX Load/Store Instructions =20 LXSD 111001 ..... ..... .............. 10 @DS diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index a3adf746bd..dc55ccadf7 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -1465,7 +1465,7 @@ void helper_VPMSUMD(ppc_avr_t *r, ppc_avr_t *a, ppc_a= vr_t *b) #else #define PKBIG 0 #endif -void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_VPKPX(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) { int i, j; ppc_avr_t result; @@ -1488,7 +1488,7 @@ void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr= _t *b) } =20 #define VPK(suffix, from, to, cvt, dosat) \ - void helper_vpk##suffix(CPUPPCState *env, ppc_avr_t *r, \ + void helper_VPK##suffix(CPUPPCState *env, ppc_avr_t *r, \ ppc_avr_t *a, ppc_avr_t *b) \ { \ int i; \ @@ -1507,18 +1507,18 @@ void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_a= vr_t *b) } \ } #define I(x, y) (x) -VPK(shss, s16, s8, cvtshsb, 1) -VPK(shus, s16, u8, cvtshub, 1) -VPK(swss, s32, s16, cvtswsh, 1) -VPK(swus, s32, u16, cvtswuh, 1) -VPK(sdss, s64, s32, cvtsdsw, 1) -VPK(sdus, s64, u32, cvtsduw, 1) -VPK(uhus, u16, u8, cvtuhub, 1) -VPK(uwus, u32, u16, cvtuwuh, 1) -VPK(udus, u64, u32, cvtuduw, 1) -VPK(uhum, u16, u8, I, 0) -VPK(uwum, u32, u16, I, 0) -VPK(udum, u64, u32, I, 0) +VPK(SHSS, s16, s8, cvtshsb, 1) +VPK(SHUS, s16, u8, cvtshub, 1) +VPK(SWSS, s32, s16, cvtswsh, 1) +VPK(SWUS, s32, u16, cvtswuh, 1) +VPK(SDSS, s64, s32, cvtsdsw, 1) +VPK(SDUS, s64, u32, cvtsduw, 1) +VPK(UHUS, u16, u8, cvtuhub, 1) +VPK(UWUS, u32, u16, cvtuwuh, 1) +VPK(UDUS, u64, u32, cvtuduw, 1) +VPK(UHUM, u16, u8, I, 0) +VPK(UWUM, u32, u16, I, 0) +VPK(UDUM, u64, u32, I, 0) #undef I #undef VPK #undef PKBIG diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 00b359f031..65230f3461 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1070,19 +1070,44 @@ TRANS(VRLQMI, do_vector_rotl_quad, false, true) =20 GEN_VXFORM_TRANS(vsl, 2, 7); GEN_VXFORM_TRANS(vsr, 2, 11); -GEN_VXFORM_ENV(vpkuhum, 7, 0); -GEN_VXFORM_ENV(vpkuwum, 7, 1); -GEN_VXFORM_ENV(vpkudum, 7, 17); -GEN_VXFORM_ENV(vpkuhus, 7, 2); -GEN_VXFORM_ENV(vpkuwus, 7, 3); -GEN_VXFORM_ENV(vpkudus, 7, 19); -GEN_VXFORM_ENV(vpkshus, 7, 4); -GEN_VXFORM_ENV(vpkswus, 7, 5); -GEN_VXFORM_ENV(vpksdus, 7, 21); -GEN_VXFORM_ENV(vpkshss, 7, 6); -GEN_VXFORM_ENV(vpkswss, 7, 7); -GEN_VXFORM_ENV(vpksdss, 7, 23); -GEN_VXFORM(vpkpx, 7, 12); +static bool do_vpk_env(DisasContext *ctx, arg_VX *a, + void (*gen_helper)(TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_ptr)) +{ + TCGv_ptr ra, rb, rd; + REQUIRE_VECTOR(ctx); + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + gen_helper(tcg_env, rd, ra, rb); + return true; +} + +static bool do_vpk(DisasContext *ctx, arg_VX *a, + void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr)) +{ + TCGv_ptr ra, rb, rd; + REQUIRE_VECTOR(ctx); + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + gen_helper(rd, ra, rb); + return true; +} + +TRANS_FLAGS(ALTIVEC, VPKUHUM, do_vpk_env, gen_helper_VPKUHUM) +TRANS_FLAGS(ALTIVEC, VPKUWUM, do_vpk_env, gen_helper_VPKUWUM) +TRANS_FLAGS2(ALTIVEC_207, VPKUDUM, do_vpk_env, gen_helper_VPKUDUM) +TRANS_FLAGS(ALTIVEC, VPKUHUS, do_vpk_env, gen_helper_VPKUHUS) +TRANS_FLAGS(ALTIVEC, VPKUWUS, do_vpk_env, gen_helper_VPKUWUS) +TRANS_FLAGS2(ALTIVEC_207, VPKUDUS, do_vpk_env, gen_helper_VPKUDUS) +TRANS_FLAGS(ALTIVEC, VPKSHUS, do_vpk_env, gen_helper_VPKSHUS) +TRANS_FLAGS(ALTIVEC, VPKSWUS, do_vpk_env, gen_helper_VPKSWUS) +TRANS_FLAGS2(ALTIVEC_207, VPKSDUS, do_vpk_env, gen_helper_VPKSDUS) +TRANS_FLAGS(ALTIVEC, VPKSHSS, do_vpk_env, gen_helper_VPKSHSS) +TRANS_FLAGS(ALTIVEC, VPKSWSS, do_vpk_env, gen_helper_VPKSWSS) +TRANS_FLAGS2(ALTIVEC_207, VPKSDSS, do_vpk_env, gen_helper_VPKSDSS) +TRANS_FLAGS(ALTIVEC, VPKPX, do_vpk, gen_helper_VPKPX) GEN_VXFORM_ENV(vsum4ubs, 4, 24); GEN_VXFORM_ENV(vsum4sbs, 4, 28); GEN_VXFORM_ENV(vsum4shs, 4, 25); diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-= ops.c.inc index b8f77d3d2c..2820976c0f 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -59,19 +59,6 @@ GEN_VXFORM_300(bcdtrunc, 0, 20), GEN_VXFORM_300(bcdutrunc, 0, 21), GEN_VXFORM(vsl, 2, 7), GEN_VXFORM(vsr, 2, 11), -GEN_VXFORM(vpkuhum, 7, 0), -GEN_VXFORM(vpkuwum, 7, 1), -GEN_VXFORM_207(vpkudum, 7, 17), -GEN_VXFORM(vpkuhus, 7, 2), -GEN_VXFORM(vpkuwus, 7, 3), -GEN_VXFORM_207(vpkudus, 7, 19), -GEN_VXFORM(vpkshus, 7, 4), -GEN_VXFORM(vpkswus, 7, 5), -GEN_VXFORM_207(vpksdus, 7, 21), -GEN_VXFORM(vpkshss, 7, 6), -GEN_VXFORM(vpkswss, 7, 7), -GEN_VXFORM_207(vpksdss, 7, 23), -GEN_VXFORM(vpkpx, 7, 12), GEN_VXFORM(vsum4ubs, 4, 24), GEN_VXFORM(vsum4sbs, 4, 28), GEN_VXFORM(vsum4shs, 4, 25), --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837507678158501 Content-Type: text/plain; charset="utf-8" From: Utkarsh Verma Move the following store conditional instructions to decodetree specification: stbcx. : X-form sthcx. : X-form stwcx. : X-form stdcx. : X-form stqcx. : X-form The changes were verified by checking that the generated TCG ops remain semantically identical to the legacy translation, using logs captured with the -d in_asm,op flag. Signed-off-by: Utkarsh Verma Reviewed-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 8 ++ target/ppc/translate.c | 103 --------------------- target/ppc/translate/fixedpoint-impl.c.inc | 84 +++++++++++++++++ 3 files changed, 92 insertions(+), 103 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index d6f1875532..824181eb4e 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -732,6 +732,14 @@ DSCLIQ 111111 ..... ..... ...... 001000010 . = @Z22_tap_sh_rc DSCRI 111011 ..... ..... ...... 001100010 . @Z22_ta_sh_rc DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc =20 +### Store Conditional Instructions + +STBCX 011111 ..... ..... ..... 1010110110 1 @X +STHCX 011111 ..... ..... ..... 1011010110 1 @X +STWCX 011111 ..... ..... ..... 0010010110 1 @X +STDCX 011111 ..... ..... ..... 0011010110 1 @X +STQCX 011111 ..... ..... ..... 0010110110 1 @X + ## Vector Exclusive-OR-based Instructions =20 VPMSUMD 000100 ..... ..... ..... 10011001000 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4bd7f44b3c..821363e7fb 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3153,104 +3153,6 @@ static void gen_stdat(DisasContext *ctx) } #endif =20 -static void gen_conditional_store(DisasContext *ctx, MemOp memop) -{ - TCGLabel *lfail; - TCGv EA; - TCGv cr0; - TCGv t0; - int rs =3D rS(ctx->opcode); - - lfail =3D gen_new_label(); - EA =3D tcg_temp_new(); - cr0 =3D tcg_temp_new(); - t0 =3D tcg_temp_new(); - - tcg_gen_mov_tl(cr0, cpu_so); - gen_set_access_type(ctx, ACCESS_RES); - gen_addr_reg_index(ctx, EA); - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop),= lfail); - - tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, - cpu_gpr[rs], ctx->mem_idx, - DEF_MEMOP(memop) | MO_ALIGN); - tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); - tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); - tcg_gen_or_tl(cr0, cr0, t0); - - gen_set_label(lfail); - tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); - tcg_gen_movi_tl(cpu_reserve, -1); -} - -#define STCX(name, memop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - gen_conditional_store(ctx, memop); \ -} - -STCX(stbcx_, MO_UB) -STCX(sthcx_, MO_UW) -STCX(stwcx_, MO_UL) - -#if defined(TARGET_PPC64) -/* stdcx. */ -STCX(stdcx_, MO_UQ) - -/* stqcx. */ -static void gen_stqcx_(DisasContext *ctx) -{ - TCGLabel *lfail; - TCGv EA, t0, t1; - TCGv cr0; - TCGv_i128 cmp, val; - int rs =3D rS(ctx->opcode); - - if (unlikely(rs & 1)) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - - lfail =3D gen_new_label(); - EA =3D tcg_temp_new(); - cr0 =3D tcg_temp_new(); - - tcg_gen_mov_tl(cr0, cpu_so); - gen_set_access_type(ctx, ACCESS_RES); - gen_addr_reg_index(ctx, EA); - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); - - cmp =3D tcg_temp_new_i128(); - val =3D tcg_temp_new_i128(); - - tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); - - /* Note that the low part is always in RS+1, even in LE mode. */ - tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); - - tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, - DEF_MEMOP(MO_128 | MO_ALIGN)); - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - tcg_gen_extr_i128_i64(t1, t0, val); - - tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); - tcg_gen_xor_tl(t0, t0, cpu_reserve_val); - tcg_gen_or_tl(t0, t0, t1); - - tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); - tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); - tcg_gen_or_tl(cr0, cr0, t0); - - gen_set_label(lfail); - tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); - tcg_gen_movi_tl(cpu_reserve, -1); -} -#endif /* defined(TARGET_PPC64) */ - /* wait */ static void gen_wait(DisasContext *ctx) { @@ -5886,14 +5788,9 @@ GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC= _STRING), GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), #if defined(TARGET_PPC64) GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), -GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), #endif /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index fa0191e866..91f9c6c391 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -204,6 +204,90 @@ TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_UQ) TRANS64(STQ, do_ldst_quad, true, false); TRANS64(PSTQ, do_ldst_quad_PLS_D, true); =20 +/* Store Conditional Instructions */ + +static bool do_store_cond(DisasContext *ctx, arg_X *a, MemOp mop) +{ + TCGLabel *lfail =3D gen_new_label(); + TCGv ea =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + TCGv cr0 =3D tcg_temp_new(); + TCGv t0 =3D tcg_temp_new(); + + tcg_gen_mov_tl(cr0, cpu_so); + gen_set_access_type(ctx, ACCESS_RES); + + tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_reserve, lfail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(mop), l= fail); + + tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, + cpu_gpr[a->rt], ctx->mem_idx, + DEF_MEMOP(mop) | MO_ALIGN); + tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); + tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); + tcg_gen_or_tl(cr0, cr0, t0); + + gen_set_label(lfail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); + tcg_gen_movi_tl(cpu_reserve, -1); + return true; +} + +TRANS_FLAGS2(ATOMIC_ISA206, STBCX, do_store_cond, MO_UB); +TRANS_FLAGS2(ATOMIC_ISA206, STHCX, do_store_cond, MO_UW); +TRANS(STWCX, do_store_cond, MO_UL); +TRANS64(STDCX, do_store_cond, MO_UQ); + +static bool trans_STQCX(DisasContext *ctx, arg_STQCX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, LSQ_ISA207); +#if defined(TARGET_PPC64) + TCGLabel *lfail =3D gen_new_label(); + TCGv ea =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv cr0 =3D tcg_temp_new(); + TCGv_i128 cmp =3D tcg_temp_new_i128(); + TCGv_i128 val =3D tcg_temp_new_i128(); + + if (unlikely(a->rt & 1)) { + gen_invalid(ctx); + return true; + } + + tcg_gen_mov_tl(cr0, cpu_so); + gen_set_access_type(ctx, ACCESS_RES); + + tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_reserve, lfail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); + + tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); + + /* Note that the low part is always in RS+1, even in LE mode. */ + tcg_gen_concat_i64_i128(val, cpu_gpr[a->rt + 1], cpu_gpr[a->rt]); + + tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, + DEF_MEMOP(MO_128 | MO_ALIGN)); + + tcg_gen_extr_i128_i64(t1, t0, val); + + tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); + tcg_gen_xor_tl(t0, t0, cpu_reserve_val); + tcg_gen_or_tl(t0, t0, t1); + + tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); + tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); + tcg_gen_or_tl(cr0, cr0, t0); + + gen_set_label(lfail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); + tcg_gen_movi_tl(cpu_reserve, -1); +#else + qemu_build_not_reached(); +#endif + return true; +} + /* * Fixed-Point Compare Instructions */ --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787837513; cv=none; d=zohomail.com; s=zohoarc; b=gDmOeQvZIGzCx4SNEE3O1TR7hKQmQNPj4iEmiM53aEyMBkg8sUi65hlNkF6R3dzp896Kc9/Ku76bVQRA+MVmHGbhs0P5Kw9aO5kXPniTBB1qr/b5NDZsmmifCt4cWycW8rwXx/x6q2188yl26N01uVyL14Tj7doFOlSlkP+c3Xk= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=+5ZhhOqGb9NvPDgHx xJYElEytBq65TwPR/bPwJbQzbs=; b=H0jq4tp6j/S4WJrdWNfxVrdeea472ggAD e09WytJapsiKl7m8QQ+Vd7OJ2A1Ml1o3pixe80mB05puJIiY40mO+sB6ZVqY+/9C SyyaNO5NiqDaXH9NhYrBB0+rbz82pcGVALrRBL4MYtgTQbuj41zW9d2g61cOMEp3 5yhQ5dSedcLX9IrtLFGAnyk2PzSsrhW5PDL6nZRM4t0B2rX4HrN7mqzE5IuolLdy T4XzZSkbb8KumN3POiJYd4Z1bZe0b+W7fZuVgeww9Jg1sazM+M+qsSd87DAVVeeN mkKL/7I+OPNQJD7OxFphIj5DqZy2YOH1w1UZob/ZZXtWmxHHogCOw== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 07/37] target/ppc: convert slw, srw instruction via decode spec Date: Thu, 27 Aug 2026 18:59:22 +0530 Message-ID: <20260827133010.278889-8-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX9ek2wy0N8zAN Iud2awSkEH+3FlkqA7XNpBHteP0IB0sOuwtZZcZd+Qv25fGkAKn7BzfgZocq6WbrsEGo864bMi8 rrbjoltRC+H/T572rN3wR2ICtN2Dtic= X-Authority-Analysis: v=2.4 cv=AYuB2XXG c=1 sm=1 tr=0 ts=6a903c29 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=pGLkceISAAAA:8 a=VnNF1IyMAAAA:8 a=Fp1rp7siH0uluUpQqjEA:9 X-Proofpoint-ORIG-GUID: _sTma-nBu1lb4RgKVAinRnZz_UqAcR33 X-Proofpoint-GUID: wrAvtQHKYCPnSQn0Dz-sOtEUNObiyzia X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX0DroanAPr0Bh x8A4AASVpuPk6EH/Vo3xjqqB4rPCiOxtALr4xFvx+Kmoo4XSWu7X0GqnZmIHPX1olU3J8dFF1pG gq0cNec5i6pkrm0tAg9g0k6mFTFajCmpN7B+bjb8h8RqKInrr+10JG0cKfCRTI3P5aCuNqbVSf/ OsCLXuyLMAojfA6HqivWK4AUOEiuJKFzZnRbbJV9njI3lCtEqCe2MQA6B8SLopH4Ne+isMmmILL QGYM7UeXRPgflW8j6TkY5YVpw7TTFGINfXFJ96MUn4w7NS5gqLZ+RRKjDHffXgTiu/WWMoleOSl Ql4prrwVxDfNvSBN/U3/H4oLT9+z8gZGq3M2xDytRJeVunIQcaFpGhUQMu9+WD/8JAVWvv1q2In D7bEMVGlzO7rjSYznBMSKqVlU4lFfgPKiNeQAIIgWN6v9761/f8sITNWiyrJSsN7jyb7tenDTGd R6YQVnKOfXrGCthgxSg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837513615158500 Content-Type: text/plain; charset="utf-8" From: "Mukesh Kumar Chaurasiya (IBM)" Move slw and srw to decodetree specification using the @X_rc format. The existing shift-masking logic from gen_slw/gen_srw is preserved verbatim in the new trans_SLW/trans_SRW handlers. Signed-off-by: Mukesh Kumar Chaurasiya (IBM) Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 5 +++ target/ppc/translate.c | 49 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 48 +++++++++++++++++++++ 3 files changed, 53 insertions(+), 49 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 824181eb4e..189f9c6fe7 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -505,6 +505,11 @@ HASHCHK 011111 ..... ..... ..... 1011110010 . = @X_DW HASHSTP 011111 ..... ..... ..... 1010010010 . @X_DW HASHCHKP 011111 ..... ..... ..... 1010110010 . @X_DW =20 +# Fixed-Point Shift Instructions + +SLW 011111 ..... ..... ..... 0000011000 . @X_rc +SRW 011111 ..... ..... ..... 1000011000 . @X_rc + ## BCD Assist =20 ADDG6S 011111 ..... ..... ..... - 001001010 - @X diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 821363e7fb..3d26e1144e 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2315,29 +2315,6 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06); =20 /*** Integer shift = ***/ =20 -/* slw & slw. */ -static void gen_slw(DisasContext *ctx) -{ - TCGv t0, t1; - - t0 =3D tcg_temp_new(); - /* AND rS with a mask that is 0 when rB >=3D 0x20 */ -#if defined(TARGET_PPC64) - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); - tcg_gen_sari_tl(t0, t0, 0x3f); -#else - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); - tcg_gen_sari_tl(t0, t0, 0x1f); -#endif - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); - t1 =3D tcg_temp_new(); - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); - tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} =20 /* sraw & sraw. */ static void gen_sraw(DisasContext *ctx) @@ -2379,30 +2356,6 @@ static void gen_srawi(DisasContext *ctx) } } =20 -/* srw & srw. */ -static void gen_srw(DisasContext *ctx) -{ - TCGv t0, t1; - - t0 =3D tcg_temp_new(); - /* AND rS with a mask that is 0 when rB >=3D 0x20 */ -#if defined(TARGET_PPC64) - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); - tcg_gen_sari_tl(t0, t0, 0x3f); -#else - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); - tcg_gen_sari_tl(t0, t0, 0x1f); -#endif - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); - tcg_gen_ext32u_tl(t0, t0); - t1 =3D tcg_temp_new(); - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); - tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} - #if defined(TARGET_PPC64) /* sld & sld. */ static void gen_sld(DisasContext *ctx) @@ -5764,10 +5717,8 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, P= PC_NONE, PPC2_ISA300), GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), -GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), #if defined(TARGET_PPC64) GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 91f9c6c391..9d04b96316 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1406,3 +1406,51 @@ TRANS(HASHST, do_hash, false, gen_helper_HASHST) TRANS(HASHCHK, do_hash, false, gen_helper_HASHCHK) TRANS(HASHSTP, do_hash, true, gen_helper_HASHSTP) TRANS(HASHCHKP, do_hash, true, gen_helper_HASHCHKP) + +static bool trans_SLW(DisasContext *ctx, arg_SLW *a) +{ + TCGv t0, t1; + + t0 =3D tcg_temp_new(); + /* AND rt with a mask that is 0 when rB >=3D 0x20 */ +#if defined(TARGET_PPC64) + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x3a); + tcg_gen_sari_tl(t0, t0, 0x3f); +#else + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x1a); + tcg_gen_sari_tl(t0, t0, 0x1f); +#endif + tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0); + t1 =3D tcg_temp_new(); + tcg_gen_andi_tl(t1, cpu_gpr[a->rb], 0x1f); + tcg_gen_shl_tl(cpu_gpr[a->ra], t0, t1); + tcg_gen_ext32u_tl(cpu_gpr[a->ra], cpu_gpr[a->ra]); + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } + return true; +} + +static bool trans_SRW(DisasContext *ctx, arg_SRW *a) +{ + TCGv t0, t1; + + t0 =3D tcg_temp_new(); + /* AND rt with a mask that is 0 when rB >=3D 0x20 */ +#if defined(TARGET_PPC64) + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x3a); + tcg_gen_sari_tl(t0, t0, 0x3f); +#else + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x1a); + tcg_gen_sari_tl(t0, t0, 0x1f); +#endif + tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0); + tcg_gen_ext32u_tl(t0, t0); + t1 =3D tcg_temp_new(); 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b=Tde5q+PaT/qZ1RNzdDDfFEDSvx1n/OAfr ehXwehPXi4VTNVfEB4F+JEoRlDeE8mSdVewhH+Z221nu+cVG/+bxr1MRr686vQdF s83UoIie5MGYejfujeYW/NABy33s/JM50jPzAXJdD266nnDVpbpRG16R9dhF31xh EItljcmLf0/ht+jD+8X28mqcJuCl+3Ws++hdS1y6+BmSN/gY1humL132KAbaUE8n iL5Goij94leIyuPXGkTFurNH2YNDJeTsS1Iljft860t9EDW/v3nzHwDjJkFD3F1x i/+mvXutFYcm333qGG6O+BsL0CKeluksrayBWF4N5L/F2St+/75Sw== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 08/37] target/ppc: convert sraw[i] instruction via decode spec Date: Thu, 27 Aug 2026 18:59:23 +0530 Message-ID: <20260827133010.278889-9-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX1OnoZaOhwtMf SSUZgKZuWVQZGlIIA28HhjD3oaw0FFSpoarGfbbyMU32/XUyxd67YgtRhy5+zkogbtfI/+1EOXQ K+6KdZF1VO1KaK+WP2+xzrqPM1dyOvE= X-Authority-Analysis: v=2.4 cv=AYuB2XXG c=1 sm=1 tr=0 ts=6a903c2f cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=pGLkceISAAAA:8 a=VnNF1IyMAAAA:8 a=gSLKyiytl6aLGSs9OJQA:9 X-Proofpoint-ORIG-GUID: pJQlU7Bsego_PIChIFNXslVPU0-i3wbo X-Proofpoint-GUID: NK7B7KG6m77q_GZnwty5qySfhO5XSftn X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfXyTLxQVF/ojOk GCiM/sOwbxgIDGZrmYUq+uuHv24Rj9sQ6rdRjhMVPnU+t/RgTCQkGz+kAi5aY9Usuk4J6ZwrvPW meKS+SJ1v6NoSEoqDDlRVAKeaLstZ9NnYMYJ3bnm1TS6ltunHm23hayEwmfFqrjOmbzfMcRRIpt KmTes15f0nyMFYKTHrDbbH8LulnupNv9yWcw7BR1O8i8EC0m1jYLBVKLqeoVYoYgXg/a/6alFJk tahzMflTWW+ggtVB87QvrcmCYj9ODKp4nLwIezyv8WdPnddJl2oELKhyVRsSLpmqa4yWdpfisjS BRMHGmhJdUnXTPvLiN4rcP14Jhp0gaAxVIE26keMY3/W6FADjiCeCYVz5CfZr+29jCRlsqivkLY +1xKMep7/zEJXsbky6aJhQrLuzyFmSqgnknSHK6fvwlh4XPfxZOgWjxwV9jF6jvHBQLzl1UMU0W /eSXkKT7YwI5f4n5aZQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837527737158500 Content-Type: text/plain; charset="utf-8" From: "Mukesh Kumar Chaurasiya (IBM)" Move sraw and srawi to decodetree specification using the @X_rc format. The existing shift-masking logic from gen_sraw/gen_srawi is preserved verbatim in the new trans_SRAW/trans_SRAWI handlers. Signed-off-by: Mukesh Kumar Chaurasiya (IBM) Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/helper.h | 2 +- target/ppc/insn32.decode | 2 ++ target/ppc/int_helper.c | 2 +- target/ppc/translate.c | 42 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 41 +++++++++++++++++++++ 5 files changed, 45 insertions(+), 44 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index a0d08d6192..d4a9334ce8 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -64,7 +64,7 @@ DEF_HELPER_4(DIVWE, tl, env, tl, tl, i32) =20 DEF_HELPER_FLAGS_1(POPCNTB, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(CMPB, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_3(sraw, tl, env, tl, tl) +DEF_HELPER_3(SRAW, tl, env, tl, tl) DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 189f9c6fe7..ef0fe12959 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -509,6 +509,8 @@ HASHCHKP 011111 ..... ..... ..... 1010110010 . = @X_DW =20 SLW 011111 ..... ..... ..... 0000011000 . @X_rc SRW 011111 ..... ..... ..... 1000011000 . @X_rc +SRAW 011111 ..... ..... ..... 1100011000 . @X_rc +SRAWI 011111 ..... ..... ..... 1100111000 . @X_rc =20 ## BCD Assist =20 diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index dc55ccadf7..b161f930ec 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -235,7 +235,7 @@ target_ulong helper_CMPB(target_ulong rs, target_ulong = rb) } =20 /* shift right arithmetic helper */ -target_ulong helper_sraw(CPUPPCState *env, target_ulong value, +target_ulong helper_SRAW(CPUPPCState *env, target_ulong value, target_ulong shift) { int32_t ret; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3d26e1144e..53acd54ad4 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2316,46 +2316,6 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06); /*** Integer shift = ***/ =20 =20 -/* sraw & sraw. */ -static void gen_sraw(DisasContext *ctx) -{ - gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env, - cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} - -/* srawi & srawi. */ -static void gen_srawi(DisasContext *ctx) -{ - int sh =3D SH(ctx->opcode); - TCGv dst =3D cpu_gpr[rA(ctx->opcode)]; - TCGv src =3D cpu_gpr[rS(ctx->opcode)]; - if (sh =3D=3D 0) { - tcg_gen_ext32s_tl(dst, src); - tcg_gen_movi_tl(cpu_ca, 0); - if (is_isa300(ctx)) { - tcg_gen_movi_tl(cpu_ca32, 0); - } - } else { - TCGv t0; - tcg_gen_ext32s_tl(dst, src); - tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); - t0 =3D tcg_temp_new(); - tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); - tcg_gen_and_tl(cpu_ca, cpu_ca, t0); - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); - if (is_isa300(ctx)) { - tcg_gen_mov_tl(cpu_ca32, cpu_ca); - } - tcg_gen_sari_tl(dst, dst, sh); - } - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, dst); - } -} - #if defined(TARGET_PPC64) /* sld & sld. */ static void gen_sld(DisasContext *ctx) @@ -5717,8 +5677,6 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PP= C_NONE, PPC2_ISA300), GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), -GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), #if defined(TARGET_PPC64) GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 9d04b96316..234404e459 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1454,3 +1454,44 @@ static bool trans_SRW(DisasContext *ctx, arg_SRW *a) } return true; } + +/* sraw & sraw. */ +static bool trans_SRAW(DisasContext *ctx, arg_SRAW *a) +{ + gen_helper_SRAW(cpu_gpr[a->ra], tcg_env, + cpu_gpr[a->rt], cpu_gpr[a->rb]); + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } + return true; +} + +/* srawi & srawi. */ +static bool trans_SRAWI(DisasContext *ctx, arg_SRAWI *a) +{ + TCGv dst =3D cpu_gpr[a->ra]; + TCGv src =3D cpu_gpr[a->rt]; + if (a->rb =3D=3D 0) { + tcg_gen_ext32s_tl(dst, src); + tcg_gen_movi_tl(cpu_ca, 0); + if (is_isa300(ctx)) { + tcg_gen_movi_tl(cpu_ca32, 0); + } + } else { + TCGv t0; + tcg_gen_ext32s_tl(dst, src); + tcg_gen_andi_tl(cpu_ca, dst, (1ULL << a->rb) - 1); + t0 =3D tcg_temp_new(); + tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); + tcg_gen_and_tl(cpu_ca, cpu_ca, t0); + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); + if (is_isa300(ctx)) { + tcg_gen_mov_tl(cpu_ca32, cpu_ca); + } + tcg_gen_sari_tl(dst, dst, a->rb); + } + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, dst); + } + return true; +} --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 27 Aug 2026 13:31:29 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4E5E02004D; Thu, 27 Aug 2026 13:31:23 +0000 (GMT) Received: from li-18a0a34c-33fc-11b2-a85c-d9f1631c5692.ibm.com (unknown [9.111.12.1]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 27 Aug 2026 13:31:23 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=0K04v8Hp+0A2+sNAB 1lXbKW+qEnZWajGEgqWuGnLC5k=; b=VBc3E16sRDiaya020kMjzs1qa9OP9u1cK jruv4M/LuNi3rj/MK1o8Z1VuRuT6/hKwNBYZHW5qmoX7t7QdM1J9nz7ntmZEaCZT oEX8Syy/Tzmfg5eLqDdodsAj8YcJJpaAlT//GWkg/474JqKJiNEBZHxjL3F/QoU4 xZZmy53lDOjX0IFkhjNFow+th6kfWM8cIJcvHo+4Eb1NMErthJyKOpGTEAzcn9R+ wS9C8Kb3oufQ1S17ENxzKPIsJnGPPQwrsaGIU0WU4ss4TN+EEVWDAGwtshJAw9Gd baIi1X1+HlynIkW+I9z+xaJ2wfy5XUi+WuThEPy7n0QWJh4CQ4khw== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 09/37] target/ppc: Convert mcrf to decode tree Date: Thu, 27 Aug 2026 18:59:24 +0530 Message-ID: <20260827133010.278889-10-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfXxzVW//1krhb3 xnodZ2+xyiuNaoxfGmXDGeoXQa0rjrOp8xQxYDQavO0vV1lOF0FnvGllgxRYDwskf9zYH3SV9IE VunIKyVSDwWR1uP8EDkel/jSITNODgw= X-Authority-Analysis: v=2.4 cv=AYuB2XXG c=1 sm=1 tr=0 ts=6a903c37 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=vy6McjWATDkKsZsaVXEA:9 X-Proofpoint-ORIG-GUID: hhYFROW73PQwy6VOXA_au4fxYVCcFXXd X-Proofpoint-GUID: Db3Zpjm0VATJ6P9RuXhLsHxpvCenxftf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX/Dp03IhnPzDZ iXjZivSx0FMIA8j61l2vozQjO+pW82rvYKj68eVYoYPSEqXpy8+1LAdwbnczZ5cxu7WFl1dSoUn q/qo1Wo1oPWSoLyXlYpgJDFgrtkcJkHhcaFadYlfyNTJPet/qKiB77pU9wjhA1J6g964ZDKNYgs fcc2U8+/+H/3qyQftkiAFnLZYfvNcQtGryjurV1l4TOqrYcfirOGk3VxleM7+E4kRfox/JR3YXH mMZTEo2tql0XrVvp2Chp2mO8EvJHHnqQpVRvdyktJUSYSfQeKCdJd14zMaormHuoZHA3yd1G+EW H2UTDZ4LvoV/kACOJd7KOPI/3rrsMKwiw+ce5ODR/RkJ4x3/0HNAyrxTzjju4Uey52J9ozG68k/ 1hTT0CSiqmbtMlFbNIVSf+ge6R8bxbGsER16KvQkerdVEDyWqyJabZBYKalH2OGn4OKLRZcX6SJ ojUrKlQvpoMbZR418cw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837537736158500 Content-Type: text/plain; charset="utf-8" From: Shivani Nittor Convert mcrf to decode tree specification. The functionality was tested by comparing the qemu -D log -d op,in_asm output as well as single stepping gdb. Signed-off-by: Shivani Nittor Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 6 ++++++ target/ppc/translate.c | 7 ------- target/ppc/translate/misc-impl.c.inc | 6 ++++++ 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index ef0fe12959..f928cd6602 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1452,6 +1452,12 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 - SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync EIEIO 011111 ----- ----- ----- 1101010110 - =20 +# Condition Register Field Instruction + +&XL_bfa bf bfa +@XL_bfa ...... bf:3 .. bfa:3 .. ..... ..... ..... . +MCRF 010011 ... -- ... -- ----- 00000 00000 - @XL_bfa + # Branch History Rolling Buffer (BHRB) Instructions =20 &XFX_bhrbe rt bhrbe diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 53acd54ad4..7e7ef4e32d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3642,12 +3642,6 @@ GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); /* crxor */ GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); =20 -/* mcrf */ -static void gen_mcrf(DisasContext *ctx) -{ - tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]= ); -} - /*** System linkage = ***/ =20 /* rfi (supervisor only) */ @@ -5709,7 +5703,6 @@ GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLO= W), GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_IS= A207), -GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), diff --git a/target/ppc/translate/misc-impl.c.inc b/target/ppc/translate/mi= sc-impl.c.inc index cbf82b1ea0..890fbb209e 100644 --- a/target/ppc/translate/misc-impl.c.inc +++ b/target/ppc/translate/misc-impl.c.inc @@ -155,3 +155,9 @@ static bool trans_ATTN(DisasContext *ctx, arg_ATTN *a) return false; #endif } + +static bool trans_MCRF(DisasContext *ctx, arg_MCRF *a) +{ + tcg_gen_mov_i32(cpu_crf[a->bf], cpu_crf[a->bfa]); + return true; +} --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787837617; cv=none; d=zohomail.com; s=zohoarc; b=Z4DyB7r5kk8XjaGDReMr7Nc4QRp2iW+cpj0bEnA77YaiMHJWhm+y3V92OKNiZeGtVKI4OyWqFGd3koGGwr5O7QSBRToWQ3uCRE5U5EkpSUXmWczutvbA01y/PSLNXaCN+UrYk52DM1j7BHogZ2uMaB3SLaBqB5VNF6Z1JH/0wJk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787837617; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837618360158500 Content-Type: text/plain; charset="utf-8" From: Amit Machhiwal Move the below instructions to decodetree specification: s{r,l}d, and srad[i] : X-form The changes were verified by validating that the TCG ops generated by these instructions remain the same after these changes. The TCG micro-ops were captured with the '-d op,in_asm' QEMU flag. Move all shift insntructions to one place in insn32.decode Signed-off-by: Sathvika Vasireddy Signed-off-by: Amit Machhiwal Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/helper.h | 2 +- target/ppc/insn32.decode | 12 ++- target/ppc/int_helper.c | 2 +- target/ppc/translate.c | 96 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 72 ++++++++++++++++ 5 files changed, 82 insertions(+), 102 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index d4a9334ce8..e7bf43bf4b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -74,7 +74,7 @@ DEF_HELPER_FLAGS_1(CBCDTD, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(CMPEQB, TCG_CALL_NO_RWG_SE, i32, tl, tl) DEF_HELPER_FLAGS_1(POPCNTW, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(BPERMD, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_3(srad, tl, env, tl, tl) +DEF_HELPER_3(SRAD, tl, env, tl, tl) DEF_HELPER_FLAGS_0(DARN32, TCG_CALL_NO_RWG, tl) DEF_HELPER_FLAGS_0(DARN64, TCG_CALL_NO_RWG, tl) #endif diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index f928cd6602..12fb4974e4 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -119,7 +119,7 @@ =20 # XS-form with fractured shift amount %xs_sh 1:1 11:5 -&XS rs ra sh rc +&XS rs ra sh rc:bool @XS ...... rs:5 ra:5 ..... ......... . rc:1 &XS sh=3D%= xs_sh =20 %x_frtp 22:4 !function=3Dtimes_2 @@ -512,6 +512,13 @@ SRW 011111 ..... ..... ..... 1000011000 . = @X_rc SRAW 011111 ..... ..... ..... 1100011000 . @X_rc SRAWI 011111 ..... ..... ..... 1100111000 . @X_rc =20 +SLD 011111 ..... ..... ..... 0000011011 . @X_rc +SRD 011111 ..... ..... ..... 1000011011 . @X_rc +SRAD 011111 ..... ..... ..... 1100011010 . @X_rc +SRADI 011111 ..... ..... ..... 110011101 . . @XS + +EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS + ## BCD Assist =20 ADDG6S 011111 ..... ..... ..... - 001001010 - @X @@ -1379,9 +1386,6 @@ DST 011111 ----- ..... ..... 0101010110 -= @X_ea DSTST 011111 ----- ..... ..... 0101110110 - @X_ea DSS 011111 ----- ..... ..... 1100110110 - @X_ea =20 -##Extend Sign Word and Shift Left Immediate XS-form -EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS - ## Load and Reserve Instructions LBARX 011111 ..... ..... ..... 0000110100 . @X_rc LHARX 011111 ..... ..... ..... 0001110100 . @X_rc diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index b161f930ec..8e8076a92c 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -261,7 +261,7 @@ target_ulong helper_SRAW(CPUPPCState *env, target_ulong= value, } =20 #if defined(TARGET_PPC64) -target_ulong helper_srad(CPUPPCState *env, target_ulong value, +target_ulong helper_SRAD(CPUPPCState *env, target_ulong value, target_ulong shift) { int64_t ret; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7e7ef4e32d..45418b4de5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2313,95 +2313,6 @@ static void gen_rldimi(DisasContext *ctx, int mbn, i= nt shn) GEN_PPC64_R4(rldimi, 0x1E, 0x06); #endif =20 -/*** Integer shift = ***/ - - -#if defined(TARGET_PPC64) -/* sld & sld. */ -static void gen_sld(DisasContext *ctx) -{ - TCGv t0, t1; - - t0 =3D tcg_temp_new(); - /* AND rS with a mask that is 0 when rB >=3D 0x40 */ - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); - tcg_gen_sari_tl(t0, t0, 0x3f); - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); - t1 =3D tcg_temp_new(); - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); - tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} - -/* srad & srad. */ -static void gen_srad(DisasContext *ctx) -{ - gen_helper_srad(cpu_gpr[rA(ctx->opcode)], tcg_env, - cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} -/* sradi & sradi. */ -static inline void gen_sradi(DisasContext *ctx, int n) -{ - int sh =3D SH(ctx->opcode) + (n << 5); - TCGv dst =3D cpu_gpr[rA(ctx->opcode)]; - TCGv src =3D cpu_gpr[rS(ctx->opcode)]; - if (sh =3D=3D 0) { - tcg_gen_mov_tl(dst, src); - tcg_gen_movi_tl(cpu_ca, 0); - if (is_isa300(ctx)) { - tcg_gen_movi_tl(cpu_ca32, 0); - } - } else { - TCGv t0; - tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); - t0 =3D tcg_temp_new(); - tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); - tcg_gen_and_tl(cpu_ca, cpu_ca, t0); - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); - if (is_isa300(ctx)) { - tcg_gen_mov_tl(cpu_ca32, cpu_ca); - } - tcg_gen_sari_tl(dst, src, sh); - } - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, dst); - } -} - -static void gen_sradi0(DisasContext *ctx) -{ - gen_sradi(ctx, 0); -} - -static void gen_sradi1(DisasContext *ctx) -{ - gen_sradi(ctx, 1); -} - -/* srd & srd. */ -static void gen_srd(DisasContext *ctx) -{ - TCGv t0, t1; - - t0 =3D tcg_temp_new(); - /* AND rS with a mask that is 0 when rB >=3D 0x40 */ - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); - tcg_gen_sari_tl(t0, t0, 0x3f); - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); - t1 =3D tcg_temp_new(); - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); - tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} -#endif - /*** Addressing modes = ***/ /* Register indirect with immediate index : EA =3D (rA|0) + SIMM */ static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, @@ -5671,13 +5582,6 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, P= PC_NONE, PPC2_ISA300), GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -#if defined(TARGET_PPC64) -GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), -GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), -GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), -GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), -GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), -#endif /* handles lfdp, lxsd, lxssp */ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), /* handles stfdp, stxsd, stxssp */ diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 234404e459..9f669894a3 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -486,6 +486,76 @@ static bool do_add_const_XO(DisasContext *ctx, arg_XO_= ta *a, TCGv const_val, return true; } =20 +static bool do_shift_X_rc(DisasContext *ctx, arg_X_rc *a, + void(*op)(TCGv, TCGv, TCGv)) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + /* AND rt with a mask that is 0 when rb >=3D 0x40 */ + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x39); + tcg_gen_sari_tl(t0, t0, 0x3f); + tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0); + tcg_gen_andi_tl(t1, cpu_gpr[a->rb], 0x3f); + op(cpu_gpr[a->ra], t0, t1); + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_SRAD(DisasContext *ctx, arg_SRAD *a) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + gen_helper_SRAD(cpu_gpr[a->ra], tcg_env, cpu_gpr[a->rt], cpu_gpr[a->rb= ]); + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_SRADI(DisasContext *ctx, arg_SRADI *a) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + int sh =3D a->sh; + TCGv dst =3D cpu_gpr[a->ra]; + TCGv src =3D cpu_gpr[a->rs]; + if (sh =3D=3D 0) { + tcg_gen_mov_tl(dst, src); + tcg_gen_movi_tl(cpu_ca, 0); + if (is_isa300(ctx)) { + tcg_gen_movi_tl(cpu_ca32, 0); + } + } else { + TCGv t0 =3D tcg_temp_new(); + tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); + tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); + tcg_gen_and_tl(cpu_ca, cpu_ca, t0); + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); + if (is_isa300(ctx)) { + tcg_gen_mov_tl(cpu_ca32, cpu_ca); + } + tcg_gen_sari_tl(dst, src, sh); + } + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, dst); + } +#else + qemu_build_not_reached(); +#endif + return true; +} + TRANS(ADD, do_add_XO, false, false); TRANS(ADDC, do_add_XO, false, true); TRANS(ADDE, do_add_XO, true, true); @@ -493,6 +563,8 @@ TRANS(ADDME, do_add_const_XO, tcg_constant_tl(-1LL), tr= ue, true); TRANS(ADDZE, do_add_const_XO, tcg_constant_tl(0), true, true); TRANS(ADDIC, do_add_D, false, true, false, false); TRANS(ADDIC_, do_add_D, false, true, false, true); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837519661158501 Content-Type: text/plain; charset="utf-8" From: Amit Machhiwal Move the below PPC instructions to decodetree specification: st{d,h,w}brx, st{d,w,h,b}cix : X-form The changes were verified by validating that the TCG micro-ops generated by those insns remain the same. These TCG micro-ops were captured with the `-d op,in_asm` QEMU flag. Additionally, remove GEN_STX and GEN_STX_E macros as they are no longer used anywhere else. Signed-off-by: Amit Machhiwal Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 8 +++ target/ppc/translate.c | 52 +++----------- target/ppc/translate/fixedpoint-impl.c.inc | 79 ++++++++++++++++++++++ 3 files changed, 95 insertions(+), 44 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 12fb4974e4..37f508a5c2 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -372,6 +372,14 @@ STVDX 011111 ..... ..... ..... 0010010001 - = @X STSKU 111110 ..... ..... ............. 0 11 @DD STCXU 111110 ..... ..... ............. 1 11 @DD =20 +STDBRX 011111 ..... ..... ..... 1010010100 - @X +STDCIX 011111 ..... ..... ..... 1111110101 - @X +STWCIX 011111 ..... ..... ..... 1110010101 - @X +STHCIX 011111 ..... ..... ..... 1110110101 - @X +STBCIX 011111 ..... ..... ..... 1111010101 - @X +STHBRX 011111 ..... ..... ..... 1110010110 - @X +STWBRX 011111 ..... ..... ..... 1010010110 - @X + ### Fixed-Point Compare Instructions =20 CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 45418b4de5..749ae56cdf 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2529,23 +2529,6 @@ GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) #endif =20 -/*** Integer store = ***/ -#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) = \ -static void glue(gen_, name##x)(DisasContext *ctx) = \ -{ = \ - TCGv EA; = \ - chk(ctx); = \ - gen_set_access_type(ctx, ACCESS_INT); = \ - EA =3D tcg_temp_new(); = \ - gen_addr_reg_index(ctx, EA); = \ - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); = \ -} -#define GEN_STX(name, stop, opc2, opc3, type) = \ - GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) - -#define GEN_STX_HVRM(name, stop, opc2, opc3, type) = \ - GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) - #define GEN_STEPX(name, stop, opc2, opc3) = \ static void glue(gen_, name##epx)(DisasContext *ctx) = \ { = \ @@ -2565,12 +2548,6 @@ GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) #endif =20 -#if defined(TARGET_PPC64) -GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) -GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) -GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) -GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) -#endif /*** Integer load and store with byte reverse = ***/ =20 /* lhbrx */ @@ -2582,15 +2559,8 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); #if defined(TARGET_PPC64) /* ldbrx */ GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); -/* stdbrx */ -GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); #endif /* TARGET_PPC64 */ =20 -/* sthbrx */ -GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); -/* stwbrx */ -GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); - /*** Integer load and store multiple = ***/ =20 /* lmw */ @@ -5147,9 +5117,17 @@ static int64_t dw_compose_ea(DisasContext *ctx, int = x) return true; \ } \ } while (0) +#define REQUIRE_HVRM(CTX) \ + do { \ + if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ + gen_priv_opc(CTX); \ + return true; \ + } \ + } while (0) #else #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) +#define REQUIRE_HVRM(CTX) do { gen_priv_opc(CTX); return true; } while (0) #endif =20 /* @@ -5756,20 +5734,6 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) #endif =20 -#undef GEN_STX_E -#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) = \ -GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), - -#if defined(TARGET_PPC64) -GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) -GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) -GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) -GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) -GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) -#endif -GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) -GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) - #undef GEN_STEPX #define GEN_STEPX(name, ldop, opc2, opc3) = \ GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, = \ diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 9f669894a3..25a60d3d3a 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -566,6 +566,85 @@ TRANS(ADDIC_, do_add_D, false, true, false, true); TRANS(SLD, do_shift_X_rc, tcg_gen_shl_tl); TRANS(SRD, do_shift_X_rc, tcg_gen_shr_tl); =20 +static bool do_stxx(DisasContext *ctx, arg_X *a, + void(*op)(DisasContext *, TCGv, TCGv), bool is_hvrm) +{ + TCGv ea; + + if (is_hvrm) { + REQUIRE_HVRM(ctx); + } + + gen_set_access_type(ctx, ACCESS_INT); + ea =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + op(ctx, cpu_gpr[a->rt], ea); + + return true; +} + +TRANS(STHBRX, do_stxx, gen_qemu_st16r, 0); +TRANS(STWBRX, do_stxx, gen_qemu_st32r, 0); + +static bool trans_STDBRX(DisasContext *ctx, arg_STDBRX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, DBRX); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st64r_i64, false); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STDCIX(DisasContext *ctx, arg_STDCIX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, CILDST); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st64_i64, true); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STWCIX(DisasContext *ctx, arg_STWCIX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, CILDST); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st32, true); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STHCIX(DisasContext *ctx, arg_STHCIX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, CILDST); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st16, true); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STBCIX(DisasContext *ctx, arg_STBCIX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, CILDST); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st8, true); +#else + qemu_build_not_reached(); +#endif + return true; +} + static bool trans_SUBFIC(DisasContext *ctx, arg_D *a) { gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837570012158500 Content-Type: text/plain; charset="utf-8" From: Aboorva Devarajan Move below instructions to decodetree specification: lwat, stwat : X-form (word atomic, ISA 3.0) ldat, stdat : X-form (doubleword atomic, ISA 3.0) The legacy gen_ld_atomic()/gen_st_atomic() functions that read register fields and the function code from ctx->opcode are replaced by new do_ld_atomic()/do_st_atomic() helpers in fixedpoint-impl.c.inc that use the pre-extracted decodetree argument fields (a->rt, a->ra, a->rb) directly. The RB field carries the Function Code (FC) selecting the atomic operation. gen_fetch_inc_conditional() is similarly moved and refactored to accept the destination register number as an explicit parameter instead of extracting it from ctx->opcode. Checked with '-d in_asm,op'. The printed TCG ops may differ from the pre-refactor log because EA now uses do_ea_calc(ctx, ra, 0), which lowers as GPR[ra] + 0 (then narrow in 32-bit mode) instead of mov/ext32u from ra alone. Signed-off-by: Aboorva Devarajan Reviewed-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 7 + target/ppc/translate.c | 212 -------------------- target/ppc/translate/fixedpoint-impl.c.inc | 214 +++++++++++++++++++++ 3 files changed, 221 insertions(+), 212 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 37f508a5c2..e8326a9d0b 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -343,6 +343,13 @@ LSKU 111010 ..... ..... ............. 0 11 = @DD LCXU 111010 ..... ..... ............. 1 11 @DD =20 =20 +### Fixed-Point Atomic Load/Store Instructions + +LWAT 011111 ..... ..... ..... 1001000110 - @X +STWAT 011111 ..... ..... ..... 1011000110 - @X +LDAT 011111 ..... ..... ..... 1001100110 - @X +STDAT 011111 ..... ..... ..... 1011100110 - @X + ### Fixed-Point Store Instructions =20 STB 100110 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 749ae56cdf..c44cffb5e8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2741,212 +2741,6 @@ static void gen_isync(DisasContext *ctx) ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } =20 -static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, - TCGv EA, TCGCond cond, int addend) -{ - TCGv t =3D tcg_temp_new(); - TCGv t2 =3D tcg_temp_new(); - TCGv u =3D tcg_temp_new(); - - tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); - tcg_gen_addi_tl(t2, EA, memop_size(memop)); - tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); - tcg_gen_addi_tl(u, t, addend); - - /* E.g. for fetch and increment bounded... */ - /* mem(EA,s) =3D (t !=3D t2 ? u =3D t + 1 : t) */ - tcg_gen_movcond_tl(cond, u, t, t2, u, t); - tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); - - /* RT =3D (t !=3D t2 ? t : u =3D 1<<(s*8-1)) */ - tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, - tcg_constant_tl(1 << (memop_size(memop) * 8 - 1))); -} - -static void gen_ld_atomic(DisasContext *ctx, MemOp memop) -{ - uint32_t gpr_FC =3D FC(ctx->opcode); - TCGv EA =3D tcg_temp_new(); - int rt =3D rD(ctx->opcode); - bool need_serial; - TCGv src, dst; - - gen_addr_register(ctx, EA); - dst =3D cpu_gpr[rt]; - src =3D cpu_gpr[(rt + 1) & 31]; - - need_serial =3D false; - memop |=3D MO_ALIGN; - switch (gpr_FC) { - case 0: /* Fetch and add */ - tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 1: /* Fetch and xor */ - tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 2: /* Fetch and or */ - tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 3: /* Fetch and 'and' */ - tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 4: /* Fetch and max unsigned */ - tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 5: /* Fetch and max signed */ - tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 6: /* Fetch and min unsigned */ - tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 7: /* Fetch and min signed */ - tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 8: /* Swap */ - tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); - break; - - case 16: /* Compare and swap not equal */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - need_serial =3D true; - } else { - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); - if ((memop & MO_SIZE) =3D=3D MO_64 || TARGET_LONG_BITS =3D=3D = 32) { - tcg_gen_mov_tl(t1, src); - } else { - tcg_gen_ext32u_tl(t1, src); - } - tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, - cpu_gpr[(rt + 2) & 31], t0); - tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); - tcg_gen_mov_tl(dst, t0); - } - break; - - case 24: /* Fetch and increment bounded */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - need_serial =3D true; - } else { - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); - } - break; - case 25: /* Fetch and increment equal */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - need_serial =3D true; - } else { - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); - } - break; - case 28: /* Fetch and decrement bounded */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - need_serial =3D true; - } else { - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); - } - break; - - default: - /* invoke data storage error handler */ - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); - } - - if (need_serial) { - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(tcg_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - } -} - -static void gen_lwat(DisasContext *ctx) -{ - gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); -} - -#ifdef TARGET_PPC64 -static void gen_ldat(DisasContext *ctx) -{ - gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); -} -#endif - -static void gen_st_atomic(DisasContext *ctx, MemOp memop) -{ - uint32_t gpr_FC =3D FC(ctx->opcode); - TCGv EA =3D tcg_temp_new(); - TCGv src, discard; - - gen_addr_register(ctx, EA); - src =3D cpu_gpr[rD(ctx->opcode)]; - discard =3D tcg_temp_new(); - - memop |=3D MO_ALIGN; - switch (gpr_FC) { - case 0: /* add and Store */ - tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); - break; - case 1: /* xor and Store */ - tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); - break; - case 2: /* Or and Store */ - tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); - break; - case 3: /* 'and' and Store */ - tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); - break; - case 4: /* Store max unsigned */ - tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); - break; - case 5: /* Store max signed */ - tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); - break; - case 6: /* Store min unsigned */ - tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); - break; - case 7: /* Store min signed */ - tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); - break; - case 24: /* Store twin */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(tcg_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - } else { - TCGv t =3D tcg_temp_new(); - TCGv t2 =3D tcg_temp_new(); - TCGv s =3D tcg_temp_new(); - TCGv s2 =3D tcg_temp_new(); - TCGv ea_plus_s =3D tcg_temp_new(); - - tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); - tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop)); - tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); - tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); - tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); - tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); - tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); - } - break; - default: - /* invoke data storage error handler */ - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); - } -} - -static void gen_stwat(DisasContext *ctx) -{ - gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); -} - -#ifdef TARGET_PPC64 -static void gen_stdat(DisasContext *ctx) -{ - gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); -} -#endif - /* wait */ static void gen_wait(DisasContext *ctx) { @@ -5571,12 +5365,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_= STRING), GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), -GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), -#if defined(TARGET_PPC64) -GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), -#endif /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 25a60d3d3a..f9435f4a00 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1646,3 +1646,217 @@ static bool trans_SRAWI(DisasContext *ctx, arg_SRAW= I *a) } return true; } + +static void do_fetch_inc_conditional(DisasContext *ctx, MemOp memop, + TCGv EA, int rt, + TCGCond cond, int addend) +{ + TCGv t =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_new(); + TCGv u =3D tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); + tcg_gen_addi_tl(t2, EA, memop_size(memop)); + tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); + tcg_gen_addi_tl(u, t, addend); + + /* mem(EA,s) =3D (t cond t2 ? u =3D t + addend : t) */ + tcg_gen_movcond_tl(cond, u, t, t2, u, t); + tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); + + /* RT =3D (t cond t2 ? t : 1<<(s*8-1)) */ + tcg_gen_movcond_tl(cond, cpu_gpr[rt], t, t2, t, + tcg_constant_tl(1 << (memop_size(memop) * 8 - 1))); +} + +/* + * Fixed-Point Atomic Load/Store Instructions + * + * In the X-form encoding the RB field carries the Function Code (FC) + * that selects the atomic operation. EA is computed from RA alone. + */ +static bool do_ld_atomic(DisasContext *ctx, arg_X *a, MemOp memop) +{ + TCGv EA, dst, src; + bool need_serial; + + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + + EA =3D do_ea_calc(ctx, a->ra, tcg_constant_tl(0)); + dst =3D cpu_gpr[a->rt]; + src =3D cpu_gpr[(a->rt + 1) & 31]; + + need_serial =3D false; + memop |=3D MO_ALIGN; + switch (a->rb) { + case 0: /* Fetch and add */ + tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 1: /* Fetch and xor */ + tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 2: /* Fetch and or */ + tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 3: /* Fetch and 'and' */ + tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 4: /* Fetch and max unsigned */ + tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 5: /* Fetch and max signed */ + tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 6: /* Fetch and min unsigned */ + tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 7: /* Fetch and min signed */ + tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 8: /* Swap */ + tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); + break; + + case 16: /* Compare and swap not equal */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); + if ((memop & MO_SIZE) =3D=3D MO_64 || TARGET_LONG_BITS =3D=3D = 32) { + tcg_gen_mov_tl(t1, src); + } else { + tcg_gen_ext32u_tl(t1, src); + } + tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, + cpu_gpr[(a->rt + 2) & 31], t0); + tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); + tcg_gen_mov_tl(dst, t0); + } + break; + + case 24: /* Fetch and increment bounded */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_NE, 1= ); + } + break; + case 25: /* Fetch and increment equal */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_EQ, 1= ); + } + break; + case 28: /* Fetch and decrement bounded */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_NE, -= 1); + } + break; + + default: + /* invoke data storage error handler */ + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); + } + + if (need_serial) { + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(tcg_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + } + return true; +} + +static bool do_st_atomic(DisasContext *ctx, arg_X *a, MemOp memop) +{ + TCGv EA, src, discard; + + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + + EA =3D do_ea_calc(ctx, a->ra, tcg_constant_tl(0)); + src =3D cpu_gpr[a->rt]; + discard =3D tcg_temp_new(); + + memop |=3D MO_ALIGN; + switch (a->rb) { + case 0: /* add and Store */ + tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 1: /* xor and Store */ + tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 2: /* Or and Store */ + tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 3: /* 'and' and Store */ + tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 4: /* Store max unsigned */ + tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; + case 5: /* Store max signed */ + tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; + case 6: /* Store min unsigned */ + tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; + case 7: /* Store min signed */ + tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; + case 24: /* Store twin */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(tcg_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + } else { + TCGv t =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_new(); + TCGv s =3D tcg_temp_new(); + TCGv s2 =3D tcg_temp_new(); + TCGv ea_plus_s =3D tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); + tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop)); + tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); + tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); + tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); + tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); + tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); + } + break; + default: + /* invoke data storage error handler */ + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); + } + return true; +} + +TRANS(LWAT, do_ld_atomic, DEF_MEMOP(MO_UL)) +TRANS(STWAT, do_st_atomic, DEF_MEMOP(MO_UL)) + +static bool trans_LDAT(DisasContext *ctx, arg_LDAT *a) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + return do_ld_atomic(ctx, a, DEF_MEMOP(MO_UQ)); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STDAT(DisasContext *ctx, arg_STDAT *a) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + return do_st_atomic(ctx, a, DEF_MEMOP(MO_UQ)); +#else + qemu_build_not_reached(); +#endif + return true; +} --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787837531; cv=none; d=zohomail.com; s=zohoarc; b=VqwJWnZA3TqN86avCoV1+YHnSZn2Z3i0jBoWkLFZeUww99sr/U0SR2R1JEbBZ1c/SA0RcNMiEDkFrH6Ttjcv59sV+xIAMR+nH7TF9GA65GIlT/jladQW8SJtQfT0l3eyFzuNcCytDxwYYBCHeWR22cOhXK5gMSILLUInMw1BzbA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787837531; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837531716158500 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Moving the following instructions to decodetree specification : isync The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Ojaswin Mujoo Reviewed-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 1 + target/ppc/translate.c | 15 --------------- target/ppc/translate/storage-ctrl-impl.c.inc | 17 +++++++++++++++++ 3 files changed, 18 insertions(+), 15 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index e8326a9d0b..6fb7754566 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1470,6 +1470,7 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 - @X_sync ...... .. l:3 ... sc:2 ..... .......... . &X_sync SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync EIEIO 011111 ----- ----- ----- 1101010110 - +ISYNC 010011 ----- ----- ----- 0010010110 - =20 # Condition Register Field Instruction =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c44cffb5e8..84589716b3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2727,20 +2727,6 @@ static inline void gen_check_tlb_flush(DisasContext = *ctx, bool global) static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } #endif =20 -/* isync */ -static void gen_isync(DisasContext *ctx) -{ - /* - * We need to check for a pending TLB flush. This can only happen in - * kernel mode however so check MSR_PR - */ - if (!ctx->pr) { - gen_check_tlb_flush(ctx, false); - } - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; -} - /* wait */ static void gen_wait(DisasContext *ctx) { @@ -5364,7 +5350,6 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_S= TRING), GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), -GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/tran= slate/storage-ctrl-impl.c.inc index b8b4454663..943229c438 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -155,6 +155,23 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE= *a) return true; } =20 +static bool trans_ISYNC(DisasContext *ctx, arg_ISYNC *a) +{ + REQUIRE_INSNS_FLAGS(ctx, MEM); + + /* + * We need to check for a pending TLB flush. This can only happen in + * kernel mode however so check MSR_PR + */ + if (!ctx->pr) { + gen_check_tlb_flush(ctx, false); + } + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; + + return true; +} + static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a) { REQUIRE_64BIT(ctx); --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787837541; cv=none; d=zohomail.com; s=zohoarc; b=lo8A6VIMze7hnX0SnCaW4i7nlaJO2Cbwjtx/fsDz954lGNbYhkppzxobhazhMuGZDkYX1KzGLvEx2HpYiELPUKaEPfLLV4rWDhrbBZU4wn1S0wcbJ6eN53S7dt/2bSu/lcmQ0gE/H3ptnqtFUfmTKocsxWtyh+6MgQ4xM/QW4+0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=P7kAxynKjVJBBfq1W tVE7zceMVkujNzaFS5jVJwMxDk=; b=oJRzc5m8RTlwyPwcAQ3KY0Hgvvb5FxbFO st49jP2RFGRAeQF7rOzqepSVoqjXFVZMOqENJZ0F6z5vZjHbuXrgyq4wo7DmuQdL hZ5eQhY9irFtxnUOEEUmLHPMov+SYYujvEcoKMGDNZeNEwIGP6COdN1odlAPcwTb rsbrgIe+2OSZ1uXfQLU5U+a396G+IbLDKsMmPtYz4YsGWOjmjfSA/x6ra0l+VX3a tZE0O4wc/GR5HBucc7LjH+AkLL0eYy1xGQzGHOI8PmjaVRh4ky9Q9XjdihGTH1QW dAp9r3xWX0eONQw5yTNDjOk93Adq/DiFJBGUsZv60zrOuVeTa0hRw== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 14/37] target/ppc: Convert b{a, l, la} to decode tree Date: Thu, 27 Aug 2026 18:59:29 +0530 Message-ID: <20260827133010.278889-15-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: -jxRMONewgVHNJgmYIg-JZvKLHdpUyBP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfXwk//vXRi6BKH hOcjcZmNC0DyvI22HYUoFJ/o3bDs2J3QfLMOFjn9zcl4wHhRbxMrHm1cCNvJE6E+C4NKhEcj9Rl 4ciuwbL+IGiofjnBft7rAmVSKmkPb5iyJCH2o7YVIhPeJTocUqNs/xAOVFvMu5r95VJjtf/bjSJ Y6ufehJlmzvLWdTzSFnubB54tMlLCrvQoomt/DaXV89XOK7Q9LuibPwfO4s6inPzFBdFzygfy84 ZmCjdcrvRD5m4b5UYHaCg3rnHXpMcHjud7kCsSQQlzugJWmKJr2QPlCJ6lBHOXRhESmiDRM/AKj IB1VVwWKpfjJj5zUiISyFs2qmT5ABoZM8VeADRUT0lPUoKsHtyVN2VLeT0M3Ft2+W/OSatyxM6A UrBh66JRoekcG+SzDyTCqwwzPwoOQwa0QP7NwOfC5reqJ/ccoJBbzauuCR8f1ZZlUSj7IcmEvav iBUbLU8aSFQOqOEbN/g== X-Authority-Analysis: v=2.4 cv=Y/nIdBeN c=1 sm=1 tr=0 ts=6a903c57 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=8uLd_aw9J8tj_XdJNvAA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX3O4c6bEbhDLZ KkJXO0v459nPvuxhIPApxGBaYtPaM2kHuOofwXnrxkXy4G+IfDPCVJlVtjlhOESThVVBnQru1gC cqOKBPX0JR5fqb69r7DLgIeFByXeWpI= X-Proofpoint-ORIG-GUID: RrqLs4flgmlF_dhFfEaMP84MFBScllFu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837541784158501 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Convert b, ba, bl and bla to decode tree specification. The functionality was tested by comparing the qemu -D log -d op,in_asm output as well as single stepping gdb to confirm LR was correctly populated only when LK is set. Signed-off-by: Ojaswin Mujoo Reviewed-by: Nikhil Kumar Singh Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 7 +++++++ target/ppc/internal.h | 7 ------- target/ppc/translate.c | 24 ------------------------ target/ppc/translate/branch-impl.c.inc | 24 ++++++++++++++++++++++++ 4 files changed, 31 insertions(+), 31 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 6fb7754566..0c58899429 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1486,6 +1486,13 @@ MCRF 010011 ... -- ... -- ----- 00000 000= 00 - @XL_bfa MFBHRBE 011111 ..... ..... ..... 0100101110 - @XFX_bhrbe CLRBHRB 011111 ----- ----- ----- 0110101110 - =20 +# Branch Instructions +%li 2:24 !function=3Dtimes_4 +&I_b li aa:bool lk:bool +@I_b ...... ........................ aa:1 lk:1 &I_b li=3D%li + +B 010010 ........................ . . @I_b + ## Misc POWER instructions =20 ATTN 000000 00000 00000 00000 0100000000 0 diff --git a/target/ppc/internal.h b/target/ppc/internal.h index a3bb12afd9..a20a0f9f7e 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -197,13 +197,6 @@ EXTRACT_HELPER(L, 16, 2); EXTRACT_HELPER(WC, 21, 2); EXTRACT_HELPER(PL, 16, 2); =20 -/*** Jump target decoding = ***/ -/* Immediate address */ -static inline target_ulong LI(uint32_t opcode) -{ - return (opcode >> 0) & 0x03FFFFFC; -} - static inline uint32_t BD(uint32_t opcode) { return (opcode >> 0) & 0xFFFC; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 84589716b3..3c6e2da8ce 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3089,29 +3089,6 @@ static inline void gen_setlr(DisasContext *ctx, targ= et_ulong nip) tcg_gen_movi_tl(cpu_lr, nip); } =20 -/* b ba bl bla */ -static void gen_b(DisasContext *ctx) -{ - target_ulong li, target; - - /* sign extend LI */ - li =3D LI(ctx->opcode); - li =3D (li ^ 0x02000000) - 0x02000000; - if (likely(AA(ctx->opcode) =3D=3D 0)) { - target =3D ctx->cia + li; - } else { - target =3D li; - } - if (LK(ctx->opcode)) { - gen_setlr(ctx, ctx->base.pc_next); - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL); - } else { - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER); - } - gen_goto_tb(ctx, 0, target); - ctx->base.is_jmp =3D DISAS_NORETURN; -} - #define BCOND_IM 0 #define BCOND_LR 1 #define BCOND_CTR 2 @@ -5353,7 +5330,6 @@ GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_= STRING), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), -GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc index 9ade0c659a..745f71afd1 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -31,3 +31,27 @@ static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) return true; } #endif + +static bool trans_B(DisasContext *ctx, arg_I_b *a) +{ + target_ulong target, li; + + /* sign extend LI */ + li =3D (a->li ^ 0x02000000) - 0x02000000; + + if (likely(a->aa =3D=3D 0)) { + target =3D ctx->cia + li; + } else { + target =3D li; + } + if (a->lk) { + gen_setlr(ctx, ctx->base.pc_next); + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL); + } else { + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER); + } + gen_goto_tb(ctx, 0, target); + ctx->base.is_jmp =3D DISAS_NORETURN; + + return true; +} --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787837569; cv=none; d=zohomail.com; s=zohoarc; b=FKffiGp8D+etxkWHJ3hcprUVvZeEWp/brBRUDer/5+GV2mxe40t+9CxotJAboGPagDEbHsK5tlR/etyqT6d8QKW7rLWKYo9Xdyz4wB/zOgDcYOo1fqb79D3efvT/EwWpx1EkMEOCzPDJGCiZBdPVSi9NbNHtUnfuqklkU4fSRnI= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=eMFil7s0PsSrm8/kw p2W/6ncUkw47QIITQyQo98V9Gk=; b=n0svt5hfp6Olj/6QXyEimXHTxUbG2V7n0 rs4j4FqqfAKVaHOD2g7cVM1HUKhoIsXVfROQRMeX1UL/W/KqpS8ZgG8sJyWwYJ3P cY3zdwwnmzVqU00kn2KzSWltB/KaMegLxPJGhdRw0I/vNire7HUksMDJBNCfFtKg BPpRjpS1YFKCKqIloT01Cs/GvQXQd+lF6LHbvzclw71ljQUtMFbfWDtRWJ5JxI4b gly+yrKzZDBDM8nHHmU0g0F1OsjhsDxwGAJimoPVK3t4tgLz8gZDqbLJin5/alAl 4uF+fkcT4sikaR8vsDrpR4Hyeebi6EDMXRNr1ggW4xd5Yt/iON4Bg== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 15/37] target/ppc: move various conditional branch insns to decodetree Date: Thu, 27 Aug 2026 18:59:30 +0530 Message-ID: <20260827133010.278889-16-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX8GJHYqM5eGsr Dr+PL8Pq232s8pu0DuFt36xZhEgk9B2XatsIB3FuejkSYkRGY4zxbrS8Dnl7k0IP1nqaHRe1zwa gfTnhDm5r9K/Hm2Eb/Q8YBIIYzUd9Lw= X-Authority-Analysis: v=2.4 cv=AYuB2XXG c=1 sm=1 tr=0 ts=6a903c5d cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=CKxRzG1O2kzciCs865QA:9 X-Proofpoint-ORIG-GUID: YRl9hXNgzpv2VBtN446jAYykg-1DOye6 X-Proofpoint-GUID: Xs_vpH-lE5hwY9ya_1OBNiXAvO4BSkrr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX1G8ck4lw/wEz 6FKNg9FF1MOqfUHze0yt3VpcRCRKEcvtN1Rv3VVWCz2umwCmrxDF6S42GEnGD7vPjyTDL/zdTSW HNtoC5rPVMl8KYGyIRMIYDIn2BlsW96ULhxDQpDDy3w0dxqLpiPZ0eV/T7NVG5TIFfWAa3gTlQA 4CSAXzS2/3fFzc9KH1XvOuMkOwBLxlZjFEU33WY9iUm9/u3o/pzBmrgKH+T7GGtwmPvO+SftAvC 8gayaIOBFh+s5JvmRiJcE4uESwhBtnwnDMhkUB4KkAjgnnE0BaPjHgGcJGlsfHTc50b2i2Wc30t mmOnPLu3bm0ckW2GAelBX2QcU5MaZvfJ+T3zWDCi7ARiBuef9tWR6vBgwI3P7b5yuKV7D++T16r IOPahF7XaoKEeA/yFxYr3xIEl/c4Ijd1In7dE6+a/suIu1R1J6Fl4LHgoQiEMVnSTQz9VmfwSOg A9/JGJPDbBAhjCUt3Gg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837570015158500 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Convert the following instructions to decodetree specification: bc bca bcl bcla bclr bclrl bcctr bcctrl bctar bctarl The branch was tested by comparing the qemu -D log -d op,in_asm output for each instruction and also for the various combinations of branch option (BO) bits for the conditional branch instructions. Additionally, gdb was used to confirm the LR and other register's behavior is consistent to legacy behavior. Further, the changes also pass a boot test into Fedora distro. Signed-off-by: Ojaswin Mujoo Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 13 +++ target/ppc/translate.c | 148 ----------------------- target/ppc/translate/branch-impl.c.inc | 156 +++++++++++++++++++++++++ 3 files changed, 169 insertions(+), 148 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 0c58899429..e7cc36bd6c 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1493,6 +1493,19 @@ CLRBHRB 011111 ----- ----- ----- 0110101110 - =20 B 010010 ........................ . . @I_b =20 +%bd 2:14 !function=3Dtimes_4 +&bcond bo:uint32_t bi bd aa:bool lk:bool +@B_bcond ...... bo:5 bi:5 .............. aa:1 lk:1 &bcond bd=3D%bd + +BC 010000 ..... ..... .............. . . @B_bcond + +&bclr bo bi bh lk:bool +@XL_bclr ...... bo:5 bi:5 --- bh:2 .......... lk:1 &bclr + +BCLR 010011 ..... ..... ---.. 0000010000 . @XL_bclr +BCCTR 010011 ..... ..... ---.. 1000010000 . @XL_bclr +BCTAR 010011 ..... ..... ---.. 1000110000 . @XL_bclr + ## Misc POWER instructions =20 ATTN 000000 00000 00000 00000 0100000000 0 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3c6e2da8ce..f5b1446d7a 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3089,150 +3089,6 @@ static inline void gen_setlr(DisasContext *ctx, tar= get_ulong nip) tcg_gen_movi_tl(cpu_lr, nip); } =20 -#define BCOND_IM 0 -#define BCOND_LR 1 -#define BCOND_CTR 2 -#define BCOND_TAR 3 - -static void gen_bcond(DisasContext *ctx, int type) -{ - uint32_t bo =3D BO(ctx->opcode); - TCGLabel *l1; - TCGv target; - target_long bhrb_type =3D BHRB_TYPE_OTHER; - - if (type =3D=3D BCOND_LR || type =3D=3D BCOND_CTR || type =3D=3D BCOND= _TAR) { - target =3D tcg_temp_new(); - if (type =3D=3D BCOND_CTR) { - tcg_gen_mov_tl(target, cpu_ctr); - } else if (type =3D=3D BCOND_TAR) { - gen_load_spr(target, SPR_TAR); - } else { - tcg_gen_mov_tl(target, cpu_lr); - } - if (!LK(ctx->opcode)) { - bhrb_type |=3D BHRB_TYPE_INDIRECT; - } - bhrb_type |=3D BHRB_TYPE_XL_FORM; - } else { - target =3D NULL; - } - if (LK(ctx->opcode)) { - gen_setlr(ctx, ctx->base.pc_next); - bhrb_type |=3D BHRB_TYPE_CALL; - } - l1 =3D gen_new_label(); - if ((bo & 0x4) =3D=3D 0) { - /* Decrement and test CTR */ - TCGv temp =3D tcg_temp_new(); - - if (type =3D=3D BCOND_CTR) { - /* - * All ISAs up to v3 describe this form of bcctr as invalid but - * some processors, ie. 64-bit server processors compliant with - * arch 2.x, do implement a "test and decrement" logic instead, - * as described in their respective UMs. This logic involves C= TR - * to act as both the branch target and a counter, which makes - * it basically useless and thus never used in real code. - * - * This form was hence chosen to trigger extra micro-architect= ural - * side-effect on real HW needed for the Spectre v2 workaround. - * It is up to guests that implement such workaround, ie. linu= x, to - * use this form in a way it just triggers the side-effect wit= hout - * doing anything else harmful. - */ - if (unlikely(!is_book3s_arch2x(ctx))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - - if (NARROW_MODE(ctx)) { - tcg_gen_ext32u_tl(temp, cpu_ctr); - } else { - tcg_gen_mov_tl(temp, cpu_ctr); - } - if (bo & 0x2) { - tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); - } else { - tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); - } - tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); - } else { - tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); - if (NARROW_MODE(ctx)) { - tcg_gen_ext32u_tl(temp, cpu_ctr); - } else { - tcg_gen_mov_tl(temp, cpu_ctr); - } - if (bo & 0x2) { - tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); - } else { - tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); - } - } - bhrb_type |=3D BHRB_TYPE_COND; - } - if ((bo & 0x10) =3D=3D 0) { - /* Test CR */ - uint32_t bi =3D BI(ctx->opcode); - uint32_t mask =3D 0x08 >> (bi & 0x03); - TCGv_i32 temp =3D tcg_temp_new_i32(); - - if (bo & 0x8) { - tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); - tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); - } else { - tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); - tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); - } - bhrb_type |=3D BHRB_TYPE_COND; - } - - gen_update_branch_history(ctx, ctx->cia, target, bhrb_type); - - if (type =3D=3D BCOND_IM) { - target_ulong li =3D (target_long)((int16_t)(BD(ctx->opcode))); - if (likely(AA(ctx->opcode) =3D=3D 0)) { - gen_goto_tb(ctx, 0, ctx->cia + li); - } else { - gen_goto_tb(ctx, 0, li); - } - } else { - if (NARROW_MODE(ctx)) { - tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); - } else { - tcg_gen_andi_tl(cpu_nip, target, ~3); - } - gen_lookup_and_goto_ptr(ctx); - } - if ((bo & 0x14) !=3D 0x14) { - /* fallthrough case */ - gen_set_label(l1); - gen_goto_tb(ctx, 1, ctx->base.pc_next); - } - ctx->base.is_jmp =3D DISAS_NORETURN; -} - -static void gen_bc(DisasContext *ctx) -{ - gen_bcond(ctx, BCOND_IM); -} - -static void gen_bcctr(DisasContext *ctx) -{ - gen_bcond(ctx, BCOND_CTR); -} - -static void gen_bclr(DisasContext *ctx) -{ - gen_bcond(ctx, BCOND_LR); -} - -static void gen_bctar(DisasContext *ctx) -{ - gen_bcond(ctx, BCOND_TAR); -} - /*** Condition register logical = ***/ #define GEN_CRLOGIC(name, tcg_op, opc) = \ static void glue(gen_, name)(DisasContext *ctx) = \ @@ -5330,10 +5186,6 @@ GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC= _STRING), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), -GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), -GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), -GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), -GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_IS= A207), GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc index 745f71afd1..c51fd9b13e 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -55,3 +55,159 @@ static bool trans_B(DisasContext *ctx, arg_I_b *a) =20 return true; } + +#define BCOND_IM 0 +#define BCOND_LR 1 +#define BCOND_CTR 2 +#define BCOND_TAR 3 + +static bool bcond_helper(DisasContext *ctx, int type, uint32_t bo, int bi, + int bd, int bh, bool aa, bool lk) +{ + TCGLabel *l1; + TCGv target; + target_long bhrb_type =3D BHRB_TYPE_OTHER; + + if (type =3D=3D BCOND_IM && bh !=3D -1) { + /* BCOND_IM should never use bh */ + return false; + } else if (type !=3D BCOND_IM && (bd !=3D -1 || aa !=3D 0)) { + /* Other BCOND types should never use bd or aa */ + return false; + } + + if (type =3D=3D BCOND_LR || type =3D=3D BCOND_CTR || type =3D=3D BCOND= _TAR) { + target =3D tcg_temp_new(); + if (type =3D=3D BCOND_CTR) { + tcg_gen_mov_tl(target, cpu_ctr); + } else if (type =3D=3D BCOND_TAR) { + gen_load_spr(target, SPR_TAR); + } else { + tcg_gen_mov_tl(target, cpu_lr); + } + if (!lk) { + bhrb_type |=3D BHRB_TYPE_INDIRECT; + } + bhrb_type |=3D BHRB_TYPE_XL_FORM; + } else { + target =3D NULL; + } + if (lk) { + gen_setlr(ctx, ctx->base.pc_next); + bhrb_type |=3D BHRB_TYPE_CALL; + } + l1 =3D gen_new_label(); + if ((bo & 0x4) =3D=3D 0) { + /* Decrement and test CTR */ + TCGv temp =3D tcg_temp_new(); + + if (type =3D=3D BCOND_CTR) { + /* + * All ISAs up to v3 describe this form of bcctr as invalid but + * some processors, ie. 64-bit server processors compliant with + * arch 2.x, do implement a "test and decrement" logic instead, + * as described in their respective UMs. This logic involves C= TR + * to act as both the branch target and a counter, which makes + * it basically useless and thus never used in real code. + * + * This form was hence chosen to trigger extra micro-architect= ural + * side-effect on real HW needed for the Spectre v2 workaround. + * It is up to guests that implement such workaround, ie. linu= x, to + * use this form in a way it just triggers the side-effect wit= hout + * doing anything else harmful. + */ + if (unlikely(!is_book3s_arch2x(ctx))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + if (NARROW_MODE(ctx)) { + tcg_gen_ext32u_tl(temp, cpu_ctr); + } else { + tcg_gen_mov_tl(temp, cpu_ctr); + } + if (bo & 0x2) { + tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); + } else { + tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); + } + tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); + } else { + tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); + if (NARROW_MODE(ctx)) { + tcg_gen_ext32u_tl(temp, cpu_ctr); + } else { + tcg_gen_mov_tl(temp, cpu_ctr); + } + if (bo & 0x2) { + tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); + } else { + tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); + } + } + bhrb_type |=3D BHRB_TYPE_COND; + } + if ((bo & 0x10) =3D=3D 0) { + /* Test CR */ + uint32_t mask =3D 0x08 >> (bi & 0x03); + TCGv_i32 temp =3D tcg_temp_new_i32(); + + if (bo & 0x8) { + tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); + tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); + } else { + tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); + tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); + } + bhrb_type |=3D BHRB_TYPE_COND; + } + + gen_update_branch_history(ctx, ctx->cia, target, bhrb_type); + + if (type =3D=3D BCOND_IM) { + target_ulong li =3D (target_long)((int16_t)(bd)); + if (likely(aa =3D=3D 0)) { + gen_goto_tb(ctx, 0, ctx->cia + li); + } else { + gen_goto_tb(ctx, 0, li); + } + } else { + if (NARROW_MODE(ctx)) { + tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); + } else { + tcg_gen_andi_tl(cpu_nip, target, ~3); + } + gen_lookup_and_goto_ptr(ctx); + } + if ((bo & 0x14) !=3D 0x14) { + /* fallthrough case */ + gen_set_label(l1); + gen_goto_tb(ctx, 1, ctx->base.pc_next); + } + ctx->base.is_jmp =3D DISAS_NORETURN; + + return true; +} + +static bool trans_BC(DisasContext *ctx, arg_bcond *a) +{ + /* + * bh is not used for bc variants hence we pass -1 + */ + return bcond_helper(ctx, BCOND_IM, a->bo, a->bi, a->bd, -1, a->aa, a->= lk); +} + +/* + * This helper is shared by bclr, bcctr and bctar. + */ +static bool bclr_helper(DisasContext *ctx, arg_bclr *a, int type) +{ + /* + * bd and aa is not used for bc variants hence we pass -1 and 0 respec= tively + */ + return bcond_helper(ctx, type, a->bo, a->bi, -1, a->bh, 0, a->lk); +} + +TRANS(BCLR, bclr_helper, BCOND_LR) +TRANS(BCCTR, bclr_helper, BCOND_CTR) +TRANS_FLAGS2(BCTAR_ISA207, BCTAR, bclr_helper, BCOND_TAR) --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787837567; cv=none; d=zohomail.com; s=zohoarc; b=Pv/ZZN3VGVjITnO2rGpchSKjNyYQicj1Rol7M4Rso4RsicKjMOvvaijKZvo0vfImRoMnB79rMtgLVg/9Idb/rcZl+iLsYI14D5ZZMlMhP7k9gRNoSX6hT3iu5+aNavaAEFaJnKV9mTzy9R/vHmpANI/5zwKruz56jFMw1VzoIBU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787837567; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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b=f7X7sqPAolfKDlcSIc/R/l COULs4yst7CUhmH0wNQhoeTwr5O+4eBchBqHftPNMQ+TxAu3fcTmafi7P2/WEq6L kyxSMVQFyXuR/GLOdtiBX9y1NhiQrU9znxw6Fbl1/WSecMNjOkV4IVjE47nftx78 ro5x/WSlf3m5d/Ca8rMa0bX4sZaQ8s9vR3+NPQ+pZrIIEe7Av/6y2WYdg/yMCYzk VxRlgq97oAeIBO1RxH1PsuKLhwrv7zXEqA/NUbu7eibo9LE3nEGDV/GTPER5ik7Y MkG2hGUNkqo7e3cwouworpz49izaqluN/F53CZfXeGB/7tjjYztr6X+N5jlA0FiQ == From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 16/37] target/ppc: Fix TRANS* macro variadic arguments handling Date: Thu, 27 Aug 2026 18:59:31 +0530 Message-ID: <20260827133010.278889-17-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837567946158500 From: Ojaswin Mujoo Use ##__VA_ARGS__ in TRANS* macros to allow variadic arguments to be optional instead of mandatory. "##" removes the preceding comma when __VA_ARGS__ is empty, enabling macros to work with functions that don't need extra parameters. This avoid compilation errors when using a pattern like below: static bool do_wait(DisasContext *ctx, arg_X_wait *a) {...} TRANS_FLAGS(WAIT, WAIT_ISA_2_X, do_wait) Compilation Error: ../target/ppc/translate.c:5526:40: error: expected expression before =E2=80= =98)=E2=80=99 token 5526 | return FUNC(ctx, a, __VA_ARGS__); \ | ^ ../target/ppc/translate/storage-ctrl-impl.c.inc:368:1: note: in expansion o= f macro =E2=80=98TRANS_FLAGS=E2=80=99 368 | TRANS_FLAGS(WAIT, WAIT_ISA_2_X, do_wait) Signed-off-by: Ojaswin Mujoo Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f5b1446d7a..322870dc0d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4749,29 +4749,29 @@ static int64_t dw_compose_ea(DisasContext *ctx, int= x) */ #define TRANS(NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ - { return FUNC(ctx, a, __VA_ARGS__); } + { return FUNC(ctx, a, ##__VA_ARGS__); } #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ - return FUNC(ctx, a, __VA_ARGS__); \ + return FUNC(ctx, a, ##__VA_ARGS__); \ } #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ - return FUNC(ctx, a, __VA_ARGS__); \ + return FUNC(ctx, a, ##__VA_ARGS__); \ } =20 #define TRANS64(NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ - { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } + { REQUIRE_64BIT(ctx); return FUNC(ctx, a, ##__VA_ARGS__); } #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ REQUIRE_64BIT(ctx); \ REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ - return FUNC(ctx, a, __VA_ARGS__); \ + return FUNC(ctx, a, ##__VA_ARGS__); \ } =20 /* TODO: More TRANS* helpers for extra insn_flags checks. */ --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 27 Aug 2026 13:32:21 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 758F120043; Thu, 27 Aug 2026 13:32:15 +0000 (GMT) Received: from li-18a0a34c-33fc-11b2-a85c-d9f1631c5692.ibm.com (unknown [9.111.12.1]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 27 Aug 2026 13:32:15 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=JalPK9pK2J2b4ofpE nG+jd28VyNFmej5Av36hE4/d6M=; b=JDLMuRUBol1fAkBYVnY0T9lmqu7IL17rU lTlr4rOvzP/s8V1NHsJHfVcscJru5afHaGOYSi69eMTQRzW0V1OmVM3nytE8vLPf RK4JpI+3QglQbxC0P5T8XHzE0y9mIySJ/ygW9HUw/Jae1wIyOSfrKTYlqkumvYg7 5xqylLsAPQl9DtvxYniDzyiCW7gGRy90S+B2BLdMbbsOM+blUc+IFk79cOs3MdZC 0gsGmo6WbqmIqERmmPTKBkpTtQGgdNU+51bwFTP9+uFTjSX13hiK+6yTaySzq5YO p1Vik2DIpK25c2olI/RLQZCTveCBrlqxlIbjSxrHooTZTcra6oMMg== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 17/37] target/ppc: Move wait instruction to decodetree Date: Thu, 27 Aug 2026 18:59:32 +0530 Message-ID: <20260827133010.278889-18-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX63aGHVYmvCwo FQSrYt4S5/5M9afQPav7k+upAIXac2OawAMSxyosWqciQDJSwTHKjRagdXVxiYrCHi8PRabMJVG n/+/mj+XjDB5NwpY5sCIC2iN5He8DOo= X-Authority-Analysis: v=2.4 cv=AYuB2XXG c=1 sm=1 tr=0 ts=6a903c6b cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=uB9JOsh-sYL72gAx4UQA:9 X-Proofpoint-ORIG-GUID: xhzzpLndZqwo61Z2kgRLLpLwLqV87K3r X-Proofpoint-GUID: euPVGynN90_ScL-qOyQRziZE3xJEB8bq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX12iRWZp608H/ IjGj4qAf5Nzdlj87KcAII/IjyEZUFOlTBhyexcSrNL8+0oM5XDHVWzEyP+TqfNzCX2doQLXJaDw 2ak/7owI6xCLhs4gkxeYO5B8LNDbnnM/OY2ZYZE06yHKIsc2cJEDAbsYUj8D+UQqhGJQ0osZF+P 1rVbqWNWn5AXL6mabbgS5otUnSo+V/CIUj0Ys6JaO5disL+LL5uaFVSV+GQXv7DTQLdmg9KxHZs 8C+rmCA4YBiaJF0wItZPqZBHDN/iKKctsdNImRxYSyrqyGW7x8hVOc18J8GIc0pwf2FGjV97ZkN okxedcsoXV9lFUF50dSajtJe5xR2fzXLfnCk+0G0z4fuaHmuedak4y/L/NOHffHeUxLqgQhJI7E /7TMMWXQ7tMHYoVT7aSjaCgS2ixWsuaPxfVFZxlanD8TbVm+Xvb+v1oJyGKjVNWXVxd5C6Sv1T5 bhDfzmq3nVaozCpZ4xQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837582082158500 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Implement wait instruction using decodetree with proper handling of WC and PL fields across different ISA versions. Since the opcode changed between ISA 2.x and 3.x we have defined 2 different decodetree instructions that are handled by the same helper. The changes have been tested by comparing the tcg generated before and after the change for wait instruction. The test was repeated for 2 types of machines: Power10 - which should use the newer wait implementation e500mc - which should use older PPC_WAIT implementation Both generated the same tcg ops with and without the change. Further, with the changes we were able to boot into Fedora distro as well. Signed-off-by: Ojaswin Mujoo Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 15 +++ target/ppc/translate.c | 91 ------------------ target/ppc/translate/storage-ctrl-impl.c.inc | 99 ++++++++++++++++++++ 3 files changed, 114 insertions(+), 91 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index e7cc36bd6c..da32ac1d28 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1478,6 +1478,21 @@ ISYNC 010011 ----- ----- ----- 0010010110 - @XL_bfa ...... bf:3 .. bfa:3 .. ..... ..... ..... . MCRF 010011 ... -- ... -- ----- 00000 00000 - @XL_bfa =20 +# Wait Instructions + +# We can use the same X_wait argument set for both WAIT and older ISA2.x +# compliant WAIT_2_x. Depending on the version, we may or may not use the +# arguments. For more information, check do_wait() helper. + +&X_wait wc pl +@X_wait ...... ..- wc:2 --- pl:2 ----- .......... - &X_wait + +# According to ISA v3.1, bit 6 and 7 are implementation dependent and "unl= ess +# the intention is to use the implementation-dependent field, these bits m= ust be +# coded zero". Hence, we code them to 0. +WAIT 011111 00-.. ---.. ----- 0000011110 - @X_wait +WAIT_ISA_2_X 011111 ---.. ---.. ----- 0000111110 - @X_wait + # Branch History Rolling Buffer (BHRB) Instructions =20 &XFX_bhrbe rt bhrbe diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 322870dc0d..e5ed4d2cc4 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2727,95 +2727,6 @@ static inline void gen_check_tlb_flush(DisasContext = *ctx, bool global) static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } #endif =20 -/* wait */ -static void gen_wait(DisasContext *ctx) -{ - uint32_t wc; - - if (ctx->insns_flags & PPC_WAIT) { - /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ - - if (ctx->insns_flags2 & PPC2_PM_ISA206) { - /* v2.06 introduced the WC field. WC > 0 may be treated as no-= op. */ - wc =3D WC(ctx->opcode); - } else { - wc =3D 0; - } - - } else if (ctx->insns_flags2 & PPC2_ISA300) { - /* v3.0 defines a new 'wait' encoding. */ - wc =3D WC(ctx->opcode); - if (ctx->insns_flags2 & PPC2_ISA310) { - uint32_t pl =3D PL(ctx->opcode); - - /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ - if (wc =3D=3D 3) { - gen_invalid(ctx); - return; - } - - /* PL 1-3 are reserved. If WC=3D2 then the insn is treated as = noop. */ - if (pl > 0 && wc !=3D 2) { - gen_invalid(ctx); - return; - } - - } else { /* ISA300 */ - /* WC 1-3 are reserved */ - if (wc > 0) { - gen_invalid(ctx); - return; - } - } - - } else { - warn_report("wait instruction decoded with wrong ISA flags."); - gen_invalid(ctx); - return; - } - - /* - * wait without WC field or with WC=3D0 waits for an exception / inter= rupt - * to occur. - */ - if (wc =3D=3D 0) { - TCGv_i32 t0 =3D tcg_constant_i32(1); - tcg_gen_st_i32(t0, tcg_env, - -offsetof(PowerPCCPU, env) + offsetof(CPUState, hal= ted)); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); - } - - /* - * Other wait types must not just wait until an exception occurs becau= se - * ignoring their other wake-up conditions could cause a hang. - * - * For v2.06 and 2.07, wc=3D1,2,3 are architected but may be implement= ed as - * no-ops. - * - * wc=3D1 and wc=3D3 explicitly allow the instruction to be treated as= a no-op. - * - * wc=3D2 waits for an implementation-specific condition, such could be - * always true, so it can be implemented as a no-op. - * - * For v3.1, wc=3D1,2 are architected but may be implemented as no-ops. - * - * wc=3D1 (waitrsv) waits for an exception or a reservation to be lost. - * Reservation-loss may have implementation-specific conditions, so it - * can be implemented as a no-op. - * - * wc=3D2 waits for an exception or an amount of time to pass. This - * amount is implementation-specific so it can be implemented as a - * no-op. - * - * ISA v3.1 allows for execution to resume "in the rare case of - * an implementation-dependent event", so in any case software must - * not depend on the architected resumption condition to become - * true, so no-op implementations should be architecturally correct - * (if suboptimal). - */ -} - #if defined(TARGET_PPC64) static void gen_doze(DisasContext *ctx) { @@ -5184,8 +5095,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_S= TRING), GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), /* ISA v3.0 changed the extended opcode from 62 to 30 */ -GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), -GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/tran= slate/storage-ctrl-impl.c.inc index 943229c438..d4d6ab765a 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -270,3 +270,102 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *= a, bool local) =20 TRANS_FLAGS(MEM_TLBIE, TLBIE, do_tlbie, false) TRANS_FLAGS(MEM_TLBIE, TLBIEL, do_tlbie, true) + +/* + * Decodetree populates a->wc and a->pl based on ISA v3.1, however they may + * or may not be used based on the ISA: + * For ISA < 2.06 - both wc and pl are ignored + * For ISA =3D=3D 2.06, 2.07, 3.0 - wc is used and pl is ignored + * For ISA 3.1 - both wc and pl are used + */ +static bool do_wait(DisasContext *ctx, arg_X_wait *a) +{ + uint32_t wc; + + if (ctx->insns_flags & PPC_WAIT) { + /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ + + if (ctx->insns_flags2 & PPC2_PM_ISA206) { + /* v2.06 introduced the WC field. WC > 0 may be treated as no-= op. */ + wc =3D a->wc; + } else { + wc =3D 0; + } + + } else if (ctx->insns_flags2 & PPC2_ISA300) { + /* v3.0 defines a new 'wait' encoding. */ + wc =3D a->wc; + if (ctx->insns_flags2 & PPC2_ISA310) { + uint32_t pl =3D a->pl; + + /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ + if (wc =3D=3D 3) { + gen_invalid(ctx); + return true; + } + + /* PL 1-3 are reserved. If WC=3D2 then the insn is treated as = noop. */ + if (pl > 0 && wc !=3D 2) { + gen_invalid(ctx); + return true; + } + + } else { /* ISA300 */ + /* WC 1-3 are reserved */ + if (wc > 0) { + gen_invalid(ctx); + return true; + } + } + + } else { + warn_report("wait instruction decoded with wrong ISA flags."); + gen_invalid(ctx); + return true; + } + + /* + * wait without WC field or with WC=3D0 waits for an exception / inter= rupt + * to occur. + */ + if (wc =3D=3D 0) { + TCGv_i32 t0 =3D tcg_constant_i32(1); + tcg_gen_st_i32(t0, tcg_env, + -offsetof(PowerPCCPU, env) + offsetof(CPUState, hal= ted)); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); + } + + /* + * Other wait types must not just wait until an exception occurs becau= se + * ignoring their other wake-up conditions could cause a hang. + * + * For v2.06 and 2.07, wc=3D1,2,3 are architected but may be implement= ed as + * no-ops. + * + * wc=3D1 and wc=3D3 explicitly allow the instruction to be treated as= a no-op. + * + * wc=3D2 waits for an implementation-specific condition, such could be + * always true, so it can be implemented as a no-op. + * + * For v3.1, wc=3D1,2 are architected but may be implemented as no-ops. + * + * wc=3D1 (waitrsv) waits for an exception or a reservation to be lost. + * Reservation-loss may have implementation-specific conditions, so it + * can be implemented as a no-op. + * + * wc=3D2 waits for an exception or an amount of time to pass. This + * amount is implementation-specific so it can be implemented as a + * no-op. + * + * ISA v3.1 allows for execution to resume "in the rare case of + * an implementation-dependent event", so in any case software must + * not depend on the architected resumption condition to become + * true, so no-op implementations should be architecturally correct + * (if suboptimal). + */ + return true; +} + +TRANS_FLAGS(WAIT, WAIT_ISA_2_X, do_wait) +TRANS_FLAGS2(ISA300, WAIT, do_wait) --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787837619; cv=none; d=zohomail.com; s=zohoarc; b=c4JRWQglL3i9uwfgw6ElXxvoD7ndp9zv3DjJmSXGvan4c6WlCT+c9+EeVJXKsM28fusnsZ2Bqb3xQWR0FndilQkMKwUkvWAJFyKTgurIMhqRSq/ILu2lW462VjB9XgfJ9sfqYxZ3DkTeVNrWsT07xiK/M3KBENNLbG7lVXuZorU= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837620346158500 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Convert the following instructions to decode tree specification: doze nap sleep rvwinkle stop The functionality was tested by comparing the qemu -D log -d op,in_asm output as well as single stepping gdb to confirm behavior was not changed for ISA3.x (stop) as well as ISA206 (doze, nap, sleep, rvwinkle). Signed-off-by: Ojaswin Mujoo Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 8 ++ target/ppc/translate.c | 85 --------------- .../ppc/translate/processor-ctrl-impl.c.inc | 100 ++++++++++++++++++ 3 files changed, 108 insertions(+), 85 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index da32ac1d28..b833244932 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -913,6 +913,14 @@ VPERMR 000100 ..... ..... ..... ..... 111011 = @VA =20 VSEL 000100 ..... ..... ..... ..... 101010 @VA =20 +## Power Management Instructions + +DOZE 010011 ----- ----- ----- 0110010010 - +NAP 010011 ----- ----- ----- 0110110010 - +SLEEP 010011 ----- ----- ----- 0111010010 - +RVWINKLE 010011 ----- ----- ----- 0111110010 - +STOP 010011 ----- ----- ----- 0101110010 - + ## Vector Integer Shift Instruction =20 VSLB 000100 ..... ..... ..... 00100000100 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e5ed4d2cc4..9d9823f92d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2728,86 +2728,6 @@ static inline void gen_check_tlb_flush(DisasContext = *ctx, bool global) { } #endif =20 #if defined(TARGET_PPC64) -static void gen_doze(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_DOZE); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_nap(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_NAP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_stop(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_STOP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_sleep(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_SLEEP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_rvwinkle(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_RVWINKLE); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, T= CGv value) { TCGv_ptr tmp =3D tcg_temp_new_ptr(); @@ -5104,11 +5024,6 @@ GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC= _NONE, PPC2_ISA300), GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), #endif -GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206= ), -GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), -GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA20= 6), -GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_IS= A206), GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), #endif /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/tr= anslate/processor-ctrl-impl.c.inc index 8abbb89630..a96c9c87ce 100644 --- a/target/ppc/translate/processor-ctrl-impl.c.inc +++ b/target/ppc/translate/processor-ctrl-impl.c.inc @@ -103,3 +103,103 @@ static bool trans_MSGSYNC(DisasContext *ctx, arg_MSGS= YNC *a) /* interpreted as no-op */ return true; } + +static bool do_doze(DisasContext *ctx, arg_DOZE *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_DOZE); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + return true; +} +TRANS_FLAGS2(PM_ISA206, DOZE, do_doze); + +static bool do_nap(DisasContext *ctx, arg_NAP *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_NAP); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + return true; +} +TRANS_FLAGS2(PM_ISA206, NAP, do_nap); + +static bool do_sleep(DisasContext *ctx, arg_SLEEP *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_SLEEP); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + return true; +} +TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep); + +static bool do_rvwinkle(DisasContext *ctx, arg_RVWINKLE *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_RVWINKLE); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + return true; +} +TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_rvwinkle); + +static bool do_stop(DisasContext *ctx, arg_STOP *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_STOP); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + return true; +} +TRANS_FLAGS2(ISA300, STOP, do_stop); --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787837617; cv=none; d=zohomail.com; s=zohoarc; b=RMJyHP6hAfljYo4aokEWHSUlTMqV/aRl9g5YhFw1K/1KkKuQL1GY7UdPzJ5PiTk+udKoG/0QMlydJWkdp2Jiw3/sskwMnoKkS2ElxFdRqgU5siSiQFVnNhXuBrh6YeQFdMvlnHKpftspc1QUl19Pf673APCZafmy3x6bsmoy2U8= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=Ylif3Uk2PHzuyeKn/ r7jwk5Y/eTeTYjHkGL15GMf84I=; b=ETNUc4TkqOJo4ildWiYNz6gXrfxpClBCO ndYhJkKo34A0z4BYQXeeIk6KeWztJks3eHtn48fjh2wDjOTZM1sNjB731cPkCOiv LimydiMasD141EjHQBPgIgvOARuWPVWMmicWm9Kq1DT+mFKUq5CBFVAxKw2ESE97 YqwQgGVohxYHTDNqwnxOG3bXjqKyy7jmxT5NG5QhOfADotLFaUpNqrxDzAqXFOWN 9CVtznl10V8kRGgxcwb4hxeob/Rj7JbmBY/8aHp0a/HLUErHu7nxH2UYIb7tWrti bH+NzB95q5NlT3lgQ38C9G7rB74dicxL4w1gIaM2WUu/c5UmOzOhQ== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 19/37] target/ppc: Refactor sleep and its variants to use a common helper Date: Thu, 27 Aug 2026 18:59:34 +0530 Message-ID: <20260827133010.278889-20-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfXx68WcjwcfNZZ nbJClQqZ/J3V9sJ189RCCKO1CY6mb2SEHX/8FjTKQkBhLiFxZiSXF49vyJeds1Tpn0a0iBJBpVo +5CtIcNvdfSY8DkpEJVbb+ky+LfqtZ8= X-Proofpoint-GUID: XankmEXju8ffn4qOX9MkuMLbhWZspIXJ X-Proofpoint-ORIG-GUID: WyrqdpDqJimzxK_zvliukuhS1pWoceFP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfXxcwc74kwQf5D OH9shHQInKX9Mr+gSxoUebrbrvrVbOqTvbljL1YWs9SPGsnzTylug+8rWw0MhkZbs4W2GT2Gb4A oPHKU8V6P5UYPqjaVB5/bOw4YT8gwSvbMh/kSQPNEsqFB6fxOFjFEiQTaSxWY9C5kRxcNWg7J9K Cx6S64G4ZNmfs/pYcwhK5KO01oZfkmzz41G8dkSAPd/RQUvb9zoUe0j6xzQMFxkxc0FaZpcOxmQ /QVP+RFvh7+ClxB4LAoBbk8cmo4+QldveN1gyb1un9Frpa3lfIsVBZVXNxyS9vu1I66zUpcZfN/ GWN4PP2o8oGuKYUUWrtfFHs/ivDV5Zx+RORihUPHmr9oEXxhOxWheF/HcbH/RDktXO8ZdkhFbU6 YxVnap/t5vq5uq7gfszszciB3nCamab6jmX1VlhEGuAu4+iEABE1cr1Go3/wH7c+2wcd1mZy4Gr BQK7/j/j8K8v55xdsUw== X-Authority-Analysis: v=2.4 cv=H7brBeYi c=1 sm=1 tr=0 ts=6a903c78 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=VnNF1IyMAAAA:8 a=AYO248uK6yRxx-YkPnAA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 bulkscore=0 adultscore=0 priorityscore=1501 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837618320158500 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo With sleep, doze, nap, rvwinkle and stop instructions moved to decodetree, the helper these instructions used : gen_helper_pminsn, should now be renamed to gen_helper_PMINSN, abiding by the decodetree standards. Do the same. Also refactor their translation routine to use a common do_sleep routine since they share majority of the code. Signed-off-by: Ojaswin Mujoo Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/helper.h | 2 +- target/ppc/tcg-excp_helper.c | 2 +- .../ppc/translate/processor-ctrl-impl.c.inc | 99 +++---------------- 3 files changed, 17 insertions(+), 86 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index e7bf43bf4b..6e14f02598 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -18,7 +18,7 @@ DEF_HELPER_1(rfdi, void, env) DEF_HELPER_1(rfmci, void, env) #if defined(TARGET_PPC64) DEF_HELPER_2(scv, noreturn, env, i32) -DEF_HELPER_2(pminsn, void, env, i32) +DEF_HELPER_2(PMINSN, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index b04f07a637..c4ffa2dfbb 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -459,7 +459,7 @@ void helper_scv(CPUPPCState *env, uint32_t lev) } } =20 -void helper_pminsn(CPUPPCState *env, uint32_t insn) +void helper_PMINSN(CPUPPCState *env, uint32_t insn) { CPUState *cs =3D env_cpu(env); =20 diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/tr= anslate/processor-ctrl-impl.c.inc index a96c9c87ce..cfcca28267 100644 --- a/target/ppc/translate/processor-ctrl-impl.c.inc +++ b/target/ppc/translate/processor-ctrl-impl.c.inc @@ -104,102 +104,33 @@ static bool trans_MSGSYNC(DisasContext *ctx, arg_MSG= SYNC *a) return true; } =20 -static bool do_doze(DisasContext *ctx, arg_DOZE *a) -{ - REQUIRE_64BIT(ctx); - -#if defined(CONFIG_USER_ONLY) - gen_priv_opc(ctx); -#else - TCGv_i32 t; - - REQUIRE_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_DOZE); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ - return true; -} -TRANS_FLAGS2(PM_ISA206, DOZE, do_doze); - -static bool do_nap(DisasContext *ctx, arg_NAP *a) +/* + * Helper to handle DOZE, NAP, SLEEP, RVWINKLE & STOP. Since none of them = use + * any arguments just use a placeholder arg_SLEEP. + */ +static bool do_sleep(DisasContext *ctx, arg_SLEEP *a, powerpc_pm_insn_t ty= pe) { REQUIRE_64BIT(ctx); =20 #if defined(CONFIG_USER_ONLY) gen_priv_opc(ctx); -#else +#elif defined(TARGET_PPC64) TCGv_i32 t; =20 REQUIRE_HV(ctx); translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_NAP); - gen_helper_pminsn(tcg_env, t); + t =3D tcg_constant_i32(type); + gen_helper_PMINSN(tcg_env, t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ - return true; -} -TRANS_FLAGS2(PM_ISA206, NAP, do_nap); - -static bool do_sleep(DisasContext *ctx, arg_SLEEP *a) -{ - REQUIRE_64BIT(ctx); - -#if defined(CONFIG_USER_ONLY) - gen_priv_opc(ctx); #else - TCGv_i32 t; - - REQUIRE_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_SLEEP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ - return true; -} -TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep); - -static bool do_rvwinkle(DisasContext *ctx, arg_RVWINKLE *a) -{ - REQUIRE_64BIT(ctx); - -#if defined(CONFIG_USER_ONLY) - gen_priv_opc(ctx); -#else - TCGv_i32 t; - - REQUIRE_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_RVWINKLE); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ + qemu_build_not_reached(); +#endif return true; } -TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_rvwinkle); - -static bool do_stop(DisasContext *ctx, arg_STOP *a) -{ - REQUIRE_64BIT(ctx); =20 -#if defined(CONFIG_USER_ONLY) - gen_priv_opc(ctx); -#else - TCGv_i32 t; - - REQUIRE_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_STOP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ - return true; -} -TRANS_FLAGS2(ISA300, STOP, do_stop); +TRANS_FLAGS2(PM_ISA206, DOZE, do_sleep, PPC_PM_DOZE); +TRANS_FLAGS2(PM_ISA206, NAP, do_sleep, PPC_PM_NAP); +TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep, PPC_PM_SLEEP); +TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_sleep, PPC_PM_RVWINKLE); +TRANS_FLAGS2(ISA300, STOP, do_sleep, PPC_PM_STOP); --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787837622; cv=none; d=zohomail.com; s=zohoarc; b=afL7RYh+eVXpA37YYMrFyczAUr43Uv1yDwG/8+5pg5A4KRTFeS4ije4vS3EIPpGOVjz8ihLqy1Xv5oGvP4qxL4cEYmKuCyrwr9mJtk+NQK3MDBgk4AIECr8DCuom2SkSodF0n4K5vIsE5mQYSPAjLByeSwNwGErrgWEqqnBd6nE= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=JSv/KLof2lIIQnJwF 4g+usV0OXBdd9l74NUEFIWSBiU=; b=WmUNHD7/13Woq9FsFX7c9XtJq+N4meAn3 VKlKkjG43K5aCpd9qfiwsEDgV53tjexvuTKmJJSuS7ufrcc6B9WlsZ5F+AZ340Sm qa8SOLq+FLcaT/sO6ldnddycwDyrye+lciiINA42DrY/hZbekXHPxbTXJmt4QsWc +zebJFt7M7pliMVMIrN6Ia8j4o+DDAwkOLTrlhnAnDMZ+CNfaEJmNSdRk/YSZgh/ OYPIzkumA5d9O1SxiNpA1WfJseCZHwZp6YMZtbJMJZJxCYrIra7RhS2kBLPQR9G6 DWr8AiPeBy4v0lsRHSgdJ/E8zAp4SPxRjy/pfpeC4Ui1q/E3EdNNg== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 20/37] target/ppc: Move Condition Register access instructions to decodetree. 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Signed-off-by: Shivang Upadhyay Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 8 +++ target/ppc/translate.c | 62 ----------------- target/ppc/translate/fixedpoint-impl.c.inc | 78 ++++++++++++++++++++++ 3 files changed, 86 insertions(+), 62 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index b833244932..137432ed96 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -70,6 +70,9 @@ %dx_d 6:s10 16:5 0:1 @DX ...... rt:5 ..... .......... ..... . &DX d=3D%d= x_d =20 +&XFX rt fxm +@XFX ...... rt:5 . fxm:8 ...... ..... . &XFX + %md_sh 1:1 11:5 %md_mb 5:1 6:5 &MD rs ra sh mb rc @@ -648,6 +651,11 @@ FSEL 111111 ..... ..... ..... ..... 10111 .= @A =20 ### Move To/From System Register Instructions =20 +MFCR 011111 ..... 0.... ....- 0000010011 - @XFX +MFOCR 011111 ..... 1.... ....- 0000010011 - @XFX +MTCRF 011111 ..... 0.... ....- 0010010000 - @XFX +MTOCRF 011111 ..... 1.... ....- 0010010000 - @XFX + SETBC 011111 ..... ..... ----- 0110000000 - @X_bi SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 9d9823f92d..59e8ecb262 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3131,40 +3131,6 @@ static void gen_mcrxrx(DisasContext *ctx) } #endif =20 -/* mfcr mfocrf */ -static void gen_mfcr(DisasContext *ctx) -{ - uint32_t crm, crn; - - if (likely(ctx->opcode & 0x00100000)) { - crm =3D CRM(ctx->opcode); - if (likely(crm && ((crm & (crm - 1)) =3D=3D 0))) { - crn =3D ctz32(crm); - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]= ); - tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rD(ctx->opcode)], crn * 4); - } - } else { - TCGv_i32 t0 =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(t0, cpu_crf[0]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[1]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[2]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[3]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[4]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[5]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[6]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[7]); - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); - } -} - /* mfmsr */ static void gen_mfmsr(DisasContext *ctx) { @@ -3245,32 +3211,6 @@ static void gen_mftb(DisasContext *ctx) gen_op_mfspr(ctx); } =20 -/* mtcrf mtocrf*/ -static void gen_mtcrf(DisasContext *ctx) -{ - uint32_t crm, crn; - - crm =3D CRM(ctx->opcode); - if (likely((ctx->opcode & 0x00100000))) { - if (crm && ((crm & (crm - 1)) =3D=3D 0)) { - TCGv_i32 temp =3D tcg_temp_new_i32(); - crn =3D ctz32(crm); - tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); - tcg_gen_shri_i32(temp, temp, crn * 4); - tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); - } - } else { - TCGv_i32 temp =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); - for (crn =3D 0 ; crn < 8 ; crn++) { - if (crm & (1 << crn)) { - tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); - tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0= xf); - } - } - } -} - /* mtmsr */ #if defined(TARGET_PPC64) static void gen_mtmsrd(DisasContext *ctx) @@ -5030,11 +4970,9 @@ GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC= _64H), GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), -GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), -GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), #if defined(TARGET_PPC64) GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index f9435f4a00..11d919a21a 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -461,6 +461,84 @@ static bool trans_ADDEX(DisasContext *ctx, arg_X *a) return true; } =20 +static bool trans_MTCRF(DisasContext *ctx, arg_MTCRF *a) +{ + TCGv_i32 temp; + uint32_t crm, crn; + + crm =3D a->fxm; + + temp =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(temp, cpu_gpr[a->rt]); + + for (crn =3D 0 ; crn < 8 ; crn++) { + if (crm & (1 << crn)) { + tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); + tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); + } + } + + return true; +} + +static bool trans_MTOCRF(DisasContext *ctx, arg_MTOCRF *a) +{ + uint32_t crm, crn; + + crm =3D a->fxm; + + /* Checking crm > 0 and set_bits(crm) =3D=3D 1 */ + if (crm && ((crm & (crm - 1)) =3D=3D 0)) { + TCGv_i32 temp =3D tcg_temp_new_i32(); + crn =3D ctz32(crm); + tcg_gen_trunc_tl_i32(temp, cpu_gpr[a->rt]); + tcg_gen_shri_i32(temp, temp, crn * 4); + tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); + } + + return true; +} + +static bool trans_MFOCR(DisasContext *ctx, arg_MFOCR *a) +{ + uint32_t crm, crn; + + crm =3D a->fxm; + + /* Checking crm > 0 and set_bits(crm) =3D=3D 1 */ + if (likely(crm && ((crm & (crm - 1)) =3D=3D 0))) { + crn =3D ctz32(crm); + tcg_gen_extu_i32_tl(cpu_gpr[a->rt], cpu_crf[7 - crn]); + tcg_gen_shli_tl(cpu_gpr[a->rt], + cpu_gpr[a->rt], crn * 4); + } + + return true; +} + +static bool trans_MFCR(DisasContext *ctx, arg_MFCR *a) +{ + TCGv_i32 t0 =3D tcg_temp_new_i32(); + tcg_gen_mov_i32(t0, cpu_crf[0]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[1]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[2]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[3]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[4]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[5]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[6]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[7]); + tcg_gen_extu_i32_tl(cpu_gpr[a->rt], t0); + + return true; +} + static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool comput= e_ca, bool compute_ov, bool compute_rc0) { --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Shivang Upadhyay Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 11 ++++ target/ppc/translate.c | 59 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 45 +++++++++++++++++ 3 files changed, 56 insertions(+), 59 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 137432ed96..5e5490b169 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -516,6 +516,17 @@ CFUGED 011111 ..... ..... ..... 0011011100 - = @X PDEPD 011111 ..... ..... ..... 0010011100 - @X PEXTD 011111 ..... ..... ..... 0010111100 - @X =20 +## Condition Register Instructions + +CRAND 010011 ..... ..... ..... 0100000001 - @X +CROR 010011 ..... ..... ..... 0111000001 - @X +CRNAND 010011 ..... ..... ..... 0011100001 - @X +CRXOR 010011 ..... ..... ..... 0011000001 - @X +CRNOR 010011 ..... ..... ..... 0000100001 - @X +CREQV 010011 ..... ..... ..... 0100100001 - @X +CRANDC 010011 ..... ..... ..... 0010000001 - @X +CRORC 010011 ..... ..... ..... 0110100001 - @X + # Fixed-Point Hash Instructions =20 HASHST 011111 ..... ..... ..... 1011010010 . @X_DW diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 59e8ecb262..c5361d8db5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2920,53 +2920,6 @@ static inline void gen_setlr(DisasContext *ctx, targ= et_ulong nip) tcg_gen_movi_tl(cpu_lr, nip); } =20 -/*** Condition register logical = ***/ -#define GEN_CRLOGIC(name, tcg_op, opc) = \ -static void glue(gen_, name)(DisasContext *ctx) = \ -{ = \ - uint8_t bitmask; = \ - int sh; = \ - TCGv_i32 t0, t1; = \ - sh =3D (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); = \ - t0 =3D tcg_temp_new_i32(); = \ - if (sh > 0) = \ - tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); = \ - else if (sh < 0) = \ - tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); = \ - else = \ - tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); = \ - t1 =3D tcg_temp_new_i32(); = \ - sh =3D (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); = \ - if (sh > 0) = \ - tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); = \ - else if (sh < 0) = \ - tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); = \ - else = \ - tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); = \ - tcg_op(t0, t0, t1); = \ - bitmask =3D 0x08 >> (crbD(ctx->opcode) & 0x03); = \ - tcg_gen_andi_i32(t0, t0, bitmask); = \ - tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); = \ - tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); = \ -} - -/* crand */ -GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); -/* crandc */ -GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); -/* creqv */ -GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); -/* crnand */ -GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); -/* crnor */ -GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); -/* cror */ -GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); -/* crorc */ -GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); -/* crxor */ -GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); - /*** System linkage = ***/ =20 /* rfi (supervisor only) */ @@ -5109,18 +5062,6 @@ GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) #endif =20 -#undef GEN_CRLOGIC -#define GEN_CRLOGIC(name, tcg_op, opc) = \ -GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) -GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), -GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), -GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), -GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), -GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), -GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), -GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), -GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), - #undef GEN_MAC_HANDLER #define GEN_MAC_HANDLER(name, opc2, opc3) = \ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 11d919a21a..d0b3bda97f 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -539,6 +539,51 @@ static bool trans_MFCR(DisasContext *ctx, arg_MFCR *a) return true; } =20 +static bool cr_logic_common(DisasContext *ctx, arg_X *a, + void (*tcg_op)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + uint8_t bitmask; + int sh; + TCGv_i32 t0, t1; + sh =3D (a->rt & 0x03) - (a->ra & 0x03); + t0 =3D tcg_temp_new_i32(); + t1 =3D tcg_temp_new_i32(); + + if (sh > 0) { + tcg_gen_shri_i32(t0, cpu_crf[a->ra >> 2], sh); + } else if (sh < 0) { + tcg_gen_shli_i32(t0, cpu_crf[a->ra >> 2], -sh); + } else { + tcg_gen_mov_i32(t0, cpu_crf[a->ra >> 2]); + } + + sh =3D (a->rt & 0x03) - (a->rb & 0x03); + if (sh > 0) { + tcg_gen_shri_i32(t1, cpu_crf[a->rb >> 2], sh); + } else if (sh < 0) { + tcg_gen_shli_i32(t1, cpu_crf[a->rb >> 2], -sh); + } else { + tcg_gen_mov_i32(t1, cpu_crf[a->rb >> 2]); + } + tcg_op(t0, t0, t1); + + bitmask =3D 0x08 >> (a->rt & 0x03); + tcg_gen_andi_i32(t0, t0, bitmask); + tcg_gen_andi_i32(t1, cpu_crf[a->rt >> 2], ~bitmask); + tcg_gen_or_i32(cpu_crf[a->rt >> 2], t0, t1); + + return true; +} + +TRANS(CRAND, cr_logic_common, tcg_gen_and_i32); +TRANS(CROR, cr_logic_common, tcg_gen_or_i32); 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=N5oFhG2ZFtkOL8EUp upgX5Y6UQHGQifNqch3a133TWA=; b=hQtoEZ64RbqZOZW8c5dmttfjEtpH3vFct dmrtBkiUYi+0wZv7Qm41o1zHx5YlVPL71Pejc6qu0CUSUnLHhozGS63F885Q1Llh ubRgF1kCVzfvU8zr9tyhqdapDpGP4exZma6QYVK1OOgfsdPzrEpJE7dK99IM0bbQ TNDOTXd4T0uWbVeKvKAc0PbHO6OlN60E2qvbzJoz71mcXG4Xh515Z9wkMPx9toQc iCZIe8TQ/pANaeRApGEf6gvNO/SFATXX0VGb1XHZUZgZwqEvdxiBR7QWOpsXB0ni D8CSkeKkJJfbPGOT7bdNkQiQXttUNLinyUf40vgFQuHkz101J88/w== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 22/37] target/ppc: make do_ea_calc_ra available for 32 bit builds Date: Thu, 27 Aug 2026 18:59:37 +0530 Message-ID: <20260827133010.278889-23-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: 1_NsHOK8BHzOHdphueO9Xou5g7kRc7Ca X-Proofpoint-ORIG-GUID: jlCx5NnR4DUSqpJ0hZO_LA_4Q9Y8Dg4O X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX/r9nfwe7esUK bSvGJpKv+XMnHmgXtazlb90GUo1e5kgKiiKyQpMScSayLAwQuuhAB3XIQ1UHp5gP705EQm3WhQP 5r0b/76dmHk3yftrTN0mGyW4RLDtZTGQPLFpwr9A5WFORb1z+w1iaZTohpm9gYE31ejViCyEq5S x0buVW++tO6M45okmeFVQXWFBNY8AwQu+rK9mPRboxYzVOMG18vOKZNFbEkrd8itWO5LRGh/2u0 dvKuhDtuX1u34vpxdipPuSk2GDvE4XPeGEwmlHXc/0bRSuBzuaCKrCRrbStwF5TZCIkFi79OP7U IMyhwJcQsvItBhXvL0NYKv62xRKZwPFfmzoAJ93Y/J8VPFPlPJsMwZr2rXlzGeqPHNv/JnuwJ6N RirbzruB27GQ6xem5MTrcJe/tTwogDd7KIBPqen1ogkpVyOYtvnjuG4kibwJXgcOyWvBryzXw9W qSpNcmJRkrVMTyuy9uA== X-Authority-Analysis: v=2.4 cv=QsRuG1yd c=1 sm=1 tr=0 ts=6a903c8c cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=0RWl5roMYX471uEN2lYA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX3jt1KkH+O8lG ASK5nXlTB0Ag9L0IP/5VWa4IFsh4gEAD0ERfFWnYM6JIHu18wo875ai3sQSsvaIMe4NOsjQoJ6m FGEA0V4PdULxnU3dHonNoAuvfTnkkpQ= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837684724158500 Content-Type: text/plain; charset="utf-8" There is no reason to keep do_ea_calc_ra exclusive to TARGET_PPC64. Make it available for PPC32 builds. Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c5361d8db5..c45883ac30 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2397,7 +2397,6 @@ static TCGv do_ea_calc(DisasContext *ctx, int ra, TCG= v displ) return ea; } =20 -#if defined(TARGET_PPC64) /* EA <- (ra =3D=3D 0) ? 0 : GPR[ra] */ static TCGv do_ea_calc_ra(DisasContext *ctx, int ra) { @@ -2411,7 +2410,6 @@ static TCGv do_ea_calc_ra(DisasContext *ctx, int ra) } return EA; } -#endif =20 /*** Integer load = ***/ #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Shivang Upadhyay Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/helper.h | 6 +- target/ppc/insn32.decode | 7 ++ target/ppc/mem_helper.c | 6 +- target/ppc/translate.c | 102 --------------------- target/ppc/translate/fixedpoint-impl.c.inc | 102 +++++++++++++++++++++ 5 files changed, 115 insertions(+), 108 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6e14f02598..18ef7786a4 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -45,9 +45,9 @@ DEF_HELPER_1(check_tlb_flush_global, void, env) =20 DEF_HELPER_3(lmw, void, env, tl, i32) DEF_HELPER_FLAGS_3(stmw, TCG_CALL_NO_WG, void, env, tl, i32) -DEF_HELPER_4(lsw, void, env, tl, i32, i32) -DEF_HELPER_5(lswx, void, env, tl, i32, i32, i32) -DEF_HELPER_FLAGS_4(stsw, TCG_CALL_NO_WG, void, env, tl, i32, i32) +DEF_HELPER_4(LSW, void, env, tl, i32, i32) +DEF_HELPER_5(LSWX, void, env, tl, i32, i32, i32) +DEF_HELPER_FLAGS_4(STSW, TCG_CALL_NO_WG, void, env, tl, i32, i32) DEF_HELPER_FLAGS_3(dcbz, TCG_CALL_NO_WG, void, env, tl, int) #ifdef TARGET_PPC64 DEF_HELPER_FLAGS_2(dcbzl, TCG_CALL_NO_WG, void, env, tl) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 5e5490b169..a88ba1fce1 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -527,6 +527,13 @@ CREQV 010011 ..... ..... ..... 0100100001 - = @X CRANDC 010011 ..... ..... ..... 0010000001 - @X CRORC 010011 ..... ..... ..... 0110100001 - @X =20 +# Fixed Point Move Assist Instructions + +LSWI 011111 ..... ..... ..... 1 001010101 - @X +LSWX 011111 ..... ..... ..... 1 000010101 - @X +STSWI 011111 ..... ..... ..... 1 011010101 - @X +STSWX 011111 ..... ..... ..... 1 010010101 - @X + # Fixed-Point Hash Instructions =20 HASHST 011111 ..... ..... ..... 1011010010 . @X_DW diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 8ad6945590..10c648cf06 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -190,7 +190,7 @@ static void do_lsw(CPUPPCState *env, target_ulong addr,= uint32_t nb, env->gpr[reg] =3D val; } =20 -void helper_lsw(CPUPPCState *env, target_ulong addr, +void helper_LSW(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg) { do_lsw(env, addr, nb, reg, GETPC()); @@ -202,7 +202,7 @@ void helper_lsw(CPUPPCState *env, target_ulong addr, * this is valid, but rA won't be loaded. For now, I'll follow the * spec... */ -void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg, +void helper_LSWX(CPUPPCState *env, target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb) { if (likely(xer_bc !=3D 0)) { @@ -218,7 +218,7 @@ void helper_lswx(CPUPPCState *env, target_ulong addr, u= int32_t reg, } } =20 -void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb, +void helper_STSW(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg) { uintptr_t raddr =3D GETPC(); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c45883ac30..d17d77a9d9 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2595,104 +2595,6 @@ static void gen_stmw(DisasContext *ctx) gen_helper_stmw(tcg_env, t0, t1); } =20 -/*** Integer load and store strings = ***/ - -/* lswi */ -/* - * PowerPC32 specification says we must generate an exception if rA is - * in the range of registers to be loaded. In an other hand, IBM says - * this is valid, but rA won't be loaded. For now, I'll follow the - * spec... - */ -static void gen_lswi(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1, t2; - int nb =3D NB(ctx->opcode); - int start =3D rD(ctx->opcode); - int ra =3D rA(ctx->opcode); - int nr; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - if (nb =3D=3D 0) { - nb =3D 32; - } - nr =3D DIV_ROUND_UP(nb, 4); - if (unlikely(lsw_reg_in_range(start, nr, ra))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - gen_addr_register(ctx, t0); - t1 =3D tcg_constant_i32(nb); - t2 =3D tcg_constant_i32(start); - gen_helper_lsw(tcg_env, t0, t1, t2); -} - -/* lswx */ -static void gen_lswx(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1, t2, t3; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - t1 =3D tcg_constant_i32(rD(ctx->opcode)); - t2 =3D tcg_constant_i32(rA(ctx->opcode)); - t3 =3D tcg_constant_i32(rB(ctx->opcode)); - gen_helper_lswx(tcg_env, t0, t1, t2, t3); -} - -/* stswi */ -static void gen_stswi(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1, t2; - int nb =3D NB(ctx->opcode); - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - gen_addr_register(ctx, t0); - if (nb =3D=3D 0) { - nb =3D 32; - } - t1 =3D tcg_constant_i32(nb); - t2 =3D tcg_constant_i32(rS(ctx->opcode)); - gen_helper_stsw(tcg_env, t0, t1, t2); -} - -/* stswx */ -static void gen_stswx(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1, t2; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - t1 =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t1, cpu_xer); - tcg_gen_andi_i32(t1, t1, 0x7F); - t2 =3D tcg_constant_i32(rS(ctx->opcode)); - gen_helper_stsw(tcg_env, t0, t1, t2); -} =20 #if !defined(CONFIG_USER_ONLY) static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) @@ -4901,10 +4803,6 @@ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000,= PPC_NONE, PPC2_ISA205), GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), -GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), -GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), -GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index d0b3bda97f..4b79e24f6f 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -584,6 +584,108 @@ TRANS(CRANDC, cr_logic_common, tcg_gen_andc_i32); TRANS(CREQV, cr_logic_common, tcg_gen_eqv_i32); TRANS(CRORC, cr_logic_common, tcg_gen_orc_i32); =20 +/*** Integer load and store strings = ***/ + +/* lswi */ +static bool trans_LSWI(DisasContext *ctx, arg_LSWI *a) +{ + TCGv t0; + TCGv_i32 t1, t2; + int nb =3D a->rb; + int start =3D a->rt; + int ra =3D a->ra; + int nr; + + REQUIRE_INSNS_FLAGS(ctx, STRING); + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + if (nb =3D=3D 0) { + nb =3D 32; + } + nr =3D DIV_ROUND_UP(nb, 4); + if (unlikely(lsw_reg_in_range(start, nr, ra))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + t0 =3D do_ea_calc_ra(ctx, ra); + t1 =3D tcg_constant_i32(nb); + t2 =3D tcg_constant_i32(start); + gen_helper_LSW(tcg_env, t0, t1, t2); + + return true; +} + +/* lswx */ +static bool trans_LSWX(DisasContext *ctx, arg_LSWX *a) +{ + TCGv t0; + TCGv_i32 t1, t2, t3; + + REQUIRE_INSNS_FLAGS(ctx, STRING); + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + + gen_set_access_type(ctx, ACCESS_INT); + t0 =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + t1 =3D tcg_constant_i32(a->rt); + t2 =3D tcg_constant_i32(a->ra); + t3 =3D tcg_constant_i32(a->rb); + gen_helper_LSWX(tcg_env, t0, t1, t2, t3); + + return true; +} + +/* stswi */ +static bool trans_STSWI(DisasContext *ctx, arg_STSWI *a) +{ + TCGv t0; + TCGv_i32 t1, t2; + int nb =3D a->rb; + + REQUIRE_INSNS_FLAGS(ctx, STRING); + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + t0 =3D do_ea_calc_ra(ctx, a->ra); + if (nb =3D=3D 0) { + nb =3D 32; + } + t1 =3D tcg_constant_i32(nb); + t2 =3D tcg_constant_i32(a->rt); + gen_helper_STSW(tcg_env, t0, t1, t2); + + return true; +} + +/* stswx */ +static bool trans_STSWX(DisasContext *ctx, arg_STSWX *a) +{ + TCGv t0; + TCGv_i32 t1, t2; + + REQUIRE_INSNS_FLAGS(ctx, STRING); + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + t0 =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=xGIlndidEzXizoHht q+D1X1zy/cbthotq9MOS0+UzHg=; b=CTCsH8I9iB99X96kV+5AmTVdumJPVCbco 6R1PBLW3CiecSkevLNdtZ5GqQO+oerELMr1QnMt8ugX4+nsIWPITKYPj/OvF8zQX 0TzSuZT8NGVSQAB9xVADsrWi5dyOV9+QPrvdoWTfqKGDPHADzuOjYjiFsvy6r6lb kKernK0Lbo/P3IK1hK2DluAhaKs5t1vQ6fMlCKQTg/Yiuj/sH8JFD49DLzoA0Iai zvJOaWBlkQ91FHM1Y+AEFS9uHtTX+UkYOk4Lygu2dnoBBbkqvTUIChoo/6+2GOIb 9s/Tp+hvZEv2CZ3FmO6ciAQBNK2bEfZVSgI9fCDEMJ7ghawHCcD5w== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 24/37] target/ppc: Move VMX integer arithmetic and BCD instructions to decodetree. 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Signed-off-by: Shivang Upadhyay Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/helper.h | 30 +-- target/ppc/insn32.decode | 39 ++++ target/ppc/int_helper.c | 32 +-- target/ppc/translate/vmx-impl.c.inc | 299 ++++++++++++---------------- target/ppc/translate/vmx-ops.c.inc | 22 -- 5 files changed, 199 insertions(+), 223 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 18ef7786a4..7da752c69b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -349,21 +349,21 @@ DEF_HELPER_FLAGS_3(vshasigmaw, TCG_CALL_NO_RWG, void,= avr, avr, i32) DEF_HELPER_FLAGS_3(vshasigmad, TCG_CALL_NO_RWG, void, avr, avr, i32) DEF_HELPER_FLAGS_4(vpermxor, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) =20 -DEF_HELPER_FLAGS_4(bcdadd, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdsub, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdcfn, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdctn, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdcfz, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdctz, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdcfsq, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdctsq, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdcpsgn, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdsetsgn, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcds, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdus, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdsr, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdtrunc, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdutrunc, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDADD, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDSUB, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCFN, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCTN, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCFZ, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCTZ, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCFSQ, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCTSQ, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDCPSGN, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDSETSGN, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDS, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDUS, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDSR, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDTRUNC, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDUTRUNC, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) =20 DEF_HELPER_4(XSADDDP, void, env, vsr, vsr, vsr) DEF_HELPER_5(xsaddqp, void, env, i32, vsr, vsr, vsr) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index a88ba1fce1..69d60605bd 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -90,6 +90,9 @@ &VX vrt vra vrb @VX ...... vrt:5 vra:5 vrb:5 .......... . &VX =20 +&VX_ps vrt vra vrb ps +@VX_ps ...... vrt:5 vra:5 vrb:5 . ps:1 ........ . &VX_ps + &VX_bf bf vra vrb @VX_bf ...... bf:3 .. vra:5 vrb:5 ........... &VX_bf =20 @@ -108,6 +111,9 @@ &VX_tb vrt vrb @VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb =20 +&VX_tb_ps vrt vrb ps +@VX_tb_ps ...... vrt:5 ..... vrb:5 . ps:1 ......... &VX_t= b_ps + &X rt ra rb @X ...... rt:5 ra:5 rb:5 .......... . &X =20 @@ -991,6 +997,10 @@ VADDSBS 000100 ..... ..... ..... 01100000000 = @VX VADDSHS 000100 ..... ..... ..... 01101000000 @VX VADDSWS 000100 ..... ..... ..... 01110000000 @VX =20 +VADDUBM 000100 ..... ..... ..... 00000000000 @VX +VADDUHM 000100 ..... ..... ..... 00001000000 @VX +VADDUWM 000100 ..... ..... ..... 00010000000 @VX +VADDUDM 000100 ..... ..... ..... 00011000000 @VX VADDUBS 000100 ..... ..... ..... 01000000000 @VX VADDUHS 000100 ..... ..... ..... 01001000000 @VX VADDUWS 000100 ..... ..... ..... 01010000000 @VX @@ -1006,6 +1016,10 @@ VSUBSBS 000100 ..... ..... ..... 11100000000= @VX VSUBSHS 000100 ..... ..... ..... 11101000000 @VX VSUBSWS 000100 ..... ..... ..... 11110000000 @VX =20 +VSUBUBM 000100 ..... ..... ..... 10000000000 @VX +VSUBUHM 000100 ..... ..... ..... 10001000000 @VX +VSUBUWM 000100 ..... ..... ..... 10010000000 @VX +VSUBUDM 000100 ..... ..... ..... 10011000000 @VX VSUBUBS 000100 ..... ..... ..... 11000000000 @VX VSUBUHS 000100 ..... ..... ..... 11001000000 @VX VSUBUWS 000100 ..... ..... ..... 11010000000 @VX @@ -1099,6 +1113,13 @@ VMULHSD 000100 ..... ..... ..... 01111001001= @VX VMULHUD 000100 ..... ..... ..... 01011001001 @VX VMULLD 000100 ..... ..... ..... 00111001001 @VX =20 +VMULUWM 000100 ..... ..... ..... 00010001001 @VX + +VMUL10UQ 000100 ..... ..... ..... 01000000001 @VX +VMUL10EUQ 000100 ..... ..... ..... 01001000001 @VX +VMUL10ECUQ 000100 ..... ..... ..... 00001000001 @VX +VMUL10CUQ 000100 ..... ..... ..... 00000000001 @VX + ## Vector Multiply-Sum Instructions =20 VMSUMUBM 000100 ..... ..... ..... ..... 100100 @VA @@ -1141,6 +1162,24 @@ VPKSWSS 000100 ..... ..... ..... 0011100111 = 0 @VX VPKSDSS 000100 ..... ..... ..... 1011100111 0 @VX VPKPX 000100 ..... ..... ..... 0110000111 0 @VX =20 +## Decimal Integer Arithmetic Instructions + +BCDADD 000100 ..... ..... ..... 1.000000001 @VX_ps +BCDSUB 000100 ..... ..... ..... 1.001000001 @VX_ps +BCDUS 000100 ..... ..... ..... 10010000001 @VX +BCDS 000100 ..... ..... ..... 1.011000001 @VX_ps +BCDCTSQ 000100 ..... 00000 ..... 10110000001 @VX_tb +BCDCTN 000100 ..... 00101 ..... 10110000001 @VX_tb +BCDCFSQ 000100 ..... 00010 ..... 1.110000001 @VX_tb_ps +BCDCTZ 000100 ..... 00100 ..... 1.110000001 @VX_tb_ps +BCDCFZ 000100 ..... 00110 ..... 1.110000001 @VX_tb_ps +BCDCFN 000100 ..... 00111 ..... 1.110000001 @VX_tb_ps +BCDSETSGN 000100 ..... 11111 ..... 1.110000001 @VX_tb_ps +BCDCPSGN 000100 ..... ..... ..... 01101000001 @VX +BCDSR 000100 ..... ..... ..... 1.111000001 @VX_ps +BCDTRUNC 000100 ..... ..... ..... 1.100000001 @VX_ps +BCDUTRUNC 000100 ..... ..... ..... 10101000001 @VX + # VSX Load/Store Instructions =20 LXSD 111001 ..... ..... .............. 10 @DS diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 8e8076a92c..86346f5b9a 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -2348,7 +2348,7 @@ static void bcd_sub_mag(ppc_avr_t *t, ppc_avr_t *a, p= pc_avr_t *b, int *invalid, *overflow =3D carry; } =20 -uint32_t helper_bcdadd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t= ps) +uint32_t helper_BCDADD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t= ps) { =20 int sgna =3D bcd_get_sgn(a); @@ -2395,7 +2395,7 @@ uint32_t helper_bcdadd(ppc_avr_t *r, ppc_avr_t *a, p= pc_avr_t *b, uint32_t ps) return cr; } =20 -uint32_t helper_bcdsub(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t= ps) +uint32_t helper_BCDSUB(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t= ps) { ppc_avr_t bcopy =3D *b; int sgnb =3D bcd_get_sgn(b); @@ -2406,10 +2406,10 @@ uint32_t helper_bcdsub(ppc_avr_t *r, ppc_avr_t *a,= ppc_avr_t *b, uint32_t ps) } /* else invalid ... defer to bcdadd code for proper handling */ =20 - return helper_bcdadd(r, a, &bcopy, ps); + return helper_BCDADD(r, a, &bcopy, ps); } =20 -uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCFN(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr =3D 0; @@ -2445,7 +2445,7 @@ uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, ui= nt32_t ps) return cr; } =20 -uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCTN(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr =3D 0; @@ -2479,7 +2479,7 @@ uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, ui= nt32_t ps) return cr; } =20 -uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCFZ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr =3D 0; @@ -2523,7 +2523,7 @@ uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, ui= nt32_t ps) return cr; } =20 -uint32_t helper_bcdctz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCTZ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr =3D 0; @@ -2582,7 +2582,7 @@ static inline int ucmp128(uint64_t alo, uint64_t ahi, (ahi > bhi ? 1 : -1); } =20 -uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCFSQ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr; @@ -2640,7 +2640,7 @@ uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, u= int32_t ps) return cr; } =20 -uint32_t helper_bcdctsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCTSQ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { uint8_t i; int cr; @@ -2680,7 +2680,7 @@ uint32_t helper_bcdctsq(ppc_avr_t *r, ppc_avr_t *b, u= int32_t ps) return cr; } =20 -uint32_t helper_bcdcpsgn(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_= t ps) +uint32_t helper_BCDCPSGN(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_= t ps) { int i; int invalid =3D 0; @@ -2703,7 +2703,7 @@ uint32_t helper_bcdcpsgn(ppc_avr_t *r, ppc_avr_t *a, = ppc_avr_t *b, uint32_t ps) return bcd_cmp_zero(r); } =20 -uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDSETSGN(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int sgnb =3D bcd_get_sgn(b); =20 @@ -2717,7 +2717,7 @@ uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b,= uint32_t ps) return bcd_cmp_zero(r); } =20 -uint32_t helper_bcds(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDS(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps) { int cr; int i =3D a->VsrSB(7); @@ -2753,7 +2753,7 @@ uint32_t helper_bcds(ppc_avr_t *r, ppc_avr_t *a, ppc_= avr_t *b, uint32_t ps) return cr; } =20 -uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t p= s) +uint32_t helper_BCDUS(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t p= s) { int cr; int i; @@ -2790,7 +2790,7 @@ uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc= _avr_t *b, uint32_t ps) return cr; } =20 -uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t p= s) +uint32_t helper_BCDSR(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t p= s) { int cr; int unused =3D 0; @@ -2836,7 +2836,7 @@ uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc= _avr_t *b, uint32_t ps) return cr; } =20 -uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_= t ps) +uint32_t helper_BCDTRUNC(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_= t ps) { uint64_t mask; uint32_t ox_flag =3D 0; @@ -2869,7 +2869,7 @@ uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, = ppc_avr_t *b, uint32_t ps) return bcd_cmp_zero(&ret) | ox_flag; } =20 -uint32_t helper_bcdutrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32= _t ps) +uint32_t helper_BCDUTRUNC(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32= _t ps) { int i; uint64_t mask; diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 65230f3461..4e7fe22156 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -142,7 +142,8 @@ static void gen_mtvscr(DisasContext *ctx) gen_helper_mtvscr(tcg_env, val); } =20 -static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry) +static bool do_vx_vmul10(DisasContext *ctx, arg_VX *a, + bool add_cin, bool ret_carry) { TCGv_i64 t0; TCGv_i64 t1; @@ -150,10 +151,7 @@ static void gen_vx_vmul10(DisasContext *ctx, bool add_= cin, bool ret_carry) TCGv_i64 avr; TCGv_i64 ten, z; =20 - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } + REQUIRE_VECTOR(ctx); =20 t0 =3D tcg_temp_new_i64(); t1 =3D tcg_temp_new_i64(); @@ -163,54 +161,32 @@ static void gen_vx_vmul10(DisasContext *ctx, bool add= _cin, bool ret_carry) z =3D tcg_constant_i64(0); =20 if (add_cin) { - get_avr64(avr, rA(ctx->opcode), false); + get_avr64(avr, a->vra, false); tcg_gen_mulu2_i64(t0, t1, avr, ten); - get_avr64(avr, rB(ctx->opcode), false); + get_avr64(avr, a->vrb, false); tcg_gen_andi_i64(t2, avr, 0xF); tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); - set_avr64(rD(ctx->opcode), avr, false); + set_avr64(a->vrt, avr, false); } else { - get_avr64(avr, rA(ctx->opcode), false); + get_avr64(avr, a->vra, false); tcg_gen_mulu2_i64(avr, t2, avr, ten); - set_avr64(rD(ctx->opcode), avr, false); + set_avr64(a->vrt, avr, false); } =20 if (ret_carry) { - get_avr64(avr, rA(ctx->opcode), true); + get_avr64(avr, a->vra, true); tcg_gen_mulu2_i64(t0, t1, avr, ten); tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); - set_avr64(rD(ctx->opcode), avr, false); - set_avr64(rD(ctx->opcode), z, true); + set_avr64(a->vrt, avr, false); + set_avr64(a->vrt, z, true); } else { - get_avr64(avr, rA(ctx->opcode), true); + get_avr64(avr, a->vra, true); tcg_gen_mul_i64(t0, avr, ten); tcg_gen_add_i64(avr, t0, t2); - set_avr64(rD(ctx->opcode), avr, true); + set_avr64(a->vrt, avr, true); } -} - -#define GEN_VX_VMUL10(name, add_cin, ret_carry) \ - static void glue(gen_, name)(DisasContext *ctx) \ - { gen_vx_vmul10(ctx, add_cin, ret_carry); } - -GEN_VX_VMUL10(vmul10uq, 0, 0); -GEN_VX_VMUL10(vmul10euq, 1, 0); -GEN_VX_VMUL10(vmul10cuq, 0, 1); -GEN_VX_VMUL10(vmul10ecuq, 1, 1); =20 -#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - tcg_op(vece, \ - avr_full_offset(rD(ctx->opcode)), \ - avr_full_offset(rA(ctx->opcode)), \ - avr_full_offset(rB(ctx->opcode)), \ - 16, 16); \ + return true; } =20 #define GEN_VXFORM(name, opc2, opc3) \ @@ -338,19 +314,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], = rb); \ } =20 -GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0); -GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \ - vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800) -GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1); -GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \ - vmul10ecuq, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2); -GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3); -GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16); -GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17); -GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18); -GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19); - static bool do_vmrg(DisasContext *ctx, arg_VX *a, void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr)) { @@ -370,6 +333,38 @@ TRANS_FLAGS(ALTIVEC, VMRGLB, do_vmrg, gen_helper_VMRGL= B); TRANS_FLAGS(ALTIVEC, VMRGLH, do_vmrg, gen_helper_VMRGLH); TRANS_FLAGS(ALTIVEC, VMRGLW, do_vmrg, gen_helper_VMRGLW); =20 +static bool do_vx_vaddsubm(DisasContext *ctx, arg_VX *a, MemOp vece, + void (*gen_op)(unsigned, uint32_t, uint32_t, + uint32_t, uint32_t, uint32_t)) +{ + REQUIRE_VECTOR(ctx); + + gen_op(vece, + avr_full_offset(a->vrt), + avr_full_offset(a->vra), + avr_full_offset(a->vrb), + 16, 16); + + return true; +} + +TRANS_FLAGS(ALTIVEC, VADDUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_add) +TRANS_FLAGS(ALTIVEC, VADDUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_add) +TRANS_FLAGS(ALTIVEC, VADDUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_add) +TRANS_FLAGS2(ALTIVEC_207, VADDUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_add) + +TRANS_FLAGS(ALTIVEC, VSUBUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_sub) +TRANS_FLAGS(ALTIVEC, VSUBUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_sub) +TRANS_FLAGS(ALTIVEC, VSUBUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_sub) +TRANS_FLAGS2(ALTIVEC_207, VSUBUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_sub) + +TRANS_FLAGS2(ALTIVEC_207, VMULUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_mul) + +TRANS_FLAGS2(ISA300, VMUL10CUQ, do_vx_vmul10, false, true) +TRANS_FLAGS2(ISA300, VMUL10ECUQ, do_vx_vmul10, true, true) +TRANS_FLAGS2(ISA300, VMUL10UQ, do_vx_vmul10, false, false) +TRANS_FLAGS2(ISA300, VMUL10EUQ, do_vx_vmul10, true, false) + static void trans_vmrgew(DisasContext *ctx) { int VT =3D rD(ctx->opcode); @@ -684,7 +679,6 @@ static void trans_vclzd(DisasContext *ctx) set_avr64(VT, avr, false); } =20 -GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2); GEN_VXFORM(vsrv, 2, 28); GEN_VXFORM(vslv, 2, 29); GEN_VXFORM(vslo, 6, 16); @@ -2523,126 +2517,93 @@ GEN_VXFORM(vpmsumb, 4, 16) GEN_VXFORM(vpmsumh, 4, 17) GEN_VXFORM(vpmsumw, 4, 18) =20 -#define GEN_BCD(op) \ -static void gen_##op(DisasContext *ctx) \ -{ \ - TCGv_ptr ra, rb, rd; \ - TCGv_i32 ps; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - ra =3D gen_avr_ptr(rA(ctx->opcode)); \ - rb =3D gen_avr_ptr(rB(ctx->opcode)); \ - rd =3D gen_avr_ptr(rD(ctx->opcode)); \ - \ - ps =3D tcg_constant_i32((ctx->opcode & 0x200) !=3D 0); \ - \ - gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \ -} - -#define GEN_BCD2(op) \ -static void gen_##op(DisasContext *ctx) \ -{ \ - TCGv_ptr rd, rb; \ - TCGv_i32 ps; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - rb =3D gen_avr_ptr(rB(ctx->opcode)); \ - rd =3D gen_avr_ptr(rD(ctx->opcode)); \ - \ - ps =3D tcg_constant_i32((ctx->opcode & 0x200) !=3D 0); \ - \ - gen_helper_##op(cpu_crf[6], rd, rb, ps); \ -} - -GEN_BCD(bcdadd) -GEN_BCD(bcdsub) -GEN_BCD2(bcdcfn) -GEN_BCD2(bcdctn) -GEN_BCD2(bcdcfz) -GEN_BCD2(bcdctz) -GEN_BCD2(bcdcfsq) -GEN_BCD2(bcdctsq) -GEN_BCD2(bcdsetsgn) -GEN_BCD(bcdcpsgn); -GEN_BCD(bcds); -GEN_BCD(bcdus); -GEN_BCD(bcdsr); -GEN_BCD(bcdtrunc); -GEN_BCD(bcdutrunc); - -static void gen_xpnd04_1(DisasContext *ctx) -{ - switch (opc4(ctx->opcode)) { - case 0: - gen_bcdctsq(ctx); - break; - case 2: - gen_bcdcfsq(ctx); - break; - case 4: - gen_bcdctz(ctx); - break; - case 5: - gen_bcdctn(ctx); - break; - case 6: - gen_bcdcfz(ctx); - break; - case 7: - gen_bcdcfn(ctx); - break; - case 31: - gen_bcdsetsgn(ctx); - break; - default: - gen_invalid(ctx); - break; - } +static bool do_bcd_ps(DisasContext *ctx, arg_VX_ps *a, + void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32)) +{ + TCGv_ptr ra, rb, rd; + TCGv_i32 ps; + + REQUIRE_VECTOR(ctx); + + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + ps =3D tcg_constant_i32(a->ps); + + helper(cpu_crf[6], rd, ra, rb, ps); + return true; } =20 -static void gen_xpnd04_2(DisasContext *ctx) -{ - switch (opc4(ctx->opcode)) { - case 0: - gen_bcdctsq(ctx); - break; - case 2: - gen_bcdcfsq(ctx); - break; - case 4: - gen_bcdctz(ctx); - break; - case 6: - gen_bcdcfz(ctx); - break; - case 7: - gen_bcdcfn(ctx); - break; - case 31: - gen_bcdsetsgn(ctx); - break; - default: - gen_invalid(ctx); - break; - } +static bool do_bcd(DisasContext *ctx, arg_VX *a, + void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32)) +{ + TCGv_ptr ra, rb, rd; + TCGv_i32 ps; + + REQUIRE_VECTOR(ctx); + + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + ps =3D tcg_constant_i32(0); + + helper(cpu_crf[6], rd, ra, rb, ps); + return true; } =20 -GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \ - bcdadd, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \ - bcdsub, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \ - bcds, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \ - bcdus, PPC_NONE, PPC2_ISA300) +static bool do_bcd_tb(DisasContext *ctx, arg_VX_tb *a, + void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32)) +{ + TCGv_ptr rd, rb; + TCGv_i32 ps; + + REQUIRE_VECTOR(ctx); + + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + + ps =3D tcg_constant_i32(0); + + helper(cpu_crf[6], rd, rb, ps); + + return true; +} + +static bool do_bcd_tb_ps(DisasContext *ctx, arg_VX_tb_ps *a, + void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32)) +{ + TCGv_ptr rd, rb; + TCGv_i32 ps; + + REQUIRE_VECTOR(ctx); + + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + + ps =3D tcg_constant_i32(a->ps); + + helper(cpu_crf[6], rd, rb, ps); + + return true; +} + +TRANS_FLAGS2(ALTIVEC_207, BCDADD, do_bcd_ps, gen_helper_BCDADD) +TRANS_FLAGS2(ALTIVEC_207, BCDSUB, do_bcd_ps, gen_helper_BCDSUB) +TRANS_FLAGS2(ISA300, BCDUS, do_bcd, gen_helper_BCDUS) +TRANS_FLAGS2(ISA300, BCDS, do_bcd_ps, gen_helper_BCDS) +TRANS_FLAGS2(ISA300, BCDCFN, do_bcd_tb_ps, gen_helper_BCDCFN) +TRANS_FLAGS2(ISA300, BCDCTN, do_bcd_tb, gen_helper_BCDCTN) +TRANS_FLAGS2(ISA300, BCDCFZ, do_bcd_tb_ps, gen_helper_BCDCFZ) +TRANS_FLAGS2(ISA300, BCDCTZ, do_bcd_tb_ps, gen_helper_BCDCTZ) +TRANS_FLAGS2(ISA300, BCDCFSQ, do_bcd_tb_ps, gen_helper_BCDCFSQ) +TRANS_FLAGS2(ISA300, BCDCTSQ, do_bcd_tb, gen_helper_BCDCTSQ) +TRANS_FLAGS2(ISA300, BCDSETSGN, do_bcd_tb_ps, gen_helper_BCDSETSGN) +TRANS_FLAGS2(ISA300, BCDCPSGN, do_bcd, gen_helper_BCDCPSGN) +TRANS_FLAGS2(ISA300, BCDTRUNC, do_bcd_ps, gen_helper_BCDTRUNC) +TRANS_FLAGS2(ISA300, BCDUTRUNC, do_bcd, gen_helper_BCDUTRUNC) +TRANS_FLAGS2(ISA300, BCDSR, do_bcd_ps, gen_helper_BCDSR) =20 static void gen_vsbox(DisasContext *ctx) { @@ -3502,5 +3463,3 @@ TRANS_FLAGS2(ISA310, VMODUQ, do_vx_helper, gen_helper= _VMODUQ) #undef GEN_VXFORM_NOA #undef GEN_VXFORM_UIMM #undef GEN_VAFORM_PAIRED - -#undef GEN_BCD2 diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-= ops.c.inc index 2820976c0f..c1951c6975 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -24,39 +24,17 @@ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000= 000, type0, type1) GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, = tp1), =20 -GEN_VXFORM_DUAL(vaddubm, vmul10cuq, 0, 0, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vadduhm, vmul10ecuq, 0, 1, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM(vadduwm, 0, 2), -GEN_VXFORM_207(vaddudm, 0, 3), -GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300), -GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300), -GEN_VXFORM_300(bcds, 0, 27), GEN_VXFORM_300(vextublx, 6, 24), GEN_VXFORM_300(vextuhlx, 6, 25), GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207), GEN_VXFORM_300(vextubrx, 6, 28), GEN_VXFORM_300(vextuhrx, 6, 29), GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_207(vmuluwm, 4, 2), GEN_VXFORM_300(vsrv, 2, 28), GEN_VXFORM_300(vslv, 2, 29), GEN_VXFORM(vslo, 6, 16), GEN_VXFORM(vsro, 6, 17), =20 -GEN_VXFORM(xpnd04_1, 0, 22), -GEN_VXFORM_300(bcdsr, 0, 23), -GEN_VXFORM_300(bcdsr, 0, 31), -GEN_VXFORM_300_EXT(vmul10uq, 0, 8, 0x0000F800), -GEN_VXFORM_300(vmul10euq, 0, 9), -GEN_VXFORM_300(bcdcpsgn, 0, 13), -GEN_VXFORM_207(bcdadd, 0, 24), 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shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 25/37] target/ppc: Move rlwimi, rlwinm instructions to decodetree Date: Thu, 27 Aug 2026 18:59:40 +0530 Message-ID: <20260827133010.278889-26-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfXym1FR2dEoGcr +AaE5j6nixjMVdxesI+tvKZXP6jM406KzsappuuNnryDQaZiI9cSPrcp+oNJF6icdpURvoGVwu5 3f/PT5/Zq40DkTgmRLIoqujCJS95DtA= X-Authority-Analysis: v=2.4 cv=AYuB2XXG c=1 sm=1 tr=0 ts=6a903c9f cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 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List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837640502158500 Content-Type: text/plain; charset="utf-8" From: Tanushree Shah -Moving the following instructions to decodetree specification: rlwimi : M-form rlwimi. : M-form rlwinm : M-form rlwinm. : M-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the "-d in_asm,op" flag. Additionally, validated using small assembly tests confirming the destination register is correctly updated based on rotated and masked source values and confirmed that the value was same before and after the change Signed-off-by: Tanushree Shah Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Reviewed-by: Amit Machhiwal Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 6 ++ target/ppc/translate.c | 106 --------------------- target/ppc/translate/fixedpoint-impl.c.inc | 102 ++++++++++++++++++++ 3 files changed, 108 insertions(+), 106 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 69d60605bd..92ee278f63 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -312,6 +312,9 @@ =20 @Z23_te_tbp ...... ....0 te:5 ....0 rmc:2 ........ rc:1 &Z23_te_tb= frt=3D%z23_frtp frb=3D%z23_frbp =20 +&M ra rs sh mb me rc:bool +@M ...... rs:5 ra:5 sh:5 mb:5 me:5 rc:1 &M + ### Fixed-Point Load Instructions =20 LBZ 100010 ..... ..... ................ @D @@ -561,6 +564,9 @@ SRADI 011111 ..... ..... ..... 110011101 . . = @XS =20 EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS =20 +RLWIMI 010100 ..... ..... ..... ..... ...... @M +RLWINM 010101 ..... ..... ..... ..... ...... @M + ## BCD Assist =20 ADDG6S 011111 ..... ..... ..... - 001001010 - @X diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d17d77a9d9..ce94f9e4e6 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2012,110 +2012,6 @@ static void gen_pause(DisasContext *ctx) =20 /*** Integer rotate = ***/ =20 -/* rlwimi & rlwimi. */ -static void gen_rlwimi(DisasContext *ctx) -{ - TCGv t_ra =3D cpu_gpr[rA(ctx->opcode)]; - TCGv t_rs =3D cpu_gpr[rS(ctx->opcode)]; - uint32_t sh =3D SH(ctx->opcode); - uint32_t mb =3D MB(ctx->opcode); - uint32_t me =3D ME(ctx->opcode); - - if (sh =3D=3D (31 - me) && mb <=3D me) { - tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); - } else { - target_ulong mask; - bool mask_in_32b =3D true; - TCGv t1; - -#if defined(TARGET_PPC64) - mb +=3D 32; - me +=3D 32; -#endif - mask =3D MASK(mb, me); - -#if defined(TARGET_PPC64) - if (mask > 0xffffffffu) { - mask_in_32b =3D false; - } -#endif - t1 =3D tcg_temp_new(); - if (mask_in_32b) { - TCGv_i32 t0 =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t0, t_rs); - tcg_gen_rotli_i32(t0, t0, sh); - tcg_gen_extu_i32_tl(t1, t0); - } else { -#if defined(TARGET_PPC64) - tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); - tcg_gen_rotli_i64(t1, t1, sh); -#else - g_assert_not_reached(); -#endif - } - - tcg_gen_andi_tl(t1, t1, mask); - tcg_gen_andi_tl(t_ra, t_ra, ~mask); - tcg_gen_or_tl(t_ra, t_ra, t1); - } - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, t_ra); - } -} - -/* rlwinm & rlwinm. */ -static void gen_rlwinm(DisasContext *ctx) -{ - TCGv t_ra =3D cpu_gpr[rA(ctx->opcode)]; - TCGv t_rs =3D cpu_gpr[rS(ctx->opcode)]; - int sh =3D SH(ctx->opcode); - int mb =3D MB(ctx->opcode); - int me =3D ME(ctx->opcode); - int len =3D me - mb + 1; - int rsh =3D (32 - sh) & 31; - - if (sh !=3D 0 && len > 0 && me =3D=3D (31 - sh)) { - tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); - } else if (me =3D=3D 31 && rsh + len <=3D 32) { - tcg_gen_extract_tl(t_ra, t_rs, rsh, len); - } else { - target_ulong mask; - bool mask_in_32b =3D true; -#if defined(TARGET_PPC64) - mb +=3D 32; - me +=3D 32; -#endif - mask =3D MASK(mb, me); -#if defined(TARGET_PPC64) - if (mask > 0xffffffffu) { - mask_in_32b =3D false; - } -#endif - if (mask_in_32b) { - if (sh =3D=3D 0) { - tcg_gen_andi_tl(t_ra, t_rs, mask); - } else { - TCGv_i32 t0 =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t0, t_rs); - tcg_gen_rotli_i32(t0, t0, sh); - tcg_gen_andi_i32(t0, t0, mask); - tcg_gen_extu_i32_tl(t_ra, t0); - } - } else { -#if defined(TARGET_PPC64) - tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); - tcg_gen_rotli_i64(t_ra, t_ra, sh); - tcg_gen_andi_i64(t_ra, t_ra, mask); -#else - g_assert_not_reached(); -#endif - } - } - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, t_ra); - } -} - /* rlwnm & rlwnm. */ static void gen_rlwnm(DisasContext *ctx) { @@ -4794,8 +4690,6 @@ GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PP= C_NONE), GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA30= 0), GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), -GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), /* handles lfdp, lxsd, lxssp */ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 4b79e24f6f..efef56a119 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1872,6 +1872,108 @@ static bool trans_SRAWI(DisasContext *ctx, arg_SRAW= I *a) return true; } =20 +static bool trans_RLWIMI(DisasContext *ctx, arg_RLWIMI *a) +{ + TCGv t_ra =3D cpu_gpr[a->ra]; + TCGv t_rs =3D cpu_gpr[a->rs]; + int mb =3D a->mb; + int me =3D a->me; + + if (a->sh =3D=3D (31 - me) && mb <=3D me) { + tcg_gen_deposit_tl(t_ra, t_ra, t_rs, a->sh, me - mb + 1); + } else { + target_ulong mask; + bool mask_in_32b =3D true; + TCGv t1; + +#if defined(TARGET_PPC64) + mb +=3D 32; + me +=3D 32; +#endif + mask =3D MASK(mb, me); + +#if defined(TARGET_PPC64) + if (mask > 0xffffffffu) { + mask_in_32b =3D false; + } +#endif + t1 =3D tcg_temp_new(); + if (mask_in_32b) { + TCGv_i32 t0 =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t0, t_rs); + tcg_gen_rotli_i32(t0, t0, a->sh); + tcg_gen_extu_i32_tl(t1, t0); + } else { +#if defined(TARGET_PPC64) + tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); + tcg_gen_rotli_i64(t1, t1, a->sh); +#else + g_assert_not_reached(); +#endif + } + + tcg_gen_andi_tl(t1, t1, mask); + tcg_gen_andi_tl(t_ra, t_ra, ~mask); + tcg_gen_or_tl(t_ra, t_ra, t1); + } + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, t_ra); + } + return true; +} + +static bool trans_RLWINM(DisasContext *ctx, arg_RLWINM *a) +{ + TCGv t_ra =3D cpu_gpr[a->ra]; + TCGv t_rs =3D cpu_gpr[a->rs]; + int me =3D a->me; + int mb =3D a->mb; + int len =3D me - mb + 1; + int rsh =3D (32 - a->sh) & 31; + + if (a->sh !=3D 0 && len > 0 && me =3D=3D (31 - a->sh)) { + tcg_gen_deposit_z_tl(t_ra, t_rs, a->sh, len); + } else if (me =3D=3D 31 && rsh + len <=3D 32) { + tcg_gen_extract_tl(t_ra, t_rs, rsh, len); + } else { + target_ulong mask; + bool mask_in_32b =3D true; +#if defined(TARGET_PPC64) + mb +=3D 32; + me +=3D 32; +#endif + mask =3D MASK(mb, me); +#if defined(TARGET_PPC64) + if (mask > 0xffffffffu) { + mask_in_32b =3D false; + } +#endif + if (mask_in_32b) { + if (a->sh =3D=3D 0) { + tcg_gen_andi_tl(t_ra, t_rs, mask); + } else { + TCGv_i32 t0 =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t0, t_rs); + tcg_gen_rotli_i32(t0, t0, a->sh); + tcg_gen_andi_i32(t0, t0, mask); + tcg_gen_extu_i32_tl(t_ra, t0); + } + } else { +#if defined(TARGET_PPC64) + tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=j7eHDt89Qik0T2PzF KGNUVLVpE/FZg7ejXqSm3HE1Xg=; b=Jh6E+o2G3y9m7Xi+SmjHm4hxUppCR46AG DjVhH9ZhmwvT2PznzWS+KOwkk8exaYM3EVyUvnpIl0fS+BxENhFCljt0Tc3SHvBm SAbcBzlPOOJDptmpqsIjMZNLOptq1JPd+ZxFoHiNKftnb898kJa3C+qCEJPL/+rK aljxtOF7ymoM+oqwEeOFStgWpyb6/nhhzIOOL3FBtrXMd/xNsP1n+cZ0YW+1QBkt ruG7+SZgNajmfOPR2TAex0D964cBoADV+6EBrhz2hNJPBzPnWsJyyHGUj3xJ39UL YRzGQu1BA5DdGH4M8nhhA3Gzeu12kG/Al+Tfn0lWOFXeA3TceCj4Q== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 26/37] target/ppc: Move lmw, stmw instructions to decodetree Date: Thu, 27 Aug 2026 18:59:41 +0530 Message-ID: <20260827133010.278889-27-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: BmpDgLE5ucm28DdzD27zKNtzzL2UvaMT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX1F2wTM2RhAdz C+qqLAqQfru7nLwxdvEweHIkWd9N5EPT2LaS61wSq4aFbPB9QuVT8p/5T3xuBhRXkrSQiqUEn49 7mc9ep1yZE30CFptWiKpCa0+y1uaaTv5BoTtfFHQluevsddh/ZG3Zoa/dBLpL1TDUNvj7CaSNRM bxFSE1AI/nXx9s+ZCLxKy9vk7TQIozSeoPj9o9bjckjG4MLQXImmQe8BmUPx0rlog+YHK3V4JeW dLSh+UNpVg6klpD08FuCiUQ1bb9qxJQSaEBxGXJ8bLm6bXknbOkQh6qxHu+4hwXjI46OP3iiueD +IuH09sFpbzgwj7SdpJuA3JXdRjMagcrKMSZhkcRFHR+FSxJAYuOtMMIwisxH1ridK7LhhNoRAU Pvm0ie90kup+F+OlHW0RsaJI2LDuwlmt9XKx8vOiyC4wOlP5s8Vp17Mi0e1BHasGHHAr23HNu55 XA/pqh5dA1/uaohNqTA== X-Authority-Analysis: v=2.4 cv=Y/nIdBeN c=1 sm=1 tr=0 ts=6a903ca6 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=EKBDPzd3v7EvMxvHOJ8A:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfXwlRhP8TZxYuU pTyfcgr+xym5Fd+PjjRmuFj1RxzMZCB+WauXOLryfkGr6uPbDFktraYKWDuaZs6RAZ5t/mrM0aO iRswEU2nawI6+KwUk7/chgVIUD0MHms= X-Proofpoint-ORIG-GUID: h8hSYqLFfHMZXuTxzpKAzjMQ0iMeCvfP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837775622158500 Content-Type: text/plain; charset="utf-8" From: Tanushree Shah Moving the following instructions to decodetree specification: lmw : D-form stmw : D-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the "-d in_asm,op" flag. Additionally, validated using small assembly tests confirming the the correct register store/load behavior. Also, confirmed the register values are same before and after the change. Signed-off-by: Tanushree Shah Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/helper.h | 4 +-- target/ppc/insn32.decode | 3 ++ target/ppc/mem_helper.c | 4 +-- target/ppc/translate.c | 39 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 32 ++++++++++++++++++ 5 files changed, 39 insertions(+), 43 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 7da752c69b..ec3350fee8 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -43,8 +43,8 @@ DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) #endif =20 -DEF_HELPER_3(lmw, void, env, tl, i32) -DEF_HELPER_FLAGS_3(stmw, TCG_CALL_NO_WG, void, env, tl, i32) +DEF_HELPER_3(LMW, void, env, tl, i32) +DEF_HELPER_FLAGS_3(STMW, TCG_CALL_NO_WG, void, env, tl, i32) DEF_HELPER_4(LSW, void, env, tl, i32, i32) DEF_HELPER_5(LSWX, void, env, tl, i32, i32, i32) DEF_HELPER_FLAGS_4(STSW, TCG_CALL_NO_WG, void, env, tl, i32, i32) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 92ee278f63..ef128f63c1 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -354,6 +354,7 @@ LVDX 011111 ..... ..... ..... 0000010001 - = @X LSKU 111010 ..... ..... ............. 0 11 @DD LCXU 111010 ..... ..... ............. 1 11 @DD =20 +LMW 101110 ..... ..... ................ @D =20 ### Fixed-Point Atomic Load/Store Instructions =20 @@ -399,6 +400,8 @@ STBCIX 011111 ..... ..... ..... 1111010101 - = @X STHBRX 011111 ..... ..... ..... 1110010110 - @X STWBRX 011111 ..... ..... ..... 1010010110 - @X =20 +STMW 101111 ..... ..... ................ @D + ### Fixed-Point Compare Instructions =20 CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 10c648cf06..dc5eab8c76 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -73,7 +73,7 @@ static void *probe_contiguous(CPUPPCState *env, target_ul= ong addr, uint32_t nb, return NULL; } =20 -void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) +void helper_LMW(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr =3D GETPC(); int mmu_idx =3D ppc_env_mmu_index(env, false); @@ -98,7 +98,7 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, uint= 32_t reg) } } =20 -void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) +void helper_STMW(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr =3D GETPC(); int mmu_idx =3D ppc_env_mmu_index(env, false); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ce94f9e4e6..880915f3da 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2455,43 +2455,6 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); #endif /* TARGET_PPC64 */ =20 -/*** Integer load and store multiple = ***/ - -/* lmw */ -static void gen_lmw(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - t1 =3D tcg_constant_i32(rD(ctx->opcode)); - gen_addr_imm_index(ctx, t0, 0); - gen_helper_lmw(tcg_env, t0, t1); -} - -/* stmw */ -static void gen_stmw(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - t1 =3D tcg_constant_i32(rS(ctx->opcode)); - gen_addr_imm_index(ctx, t0, 0); - gen_helper_stmw(tcg_env, t0, t1); -} - - #if !defined(CONFIG_USER_ONLY) static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { @@ -4695,8 +4658,6 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_= INTEGER), GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), /* handles stfdp, stxsd, stxssp */ GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), -GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index efef56a119..8475205f14 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -288,6 +288,38 @@ static bool trans_STQCX(DisasContext *ctx, arg_STQCX *= a) return true; } =20 +/* Load/Store Multiple Word */ +static bool do_ldst_multiple(DisasContext *ctx, arg_D *a, bool store) +{ + TCGv ea; + TCGv_i32 reg; + + REQUIRE_INSNS_FLAGS(ctx, INTEGER); + + /* Little-endian mode is not supported for multiple word operations */ + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + + gen_set_access_type(ctx, ACCESS_INT); + + reg =3D tcg_constant_i32(a->rt); + ea =3D do_ea_calc(ctx, a->ra, tcg_constant_tl(a->si)); + + /* Call the appropriate helper function */ + if (store) { + gen_helper_STMW(tcg_env, ea, reg); + } else { + gen_helper_LMW(tcg_env, ea, reg); + } + + return true; +} + +TRANS(LMW, do_ldst_multiple, false) +TRANS(STMW, do_ldst_multiple, true) + /* * Fixed-Point Compare Instructions */ --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 27 Aug 2026 13:33:21 +0000 (GMT) Received: from li-18a0a34c-33fc-11b2-a85c-d9f1631c5692.ibm.com (unknown [9.111.12.1]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 27 Aug 2026 13:33:21 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=7e4qDD9wEhNpDV98l pfblETsLWjPUQf9LBfBv3tFkk4=; b=lAioPWimO08qVBH8Sm3JxVErUaVJkaxJb ydLQZ3Cx4VYsm4JlwczNoR2Iy1RRO4za36Py/23uVA9AXw0CGKvMfx8wiMk4rn+K J5EIR/UWm0W6pRqE7NtQAESSmqI277bDIjd0UOR70+uXDg9yd7BltxoVxklwfUBn 9cOpOioQb+KSg2TbU8J/rv0MSmW5+kl+1tv6ZZyx9JBkf8/gIor6wIs1IaDi9MXI 5Rr8uEI1iwN/HoTZpvVZ5zs2SRmbqcy1cXU8Xbi/4qEaHRf6opG+Y+ZoQ/SqTw45 lVJnVGhGrTXmaYCqF5161dwihB3hm9sfdq0L6/Gx+QFrh/asU4BUA== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 27/37] target/ppc: Move mfmsr, mtmsr[d] instructions to decodetree Date: Thu, 27 Aug 2026 18:59:42 +0530 Message-ID: <20260827133010.278889-28-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: QHC-bN97K53q6K3NS4vvq_ESJilSgCNv X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX7/Sk7JndullS a19BHX2KPzidjFr5LgR9VSrbUbSYRV/Mla11YKRTXaxbULu7yI4Kjrd674iQOGGDWEcTUgjJv8w Voqs1fpBFodxnoilXX9uaVkLiYnoj2ZlgnN/ifVu9TT4WTNA7y12byE6tEEzg2vwgLqpQ7i4iXx WnvtO4gqYz5MfMtvvs/v1rSSR7YmxTzux088AKXeD27k2tO0bct0L5avBfHiEmQsx5ykw+pDldH At3HejvxeOgTtwJwH8w5e/Zl2FlnEXdNInddiI948aCiFlRpWQ44NBZXnlyHloTiN+VGeTCMHM/ AHcsh60Rj17xzC3hgVBCLZVfQ/qMuGuy42mz2yVS4p6J+8Pe2sRDRXayENEj+8PfmqkYS4yI/QZ 3x1P0g2sUkoYV71SNzTN5xQp6P9kfa47kRA+RPYB7Mc8/HSSCfGD/HePiuTs8j+C+sFYeZVsqu2 YNwxQmt8J2ALNSc4nbw== X-Authority-Analysis: v=2.4 cv=Y/nIdBeN c=1 sm=1 tr=0 ts=6a903caf cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=fRY7pOLSFYBF0tKEtWUA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX2vJQxN/M47H+ UOH4+5uyIskoy5+L947g1ZexdEsrMaYdgZ6Nbc5d3/OY/rE08pE/M7qdTHzyHq1z7IGK5+QajFr DcFJTa6apeawENKWi0cD1H9k2WbFnSU= X-Proofpoint-ORIG-GUID: vEXrNFODwb79PfiAgHKefy7VgwOagTeT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837680800158500 Content-Type: text/plain; charset="utf-8" From: Vishal Chourasia Moving the following instructions to decodetree specification: mfmsr : X-form mtmsr[d] : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the `-d in_asm,op` flag. This also includes improvements from review feedback: - Gate MFMSR/MTMSR on PPC_MISC via TRANS_FLAGS() - Use UINT32_MAX instead of 0xFFFFFFFF for clarity Signed-off-by: Vishal Chourasia Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 5 ++ target/ppc/translate.c | 97 ---------------------------- target/ppc/translate/misc-impl.c.inc | 64 ++++++++++++++++++ 3 files changed, 69 insertions(+), 97 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index ef128f63c1..1e263449a5 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -315,6 +315,11 @@ &M ra rs sh mb me rc:bool @M ...... rs:5 ra:5 sh:5 mb:5 me:5 rc:1 &M =20 +### MSR +MFMSR 011111 ..... ----- ----- 0001010011 - @X_t +MTMSR 011111 ..... ---- . ----- 0010010010 - @X_rs_l +MTMSRD 011111 ..... ---- . ----- 0010110010 - @X_rs_l + ### Fixed-Point Load Instructions =20 LBZ 100010 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 880915f3da..1d069c5250 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2843,13 +2843,6 @@ static void gen_mcrxrx(DisasContext *ctx) } #endif =20 -/* mfmsr */ -static void gen_mfmsr(DisasContext *ctx) -{ - CHK_SV(ctx); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); -} - /* mfspr */ static inline void gen_op_mfspr(DisasContext *ctx) { @@ -2923,93 +2916,6 @@ static void gen_mftb(DisasContext *ctx) gen_op_mfspr(ctx); } =20 -/* mtmsr */ -#if defined(TARGET_PPC64) -static void gen_mtmsrd(DisasContext *ctx) -{ - if (unlikely(!is_book3s_arch2x(ctx))) { - gen_invalid(ctx); - return; - } - - CHK_SV(ctx); - -#if !defined(CONFIG_USER_ONLY) - TCGv t0, t1; - target_ulong mask; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - - translator_io_start(&ctx->base); - - if (ctx->opcode & 0x00010000) { - /* L=3D1 form only updates EE and RI */ - mask =3D (1ULL << MSR_RI) | (1ULL << MSR_EE); - } else { - /* mtmsrd does not alter HV, S, ME, or LE */ - mask =3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | - (1ULL << MSR_HV)); - /* - * XXX: we need to update nip before the store if we enter - * power saving mode, we will exit the loop directly from - * ppc_store_msr - */ - gen_update_nip(ctx, ctx->base.pc_next); - } - - tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); - tcg_gen_andi_tl(t1, cpu_msr, ~mask); - tcg_gen_or_tl(t0, t0, t1); - - gen_helper_store_msr(tcg_env, t0); - - /* Must stop the translation as machine state (may have) changed */ - ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; -#endif /* !defined(CONFIG_USER_ONLY) */ -} -#endif /* defined(TARGET_PPC64) */ - -static void gen_mtmsr(DisasContext *ctx) -{ - CHK_SV(ctx); - -#if !defined(CONFIG_USER_ONLY) - TCGv t0, t1; - target_ulong mask =3D 0xFFFFFFFF; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - - translator_io_start(&ctx->base); - if (ctx->opcode & 0x00010000) { - /* L=3D1 form only updates EE and RI */ - mask &=3D (1ULL << MSR_RI) | (1ULL << MSR_EE); - } else { - if (likely(!(ctx->insns_flags2 & PPC2_PPE42))) { - /* mtmsr does not alter S, ME, or LE */ - mask &=3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR= _S)); - } - - /* - * XXX: we need to update nip before the store if we enter - * power saving mode, we will exit the loop directly from - * ppc_store_msr - */ - gen_update_nip(ctx, ctx->base.pc_next); - } - - tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); - tcg_gen_andi_tl(t1, cpu_msr, ~mask); - tcg_gen_or_tl(t0, t0, t1); - - gen_helper_store_msr(tcg_env, t0); - - /* Must stop the translation as machine state (may have) changed */ - ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; -#endif -} - /* mtspr */ static void gen_mtspr(DisasContext *ctx) { @@ -4674,15 +4580,12 @@ GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PP= C_64H), GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), -GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), #if defined(TARGET_PPC64) -GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), #endif -GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE20= 6), diff --git a/target/ppc/translate/misc-impl.c.inc b/target/ppc/translate/mi= sc-impl.c.inc index 890fbb209e..54712f9b73 100644 --- a/target/ppc/translate/misc-impl.c.inc +++ b/target/ppc/translate/misc-impl.c.inc @@ -161,3 +161,67 @@ static bool trans_MCRF(DisasContext *ctx, arg_MCRF *a) tcg_gen_mov_i32(cpu_crf[a->bf], cpu_crf[a->bfa]); return true; } + +static bool do_mfmsr(DisasContext *ctx, arg_X_t *a) +{ + REQUIRE_SV(ctx); + tcg_gen_mov_tl(cpu_gpr[a->rt], cpu_msr); + return true; +} +TRANS_FLAGS(MISC, MFMSR, do_mfmsr) + +static bool do_mtmsr(DisasContext *ctx, arg_X_rs_l *a, bool is_mtmsrd) +{ + REQUIRE_SV(ctx); +#if !defined(CONFIG_USER_ONLY) + TCGv t0, t1; + target_ulong mask; + + if (is_mtmsrd) { + if (unlikely(!is_book3s_arch2x(ctx))) { + gen_invalid(ctx); + return true; + } + mask =3D ~(target_ulong)0; + } else { + mask =3D UINT32_MAX; + } + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + translator_io_start(&ctx->base); + + if (a->l) { + /* L=3D1 form only updates EE and RI */ + mask &=3D (1ULL << MSR_RI) | (1ULL << MSR_EE); + } else { + if (is_mtmsrd) { + /* mtmsrd does not alter HV, S, ME, or LE */ + mask &=3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | + (1ULL << MSR_S) | (1ULL << MSR_HV)); + } else if (likely(!(ctx->insns_flags2 & PPC2_PPE42))) { + /* mtmsr does not alter S, ME, or LE */ + mask &=3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR= _S)); + } + /* + * XXX: we need to update nip before the store if we enter + * power saving mode, we will exit the loop directly from + * ppc_store_msr + */ + gen_update_nip(ctx, ctx->base.pc_next); + } + + tcg_gen_andi_tl(t0, cpu_gpr[a->rs], mask); + tcg_gen_andi_tl(t1, cpu_msr, ~mask); + tcg_gen_or_tl(t0, t0, t1); + + gen_helper_store_msr(tcg_env, t0); + + /* Must stop the translation as machine state (may have) changed */ + ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; +#endif /* !CONFIG_USER_ONLY */ + return true; +} + +TRANS_FLAGS(MISC, MTMSR, do_mtmsr, false) +TRANS64(MTMSRD, do_mtmsr, true) --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787837680; cv=none; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837680739158500 Content-Type: text/plain; charset="utf-8" From: Vishal Chourasia Moving the following instructions to decodetree specification: brd, brw, brh : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the `-d in_asm,op` flag. This also includes improvements from review feedback: - Add TARGET_PPC64 guards with qemu_build_not_reached() for 32-bit builds Signed-off-by: Vishal Chourasia Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Reviewed-by: Amit Machhiwal Tested-by: Aniket Sahu --- target/ppc/insn32.decode | 5 +++ target/ppc/translate.c | 35 ---------------- target/ppc/translate/fixedpoint-impl.c.inc | 48 ++++++++++++++++++++++ 3 files changed, 53 insertions(+), 35 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 1e263449a5..7bbe1f8838 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -320,6 +320,11 @@ MFMSR 011111 ..... ----- ----- 0001010011 - = @X_t MTMSR 011111 ..... ---- . ----- 0010010010 - @X_rs_l MTMSRD 011111 ..... ---- . ----- 0010110010 - @X_rs_l =20 +### Fixed-Point Byte-Reverse Instructions +BRW 011111 ..... ..... ----- 0010011011 - @X_sa +BRD 011111 ..... ..... ----- 0010111011 - @X_sa +BRH 011111 ..... ..... ----- 0011011011 - @X_sa + ### Fixed-Point Load Instructions =20 LBZ 100010 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 1d069c5250..20d3e7c1ab 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4519,42 +4519,7 @@ static void gen_dform3D(DisasContext *ctx) return gen_invalid(ctx); } =20 -#if defined(TARGET_PPC64) -/* brd */ -static void gen_brd(DisasContext *ctx) -{ - tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]= ); -} - -/* brw */ -static void gen_brw(DisasContext *ctx) -{ - tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]= ); - tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], = 32); - -} - -/* brh */ -static void gen_brh(DisasContext *ctx) -{ - TCGv_i64 mask =3D tcg_constant_i64(0x00ff00ff00ff00ffull); - TCGv_i64 t1 =3D tcg_temp_new_i64(); - TCGv_i64 t2 =3D tcg_temp_new_i64(); - - tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); - tcg_gen_and_i64(t2, t1, mask); - tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); - tcg_gen_shli_i64(t1, t1, 8); - tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); -} -#endif - static opcode_t opcodes[] =3D { -#if defined(TARGET_PPC64) -GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), -GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), -GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), -#endif GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA30= 0), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 8475205f14..0e1960a272 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -17,6 +17,54 @@ * License along with this library; if not, see . */ =20 +/* + * Byte-Reverse Instructions + */ +static bool trans_BRD(DisasContext *ctx, arg_BRD *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA310); +#if defined(TARGET_PPC64) + tcg_gen_bswap64_i64(cpu_gpr[a->ra], cpu_gpr[a->rs]); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_BRW(DisasContext *ctx, arg_BRW *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA310); +#if defined(TARGET_PPC64) + tcg_gen_bswap64_i64(cpu_gpr[a->ra], cpu_gpr[a->rs]); + tcg_gen_rotli_i64(cpu_gpr[a->ra], cpu_gpr[a->ra], 32); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_BRH(DisasContext *ctx, arg_BRH *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA310); +#if defined(TARGET_PPC64) + TCGv_i64 mask =3D tcg_constant_i64(0x00ff00ff00ff00ffull); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2 =3D tcg_temp_new_i64(); + + tcg_gen_shri_i64(t1, cpu_gpr[a->rs], 8); + tcg_gen_and_i64(t2, t1, mask); + tcg_gen_and_i64(t1, cpu_gpr[a->rs], mask); + tcg_gen_shli_i64(t1, t1, 8); + tcg_gen_or_i64(cpu_gpr[a->ra], t1, t2); +#else + qemu_build_not_reached(); +#endif + return true; +} + /* * Fixed-Point Load/Store Instructions */ --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787837733; cv=none; d=zohomail.com; s=zohoarc; b=TjKRUpYxt0t1SxIuaYOip7Nb2Naku9+fuv8g5+YiS0StRsY4u/n0Gvt4np03plzrJVOYCwUMbIS+72Iv37Y9Js684mvcbOiMCmBKIhlgn16rdlVw+f8UETG/oefWVM5pSwDaLUWdD1NH59wQT7UJfyKHzFHq9GEi6asCpWRwuEA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787837733; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837735212158502 Content-Type: text/plain; charset="utf-8" From: Vishal Chourasia Moving the following instructions to decodetree specification: sc, scv : SC-form rfi, rfid, rfscv, hrfid : XL-form This builds upon the previous work that moved mfmsr and mtmsr[d] instructions to decodetree. The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the `-d in_asm,op` flag, and also by booting a pseries qemu guest. This also includes improvements from review feedback: - Rename helpers to uppercase (RFI/RFID/RFSCV/HRFID) to match ISA mnemonics - Add TRANS64_FLAGS() macro variants - Add REQUIRE_INSNS_FLAGS_NOT() check for flag exclusion - Specify lev field as uint8_t in SC instruction format - Remove redundant masking in SCV since lev is already 7-bit - Replace TARGET_PPC64 ifdefs with REQUIRE_64BIT() macro - Gate SC, SCV, RFI, RFID, RFSCV, and HRFID with appropriate flags - Consolidate CONFIG_USER_ONLY guards into single block Signed-off-by: Vishal Chourasia Reviewed-by: Glenn Miles Signed-off-by: Chinmay Rath Reviewed-by: Amit Machhiwal Tested-by: Aniket Sahu --- target/ppc/helper.h | 8 +- target/ppc/insn32.decode | 11 +++ target/ppc/tcg-excp_helper.c | 8 +- target/ppc/translate.c | 126 ++------------------------- target/ppc/translate/misc-impl.c.inc | 102 ++++++++++++++++++++++ 5 files changed, 128 insertions(+), 127 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index ec3350fee8..80d6616bab 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -11,7 +11,7 @@ DEF_HELPER_4(HASHCHKP, void, env, tl, tl, tl) #if !defined(CONFIG_USER_ONLY) DEF_HELPER_2(store_msr, void, env, tl) DEF_HELPER_1(ppc_maybe_interrupt, void, env) -DEF_HELPER_1(rfi, void, env) +DEF_HELPER_1(RFI, void, env) DEF_HELPER_1(40x_rfci, void, env) DEF_HELPER_1(rfci, void, env) DEF_HELPER_1(rfdi, void, env) @@ -19,9 +19,9 @@ DEF_HELPER_1(rfmci, void, env) #if defined(TARGET_PPC64) DEF_HELPER_2(scv, noreturn, env, i32) DEF_HELPER_2(PMINSN, void, env, i32) -DEF_HELPER_1(rfid, void, env) -DEF_HELPER_1(rfscv, void, env) -DEF_HELPER_1(hrfid, void, env) +DEF_HELPER_1(RFID, void, env) +DEF_HELPER_1(RFSCV, void, env) +DEF_HELPER_1(HRFID, void, env) DEF_HELPER_2(rfebb, void, env, tl) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 7bbe1f8838..6563dc4f64 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -199,6 +199,9 @@ &X_rs_l rs l:bool @X_rs_l ...... rs:5 .... l:1 ..... .......... . &X_rs_l =20 +&SC lev:uint8_t +@SC ...... ..... ..... .... lev:7 ... . . &SC + &X_uim5 xt uim:uint8_t @X_uim5 ...... ..... ..... uim:5 .......... . &X_uim5 xt= =3D%x_xt =20 @@ -320,6 +323,14 @@ MFMSR 011111 ..... ----- ----- 0001010011 - = @X_t MTMSR 011111 ..... ---- . ----- 0010010010 - @X_rs_l MTMSRD 011111 ..... ---- . ----- 0010110010 - @X_rs_l =20 +### System Call and Return from Interrupt +SC 010001 ----- ----- ---- ....... --- 1 - @SC +SCV 010001 ----- ----- ---- ....... --- 0 1 @SC +RFI 010011 ----- ----- ----- 0000110010 - +RFID 010011 ----- ----- ----- 0000010010 - +RFSCV 010011 ----- ----- ----- 0001010010 - +HRFID 010011 ----- ----- ----- 0100010010 - + ### Fixed-Point Byte-Reverse Instructions BRW 011111 ..... ..... ----- 0010011011 - @X_sa BRD 011111 ..... ..... ----- 0010111011 - @X_sa diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index c4ffa2dfbb..d06d3f8642 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -528,13 +528,13 @@ static void do_rfi(CPUPPCState *env, target_ulong nip= , target_ulong msr) check_tlb_flush(env, false); } =20 -void helper_rfi(CPUPPCState *env) +void helper_RFI(CPUPPCState *env) { do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); } =20 #ifdef TARGET_PPC64 -void helper_rfid(CPUPPCState *env) +void helper_RFID(CPUPPCState *env) { /* * The architecture defines a number of rules for which bits can @@ -545,12 +545,12 @@ void helper_rfid(CPUPPCState *env) do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); } =20 -void helper_rfscv(CPUPPCState *env) +void helper_RFSCV(CPUPPCState *env) { do_rfi(env, env->lr, env->ctr); } =20 -void helper_hrfid(CPUPPCState *env) +void helper_HRFID(CPUPPCState *env) { do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 20d3e7c1ab..f46e2167ea 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2679,110 +2679,6 @@ static inline void gen_setlr(DisasContext *ctx, tar= get_ulong nip) tcg_gen_movi_tl(cpu_lr, nip); } =20 -/*** System linkage = ***/ - -/* rfi (supervisor only) */ -static void gen_rfi(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - /* - * This instruction doesn't exist anymore on 64-bit server - * processors compliant with arch 2.x - */ - if (is_book3s_arch2x(ctx)) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - /* Restore CPU state */ - CHK_SV(ctx); - translator_io_start(&ctx->base); - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); - gen_helper_rfi(tcg_env); - ctx->base.is_jmp =3D DISAS_EXIT; -#endif -} - -#if defined(TARGET_PPC64) -static void gen_rfid(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - /* Restore CPU state */ - CHK_SV(ctx); - translator_io_start(&ctx->base); - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); - gen_helper_rfid(tcg_env); - ctx->base.is_jmp =3D DISAS_EXIT; -#endif -} - -#if !defined(CONFIG_USER_ONLY) -static void gen_rfscv(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - /* Restore CPU state */ - CHK_SV(ctx); - translator_io_start(&ctx->base); - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); - gen_helper_rfscv(tcg_env); - ctx->base.is_jmp =3D DISAS_EXIT; -#endif -} -#endif - -static void gen_hrfid(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - /* Restore CPU state */ - CHK_HV(ctx); - translator_io_start(&ctx->base); - gen_helper_hrfid(tcg_env); - ctx->base.is_jmp =3D DISAS_EXIT; -#endif -} -#endif - -/* sc */ -#if defined(CONFIG_USER_ONLY) -#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER -#else -#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL -#endif -static void gen_sc(DisasContext *ctx) -{ - uint32_t lev; - - /* - * LEV is a 7-bit field, but the top 6 bits are treated as a reserved - * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is - * for Ultravisor which TCG does not support, so just ignore the top 6. - */ - lev =3D (ctx->opcode >> 5) & 0x1; - gen_exception_err(ctx, POWERPC_SYSCALL, lev); -} - -#if defined(TARGET_PPC64) -#if !defined(CONFIG_USER_ONLY) -static void gen_scv(DisasContext *ctx) -{ - uint32_t lev =3D (ctx->opcode >> 5) & 0x7F; - - /* Set the PC back to the faulting instruction. */ - gen_update_nip(ctx, ctx->cia); - gen_helper_scv(tcg_env, tcg_constant_i32(lev)); - - ctx->base.is_jmp =3D DISAS_NORETURN; -} -#endif -#endif - /*** Trap = ***/ =20 /* Check for unconditional traps (always or never) */ @@ -4155,6 +4051,13 @@ static int64_t dw_compose_ea(DisasContext *ctx, int = x) #define TRANS64(NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { REQUIRE_64BIT(ctx); return FUNC(ctx, a, ##__VA_ARGS__); } +#define TRANS64_FLAGS(FLAGS, NAME, FUNC, ...) \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \ + { \ + REQUIRE_64BIT(ctx); \ + REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ + return FUNC(ctx, a, ##__VA_ARGS__); \ + } #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ @@ -4529,21 +4432,6 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC= _INTEGER), GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), /* handles stfdp, stxsd, stxssp */ GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), -/* ISA v3.0 changed the extended opcode from 62 to 30 */ -GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), -#if defined(TARGET_PPC64) -GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), -#if !defined(CONFIG_USER_ONLY) -/* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ -GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), -#endif -GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), -#endif -/* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ -GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), -GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), diff --git a/target/ppc/translate/misc-impl.c.inc b/target/ppc/translate/mi= sc-impl.c.inc index 54712f9b73..26c82a5a7f 100644 --- a/target/ppc/translate/misc-impl.c.inc +++ b/target/ppc/translate/misc-impl.c.inc @@ -225,3 +225,105 @@ static bool do_mtmsr(DisasContext *ctx, arg_X_rs_l *a= , bool is_mtmsrd) =20 TRANS_FLAGS(MISC, MTMSR, do_mtmsr, false) TRANS64(MTMSRD, do_mtmsr, true) + +/* + * System Call and Return from Interrupt Instructions + */ + +static bool do_SC(DisasContext *ctx, arg_SC * a, uint32_t excp) +{ + uint32_t lev; + + /* + * LEV is a 7-bit field, but the top 6 bits are treated as a reserved + * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is + * for Ultravisor which TCG does not support, so just ignore the top 6. + */ + lev =3D a->lev & 0x1; + gen_exception_err(ctx, excp, lev); + return true; +} + +static bool do_SCV(DisasContext *ctx, arg_SC *a) +{ +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + /* Set the PC back to the faulting instruction. */ + gen_update_nip(ctx, ctx->cia); + gen_helper_scv(tcg_env, tcg_constant_i32(a->lev)); + + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +#else + gen_invalid(ctx); + return true; +#endif +} + +/* + * Common helper for return-from-interrupt instructions + */ +enum { + RFI_KIND_RFI =3D 0, + RFI_KIND_RFID =3D 1, + RFI_KIND_HRFID =3D 2, + RFI_KIND_RFSCV =3D 3, +}; + +static bool do_rfi(DisasContext *ctx, arg_RFID *a, int kind) +{ +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); + return true; +#else + void (*helper)(TCGv_ptr); + + switch (kind) { + case RFI_KIND_RFI: + if (is_book3s_arch2x(ctx)) { + gen_invalid(ctx); + return true; + } + REQUIRE_SV(ctx); + helper =3D gen_helper_RFI; + break; +#if defined(TARGET_PPC64) + case RFI_KIND_HRFID: + REQUIRE_HV(ctx); + helper =3D gen_helper_HRFID; + break; + case RFI_KIND_RFID: + REQUIRE_SV(ctx); + helper =3D gen_helper_RFID; + break; + case RFI_KIND_RFSCV: + REQUIRE_SV(ctx); + helper =3D gen_helper_RFSCV; + break; +#endif + default: + gen_invalid(ctx); + return true; + } + + translator_io_start(&ctx->base); + if (kind !=3D RFI_KIND_HRFID) { + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); + } + helper(tcg_env); + ctx->base.is_jmp =3D DISAS_EXIT; + return true; +#endif +} + +#if defined(CONFIG_USER_ONLY) +TRANS_FLAGS(FLOW, SC, do_SC, POWERPC_EXCP_SYSCALL_USER) +#else +TRANS_FLAGS(FLOW, SC, do_SC, POWERPC_EXCP_SYSCALL) +#endif + +TRANS64_FLAGS2(ISA300, SCV, do_SCV) + +TRANS_FLAGS(FLOW, RFI, do_rfi, RFI_KIND_RFI) +TRANS64(RFID, do_rfi, RFI_KIND_RFID) +TRANS64_FLAGS(64H, HRFID, do_rfi, RFI_KIND_HRFID) +TRANS64_FLAGS2(ISA300, RFSCV, do_rfi, RFI_KIND_RFSCV) --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837797439158500 Content-Type: text/plain; charset="utf-8" There are several flags for Power ISA 2.07 currently in use, namely : PPC2_VSX207, PPC2_BCTAR_ISA207, PPC2_LSQ_ISA207, etc, but most of them are used together without any individual use. Create a generic ISA 2.07 flag and switch usage of PPC2_VSX207 to it instead. Next commits would consolidate the remaining flags. Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/cpu.h | 6 ++-- target/ppc/cpu_init.c | 2 +- target/ppc/cpu_init.h | 2 +- target/ppc/translate/fp-impl.c.inc | 4 +-- target/ppc/translate/vsx-impl.c.inc | 56 ++++++++++++++--------------- target/ppc/translate/vsx-ops.c.inc | 24 ++++++------- 6 files changed, 47 insertions(+), 47 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index cbd5964b1a..91ef34cb21 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2565,8 +2565,8 @@ enum { PPC2_DBRX =3D 0x0000000000000010ULL, /* Book I 2.05 PowerPC specification = */ PPC2_ISA205 =3D 0x0000000000000020ULL, - /* VSX additions in ISA 2.07 = */ - PPC2_VSX207 =3D 0x0000000000000040ULL, + /* POWER ISA 2.07 = */ + PPC2_ISA207 =3D 0x0000000000000040ULL, /* ISA 2.06B bpermd = */ PPC2_PERM_ISA206 =3D 0x0000000000000080ULL, /* ISA 2.06B divide extended variants = */ @@ -2607,7 +2607,7 @@ enum { PPC2_PPE42XM =3D 0x0000000002000000ULL, =20 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX= | \ - PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ + PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index e2533481d8..b913edd243 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6346,7 +6346,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *d= ata) PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD | PPC_CILDST; - pcc->insns_flags2 =3D PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | + pcc->insns_flags2 =3D PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index f8fd6ff5cd..1c41c0d349 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -15,7 +15,7 @@ #define PPC_INSNS_FLAGS_POWER11 PPC_INSNS_FLAGS_POWER10 =20 #define PPC_INSNS_FLAGS2_POWER_COMMON \ - (PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \ + (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | \ PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \ diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-i= mpl.c.inc index 464fb1d90f..e0d9fa2e24 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -342,7 +342,7 @@ static bool trans_FCPSGN(DisasContext *ctx, arg_FCPSGN = *a) static bool trans_FMRGEW(DisasContext *ctx, arg_FMRGEW *a) { TCGv_i64 t0, t1, t2; - REQUIRE_INSNS_FLAGS2(ctx, VSX207); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); REQUIRE_FPU(ctx); t0 =3D tcg_temp_new_i64(); t1 =3D tcg_temp_new_i64(); @@ -358,7 +358,7 @@ static bool trans_FMRGEW(DisasContext *ctx, arg_FMRGEW = *a) static bool trans_FMRGOW(DisasContext *ctx, arg_FMRGOW *a) { TCGv_i64 t0, t1, t2; - REQUIRE_INSNS_FLAGS2(ctx, VSX207); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); REQUIRE_FPU(ctx); t0 =3D tcg_temp_new_i64(); t1 =3D tcg_temp_new_i64(); diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index 00ad57c628..78311dcba9 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -50,11 +50,11 @@ static bool do_lxs(DisasContext *ctx, arg_X *a, } =20 TRANS_FLAGS2(VSX, LXSDX, do_lxs, gen_qemu_ld64_i64); -TRANS_FLAGS2(VSX207, LXSIWAX, do_lxs, gen_qemu_ld32s_i64); +TRANS_FLAGS2(ISA207, LXSIWAX, do_lxs, gen_qemu_ld32s_i64); TRANS_FLAGS2(ISA300, LXSIBZX, do_lxs, gen_qemu_ld8u_i64); TRANS_FLAGS2(ISA300, LXSIHZX, do_lxs, gen_qemu_ld16u_i64); -TRANS_FLAGS2(VSX207, LXSIWZX, do_lxs, gen_qemu_ld32u_i64); -TRANS_FLAGS2(VSX207, LXSSPX, do_lxs, gen_qemu_ld32fs); +TRANS_FLAGS2(ISA207, LXSIWZX, do_lxs, gen_qemu_ld32u_i64); +TRANS_FLAGS2(ISA207, LXSSPX, do_lxs, gen_qemu_ld32fs); =20 static bool trans_LXVD2X(DisasContext *ctx, arg_LXVD2X *a) { @@ -304,8 +304,8 @@ static bool do_stxs(DisasContext *ctx, arg_X *a, TRANS_FLAGS2(VSX, STXSDX, do_stxs, gen_qemu_st64_i64); TRANS_FLAGS2(ISA300, STXSIBX, do_stxs, gen_qemu_st8_i64); TRANS_FLAGS2(ISA300, STXSIHX, do_stxs, gen_qemu_st16_i64); -TRANS_FLAGS2(VSX207, STXSIWX, do_stxs, gen_qemu_st32_i64); -TRANS_FLAGS2(VSX207, STXSSPX, do_stxs, gen_qemu_st32fs); +TRANS_FLAGS2(ISA207, STXSIWX, do_stxs, gen_qemu_st32_i64); +TRANS_FLAGS2(ISA207, STXSSPX, do_stxs, gen_qemu_st32fs); =20 static bool trans_STXVD2X(DisasContext *ctx, arg_STXVD2X *a) { @@ -988,7 +988,7 @@ GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) -GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207) +GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_ISA207) GEN_VSX_HELPER_R2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300) GEN_VSX_HELPER_R2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300) GEN_VSX_HELPER_R2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300) @@ -1185,7 +1185,7 @@ bool trans_XSCVSPDPN(DisasContext *ctx, arg_XX2 *a) { TCGv_i64 tmp; =20 - REQUIRE_INSNS_FLAGS2(ctx, VSX207); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); REQUIRE_VSX(ctx); =20 tmp =3D tcg_temp_new_i64(); @@ -1210,16 +1210,16 @@ GEN_VSX_HELPER_X2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207) +GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_ISA207) GEN_VSX_HELPER_R2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300) GEN_VSX_HELPER_R2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300) GEN_VSX_HELPER_R2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300) GEN_VSX_HELPER_R3(xssubqp, 0x04, 0x10, 0, PPC2_ISA300) -GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) +GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_ISA207) +GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_ISA207) +GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_ISA207) +GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_ISA207) +GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_ISA207) =20 GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) @@ -1409,14 +1409,14 @@ TRANS_FLAGS2(VSX, XSNMADDADP, do_xsmadd_XX3, true, = gen_helper_XSNMADDDP) TRANS_FLAGS2(VSX, XSNMADDMDP, do_xsmadd_XX3, false, gen_helper_XSNMADDDP) TRANS_FLAGS2(VSX, XSNMSUBADP, do_xsmadd_XX3, true, gen_helper_XSNMSUBDP) TRANS_FLAGS2(VSX, XSNMSUBMDP, do_xsmadd_XX3, false, gen_helper_XSNMSUBDP) -TRANS_FLAGS2(VSX207, XSMADDASP, do_xsmadd_XX3, true, gen_helper_XSMADDSP) -TRANS_FLAGS2(VSX207, XSMADDMSP, do_xsmadd_XX3, false, gen_helper_XSMADDSP) -TRANS_FLAGS2(VSX207, XSMSUBASP, do_xsmadd_XX3, true, gen_helper_XSMSUBSP) -TRANS_FLAGS2(VSX207, XSMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSMSUBSP) -TRANS_FLAGS2(VSX207, XSNMADDASP, do_xsmadd_XX3, true, gen_helper_XSNMADDSP) -TRANS_FLAGS2(VSX207, XSNMADDMSP, do_xsmadd_XX3, false, gen_helper_XSNMADDS= P) -TRANS_FLAGS2(VSX207, XSNMSUBASP, do_xsmadd_XX3, true, gen_helper_XSNMSUBSP) -TRANS_FLAGS2(VSX207, XSNMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSNMSUBS= P) +TRANS_FLAGS2(ISA207, XSMADDASP, do_xsmadd_XX3, true, gen_helper_XSMADDSP) +TRANS_FLAGS2(ISA207, XSMADDMSP, do_xsmadd_XX3, false, gen_helper_XSMADDSP) +TRANS_FLAGS2(ISA207, XSMSUBASP, do_xsmadd_XX3, true, gen_helper_XSMSUBSP) +TRANS_FLAGS2(ISA207, XSMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSMSUBSP) +TRANS_FLAGS2(ISA207, XSNMADDASP, do_xsmadd_XX3, true, gen_helper_XSNMADDSP) +TRANS_FLAGS2(ISA207, XSNMADDMSP, do_xsmadd_XX3, false, gen_helper_XSNMADDS= P) +TRANS_FLAGS2(ISA207, XSNMSUBASP, do_xsmadd_XX3, true, gen_helper_XSNMSUBSP) +TRANS_FLAGS2(ISA207, XSNMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSNMSUBS= P) =20 static bool do_xsmadd_X(DisasContext *ctx, arg_X_rc *a, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_pt= r), @@ -1590,9 +1590,9 @@ TRANS_FLAGS2(VSX, XXLANDC, do_logical_op, MO_64, tcg_= gen_gvec_andc); TRANS_FLAGS2(VSX, XXLOR, do_logical_op, MO_64, tcg_gen_gvec_or); TRANS_FLAGS2(VSX, XXLXOR, do_logical_op, MO_64, tcg_gen_gvec_xor); TRANS_FLAGS2(VSX, XXLNOR, do_logical_op, MO_64, tcg_gen_gvec_nor); -TRANS_FLAGS2(VSX207, XXLEQV, do_logical_op, MO_64, tcg_gen_gvec_eqv); -TRANS_FLAGS2(VSX207, XXLNAND, do_logical_op, MO_64, tcg_gen_gvec_nand); -TRANS_FLAGS2(VSX207, XXLORC, do_logical_op, MO_64, tcg_gen_gvec_orc); +TRANS_FLAGS2(ISA207, XXLEQV, do_logical_op, MO_64, tcg_gen_gvec_eqv); +TRANS_FLAGS2(ISA207, XXLNAND, do_logical_op, MO_64, tcg_gen_gvec_nand); +TRANS_FLAGS2(ISA207, XXLORC, do_logical_op, MO_64, tcg_gen_gvec_orc); =20 #define VSX_XXMRG(name, high) \ static void glue(gen_, name)(DisasContext *ctx) \ @@ -2682,10 +2682,10 @@ TRANS_FLAGS2(ISA300, XSMINCDP, do_helper_XX3, gen_h= elper_XSMINCDP) TRANS_FLAGS2(ISA300, XSMAXJDP, do_helper_XX3, gen_helper_XSMAXJDP) TRANS_FLAGS2(ISA300, XSMINJDP, do_helper_XX3, gen_helper_XSMINJDP) =20 -TRANS_FLAGS2(VSX207, XSADDSP, do_helper_XX3, gen_helper_XSADDSP) -TRANS_FLAGS2(VSX207, XSSUBSP, do_helper_XX3, gen_helper_XSSUBSP) -TRANS_FLAGS2(VSX207, XSMULSP, do_helper_XX3, gen_helper_XSMULSP) -TRANS_FLAGS2(VSX207, XSDIVSP, do_helper_XX3, gen_helper_XSDIVSP) +TRANS_FLAGS2(ISA207, XSADDSP, do_helper_XX3, gen_helper_XSADDSP) +TRANS_FLAGS2(ISA207, XSSUBSP, do_helper_XX3, gen_helper_XSSUBSP) +TRANS_FLAGS2(ISA207, XSMULSP, do_helper_XX3, gen_helper_XSMULSP) +TRANS_FLAGS2(ISA207, XSDIVSP, do_helper_XX3, gen_helper_XSDIVSP) =20 TRANS_FLAGS2(VSX, XSADDDP, do_helper_XX3, gen_helper_XSADDDP) TRANS_FLAGS2(VSX, XSSUBDP, do_helper_XX3, gen_helper_XSSUBDP) diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-= ops.c.inc index e553b5b8fa..ae3df2c13d 100644 --- a/target/ppc/translate/vsx-ops.c.inc +++ b/target/ppc/translate/vsx-ops.c.inc @@ -1,9 +1,9 @@ -GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207= ), -GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207= ), -GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207= ), +GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_ISA207= ), +GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_ISA207= ), +GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_ISA207= ), #if defined(TARGET_PPC64) -GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207), -GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_ISA207), +GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_ISA207), GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300= ), GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300= ), @@ -127,7 +127,7 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001), GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001), GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300), GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX), -GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207), +GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_ISA207), GEN_XX2FORM_EO(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300), GEN_VSX_XFORM_300_EO(xscvsdqp, 0x04, 0x1A, 0x0A, 0x00000001), GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX), @@ -145,12 +145,12 @@ GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX), GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX), =20 GEN_VSX_XFORM_300(xsdivqp, 0x04, 0x11, 0x0), -GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207), -GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207), -GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207), -GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207), -GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207), -GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207), +GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_ISA207), +GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_ISA207), +GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_ISA207), +GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_ISA207), +GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_ISA207), +GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_ISA207), =20 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX), GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX), --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837727026158500 Content-Type: text/plain; charset="utf-8" PPC2_BCTAR_ISA207 is only ever set in the CPUPPCState's insns_flags2 alongside PPC2_ISA207. Checks made by PPC2_BCTAR_ISA207 could be replaced with PPC2_ISA207, hence rendering it useless and apt for removal. This patch does the same. Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- linux-user/ppc/elfload.c | 7 +++---- target/ppc/cpu.h | 4 +--- target/ppc/cpu_init.c | 2 +- target/ppc/cpu_init.h | 2 +- target/ppc/translate/branch-impl.c.inc | 2 +- 5 files changed, 7 insertions(+), 10 deletions(-) diff --git a/linux-user/ppc/elfload.c b/linux-user/ppc/elfload.c index 0d54da9803..5c6065e08a 100644 --- a/linux-user/ppc/elfload.c +++ b/linux-user/ppc/elfload.c @@ -116,10 +116,9 @@ abi_ulong get_elf_hwcap2(CPUState *cs) do { if (cpu->env.insns_flags2 & flag) { features |=3D feature; } } wh= ile (0) =20 GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL); - GET_FEATURE2(PPC2_BCTAR_ISA207, QEMU_PPC_FEATURE2_HAS_TAR); - GET_FEATURE2((PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA207S), QEMU_PPC_FEATURE2_ARCH_2_07 | - QEMU_PPC_FEATURE2_VEC_CRYPTO); + GET_FEATURE2((PPC2_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 | + QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR= )); GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 | QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128); GET_FEATURE2(PPC2_ISA310, QEMU_PPC_FEATURE2_ARCH_3_1 | diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 91ef34cb21..df1e943d8d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2577,8 +2577,6 @@ enum { PPC2_FP_CVT_ISA206 =3D 0x0000000000000400ULL, /* ISA 2.06B floating point test instructions = */ PPC2_FP_TST_ISA206 =3D 0x0000000000000800ULL, - /* ISA 2.07 bctar instruction = */ - PPC2_BCTAR_ISA207 =3D 0x0000000000001000ULL, /* ISA 2.07 load/store quadword = */ PPC2_LSQ_ISA207 =3D 0x0000000000002000ULL, /* ISA 2.07 Altivec = */ @@ -2610,7 +2608,7 @@ enum { PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ + PPC2_LSQ_ISA207 | \ PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index b913edd243..c250f805a7 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6349,7 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *d= ata) pcc->insns_flags2 =3D PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | + PPC2_FP_TST_ISA206 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index 1c41c0d349..7dd587908e 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -17,7 +17,7 @@ #define PPC_INSNS_FLAGS2_POWER_COMMON \ (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ - PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | \ + PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \ PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206) diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc index c51fd9b13e..e5b64ca84e 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -210,4 +210,4 @@ static bool bclr_helper(DisasContext *ctx, arg_bclr *a,= int type) =20 TRANS(BCLR, bclr_helper, BCOND_LR) TRANS(BCCTR, bclr_helper, BCOND_CTR) -TRANS_FLAGS2(BCTAR_ISA207, BCTAR, bclr_helper, BCOND_TAR) +TRANS_FLAGS2(ISA207, BCTAR, bclr_helper, BCOND_TAR) --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837819611158500 Content-Type: text/plain; charset="utf-8" PPC2_LSQ_ISA207 is only ever set in the CPUPPCState's insns_flags2 alongside PPC2_ISA207. Checks made by PPC2_LSQ_ISA207 could be replaced with PPC2_ISA207, hence rendering it useless and apt for removal. This patch does the same. Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- linux-user/ppc/elfload.c | 2 +- target/ppc/cpu.h | 3 --- target/ppc/cpu_init.c | 3 +-- target/ppc/cpu_init.h | 2 +- target/ppc/translate/fixedpoint-impl.c.inc | 4 ++-- 5 files changed, 5 insertions(+), 9 deletions(-) diff --git a/linux-user/ppc/elfload.c b/linux-user/ppc/elfload.c index 5c6065e08a..76ab9f43de 100644 --- a/linux-user/ppc/elfload.c +++ b/linux-user/ppc/elfload.c @@ -116,7 +116,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) do { if (cpu->env.insns_flags2 & flag) { features |=3D feature; } } wh= ile (0) =20 GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL); - GET_FEATURE2((PPC2_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + GET_FEATURE2((PPC2_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 | QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR= )); GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 | diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index df1e943d8d..b3cd8d85df 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2577,8 +2577,6 @@ enum { PPC2_FP_CVT_ISA206 =3D 0x0000000000000400ULL, /* ISA 2.06B floating point test instructions = */ PPC2_FP_TST_ISA206 =3D 0x0000000000000800ULL, - /* ISA 2.07 load/store quadword = */ - PPC2_LSQ_ISA207 =3D 0x0000000000002000ULL, /* ISA 2.07 Altivec = */ PPC2_ALTIVEC_207 =3D 0x0000000000004000ULL, /* PowerISA 2.07 Book3s specification = */ @@ -2608,7 +2606,6 @@ enum { PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_LSQ_ISA207 | \ PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c250f805a7..4cc8b93dca 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6349,8 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *d= ata) pcc->insns_flags2 =3D PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_FP_TST_ISA206 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index 7dd587908e..6961007926 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -18,7 +18,7 @@ (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \ + PPC2_ALTIVEC_207 | PPC2_ISA205 | \ PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206) =20 diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 0e1960a272..c3d8bbf267 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -124,7 +124,7 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, b= ool store, bool prefixed) =20 REQUIRE_INSNS_FLAGS(ctx, 64BX); =20 - if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) { + if (!prefixed && !(ctx->insns_flags2 & PPC2_ISA207)) { /* lq and stq were privileged prior to V. 2.07 */ REQUIRE_SV(ctx); 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=f0KcWXqJ82rksmt9w UFTAJIPCd6b60qa+2x2IBIKbBk=; b=qLsdO6gAGIHKShF2XE1CUIZZsCL09gLy5 aHocKlFcitCMXLeeqJHuSfWJo7VU9hPDt1ptSyZmsvpHCe7UPpJkNbkeSWoCO0N+ ZZu4f583/zBepGyU96UzVem3klYcGOdM1XyF8pyZEpQfsBtLCZSi3Y+ge+dzzOPU lzV2EERWnGQ2TXg/B6fHZbK+4sAPJY5JMkzLroAIZvfgTUjccsXvGvqylCqgi/Hg cL2YnJ7CKRFS1H6UjEtQEpv2NdkZe32G6kb19FMPEWsP7GTmXM7UAqRVjt7hQXd0 5EGx9GjBEwD+3l5DHGjY6uGVQyWETCianz2diwGL+ZVbb4sfmBbvQ== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 33/37] target/ppc: Use PPC2_ISA207 instead of PPC2_ALTIVEC_207 Date: Thu, 27 Aug 2026 18:59:48 +0530 Message-ID: <20260827133010.278889-34-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-ORIG-GUID: dc5SJqIxcGDHiXf38xnFBcb_x0PBX0sF X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfXwIxyj81DzX2q fFAqQJRmHaB5zrntIHeD5HzrZysaahy+10fdOtw5eKyqICNQF/0NvamobodWgPlMvGZHrOKQY8f Lu9aboxNpXH95AHEO5iuemTJ3Md7GCA= X-Proofpoint-GUID: SnEjU7d1SYhpzSOEg88H_TpJLn6GuiUV X-Authority-Analysis: v=2.4 cv=JZyMa0KV c=1 sm=1 tr=0 ts=6a903cd6 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8 a=KKAkSRfTAAAA:8 a=TVBnEkQHhD3h3QFkF50A:9 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfXx+mqiOJBVZmn yQ8WC5u1ymCkmLQKbY7JwjS/7L0AzZWsUNB4ML9aCAjpxzIX2A7uH+hNRNljaS/rpy8q1DBsG2x um8Tg6cyQFcCMnpBzQEaSwHU0tHGgxu2R1mcRcP+L6UuM9TIoCMxXybOfdk35coODV8LWu5MXPF L0VeWwz/DJoUrgoFXIK2NyfpEgv554vikr8V5AQVab93HI1xPZAfdI65CZM4BSQFVR/VnHmyEo4 3U5yp0AGKTc5N8idsxJG9XYWLKejA8bzYFvxQ6Ag/zHN6x+i9xhJs9ZCysQy6bzYVSctV/IbWSD 98xNmsKOmS5aqGEngy2OFG1nIiqezmsOn4RgXHJKLqoFpcuZoUiBu40Nk1BGGBj3s0jLFtriFPp fV4gcjyrw2r/vUrmklRbAN4oMnOnPZ9zGnLGsOkf7MviSWYfZexRZ/aVSSxvPvUSUWk7sBVIkzI 1Ax7PQPmRYAyNWmXNVg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 adultscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837821549158500 Content-Type: text/plain; charset="utf-8" PPC2_ALTIVEC_207 is only ever set in the CPUPPCState's insns_flags2 alongside PPC2_ISA207. Checks made by PPC2_ALTIVEC_207 could be replaced with PPC2_ISA207, hence rendering it useless and apt for removal. This patch does the same. Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- linux-user/ppc/elfload.c | 3 +- target/ppc/cpu.h | 4 +- target/ppc/cpu_init.c | 2 +- target/ppc/cpu_init.h | 3 +- target/ppc/translate/vmx-impl.c.inc | 102 ++++++++++++++-------------- target/ppc/translate/vmx-ops.c.inc | 18 ++--- 6 files changed, 64 insertions(+), 68 deletions(-) diff --git a/linux-user/ppc/elfload.c b/linux-user/ppc/elfload.c index 76ab9f43de..8c40f1a663 100644 --- a/linux-user/ppc/elfload.c +++ b/linux-user/ppc/elfload.c @@ -116,8 +116,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) do { if (cpu->env.insns_flags2 & flag) { features |=3D feature; } } wh= ile (0) =20 GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL); - GET_FEATURE2((PPC2_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 | + GET_FEATURE2((PPC2_ISA207 | PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_0= 7 | QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR= )); GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 | QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b3cd8d85df..00676cea2b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2577,8 +2577,6 @@ enum { PPC2_FP_CVT_ISA206 =3D 0x0000000000000400ULL, /* ISA 2.06B floating point test instructions = */ PPC2_FP_TST_ISA206 =3D 0x0000000000000800ULL, - /* ISA 2.07 Altivec = */ - PPC2_ALTIVEC_207 =3D 0x0000000000004000ULL, /* PowerISA 2.07 Book3s specification = */ PPC2_ISA207S =3D 0x0000000000008000ULL, /* Double precision floating point conversion for signed integer 64 = */ @@ -2606,7 +2604,7 @@ enum { PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ + PPC2_ISA207S | PPC2_DFP | \ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \ PPC2_BCDA_ISA206 | PPC2_PPE42 | PPC2_PPE42X | \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 4cc8b93dca..c251426b2e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6349,7 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *d= ata) pcc->insns_flags2 =3D PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_ALTIVEC_207 | + PPC2_FP_TST_ISA206 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index 6961007926..73f014c82a 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -17,8 +17,7 @@ #define PPC_INSNS_FLAGS2_POWER_COMMON \ (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ - PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_ALTIVEC_207 | PPC2_ISA205 | \ + PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_ISA205 | \ PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206) =20 diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 4e7fe22156..486f5c2151 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -351,14 +351,14 @@ static bool do_vx_vaddsubm(DisasContext *ctx, arg_VX = *a, MemOp vece, TRANS_FLAGS(ALTIVEC, VADDUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_add) TRANS_FLAGS(ALTIVEC, VADDUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_add) TRANS_FLAGS(ALTIVEC, VADDUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_add) -TRANS_FLAGS2(ALTIVEC_207, VADDUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_add) +TRANS_FLAGS2(ISA207, VADDUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_add) =20 TRANS_FLAGS(ALTIVEC, VSUBUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_sub) TRANS_FLAGS(ALTIVEC, VSUBUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_sub) TRANS_FLAGS(ALTIVEC, VSUBUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_sub) -TRANS_FLAGS2(ALTIVEC_207, VSUBUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_sub) +TRANS_FLAGS2(ISA207, VSUBUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_sub) =20 -TRANS_FLAGS2(ALTIVEC_207, VMULUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_mul) +TRANS_FLAGS2(ISA207, VMULUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_mul) =20 TRANS_FLAGS2(ISA300, VMUL10CUQ, do_vx_vmul10, false, true) TRANS_FLAGS2(ISA300, VMUL10ECUQ, do_vx_vmul10, true, true) @@ -699,22 +699,22 @@ static bool do_vector_gvec3_VX(DisasContext *ctx, arg= _VX *a, int vece, TRANS_FLAGS(ALTIVEC, VSLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shlv); TRANS_FLAGS(ALTIVEC, VSLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shlv); TRANS_FLAGS(ALTIVEC, VSLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shlv); -TRANS_FLAGS2(ALTIVEC_207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sh= lv); +TRANS_FLAGS2(ISA207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shlv); =20 TRANS_FLAGS(ALTIVEC, VSRB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shrv); TRANS_FLAGS(ALTIVEC, VSRH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shrv); TRANS_FLAGS(ALTIVEC, VSRW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shrv); -TRANS_FLAGS2(ALTIVEC_207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sh= rv); +TRANS_FLAGS2(ISA207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shrv); =20 TRANS_FLAGS(ALTIVEC, VSRAB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_sarv); TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv); TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv); -TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_s= arv); +TRANS_FLAGS2(ISA207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv); =20 TRANS_FLAGS(ALTIVEC, VRLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_rotlv) TRANS_FLAGS(ALTIVEC, VRLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_rotlv) TRANS_FLAGS(ALTIVEC, VRLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_rotlv) -TRANS_FLAGS2(ALTIVEC_207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_ro= tlv) +TRANS_FLAGS2(ISA207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_rotlv) =20 /* Logical operations */ TRANS_FLAGS(ALTIVEC, VAND, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_and); @@ -722,30 +722,30 @@ TRANS_FLAGS(ALTIVEC, VANDC, do_vector_gvec3_VX, MO_64= , tcg_gen_gvec_andc); TRANS_FLAGS(ALTIVEC, VOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_or); TRANS_FLAGS(ALTIVEC, VXOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_xor); TRANS_FLAGS(ALTIVEC, VNOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_nor); -TRANS_FLAGS2(ALTIVEC_207, VEQV, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_eq= v); -TRANS_FLAGS2(ALTIVEC_207, VNAND, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_n= and); -TRANS_FLAGS2(ALTIVEC_207, VORC, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_or= c); +TRANS_FLAGS2(ISA207, VEQV, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_eqv); +TRANS_FLAGS2(ISA207, VNAND, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_nand); +TRANS_FLAGS2(ISA207, VORC, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_orc); =20 /* Integer Max/Min operations */ TRANS_FLAGS(ALTIVEC, VMAXUB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_umax); TRANS_FLAGS(ALTIVEC, VMAXUH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_umax); TRANS_FLAGS(ALTIVEC, VMAXUW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_umax); -TRANS_FLAGS2(ALTIVEC_207, VMAXUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_= umax); +TRANS_FLAGS2(ISA207, VMAXUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_umax); =20 TRANS_FLAGS(ALTIVEC, VMAXSB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_smax); TRANS_FLAGS(ALTIVEC, VMAXSH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_smax); TRANS_FLAGS(ALTIVEC, VMAXSW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_smax); -TRANS_FLAGS2(ALTIVEC_207, VMAXSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_= smax); +TRANS_FLAGS2(ISA207, VMAXSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_smax); =20 TRANS_FLAGS(ALTIVEC, VMINUB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_umin); TRANS_FLAGS(ALTIVEC, VMINUH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_umin); TRANS_FLAGS(ALTIVEC, VMINUW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_umin); -TRANS_FLAGS2(ALTIVEC_207, VMINUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_= umin); +TRANS_FLAGS2(ISA207, VMINUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_umin); =20 TRANS_FLAGS(ALTIVEC, VMINSB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_smin); TRANS_FLAGS(ALTIVEC, VMINSH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_smin); TRANS_FLAGS(ALTIVEC, VMINSW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_smin); -TRANS_FLAGS2(ALTIVEC_207, VMINSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_= smin); +TRANS_FLAGS2(ISA207, VMINSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_smin); =20 static TCGv_vec do_vrl_mask_vec(unsigned vece, TCGv_vec vrb) { @@ -1091,16 +1091,16 @@ static bool do_vpk(DisasContext *ctx, arg_VX *a, =20 TRANS_FLAGS(ALTIVEC, VPKUHUM, do_vpk_env, gen_helper_VPKUHUM) TRANS_FLAGS(ALTIVEC, VPKUWUM, do_vpk_env, gen_helper_VPKUWUM) -TRANS_FLAGS2(ALTIVEC_207, VPKUDUM, do_vpk_env, gen_helper_VPKUDUM) +TRANS_FLAGS2(ISA207, VPKUDUM, do_vpk_env, gen_helper_VPKUDUM) TRANS_FLAGS(ALTIVEC, VPKUHUS, do_vpk_env, gen_helper_VPKUHUS) TRANS_FLAGS(ALTIVEC, VPKUWUS, do_vpk_env, gen_helper_VPKUWUS) -TRANS_FLAGS2(ALTIVEC_207, VPKUDUS, do_vpk_env, gen_helper_VPKUDUS) +TRANS_FLAGS2(ISA207, VPKUDUS, do_vpk_env, gen_helper_VPKUDUS) TRANS_FLAGS(ALTIVEC, VPKSHUS, do_vpk_env, gen_helper_VPKSHUS) TRANS_FLAGS(ALTIVEC, VPKSWUS, do_vpk_env, gen_helper_VPKSWUS) -TRANS_FLAGS2(ALTIVEC_207, VPKSDUS, do_vpk_env, gen_helper_VPKSDUS) +TRANS_FLAGS2(ISA207, VPKSDUS, do_vpk_env, gen_helper_VPKSDUS) TRANS_FLAGS(ALTIVEC, VPKSHSS, do_vpk_env, gen_helper_VPKSHSS) TRANS_FLAGS(ALTIVEC, VPKSWSS, do_vpk_env, gen_helper_VPKSWSS) -TRANS_FLAGS2(ALTIVEC_207, VPKSDSS, do_vpk_env, gen_helper_VPKSDSS) +TRANS_FLAGS2(ISA207, VPKSDSS, do_vpk_env, gen_helper_VPKSDSS) TRANS_FLAGS(ALTIVEC, VPKPX, do_vpk, gen_helper_VPKPX) GEN_VXFORM_ENV(vsum4ubs, 4, 24); GEN_VXFORM_ENV(vsum4sbs, 4, 28); @@ -1114,12 +1114,12 @@ GEN_VXFORM_ENV(vminfp, 5, 17); GEN_VXFORM_HETRO(vextublx, 6, 24) GEN_VXFORM_HETRO(vextuhlx, 6, 25) GEN_VXFORM_HETRO(vextuwlx, 6, 26) -GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207, +GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ISA207, vextuwlx, PPC_NONE, PPC2_ISA300) GEN_VXFORM_HETRO(vextubrx, 6, 28) GEN_VXFORM_HETRO(vextuhrx, 6, 29) GEN_VXFORM_HETRO(vextuwrx, 6, 30) -GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, +GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ISA207, vextuwrx, PPC_NONE, PPC2_ISA300) =20 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ @@ -1209,16 +1209,16 @@ static bool do_vcmp(DisasContext *ctx, arg_VC *a, T= CGCond cond, int vece) TRANS_FLAGS(ALTIVEC, VCMPEQUB, do_vcmp, TCG_COND_EQ, MO_8) TRANS_FLAGS(ALTIVEC, VCMPEQUH, do_vcmp, TCG_COND_EQ, MO_16) TRANS_FLAGS(ALTIVEC, VCMPEQUW, do_vcmp, TCG_COND_EQ, MO_32) -TRANS_FLAGS2(ALTIVEC_207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64) +TRANS_FLAGS2(ISA207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64) =20 TRANS_FLAGS(ALTIVEC, VCMPGTSB, do_vcmp, TCG_COND_GT, MO_8) TRANS_FLAGS(ALTIVEC, VCMPGTSH, do_vcmp, TCG_COND_GT, MO_16) TRANS_FLAGS(ALTIVEC, VCMPGTSW, do_vcmp, TCG_COND_GT, MO_32) -TRANS_FLAGS2(ALTIVEC_207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64) +TRANS_FLAGS2(ISA207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64) TRANS_FLAGS(ALTIVEC, VCMPGTUB, do_vcmp, TCG_COND_GTU, MO_8) TRANS_FLAGS(ALTIVEC, VCMPGTUH, do_vcmp, TCG_COND_GTU, MO_16) TRANS_FLAGS(ALTIVEC, VCMPGTUW, do_vcmp, TCG_COND_GTU, MO_32) -TRANS_FLAGS2(ALTIVEC_207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64) +TRANS_FLAGS2(ISA207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64) =20 TRANS_FLAGS2(ISA300, VCMPNEB, do_vcmp, TCG_COND_NE, MO_8) TRANS_FLAGS2(ISA300, VCMPNEH, do_vcmp, TCG_COND_NE, MO_16) @@ -2330,11 +2330,11 @@ static bool do_va_helper(DisasContext *ctx, arg_VA = *a, return true; } =20 -TRANS_FLAGS2(ALTIVEC_207, VADDECUQ, do_va_helper, gen_helper_VADDECUQ) -TRANS_FLAGS2(ALTIVEC_207, VADDEUQM, do_va_helper, gen_helper_VADDEUQM) +TRANS_FLAGS2(ISA207, VADDECUQ, do_va_helper, gen_helper_VADDECUQ) +TRANS_FLAGS2(ISA207, VADDEUQM, do_va_helper, gen_helper_VADDEUQM) =20 -TRANS_FLAGS2(ALTIVEC_207, VSUBEUQM, do_va_helper, gen_helper_VSUBEUQM) -TRANS_FLAGS2(ALTIVEC_207, VSUBECUQ, do_va_helper, gen_helper_VSUBECUQ) +TRANS_FLAGS2(ISA207, VSUBEUQM, do_va_helper, gen_helper_VSUBEUQM) +TRANS_FLAGS2(ISA207, VSUBECUQ, do_va_helper, gen_helper_VSUBECUQ) =20 TRANS_FLAGS(ALTIVEC, VPERM, do_va_helper, gen_helper_VPERM) TRANS_FLAGS2(ISA300, VPERMR, do_va_helper, gen_helper_VPERMR) @@ -2502,14 +2502,14 @@ GEN_VXFORM_NOA(vpopcntb, 1, 28) GEN_VXFORM_NOA(vpopcnth, 1, 29) GEN_VXFORM_NOA(vpopcntw, 1, 30) GEN_VXFORM_NOA(vpopcntd, 1, 31) -GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \ - vpopcntb, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \ - vpopcnth, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \ - vpopcntw, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \ - vpopcntd, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ISA207, \ + vpopcntb, PPC_NONE, PPC2_ISA207) +GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ISA207, \ + vpopcnth, PPC_NONE, PPC2_ISA207) +GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ISA207, \ + vpopcntw, PPC_NONE, PPC2_ISA207) +GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ISA207, \ + vpopcntd, PPC_NONE, PPC2_ISA207) GEN_VXFORM(vbpermd, 6, 23); GEN_VXFORM(vbpermq, 6, 21); GEN_VXFORM_TRANS(vgbbd, 6, 20); @@ -2589,8 +2589,8 @@ static bool do_bcd_tb_ps(DisasContext *ctx, arg_VX_tb= _ps *a, return true; } =20 -TRANS_FLAGS2(ALTIVEC_207, BCDADD, do_bcd_ps, gen_helper_BCDADD) -TRANS_FLAGS2(ALTIVEC_207, BCDSUB, do_bcd_ps, gen_helper_BCDSUB) +TRANS_FLAGS2(ISA207, BCDADD, do_bcd_ps, gen_helper_BCDADD) +TRANS_FLAGS2(ISA207, BCDSUB, do_bcd_ps, gen_helper_BCDSUB) TRANS_FLAGS2(ISA300, BCDUS, do_bcd, gen_helper_BCDUS) TRANS_FLAGS2(ISA300, BCDS, do_bcd_ps, gen_helper_BCDS) TRANS_FLAGS2(ISA300, BCDCFN, do_bcd_tb_ps, gen_helper_BCDCFN) @@ -2622,10 +2622,10 @@ GEN_VXFORM(vcipherlast, 4, 20) GEN_VXFORM(vncipher, 4, 21) GEN_VXFORM(vncipherlast, 4, 21) =20 -GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207, - vcipherlast, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207, - vncipherlast, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ISA207, + vcipherlast, PPC_NONE, PPC2_ISA207) +GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ISA207, + vncipherlast, PPC_NONE, PPC2_ISA207) =20 #define VSHASIGMA(op) \ static void gen_##op(DisasContext *ctx) \ @@ -2647,7 +2647,7 @@ VSHASIGMA(vshasigmad) =20 GEN_VXFORM3(vpermxor, 22, 0xFF) GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, - vpermxor, PPC_NONE, PPC2_ALTIVEC_207) + vpermxor, PPC_NONE, PPC2_ISA207) =20 static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a) { @@ -2815,13 +2815,13 @@ static bool do_vx_helper(DisasContext *ctx, arg_VX = *a, return true; } =20 -TRANS_FLAGS2(ALTIVEC_207, VADDCUQ, do_vx_helper, gen_helper_VADDCUQ) -TRANS_FLAGS2(ALTIVEC_207, VADDUQM, do_vx_helper, gen_helper_VADDUQM) +TRANS_FLAGS2(ISA207, VADDCUQ, do_vx_helper, gen_helper_VADDCUQ) +TRANS_FLAGS2(ISA207, VADDUQM, do_vx_helper, gen_helper_VADDUQM) =20 -TRANS_FLAGS2(ALTIVEC_207, VPMSUMD, do_vx_helper, gen_helper_VPMSUMD) +TRANS_FLAGS2(ISA207, VPMSUMD, do_vx_helper, gen_helper_VPMSUMD) =20 -TRANS_FLAGS2(ALTIVEC_207, VSUBCUQ, do_vx_helper, gen_helper_VSUBCUQ) -TRANS_FLAGS2(ALTIVEC_207, VSUBUQM, do_vx_helper, gen_helper_VSUBUQM) +TRANS_FLAGS2(ISA207, VSUBCUQ, do_vx_helper, gen_helper_VSUBCUQ) +TRANS_FLAGS2(ISA207, VSUBUQM, do_vx_helper, gen_helper_VSUBUQM) =20 static void gen_VADDCUW_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_ve= c b) { @@ -3092,10 +3092,10 @@ TRANS_FLAGS(ALTIVEC, VMULESH, do_vx_helper, gen_hel= per_VMULESH) TRANS_FLAGS(ALTIVEC, VMULOSH, do_vx_helper, gen_helper_VMULOSH) TRANS_FLAGS(ALTIVEC, VMULEUH, do_vx_helper, gen_helper_VMULEUH) TRANS_FLAGS(ALTIVEC, VMULOUH, do_vx_helper, gen_helper_VMULOUH) -TRANS_FLAGS2(ALTIVEC_207, VMULESW, do_vx_helper, gen_helper_VMULESW) -TRANS_FLAGS2(ALTIVEC_207, VMULOSW, do_vx_helper, gen_helper_VMULOSW) -TRANS_FLAGS2(ALTIVEC_207, VMULEUW, do_vx_helper, gen_helper_VMULEUW) -TRANS_FLAGS2(ALTIVEC_207, VMULOUW, do_vx_helper, gen_helper_VMULOUW) +TRANS_FLAGS2(ISA207, VMULESW, do_vx_helper, gen_helper_VMULESW) +TRANS_FLAGS2(ISA207, VMULOSW, do_vx_helper, gen_helper_VMULOSW) +TRANS_FLAGS2(ISA207, VMULEUW, do_vx_helper, gen_helper_VMULEUW) +TRANS_FLAGS2(ISA207, VMULOUW, do_vx_helper, gen_helper_VMULOUW) TRANS_FLAGS2(ISA310, VMULESD, do_vx_vmuleo, true , tcg_gen_muls2_i64) TRANS_FLAGS2(ISA310, VMULOSD, do_vx_vmuleo, false, tcg_gen_muls2_i64) TRANS_FLAGS2(ISA310, VMULEUD, do_vx_vmuleo, true , tcg_gen_mulu2_i64) diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-= ops.c.inc index c1951c6975..2facbc7cb4 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -2,7 +2,7 @@ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) =20 #define GEN_VXFORM_207(name, opc2, opc3) \ -GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_2= 07) +GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA207) =20 #define GEN_VXFORM_300(name, opc2, opc3) \ GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300) @@ -26,10 +26,10 @@ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10)= , 0x00000000, tp0, tp1), =20 GEN_VXFORM_300(vextublx, 6, 24), GEN_VXFORM_300(vextuhlx, 6, 25), -GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ISA207), GEN_VXFORM_300(vextubrx, 6, 28), GEN_VXFORM_300(vextuhrx, 6, 29), -GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ISA207), GEN_VXFORM_300(vsrv, 2, 28), GEN_VXFORM_300(vslv, 2, 29), GEN_VXFORM(vslo, 6, 16), @@ -113,10 +113,10 @@ GEN_VXFORM_UIMM(vctsxs, 5, 15), GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), =20 -GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ISA207), +GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ISA207), +GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ISA207), +GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ISA207), =20 GEN_VXFORM_300(vbpermd, 6, 23), GEN_VXFORM_207(vbpermq, 6, 21), @@ -127,8 +127,8 @@ GEN_VXFORM_207(vpmsumw, 4, 18), =20 GEN_VXFORM_207(vsbox, 4, 23), =20 -GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ISA207), +GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ISA207), =20 GEN_VXFORM_207(vshasigmaw, 1, 26), GEN_VXFORM_207(vshasigmad, 1, 27), --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837813499158500 Content-Type: text/plain; charset="utf-8" PPC2_ISA207S is only ever set in the CPUPPCState's insns_flags2 alongside PPC2_ISA207. Checks made by PPC2_ISA207S could be replaced with PPC2_ISA207, hence rendering it useless and apt for removal. This patch does the same. Reviewed-by: Amit Machhiwal Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- hw/ppc/spapr_caps.c | 2 +- linux-user/ppc/elfload.c | 2 +- target/ppc/cpu.h | 5 +---- target/ppc/cpu_init.c | 3 +-- target/ppc/cpu_init.h | 2 +- target/ppc/tcg-excp_helper.c | 8 ++++---- target/ppc/translate.c | 6 +++--- target/ppc/translate/bhrb-impl.c.inc | 4 ++-- target/ppc/translate/branch-impl.c.inc | 2 +- target/ppc/translate/processor-ctrl-impl.c.inc | 8 ++++---- 10 files changed, 19 insertions(+), 23 deletions(-) diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index f4a26a85b5..0d659e9b02 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -676,7 +676,7 @@ static void cap_ail_mode_3_apply(SpaprMachineState *spa= pr, =20 if (tcg_enabled()) { /* AIL-3 is only supported on POWER8 and above CPUs. */ - if (!(pcc->insns_flags2 & PPC2_ISA207S)) { + if (!(pcc->insns_flags2 & PPC2_ISA207)) { error_setg(errp, "TCG only supports cap-ail-mode-3 on POWER8 a= nd later CPUs"); error_append_hint(errp, "Try appending -machine cap-ail-mode-3= =3Doff\n"); return; diff --git a/linux-user/ppc/elfload.c b/linux-user/ppc/elfload.c index 8c40f1a663..7bf49e7c0b 100644 --- a/linux-user/ppc/elfload.c +++ b/linux-user/ppc/elfload.c @@ -116,7 +116,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) do { if (cpu->env.insns_flags2 & flag) { features |=3D feature; } } wh= ile (0) =20 GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL); - GET_FEATURE2((PPC2_ISA207 | PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_0= 7 | + GET_FEATURE2(PPC2_ISA207, (QEMU_PPC_FEATURE2_ARCH_2_07 | QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR= )); GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 | QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 00676cea2b..4a77607f80 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2577,8 +2577,6 @@ enum { PPC2_FP_CVT_ISA206 =3D 0x0000000000000400ULL, /* ISA 2.06B floating point test instructions = */ PPC2_FP_TST_ISA206 =3D 0x0000000000000800ULL, - /* PowerISA 2.07 Book3s specification = */ - PPC2_ISA207S =3D 0x0000000000008000ULL, /* Double precision floating point conversion for signed integer 64 = */ PPC2_FP_CVT_S64 =3D 0x0000000000010000ULL, /* Transactional Memory (ISA 2.07, Book II) = */ @@ -2603,8 +2601,7 @@ enum { #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX= | \ PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ - PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_ISA207S | PPC2_DFP | \ + PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_DFP= | \ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \ PPC2_BCDA_ISA206 | PPC2_PPE42 | PPC2_PPE42X | \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c251426b2e..6c626843c9 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6349,8 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *d= ata) pcc->insns_flags2 =3D PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_FP_TST_ISA206 | PPC2_ISA205 | PPC2_FP_CVT_S64= | PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; pcc->msr_mask =3D (1ull << MSR_SF) | diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index 73f014c82a..4ba559d8af 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -18,7 +18,7 @@ (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_ISA205 | \ - PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ + PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206) =20 #define PPC_INSNS_FLAGS2_POWER9 \ diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index d06d3f8642..93aedb0c8e 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -314,7 +314,7 @@ void ppc_cpu_debug_excp_handler(CPUState *cs) #if defined(TARGET_PPC64) CPUPPCState *env =3D cpu_env(cs); =20 - if (env->insns_flags2 & PPC2_ISA207S) { + if (env->insns_flags2 & PPC2_ISA207) { if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { env->spr[SPR_DAR] =3D cs->watchpoint_hit->hitaddr; @@ -336,7 +336,7 @@ bool ppc_cpu_debug_check_breakpoint(CPUState *cs) #if defined(TARGET_PPC64) CPUPPCState *env =3D cpu_env(cs); =20 - if (env->insns_flags2 & PPC2_ISA207S) { + if (env->insns_flags2 & PPC2_ISA207) { target_ulong priv; =20 priv =3D env->spr[SPR_CIABR] & PPC_BITMASK(62, 63); @@ -365,7 +365,7 @@ bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWa= tchpoint *wp) bool wt, wti, hv, sv, pr; uint32_t dawrx; =20 - if ((env->insns_flags2 & PPC2_ISA207S) && + if ((env->insns_flags2 & PPC2_ISA207) && (wp =3D=3D env->dawr_watchpoint[0])) { dawrx =3D env->spr[SPR_DAWRX0]; } else if ((env->insns_flags2 & PPC2_ISA310) && @@ -849,7 +849,7 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulo= ng rb) void helper_book3s_trace(CPUPPCState *env, target_ulong prev_ip) { uint32_t error_code =3D 0; - if (env->insns_flags2 & PPC2_ISA207S) { + if (env->insns_flags2 & PPC2_ISA207) { /* Load/store reporting, SRR1[35, 36] and SDAR, are not implemente= d. */ env->spr[SPR_POWER_SIAR] =3D prev_ip; error_code =3D PPC_BIT(33); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f46e2167ea..6408ed7de7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2775,7 +2775,7 @@ static inline void gen_op_mfspr(DisasContext *ctx) } } else { /* ISA 2.07 defines these as no-ops */ - if ((ctx->insns_flags2 & PPC2_ISA207S) && + if ((ctx->insns_flags2 & PPC2_ISA207) && (sprn >=3D 808 && sprn <=3D 811)) { /* This is a nop */ return; @@ -2841,7 +2841,7 @@ static void gen_mtspr(DisasContext *ctx) } } else { /* ISA 2.07 defines these as no-ops */ - if ((ctx->insns_flags2 & PPC2_ISA207S) && + if ((ctx->insns_flags2 & PPC2_ISA207) && (sprn >=3D 808 && sprn <=3D 811)) { /* This is a nop */ return; @@ -4135,7 +4135,7 @@ TRANS64(LDARX, do_load_locked, DEF_MEMOP(MO_UQ)) static bool trans_LQARX(DisasContext *ctx, arg_LQARX *a) { REQUIRE_64BIT(ctx); - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); #if defined(TARGET_PPC64) TCGv EA; TCGv_i128 t16; diff --git a/target/ppc/translate/bhrb-impl.c.inc b/target/ppc/translate/bh= rb-impl.c.inc index 3a19bc4555..4b3914a1f6 100644 --- a/target/ppc/translate/bhrb-impl.c.inc +++ b/target/ppc/translate/bhrb-impl.c.inc @@ -14,7 +14,7 @@ =20 static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrbe *arg) { - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); TCGv_i32 bhrbe =3D tcg_constant_i32(arg->bhrbe); gen_helper_mfbhrbe(cpu_gpr[arg->rt], tcg_env, bhrbe); return true; @@ -22,7 +22,7 @@ static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrb= e *arg) =20 static bool trans_CLRBHRB(DisasContext *ctx, arg_CLRBHRB *arg) { - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); gen_helper_clrbhrb(tcg_env); return true; } diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc index e5b64ca84e..51fcabff63 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -14,7 +14,7 @@ =20 static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) { - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); =20 translator_io_start(&ctx->base); gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/tr= anslate/processor-ctrl-impl.c.inc index cfcca28267..cb125cfa72 100644 --- a/target/ppc/translate/processor-ctrl-impl.c.inc +++ b/target/ppc/translate/processor-ctrl-impl.c.inc @@ -23,7 +23,7 @@ =20 static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a) { - if (!(ctx->insns_flags2 & PPC2_ISA207S)) { + if (!(ctx->insns_flags2 & PPC2_ISA207)) { /* * Before Power ISA 2.07, processor control instructions were only * implemented in the "Embedded.Processor Control" category. @@ -47,7 +47,7 @@ static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a) =20 static bool trans_MSGSND(DisasContext *ctx, arg_X_rb *a) { - if (!(ctx->insns_flags2 & PPC2_ISA207S)) { + if (!(ctx->insns_flags2 & PPC2_ISA207)) { /* * Before Power ISA 2.07, processor control instructions were only * implemented in the "Embedded.Processor Control" category. @@ -72,7 +72,7 @@ static bool trans_MSGSND(DisasContext *ctx, arg_X_rb *a) static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a) { REQUIRE_64BIT(ctx); - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); REQUIRE_SV(ctx); #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) gen_helper_book3s_msgclrp(tcg_env, cpu_gpr[a->rb]); @@ -85,7 +85,7 @@ static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a) static bool trans_MSGSNDP(DisasContext *ctx, arg_X_rb *a) { REQUIRE_64BIT(ctx); - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); REQUIRE_SV(ctx); #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) gen_helper_book3s_msgsndp(tcg_env, cpu_gpr[a->rb]); --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1787837688; cv=none; d=zohomail.com; s=zohoarc; b=FpqH7ipRtU3DnayKuwpSSDHxIXSdFrl3z64/Vob6mrEr1UjEhdS4XdUjOFb2PiCdedIcaFQc20TQAJ2U/jJBQYcrN5LOxzWQwKB6QqaA2G9oWwsJyuFST7iTde+ns8XKn9OXRr7yd9DlzBanlUfc6nij34Dn83YYCZhomDjVl4c= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=tnlQIZ+8F1awsQZgS BNauADfqrfN6SbSYPpUe51qZu0=; b=bbEUjrnrP7TNL8gCZeBpwnJbIxqKoGX/a fw+drW5LwtWQSH3XqzOZ5D9ox2WOtIIGnyd9UbOMJP/1bxnD4hHRPgjGi0s4v9Oq ZmxeK8E55Oi9URyXM54uS6uosgLLehCqEEbsSaXdopoHS2rs0g5Jg1UYxk+HwM2X kvIUTTagg2+sogSWfdJeNHkZu4ozsVI79Rg1zn4dmjnKF1TEEWDql9728liwKvpq e5XcM0BB3O2fUHuRcH2EsoD0SmyamoQO1aw0Zjb2uzGFyV/Ck91JAWApdGzH5j9t 7+hpMgd4Z97eZclEgK1YcTc7MjadhBC8jFZ+xpLNbews0984woE7g== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [PATCH v3 35/37] target/ppc: Reorder PPC2 flags Date: Thu, 27 Aug 2026 18:59:50 +0530 Message-ID: <20260827133010.278889-36-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: XYNaCYcPyJOlsdhvZFDxgmaQWWhq8bkO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX6GOVJRmB/m81 SzwwpFPrWOibMtmPI0Nrz0CYT74kvzzBGrlZamtXL4v+aDLHzKDD399epULE26rCC9nvt5HMvc+ F+cJmKy9NNg4ghEekPPCG3RBjMp2zt+RWzaOHalJ6LVggOMW8hRTeHIoeSylH7YveyI6z6qPavG KRsuCLyStZ61qbKnw8KGaGjbRtAPFA5nsBkoQ8Y/8Awo9A840MH0HtXRRaQSjeNlmmbKtOEtNbG K9cVbOT3f/9UTh9mm2cDHVoBpdRsOfJRurUo/vCNYEVVOAHciJnvaItZeXG93hI7Tvr3o3ES7O1 Q8kZ4mMFS9ZK/GGmnBw3NcHZLRfeormczezg8TiZH890GG4msbAVwqIcAGtFIUiOWMBl9pmoRBW 2ctfrlm7ccNMN9FdVbN3Q9PVHOSqvfq5nxssufohIpd2xjGOPKO80Ys9tltLY1q1iUndDyCtBvj YRc/nsx8DutpECMS7WQ== X-Authority-Analysis: v=2.4 cv=Y/nIdBeN c=1 sm=1 tr=0 ts=6a903cdf cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=KKAkSRfTAAAA:8 a=n9CTefPPWk96pEdnryYA:9 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX25mDbIG5doGT HEzakT/Wmy9EjwtrARSPFrEGfjHY47BDdCn1O+9kMkNILkREFrC8paRmbeF8d8+NxEsPyxxK+wF O8bF0LL4UrN9RypGHMnRH1uS/I1ywa0= X-Proofpoint-ORIG-GUID: 1DKLOoWSk89AGykSpdNMfgi3gJLpw3N_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837688753158500 Content-Type: text/plain; charset="utf-8" Consolidation of different variations of Power ISA 2.07 flags into the PPC2_ISA207 flag has left gaps in the flag encoding. This patch reorders them, restoring the expected incremental order without any gaps, freeing up bits for future use. Reviewed-by: Amit Machhiwal Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/cpu.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 4a77607f80..3fb51bbeb8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2578,25 +2578,25 @@ enum { /* ISA 2.06B floating point test instructions = */ PPC2_FP_TST_ISA206 =3D 0x0000000000000800ULL, /* Double precision floating point conversion for signed integer 64 = */ - PPC2_FP_CVT_S64 =3D 0x0000000000010000ULL, + PPC2_FP_CVT_S64 =3D 0x0000000000001000ULL, /* Transactional Memory (ISA 2.07, Book II) = */ - PPC2_TM =3D 0x0000000000020000ULL, + PPC2_TM =3D 0x0000000000002000ULL, /* Server PM instructgions (ISA 2.06, Book III) = */ - PPC2_PM_ISA206 =3D 0x0000000000040000ULL, + PPC2_PM_ISA206 =3D 0x0000000000004000ULL, /* POWER ISA 3.0 = */ - PPC2_ISA300 =3D 0x0000000000080000ULL, + PPC2_ISA300 =3D 0x0000000000008000ULL, /* POWER ISA 3.1 = */ - PPC2_ISA310 =3D 0x0000000000100000ULL, + PPC2_ISA310 =3D 0x0000000000010000ULL, /* lwsync instruction = */ - PPC2_MEM_LWSYNC =3D 0x0000000000200000ULL, + PPC2_MEM_LWSYNC =3D 0x0000000000020000ULL, /* ISA 2.06 BCD assist instructions = */ - PPC2_BCDA_ISA206 =3D 0x0000000000400000ULL, + PPC2_BCDA_ISA206 =3D 0x0000000000040000ULL, /* PPE42 instructions = */ - PPC2_PPE42 =3D 0x0000000000800000ULL, + PPC2_PPE42 =3D 0x0000000000080000ULL, /* PPE42X instructions = */ - PPC2_PPE42X =3D 0x0000000001000000ULL, + PPC2_PPE42X =3D 0x0000000000100000ULL, /* PPE42XM instructions = */ - PPC2_PPE42XM =3D 0x0000000002000000ULL, + PPC2_PPE42XM =3D 0x0000000000200000ULL, =20 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX= | \ PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 27 Aug 2026 13:34:25 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 23A1120040; Thu, 27 Aug 2026 13:34:19 +0000 (GMT) Received: from li-18a0a34c-33fc-11b2-a85c-d9f1631c5692.ibm.com (unknown [9.111.12.1]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 27 Aug 2026 13:34:18 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=ruhDXg6Jy0EavW7Ok EbLPkYuUWpA7LPgZmz11PRcUYg=; b=R5x8qB+HdnrXkbzECnw0PDONZ9QAE4CSp 6sFuEa+GA62rP6mkeTdwYwxQSurALFs19UlraPCVKOF29SbpSQIeuy2u4wxQ6yZI MkcD1e18H6WjvSRQU5XSUHY4wiL6zVR8QEctLfeyx4idy56JTsDphesiS2yzc7sk KN8CJStmCnZY0zJy6bquLIYRsiSfjJKvgtIa5rxD8la5OkRRq1iUY1tEJzqWJZNo Ct5gLrGoaZ6eitn3bg0kDzSQWWMxFAOjQ4lT+kPLFoZFRVRdaeP1+9kjdG7YETmP 6WbSZIFetZFB3sJNDPUeaXEKfuUU+xg/1G557PVgJlIgNw7WRWuRw== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath , Tasmiya Nalatwad Subject: [PATCH v3 36/37] target/ppc: Add ICBT support for ISA version 2.07 Date: Thu, 27 Aug 2026 18:59:51 +0530 Message-ID: <20260827133010.278889-37-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: jzj3zbeGllzZNH4Aqx2ATYnhjovZuW-9 X-Proofpoint-ORIG-GUID: g52qGeGt8TrneWt6hlxuPJ2YC5Lene00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfXwVx55PhumPks mDgBdpSuyWleZ+Hft4XcctpsouIFTTETFZmhRm9ZWsqjqpKORS/zsQmUJ4nQmLdQRbMA5RGdv1X /Ek6AtpQus8RQjHAqBG5BnmoRCqL6m6TT4QxoxwI9RDzHAeJYnu9ZVcjMNTCbAFVpxqSME0uqeM RhFdyqQg4SYfKtc17r69iPg8S6cFOKDH0pgh2/SocSytmMPB/OHUsfbqBoLTklVF6JJ272lnVjc FOJ5ynAZg3IAmn9CPU33dzfXPKwEAtksGsBsuDrAR42gWrsS19IthKSh9EWyJGgWTPTpFlGDjLI TLjfBfdwIBFBP4uWiqxAjl7XcQj+XHLMAQlA/1Z9K9BiRUvlGwi6d5lhfa21Fr1/3SBpYO6PuPz gPL9HFDqZ7epm8oW0JNC3cw4DZZnswsaZGLgql1DLy4IQ1cxzzc80rJq8iUte9bVKyIXmo+GqK9 IFwmB4Oe4hh1YGbuTZg== X-Authority-Analysis: v=2.4 cv=QsRuG1yd c=1 sm=1 tr=0 ts=6a903ce6 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=KKAkSRfTAAAA:8 a=VhmWRyikh7PcAoWILYgA:9 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX08WfpAb39rjS /ayLg534IjEJaJOST2+ErklGc5c369+YGnX2A5UvHnlSPv35R5v7AKxAgN5vFFFOPeUYVX/d6jE k31ePHWyqvb7A+sAt1FIWieITPjsjqE= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837819635158500 Content-Type: text/plain; charset="utf-8" The summary of changes in Power ISA version 2.07B mentions : "ICBT instruction has been moved from the Embedded category to the Base category". Updating ICBT flag for the same. While we are at it, correct the invalid mask as per the ISA as well. Reviewed-by: Amit Machhiwal Tested-by: Tasmiya Nalatwad Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- target/ppc/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 6408ed7de7..148d9f17d7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4498,8 +4498,8 @@ GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12,= 0x00, 0x03800001, GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), -GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, - PPC_BOOKE, PPC2_BOOKE206), +GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x02000001, + PPC_BOOKE, (PPC2_BOOKE206 | PPC2_ISA207)), GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_440_SPEC), GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), --=20 2.55.0 From nobody Sat Sep 26 21:35:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 27 Aug 2026 13:34:32 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B3F7C20040; Thu, 27 Aug 2026 13:34:25 +0000 (GMT) Received: from li-18a0a34c-33fc-11b2-a85c-d9f1631c5692.ibm.com (unknown [9.111.12.1]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 27 Aug 2026 13:34:25 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=Nxu+VgowzuJklGjoJ LtZ+xUnfmSCsm7cXPMOi10zmlw=; b=A9wtESbS5Rqdqj914+inesbFocPgT1BzF RslGI8z88oUZBPHOHfNNfHTH4muVYJzjugUgF9isrKvDDbo67buhEjm0STaA0/SU ixZzwDNTo6pgIMKGHG03h56jijN34hUIOo1Hk25wSLco8gH6kG+Vu55hzhLT01OB 8BcoMh+nA3yxJhho4nQfUSJFJRcKdqlIEj5+ZZxydUiUN9R+CNcqKXlui029QRK6 X7D7jBpC5j88qL8s+lrXu7F6pyYt+THNR9gnvGtCEO53/x0Cm+ny07cOyqMpHMbX r2JwuOwYzq1HaIoorEaewvuYWP6a+yy2ucO9lXiqmmJBOQzy4XFOw== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com, milesg@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath , Aditya Gupta , Gautam Menghani Subject: [PATCH v3 37/37] target/ppc: Add self as maintainer for PowerPC TCG CPUs Date: Thu, 27 Aug 2026 18:59:52 +0530 Message-ID: <20260827133010.278889-38-rathc@linux.ibm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827133010.278889-1-rathc@linux.ibm.com> References: <20260827133010.278889-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=TfimcxQh c=1 sm=1 tr=0 ts=6a903ced cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VnNF1IyMAAAA:8 a=pGLkceISAAAA:8 a=69wJf7TsAAAA:8 a=m3VQ6hfItiEfsWDAiLMA:9 a=Fg1AiH1G6rFz08G2ETeA:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX3e/4wAl1Jnkk Oc2X/t75WiPCrC/BWEb/xHltt1UZlT+YtpLsIrwBMcMO+pHTZap4vndfx+ATIsc3qATzu0KLFUe o+Q92DkM4NE+RmgRSKG5BK6eOWmDYV4= X-Proofpoint-GUID: RsOpiFVC_wkvM1WpZfeVARjTu5c5b5qQ X-Proofpoint-ORIG-GUID: Q8m6oE7UNfgrxDA_rb-4AC5f2xUIVLK2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDExMyBTYWx0ZWRfX6/mygMwukgAu lDHn+QHfYUxa+G7Z39VYPUQo7YeCLi83oscouljGE/o8+ZdxrWi6+meoiWwhbWIO2HL7GZotm7n em7Ej9xpISpY/aLl/Z7/CIbyb4CU0d/7CncSWtGDgAyojpi6zLusajIwDV6Yo4RMQvipcArw/s2 tGVlA9RXjwSeV+wqifocpN1TkMrJ/enYMBAHazXM4mdNZn9fD5DhXERAg5FnkXKgA6RbQEI9Vpg iDMYvm5TbVnckv/bZWIoZ478oC1A1XKo9pgiZNgspUouii4p6KSI4MGiV4r5G0QR+YGbIKhe8ed NQU+XmHQrMqMO8d379G9wZ781WrIHYzqtNQNWd9t8u0R/e+Gsb4MzAWspQVy1oX5yMfmXJdH4Ue NeEk9hWYXlHlRloXFJK+2+xXHeGoIuV5DAi6suejYrBVNZOXzXOOR8+hA0ZeAd8z4Xj6oA/4Oa7 hmjqpbX1nspjhUBCZpg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 phishscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1787837781368158500 Content-Type: text/plain; charset="utf-8" I have been contributing and reviewing code in the PowerPC TCG CPUs module for a long time now. Stepping up as an active maintainer to better reflect the current status. Acked-by: Aditya Gupta Acked-by: Gautam Menghani Acked-by: Amit Machhiwal Signed-off-by: Chinmay Rath Tested-by: Aniket Sahu --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 2a0ee348c4..f040083503 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -337,8 +337,8 @@ F: tests/functional/or1k/meson.build F: tests/tcg/or1k/ =20 PowerPC TCG CPUs +M: Chinmay Rath M: Nicholas Piggin -R: Chinmay Rath R: Glenn Miles R: Harsh Prateek Bora L: qemu-ppc@nongnu.org --=20 2.55.0