From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787817185178102.24302369705936; Thu, 27 Aug 2026 00:53:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzUu8-0003rf-Av; Thu, 27 Aug 2026 03:52:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wzUu6-0003qz-0I for qemu-devel@nongnu.org; Thu, 27 Aug 2026 03:52:06 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzUu2-00050k-Bu for qemu-devel@nongnu.org; Thu, 27 Aug 2026 03:52:05 -0400 Received: from loongson.cn (unknown [10.40.46.54]) by gateway (Coremail) with SMTP id _____8CxQNGa7I9qtpwFAA--.15928S3; Thu, 27 Aug 2026 15:51:54 +0800 (CST) Received: from fedora.loongson.cn (unknown [10.40.46.54]) by front1 (Coremail) with SMTP id qMiowJAxnM6Z7I9qFvwTAA--.16948S3; Thu, 27 Aug 2026 15:51:53 +0800 (CST) From: Bibo Mao To: Song Gao <17746591750@163.com> Cc: Xianglai Li , Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 1/3] hw/intc/loongarch_ipi: Add ipi interrupt status display Date: Thu, 27 Aug 2026 15:53:08 +0800 Message-ID: <20260827075310.1389232-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260827075310.1389232-1-maobibo@loongson.cn> References: <20260827075310.1389232-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxnM6Z7I9qFvwTAA--.16948S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBj93XoWxAry7Xr47JF4xKr1ftr4DJrc_yoW5Xw4rpF W3uF45Cr48AFsrGrZxA3sIqFn8Gw1xZFy7uFs7C348AFWUJrn0qayIyr9xXFyUC3y8GF1Y qw4fJa4q9a1UArcCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUk2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r126r13M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxU7cdbUUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1787817187249158500 Content-Type: text/plain; charset="utf-8" When irqchip in kernel is enabled, the register status of ipi irqchip is in KVM kernel. Here add interrupt status display in user side in order to debug irqchip driver. Signed-off-by: Bibo Mao Reviewed-by: Xianglai Li --- hw/intc/loongarch_ipi.c | 42 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 5d8b8c96df..28d816e3f5 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -9,6 +9,7 @@ #include "qemu/error-report.h" #include "hw/core/boards.h" #include "qapi/error.h" +#include "hw/intc/intc.h" #include "hw/intc/loongarch_ipi.h" #include "hw/core/qdev-properties.h" #include "system/kvm.h" @@ -193,8 +194,47 @@ static int loongarch_ipi_post_load(void *opaque, int v= ersion_id) return 0; } =20 +static void loongarch_ipi_print_info(InterruptStatsProvider *obj, GString = *buf) +{ + LoongsonIPICommonState *lics =3D LOONGSON_IPI_COMMON(obj); + int i, j; + IPICore *core; + uint64_t mbx; + unsigned long pos; + + loongarch_ipi_pre_save(lics); + + g_string_append_printf(buf, "%s:\n", object_get_typename(OBJECT(obj))); + for (i =3D 0; i < lics->num_cpu; i++) { + core =3D lics->cpu + i; + /* IPI with targeted CPU available however not present */ + if (!core->cpu) { + continue; + } + + g_string_append_printf(buf, " CPU %-3u status=3D0x%x en=3D0x%x\n", + i, core->status, core->en); + + pos =3D find_first_bit((unsigned long *)core->buf, IPI_MBX_NUM * 6= 4); + /* All zero in mailbox */ + if (pos =3D=3D (IPI_MBX_NUM * 64)) { + continue; + } + + for (j =3D 0; j < IPI_MBX_NUM; j++) { + mbx =3D *(uint64_t *)&core->buf[2 * j]; + if (mbx) { + g_string_append_printf(buf, " MBX[%-1u] 0x%016"PRIx64, j,= mbx); + } + } + + g_string_append_c(buf, '\n'); + } +} + static void loongarch_ipi_class_init(ObjectClass *klass, const void *data) { + InterruptStatsProviderClass *ic =3D INTERRUPT_STATS_PROVIDER_CLASS(kla= ss); LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_CLASS(klass); HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); LoongarchIPIClass *lic =3D LOONGARCH_IPI_CLASS(klass); @@ -211,6 +251,7 @@ static void loongarch_ipi_class_init(ObjectClass *klass= , const void *data) hc->unplug =3D loongarch_ipi_cpu_unplug; licc->pre_save =3D loongarch_ipi_pre_save; licc->post_load =3D loongarch_ipi_post_load; + ic->print_info =3D loongarch_ipi_print_info; } =20 static const TypeInfo loongarch_ipi_types[] =3D { @@ -222,6 +263,7 @@ static const TypeInfo loongarch_ipi_types[] =3D { .class_init =3D loongarch_ipi_class_init, .interfaces =3D (const InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, + { TYPE_INTERRUPT_STATS_PROVIDER }, { } }, } --=20 2.54.0 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178781716942731.9776651155006; Thu, 27 Aug 2026 00:52:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzUu9-0003ul-PF; Thu, 27 Aug 2026 03:52:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wzUu6-0003rH-LL for qemu-devel@nongnu.org; Thu, 27 Aug 2026 03:52:06 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzUu3-00050j-Eu for qemu-devel@nongnu.org; Thu, 27 Aug 2026 03:52:06 -0400 Received: from loongson.cn (unknown [10.40.46.54]) by gateway (Coremail) with SMTP id _____8Ax39Ka7I9quZwFAA--.15510S3; Thu, 27 Aug 2026 15:51:54 +0800 (CST) Received: from fedora.loongson.cn (unknown [10.40.46.54]) by front1 (Coremail) with SMTP id qMiowJAxnM6Z7I9qFvwTAA--.16948S4; Thu, 27 Aug 2026 15:51:54 +0800 (CST) From: Bibo Mao To: Song Gao <17746591750@163.com> Cc: Xianglai Li , Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 2/3] hw/intc/loongarch_pch_pic: Add pic interrupt status display Date: Thu, 27 Aug 2026 15:53:09 +0800 Message-ID: <20260827075310.1389232-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260827075310.1389232-1-maobibo@loongson.cn> References: <20260827075310.1389232-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxnM6Z7I9qFvwTAA--.16948S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBj93XoWxJFW5Jr45GFWfury8Jw43urX_yoW5CF43pF W7uFnxJr4DGFsrXr93Z345ZF1FqFyxur13KanxA3y0krZ8Gr1DXa48trW29F1UK393Cr12 gws5t3WYg3WUCrbCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUk2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxU2nYFDUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1787817172924158500 Content-Type: text/plain; charset="utf-8" When irqchip in kernel is enabled, the register status of pch_pic irqchip is in KVM kernel. Here add interrupt status display in user side in order to debug pch_pic irqchip driver. Signed-off-by: Bibo Mao Reviewed-by: Xianglai Li --- hw/intc/loongarch_pch_pic.c | 38 +++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index e87c7497c1..34090514ec 100644 --- a/hw/intc/loongarch_pch_pic.c +++ b/hw/intc/loongarch_pch_pic.c @@ -9,6 +9,7 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "hw/core/irq.h" +#include "hw/intc/intc.h" #include "hw/intc/loongarch_pch_pic.h" #include "system/kvm.h" #include "trace.h" @@ -331,11 +332,43 @@ static int loongarch_pic_post_load(LoongArchPICCommon= State *opaque, return 0; } =20 +static void loongarch_pic_print_info(InterruptStatsProvider *obj, GString = *buf) +{ + LoongArchPICCommonState *s =3D LOONGARCH_PIC_COMMON(obj); + uint64_t *vector; + + loongarch_pic_pre_save(s); + g_string_append_printf(buf, "%s:\n", object_get_typename(OBJECT(obj))); + + g_string_append_printf(buf, " mask 0x%016"PRIx64" msi_en 0x%016"P= RIx64 + " edge 0x%016"PRIx64" clr 0x%016"PRIx64= "\n", + s->int_mask, s->htmsi_en, s->intedge, + s->intclr); + + g_string_append_printf(buf, " last_irr 0x%016"PRIx64" irr 0x%016"P= RIx64 + " isr 0x%016"PRIx64" polary 0x%016"PRIx64= "\n", + s->last_intirr, s->intirr, s->intisr, + s->int_polarity); + + vector =3D (uint64_t *)s->htmsi_vector; + g_string_append_printf(buf, " MSI map 0x%016"PRIx64" 0x%016"PRIx64 + " 0x%016"PRIx64" 0x%016"PRIx64"\n", + *vector, *(vector + 1), *(vector + 2), + *(vector + 3)); + + vector +=3D 4; + g_string_append_printf(buf, " 0x%016"PRIx64" 0x%016"PRIx64 + " 0x%016"PRIx64" 0x%016"PRIx64"\n", + *vector, *(vector + 1), *(vector + 2), + *(vector + 3)); +} + static void loongarch_pic_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); LoongarchPICClass *lpc =3D LOONGARCH_PIC_CLASS(klass); LoongArchPICCommonClass *lpcc =3D LOONGARCH_PIC_COMMON_CLASS(klass); + InterruptStatsProviderClass *ic =3D INTERRUPT_STATS_PROVIDER_CLASS(kla= ss); ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 resettable_class_set_parent_phases(rc, NULL, loongarch_pic_reset_hold, @@ -344,6 +377,7 @@ static void loongarch_pic_class_init(ObjectClass *klass= , const void *data) &lpc->parent_realize); lpcc->pre_save =3D loongarch_pic_pre_save; lpcc->post_load =3D loongarch_pic_post_load; + ic->print_info =3D loongarch_pic_print_info; } =20 static const TypeInfo loongarch_pic_types[] =3D { @@ -353,6 +387,10 @@ static const TypeInfo loongarch_pic_types[] =3D { .instance_size =3D sizeof(LoongarchPICState), .class_size =3D sizeof(LoongarchPICClass), .class_init =3D loongarch_pic_class_init, + .interfaces =3D (const InterfaceInfo[]) { + { TYPE_INTERRUPT_STATS_PROVIDER }, + { } + }, } }; =20 --=20 2.54.0 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787817169543170.19116141750067; Thu, 27 Aug 2026 00:52:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzUu9-0003tL-3T; Thu, 27 Aug 2026 03:52:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wzUu6-0003r8-Cg for qemu-devel@nongnu.org; Thu, 27 Aug 2026 03:52:06 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzUu4-00050i-1m for qemu-devel@nongnu.org; Thu, 27 Aug 2026 03:52:06 -0400 Received: from loongson.cn (unknown [10.40.46.54]) by gateway (Coremail) with SMTP id _____8DxC9Ka7I9qvJwFAA--.15858S3; Thu, 27 Aug 2026 15:51:54 +0800 (CST) Received: from fedora.loongson.cn (unknown [10.40.46.54]) by front1 (Coremail) with SMTP id qMiowJAxnM6Z7I9qFvwTAA--.16948S5; Thu, 27 Aug 2026 15:51:54 +0800 (CST) From: Bibo Mao To: Song Gao <17746591750@163.com> Cc: Xianglai Li , Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 3/3] hw/intc/loongarch_extioi: Add extioi interrupt status display Date: Thu, 27 Aug 2026 15:53:10 +0800 Message-ID: <20260827075310.1389232-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260827075310.1389232-1-maobibo@loongson.cn> References: <20260827075310.1389232-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxnM6Z7I9qFvwTAA--.16948S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBj93XoWxZryUtw1DuFyDur45Ww15Awc_yoW5KrWfpF 43uFW3Wr4UGanxJr9xWayDuF1rtws3ur12qFZFv348uayUGryDuas2qry7XF4UCws7K3Wv kwn5tryYgF1DArcCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUk2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5McIj6I8E87Iv 67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxUcCD7UUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1787817173221158500 Content-Type: text/plain; charset="utf-8" When irqchip in kernel is enabled, the register status of extioi irqchip is in KVM kernel. Here add interrupt status display in user side in order to debug extioi irqchip driver. Signed-off-by: Bibo Mao Reviewed-by: Xianglai Li --- hw/intc/loongarch_extioi.c | 58 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c index 2999740269..06f2aa7b14 100644 --- a/hw/intc/loongarch_extioi.c +++ b/hw/intc/loongarch_extioi.c @@ -10,6 +10,7 @@ #include "qemu/log.h" #include "qapi/error.h" #include "hw/core/irq.h" +#include "hw/intc/intc.h" #include "hw/loongarch/virt.h" #include "system/address-spaces.h" #include "system/kvm.h" @@ -420,11 +421,63 @@ static int vmstate_extioi_post_load(void *opaque, int= version_id) return 0; } =20 +static void loongarch_extioi_print_info(InterruptStatsProvider *obj, + GString *buf) +{ + LoongArchExtIOICommonState *s =3D LOONGARCH_EXTIOI_COMMON(obj); + uint64_t *val; + unsigned long irq; + ExtIOICore *core; + int i; + + vmstate_extioi_pre_save(s); + g_string_append_printf(buf, "%s:\n", object_get_typename(OBJECT(obj))); + + val =3D (uint64_t *)s->isr; + g_string_append_printf(buf, " ISR 0x%016"PRIx64" 0x%016"PRIx64 + " 0x%016"PRIx64" 0x%016"PRIx64"\n", + *val, *(val + 1), *(val + 2), *(val + 3)); + val =3D (uint64_t *)s->enable; + g_string_append_printf(buf, " ENABLE 0x%016"PRIx64" 0x%016"PRIx64 + " 0x%016"PRIx64" 0x%016"PRIx64"\n", + *val, *(val + 1), *(val + 2), *(val + 3)); + val =3D (uint64_t *)s->ipmap; + g_string_append_printf(buf, " IPMAP 0x%016"PRIx64"\n", *val); + + val =3D (uint64_t *)s->coremap; + for (i =3D 0; i < EXTIOI_IRQS; i +=3D 32) { + g_string_append_printf(buf, " COREMAP 0x%016"PRIx64" 0x%016"PRIx64 + " 0x%016"PRIx64" 0x%016"PRIx64"\n", + *val, *(val + 1), *(val + 2), *(val + = 3)); + val +=3D 4; + } + + core =3D s->cpu; + for (i =3D 0; i < s->num_cpu; i++, core++) { + if (!core->cpu) { + continue; + } + + irq =3D find_first_bit((unsigned long *)core->coreisr, EXTIOI_IRQS= ); + /* No pending IRQ */ + if (irq =3D=3D EXTIOI_IRQS) { + continue; + } + + val =3D (uint64_t *)core->coreisr; + g_string_append_printf(buf, " CPU[%d] ISR 0x%016"PRIx64" 0x%016"P= RIx64 + " 0x%016"PRIx64" 0x%016"PRIx64"\n", + i, *val, *(val + 1), *(val + 2), + *(val + 3)); + } +} + static void loongarch_extioi_class_init(ObjectClass *klass, const void *da= ta) { DeviceClass *dc =3D DEVICE_CLASS(klass); LoongArchExtIOIClass *lec =3D LOONGARCH_EXTIOI_CLASS(klass); LoongArchExtIOICommonClass *lecc =3D LOONGARCH_EXTIOI_COMMON_CLASS(kla= ss); + InterruptStatsProviderClass *ic =3D INTERRUPT_STATS_PROVIDER_CLASS(kla= ss); ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 device_class_set_parent_realize(dc, loongarch_extioi_realize, @@ -433,6 +486,7 @@ static void loongarch_extioi_class_init(ObjectClass *kl= ass, const void *data) NULL, &lec->parent_phases); lecc->pre_save =3D vmstate_extioi_pre_save; lecc->post_load =3D vmstate_extioi_post_load; + ic->print_info =3D loongarch_extioi_print_info; } =20 static const TypeInfo loongarch_extioi_types[] =3D { @@ -442,6 +496,10 @@ static const TypeInfo loongarch_extioi_types[] =3D { .instance_size =3D sizeof(LoongArchExtIOIState), .class_size =3D sizeof(LoongArchExtIOIClass), .class_init =3D loongarch_extioi_class_init, + .interfaces =3D (const InterfaceInfo[]) { + { TYPE_INTERRUPT_STATS_PROVIDER }, + { } + }, } }; =20 --=20 2.54.0