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Wed, 26 Aug 2026 21:16:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, pierrick.bouvier@oss.qualcomm.com, philmd@oss.qualcomm.com Subject: [PATCH v4 1/6] target/arm: Move -cpu max stuff out of cpu32.c Date: Wed, 26 Aug 2026 21:15:52 -0700 Message-ID: <20260827041557.775080-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260827041557.775080-1-richard.henderson@linaro.org> References: <20260827041557.775080-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787804272213158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/tcg/cpu-max-v8.c | 117 ++++++++++++++++++++++++++++++++++++ target/arm/tcg/cpu32.c | 111 ---------------------------------- target/arm/tcg/meson.build | 1 + 3 files changed, 118 insertions(+), 111 deletions(-) create mode 100644 target/arm/tcg/cpu-max-v8.c diff --git a/target/arm/tcg/cpu-max-v8.c b/target/arm/tcg/cpu-max-v8.c new file mode 100644 index 00000000000..5c0ba28edf8 --- /dev/null +++ b/target/arm/tcg/cpu-max-v8.c @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + + +/* Share AArch32 -cpu max features with AArch64. */ +void aa32_max_features(ARMCPU *cpu) +{ + uint32_t t; + ARMISARegisters *isar =3D &cpu->isar; + + /* Add additional features supported by QEMU */ + t =3D GET_IDREG(isar, ID_ISAR5); + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ + SET_IDREG(isar, ID_ISAR5, t); + + t =3D GET_IDREG(isar, ID_ISAR6); + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ + SET_IDREG(isar, ID_ISAR6, t); + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ + + t =3D GET_IDREG(isar, ID_MMFR4); + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ + t =3D FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */ + SET_IDREG(isar, ID_MMFR4, t); + + FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ + + t =3D GET_IDREG(isar, ID_PFR0); + t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ + SET_IDREG(isar, ID_PFR0, t); + + t =3D GET_IDREG(isar, ID_PFR2); + t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ + SET_IDREG(isar, ID_PFR2, t); + + t =3D GET_IDREG(isar, ID_DFR0); + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ + SET_IDREG(isar, ID_DFR0, t); + + /* Debug ID registers. */ + + /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ + t =3D 0x00008000; + t =3D FIELD_DP32(t, DBGDIDR, SE_IMP, 1); + t =3D FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); + t =3D FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ + t =3D FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); + t =3D FIELD_DP32(t, DBGDIDR, BRPS, 5); + t =3D FIELD_DP32(t, DBGDIDR, WRPS, 3); + cpu->isar.dbgdidr =3D t; + + t =3D 0; + t =3D FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); + t =3D FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); + t =3D FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); + t =3D FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); + t =3D FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); + t =3D FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); + t =3D FIELD_DP32(t, DBGDEVID, AUXREGS, 0); + t =3D FIELD_DP32(t, DBGDEVID, CIDMASK, 0); + cpu->isar.dbgdevid =3D t; + + /* Bits[31:4] are RES0. */ + t =3D 0; + t =3D FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); + cpu->isar.dbgdevid1 =3D t; + + FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ +} + +void aarch32_max_tcg_init(ARMCPU *cpu) +{ + aarch64_aa32_a57_init(cpu, false); + aa32_max_features(cpu); +#ifdef CONFIG_USER_ONLY + /* + * Break with true ARMv8 and add back old-style VFP short-vector + * support. Only do this for user-mode, where -cpu max is the default, + * so that older v6 and v7 programs are more likely to work without + * adjustment. + */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); +#endif +} diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index bc07e33877a..34436ad6ec4 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -758,114 +758,3 @@ static void arm_tcg_cpu_register_types(void) type_init(arm_tcg_cpu_register_types) =20 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ - -/* Share AArch32 -cpu max features with AArch64. */ -void aa32_max_features(ARMCPU *cpu) -{ - uint32_t t; - ARMISARegisters *isar =3D &cpu->isar; - - /* Add additional features supported by QEMU */ - t =3D GET_IDREG(isar, ID_ISAR5); - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ - SET_IDREG(isar, ID_ISAR5, t); - - t =3D GET_IDREG(isar, ID_ISAR6); - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ - SET_IDREG(isar, ID_ISAR6, t); - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ - - t =3D GET_IDREG(isar, ID_MMFR4); - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ - t =3D FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */ - SET_IDREG(isar, ID_MMFR4, t); - - FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ - - t =3D GET_IDREG(isar, ID_PFR0); - t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ - SET_IDREG(isar, ID_PFR0, t); - - t =3D GET_IDREG(isar, ID_PFR2); - t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ - SET_IDREG(isar, ID_PFR2, t); - - t =3D GET_IDREG(isar, ID_DFR0); - t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ - SET_IDREG(isar, ID_DFR0, t); - - /* Debug ID registers. */ - - /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ - t =3D 0x00008000; - t =3D FIELD_DP32(t, DBGDIDR, SE_IMP, 1); - t =3D FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); - t =3D FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); - t =3D FIELD_DP32(t, DBGDIDR, BRPS, 5); - t =3D FIELD_DP32(t, DBGDIDR, WRPS, 3); - cpu->isar.dbgdidr =3D t; - - t =3D 0; - t =3D FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); - t =3D FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); - t =3D FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); - t =3D FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); - t =3D FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); - t =3D FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); - t =3D FIELD_DP32(t, DBGDEVID, AUXREGS, 0); - t =3D FIELD_DP32(t, DBGDEVID, CIDMASK, 0); - cpu->isar.dbgdevid =3D t; - - /* Bits[31:4] are RES0. */ - t =3D 0; - t =3D FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); - cpu->isar.dbgdevid1 =3D t; - - FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ -} - -void aarch32_max_tcg_init(ARMCPU *cpu) -{ - aarch64_aa32_a57_init(cpu, false); - aa32_max_features(cpu); -#ifdef CONFIG_USER_ONLY - /* - * Break with true ARMv8 and add back old-style VFP short-vector - * support. Only do this for user-mode, where -cpu max is the default, - * so that older v6 and v7 programs are more likely to work without - * adjustment. - */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); -#endif -} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index cbfac0036e7..35e70b004d9 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -65,6 +65,7 @@ arm_common_user_system_ss.add( translate32_d, vfp_d, files( + 'cpu-max-v8.c', 'debug.c', 'gengvec.c', 'hflags.c', --=20 2.53.0 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787804238; cv=none; d=zohomail.com; s=zohoarc; b=Ln/7a4Czgv+BgeGCREuRkVOzU6V5gAounUCwO0tHtqIPdfYDQXZbpD6u31zF+ibCxeZLuXViLkTR0C9UEHdGDRcuTZ5An+PwL7VH1ZeR+Qls5N//aUnBufrGQkkYtP0iDsYK3UDi0BuL1L5u9YDpm3Sr8EXM6IkRn+1Su417otk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787804238; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Mqdk3c9HbzgZWSmcwYY8mMSQqF5s5IhpPUD59+J81rc=; b=GbVLPcEM70X3+A7sKUoz9C81ZR/OLduXRsVS5YGZzreZDKtvGoFelx0znUKnafviGdykcf+WKOtjYFzd+NSdVzMkf3Jthq08PldEV76uCoL/Dp1hi1v1o4FfWJj4lHOqSH2l15bn2BlkM8wiHodTfne/KxHtrDAd+dDOfpTXvR0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787804238215720.1164713073439; Wed, 26 Aug 2026 21:17:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzRXF-00077K-NK; Thu, 27 Aug 2026 00:16:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wzRXD-00075b-Fm for qemu-devel@nongnu.org; Thu, 27 Aug 2026 00:16:15 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wzRXB-0006RY-Cl for qemu-devel@nongnu.org; Thu, 27 Aug 2026 00:16:15 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-38e041ea211so259025a91.0 for ; Wed, 26 Aug 2026 21:16:12 -0700 (PDT) Received: from stoup (174-21-93-59.tukw.qwest.net. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/tcg/cpu32.c | 5 ----- target/arm/tcg/meson.build | 10 +++++----- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 34436ad6ec4..2d642ef8787 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -19,9 +19,6 @@ #include "cpregs.h" =20 =20 -/* CPU models. These are not needed for the AArch64 linux-user build. */ -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - static void arm926_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -756,5 +753,3 @@ static void arm_tcg_cpu_register_types(void) } =20 type_init(arm_tcg_cpu_register_types) - -#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 35e70b004d9..a3e9d55e853 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -30,10 +30,6 @@ translate32_d =3D [ arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64) arm_stubs_ss.add(files('stubs32.c')) =20 -arm_ss.add(files( - 'cpu32.c', -)) - arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'gengvec64.c', 'translate-a64.c', @@ -49,7 +45,10 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( )) =20 arm_common_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c= ')) -arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) +arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( + 'cpu-v7m.c', + 'cpu32.c', +)) =20 arm_common_ss.add(zlib) arm_common_ss.add(files( @@ -86,6 +85,7 @@ arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_= true: files( )) =20 arm_common_system_ss.add(files( + 'cpu32.c', 'cpregs-at.c', 'gicv5-cpuif.c', 'psci.c', --=20 2.53.0 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787804267; cv=none; d=zohomail.com; s=zohoarc; b=Q64rjSREBE9J0i4AtVjmeB4AtdcNZdheekpdornv8RuTXpFbt7AfkgYgshdsA8CR1AVYrwo7grVxl2P0PGwgepN9b49tR+NXsV6AheLj0sd483Ex0MdO4gXNoLlcV8LYn7h+60g10iO0W+dsuui9NyARos+AjiLeIB3w4zpPkz8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787804267; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=83aT+OUoVaSXUBZswXWe9rjbvcEl2UZbMtOlAN3Bbm0=; b=XRdxDsglzECDl2zUkrJFKCr8c056TyHtSEzNtibeUqWuldIGxe95SbLELUWS1Qkksc2z7rjURVJWxfNi1x2jIZgITqWqzQl05bVYF+XbVl7XoMiSSZY53Xk6jweVlAOhL09Crfn8c07wdV9gjQaTb9re9G0fVWWwx8AZHgnyZPo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787804267342868.3862087176997; Wed, 26 Aug 2026 21:17:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzRXK-00078g-K6; Thu, 27 Aug 2026 00:16:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wzRXE-00076M-OY for qemu-devel@nongnu.org; Thu, 27 Aug 2026 00:16:16 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wzRXC-0006Rs-BZ for qemu-devel@nongnu.org; Thu, 27 Aug 2026 00:16:16 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-2d6fe26ef1cso19724525ad.2 for ; Wed, 26 Aug 2026 21:16:13 -0700 (PDT) Received: from stoup (174-21-93-59.tukw.qwest.net. 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 +- target/arm/cpu-max.c | 2 +- target/arm/tcg/cpu-max-v8.c | 4 +++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index f6b4e173a54..fc7d5ad6f2c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1838,7 +1838,7 @@ uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool s= ecure, bool el_is_in_host(CPUARMState *env, int el); =20 void aa32_max_features(ARMCPU *cpu); -void aarch32_max_tcg_init(ARMCPU *cpu); +void aarch32_max_v8_tcg_initfn(Object *obj); int exception_target_el(CPUARMState *env); bool arm_singlestep_active(CPUARMState *env); bool arm_generate_debug_exceptions(CPUARMState *env); diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 4df52bcb08e..9ed45c8764f 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -108,7 +108,7 @@ static void cpu_max_initfn(Object *obj) =20 if (tcg_enabled()) { if (!aarch64_enabled) { - aarch32_max_tcg_init(cpu); + aarch32_max_v8_tcg_initfn(obj); } else { aarch64_max_tcg_initfn(obj); } diff --git a/target/arm/tcg/cpu-max-v8.c b/target/arm/tcg/cpu-max-v8.c index 5c0ba28edf8..5a9845d88f3 100644 --- a/target/arm/tcg/cpu-max-v8.c +++ b/target/arm/tcg/cpu-max-v8.c @@ -101,8 +101,10 @@ void aa32_max_features(ARMCPU *cpu) FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ } =20 -void aarch32_max_tcg_init(ARMCPU *cpu) +void aarch32_max_v8_tcg_initfn(Object *obj) { + ARMCPU *cpu =3D ARM_CPU(obj); + aarch64_aa32_a57_init(cpu, false); aa32_max_features(cpu); #ifdef CONFIG_USER_ONLY --=20 2.53.0 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787804284; cv=none; d=zohomail.com; s=zohoarc; b=YrtyiqWF6PdgB4MCFz+1eK1afRXoAG9U/dbywJfZoQFM+A3R94pqOa+EZth5dC6l/S5lMMmhoFJEnY6piCQuoPJAVZCEdvVndRgNq4oVwC0Vx7WqOzZw7xlijU4NOBZ4ePBKTkkPAsJGjzSrPXGkJvVTagVjR35TS/kuXB0TO18= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787804284; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NN+AYChl0fCz2uWH5Ftv6FK+uk3UyZJ6XO3OQUKzsbk=; b=nPc+infcGWKHfmofTkQSZ7H3sEienFq0yLT9DeqC5Y5+KVbTT4r/zMAsrsymjK7plVrmt9MnEjOO2zkoEVxl6j+hokC1y4cWOa5MMSMehW01b5LNYkVS7M8ghdAUyRAQ8d8mFzs1aNBKX34Hrpwya/xR1BQDvlUwsy+biI8IovY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787804284712336.29043648809545; Wed, 26 Aug 2026 21:18:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzRXM-0007AB-61; Thu, 27 Aug 2026 00:16:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wzRXF-00076t-CT for qemu-devel@nongnu.org; Thu, 27 Aug 2026 00:16:17 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wzRXD-0006S4-7t for qemu-devel@nongnu.org; Thu, 27 Aug 2026 00:16:17 -0400 Received: by mail-pj1-x102f.google.com with SMTP id 98e67ed59e1d1-38e58034d05so275009a91.2 for ; Wed, 26 Aug 2026 21:16:14 -0700 (PDT) Received: from stoup (174-21-93-59.tukw.qwest.net. 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So far, the cpu types both exactly match "max". Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/sbsa-ref.c | 2 ++ hw/arm/virt.c | 2 ++ target/arm/tcg/cpu-max-v8.c | 11 +++++++++++ target/arm/tcg/cpu64.c | 1 + 4 files changed, 16 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 484b90053e8..56d08f605c8 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -913,6 +913,8 @@ static void sbsa_ref_class_init(ObjectClass *oc, const = void *data) ARM_CPU_TYPE_NAME("neoverse-v1"), ARM_CPU_TYPE_NAME("neoverse-n2"), ARM_CPU_TYPE_NAME("max"), + ARM_CPU_TYPE_NAME("max-v8"), + ARM_CPU_TYPE_NAME("max-v9"), NULL, }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index e7a56e37f73..d738b95c726 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -4132,6 +4132,7 @@ static GPtrArray *virt_get_valid_cpu_types(const Mach= ineState *ms) if (tcg_enabled()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max-v8"))); } if (tcg_enabled() && target_aarch64()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35"))); @@ -4143,6 +4144,7 @@ static GPtrArray *virt_get_valid_cpu_types(const Mach= ineState *ms) g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max-v9"))); } if (target_aarch64()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); diff --git a/target/arm/tcg/cpu-max-v8.c b/target/arm/tcg/cpu-max-v8.c index 5a9845d88f3..55f8c341423 100644 --- a/target/arm/tcg/cpu-max-v8.c +++ b/target/arm/tcg/cpu-max-v8.c @@ -2,6 +2,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "qemu/target-info.h" #include "internals.h" =20 =20 @@ -117,3 +118,13 @@ void aarch32_max_v8_tcg_initfn(Object *obj) cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); #endif } + +static void cpu_max_v8_register_type(void) +{ + static const ARMCPUInfo max_v8[2] =3D { + { .name =3D "max-v8", .initfn =3D aarch32_max_v8_tcg_initfn }, + { .name =3D "max-v8", .initfn =3D aarch64_max_tcg_initfn } + }; + arm_cpu_register(&max_v8[target_aarch64()]); +} +type_init(cpu_max_v8_register_type) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index b38c61ba623..d44a8221c8b 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1488,6 +1488,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, { .name =3D "neoverse-n2", .initfn =3D aarch64_neoverse_n2_init= fn }, + { .name =3D "max-v9", .initfn =3D aarch64_max_tcg_initfn }, }; =20 static void aarch64_cpu_register_types(void) --=20 2.53.0 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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These tests must use Armv8. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tests/qtest/arm-cpu-features.c | 4 ++-- tests/functional/aarch64/test_virt_aarch64_off.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index cb4d01fd46a..7348fb8d28b 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -493,8 +493,8 @@ static void test_query_cpu_model_expansion(const void *= data) sve_tests_default(qts, "max"); pauth_tests_default(qts, "max"); =20 - /* TCG allows us to turn off AArch64 on the 'max' CPU type */ - assert_set_feature(qts, "max", "aarch64", false); + /* TCG allows us to turn off AArch64 on the 'max-v8' CPU type */ + assert_set_feature(qts, "max-v8", "aarch64", false); } =20 qtest_quit(qts); diff --git a/tests/functional/aarch64/test_virt_aarch64_off.py b/tests/func= tional/aarch64/test_virt_aarch64_off.py index 13d8b73b0d7..73c9a4109c0 100755 --- a/tests/functional/aarch64/test_virt_aarch64_off.py +++ b/tests/functional/aarch64/test_virt_aarch64_off.py @@ -18,9 +18,9 @@ class ArmVirtMachine(LinuxKernelTest): def test_arm_virt(self): self.set_machine('virt') # KVM aarch64=3Doff requires a host CPU that supports it, so - # restrict the test to TCG only + # restrict the test to TCG ARMv8. self.require_accelerator('tcg') - self.vm.add_args('-cpu', 'max,aarch64=3Doff') + self.vm.add_args('-cpu', 'max-v8,aarch64=3Doff') =20 kernel_path =3D self.ASSET_KERNEL.fetch() =20 --=20 2.53.0 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787804238; cv=none; d=zohomail.com; s=zohoarc; b=V+i4zexbuqpVA1CuhhBQP/sSHxkj4zAgBo4F+ZMMzQwb0i9aNvsNFZrWttUK3pVE6DghoS52u8r505m1IQvBs89Jsk3V6ywoexRVsiUVOhB9Im+XYvFE49EHTrC4T2Mea6VexZg/bb3lmYUDZHJB+IhGOv9OY30UrFxvpI1NliI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787804238; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8fVuO7QFobOaYWyxa9ruyag/nbjeuTU+JhVLHb50t1A=; b=aSuhZElE+vlKVfCaS+rT+DE59ZRM2CGOXkPSIOKpzLWAlP4BDDxlzrB6d+6ZS0rZmplPiKFXjX16rpYhgX0Yjl0y80pITTEUI9EqVWS+Z/n/FtIgfkQpUR0/mEYr72Yn3v0YrQNnFhckv8GGJMe/ml58UKtOXuzub2OpJmBTyLo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787804238727692.6814826246496; Wed, 26 Aug 2026 21:17:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzRXJ-00078P-L5; Thu, 27 Aug 2026 00:16:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wzRXH-000785-K8 for qemu-devel@nongnu.org; Thu, 27 Aug 2026 00:16:19 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wzRXF-0006TN-0H for qemu-devel@nongnu.org; Thu, 27 Aug 2026 00:16:19 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-2d58efc7356so20400635ad.1 for ; Wed, 26 Aug 2026 21:16:16 -0700 (PDT) Received: from stoup (174-21-93-59.tukw.qwest.net. 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Do not include the prohibited v8 features in "max-v9". In aarch64 tcg mode, define "max" as "max-v9". Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 3 +- target/arm/cpu-max.c | 2 +- target/arm/tcg/cpu-max-v8.c | 2 +- target/arm/tcg/cpu64.c | 160 ++++++++++++++++++++++------------ target/arm/tcg/stubs32.c | 7 +- docs/system/arm/emulation.rst | 13 ++- 6 files changed, 128 insertions(+), 59 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fc7d5ad6f2c..1775835ad50 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1809,7 +1809,8 @@ void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **er= rp); void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); -void aarch64_max_tcg_initfn(Object *obj); +void aarch64_max_v8_tcg_initfn(Object *obj); +void aarch64_max_v9_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 9ed45c8764f..739500a04fc 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -110,7 +110,7 @@ static void cpu_max_initfn(Object *obj) if (!aarch64_enabled) { aarch32_max_v8_tcg_initfn(obj); } else { - aarch64_max_tcg_initfn(obj); + aarch64_max_v9_tcg_initfn(obj); } return; } diff --git a/target/arm/tcg/cpu-max-v8.c b/target/arm/tcg/cpu-max-v8.c index 55f8c341423..65f851f2006 100644 --- a/target/arm/tcg/cpu-max-v8.c +++ b/target/arm/tcg/cpu-max-v8.c @@ -123,7 +123,7 @@ static void cpu_max_v8_register_type(void) { static const ARMCPUInfo max_v8[2] =3D { { .name =3D "max-v8", .initfn =3D aarch32_max_v8_tcg_initfn }, - { .name =3D "max-v8", .initfn =3D aarch64_max_tcg_initfn } + { .name =3D "max-v8", .initfn =3D aarch64_max_v8_tcg_initfn }, }; arm_cpu_register(&max_v8[target_aarch64()]); } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index d44a8221c8b..251c4b3cf60 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1166,11 +1166,10 @@ static void aarch64_neoverse_n2_initfn(Object *obj) } =20 /* - * -cpu max: a CPU with as many features enabled as our emulation supports. - * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; - * this only needs to handle 64 bits. + * -cpu max-v8: an ARMv8 CPU with as many features enabled as + * our emulation supports. */ -void aarch64_max_tcg_initfn(Object *obj) +void aarch64_max_v8_tcg_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); ARMISARegisters *isar =3D &cpu->isar; @@ -1244,7 +1243,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* v8.0: FEAT_SHA1 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* v8.1: FEAT_SHA512 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* v8.0: FEAT_CRC32 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 3); /* v9.3: FEAT_LSE128 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* v8.0: FEAT_LSE */ t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* v8.0: FEAT_RDM */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* v8.1: FEAT_SHA3 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* v8.1: FEAT_SM3 */ @@ -1277,16 +1276,10 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* v8.7: FEAT_MOPS */ t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* v8.7: FEAT_HBC */ t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* v8.6: FEAT_WFxT */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* v9.3: FEAT_CMPBR */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* v9.2: FEAT_LUT */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 1); /* v8.7: FEAT_CSSC */ t =3D FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* v8.8: FEAT_ATS1A */ SET_IDREG(isar, ID_AA64ISAR2, t); =20 - t =3D GET_IDREG(isar, ID_AA64ISAR3); - t =3D FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* v9.2: FEAT_FAMINMAX= */ - t =3D FIELD_DP64(t, ID_AA64ISAR3, FPRCVT, 1); /* v9.5: FEAT_FPRCVT */ - SET_IDREG(isar, ID_AA64ISAR3, t); - t =3D GET_IDREG(isar, ID_AA64PFR0); t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* v8.2: FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* v8.2: FEAT_FP16 */ @@ -1308,17 +1301,14 @@ void aarch64_max_tcg_initfn(Object *obj) */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* v8.5: FEAT_MTE3 */ t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* v8.3: FEAT_DoubleFa= ult */ - t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* v9.2: FEAT_SME2 */ t =3D FIELD_DP64(t, ID_AA64PFR1, RNDR_TRAP, 1); /* v8.4: FEAT_RNG_TRAP= */ t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* v8.0: FEAT_CSV2_3 */ t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* v8.7: FEAT_NMI */ - t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* v9.3: FEAT_GCS */ /* v8.7: FEAT_MTE_NO_ADDRESS_TAGS + FEAT_MTE_CANONICAL_TAGS */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTEX, 1); SET_IDREG(isar, ID_AA64PFR1, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR2); - t =3D FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* v9.2: FEAT_FPMR */ t =3D FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 1); /* v8.7: FEAT_MTE_TAGG= ED_FAR */ t =3D FIELD_DP64(t, ID_AA64PFR2, MTESTOREONLY, 1); /* v8.7: FEAT_MTE_S= TORE_ONLY */ t =3D FIELD_DP64(t, ID_AA64PFR2, MTEPERM, 1); /* v8.7: FEAT_MTE_PERM= */ @@ -1368,25 +1358,14 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D GET_IDREG(isar, ID_AA64MMFR3); t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* v8.0: FEAT_TCR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* v8.0: FEAT_SCTLR2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* v9.2: FEAT_MEC */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* v8.2: FEAT_FPACC_= SPEC */ t =3D FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* v8.8: FEAT_S1PIE */ t =3D FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* v8.8: FEAT_S2PIE */ t =3D FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* v8.8: FEAT_AIE */ SET_IDREG(isar, ID_AA64MMFR3, t); =20 - t =3D GET_IDREG(isar, ID_AA64MMFR4); - t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* v9.4: FEAT_ASID2 */ - SET_IDREG(isar, ID_AA64MMFR4, t); - t =3D GET_IDREG(isar, ID_AA64ZFR0); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* v9.2: FEAT_SVE2p1 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMUL= L128 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitP= erm */ t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 2); /* v8.2: FEAT_EBF16 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* v9.2: FEAT_SVE_B16B= 16 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3= */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* v9.0: FEAT_SVE_SM4 = */ t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* v8.1: FEAT_I8MM */ t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* v8.2: FEAT_F32MM */ t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* v8.2: FEAT_F64MM */ @@ -1398,6 +1377,106 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* v8.5: FEAT_HPMN0 */ SET_IDREG(isar, ID_AA64DFR0, t); =20 + /* Replicate the same data to the 32-bit id registers. */ + aa32_max_features(cpu); + +#ifdef CONFIG_USER_ONLY + /* + * For usermode -cpu max we can use a larger and more efficient DCZ + * blocksize since we don't have to follow what the hardware does. + */ + cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ + set_dczid_bs(cpu, 7); /* 512 bytes */ +#endif + + /* v8.2: FEAT_SVE */ + cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); + aarch64_add_sve_properties(OBJECT(cpu)); + object_property_add(OBJECT(cpu), "sve-max-vq", "uint32", + cpu_max_get_sve_max_vq, cpu_max_set_sve_max_vq, + NULL, NULL); + + /* v8.2: FEAT_PAuth2 */ + aarch64_add_pauth_properties(OBJECT(cpu)); + + /* v8.4: FEAT_MTE2 */ + cpu->gm_blocksize =3D 6; /* 256 bytes */ + + /* v8.6: FEAT_LPA2 */ + qdev_property_add_static(DEVICE(cpu), &arm_cpu_lpa2_property); +} + +/* + * -cpu max-v9: an ARMv9 CPU with as many features enabled as + * our emulation supports. + */ +void aarch64_max_v9_tcg_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; + uint64_t t; + + /* Armv9.0 is based on a minimum of Armv8.5. */ + aarch64_max_v8_tcg_initfn(obj); + + /* + * Armv9.0 does not support AArch32 except at EL0, + * therefore indicate EL1 through EL3 are AArch64-only. + */ + t =3D GET_IDREG(isar, ID_AA64PFR0); + t =3D FIELD_DP64(t, ID_AA64PFR0, EL1, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, EL2, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, EL3, 1); + SET_IDREG(isar, ID_AA64PFR0, t); + + /* v9.0 prohibits FEAT_DoubleLock. */ + FIELD_DP64_IDREG(isar, ID_AA64DFR0, DOUBLELOCK, -1); + FIELD_DP64_IDREG(isar, ID_AA64PFR0, RAS, 1); + isar->dbgdevid =3D FIELD_DP32(isar->dbgdevid, DBGDEVID, DOUBLELOCK, 0); + + /* + * Below, note the revision from which the feature is OPTIONAL. + */ + t =3D GET_IDREG(isar, ID_AA64ISAR0); + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 3); /* v9.3: FEAT_LSE128 */ + SET_IDREG(isar, ID_AA64ISAR0, t); + + t =3D GET_IDREG(isar, ID_AA64ISAR2); + t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* v9.3: FEAT_CMPBR */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* v9.2: FEAT_LUT */ + SET_IDREG(isar, ID_AA64ISAR2, t); + + t =3D GET_IDREG(isar, ID_AA64ISAR3); + t =3D FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* v9.2: FEAT_FAMINMAX= */ + t =3D FIELD_DP64(t, ID_AA64ISAR3, FPRCVT, 1); /* v9.5: FEAT_FPRCVT */ + SET_IDREG(isar, ID_AA64ISAR3, t); + + t =3D GET_IDREG(isar, ID_AA64PFR1); + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* v9.2: FEAT_SME2 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* v9.3: FEAT_GCS */ + SET_IDREG(isar, ID_AA64PFR1, t); + + t =3D GET_IDREG(isar, ID_AA64PFR2); + t =3D FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* v9.2: FEAT_FPMR */ + SET_IDREG(isar, ID_AA64PFR2, t); + + t =3D GET_IDREG(isar, ID_AA64MMFR3); + t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* v9.2: FEAT_MEC */ + SET_IDREG(isar, ID_AA64MMFR3, t); + + t =3D GET_IDREG(isar, ID_AA64MMFR4); + t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* v9.4: FEAT_ASID2 */ + SET_IDREG(isar, ID_AA64MMFR4, t); + + t =3D GET_IDREG(isar, ID_AA64ZFR0); + t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* v9.2: FEAT_SVE2p1 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMUL= L128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitP= erm */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* v9.2: FEAT_SVE_B16B= 16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3= */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* v9.0: FEAT_SVE_SM4 = */ + SET_IDREG(isar, ID_AA64ZFR0, t); + t =3D GET_IDREG(isar, ID_AA64SMFR0); t =3D FIELD_DP64(t, ID_AA64SMFR0, SMOP4, 1); /* v9.4: FEAT_SME_MOP4= */ t =3D FIELD_DP64(t, ID_AA64SMFR0, STMOP, 1); /* v9.4: FEAT_SME_TMOP= */ @@ -1434,43 +1513,16 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64FPFR0, F8CVT, 1); /* v9.2: FEAT_FP8 */ SET_IDREG(isar, ID_AA64FPFR0, t); =20 - /* Replicate the same data to the 32-bit id registers. */ - aa32_max_features(cpu); - -#ifdef CONFIG_USER_ONLY - /* - * For usermode -cpu max we can use a larger and more efficient DCZ - * blocksize since we don't have to follow what the hardware does. - */ - cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ - set_dczid_bs(cpu, 7); /* 512 bytes */ -#endif - - /* v8.4: FEAT_MTE2 */ - cpu->gm_blocksize =3D 6; /* 256 bytes */ - - /* v8.2: FEAT_SVE */ - cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); - aarch64_add_sve_properties(obj); - object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, - cpu_max_set_sve_max_vq, NULL, NULL); - /* v9.2: FEAT_SME */ cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; aarch64_add_sme_properties(obj); =20 - /* v8.2: FEAT_PAuth2 */ - aarch64_add_pauth_properties(obj); - /* v9.1: FEAT_RME */ object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rm= e); =20 /* v9.4: FEAT_RME_GPC2 */ object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz, cpu_max_set_l0gptsz, NULL, NULL); - - /* v8.6: FEAT_LPA2 */ - qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); } =20 static const ARMCPUInfo aarch64_cpus[] =3D { @@ -1488,7 +1540,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, { .name =3D "neoverse-n2", .initfn =3D aarch64_neoverse_n2_init= fn }, - { .name =3D "max-v9", .initfn =3D aarch64_max_tcg_initfn }, + { .name =3D "max-v9", .initfn =3D aarch64_max_v9_tcg_initf= n }, }; =20 static void aarch64_cpu_register_types(void) diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c index 78f819ef6ff..af0911a24c3 100644 --- a/target/arm/tcg/stubs32.c +++ b/target/arm/tcg/stubs32.c @@ -28,7 +28,12 @@ void aarch64_host_initfn(Object *obj) g_assert_not_reached(); } =20 -void aarch64_max_tcg_initfn(Object *obj) +void aarch64_max_v8_tcg_initfn(Object *obj) +{ + g_assert_not_reached(); +} + +void aarch64_max_v9_tcg_initfn(Object *obj) { g_assert_not_reached(); } diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index cc42db9e0b7..ff02435975b 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -230,7 +230,18 @@ to the `Arm Architecture Reference Manual for A-profil= e architecture When a specific named CPU is being emulated, only those features which are present in hardware for that CPU are emulated. (If a feature is not in the list above then it is not supported, even if the real -hardware should have it.) The ``max`` CPU enables all features. +hardware should have it.) + +The ``max-v8`` CPU enables all of the listed Armv8-A architecture +extensions but none of the Armv9-A architecture extensions. + +The ``max-v9`` CPU enables all of the listed extensions except for +those that are prohibited by the Armv9-A architecture: FEAT_AA32EL1, +FEAT_AA32EL2, FEAT_AA32EL3, and FEAT_DoubleLock. + +The ``max`` CPU is an alias for ``max-v9`` under AArch64 TCG emulation, +an alias for ``max-v8`` under AArch32 TCG emulation, or an alias +for ``host`` under hardware virtualization. =20 R-profile CPU architecture support =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.53.0