From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787795340646127.87032279817481; Wed, 26 Aug 2026 18:49:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzPEF-00026V-Mb; Wed, 26 Aug 2026 21:48:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wzPEA-000259-Fx for qemu-devel@nongnu.org; Wed, 26 Aug 2026 21:48:26 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzPE7-0007pN-LE for qemu-devel@nongnu.org; Wed, 26 Aug 2026 21:48:26 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Cx_9Jhl49qfoYFAA--.15525S3; Thu, 27 Aug 2026 09:48:17 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJCx+c1dl49q1KwTAA--.16714S3; Thu, 27 Aug 2026 09:48:17 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, Bibo Mao Subject: [PULL 1/3] hw/loongarch/boot: Check memory boundary in init_boot_rom() Date: Thu, 27 Aug 2026 09:28:09 +0800 Message-Id: <20260827012811.1008381-2-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20260827012811.1008381-1-gaosong@loongson.cn> References: <20260827012811.1008381-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCx+c1dl49q1KwTAA--.16714S3 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1787795343102158500 Content-Type: text/plain; charset="utf-8" From: Bibo Mao When booting the Linux kernel without UEFI BIOS, QEMU needs to set the boot param for kernel. For the LoongArch Linux kernel, it is put in structure loongarch_boot_info, and the total size is 1MB. Here add memory boundary checking with preparing kernel boot param in loongarch_boot_info. Signed-off-by: Bibo Mao Reviewed-by: Song Gao Message-ID: <20260807070029.1171348-2-maobibo@loongson.cn> Signed-off-by: Song Gao --- hw/loongarch/boot.c | 68 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 55 insertions(+), 13 deletions(-) diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c index ef8eae237c..fe91ab16bd 100644 --- a/hw/loongarch/boot.c +++ b/hw/loongarch/boot.c @@ -173,12 +173,19 @@ static void init_efi_fdt_table(struct efi_system_tabl= e *systab) systab->nr_tables =3D 3; } =20 -static void init_systab(MachineState *ms, +static void init_systab(MachineState *ms, size_t size, struct loongarch_boot_info *info, void *p, void *s= tart) { void *bp_tables_start; struct efi_system_table *systab =3D p; LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(ms); + size_t len; + + len =3D ROUND_UP(sizeof(struct efi_system_table), 64 * KiB); + if (len > size) { + error_report("could not init efi_system_table"); + exit(1); + } =20 info->a2 =3D p - start; =20 @@ -190,29 +197,56 @@ static void init_systab(MachineState *ms, systab->boottime =3D 0; systab->nr_tables =3D 0; =20 - p +=3D ROUND_UP(sizeof(struct efi_system_table), 64 * KiB); + p +=3D len; + size -=3D len; =20 systab->tables =3D p; bp_tables_start =3D p; =20 + len =3D ROUND_UP(sizeof(struct efi_boot_memmap) + + sizeof(efi_memory_desc_t) * lvms->memmap_entries, 64 * = KiB); + if (len > size) { + error_report("could not init efi_boot_memmap"); + exit(1); + } + init_efi_boot_memmap(ms, systab, p, start); - p +=3D ROUND_UP(sizeof(struct efi_boot_memmap) + - sizeof(efi_memory_desc_t) * lvms->memmap_entries, 64 * K= iB); + p +=3D len; + size -=3D len; + + len =3D ROUND_UP(sizeof(struct efi_initrd), 64 * KiB); + if (len > size) { + error_report("could not init efi_initrd"); + exit(1); + } + init_efi_initrd_table(info, systab, p, start); - p +=3D ROUND_UP(sizeof(struct efi_initrd), 64 * KiB); + p +=3D len; + size -=3D len; init_efi_fdt_table(systab); =20 systab->tables =3D (struct efi_configuration_table *)(bp_tables_start = - start); } =20 -static void init_cmdline(struct loongarch_boot_info *info, void *p, void *= start) +static size_t init_cmdline(struct loongarch_boot_info *info, void *p, + void *start, size_t size) { hwaddr cmdline_addr =3D p - start; + size_t len; =20 info->a0 =3D 1; info->a1 =3D cmdline_addr; =20 - g_strlcpy(p, info->kernel_cmdline, COMMAND_LINE_SIZE); + len =3D g_strlcpy(p, info->kernel_cmdline, size); + + /* include terminating null byte */ + if (len < size) { + len +=3D 1; + } else { + len =3D size; + } + + return len; } =20 static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) @@ -385,15 +419,21 @@ static void loongarch_firmware_boot(LoongArchVirtMach= ineState *lvms, fw_cfg_add_kernel_info(info, lvms->fw_cfg); } =20 -static void init_boot_rom(MachineState *ms, +static void init_boot_rom(MachineState *ms, size_t size, struct loongarch_boot_info *info, void *p) { void *start =3D p; + size_t len; =20 - init_cmdline(info, p, start); - p +=3D COMMAND_LINE_SIZE; + len =3D init_cmdline(info, p, start, size); + len =3D ROUND_UP(len, 64 * KiB); + if (len > size) { + error_report("could not init systab"); + exit(1); + } =20 - init_systab(ms, info, p, start); + p +=3D len; + init_systab(ms, size - len, info, p, start); } =20 static void loongarch_direct_kernel_boot(MachineState *ms, @@ -403,6 +443,7 @@ static void loongarch_direct_kernel_boot(MachineState *= ms, void *p, *bp; int64_t kernel_addr =3D VIRT_FLASH0_BASE; uint64_t *data; + size_t size; =20 if (info->kernel_filename) { kernel_addr =3D load_kernel_info(info, phys_addr_mask); @@ -415,8 +456,9 @@ static void loongarch_direct_kernel_boot(MachineState *= ms, /* Load cmdline and system tables at [0 - 1 MiB] */ p =3D g_malloc0(1 * MiB); bp =3D p; - init_boot_rom(ms, info, p); - rom_add_blob_fixed_as("boot_info", bp, 1 * MiB, 0, &address_space_memo= ry); + size =3D 1 * MiB; + init_boot_rom(ms, size, info, p); + rom_add_blob_fixed_as("boot_info", bp, size, 0, &address_space_memory); =20 /* Load slave boot code at pflash0 . */ void *boot_code =3D g_malloc0(VIRT_FLASH0_SIZE); --=20 2.55.0 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787795339440858.7950024005677; Wed, 26 Aug 2026 18:48:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzPED-00025u-B5; Wed, 26 Aug 2026 21:48:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wzPEB-00025H-8f for qemu-devel@nongnu.org; Wed, 26 Aug 2026 21:48:27 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzPE8-0007pO-5c for qemu-devel@nongnu.org; Wed, 26 Aug 2026 21:48:27 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8DxTtNil49qgIYFAA--.15336S3; Thu, 27 Aug 2026 09:48:18 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJCx+c1dl49q1KwTAA--.16714S4; Thu, 27 Aug 2026 09:48:17 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, Bibo Mao Subject: [PULL 2/3] hw/loongarch/virt: Add bootargs and initrd to device-tree Date: Thu, 27 Aug 2026 09:28:10 +0800 Message-Id: <20260827012811.1008381-3-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20260827012811.1008381-1-gaosong@loongson.cn> References: <20260827012811.1008381-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCx+c1dl49q1KwTAA--.16714S4 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1787795343177158500 Content-Type: text/plain; charset="utf-8" From: Bibo Mao Add bootarg and initrd information in fdt tree. Signed-off-by: Bibo Mao Reviewed-by: Song Gao Message-ID: <20260807070029.1171348-3-maobibo@loongson.cn> Signed-off-by: Song Gao --- hw/loongarch/virt-fdt-build.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/hw/loongarch/virt-fdt-build.c b/hw/loongarch/virt-fdt-build.c index 6c06b36fca..c6f5d022c5 100644 --- a/hw/loongarch/virt-fdt-build.c +++ b/hw/loongarch/virt-fdt-build.c @@ -25,6 +25,7 @@ static void create_fdt(LoongArchVirtMachineState *lvms) { MachineState *ms =3D MACHINE(lvms); uint8_t rng_seed[32]; + int ret; =20 ms->fdt =3D create_device_tree(&lvms->fdt_size); if (!ms->fdt) { @@ -39,6 +40,32 @@ static void create_fdt(LoongArchVirtMachineState *lvms) qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); qemu_fdt_add_subnode(ms->fdt, "/chosen"); =20 + if (ms->kernel_cmdline && *ms->kernel_cmdline) { + ret =3D qemu_fdt_setprop_string(ms->fdt, "/chosen", "bootargs", + ms->kernel_cmdline); + if (ret < 0) { + error_report("set /chosen/bootargs failed"); + exit(1); + } + } + + if (lvms->bootinfo.initrd_addr) { + ret =3D qemu_fdt_setprop_cell(ms->fdt, "/chosen", "linux,initrd-st= art", + lvms->bootinfo.initrd_addr); + if (ret < 0) { + error_report("set /chosen/linux,initrd-start failed"); + exit(1); + } + + ret =3D qemu_fdt_setprop_cell(ms->fdt, "/chosen", "linux,initrd-en= d", + lvms->bootinfo.initrd_addr + + lvms->bootinfo.initrd_size); + if (ret < 0) { + error_report("set /chosen/linux,initrd-end failed"); + exit(1); + } + } + /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_= seed)); --=20 2.55.0 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787795338992503.95567135913825; Wed, 26 Aug 2026 18:48:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzPEC-00025W-JY; Wed, 26 Aug 2026 21:48:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wzPEA-00024z-2y for qemu-devel@nongnu.org; Wed, 26 Aug 2026 21:48:26 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzPE7-0007pR-KU for qemu-devel@nongnu.org; Wed, 26 Aug 2026 21:48:25 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Cx+9Fil49qg4YFAA--.15590S3; Thu, 27 Aug 2026 09:48:18 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJCx+c1dl49q1KwTAA--.16714S5; Thu, 27 Aug 2026 09:48:18 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, Bibo Mao , "Andrew S . Rightenburg" , Song Gao <17746591750@163.com> Subject: [PULL 3/3] target/loongarch: Fix SWI interrupt delivery via CSR_ESTAT Date: Thu, 27 Aug 2026 09:28:11 +0800 Message-Id: <20260827012811.1008381-4-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20260827012811.1008381-1-gaosong@loongson.cn> References: <20260827012811.1008381-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCx+c1dl49q1KwTAA--.16714S5 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1787795343092158500 Content-Type: text/plain; charset="utf-8" From: Bibo Mao In TCG mode, helper_csrwr_estat() updates CSR.ESTAT.IS[1:0] (SWI0/SWI1) when the guest writes CSR_ESTAT, but it did not update the CPU interrupt request state. As a result, software interrupts could be observed as pending in CSR.ESTAT while no interrupt exception was taken. Update CPU_INTERRUPT_HARD after modifying CSR_ESTAT, matching the behavior = of loongarch_cpu_set_irq(). The helper runs without the Big QEMU Lock (BQL), so take the BQL while calling cpu_interrupt(). Fixes: 5b1dedfe848b ("target/loongarch: Add LoongArch CSR instruction") Reported-by: Andrew S. Rightenburg Signed-off-by: Andrew S. Rightenburg Signed-off-by: Bibo Mao Reviewed-by: Song Gao <17746591750@163.com> Message-ID: <20260806120315.1059413-1-maobibo@loongson.cn> Signed-off-by: Song Gao --- target/loongarch/cpu.c | 26 ++++++++++++++++++++------ target/loongarch/internals.h | 1 + target/loongarch/tcg/csr_helper.c | 10 ++++++++++ 3 files changed, 31 insertions(+), 6 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index bd819247c7..84a130956d 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -58,12 +58,29 @@ static vaddr loongarch_cpu_get_pc(CPUState *cs) #ifndef CONFIG_USER_ONLY #include "hw/loongarch/virt.h" =20 +void loongarch_cpu_update_irq(LoongArchCPU *cpu, uint64_t old) +{ + CPULoongArchState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + CPUSysState *sys =3D env_sys(env); + + if (FIELD_EX64(sys->CSR_ESTAT, CSR_ESTAT, IS)) { + if (!FIELD_EX64(old, CSR_ESTAT, IS)) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } + } else { + if (FIELD_EX64(old, CSR_ESTAT, IS)) { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } + } +} + void loongarch_cpu_set_irq(void *opaque, int irq, int level) { LoongArchCPU *cpu =3D opaque; CPULoongArchState *env =3D &cpu->env; - CPUState *cs =3D CPU(cpu); CPUSysState *sys =3D env_sys(env); + uint64_t old; =20 if (irq < 0 || irq >=3D N_IRQS) { return; @@ -72,12 +89,9 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int le= vel) if (kvm_enabled()) { kvm_loongarch_set_interrupt(cpu, irq, level); } else if (tcg_enabled()) { + old =3D sys->CSR_ESTAT; sys->CSR_ESTAT =3D deposit64(sys->CSR_ESTAT, irq, 1, level !=3D 0); - if (FIELD_EX64(sys->CSR_ESTAT, CSR_ESTAT, IS)) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } + loongarch_cpu_update_irq(cpu, old); } } =20 diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index e01dbed40f..0b670f9466 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -31,6 +31,7 @@ void restore_fp_status(CPULoongArchState *env); #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_loongarch_cpu; =20 +void loongarch_cpu_update_irq(LoongArchCPU *cpu, uint64_t old); void loongarch_cpu_set_irq(void *opaque, int irq, int level); =20 void loongarch_constant_timer_cb(void *opaque); diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h= elper.c index 7dc33bc180..155482efc6 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -106,6 +106,16 @@ target_ulong helper_csrwr_estat(CPULoongArchState *env= , target_ulong val) =20 /* Only IS[1:0] can be written */ sys->CSR_ESTAT =3D deposit64(sys->CSR_ESTAT, 0, 2, val); + /* + * Software interrupts (SWI0/SWI1) are latched in CSR.ESTAT.IS[1:0]. + * Make sure the CPU interrupt request state tracks the pending bits, + * matching the behavior of loongarch_cpu_set_irq(). + */ + if (sys->CSR_ESTAT !=3D old_v) { + bql_lock(); + loongarch_cpu_update_irq(env_archcpu(env), old_v); + bql_unlock(); + } =20 return old_v; } --=20 2.55.0