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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c107::9; envelope-from=tdave@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1787791356180158500 Content-Type: text/plain; charset="utf-8" Introduce two PCI properties used to configure fixed BAR placement. The fixed-bar property is added to pcie-root-port. It identifies a root port whose subordinate PCI hierarchy participates in fixed BAR placement. The pci-bars property is added to PCI devices and accepts explicit BAR addresses in the form: pci-bars=3DbarN@[,barM@]... The parser validates the property syntax and stores the user-provided addresses on the PCIDevice for later use. These properties are generic and can be used with both emulated and VFIO-backed PCI devices. Signed-off-by: Tushar Dave --- hw/pci-bridge/pcie_root_port.c | 1 + hw/pci/pci.c | 129 +++++++++++++++++++++++++++++++++ include/hw/pci/pci_device.h | 10 +++ include/hw/pci/pcie_port.h | 1 + 4 files changed, 141 insertions(+) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 7c3e78010b..cea39b92ca 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -151,6 +151,7 @@ static void rp_exit(PCIDevice *d) static const Property rp_props[] =3D { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), + DEFINE_PROP_BOOL("fixed-bar", PCIESlot, fixed_bar, false), }; =20 static void rp_instance_post_init(Object *obj) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index d3191609e2..1a326f6f91 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -50,6 +50,7 @@ #include "hw/core/boards.h" #include "hw/nvram/fw_cfg.h" #include "qapi/error.h" +#include "qapi/util.h" #include "qemu/cutils.h" #include "pci-internal.h" =20 @@ -88,6 +89,7 @@ static const Property pci_props[] =3D { DEFINE_PROP_STRING("romfile", PCIDevice, romfile), DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, UINT32_MAX), DEFINE_PROP_INT32("rombar", PCIDevice, rom_bar, -1), + DEFINE_PROP_STRING("pci-bars", PCIDevice, pci_bars), DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, @@ -225,6 +227,125 @@ static void pci_bus_unrealize(BusState *qbus) vmstate_unregister(NULL, &vmstate_pcibus, bus); } =20 +#define PCI_BARS_SYNTAX "expected barN@[,barM@]*; " + +static int pci_parse_bar_token(const char *tok, Error **errp) +{ + int v =3D qapi_enum_parse(&OffAutoPCIBAR_lookup, tok, -1, errp); + + if (v < 0) { + return -1; + } + if (v < OFF_AUTO_PCIBAR_BAR0) { + error_setg(errp, "pci-bars: " PCI_BARS_SYNTAX + "invalid BAR '%s', expected bar0..bar5", tok); + return -1; + } + return v - OFF_AUTO_PCIBAR_BAR0; +} + +/* + * Parse pci-bars=3DbarN@[,barM@]* + * Stores parsed addresses into pci_dev->fixed_bar_addrs[]. + * BAR existence is checked here against io_regions[], which is already + * populated by the device's own realize() at this point. Alignment and + * MMIO-window placement checks are deferred to blob-write time, when + * the full fixed-bar topology is available. + */ +static void pci_parse_pci_bars(PCIDevice *pci_dev, Error **errp) +{ + Error *local_err =3D NULL; + char **entries =3D NULL; + char **parts =3D NULL; + const char *endp; + char **e; + uint64_t bar_addr; + PCIIORegion *r; + int index; + int i, ret; + + if (!pci_dev->pci_bars || !*pci_dev->pci_bars) { + return; + } + if (DEVICE(pci_dev)->hotplugged) { + error_setg(&local_err, + "pci-bars is not supported on hot-plugged devices"); + goto out; + } + + entries =3D g_strsplit(pci_dev->pci_bars, ",", -1); + for (e =3D entries; e && *e; e++) { + const char *entry =3D g_strstrip(*e); + if (*entry =3D=3D '\0') { + error_setg(&local_err, + "pci-bars: " PCI_BARS_SYNTAX "empty field in list"); + goto out; + } + + parts =3D g_strsplit(entry, "@", 2); + if (!parts[0] || !parts[1]) { + error_setg(&local_err, + "pci-bars: " PCI_BARS_SYNTAX "missing '@' in '%s'", + entry); + goto out; + } + + index =3D pci_parse_bar_token(parts[0], &local_err); + if (index < 0) { + goto out; + } + + r =3D &pci_dev->io_regions[index]; + if (!r->size) { + error_setg(&local_err, "pci-bars: bar%d does not exist on %s", + index, pci_dev->name); + goto out; + } + if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { + error_setg(&local_err, "pci-bars: bar%d on %s is an I/O BAR, " + "not a memory BAR", index, pci_dev->name); + goto out; + } + + ret =3D qemu_strtou64(parts[1], &endp, 0, &bar_addr); + if (ret) { + error_setg(&local_err, + "pci-bars: " PCI_BARS_SYNTAX + "unparseable address in '%s'", entry); + goto out; + } + if (*endp !=3D '\0') { + error_setg(&local_err, + "pci-bars: " PCI_BARS_SYNTAX + "trailing data after address in '%s'", entry); + goto out; + } + g_clear_pointer(&parts, g_strfreev); + + if (!pci_dev->fixed_bar_addrs) { + pci_dev->fixed_bar_addrs =3D g_new(pcibus_t, PCI_NUM_REGIONS -= 1); + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + pci_dev->fixed_bar_addrs[i] =3D PCI_BAR_UNMAPPED; + } + } + if (pci_dev->fixed_bar_addrs[index] !=3D PCI_BAR_UNMAPPED) { + error_setg(&local_err, + "pci-bars: bar%d specified more than once", + index); + goto out; + } + pci_dev->fixed_bar_addrs[index] =3D (pcibus_t)bar_addr; + } + +out: + g_clear_pointer(&parts, g_strfreev); + g_strfreev(entries); + if (local_err) { + g_clear_pointer(&pci_dev->fixed_bar_addrs, g_free); + error_propagate(errp, local_err); + } +} + static int pcibus_num(PCIBus *bus) { if (pci_bus_is_root(bus)) { @@ -1479,6 +1600,7 @@ static void pci_qdev_unrealize(DeviceState *dev) pci_unregister_io_regions(pci_dev); pci_del_option_rom(pci_dev); pcie_sriov_unregister_device(pci_dev); + g_clear_pointer(&pci_dev->fixed_bar_addrs, g_free); =20 if (pc->exit) { pc->exit(pci_dev); @@ -2376,6 +2498,13 @@ static void pci_qdev_realize(DeviceState *qdev, Erro= r **errp) is_default_rom =3D true; } =20 + pci_parse_pci_bars(pci_dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + pci_qdev_unrealize(DEVICE(pci_dev)); + return; + } + pci_add_option_rom(pci_dev, is_default_rom, &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index 5cac6e1688..0bdc7ebce3 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -187,6 +187,16 @@ struct PCIDevice { uint32_t max_bounce_buffer_size; =20 char *sriov_pf; + + /* + * pci-bars property holds user-supplied fixed BAR addresses. + * pci_bars is the raw property string (barN@,...). + * fixed_bar_addrs is the parsed array (PCI_NUM_REGIONS-1 entries); + * each slot is PCI_BAR_UNMAPPED or the address for that BAR. + * NULL when the property is not set. + */ + char *pci_bars; + pcibus_t *fixed_bar_addrs; }; =20 static inline int pci_intx(PCIDevice *pci_dev) diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index b28af067a6..ef66c9768b 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -65,6 +65,7 @@ struct PCIESlot { =20 /* broken ACPI hotplug compat knob to preserve 6.1 ABI intact */ bool hide_native_hotplug_cap; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c107::9; envelope-from=tdave@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1787791352909158500 Validate the fixed BAR configuration specified through the pci-bars property on PCI devices and the fixed-bar property on PCIe root ports. When fixed-bar=3Don is set on a root port, every device in its hierarchy with a memory BAR must have pci-bars=3D specified. For any device with pci-bars=3D specified, validate that every memory BAR has an assigned address, and that each assigned address: - is aligned to its BAR size; - is within the appropriate PCIe MMIO aperture; and - does not overlap any other fixed BAR. Abort QEMU if any validation fails. Signed-off-by: Tushar Dave --- hw/pci/meson.build | 1 + hw/pci/pci-fixed-bar-validate.c | 279 ++++++++++++++++++++++++++++++++ hw/pci/pci-fixed-bar-validate.h | 21 +++ 3 files changed, 301 insertions(+) create mode 100644 hw/pci/pci-fixed-bar-validate.c create mode 100644 hw/pci/pci-fixed-bar-validate.h diff --git a/hw/pci/meson.build b/hw/pci/meson.build index a6cbd89c0a..44b94a24b4 100644 --- a/hw/pci/meson.build +++ b/hw/pci/meson.build @@ -17,6 +17,7 @@ pci_ss.add(files( pci_ss.add(files('pcie.c', 'pcie_aer.c')) pci_ss.add(files('pcie_doe.c')) system_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pcie_port.c', 'p= cie_host.c')) +system_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pci-fixed-bar-va= lidate.c')) system_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss) =20 stub_ss.add(files('pci-stub.c')) diff --git a/hw/pci/pci-fixed-bar-validate.c b/hw/pci/pci-fixed-bar-validat= e.c new file mode 100644 index 0000000000..a8cce3d296 --- /dev/null +++ b/hw/pci/pci-fixed-bar-validate.c @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved + * BAR address validation for fixed-BAR placement. + * + * Written by Tushar Dave + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pcie_port.h" +#include "hw/pci/pci_host.h" +#include "qemu/error-report.h" +#include "qemu/range.h" +#include "pci-internal.h" +#include "pci-fixed-bar-validate.h" + +/* + * Claimed BAR ranges =E2=80=94 detect inter-device and inter-hierarchy ov= erlaps + * across all fixed BARs system-wide. + */ + +typedef struct { + uint64_t start; + uint64_t end; + const char *owner; /* device name, for error messages */ + int bar; +} FixedClaim; + +static GArray *fixed_claims; + +static void fixed_claims_init(void) +{ + if (fixed_claims) { + g_array_free(fixed_claims, true); + } + fixed_claims =3D g_array_new(false, true, sizeof(FixedClaim)); +} + +static void fixed_claims_free(void) +{ + g_array_free(fixed_claims, true); + fixed_claims =3D NULL; +} + +static bool fixed_claims_overlap(uint64_t start, uint64_t end, + const char **owner_out, int *bar_out, + uint64_t *start_out, uint64_t *end_out) +{ + FixedClaim *c; + guint i; + + for (i =3D 0; i < fixed_claims->len; i++) { + c =3D &g_array_index(fixed_claims, FixedClaim, i); + if (ranges_overlap(start, end - start + 1, + c->start, c->end - c->start + 1)) { + *owner_out =3D c->owner; + *bar_out =3D c->bar; + *start_out =3D c->start; + *end_out =3D c->end; + return true; + } + } + return false; +} + +static void fixed_claims_add(uint64_t start, uint64_t end, + const char *owner, int bar) +{ + FixedClaim cl; + + cl.start =3D start; + cl.end =3D end; + cl.owner =3D owner; + cl.bar =3D bar; + g_array_append_val(fixed_claims, cl); +} + +static bool validate_bars(PCIDevice *pdev, FixedBarsInfo *info, + bool is_fixed_subtree) +{ + const char *devname =3D DEVICE(pdev)->id ? DEVICE(pdev)->id : pdev->n= ame; + const char *overlap_owner; + const char *wname; + bool has_pci_bars =3D (pdev->fixed_bar_addrs !=3D NULL); + bool is_64bit; + uint64_t addr, end, wbase, wlim, overlap_start, overlap_end; + PCIIORegion *r; + int overlap_bar; + int i; + + if (is_fixed_subtree && !has_pci_bars) { + error_report("pci-bars: %s [%02x:%02x.%x] under fixed-bar root por= t " + "has memory BARs but no pci-bars=3D specified", + devname, pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); + exit(1); + } + + if (!has_pci_bars) { + return false; + } + + /* Completeness: every memory BAR must have an address. */ + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + r =3D &pdev->io_regions[i]; + if (!r->size || (r->type & PCI_BASE_ADDRESS_SPACE_IO)) { + continue; + } + if (pdev->fixed_bar_addrs[i] =3D=3D PCI_BAR_UNMAPPED) { + error_report("pci-bars: %s [%02x:%02x.%x] BAR%d " + "missing from pci-bars=3D", + devname, pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), i); + exit(1); + } + } + + /* Per-BAR checks: alignment, MMIO window, overlap. */ + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + r =3D &pdev->io_regions[i]; + if (!r->size || (r->type & PCI_BASE_ADDRESS_SPACE_IO)) { + continue; + } + + is_64bit =3D !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); + addr =3D (uint64_t)pdev->fixed_bar_addrs[i]; + + if (r->size - 1 > UINT64_MAX - addr) { + error_report("pci-bars: %s [%02x:%02x.%x] BAR%d " + "addr=3D0x%"PRIx64" + size=3D0x%"PRIx64" overflow= s", + devname, pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), + i, addr, r->size); + exit(1); + } + end =3D addr + r->size - 1; + + /* + * wbase/wlim are both inclusive bounds (mmio*_limit =3D base+size= -1, + * set by the caller alongside mmio*_base), matching end's own + * inclusive computation above. + */ + if (is_64bit) { + wbase =3D info->mmio64_base; + wlim =3D info->mmio64_limit; + wname =3D "64-bit MMIO"; + } else { + wbase =3D info->mmio32_base; + wlim =3D info->mmio32_limit; + wname =3D "32-bit MMIO"; + } + + if (addr & (r->size - 1)) { + error_report("pci-bars: %s [%02x:%02x.%x] BAR%d " + "addr=3D0x%"PRIx64" not aligned to size=3D0x%"PRI= x64, + devname, pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), + i, addr, r->size); + exit(1); + } + + if (addr < wbase || end > wlim) { + error_report("pci-bars: %s [%02x:%02x.%x] BAR%d " + "[0x%"PRIx64"..0x%"PRIx64"] outside %s window " + "[0x%"PRIx64"..0x%"PRIx64"]", + devname, pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), + i, addr, end, wname, wbase, wlim); + exit(1); + } + + if (fixed_claims_overlap(addr, end, &overlap_owner, &overlap_bar, + &overlap_start, &overlap_end)) { + error_report("pci-bars: %s [%02x:%02x.%x] BAR%d " + "[0x%"PRIx64"..0x%"PRIx64"] overlaps %s BAR%d " + "[0x%"PRIx64"..0x%"PRIx64"]", + devname, pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), + i, addr, end, overlap_owner, overlap_bar, + overlap_start, overlap_end); + exit(1); + } + + fixed_claims_add(addr, end, devname, i); + } + + return true; +} + +/* + * True if bus, or any of its ancestor buses, hangs off a fixed-bar=3Don + * root port. Walks up via bus->parent_dev / pci_get_bus(). + */ +static bool bus_is_fixed_subtree(PCIBus *bus) +{ + PCIDevice *parent; + + while (bus) { + parent =3D bus->parent_dev; + if (!parent) { + return false; + } + if (object_dynamic_cast(OBJECT(parent), TYPE_PCIE_ROOT_PORT) && + PCIE_SLOT(parent)->fixed_bar) { + return true; + } + bus =3D pci_get_bus(parent); + } + return false; +} + +static void scan_bus(PCIBus *bus, void *opaque); + +static void scan_bus_device(PCIBus *bus, PCIDevice *pdev, void *opaque) +{ + FixedBarsInfo *info =3D opaque; + bool has_mem_bar =3D false; + PCIIORegion *r; + PCIBus *sec; + int i; + + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + r =3D &pdev->io_regions[i]; + if (r->size && !(r->type & PCI_BASE_ADDRESS_SPACE_IO)) { + has_mem_bar =3D true; + break; + } + } + + if (has_mem_bar) { + if (validate_bars(pdev, info, bus_is_fixed_subtree(bus))) { + info->any_fixed =3D true; + } + } + + if (!object_dynamic_cast(OBJECT(pdev), TYPE_PCI_BRIDGE)) { + return; + } + sec =3D pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); + if (sec) { + scan_bus(sec, opaque); + } +} + +static void scan_bus(PCIBus *bus, void *opaque) +{ + pci_for_each_device_under_bus(bus, scan_bus_device, opaque); +} + +static void scan_all_host_bridges(FixedBarsInfo *info) +{ + PCIHostState *hb; + + fixed_claims_init(); + QLIST_FOREACH(hb, &pci_host_bridges, next) { + if (hb->bus) { + scan_bus(hb->bus, info); + } + } + fixed_claims_free(); +} + +/* + * fixed_bars_validate - scan all PCI devices, validate fixed BAR addresse= s. + * + * @info: carries MMIO window bounds for validation. + * + * Returns true if any fixed BAR devices were found, false if there is + * nothing to do. Aborts on any validation error. + */ +bool fixed_bars_validate(FixedBarsInfo *info) +{ + info->any_fixed =3D false; + scan_all_host_bridges(info); + return info->any_fixed; +} diff --git a/hw/pci/pci-fixed-bar-validate.h b/hw/pci/pci-fixed-bar-validat= e.h new file mode 100644 index 0000000000..297d1480c0 --- /dev/null +++ b/hw/pci/pci-fixed-bar-validate.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved + * + * Written by Tushar Dave + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_PCI_FIXED_BAR_VALIDATE_H +#define HW_PCI_FIXED_BAR_VALIDATE_H + +typedef struct { + bool any_fixed; + uint64_t mmio32_base; + uint64_t mmio32_limit; + uint64_t mmio64_base; + uint64_t mmio64_limit; +} FixedBarsInfo; + +bool fixed_bars_validate(FixedBarsInfo *info); + +#endif /* HW_PCI_FIXED_BAR_VALIDATE_H */ --=20 2.34.1 From nobody Sat Sep 26 22:14:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1787791381; cv=pass; d=zohomail.com; s=zohoarc; b=n0nehkEthvSIy5+UplzzS+Q5BbPR2hhLBVBRGysiPhkPJYNpiYeQ4BgHcVmkSjPGCGI2PqcZnGwO+3dYHMCz8g0wsEtRv2si+eNWaj1kO1Peq5TxNG36TQ4e5EfTggAVWSr+8FQF9etccuIe7yZSLg9NhZRKMX/3obk8y3489DM= ARC-Message-Signature: i=2; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c107::9; envelope-from=tdave@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1787791382254158500 Introduce a fixed BAR fw_cfg blob exporter that serializes PCI device and BAR information into the "etc/fixed-bars" fw_cfg file. The blob contains an entry for every PCI function with memory BARs. Each entry identifies whether the device has a fixed BAR configuration, and fixed BAR entries include the configured address, size, and type information. Signed-off-by: Tushar Dave --- hw/pci/meson.build | 1 + hw/pci/pci-fixed-bar-blob.c | 291 ++++++++++++++++++++++++++++++++++++ hw/pci/pci-fixed-bar.h | 60 ++++++++ 3 files changed, 352 insertions(+) create mode 100644 hw/pci/pci-fixed-bar-blob.c create mode 100644 hw/pci/pci-fixed-bar.h diff --git a/hw/pci/meson.build b/hw/pci/meson.build index 44b94a24b4..5d975f27ef 100644 --- a/hw/pci/meson.build +++ b/hw/pci/meson.build @@ -18,6 +18,7 @@ pci_ss.add(files('pcie.c', 'pcie_aer.c')) pci_ss.add(files('pcie_doe.c')) system_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pcie_port.c', 'p= cie_host.c')) system_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pci-fixed-bar-va= lidate.c')) +system_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pci-fixed-bar-bl= ob.c')) system_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss) =20 stub_ss.add(files('pci-stub.c')) diff --git a/hw/pci/pci-fixed-bar-blob.c b/hw/pci/pci-fixed-bar-blob.c new file mode 100644 index 0000000000..d60ee65bf4 --- /dev/null +++ b/hw/pci/pci-fixed-bar-blob.c @@ -0,0 +1,291 @@ +/* + * Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved + * Write validated fixed-BAR device info to the etc/fixed-bars fw_cfg blob. + * + * Written by Tushar Dave + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/nvram/fw_cfg.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pci_host.h" +#include "hw/pci/pcie_port.h" +#include "qemu/error-report.h" +#include "pci-internal.h" +#include "pci-fixed-bar.h" +#include "pci-fixed-bar-validate.h" + +typedef struct { + uint8_t bar; + uint32_t flags; + uint64_t addr; + uint64_t size; +} BarInfo; + +/* One PCI function entry to be written to the blob. */ +typedef struct { + uint8_t rp_bus; /* primary bus of the root port this device is un= der */ + uint16_t vendor_id; + uint16_t device_id; + bool is_fixed; + GArray *bars; /* array of BarInfo */ +} DeviceInfo; + +typedef struct { + GArray *devices; + PCIBus *root_bus; +} CollectCtx; + +static void collect_device(PCIBus *bus, PCIDevice *pdev, void *opaque); + +/* Visit every device on this bus, in devfn order. */ +static void collect_bus(PCIBus *bus, void *opaque) +{ + pci_for_each_device_under_bus(bus, collect_device, opaque); +} + +/* + * Primary bus number of the nearest TYPE_PCIE_ROOT_PORT ancestor of bus + * =E2=80=94 i.e. the bus the root port device itself lives on, not its + * secondary bus. Falls back to the host bridge's own bus number if bus + * isn't under any root port (e.g. a device directly on the host + * bridge's primary bus). + */ +static uint8_t find_root_port_bus(PCIBus *bus, PCIBus *host_bus) +{ + PCIDevice *parent; + + while (bus) { + parent =3D bus->parent_dev; + if (!parent) { + break; + } + if (object_dynamic_cast(OBJECT(parent), TYPE_PCIE_ROOT_PORT)) { + return pci_bus_num(pci_get_bus(parent)); + } + bus =3D pci_get_bus(parent); + } + return pci_bus_num(host_bus); +} + +static void collect_device(PCIBus *bus, PCIDevice *pdev, void *opaque) +{ + CollectCtx *ctx =3D opaque; + bool has_mem_bar =3D false; + bool is_64bit, is_pref; + DeviceInfo dev; + PCIIORegion *r; + PCIBus *sec; + BarInfo bi; + int i; + + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + r =3D &pdev->io_regions[i]; + if (r->size && !(r->type & PCI_BASE_ADDRESS_SPACE_IO)) { + has_mem_bar =3D true; + break; + } + } + + /* + * Every device with a memory BAR gets an entry, fixed or not =E2=80= =94 not + * just ones with pci-bars=3D set. This preserves the exact device + * sequence CheckDevice() needs for positional VID:DID matching (see + * collect_all_host_bridges()); only fixed devices carry BAR records + * (dev.bars stays empty, dev.is_fixed false, otherwise). + */ + if (has_mem_bar) { + memset(&dev, 0, sizeof(dev)); + dev.rp_bus =3D find_root_port_bus(bus, ctx->root_bus); + dev.vendor_id =3D pci_get_word(pdev->config + PCI_VENDOR_ID); + dev.device_id =3D pci_get_word(pdev->config + PCI_DEVICE_ID); + dev.is_fixed =3D (pdev->fixed_bar_addrs !=3D NULL); + dev.bars =3D g_array_new(false, true, sizeof(BarInfo)); + + if (dev.is_fixed) { + for (i =3D 0; i < PCI_NUM_REGIONS - 1; i++) { + r =3D &pdev->io_regions[i]; + if (!r->size || (r->type & PCI_BASE_ADDRESS_SPACE_IO)) { + continue; + } + is_64bit =3D !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); + is_pref =3D !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); + + memset(&bi, 0, sizeof(bi)); + bi.bar =3D i; + bi.addr =3D (uint64_t)pdev->fixed_bar_addrs[i]; + bi.size =3D r->size; + bi.flags =3D (is_64bit ? QEMU_FIXED_BAR_F_MEM64 : 0) | + (is_pref ? QEMU_FIXED_BAR_F_PREF : 0); + g_array_append_val(dev.bars, bi); + } + } + g_array_append_val(ctx->devices, dev); + } + + if (!object_dynamic_cast(OBJECT(pdev), TYPE_PCI_BRIDGE)) { + return; + } + sec =3D pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); + if (sec) { + collect_bus(sec, opaque); + } +} + +static gint cmp_host_bus_num(gconstpointer a, gconstpointer b) +{ + PCIHostState *ha =3D *(PCIHostState **)a; + PCIHostState *hb =3D *(PCIHostState **)b; + return (gint)pci_bus_num(ha->bus) - (gint)pci_bus_num(hb->bus); +} + +/* + * EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL's CheckDevice interface + * (UEFI PI Spec 1.2 Vol 5) only passes VendorId/DeviceId/RevisionId/ + * SubsystemVendorId/SubsystemDeviceId, no BDF =E2=80=94 so in EDK2 we can= 't + * match a blob entry to a specific device directly using BDF. To work + * around that, we prepare the blob entries in the same order PciBusDxe + * discovers devices, so matching by VID:DID inherently works. + */ +static void collect_all_host_bridges(CollectCtx *ctx) +{ + PCIHostState *hb; + GPtrArray *sorted; + guint i; + + sorted =3D g_ptr_array_new(); + QLIST_FOREACH(hb, &pci_host_bridges, next) { + if (hb->bus) { + g_ptr_array_add(sorted, hb); + } + } + g_ptr_array_sort(sorted, cmp_host_bus_num); + + for (i =3D 0; i < sorted->len; i++) { + hb =3D g_ptr_array_index(sorted, i); + ctx->root_bus =3D hb->bus; + collect_bus(hb->bus, ctx); + } + + g_ptr_array_free(sorted, true); +} + +static uint8_t *create_blob(CollectCtx *ctx, size_t *blob_size) +{ + QemuFixedBarsDevice *dout; + QemuFixedBarsBar *bout; + QemuFixedBarsHdr *hdr; + DeviceInfo *dev; + uint8_t *blob; + uint8_t *ptr; + BarInfo *bi; + size_t sz; + guint d, b; + + sz =3D sizeof(QemuFixedBarsHdr); + for (d =3D 0; d < ctx->devices->len; d++) { + dev =3D &g_array_index(ctx->devices, DeviceInfo, d); + sz +=3D sizeof(QemuFixedBarsDevice); + sz +=3D dev->bars->len * sizeof(QemuFixedBarsBar); + } + + blob =3D g_malloc0(sz); + hdr =3D (QemuFixedBarsHdr *)blob; + hdr->version =3D cpu_to_le32(QEMU_FIXED_BARS_VERSION); + hdr->num_devices =3D cpu_to_le32(ctx->devices->len); + + ptr =3D blob + sizeof(*hdr); + for (d =3D 0; d < ctx->devices->len; d++) { + dev =3D &g_array_index(ctx->devices, DeviceInfo, d); + dout =3D (QemuFixedBarsDevice *)ptr; + + dout->vendor_id =3D cpu_to_le16(dev->vendor_id); + dout->device_id =3D cpu_to_le16(dev->device_id); + dout->dev_flags =3D dev->is_fixed ? QEMU_FIXED_BARS_DEV_F_FIXED : = 0; + dout->rp_bus =3D dev->rp_bus; + dout->num_bars =3D dev->bars->len; + dout->reserved =3D 0; + ptr +=3D sizeof(QemuFixedBarsDevice); + + for (b =3D 0; b < dev->bars->len; b++) { + bi =3D &g_array_index(dev->bars, BarInfo, b); + bout =3D (QemuFixedBarsBar *)ptr; + + bout->bar =3D bi->bar; + bout->flags =3D cpu_to_le32(bi->flags); + bout->address =3D cpu_to_le64(bi->addr); + bout->size =3D cpu_to_le64(bi->size); + ptr +=3D sizeof(QemuFixedBarsBar); + } + } + + *blob_size =3D sz; + return blob; +} + +/* + * fixed_bars_write_blob - validate fixed BAR addresses and write fw_cfg b= lob. + * + * @fw_cfg: fw_cfg state to write the etc/fixed-bars blob into. + * @mmio32_base: base of the machine's 32-bit PCIe MMIO aperture. + * @mmio32_size: size of the machine's 32-bit PCIe MMIO aperture. + * @mmio64_base: base of the machine's 64-bit PCIe MMIO aperture. + * @mmio64_size: size of the machine's 64-bit PCIe MMIO aperture. + * + * Returns true if any fixed BAR device was found and the blob was + * written, false if there was nothing to do. Aborts if any BAR + * address fails validation. + */ +bool fixed_bars_write_blob(FWCfgState *fw_cfg, + uint64_t mmio32_base, + uint64_t mmio32_size, + uint64_t mmio64_base, + uint64_t mmio64_size) +{ + FixedBarsInfo info; + CollectCtx ctx; + uint8_t *blob; + size_t blob_size; + guint d; + + if (!mmio32_size || !mmio64_size) { + error_report("pci-bars: zero-size PCIe MMIO aperture " + "(32-bit=3D0x%"PRIx64", 64-bit=3D0x%"PRIx64")", + mmio32_size, mmio64_size); + exit(1); + } + if (mmio32_size - 1 > UINT64_MAX - mmio32_base || + mmio64_size - 1 > UINT64_MAX - mmio64_base) { + error_report("pci-bars: PCIe MMIO aperture base+size overflows " + "(32-bit base=3D0x%"PRIx64" size=3D0x%"PRIx64", " + "64-bit base=3D0x%"PRIx64" size=3D0x%"PRIx64")", + mmio32_base, mmio32_size, mmio64_base, mmio64_size); + exit(1); + } + + info.mmio32_base =3D mmio32_base; + info.mmio32_limit =3D mmio32_base + mmio32_size - 1; + info.mmio64_base =3D mmio64_base; + info.mmio64_limit =3D mmio64_base + mmio64_size - 1; + + if (!fixed_bars_validate(&info)) { + return false; + } + + ctx.devices =3D g_array_new(false, true, sizeof(DeviceInfo)); + ctx.root_bus =3D NULL; + collect_all_host_bridges(&ctx); + + blob =3D create_blob(&ctx, &blob_size); + fw_cfg_add_file(fw_cfg, FW_CFG_FIXED_BARS, blob, blob_size); + + for (d =3D 0; d < ctx.devices->len; d++) { + g_array_free(g_array_index(ctx.devices, DeviceInfo, d).bars, true); + } + g_array_free(ctx.devices, true); + + return true; +} diff --git a/hw/pci/pci-fixed-bar.h b/hw/pci/pci-fixed-bar.h new file mode 100644 index 0000000000..3afc22a733 --- /dev/null +++ b/hw/pci/pci-fixed-bar.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved + * Fixed-BAR =E2=80=94 QEMU side declarations. + * + * Written by Tushar Dave + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_PCI_FIXED_BAR_H +#define HW_PCI_FIXED_BAR_H + +#include "hw/nvram/fw_cfg.h" +#include "hw/pci/pci_bus.h" + +#define FW_CFG_FIXED_BARS "etc/fixed-bars" +#define QEMU_FIXED_BARS_VERSION 1 + +/* + * On-wire layout (little-endian, packed): + * + * QemuFixedBarsHdr + * + * For each device (num_devices total): + * QemuFixedBarsDevice -- device header + * QemuFixedBarsBar[num_bars] -- one record per BAR (FIXED only) + */ + +typedef struct { + uint32_t version; /* QEMU_FIXED_BARS_VERSION */ + uint32_t num_devices; +} QEMU_PACKED QemuFixedBarsHdr; /* 8 bytes */ + +typedef struct { + uint16_t vendor_id; + uint16_t device_id; + uint8_t dev_flags; /* QEMU_FIXED_BARS_DEV_F_* */ + uint8_t rp_bus; /* primary bus of the root port this device is un= der */ + uint8_t num_bars; + uint8_t reserved; +} QEMU_PACKED QemuFixedBarsDevice; /* 8 bytes */ + +typedef struct { + uint8_t bar; + uint8_t reserved[3]; + uint32_t flags; /* QEMU_FIXED_BAR_F_* */ + uint64_t address; + uint64_t size; +} QEMU_PACKED QemuFixedBarsBar; /* 24 bytes */ + +#define QEMU_FIXED_BAR_F_MEM64 (1u << 0) +#define QEMU_FIXED_BAR_F_PREF (1u << 1) +#define QEMU_FIXED_BARS_DEV_F_FIXED (1u << 0) + +bool fixed_bars_write_blob(FWCfgState *fw_cfg, + uint64_t mmio32_base, + uint64_t mmio32_size, + uint64_t mmio64_base, + uint64_t mmio64_size); + +#endif /* HW_PCI_FIXED_BAR_H */ --=20 2.34.1 From nobody Sat Sep 26 22:14:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1787791374; cv=pass; d=zohomail.com; s=zohoarc; b=AW+c1fsrEvlQR6INQIBv+IBtoXhL+9Dy5RNsUVojdewKU/U3rCiwj0vG3gGGJFZF1lon+wHKvJrhMB1sFyxJotQubmZZWroXSnK71yCxoh66ERQTAjdVGpsf7P4gANbaidRYEUrO+9VuunJ2xq6L+AQ19KYxZJme3+Ooev84uTA= ARC-Message-Signature: i=2; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c107::9; envelope-from=tdave@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1787791376203158500 Content-Type: text/plain; charset="utf-8" Export fixed BAR metadata from the virt machine through the "etc/fixed-bars" fw_cfg file during machine initialization. Fixed BAR placement requires firmware to preserve the PCI resource configuration established by QEMU. ACPI provides this via the PCI boot configuration preservation mechanism, _DSM function 5. Reject fixed BAR configuration when ACPI is disabled, and request PCI boot configuration preservation when ACPI is enabled. Signed-off-by: Tushar Dave --- hw/arm/virt.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index e7a56e37f7..cb9cd2d25c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -96,6 +96,7 @@ #include "hw/cxl/cxl_host.h" #include "qemu/guest-random.h" #include "hw/watchdog/sbsa_gwdt.h" +#include "hw/pci/pci-fixed-bar.h" =20 static GlobalProperty arm_virt_compat_defaults[] =3D { { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" }, @@ -2440,6 +2441,21 @@ void virt_machine_done(Notifier *notifier, void *dat= a) vms->memmap[VIRT_PLATFORM_BUS].size, vms->irqmap[VIRT_PLATFORM_BUS]); } + if (fixed_bars_write_blob(vms->fw_cfg, + vms->memmap[VIRT_PCIE_MMIO].base, + vms->memmap[VIRT_PCIE_MMIO].size, + vms->memmap[VIRT_HIGH_PCIE_MMIO].base, + vms->memmap[VIRT_HIGH_PCIE_MMIO].size)) { + if (!virt_is_acpi_enabled(vms)) { + error_report("pci-bars: fixed BAR placement requires ACPI to " + "preserve the PCI boot configuration, otherwise " + "these BAR assignments could be reassigned later " + "with no protection"); + exit(1); + } + vms->pci_preserve_config =3D true; + } + if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) = < 0) { exit(1); } --=20 2.34.1 From nobody Sat Sep 26 22:14:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1787791349; cv=pass; d=zohomail.com; s=zohoarc; b=knk4gn1qylKeX+WWkqkACOZMniUr8xE4XZNS2CuUSbdFRkB8oC+B2yupG84BRmsdD/4x6FBc31jdAFny20lNw7qTOfnMlhoLDzy00TJhsc8HmWumpRSj3DmbIwHutkGZxagg852r2g/3AmnNGAueeZBqcrbb1CIMcSlStToTwXc= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787791349; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c107::9; envelope-from=tdave@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1787791352870158500 Content-Type: text/plain; charset="utf-8" Add a highmem-mmio-base property to override the base of the virt machine's high PCIe MMIO window, alongside the existing highmem-mmio-size: -machine virt,highmem-mmio-base=3D,highmem-mmio-size=3D Some PCI devices require MMIO resources to be placed within a specific address range that cannot be satisfied by the default placement. The configured base is validated to be non-zero, aligned to highmem-mmio-size, non-overlapping with the existing high memory layout, and within the configured physical address space. Signed-off-by: Tushar Dave --- hw/arm/virt.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index cb9cd2d25c..47653b8753 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2515,9 +2515,34 @@ static void virt_set_high_memmap(VirtMachineState *v= ms, =20 for (i =3D VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { region_enabled =3D virt_get_high_memmap_enabled(vms, i); - region_base =3D ROUND_UP(base, extended_memmap[i].size); region_size =3D extended_memmap[i].size; =20 + if (i =3D=3D VIRT_HIGH_PCIE_MMIO && extended_memmap[i].base) { + region_base =3D extended_memmap[i].base; + + if (region_base < base) { + error_report("highmem-mmio-base 0x%"PRIx64" overlaps prior= " + "high memory layout (must be >=3D 0x%"PRIx64"= )", + region_base, base); + exit(1); + } + if (region_base % region_size !=3D 0) { + error_report("highmem-mmio-base 0x%"PRIx64" must be " + "aligned to highmem-mmio-size 0x%"PRIx64, + region_base, region_size); + exit(1); + } + if (region_base + region_size > BIT_ULL(pa_bits)) { + error_report("highmem-mmio-base + highmem-mmio-size " + "[0x%"PRIx64", 0x%"PRIx64") exceeds %d-bit PA= " + "space", region_base, + region_base + region_size, pa_bits); + exit(1); + } + } else { + region_base =3D ROUND_UP(base, region_size); + } + vms->memmap[i].base =3D region_base; vms->memmap[i].size =3D region_size; =20 @@ -3418,6 +3443,33 @@ static void virt_set_highmem_mmio_size(Object *obj, = Visitor *v, extended_memmap[VIRT_HIGH_PCIE_MMIO].size =3D size; } =20 +static void virt_get_highmem_mmio_base(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + uint64_t base =3D extended_memmap[VIRT_HIGH_PCIE_MMIO].base; + + visit_type_size(v, name, &base, errp); +} + +static void virt_set_highmem_mmio_base(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + uint64_t base; + + if (!visit_type_size(v, name, &base, errp)) { + return; + } + + if (base =3D=3D 0) { + error_setg(errp, "highmem-mmio-base cannot be 0"); + return; + } + + extended_memmap[VIRT_HIGH_PCIE_MMIO].base =3D base; +} + static char *virt_get_msi(Object *obj, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); @@ -4285,6 +4337,14 @@ static void virt_machine_class_init(ObjectClass *oc,= const void *data) "Set the high memory region size= " "for PCI MMIO"); =20 + object_class_property_add(oc, "highmem-mmio-base", "size", + virt_get_highmem_mmio_base, + virt_set_highmem_mmio_base, + NULL, NULL); + object_class_property_set_description(oc, "highmem-mmio-base", + "Set the high memory region base= " + "for PCI MMIO"); + object_class_property_add(oc, "virtio-mmio-transports", "uint8", virt_get_virtio_transports, virt_set_virtio_transports, --=20 2.34.1