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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KmuEzpXCD6VmoJtt/XZUs9llE/2YuHOKrCwlztASk6g=; b=BWgWAg8YUz6bTYF90LtpCBzaLvuCYVq8+t6J80yTgoxdCfubjyTD3v6e0r7+zpRKzYA2WX JOYLg8+seiPf1zAECGGTffNN33xPW7X6GRjD5NYuiNrM/+HydGqe+n6Iw0M8G1JJTIT1pF M/+wE9QCVpFLqSZBWLZCZDesksHQdi4= X-MC-Unique: R76zvBtUNuatUzaYT3uWRA-1 X-Mimecast-MFC-AGG-ID: R76zvBtUNuatUzaYT3uWRA_1787737084 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 01/20] scripts: introduce scripts/update-aarch64-cpu-sysregs-header.py Date: Wed, 26 Aug 2026 11:36:06 +0200 Message-ID: <20260826093747.1670077-2-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Introduce a script that takes as input the Registers.json file delivered in the AARCHMRS Features Model downloadable from the Arm Developer A-Profile Architecture Exploration Tools page: https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloads and outputs the list of ID regs in target/arm/cpu-sysregs.h.inc under the form of DEF(, , , , , ). We only care about IDregs with opcodes satisfying: op0 =3D 3, op1 =3D {0,1,3}, crn =3D 0, crm within [0, 7], op2 within [0, 7] Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Khushit Shah --- scripts/update-aarch64-cpu-sysregs-header.py | 146 +++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100755 scripts/update-aarch64-cpu-sysregs-header.py diff --git a/scripts/update-aarch64-cpu-sysregs-header.py b/scripts/update-= aarch64-cpu-sysregs-header.py new file mode 100755 index 0000000000..ef1471a197 --- /dev/null +++ b/scripts/update-aarch64-cpu-sysregs-header.py @@ -0,0 +1,146 @@ +#!/usr/bin/env python3 + +# This script takes as input the Registers.json file delivered in +# the AARCHMRS Features Model downloadable from the Arm Developer +# A-Profile Architecture Exploration Tools page: +# https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloa= ds +# and outputs the list of ID regs in target/arm/cpu-sysregs.h.inc +# under the form of DEF(, , , , , ) +# +# Copyright (C) 2026 Red Hat, Inc. +# +# Authors: Eric Auger +# +# SPDX-License-Identifier: GPL-2.0-or-later + + +import json +import os +import sys + +def is_demux_register(r): + name =3D r.get('name', '') + + if name.startswith("CCSIDR"): + return True + + return False + +# Some regs have op code values like 000x, 001x. Anyway we don't need +# them. Besides some regs are undesired in the generated file such as +# VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we +# are interested in and are tricky to decode as their system accessor +# refer to MPIDR_EL1/MIDR_EL1 respectively + +skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \ + 'VMPIDR_EL2', 'VPIDR_EL2'] + +# returns the int value of a given @opcode for a reg @encoding +def get_opcode(encoding, opcode): + fvalue =3D encoding.get(opcode) + if fvalue: + value =3D fvalue.get('value') + if isinstance(value, str): + value =3D value.strip("'") + value =3D int(value, 2) + return value + return -1 + +def extract_idregs_from_registers_json(filename): + """ + Load a Registers.json file and extract all ID registers, decode their + opcode and dump the information in target/arm/cpu-sysregs.h.inc + + Args: + filename (str): The path to the Registers.json + returns: + idregs: list of ID regs and their encoding + """ + if not os.path.exists(filename): + print(f"Error: {filename} could not be found!") + return {} + + try: + with open(filename, 'r') as f: + register_data =3D json.load(f) + + except json.JSONDecodeError: + print(f"Could not decode json from '{filename}'!") + return {} + except Exception as e: + print(f"Unexpected error while reading {filename}: {e}") + return {} + + registers =3D [ + r for r in register_data + if isinstance(r, dict) + and r.get('_type') =3D=3D 'Register' + and not is_demux_register(r) + ] + + idregs =3D {} + + for register in registers: + reg_name =3D register.get('name') + + is_skipped =3D any(term in (reg_name or "").upper() for term in sk= iplist) + + if reg_name and not is_skipped: + accessors =3D register.get('accessors', []) + + for accessor in accessors: + type =3D accessor.get('_type') + if type in ['Accessors.SystemAccessor']: + encoding_list =3D accessor.get('encoding') + + if isinstance(encoding_list, list) and encoding_list a= nd \ + isinstance(encoding_list[0], dict): + encoding_wrapper =3D encoding_list[0] + encoding_source =3D encoding_wrapper.get('encoding= s', \ + encoding_wr= apper) + + if isinstance(encoding_source, dict): + op0 =3D get_opcode(encoding_source, 'op0') + op1 =3D get_opcode(encoding_source, 'op1') + op2 =3D get_opcode(encoding_source, 'op2') + crn =3D get_opcode(encoding_source, 'CRn') + crm =3D get_opcode(encoding_source, 'CRm') + encoding_str=3Df"{op0} {op1} {crn} {crm} {= op2}" + + # ID regs are assumed within this scope + if op0 =3D=3D 3 and (op1 =3D=3D 0 or op1 =3D=3D 1 or op1 = =3D=3D 3) and \ + crn =3D=3D 0 and (crm >=3D 0 and crm <=3D 7) and (op2 >= =3D 0 and op2 <=3D 7): + idregs[reg_name] =3D encoding_str + + return idregs + +if __name__ =3D=3D "__main__": + # Single arg expected: the path to the Registers.json file + if len(sys.argv) < 2: + print("Usage: python scripts/update-aarch64-cpu-sysregs-header.py " + "") + sys.exit(1) + else: + json_file_path =3D sys.argv[1] + + extracted_registers =3D extract_idregs_from_registers_json(json_file_p= ath) + + if extracted_registers: + output_list =3D extracted_registers.items() + + # Sort by register name + sorted_output =3D sorted(output_list, key=3Dlambda item: item[0]) + + # format lines as DEF(, , , , , ) + final_output =3D "" + for reg_name, encoding in sorted_output: + reformatted_encoding =3D encoding.replace(" ", ", ") + final_output +=3D f"DEF({reg_name}, {reformatted_encoding})\n" + + with open("target/arm/cpu-sysregs.h.inc", 'w') as f: + f.write("/* SPDX-License-Identifier: GPL-2.0-or-later */\n\n") + f.write("/* This file is autogenerated by ") + f.write("scripts/update-aarch64-cpu-sysregs-header.py */\n") + f.write("/* DEF(, , , , , ) */\= n\n") + f.write(final_output) + print("updated target/arm/cpu-sysregs.h.inc") --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737095; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PGwhGSRwbZ5oBDYs0gjQNDzMSLjGv9rxTmsKdTjHBlA=; b=BZa9EWAJIrYZjOK6+nWm7K5MclHwgTkSOrhVV4d/fxlmhPWvdbLou6triFmFEsXKHvozWG oLhDy4TUETnr/GjFhDrh9w8zrMi7A16CaPTe2UtvvDsN7JUvZaYMzO7LTcr6EfaqbXTP1b DPpe/JUFc7oF87/xOBFFjCtzI4V5TKs= X-MC-Unique: xEHeRsUjPpam_RyajDUDYQ-1 X-Mimecast-MFC-AGG-ID: xEHeRsUjPpam_RyajDUDYQ_1787737090 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 02/20] target/arm/cpu-sysregs.h.inc: Sort by name alphabetical order Date: Wed, 26 Aug 2026 11:36:07 +0200 Message-ID: <20260826093747.1670077-3-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737133169158500 Content-Type: text/plain; charset="utf-8" Sort by register name alphabetical order. This will allow to easily diff with the future content, automatically generated. No functional change intended. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Shameer Kolothum Reviewed-by: Khushit Shah --- v5 -> v6: - v5 version conflicted because ID_AA64FPFR0_EL1 has been added v4 -> v5: - remove spurious CCSIDR definition --- target/arm/cpu-sysregs.h.inc | 44 ++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index 6e8b335b8f..ec5a12b0f4 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) -DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) -DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2) -DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) -DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) -DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) -DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(CLIDR_EL1, 3, 1, 0, 0, 1) +DEF(CTR_EL0, 3, 3, 0, 0, 1) +DEF(DCZID_EL0, 3, 3, 0, 0, 7) DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4) DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5) +DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) +DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) @@ -17,29 +16,30 @@ DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4) -DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) -DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) -DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) +DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) +DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) +DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2) +DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) +DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) DEF(ID_AFR0_EL1, 3, 0, 0, 1, 3) -DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4) -DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5) -DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6) -DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7) +DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) +DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) DEF(ID_ISAR0_EL1, 3, 0, 0, 2, 0) DEF(ID_ISAR1_EL1, 3, 0, 0, 2, 1) DEF(ID_ISAR2_EL1, 3, 0, 0, 2, 2) DEF(ID_ISAR3_EL1, 3, 0, 0, 2, 3) DEF(ID_ISAR4_EL1, 3, 0, 0, 2, 4) DEF(ID_ISAR5_EL1, 3, 0, 0, 2, 5) -DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6) DEF(ID_ISAR6_EL1, 3, 0, 0, 2, 7) +DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4) +DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5) +DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6) +DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7) +DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6) +DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) +DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) +DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) +DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) DEF(MVFR0_EL1, 3, 0, 0, 3, 0) DEF(MVFR1_EL1, 3, 0, 0, 3, 1) DEF(MVFR2_EL1, 3, 0, 0, 3, 2) -DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) -DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) -DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) -DEF(CLIDR_EL1, 3, 1, 0, 0, 1) -DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) -DEF(CTR_EL0, 3, 3, 0, 0, 1) -DEF(DCZID_EL0, 3, 3, 0, 0, 7) --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737103; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=voHwf+YFtdVEzgBWVvYQX13hhjEDTySDg3UzKLNi7tE=; b=Q6QiqPHfksOIbxYa7TqEcoU1KA+BydwqF536Jyek/iDuAGVQTvvVxTRhBBqGn4Zh1SkDNg jTCTfYTK0JzONfGikaaW9broLlxfBkeY5iK8/CJQk/QYvUk6AydgfxqcUWeMnS4tDhbSGC cmgO/x4pDFCAbCFTyML//pVUWG2IJmQ= X-MC-Unique: 8yYWgmCUNd2QPisvDYomOw-1 X-Mimecast-MFC-AGG-ID: 8yYWgmCUNd2QPisvDYomOw_1787737097 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 03/20] target/arm/cpu-sysregs.h.inc: Update with automatic generation Date: Wed, 26 Aug 2026 11:36:08 +0200 Message-ID: <20260826093747.1670077-4-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737135171158500 Content-Type: text/plain; charset="utf-8" Generated definitions with scripts/update-aarch64-cpu-sysregs-header.py based on "AARCHMRS containing the JSON files for Arm A-profile architecture (2026-03)" Registers.json file. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Shameer Kolothum --- target/arm/cpu-sysregs.h.inc | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index ec5a12b0f4..8b77c490d4 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -1,11 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* This file is autogenerated by scripts/update-aarch64-cpu-sysregs-header= .py */ +/* DEF(, , , , , ) */ + +DEF(AIDR_EL1, 3, 1, 0, 0, 7) DEF(CLIDR_EL1, 3, 1, 0, 0, 1) DEF(CTR_EL0, 3, 3, 0, 0, 1) DEF(DCZID_EL0, 3, 3, 0, 0, 7) +DEF(GMID_EL1, 3, 1, 0, 0, 4) DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4) DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5) DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(ID_AA64DFR2_EL1, 3, 0, 0, 5, 2) DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) @@ -40,6 +47,10 @@ DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) +DEF(MIDR_EL1, 3, 0, 0, 0, 0) +DEF(MPIDR_EL1, 3, 0, 0, 0, 5) DEF(MVFR0_EL1, 3, 0, 0, 3, 0) DEF(MVFR1_EL1, 3, 0, 0, 3, 1) DEF(MVFR2_EL1, 3, 0, 0, 3, 2) +DEF(REVIDR_EL1, 3, 0, 0, 0, 6) +DEF(SMIDR_EL1, 3, 1, 0, 0, 6) --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 26 Aug 2026 05:38:31 -0400 Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-557-VmDD3r8fPwquTFttcLukuw-1; Wed, 26 Aug 2026 05:38:25 -0400 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 3A3D0197765F; Wed, 26 Aug 2026 09:38:23 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.48.93]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 5CC9F1955F05; Wed, 26 Aug 2026 09:38:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737109; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CYMDAiuX3NMXS8zhqozIt3cUizP2vJsejo6cSarl3BA=; b=Vn7fgsSrPo4s9nomwL9WIdpBsl+ejDfj9RPIEzot67P33WsDFC9XODoZpQPejMAkVaUccY NjWWSZPXarWfyfqdSGV2uLIM9CkTBh0wHqZp/vWqkEGOJmUqutFV/ckj5rpqpMirjM+bSD oenRDBZnGLooMtVCtPu/9sWgz0yFHxE= X-MC-Unique: VmDD3r8fPwquTFttcLukuw-1 X-Mimecast-MFC-AGG-ID: VmDD3r8fPwquTFttcLukuw_1787737103 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 04/20] arm/cpu: Add infra to handle generated ID register definitions Date: Wed, 26 Aug 2026 11:36:09 +0200 Message-ID: <20260826093747.1670077-5-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737145289158500 Content-Type: text/plain; charset="utf-8" Introduce an infrastructure to store the definition of all ID regs: This include their name, index and array of named fields. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Co-authored-by: Khushit Shah Signed-off-by: Khushit Shah --- v7 -> v8: - remove typedef struct ArmIdRegArchVal v5 -> v6: - add ArmIdRegArchVal --- target/arm/cpu-idregs.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 target/arm/cpu-idregs.h diff --git a/target/arm/cpu-idregs.h b/target/arm/cpu-idregs.h new file mode 100644 index 0000000000..98c7a7518f --- /dev/null +++ b/target/arm/cpu-idregs.h @@ -0,0 +1,36 @@ +/* + * handle ID registers and their fields + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef TARGET_ARM_CPU_IDREGS_H +#define TARGET_ARM_CPU_IDREGS_H + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "cpu-sysregs.h" + +typedef struct ARM64SysRegField { + const char *name; /* name of the field, for instance CTR_EL0_IDC */ + ARMIDRegisterIdx index; /* parent register, e.g. CTR_EL0_IDX */ + int shift; /* lsb of the field in the register */ + int length; /* highest bit number */ + uint64_t *arch_vals; + uint32_t arch_vals_count; +} ARM64SysRegField; + +typedef struct ARM64SysReg { + const char *name; /* name of the sysreg, for instance CTR_EL0 */ + ARMIDRegisterIdx index; /* register index, e.g. CTR_EL0_IDX */ + struct ARM64SysRegField *fields; + uint32_t fields_count; + uint64_t writable_mask; +} ARM64SysReg; + +/* + * List of exposed ID regs (automatically populated from AARCHMRS Register= s.json) + */ +extern ARM64SysReg arm64_id_regs[NUM_ID_IDX]; + +#endif --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1787737233; cv=none; d=zohomail.com; s=zohoarc; b=MYYprnqtVa4MaLFUOR3OycSKwINYibIVHC00DaqK/cNnW+Ad7SQW8iShxM2iVxRkm5c9mkThNJai3qHlfof7UbzVvl2SyYlpsobjSBT+ds7imV4qw1JLkO2wAP0XvnAC4Gu36krXU/WPsE/KYx5h5qI5CjCExh8v6CS0bVVRKWQ= ARC-Message-Signature: i=1; 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Wed, 26 Aug 2026 09:38:30 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.48.93]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id B3F751955F05; Wed, 26 Aug 2026 09:38:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737201; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XmgKG6NMohjgsyNM/iCgqjlycA3hA6zWHQIfm95HhtQ=; b=WosTlRCce/fWaV89GggdE4qD1+d/UgrWG3YnVQaa7URok9y6fEY8UvqCPF3Zi0Ouaaa727 kQWHghPBQ4N6M6vHdWegd95/N8fFgt3CldsxJlEAVuVkOC51TGG9MhuHkHoS/dsfG+0/mc 470VqwPTjCwNi0lEfwAGxSzePvh7whc= X-MC-Unique: 3ARD8plnOByV-xzSflukgA-1 X-Mimecast-MFC-AGG-ID: 3ARD8plnOByV-xzSflukgA_1787737110 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 05/20] scripts: Introduce scripts/aarch64_sysreg_helpers module Date: Wed, 26 Aug 2026 11:36:10 +0200 Message-ID: <20260826093747.1670077-6-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737235783158500 Content-Type: text/plain; charset="utf-8" We plan to reuse get_opcode() and extract_idregs_from_registers_json() functions in another script. So let's move them into a module No functional change intended. Signed-off-by: Eric Auger Reviewed-by: Khushit Shah --- scripts/aarch64_sysreg_helpers.py | 121 +++++++++++++++++++ scripts/update-aarch64-cpu-sysregs-header.py | 97 +-------------- 2 files changed, 122 insertions(+), 96 deletions(-) create mode 100644 scripts/aarch64_sysreg_helpers.py diff --git a/scripts/aarch64_sysreg_helpers.py b/scripts/aarch64_sysreg_hel= pers.py new file mode 100644 index 0000000000..24bbc5bb3d --- /dev/null +++ b/scripts/aarch64_sysreg_helpers.py @@ -0,0 +1,121 @@ +#!/usr/bin/env python3 + +# Helpers used in aarch64 sysreg definition generation +# +# Copyright (C) 2026 Red Hat, Inc. +# +# Authors: Eric Auger +# +# SPDX-License-Identifier: GPL-2.0-or-later + + +import json +import os + +def is_demux_register(r): + name =3D r.get('name', '') + + if name.startswith("CCSIDR"): + return True + + return False + +# Some regs have op code values like 000x, 001x. Anyway we don't need +# them. Besides some regs are undesired in the generated file such as +# VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we +# are interested in and are tricky to decode as their system accessor +# refer to MPIDR_EL1/MIDR_EL1 respectively + +skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \ + 'VMPIDR_EL2', 'VPIDR_EL2'] + +# returns the int value of a given @opcode for a reg @encoding +def get_opcode(encoding, opcode): + fvalue =3D encoding.get(opcode) + if fvalue: + value =3D fvalue.get('value') + if isinstance(value, str): + value =3D value.strip("'") + value =3D int(value, 2) + return value + return -1 + +def extract_idregs_from_registers_json(filename): + """ + Load a Registers.json file and extract all ID registers, decode their + opcode and dump the information in target/arm/cpu-sysregs.h.inc + + Args: + filename (str): The path to the Registers.json + returns: + idregs: list of ID regs and their encoding + """ + if not os.path.exists(filename): + print(f"Error: {filename} could not be found!") + return {} + + try: + with open(filename, 'r') as f: + register_data =3D json.load(f) + + except json.JSONDecodeError: + print(f"Could not decode json from '{filename}'!") + return {} + except Exception as e: + print(f"Unexpected error while reading {filename}: {e}") + return {} + + registers =3D [ + r for r in register_data + if isinstance(r, dict) + and r.get('_type') =3D=3D 'Register' + and not is_demux_register(r) + ] + + idregs =3D {} + + # Some regs have op code values like 000x, 001x. Anyway we don't need + # them. Besides some regs are undesired in the generated file such as + # VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we + # are interested in and are tricky to decode as their system accessor + # refer to MPIDR_EL1/MIDR_EL1 respectively + + skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \ + 'VMPIDR_EL2', 'VPIDR_EL2'] + + for register in registers: + reg_name =3D register.get('name') + + is_skipped =3D any(term in (reg_name or "").upper() for term in sk= iplist) + + if reg_name and not is_skipped: + accessors =3D register.get('accessors', []) + + for accessor in accessors: + type =3D accessor.get('_type') + if type in ['Accessors.SystemAccessor']: + encoding_list =3D accessor.get('encoding') + + if isinstance(encoding_list, list) and encoding_list a= nd \ + isinstance(encoding_list[0], dict): + encoding_wrapper =3D encoding_list[0] + encoding_source =3D encoding_wrapper.get('encoding= s', \ + encoding_wr= apper) + + if isinstance(encoding_source, dict): + op0 =3D get_opcode(encoding_source, 'op0') + op1 =3D get_opcode(encoding_source, 'op1') + op2 =3D get_opcode(encoding_source, 'op2') + crn =3D get_opcode(encoding_source, 'CRn') + crm =3D get_opcode(encoding_source, 'CRm') + encoding_str=3Df"{op0} {op1} {crn} {crm} {= op2}" + + # ID regs are assumed within this scope + if op0 =3D=3D 3 and (op1 =3D=3D 0 or op1 =3D=3D 1 or op1 = =3D=3D 3) and \ + crn =3D=3D 0 and (crm >=3D 0 and crm <=3D 7) and (op2 >= =3D 0 and op2 <=3D 7): + idregs[reg_name] =3D encoding_str + + return idregs + + + diff --git a/scripts/update-aarch64-cpu-sysregs-header.py b/scripts/update-= aarch64-cpu-sysregs-header.py index ef1471a197..43107264e9 100755 --- a/scripts/update-aarch64-cpu-sysregs-header.py +++ b/scripts/update-aarch64-cpu-sysregs-header.py @@ -17,102 +17,7 @@ import json import os import sys - -def is_demux_register(r): - name =3D r.get('name', '') - - if name.startswith("CCSIDR"): - return True - - return False - -# Some regs have op code values like 000x, 001x. Anyway we don't need -# them. Besides some regs are undesired in the generated file such as -# VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we -# are interested in and are tricky to decode as their system accessor -# refer to MPIDR_EL1/MIDR_EL1 respectively - -skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \ - 'VMPIDR_EL2', 'VPIDR_EL2'] - -# returns the int value of a given @opcode for a reg @encoding -def get_opcode(encoding, opcode): - fvalue =3D encoding.get(opcode) - if fvalue: - value =3D fvalue.get('value') - if isinstance(value, str): - value =3D value.strip("'") - value =3D int(value, 2) - return value - return -1 - -def extract_idregs_from_registers_json(filename): - """ - Load a Registers.json file and extract all ID registers, decode their - opcode and dump the information in target/arm/cpu-sysregs.h.inc - - Args: - filename (str): The path to the Registers.json - returns: - idregs: list of ID regs and their encoding - """ - if not os.path.exists(filename): - print(f"Error: {filename} could not be found!") - return {} - - try: - with open(filename, 'r') as f: - register_data =3D json.load(f) - - except json.JSONDecodeError: - print(f"Could not decode json from '{filename}'!") - return {} - except Exception as e: - print(f"Unexpected error while reading {filename}: {e}") - return {} - - registers =3D [ - r for r in register_data - if isinstance(r, dict) - and r.get('_type') =3D=3D 'Register' - and not is_demux_register(r) - ] - - idregs =3D {} - - for register in registers: - reg_name =3D register.get('name') - - is_skipped =3D any(term in (reg_name or "").upper() for term in sk= iplist) - - if reg_name and not is_skipped: - accessors =3D register.get('accessors', []) - - for accessor in accessors: - type =3D accessor.get('_type') - if type in ['Accessors.SystemAccessor']: - encoding_list =3D accessor.get('encoding') - - if isinstance(encoding_list, list) and encoding_list a= nd \ - isinstance(encoding_list[0], dict): - encoding_wrapper =3D encoding_list[0] - encoding_source =3D encoding_wrapper.get('encoding= s', \ - encoding_wr= apper) - - if isinstance(encoding_source, dict): - op0 =3D get_opcode(encoding_source, 'op0') - op1 =3D get_opcode(encoding_source, 'op1') - op2 =3D get_opcode(encoding_source, 'op2') - crn =3D get_opcode(encoding_source, 'CRn') - crm =3D get_opcode(encoding_source, 'CRm') - encoding_str=3Df"{op0} {op1} {crn} {crm} {= op2}" - - # ID regs are assumed within this scope - if op0 =3D=3D 3 and (op1 =3D=3D 0 or op1 =3D=3D 1 or op1 = =3D=3D 3) and \ - crn =3D=3D 0 and (crm >=3D 0 and crm <=3D 7) and (op2 >= =3D 0 and op2 <=3D 7): - idregs[reg_name] =3D encoding_str - - return idregs +from aarch64_sysreg_helpers import extract_idregs_from_registers_json =20 if __name__ =3D=3D "__main__": # Single arg expected: the path to the Registers.json file --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737122; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0MgtnSaVh9ax7ryBzZLi/K7BKaomljz1Cy0WeKLK4ak=; b=EssawiXv9OF7lHJV8XGm/7jN4lDn+XmZ5GGGBvdPV3cQJuVVkwbCFw86qz93U+CZOAOtQX gY+HkSaEM3C1XhprwOgqW1rVFzGOegV2JyWQppITMcx6ctaH1E+Gk82eGqLdmuxGSSNJeq eYwmYJGWdgh9j/ydVfy2jVEjwTDEd8M= X-MC-Unique: bhrNP6rqNiOni9GRHUkfPg-1 X-Mimecast-MFC-AGG-ID: bhrNP6rqNiOni9GRHUkfPg_1787737117 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 06/20] scripts: Introduce scripts/update-aarch64-cpu-sysreg-properties.py Date: Wed, 26 Aug 2026 11:36:11 +0200 Message-ID: <20260826093747.1670077-7-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737157320158500 Content-Type: text/plain; charset="utf-8" Introduce a script that takes as input the Registers.json file delivered in the AARCHMRS Features Model downloadable from the Arm Developer A-Profile Architecture Exploration Tools page: https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloads and automates the generation of system register properties definitions. generates target/arm/cpu-idregs.h.inc containing definitions for feature ID registers. We only care about IDregs with opcodes satisfying: op0 =3D 3, op1 =3D {0,1,3}, crn =3D 0, crm within [0, 7], op2 within [0, 7] Signed-off-by: Eric Auger --- v5 -> v6 - add ident --- .../update-aarch64-cpu-sysreg-properties.py | 166 ++++++++++++++++++ 1 file changed, 166 insertions(+) create mode 100644 scripts/update-aarch64-cpu-sysreg-properties.py diff --git a/scripts/update-aarch64-cpu-sysreg-properties.py b/scripts/upda= te-aarch64-cpu-sysreg-properties.py new file mode 100644 index 0000000000..6f5edb88d2 --- /dev/null +++ b/scripts/update-aarch64-cpu-sysreg-properties.py @@ -0,0 +1,166 @@ +#!/usr/bin/env python3 + +# This script takes as input the Registers.json file delivered in +# the AARCHMRS Features Model downloadable from the Arm Developer +# A-Profile Architecture Exploration Tools page: +# https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloa= ds +# and outputs target/arm/cpu-idregs.h.inc content. +# ID regs are defined using this pattern: +# +# IDREG_START(REG) +# IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) +# ... +# IDREG_END(REG) +# +# Copyright (C) 2026 Red Hat, Inc. +# +# Authors: Eric Auger +# +# SPDX-License-Identifier: GPL-2.0-or-later + + +import json +import os +import sys +from aarch64_sysreg_helpers import extract_idregs_from_registers_json + +def collect_fields(item, bit_offset=3D0): + """ + Recursively finds all field-like objects, handling Fields.Array, + Fields.ArrayField, and ConditionalField structures. + Applies bit_offset from containers to child fields. + """ + fields =3D [] + if not isinstance(item, dict): + return fields + + _type =3D item.get('_type', '') + + # Array types (for example CLIDR_EL1 Ctype, Ttype) + if _type =3D=3D 'Fields.Array': + name_template =3D item.get('name') or item.get('label', '') + index_info =3D item.get('indexes', [{}])[0] + start_idx =3D index_info.get('start', 0) + count =3D index_info.get('width', 0) + + full_range =3D item.get('rangeset', [{}])[0] + bit_start =3D full_range.get('start', 0) + bit_offset + elem_width =3D full_range.get('width', 0) // count if count else 0 + + for i in range(count): + idx =3D start_idx + i + # Correctly handle indexed names like Ctype1, Ctype2 + field_name =3D name_template.replace('', str(idx)) + fields.append({ + 'name': field_name, + 'rangeset': [{ + 'start': bit_start + (i * elem_width), + 'width': elem_width + }], + '_type': 'Fields.Field' + }) + return fields + + # ConditionalFields + elif _type =3D=3D 'Fields.ConditionalField': + inner_offset =3D bit_offset + if item.get('rangeset'): + # Parent container defines the absolute start bit + inner_offset =3D item['rangeset'][0].get('start', bit_offset) + + for entry in item.get('fields', []): + inner =3D entry.get('field') + if inner: + fields.extend(collect_fields(inner, inner_offset)) + return fields + + # Normal Field Types + leaf_types =3D ['Fields.Field', 'Fields.ConstantField', + 'Fields.EnumeratedField', 'Fields.Bitfield'] + if _type in leaf_types: + field_copy =3D item.copy() + if field_copy.get('rangeset'): + new_ranges =3D [] + for r in field_copy['rangeset']: + nr =3D r.copy() + # Apply the cumulative offset to the field's start bit + nr['start'] =3D r.get('start', 0) + bit_offset + new_ranges.append(nr) + field_copy['rangeset'] =3D new_ranges + fields.append(field_copy) + return fields + + # Traverse the hierarchy for other cases + for key in ['fields', 'values', 'fieldsets']: + for nested in item.get(key, []): + fields.extend(collect_fields(nested, bit_offset)) + + return fields + + +def generate_sysreg_properties_from_registers_json(id_reg_names, raw_json_= path): + with open(raw_json_path, 'r') as f: + register_data =3D json.load(f) + + regs =3D {r.get('name'): r for r in register_data if r.get('_type') = =3D=3D 'Register'} + + final_output =3D "" + + for reg_name in id_reg_names: + register =3D regs.get(reg_name) + if not register: + continue + + final_output +=3D f"IDREG_START({reg_name})\n" + + unique_fields =3D {} + for fieldset in register.get('fieldsets', []): + candidates =3D collect_fields(fieldset) + for val in candidates: + name =3D (val.get('name') or val.get('label', '')).strip() + if not name or "RESERVED" in name.upper(): + continue + for r in val.get('rangeset', []): + lsb =3D int(r.get('start')) + width =3D r.get('width') + msb =3D lsb + int(width) - 1 + + # Only keep the fields with the highest MSB + # needed fir CCSIDR_EL1 + if name not in unique_fields or msb > unique_fields[na= me]['msb']: + unique_fields[name] =3D {'lsb': lsb, 'msb': msb, '= width': width} + + # Sort decreasing lsbs + sorted_fields =3D sorted(unique_fields.items(), + key=3Dlambda x: x[1]['lsb'], reverse=3DTrue) + + for name, bits in sorted_fields: + line =3D (f" IDREG_FIELD({reg_name}, " + f"{name}, {bits['lsb']}, {bits['width']})\n") + final_output +=3D line + final_output +=3D f"IDREG_END({reg_name})\n" + final_output +=3D "\n" + + os.makedirs("target/arm", exist_ok=3DTrue) + with open("target/arm/cpu-idregs.h.inc", 'w') as f: + f.write("/* AUTOMATICALLY GENERATED, DO NOT MODIFY */\n\n") + f.write("/* SPDX-License-Identifier: GPL-2.0-or-later */\n\n") + f.write("/* IDREG_START(REG) */\n") + f.write("/* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */\n") + f.write("/* ... */\n") + f.write("/* IDREG_END(REG) */\n\n") + f.write(final_output) + +if __name__ =3D=3D "__main__": + if len(sys.argv) < 2: + print("Usage: python scripts/update-aarch64-cpu-sysreg-properties.= py " + "") + else: + json_path =3D sys.argv[1] + + id_regs_dict =3D extract_idregs_from_registers_json(json_path) + sorted_names =3D sorted(id_regs_dict.keys()) + + if sorted_names: + generate_sysreg_properties_from_registers_json(sorted_names, j= son_path) + print("Generated target/arm/cpu-idregs.h.inc") --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737200; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=e8i2vuqnFKuWkX5qslhpvJPs44SxMMtPwaLpKERBO9g=; b=C+zMwrD9RHxu9ma2/XPolEnLPUR6OWWWetYYjTAJ9RL9yQUyk6tK/MElY6V7fZl36x41ux ZmV4LByQMMGfaU4smVmr8kd1+EKClYhtzWeXbZgJyafwy6PCvvIFI129l+GYK3KMra+Wtk VLBPMEqXeYO1tXNAr0gNgXy6ktW8Vq0= X-MC-Unique: qTvZv3M_OPqtV5l4hJqdGA-1 X-Mimecast-MFC-AGG-ID: qTvZv3M_OPqtV5l4hJqdGA_1787737123 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 07/20] target/arm/cpu-idregs.h.inc: generate with script Date: Wed, 26 Aug 2026 11:36:12 +0200 Message-ID: <20260826093747.1670077-8-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737241680158500 Content-Type: text/plain; charset="utf-8" Generate ID reg definitions with the scripts/update-aarch64-cpu-sysreg-prop= erties.py based on AARCHMRS_OPENSOURCE_A_profile_FAT-2026-03 Registers.json Each register and fields are described with this pattern: IDREG_START(REG) IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) ... IDREG_END(REG) Signed-off-by: Eric Auger Suggested-by: Khushit Shah Suggested-by: Shaju Abraham --- target/arm/cpu-idregs.h.inc | 607 ++++++++++++++++++++++++++++++++++++ 1 file changed, 607 insertions(+) create mode 100644 target/arm/cpu-idregs.h.inc diff --git a/target/arm/cpu-idregs.h.inc b/target/arm/cpu-idregs.h.inc new file mode 100644 index 0000000000..c9745e2fb6 --- /dev/null +++ b/target/arm/cpu-idregs.h.inc @@ -0,0 +1,607 @@ +/* AUTOMATICALLY GENERATED, DO NOT MODIFY */ + +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* IDREG_START(REG) */ +/* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */ +/* ... */ +/* IDREG_END(REG) */ + +IDREG_START(AIDR_EL1) +IDREG_END(AIDR_EL1) + +IDREG_START(CLIDR_EL1) + IDREG_FIELD(CLIDR_EL1, Ttype7, 45, 2) + IDREG_FIELD(CLIDR_EL1, Ttype6, 43, 2) + IDREG_FIELD(CLIDR_EL1, Ttype5, 41, 2) + IDREG_FIELD(CLIDR_EL1, Ttype4, 39, 2) + IDREG_FIELD(CLIDR_EL1, Ttype3, 37, 2) + IDREG_FIELD(CLIDR_EL1, Ttype2, 35, 2) + IDREG_FIELD(CLIDR_EL1, Ttype1, 33, 2) + IDREG_FIELD(CLIDR_EL1, ICB, 30, 3) + IDREG_FIELD(CLIDR_EL1, LoUU, 27, 3) + IDREG_FIELD(CLIDR_EL1, LoC, 24, 3) + IDREG_FIELD(CLIDR_EL1, LoUIS, 21, 3) + IDREG_FIELD(CLIDR_EL1, Ctype7, 18, 3) + IDREG_FIELD(CLIDR_EL1, Ctype6, 15, 3) + IDREG_FIELD(CLIDR_EL1, Ctype5, 12, 3) + IDREG_FIELD(CLIDR_EL1, Ctype4, 9, 3) + IDREG_FIELD(CLIDR_EL1, Ctype3, 6, 3) + IDREG_FIELD(CLIDR_EL1, Ctype2, 3, 3) + IDREG_FIELD(CLIDR_EL1, Ctype1, 0, 3) +IDREG_END(CLIDR_EL1) + +IDREG_START(CTR_EL0) + IDREG_FIELD(CTR_EL0, TminLine, 32, 6) + IDREG_FIELD(CTR_EL0, DIC, 29, 1) + IDREG_FIELD(CTR_EL0, IDC, 28, 1) + IDREG_FIELD(CTR_EL0, CWG, 24, 4) + IDREG_FIELD(CTR_EL0, ERG, 20, 4) + IDREG_FIELD(CTR_EL0, DminLine, 16, 4) + IDREG_FIELD(CTR_EL0, L1Ip, 14, 2) + IDREG_FIELD(CTR_EL0, IminLine, 0, 4) +IDREG_END(CTR_EL0) + +IDREG_START(DCZID_EL0) + IDREG_FIELD(DCZID_EL0, TBS, 5, 4) + IDREG_FIELD(DCZID_EL0, DZP, 4, 1) + IDREG_FIELD(DCZID_EL0, BS, 0, 4) +IDREG_END(DCZID_EL0) + +IDREG_START(GMID_EL1) + IDREG_FIELD(GMID_EL1, BS, 0, 4) +IDREG_END(GMID_EL1) + +IDREG_START(ID_AA64AFR0_EL1) +IDREG_END(ID_AA64AFR0_EL1) + +IDREG_START(ID_AA64AFR1_EL1) +IDREG_END(ID_AA64AFR1_EL1) + +IDREG_START(ID_AA64DFR0_EL1) + IDREG_FIELD(ID_AA64DFR0_EL1, HPMN0, 60, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, ExtTrcBuff, 56, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, BRBE, 52, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, MTPMU, 48, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, TraceBuffer, 44, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, TraceFilt, 40, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, DoubleLock, 36, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, PMSVer, 32, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, WRPs, 20, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, PMSS, 16, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, BRPs, 12, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, PMUVer, 8, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, TraceVer, 4, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, DebugVer, 0, 4) +IDREG_END(ID_AA64DFR0_EL1) + +IDREG_START(ID_AA64DFR1_EL1) + IDREG_FIELD(ID_AA64DFR1_EL1, ABL_CMPs, 56, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, DPFZS, 52, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, EBEP, 48, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, ITE, 44, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, ABLE, 40, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, PMICNTR, 36, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, SPMU, 32, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, CTX_CMPs, 24, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, WRPs, 16, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, BRPs, 8, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, SYSPMUID, 0, 8) +IDREG_END(ID_AA64DFR1_EL1) + +IDREG_START(ID_AA64DFR2_EL1) + IDREG_FIELD(ID_AA64DFR2_EL1, TRBE_EXC, 24, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, SPE_nVM, 20, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, SPE_EXC, 16, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, BWE, 4, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, STEP, 0, 4) +IDREG_END(ID_AA64DFR2_EL1) + +IDREG_START(ID_AA64FPFR0_EL1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8CVT, 31, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8FMA, 30, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP4, 29, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP2, 28, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM8, 27, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM4, 26, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F16MM2, 15, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8E4M3, 1, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8E5M2, 0, 1) +IDREG_END(ID_AA64FPFR0_EL1) + +IDREG_START(ID_AA64ISAR0_EL1) + IDREG_FIELD(ID_AA64ISAR0_EL1, RNDR, 60, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, TLB, 56, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, TS, 52, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, FHM, 48, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, DP, 44, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SM4, 40, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SM3, 36, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SHA3, 32, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, RDM, 28, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, Atomic, 20, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, CRC32, 16, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SHA2, 12, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SHA1, 8, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, AES, 4, 4) +IDREG_END(ID_AA64ISAR0_EL1) + +IDREG_START(ID_AA64ISAR1_EL1) + IDREG_FIELD(ID_AA64ISAR1_EL1, LS64, 60, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, XS, 56, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, I8MM, 52, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, DGH, 48, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, BF16, 44, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, SPECRES, 40, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, SB, 36, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, FRINTTS, 32, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, GPI, 28, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, GPA, 24, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, LRCPC, 20, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, FCMA, 16, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, JSCVT, 12, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, API, 8, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, APA, 4, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, DPB, 0, 4) +IDREG_END(ID_AA64ISAR1_EL1) + +IDREG_START(ID_AA64ISAR2_EL1) + IDREG_FIELD(ID_AA64ISAR2_EL1, ATS1A, 60, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, LUT, 56, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, CSSC, 52, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, RPRFM, 48, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, PCDPHINT, 44, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, PRFMSLC, 40, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, SYSINSTR_128, 36, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, SYSREG_128, 32, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, CLRBHB, 28, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, PAC_frac, 24, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, BC, 20, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, MOPS, 16, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, APA3, 12, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, GPA3, 8, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, RPRES, 4, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, WFxT, 0, 4) +IDREG_END(ID_AA64ISAR2_EL1) + +IDREG_START(ID_AA64ISAR3_EL1) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSCP, 44, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSCSHINT, 40, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, MTETC, 36, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, PAC_frac2, 32, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, FPRCVT, 28, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSUI, 24, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, OCCMO, 20, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSFE, 16, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, PACM, 12, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, TLBIW, 8, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, FAMINMAX, 4, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, CPA, 0, 4) +IDREG_END(ID_AA64ISAR3_EL1) + +IDREG_START(ID_AA64MMFR0_EL1) + IDREG_FIELD(ID_AA64MMFR0_EL1, ECV, 60, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, FGT, 56, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, ExS, 44, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4_2, 40, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64_2, 36, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16_2, 32, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4, 28, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64, 24, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16, 20, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, BigEndEL0, 16, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, SNSMem, 12, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, BigEnd, 8, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, ASIDBits, 4, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, PARange, 0, 4) +IDREG_END(ID_AA64MMFR0_EL1) + +IDREG_START(ID_AA64MMFR1_EL1) + IDREG_FIELD(ID_AA64MMFR1_EL1, ECBHB, 60, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, CMOW, 56, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, TIDCP1, 52, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, nTLBPA, 48, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, AFP, 44, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, HCX, 40, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, ETS, 36, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, TWED, 32, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, XNX, 28, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, SpecSEI, 24, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, PAN, 20, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, LO, 16, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, HPDS, 12, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, VH, 8, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, VMIDBits, 4, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, HAFDBS, 0, 4) +IDREG_END(ID_AA64MMFR1_EL1) + +IDREG_START(ID_AA64MMFR2_EL1) + IDREG_FIELD(ID_AA64MMFR2_EL1, E0PD, 60, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, EVT, 56, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, BBM, 52, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, TTL, 48, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, FWB, 40, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, IDS, 36, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, AT, 32, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, ST, 28, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, NV, 24, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, CCIDX, 20, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, VARange, 16, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, IESB, 12, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, LSM, 8, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, UAO, 4, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, CnP, 0, 4) +IDREG_END(ID_AA64MMFR2_EL1) + +IDREG_START(ID_AA64MMFR3_EL1) + IDREG_FIELD(ID_AA64MMFR3_EL1, Spec_FPACC, 60, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, ADERR, 56, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, SDERR, 52, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, ANERR, 44, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, SNERR, 40, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, D128_2, 36, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, D128, 32, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, MEC, 28, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, AIE, 24, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S2POE, 20, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S1POE, 16, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S2PIE, 12, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S1PIE, 8, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, SCTLRX, 4, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, TCRX, 0, 4) +IDREG_END(ID_AA64MMFR3_EL1) + +IDREG_START(ID_AA64MMFR4_EL1) + IDREG_FIELD(ID_AA64MMFR4_EL1, MTEFGT, 60, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, SCRX, 56, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, TEV, 52, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, TPS, 48, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, SRMASK, 44, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, TLBID, 40, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, E3DSE, 36, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, EAESR, 32, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, RMEGDI, 28, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, E2H0, 24, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, NV_frac, 20, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, FGWTE3, 16, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, HACDBS, 12, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, ASID2, 8, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, EIESB, 4, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, PoPS, 0, 4) +IDREG_END(ID_AA64MMFR4_EL1) + +IDREG_START(ID_AA64PFR0_EL1) + IDREG_FIELD(ID_AA64PFR0_EL1, CSV3, 60, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, CSV2, 56, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, RME, 52, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, DIT, 48, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, AMU, 44, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, MPAM, 40, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, SEL2, 36, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, SVE, 32, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, RAS, 28, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, GIC, 24, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, AdvSIMD, 20, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, FP, 16, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL3, 12, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL2, 8, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL1, 4, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL0, 0, 4) +IDREG_END(ID_AA64PFR0_EL1) + +IDREG_START(ID_AA64PFR1_EL1) + IDREG_FIELD(ID_AA64PFR1_EL1, PFAR, 60, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, DF2, 56, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MTEX, 52, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, THE, 48, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, GCS, 44, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MTE_frac, 40, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, NMI, 36, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, CSV2_frac, 32, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, RNDR_trap, 28, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, SME, 24, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MPAM_frac, 16, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, RAS_frac, 12, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MTE, 8, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, SSBS, 4, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, BT, 0, 4) +IDREG_END(ID_AA64PFR1_EL1) + +IDREG_START(ID_AA64PFR2_EL1) + IDREG_FIELD(ID_AA64PFR2_EL1, VMTETCL, 44, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, VMTETC, 40, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, VMTE, 36, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, FPMR, 32, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MPAM2, 28, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, FGDT, 24, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTEEIRG, 20, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, UINJ, 16, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, GCIE, 12, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTEFAR, 8, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTESTOREONLY, 4, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTEPERM, 0, 4) +IDREG_END(ID_AA64PFR2_EL1) + +IDREG_START(ID_AA64SMFR0_EL1) + IDREG_FIELD(ID_AA64SMFR0_EL1, FA64, 63, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, LUT6, 61, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, LUTv2, 60, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SMEver, 56, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, I16I64, 52, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, F64F64, 48, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, I16I32, 44, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, B16B16, 43, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F16F16, 42, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F8F16, 41, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F8F32, 40, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, I8I32, 36, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, F16F32, 35, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, B16F32, 34, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, BI32I32, 33, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F32F32, 32, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SF8FMA, 30, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP4, 29, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP2, 28, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SBitPerm, 25, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, AES, 24, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SFEXPA, 23, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, STMOP, 16, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SMOP4, 0, 1) +IDREG_END(ID_AA64SMFR0_EL1) + +IDREG_START(ID_AA64ZFR0_EL1) + IDREG_FIELD(ID_AA64ZFR0_EL1, F64MM, 56, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, F32MM, 52, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, F16MM, 48, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, I8MM, 44, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, SM4, 40, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, SHA3, 32, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, B16B16, 24, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, BF16, 20, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, BitPerm, 16, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, EltPerm, 12, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, AES, 4, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, SVEver, 0, 4) +IDREG_END(ID_AA64ZFR0_EL1) + +IDREG_START(ID_AFR0_EL1) +IDREG_END(ID_AFR0_EL1) + +IDREG_START(ID_DFR0_EL1) + IDREG_FIELD(ID_DFR0_EL1, TraceFilt, 28, 4) + IDREG_FIELD(ID_DFR0_EL1, PerfMon, 24, 4) + IDREG_FIELD(ID_DFR0_EL1, MProfDbg, 20, 4) + IDREG_FIELD(ID_DFR0_EL1, MMapTrc, 16, 4) + IDREG_FIELD(ID_DFR0_EL1, CopTrc, 12, 4) + IDREG_FIELD(ID_DFR0_EL1, MMapDbg, 8, 4) + IDREG_FIELD(ID_DFR0_EL1, CopSDbg, 4, 4) + IDREG_FIELD(ID_DFR0_EL1, CopDbg, 0, 4) +IDREG_END(ID_DFR0_EL1) + +IDREG_START(ID_DFR1_EL1) + IDREG_FIELD(ID_DFR1_EL1, HPMN0, 4, 4) + IDREG_FIELD(ID_DFR1_EL1, MTPMU, 0, 4) +IDREG_END(ID_DFR1_EL1) + +IDREG_START(ID_ISAR0_EL1) + IDREG_FIELD(ID_ISAR0_EL1, Divide, 24, 4) + IDREG_FIELD(ID_ISAR0_EL1, Debug, 20, 4) + IDREG_FIELD(ID_ISAR0_EL1, Coproc, 16, 4) + IDREG_FIELD(ID_ISAR0_EL1, CmpBranch, 12, 4) + IDREG_FIELD(ID_ISAR0_EL1, BitField, 8, 4) + IDREG_FIELD(ID_ISAR0_EL1, BitCount, 4, 4) + IDREG_FIELD(ID_ISAR0_EL1, Swap, 0, 4) +IDREG_END(ID_ISAR0_EL1) + +IDREG_START(ID_ISAR1_EL1) + IDREG_FIELD(ID_ISAR1_EL1, Jazelle, 28, 4) + IDREG_FIELD(ID_ISAR1_EL1, Interwork, 24, 4) + IDREG_FIELD(ID_ISAR1_EL1, Immediate, 20, 4) + IDREG_FIELD(ID_ISAR1_EL1, IfThen, 16, 4) + IDREG_FIELD(ID_ISAR1_EL1, Extend, 12, 4) + IDREG_FIELD(ID_ISAR1_EL1, Except_AR, 8, 4) + IDREG_FIELD(ID_ISAR1_EL1, Except, 4, 4) + IDREG_FIELD(ID_ISAR1_EL1, Endian, 0, 4) +IDREG_END(ID_ISAR1_EL1) + +IDREG_START(ID_ISAR2_EL1) + IDREG_FIELD(ID_ISAR2_EL1, Reversal, 28, 4) + IDREG_FIELD(ID_ISAR2_EL1, PSR_AR, 24, 4) + IDREG_FIELD(ID_ISAR2_EL1, MultU, 20, 4) + IDREG_FIELD(ID_ISAR2_EL1, MultS, 16, 4) + IDREG_FIELD(ID_ISAR2_EL1, Mult, 12, 4) + IDREG_FIELD(ID_ISAR2_EL1, MultiAccessInt, 8, 4) + IDREG_FIELD(ID_ISAR2_EL1, MemHint, 4, 4) + IDREG_FIELD(ID_ISAR2_EL1, LoadStore, 0, 4) +IDREG_END(ID_ISAR2_EL1) + +IDREG_START(ID_ISAR3_EL1) + IDREG_FIELD(ID_ISAR3_EL1, T32EE, 28, 4) + IDREG_FIELD(ID_ISAR3_EL1, TrueNOP, 24, 4) + IDREG_FIELD(ID_ISAR3_EL1, T32Copy, 20, 4) + IDREG_FIELD(ID_ISAR3_EL1, TabBranch, 16, 4) + IDREG_FIELD(ID_ISAR3_EL1, SynchPrim, 12, 4) + IDREG_FIELD(ID_ISAR3_EL1, SVC, 8, 4) + IDREG_FIELD(ID_ISAR3_EL1, SIMD, 4, 4) + IDREG_FIELD(ID_ISAR3_EL1, Saturate, 0, 4) +IDREG_END(ID_ISAR3_EL1) + +IDREG_START(ID_ISAR4_EL1) + IDREG_FIELD(ID_ISAR4_EL1, SWP_frac, 28, 4) + IDREG_FIELD(ID_ISAR4_EL1, PSR_M, 24, 4) + IDREG_FIELD(ID_ISAR4_EL1, SynchPrim_frac, 20, 4) + IDREG_FIELD(ID_ISAR4_EL1, Barrier, 16, 4) + IDREG_FIELD(ID_ISAR4_EL1, SMC, 12, 4) + IDREG_FIELD(ID_ISAR4_EL1, Writeback, 8, 4) + IDREG_FIELD(ID_ISAR4_EL1, WithShifts, 4, 4) + IDREG_FIELD(ID_ISAR4_EL1, Unpriv, 0, 4) +IDREG_END(ID_ISAR4_EL1) + +IDREG_START(ID_ISAR5_EL1) + IDREG_FIELD(ID_ISAR5_EL1, VCMA, 28, 4) + IDREG_FIELD(ID_ISAR5_EL1, RDM, 24, 4) + IDREG_FIELD(ID_ISAR5_EL1, CRC32, 16, 4) + IDREG_FIELD(ID_ISAR5_EL1, SHA2, 12, 4) + IDREG_FIELD(ID_ISAR5_EL1, SHA1, 8, 4) + IDREG_FIELD(ID_ISAR5_EL1, AES, 4, 4) + IDREG_FIELD(ID_ISAR5_EL1, SEVL, 0, 4) +IDREG_END(ID_ISAR5_EL1) + +IDREG_START(ID_ISAR6_EL1) + IDREG_FIELD(ID_ISAR6_EL1, CLRBHB, 28, 4) + IDREG_FIELD(ID_ISAR6_EL1, I8MM, 24, 4) + IDREG_FIELD(ID_ISAR6_EL1, BF16, 20, 4) + IDREG_FIELD(ID_ISAR6_EL1, SPECRES, 16, 4) + IDREG_FIELD(ID_ISAR6_EL1, SB, 12, 4) + IDREG_FIELD(ID_ISAR6_EL1, FHM, 8, 4) + IDREG_FIELD(ID_ISAR6_EL1, DP, 4, 4) + IDREG_FIELD(ID_ISAR6_EL1, JSCVT, 0, 4) +IDREG_END(ID_ISAR6_EL1) + +IDREG_START(ID_MMFR0_EL1) + IDREG_FIELD(ID_MMFR0_EL1, InnerShr, 28, 4) + IDREG_FIELD(ID_MMFR0_EL1, FCSE, 24, 4) + IDREG_FIELD(ID_MMFR0_EL1, AuxReg, 20, 4) + IDREG_FIELD(ID_MMFR0_EL1, TCM, 16, 4) + IDREG_FIELD(ID_MMFR0_EL1, ShareLvl, 12, 4) + IDREG_FIELD(ID_MMFR0_EL1, OuterShr, 8, 4) + IDREG_FIELD(ID_MMFR0_EL1, PMSA, 4, 4) + IDREG_FIELD(ID_MMFR0_EL1, VMSA, 0, 4) +IDREG_END(ID_MMFR0_EL1) + +IDREG_START(ID_MMFR1_EL1) + IDREG_FIELD(ID_MMFR1_EL1, BPred, 28, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1TstCln, 24, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1Uni, 20, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1Hvd, 16, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1UniSW, 12, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1HvdSW, 8, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1UniVA, 4, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1HvdVA, 0, 4) +IDREG_END(ID_MMFR1_EL1) + +IDREG_START(ID_MMFR2_EL1) + IDREG_FIELD(ID_MMFR2_EL1, HWAccFlg, 28, 4) + IDREG_FIELD(ID_MMFR2_EL1, WFIStall, 24, 4) + IDREG_FIELD(ID_MMFR2_EL1, MemBarr, 20, 4) + IDREG_FIELD(ID_MMFR2_EL1, UniTLB, 16, 4) + IDREG_FIELD(ID_MMFR2_EL1, HvdTLB, 12, 4) + IDREG_FIELD(ID_MMFR2_EL1, L1HvdRng, 8, 4) + IDREG_FIELD(ID_MMFR2_EL1, L1HvdBG, 4, 4) + IDREG_FIELD(ID_MMFR2_EL1, L1HvdFG, 0, 4) +IDREG_END(ID_MMFR2_EL1) + +IDREG_START(ID_MMFR3_EL1) + IDREG_FIELD(ID_MMFR3_EL1, Supersec, 28, 4) + IDREG_FIELD(ID_MMFR3_EL1, CMemSz, 24, 4) + IDREG_FIELD(ID_MMFR3_EL1, CohWalk, 20, 4) + IDREG_FIELD(ID_MMFR3_EL1, PAN, 16, 4) + IDREG_FIELD(ID_MMFR3_EL1, MaintBcst, 12, 4) + IDREG_FIELD(ID_MMFR3_EL1, BPMaint, 8, 4) + IDREG_FIELD(ID_MMFR3_EL1, CMaintSW, 4, 4) + IDREG_FIELD(ID_MMFR3_EL1, CMaintVA, 0, 4) +IDREG_END(ID_MMFR3_EL1) + +IDREG_START(ID_MMFR4_EL1) + IDREG_FIELD(ID_MMFR4_EL1, EVT, 28, 4) + IDREG_FIELD(ID_MMFR4_EL1, CCIDX, 24, 4) + IDREG_FIELD(ID_MMFR4_EL1, LSM, 20, 4) + IDREG_FIELD(ID_MMFR4_EL1, HPDS, 16, 4) + IDREG_FIELD(ID_MMFR4_EL1, CnP, 12, 4) + IDREG_FIELD(ID_MMFR4_EL1, XNX, 8, 4) + IDREG_FIELD(ID_MMFR4_EL1, AC2, 4, 4) + IDREG_FIELD(ID_MMFR4_EL1, SpecSEI, 0, 4) +IDREG_END(ID_MMFR4_EL1) + +IDREG_START(ID_MMFR5_EL1) + IDREG_FIELD(ID_MMFR5_EL1, nTLBPA, 4, 4) + IDREG_FIELD(ID_MMFR5_EL1, ETS, 0, 4) +IDREG_END(ID_MMFR5_EL1) + +IDREG_START(ID_PFR0_EL1) + IDREG_FIELD(ID_PFR0_EL1, RAS, 28, 4) + IDREG_FIELD(ID_PFR0_EL1, DIT, 24, 4) + IDREG_FIELD(ID_PFR0_EL1, AMU, 20, 4) + IDREG_FIELD(ID_PFR0_EL1, CSV2, 16, 4) + IDREG_FIELD(ID_PFR0_EL1, State3, 12, 4) + IDREG_FIELD(ID_PFR0_EL1, State2, 8, 4) + IDREG_FIELD(ID_PFR0_EL1, State1, 4, 4) + IDREG_FIELD(ID_PFR0_EL1, State0, 0, 4) +IDREG_END(ID_PFR0_EL1) + +IDREG_START(ID_PFR1_EL1) + IDREG_FIELD(ID_PFR1_EL1, GIC, 28, 4) + IDREG_FIELD(ID_PFR1_EL1, Virt_frac, 24, 4) + IDREG_FIELD(ID_PFR1_EL1, Sec_frac, 20, 4) + IDREG_FIELD(ID_PFR1_EL1, GenTimer, 16, 4) + IDREG_FIELD(ID_PFR1_EL1, Virtualization, 12, 4) + IDREG_FIELD(ID_PFR1_EL1, MProgMod, 8, 4) + IDREG_FIELD(ID_PFR1_EL1, Security, 4, 4) + IDREG_FIELD(ID_PFR1_EL1, ProgMod, 0, 4) +IDREG_END(ID_PFR1_EL1) + +IDREG_START(ID_PFR2_EL1) + IDREG_FIELD(ID_PFR2_EL1, RAS_frac, 8, 4) + IDREG_FIELD(ID_PFR2_EL1, SSBS, 4, 4) + IDREG_FIELD(ID_PFR2_EL1, CSV3, 0, 4) +IDREG_END(ID_PFR2_EL1) + +IDREG_START(MIDR_EL1) + IDREG_FIELD(MIDR_EL1, Implementer, 24, 8) + IDREG_FIELD(MIDR_EL1, Variant, 20, 4) + IDREG_FIELD(MIDR_EL1, Architecture, 16, 4) + IDREG_FIELD(MIDR_EL1, PartNum, 4, 12) + IDREG_FIELD(MIDR_EL1, Revision, 0, 4) +IDREG_END(MIDR_EL1) + +IDREG_START(MPIDR_EL1) + IDREG_FIELD(MPIDR_EL1, Aff3, 32, 8) + IDREG_FIELD(MPIDR_EL1, U, 30, 1) + IDREG_FIELD(MPIDR_EL1, MT, 24, 1) + IDREG_FIELD(MPIDR_EL1, Aff2, 16, 8) + IDREG_FIELD(MPIDR_EL1, Aff1, 8, 8) + IDREG_FIELD(MPIDR_EL1, Aff0, 0, 8) +IDREG_END(MPIDR_EL1) + +IDREG_START(MVFR0_EL1) + IDREG_FIELD(MVFR0_EL1, FPRound, 28, 4) + IDREG_FIELD(MVFR0_EL1, FPShVec, 24, 4) + IDREG_FIELD(MVFR0_EL1, FPSqrt, 20, 4) + IDREG_FIELD(MVFR0_EL1, FPDivide, 16, 4) + IDREG_FIELD(MVFR0_EL1, FPTrap, 12, 4) + IDREG_FIELD(MVFR0_EL1, FPDP, 8, 4) + IDREG_FIELD(MVFR0_EL1, FPSP, 4, 4) + IDREG_FIELD(MVFR0_EL1, SIMDReg, 0, 4) +IDREG_END(MVFR0_EL1) + +IDREG_START(MVFR1_EL1) + IDREG_FIELD(MVFR1_EL1, SIMDFMAC, 28, 4) + IDREG_FIELD(MVFR1_EL1, FPHP, 24, 4) + IDREG_FIELD(MVFR1_EL1, SIMDHP, 20, 4) + IDREG_FIELD(MVFR1_EL1, SIMDSP, 16, 4) + IDREG_FIELD(MVFR1_EL1, SIMDInt, 12, 4) + IDREG_FIELD(MVFR1_EL1, SIMDLS, 8, 4) + IDREG_FIELD(MVFR1_EL1, FPDNaN, 4, 4) + IDREG_FIELD(MVFR1_EL1, FPFtZ, 0, 4) +IDREG_END(MVFR1_EL1) + +IDREG_START(MVFR2_EL1) + IDREG_FIELD(MVFR2_EL1, FPMisc, 4, 4) + IDREG_FIELD(MVFR2_EL1, SIMDMisc, 0, 4) +IDREG_END(MVFR2_EL1) + +IDREG_START(REVIDR_EL1) +IDREG_END(REVIDR_EL1) + +IDREG_START(SMIDR_EL1) + IDREG_FIELD(SMIDR_EL1, NSMC, 56, 4) + IDREG_FIELD(SMIDR_EL1, HIP, 52, 4) + IDREG_FIELD(SMIDR_EL1, Affinity2, 32, 20) + IDREG_FIELD(SMIDR_EL1, Implementer, 24, 8) + IDREG_FIELD(SMIDR_EL1, Revision, 16, 8) + IDREG_FIELD(SMIDR_EL1, SMPS, 15, 1) + IDREG_FIELD(SMIDR_EL1, SH, 13, 2) + IDREG_FIELD(SMIDR_EL1, Affinity, 0, 12) +IDREG_END(SMIDR_EL1) + --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1787737154; cv=none; d=zohomail.com; s=zohoarc; b=W5QDKTqw0O5Q8eANhHhISMq0WMVZK56/1d3vVJnZqOamoerrdMp8VwJX24fovjT4Qzwh7wIt5TCs7jwsfxKtXkxniGF2EeFHyjtq0Fey9rRTAvzEGHjm6YJkathBKEziPQLWTo3J20OC2d8PEWp0V4idt9CTbQswTMIuDfofdpM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787737154; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 08/20] target/arm/cpu-idregs.h.inc: Generate enum values Date: Wed, 26 Aug 2026 11:36:13 +0200 Message-ID: <20260826093747.1670077-9-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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1787737155532158500 Content-Type: text/plain; charset="utf-8" Modify the python script so that enum values are also extracted from Registers.json. If enum values are found, the field and its enum values are defined within IDREG_FIELD_START/END. Each enum value is defined with IDREG_FIELD_ARCH_VAL() macro. Signed-off-by: Eric Auger v7 -> v8: Properly handle ValueRange --- target/arm/cpu-idregs.h.inc | 2657 ++++++++++++++--- .../update-aarch64-cpu-sysreg-properties.py | 86 +- 2 files changed, 2332 insertions(+), 411 deletions(-) diff --git a/target/arm/cpu-idregs.h.inc b/target/arm/cpu-idregs.h.inc index c9745e2fb6..10ddfdf43a 100644 --- a/target/arm/cpu-idregs.h.inc +++ b/target/arm/cpu-idregs.h.inc @@ -4,7 +4,11 @@ =20 /* IDREG_START(REG) */ /* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */ +/* or for fields with enum values */ +/* IDREG_FIELD_START(REG, FIELD, SHIFT, LENGTH) */ +/* IDREG_FIELD_ARCH_VAL(VALUE) */ /* ... */ +/* IDREG_FIELD_END(REG, FIELD) */ /* IDREG_END(REG) */ =20 IDREG_START(AIDR_EL1) @@ -18,7 +22,16 @@ IDREG_START(CLIDR_EL1) IDREG_FIELD(CLIDR_EL1, Ttype3, 37, 2) IDREG_FIELD(CLIDR_EL1, Ttype2, 35, 2) IDREG_FIELD(CLIDR_EL1, Ttype1, 33, 2) - IDREG_FIELD(CLIDR_EL1, ICB, 30, 3) + IDREG_FIELD_START(CLIDR_EL1, ICB, 30, 3) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_END(CLIDR_EL1, ICB) IDREG_FIELD(CLIDR_EL1, LoUU, 27, 3) IDREG_FIELD(CLIDR_EL1, LoC, 24, 3) IDREG_FIELD(CLIDR_EL1, LoUIS, 21, 3) @@ -33,12 +46,23 @@ IDREG_END(CLIDR_EL1) =20 IDREG_START(CTR_EL0) IDREG_FIELD(CTR_EL0, TminLine, 32, 6) - IDREG_FIELD(CTR_EL0, DIC, 29, 1) - IDREG_FIELD(CTR_EL0, IDC, 28, 1) + IDREG_FIELD_START(CTR_EL0, DIC, 29, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(CTR_EL0, DIC) + IDREG_FIELD_START(CTR_EL0, IDC, 28, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(CTR_EL0, IDC) IDREG_FIELD(CTR_EL0, CWG, 24, 4) IDREG_FIELD(CTR_EL0, ERG, 20, 4) IDREG_FIELD(CTR_EL0, DminLine, 16, 4) - IDREG_FIELD(CTR_EL0, L1Ip, 14, 2) + IDREG_FIELD_START(CTR_EL0, L1Ip, 14, 2) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(CTR_EL0, L1Ip) IDREG_FIELD(CTR_EL0, IminLine, 0, 4) IDREG_END(CTR_EL0) =20 @@ -59,549 +83,2368 @@ IDREG_START(ID_AA64AFR1_EL1) IDREG_END(ID_AA64AFR1_EL1) =20 IDREG_START(ID_AA64DFR0_EL1) - IDREG_FIELD(ID_AA64DFR0_EL1, HPMN0, 60, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, ExtTrcBuff, 56, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, BRBE, 52, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, MTPMU, 48, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, TraceBuffer, 44, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, TraceFilt, 40, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, DoubleLock, 36, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, PMSVer, 32, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, WRPs, 20, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, PMSS, 16, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, BRPs, 12, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, PMUVer, 8, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, TraceVer, 4, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, DebugVer, 0, 4) + IDREG_FIELD_START(ID_AA64DFR0_EL1, HPMN0, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR0_EL1, HPMN0) + IDREG_FIELD_START(ID_AA64DFR0_EL1, ExtTrcBuff, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR0_EL1, ExtTrcBuff) + IDREG_FIELD_START(ID_AA64DFR0_EL1, BRBE, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64DFR0_EL1, BRBE) + IDREG_FIELD_START(ID_AA64DFR0_EL1, MTPMU, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64DFR0_EL1, MTPMU) + IDREG_FIELD_START(ID_AA64DFR0_EL1, TraceBuffer, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64DFR0_EL1, TraceBuffer) + IDREG_FIELD_START(ID_AA64DFR0_EL1, TraceFilt, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR0_EL1, TraceFilt) + IDREG_FIELD_START(ID_AA64DFR0_EL1, DoubleLock, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64DFR0_EL1, DoubleLock) + IDREG_FIELD_START(ID_AA64DFR0_EL1, PMSVer, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_END(ID_AA64DFR0_EL1, PMSVer) + IDREG_FIELD_START(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_ARCH_VAL(12) + IDREG_FIELD_ARCH_VAL(13) + IDREG_FIELD_ARCH_VAL(14) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64DFR0_EL1, CTX_CMPs) + IDREG_FIELD_START(ID_AA64DFR0_EL1, WRPs, 20, 4) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_ARCH_VAL(12) + IDREG_FIELD_ARCH_VAL(13) + IDREG_FIELD_ARCH_VAL(14) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64DFR0_EL1, WRPs) + IDREG_FIELD_START(ID_AA64DFR0_EL1, PMSS, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR0_EL1, PMSS) + IDREG_FIELD_START(ID_AA64DFR0_EL1, BRPs, 12, 4) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_ARCH_VAL(12) + IDREG_FIELD_ARCH_VAL(13) + IDREG_FIELD_ARCH_VAL(14) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64DFR0_EL1, BRPs) + IDREG_FIELD_START(ID_AA64DFR0_EL1, PMUVer, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64DFR0_EL1, PMUVer) + IDREG_FIELD_START(ID_AA64DFR0_EL1, TraceVer, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR0_EL1, TraceVer) + IDREG_FIELD_START(ID_AA64DFR0_EL1, DebugVer, 0, 4) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_END(ID_AA64DFR0_EL1, DebugVer) IDREG_END(ID_AA64DFR0_EL1) =20 IDREG_START(ID_AA64DFR1_EL1) - IDREG_FIELD(ID_AA64DFR1_EL1, ABL_CMPs, 56, 8) - IDREG_FIELD(ID_AA64DFR1_EL1, DPFZS, 52, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, EBEP, 48, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, ITE, 44, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, ABLE, 40, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, PMICNTR, 36, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, SPMU, 32, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, CTX_CMPs, 24, 8) - IDREG_FIELD(ID_AA64DFR1_EL1, WRPs, 16, 8) - IDREG_FIELD(ID_AA64DFR1_EL1, BRPs, 8, 8) - IDREG_FIELD(ID_AA64DFR1_EL1, SYSPMUID, 0, 8) + IDREG_FIELD_START(ID_AA64DFR1_EL1, ABL_CMPs, 56, 8) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_ARCH_VAL(12) + IDREG_FIELD_ARCH_VAL(13) + IDREG_FIELD_ARCH_VAL(14) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_ARCH_VAL(16) + IDREG_FIELD_ARCH_VAL(17) + IDREG_FIELD_ARCH_VAL(18) + IDREG_FIELD_ARCH_VAL(19) + IDREG_FIELD_ARCH_VAL(20) + IDREG_FIELD_ARCH_VAL(21) + IDREG_FIELD_ARCH_VAL(22) + IDREG_FIELD_ARCH_VAL(23) + IDREG_FIELD_ARCH_VAL(24) + IDREG_FIELD_ARCH_VAL(25) + IDREG_FIELD_ARCH_VAL(26) + IDREG_FIELD_ARCH_VAL(27) + IDREG_FIELD_ARCH_VAL(28) + IDREG_FIELD_ARCH_VAL(29) + IDREG_FIELD_ARCH_VAL(30) + IDREG_FIELD_ARCH_VAL(31) + IDREG_FIELD_ARCH_VAL(32) + IDREG_FIELD_ARCH_VAL(33) + IDREG_FIELD_ARCH_VAL(34) + IDREG_FIELD_ARCH_VAL(35) + IDREG_FIELD_ARCH_VAL(36) + IDREG_FIELD_ARCH_VAL(37) + IDREG_FIELD_ARCH_VAL(38) + IDREG_FIELD_ARCH_VAL(39) + IDREG_FIELD_ARCH_VAL(40) + IDREG_FIELD_ARCH_VAL(41) + IDREG_FIELD_ARCH_VAL(42) + IDREG_FIELD_ARCH_VAL(43) + IDREG_FIELD_ARCH_VAL(44) + IDREG_FIELD_ARCH_VAL(45) + IDREG_FIELD_ARCH_VAL(46) + IDREG_FIELD_ARCH_VAL(47) + IDREG_FIELD_ARCH_VAL(48) + IDREG_FIELD_ARCH_VAL(49) + IDREG_FIELD_ARCH_VAL(50) + IDREG_FIELD_ARCH_VAL(51) + IDREG_FIELD_ARCH_VAL(52) + IDREG_FIELD_ARCH_VAL(53) + IDREG_FIELD_ARCH_VAL(54) + IDREG_FIELD_ARCH_VAL(55) + IDREG_FIELD_ARCH_VAL(56) + IDREG_FIELD_ARCH_VAL(57) + IDREG_FIELD_ARCH_VAL(58) + IDREG_FIELD_ARCH_VAL(59) + IDREG_FIELD_ARCH_VAL(60) + IDREG_FIELD_ARCH_VAL(61) + IDREG_FIELD_ARCH_VAL(62) + IDREG_FIELD_ARCH_VAL(63) + IDREG_FIELD_END(ID_AA64DFR1_EL1, ABL_CMPs) + IDREG_FIELD_START(ID_AA64DFR1_EL1, DPFZS, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR1_EL1, DPFZS) + IDREG_FIELD_START(ID_AA64DFR1_EL1, EBEP, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR1_EL1, EBEP) + IDREG_FIELD_START(ID_AA64DFR1_EL1, ITE, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR1_EL1, ITE) + IDREG_FIELD_START(ID_AA64DFR1_EL1, ABLE, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR1_EL1, ABLE) + IDREG_FIELD_START(ID_AA64DFR1_EL1, PMICNTR, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR1_EL1, PMICNTR) + IDREG_FIELD_START(ID_AA64DFR1_EL1, SPMU, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64DFR1_EL1, SPMU) + IDREG_FIELD_START(ID_AA64DFR1_EL1, CTX_CMPs, 24, 8) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_ARCH_VAL(12) + IDREG_FIELD_ARCH_VAL(13) + IDREG_FIELD_ARCH_VAL(14) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_ARCH_VAL(16) + IDREG_FIELD_ARCH_VAL(17) + IDREG_FIELD_ARCH_VAL(18) + IDREG_FIELD_ARCH_VAL(19) + IDREG_FIELD_ARCH_VAL(20) + IDREG_FIELD_ARCH_VAL(21) + IDREG_FIELD_ARCH_VAL(22) + IDREG_FIELD_ARCH_VAL(23) + IDREG_FIELD_ARCH_VAL(24) + IDREG_FIELD_ARCH_VAL(25) + IDREG_FIELD_ARCH_VAL(26) + IDREG_FIELD_ARCH_VAL(27) + IDREG_FIELD_ARCH_VAL(28) + IDREG_FIELD_ARCH_VAL(29) + IDREG_FIELD_ARCH_VAL(30) + IDREG_FIELD_ARCH_VAL(31) + IDREG_FIELD_ARCH_VAL(32) + IDREG_FIELD_ARCH_VAL(33) + IDREG_FIELD_ARCH_VAL(34) + IDREG_FIELD_ARCH_VAL(35) + IDREG_FIELD_ARCH_VAL(36) + IDREG_FIELD_ARCH_VAL(37) + IDREG_FIELD_ARCH_VAL(38) + IDREG_FIELD_ARCH_VAL(39) + IDREG_FIELD_ARCH_VAL(40) + IDREG_FIELD_ARCH_VAL(41) + IDREG_FIELD_ARCH_VAL(42) + IDREG_FIELD_ARCH_VAL(43) + IDREG_FIELD_ARCH_VAL(44) + IDREG_FIELD_ARCH_VAL(45) + IDREG_FIELD_ARCH_VAL(46) + IDREG_FIELD_ARCH_VAL(47) + IDREG_FIELD_ARCH_VAL(48) + IDREG_FIELD_ARCH_VAL(49) + IDREG_FIELD_ARCH_VAL(50) + IDREG_FIELD_ARCH_VAL(51) + IDREG_FIELD_ARCH_VAL(52) + IDREG_FIELD_ARCH_VAL(53) + IDREG_FIELD_ARCH_VAL(54) + IDREG_FIELD_ARCH_VAL(55) + IDREG_FIELD_ARCH_VAL(56) + IDREG_FIELD_ARCH_VAL(57) + IDREG_FIELD_ARCH_VAL(58) + IDREG_FIELD_ARCH_VAL(59) + IDREG_FIELD_ARCH_VAL(60) + IDREG_FIELD_ARCH_VAL(61) + IDREG_FIELD_ARCH_VAL(62) + IDREG_FIELD_ARCH_VAL(63) + IDREG_FIELD_END(ID_AA64DFR1_EL1, CTX_CMPs) + IDREG_FIELD_START(ID_AA64DFR1_EL1, WRPs, 16, 8) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_ARCH_VAL(12) + IDREG_FIELD_ARCH_VAL(13) + IDREG_FIELD_ARCH_VAL(14) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_ARCH_VAL(16) + IDREG_FIELD_ARCH_VAL(17) + IDREG_FIELD_ARCH_VAL(18) + IDREG_FIELD_ARCH_VAL(19) + IDREG_FIELD_ARCH_VAL(20) + IDREG_FIELD_ARCH_VAL(21) + IDREG_FIELD_ARCH_VAL(22) + IDREG_FIELD_ARCH_VAL(23) + IDREG_FIELD_ARCH_VAL(24) + IDREG_FIELD_ARCH_VAL(25) + IDREG_FIELD_ARCH_VAL(26) + IDREG_FIELD_ARCH_VAL(27) + IDREG_FIELD_ARCH_VAL(28) + IDREG_FIELD_ARCH_VAL(29) + IDREG_FIELD_ARCH_VAL(30) + IDREG_FIELD_ARCH_VAL(31) + IDREG_FIELD_ARCH_VAL(32) + IDREG_FIELD_ARCH_VAL(33) + IDREG_FIELD_ARCH_VAL(34) + IDREG_FIELD_ARCH_VAL(35) + IDREG_FIELD_ARCH_VAL(36) + IDREG_FIELD_ARCH_VAL(37) + IDREG_FIELD_ARCH_VAL(38) + IDREG_FIELD_ARCH_VAL(39) + IDREG_FIELD_ARCH_VAL(40) + IDREG_FIELD_ARCH_VAL(41) + IDREG_FIELD_ARCH_VAL(42) + IDREG_FIELD_ARCH_VAL(43) + IDREG_FIELD_ARCH_VAL(44) + IDREG_FIELD_ARCH_VAL(45) + IDREG_FIELD_ARCH_VAL(46) + IDREG_FIELD_ARCH_VAL(47) + IDREG_FIELD_ARCH_VAL(48) + IDREG_FIELD_ARCH_VAL(49) + IDREG_FIELD_ARCH_VAL(50) + IDREG_FIELD_ARCH_VAL(51) + IDREG_FIELD_ARCH_VAL(52) + IDREG_FIELD_ARCH_VAL(53) + IDREG_FIELD_ARCH_VAL(54) + IDREG_FIELD_ARCH_VAL(55) + IDREG_FIELD_ARCH_VAL(56) + IDREG_FIELD_ARCH_VAL(57) + IDREG_FIELD_ARCH_VAL(58) + IDREG_FIELD_ARCH_VAL(59) + IDREG_FIELD_ARCH_VAL(60) + IDREG_FIELD_ARCH_VAL(61) + IDREG_FIELD_ARCH_VAL(62) + IDREG_FIELD_ARCH_VAL(63) + IDREG_FIELD_END(ID_AA64DFR1_EL1, WRPs) + IDREG_FIELD_START(ID_AA64DFR1_EL1, BRPs, 8, 8) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_ARCH_VAL(12) + IDREG_FIELD_ARCH_VAL(13) + IDREG_FIELD_ARCH_VAL(14) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_ARCH_VAL(16) + IDREG_FIELD_ARCH_VAL(17) + IDREG_FIELD_ARCH_VAL(18) + IDREG_FIELD_ARCH_VAL(19) + IDREG_FIELD_ARCH_VAL(20) + IDREG_FIELD_ARCH_VAL(21) + IDREG_FIELD_ARCH_VAL(22) + IDREG_FIELD_ARCH_VAL(23) + IDREG_FIELD_ARCH_VAL(24) + IDREG_FIELD_ARCH_VAL(25) + IDREG_FIELD_ARCH_VAL(26) + IDREG_FIELD_ARCH_VAL(27) + IDREG_FIELD_ARCH_VAL(28) + IDREG_FIELD_ARCH_VAL(29) + IDREG_FIELD_ARCH_VAL(30) + IDREG_FIELD_ARCH_VAL(31) + IDREG_FIELD_ARCH_VAL(32) + IDREG_FIELD_ARCH_VAL(33) + IDREG_FIELD_ARCH_VAL(34) + IDREG_FIELD_ARCH_VAL(35) + IDREG_FIELD_ARCH_VAL(36) + IDREG_FIELD_ARCH_VAL(37) + IDREG_FIELD_ARCH_VAL(38) + IDREG_FIELD_ARCH_VAL(39) + IDREG_FIELD_ARCH_VAL(40) + IDREG_FIELD_ARCH_VAL(41) + IDREG_FIELD_ARCH_VAL(42) + IDREG_FIELD_ARCH_VAL(43) + IDREG_FIELD_ARCH_VAL(44) + IDREG_FIELD_ARCH_VAL(45) + IDREG_FIELD_ARCH_VAL(46) + IDREG_FIELD_ARCH_VAL(47) + IDREG_FIELD_ARCH_VAL(48) + IDREG_FIELD_ARCH_VAL(49) + IDREG_FIELD_ARCH_VAL(50) + IDREG_FIELD_ARCH_VAL(51) + IDREG_FIELD_ARCH_VAL(52) + IDREG_FIELD_ARCH_VAL(53) + IDREG_FIELD_ARCH_VAL(54) + IDREG_FIELD_ARCH_VAL(55) + IDREG_FIELD_ARCH_VAL(56) + IDREG_FIELD_ARCH_VAL(57) + IDREG_FIELD_ARCH_VAL(58) + IDREG_FIELD_ARCH_VAL(59) + IDREG_FIELD_ARCH_VAL(60) + IDREG_FIELD_ARCH_VAL(61) + IDREG_FIELD_ARCH_VAL(62) + IDREG_FIELD_ARCH_VAL(63) + IDREG_FIELD_END(ID_AA64DFR1_EL1, BRPs) + IDREG_FIELD_START(ID_AA64DFR1_EL1, SYSPMUID, 0, 8) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_ARCH_VAL(12) + IDREG_FIELD_ARCH_VAL(13) + IDREG_FIELD_ARCH_VAL(14) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_ARCH_VAL(16) + IDREG_FIELD_ARCH_VAL(17) + IDREG_FIELD_ARCH_VAL(18) + IDREG_FIELD_ARCH_VAL(19) + IDREG_FIELD_ARCH_VAL(20) + IDREG_FIELD_ARCH_VAL(21) + IDREG_FIELD_ARCH_VAL(22) + IDREG_FIELD_ARCH_VAL(23) + IDREG_FIELD_ARCH_VAL(24) + IDREG_FIELD_ARCH_VAL(25) + IDREG_FIELD_ARCH_VAL(26) + IDREG_FIELD_ARCH_VAL(27) + IDREG_FIELD_ARCH_VAL(28) + IDREG_FIELD_ARCH_VAL(29) + IDREG_FIELD_ARCH_VAL(30) + IDREG_FIELD_ARCH_VAL(31) + IDREG_FIELD_END(ID_AA64DFR1_EL1, SYSPMUID) IDREG_END(ID_AA64DFR1_EL1) =20 IDREG_START(ID_AA64DFR2_EL1) - IDREG_FIELD(ID_AA64DFR2_EL1, TRBE_EXC, 24, 4) - IDREG_FIELD(ID_AA64DFR2_EL1, SPE_nVM, 20, 4) - IDREG_FIELD(ID_AA64DFR2_EL1, SPE_EXC, 16, 4) - IDREG_FIELD(ID_AA64DFR2_EL1, BWE, 4, 4) - IDREG_FIELD(ID_AA64DFR2_EL1, STEP, 0, 4) + IDREG_FIELD_START(ID_AA64DFR2_EL1, TRBE_EXC, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR2_EL1, TRBE_EXC) + IDREG_FIELD_START(ID_AA64DFR2_EL1, SPE_nVM, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR2_EL1, SPE_nVM) + IDREG_FIELD_START(ID_AA64DFR2_EL1, SPE_EXC, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR2_EL1, SPE_EXC) + IDREG_FIELD_START(ID_AA64DFR2_EL1, BWE, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64DFR2_EL1, BWE) + IDREG_FIELD_START(ID_AA64DFR2_EL1, STEP, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR2_EL1, STEP) IDREG_END(ID_AA64DFR2_EL1) =20 IDREG_START(ID_AA64FPFR0_EL1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8CVT, 31, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8FMA, 30, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP4, 29, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP2, 28, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM8, 27, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM4, 26, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F16MM2, 15, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8E4M3, 1, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8E5M2, 0, 1) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8CVT, 31, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8CVT) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8FMA, 30, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8FMA) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8DP4, 29, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8DP4) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8DP2, 28, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8DP2) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8MM8, 27, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8MM8) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8MM4, 26, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8MM4) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F16MM2, 15, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F16MM2) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8E4M3, 1, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8E4M3) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8E5M2, 0, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8E5M2) IDREG_END(ID_AA64FPFR0_EL1) =20 IDREG_START(ID_AA64ISAR0_EL1) - IDREG_FIELD(ID_AA64ISAR0_EL1, RNDR, 60, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, TLB, 56, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, TS, 52, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, FHM, 48, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, DP, 44, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SM4, 40, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SM3, 36, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SHA3, 32, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, RDM, 28, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, Atomic, 20, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, CRC32, 16, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SHA2, 12, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SHA1, 8, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, AES, 4, 4) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, RNDR, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, RNDR) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, TLB, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, TLB) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, TS, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, TS) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, FHM, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, FHM) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, DP, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, DP) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, SM4, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, SM4) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, SM3, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, SM3) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, SHA3, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, SHA3) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, RDM, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, RDM) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, Atomic, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, Atomic) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, CRC32, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, CRC32) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, SHA2, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, SHA2) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, SHA1, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, SHA1) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, AES, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, AES) IDREG_END(ID_AA64ISAR0_EL1) =20 IDREG_START(ID_AA64ISAR1_EL1) - IDREG_FIELD(ID_AA64ISAR1_EL1, LS64, 60, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, XS, 56, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, I8MM, 52, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, DGH, 48, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, BF16, 44, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, SPECRES, 40, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, SB, 36, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, FRINTTS, 32, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, GPI, 28, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, GPA, 24, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, LRCPC, 20, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, FCMA, 16, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, JSCVT, 12, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, API, 8, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, APA, 4, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, DPB, 0, 4) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, LS64, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, LS64) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, XS, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, XS) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, I8MM, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, I8MM) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, DGH, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, DGH) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, BF16, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, BF16) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, SPECRES, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, SPECRES) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, SB, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, SB) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, FRINTTS, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, FRINTTS) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, GPI, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, GPI) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, GPA, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, GPA) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, LRCPC, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, LRCPC) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, FCMA, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, FCMA) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, JSCVT, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, JSCVT) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, API, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, API) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, APA, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, APA) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, DPB, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, DPB) IDREG_END(ID_AA64ISAR1_EL1) =20 IDREG_START(ID_AA64ISAR2_EL1) - IDREG_FIELD(ID_AA64ISAR2_EL1, ATS1A, 60, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, LUT, 56, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, CSSC, 52, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, RPRFM, 48, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, PCDPHINT, 44, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, PRFMSLC, 40, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, SYSINSTR_128, 36, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, SYSREG_128, 32, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, CLRBHB, 28, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, PAC_frac, 24, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, BC, 20, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, MOPS, 16, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, APA3, 12, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, GPA3, 8, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, RPRES, 4, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, WFxT, 0, 4) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, ATS1A, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, ATS1A) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, LUT, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, LUT) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, CSSC, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, CSSC) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, RPRFM, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, RPRFM) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, PCDPHINT, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, PCDPHINT) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, PRFMSLC, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, PRFMSLC) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, SYSINSTR_128, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, SYSINSTR_128) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, SYSREG_128, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, SYSREG_128) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, CLRBHB, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, CLRBHB) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, PAC_frac, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, PAC_frac) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, BC, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, BC) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, MOPS, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, MOPS) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, APA3, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, APA3) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, GPA3, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, GPA3) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, RPRES, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, RPRES) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, WFxT, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, WFxT) IDREG_END(ID_AA64ISAR2_EL1) =20 IDREG_START(ID_AA64ISAR3_EL1) - IDREG_FIELD(ID_AA64ISAR3_EL1, LSCP, 44, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, LSCSHINT, 40, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, MTETC, 36, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, PAC_frac2, 32, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, FPRCVT, 28, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, LSUI, 24, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, OCCMO, 20, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, LSFE, 16, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, PACM, 12, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, TLBIW, 8, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, FAMINMAX, 4, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, CPA, 0, 4) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, LSCP, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, LSCP) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, LSCSHINT, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, LSCSHINT) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, MTETC, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, MTETC) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, PAC_frac2, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, PAC_frac2) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, FPRCVT, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, FPRCVT) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, LSUI, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, LSUI) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, OCCMO, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, OCCMO) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, LSFE, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, LSFE) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, PACM, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, PACM) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, TLBIW, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, TLBIW) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, FAMINMAX, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, FAMINMAX) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, CPA, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, CPA) IDREG_END(ID_AA64ISAR3_EL1) =20 IDREG_START(ID_AA64MMFR0_EL1) - IDREG_FIELD(ID_AA64MMFR0_EL1, ECV, 60, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, FGT, 56, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, ExS, 44, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4_2, 40, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64_2, 36, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16_2, 32, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4, 28, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64, 24, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16, 20, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, BigEndEL0, 16, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, SNSMem, 12, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, BigEnd, 8, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, ASIDBits, 4, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, PARange, 0, 4) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, ECV, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, ECV) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, FGT, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, FGT) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, ExS, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, ExS) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, TGran4_2, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, TGran4_2) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, TGran64_2, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, TGran64_2) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, TGran16_2, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, TGran16_2) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, TGran4, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, TGran4) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, TGran64, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, TGran64) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, TGran16, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, TGran16) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, BigEndEL0, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, BigEndEL0) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, SNSMem, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, SNSMem) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, BigEnd, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, BigEnd) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, ASIDBits, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, ASIDBits) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, PARange, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, PARange) IDREG_END(ID_AA64MMFR0_EL1) =20 IDREG_START(ID_AA64MMFR1_EL1) - IDREG_FIELD(ID_AA64MMFR1_EL1, ECBHB, 60, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, CMOW, 56, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, TIDCP1, 52, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, nTLBPA, 48, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, AFP, 44, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, HCX, 40, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, ETS, 36, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, TWED, 32, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, XNX, 28, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, SpecSEI, 24, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, PAN, 20, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, LO, 16, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, HPDS, 12, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, VH, 8, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, VMIDBits, 4, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, HAFDBS, 0, 4) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, ECBHB, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, ECBHB) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, CMOW, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, CMOW) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, TIDCP1, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, TIDCP1) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, nTLBPA, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, nTLBPA) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, AFP, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, AFP) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, HCX, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, HCX) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, ETS, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, ETS) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, TWED, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, TWED) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, XNX, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, XNX) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, SpecSEI, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, SpecSEI) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, PAN, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, PAN) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, LO, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, LO) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, HPDS, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, HPDS) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, VH, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, VH) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, VMIDBits, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, VMIDBits) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, HAFDBS, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, HAFDBS) IDREG_END(ID_AA64MMFR1_EL1) =20 IDREG_START(ID_AA64MMFR2_EL1) - IDREG_FIELD(ID_AA64MMFR2_EL1, E0PD, 60, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, EVT, 56, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, BBM, 52, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, TTL, 48, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, FWB, 40, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, IDS, 36, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, AT, 32, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, ST, 28, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, NV, 24, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, CCIDX, 20, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, VARange, 16, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, IESB, 12, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, LSM, 8, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, UAO, 4, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, CnP, 0, 4) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, E0PD, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, E0PD) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, EVT, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, EVT) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, BBM, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, BBM) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, TTL, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, TTL) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, FWB, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, FWB) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, IDS, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, IDS) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, AT, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, AT) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, ST, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, ST) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, NV, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, NV) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, CCIDX, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, CCIDX) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, VARange, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, VARange) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, IESB, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, IESB) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, LSM, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, LSM) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, UAO, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, UAO) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, CnP, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, CnP) IDREG_END(ID_AA64MMFR2_EL1) =20 IDREG_START(ID_AA64MMFR3_EL1) - IDREG_FIELD(ID_AA64MMFR3_EL1, Spec_FPACC, 60, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, ADERR, 56, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, SDERR, 52, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, ANERR, 44, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, SNERR, 40, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, D128_2, 36, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, D128, 32, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, MEC, 28, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, AIE, 24, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, S2POE, 20, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, S1POE, 16, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, S2PIE, 12, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, S1PIE, 8, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, SCTLRX, 4, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, TCRX, 0, 4) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, Spec_FPACC, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, Spec_FPACC) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, ADERR, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, ADERR) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, SDERR, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, SDERR) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, ANERR, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, ANERR) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, SNERR, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, SNERR) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, D128_2, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, D128_2) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, D128, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, D128) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, MEC, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, MEC) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, AIE, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, AIE) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, S2POE, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, S2POE) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, S1POE, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, S1POE) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, S2PIE, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, S2PIE) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, S1PIE, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, S1PIE) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, SCTLRX, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, SCTLRX) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, TCRX, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, TCRX) IDREG_END(ID_AA64MMFR3_EL1) =20 IDREG_START(ID_AA64MMFR4_EL1) - IDREG_FIELD(ID_AA64MMFR4_EL1, MTEFGT, 60, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, SCRX, 56, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, TEV, 52, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, TPS, 48, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, SRMASK, 44, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, TLBID, 40, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, E3DSE, 36, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, EAESR, 32, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, RMEGDI, 28, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, E2H0, 24, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, NV_frac, 20, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, FGWTE3, 16, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, HACDBS, 12, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, ASID2, 8, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, EIESB, 4, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, PoPS, 0, 4) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, MTEFGT, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, MTEFGT) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, SCRX, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, SCRX) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, TEV, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, TEV) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, TPS, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, TPS) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, SRMASK, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, SRMASK) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, TLBID, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, TLBID) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, E3DSE, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, E3DSE) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, EAESR, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, EAESR) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, RMEGDI, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, RMEGDI) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, E2H0, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(14) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, E2H0) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, NV_frac, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, NV_frac) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, FGWTE3, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, FGWTE3) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, HACDBS, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, HACDBS) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, ASID2, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, ASID2) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, EIESB, 4, 4) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, EIESB) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, PoPS, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, PoPS) IDREG_END(ID_AA64MMFR4_EL1) =20 IDREG_START(ID_AA64PFR0_EL1) - IDREG_FIELD(ID_AA64PFR0_EL1, CSV3, 60, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, CSV2, 56, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, RME, 52, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, DIT, 48, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, AMU, 44, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, MPAM, 40, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, SEL2, 36, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, SVE, 32, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, RAS, 28, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, GIC, 24, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, AdvSIMD, 20, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, FP, 16, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, EL3, 12, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, EL2, 8, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, EL1, 4, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, EL0, 0, 4) + IDREG_FIELD_START(ID_AA64PFR0_EL1, CSV3, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR0_EL1, CSV3) + IDREG_FIELD_START(ID_AA64PFR0_EL1, CSV2, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64PFR0_EL1, CSV2) + IDREG_FIELD_START(ID_AA64PFR0_EL1, RME, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64PFR0_EL1, RME) + IDREG_FIELD_START(ID_AA64PFR0_EL1, DIT, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR0_EL1, DIT) + IDREG_FIELD_START(ID_AA64PFR0_EL1, AMU, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR0_EL1, AMU) + IDREG_FIELD_START(ID_AA64PFR0_EL1, MPAM, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR0_EL1, MPAM) + IDREG_FIELD_START(ID_AA64PFR0_EL1, SEL2, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR0_EL1, SEL2) + IDREG_FIELD_START(ID_AA64PFR0_EL1, SVE, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR0_EL1, SVE) + IDREG_FIELD_START(ID_AA64PFR0_EL1, RAS, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64PFR0_EL1, RAS) + IDREG_FIELD_START(ID_AA64PFR0_EL1, GIC, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64PFR0_EL1, GIC) + IDREG_FIELD_START(ID_AA64PFR0_EL1, AdvSIMD, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64PFR0_EL1, AdvSIMD) + IDREG_FIELD_START(ID_AA64PFR0_EL1, FP, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64PFR0_EL1, FP) + IDREG_FIELD_START(ID_AA64PFR0_EL1, EL3, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR0_EL1, EL3) + IDREG_FIELD_START(ID_AA64PFR0_EL1, EL2, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR0_EL1, EL2) + IDREG_FIELD_START(ID_AA64PFR0_EL1, EL1, 4, 4) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR0_EL1, EL1) + IDREG_FIELD_START(ID_AA64PFR0_EL1, EL0, 0, 4) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR0_EL1, EL0) IDREG_END(ID_AA64PFR0_EL1) =20 IDREG_START(ID_AA64PFR1_EL1) - IDREG_FIELD(ID_AA64PFR1_EL1, PFAR, 60, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, DF2, 56, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, MTEX, 52, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, THE, 48, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, GCS, 44, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, MTE_frac, 40, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, NMI, 36, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, CSV2_frac, 32, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, RNDR_trap, 28, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, SME, 24, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, MPAM_frac, 16, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, RAS_frac, 12, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, MTE, 8, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, SSBS, 4, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, BT, 0, 4) + IDREG_FIELD_START(ID_AA64PFR1_EL1, PFAR, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, PFAR) + IDREG_FIELD_START(ID_AA64PFR1_EL1, DF2, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, DF2) + IDREG_FIELD_START(ID_AA64PFR1_EL1, MTEX, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, MTEX) + IDREG_FIELD_START(ID_AA64PFR1_EL1, THE, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, THE) + IDREG_FIELD_START(ID_AA64PFR1_EL1, GCS, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, GCS) + IDREG_FIELD_START(ID_AA64PFR1_EL1, MTE_frac, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64PFR1_EL1, MTE_frac) + IDREG_FIELD_START(ID_AA64PFR1_EL1, NMI, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, NMI) + IDREG_FIELD_START(ID_AA64PFR1_EL1, CSV2_frac, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR1_EL1, CSV2_frac) + IDREG_FIELD_START(ID_AA64PFR1_EL1, RNDR_trap, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, RNDR_trap) + IDREG_FIELD_START(ID_AA64PFR1_EL1, SME, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR1_EL1, SME) + IDREG_FIELD_START(ID_AA64PFR1_EL1, MPAM_frac, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, MPAM_frac) + IDREG_FIELD_START(ID_AA64PFR1_EL1, RAS_frac, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, RAS_frac) + IDREG_FIELD_START(ID_AA64PFR1_EL1, MTE, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64PFR1_EL1, MTE) + IDREG_FIELD_START(ID_AA64PFR1_EL1, SSBS, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR1_EL1, SSBS) + IDREG_FIELD_START(ID_AA64PFR1_EL1, BT, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR1_EL1, BT) IDREG_END(ID_AA64PFR1_EL1) =20 IDREG_START(ID_AA64PFR2_EL1) - IDREG_FIELD(ID_AA64PFR2_EL1, VMTETCL, 44, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, VMTETC, 40, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, VMTE, 36, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, FPMR, 32, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MPAM2, 28, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, FGDT, 24, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MTEEIRG, 20, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, UINJ, 16, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, GCIE, 12, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MTEFAR, 8, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MTESTOREONLY, 4, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MTEPERM, 0, 4) + IDREG_FIELD_START(ID_AA64PFR2_EL1, VMTETCL, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, VMTETCL) + IDREG_FIELD_START(ID_AA64PFR2_EL1, VMTETC, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64PFR2_EL1, VMTETC) + IDREG_FIELD_START(ID_AA64PFR2_EL1, VMTE, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR2_EL1, VMTE) + IDREG_FIELD_START(ID_AA64PFR2_EL1, FPMR, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, FPMR) + IDREG_FIELD_START(ID_AA64PFR2_EL1, MPAM2, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, MPAM2) + IDREG_FIELD_START(ID_AA64PFR2_EL1, FGDT, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR2_EL1, FGDT) + IDREG_FIELD_START(ID_AA64PFR2_EL1, MTEEIRG, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, MTEEIRG) + IDREG_FIELD_START(ID_AA64PFR2_EL1, UINJ, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, UINJ) + IDREG_FIELD_START(ID_AA64PFR2_EL1, GCIE, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, GCIE) + IDREG_FIELD_START(ID_AA64PFR2_EL1, MTEFAR, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, MTEFAR) + IDREG_FIELD_START(ID_AA64PFR2_EL1, MTESTOREONLY, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, MTESTOREONLY) + IDREG_FIELD_START(ID_AA64PFR2_EL1, MTEPERM, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, MTEPERM) IDREG_END(ID_AA64PFR2_EL1) =20 IDREG_START(ID_AA64SMFR0_EL1) - IDREG_FIELD(ID_AA64SMFR0_EL1, FA64, 63, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, LUT6, 61, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, LUTv2, 60, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SMEver, 56, 4) - IDREG_FIELD(ID_AA64SMFR0_EL1, I16I64, 52, 4) - IDREG_FIELD(ID_AA64SMFR0_EL1, F64F64, 48, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, I16I32, 44, 4) - IDREG_FIELD(ID_AA64SMFR0_EL1, B16B16, 43, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, F16F16, 42, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, F8F16, 41, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, F8F32, 40, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, I8I32, 36, 4) - IDREG_FIELD(ID_AA64SMFR0_EL1, F16F32, 35, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, B16F32, 34, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, BI32I32, 33, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, F32F32, 32, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SF8FMA, 30, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP4, 29, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP2, 28, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SBitPerm, 25, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, AES, 24, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SFEXPA, 23, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, STMOP, 16, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SMOP4, 0, 1) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, FA64, 63, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, FA64) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, LUT6, 61, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, LUT6) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, LUTv2, 60, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, LUTv2) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SMEver, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SMEver) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, I16I64, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, I16I64) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, F64F64, 48, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, F64F64) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, I16I32, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, I16I32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, B16B16, 43, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, B16B16) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, F16F16, 42, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, F16F16) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, F8F16, 41, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, F8F16) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, F8F32, 40, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, F8F32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, I8I32, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, I8I32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, F16F32, 35, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, F16F32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, B16F32, 34, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, B16F32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, BI32I32, 33, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, BI32I32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, F32F32, 32, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, F32F32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SF8FMA, 30, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SF8FMA) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SF8DP4, 29, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SF8DP4) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SF8DP2, 28, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SF8DP2) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SBitPerm, 25, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SBitPerm) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, AES, 24, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, AES) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SFEXPA, 23, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SFEXPA) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, STMOP, 16, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, STMOP) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SMOP4, 0, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SMOP4) IDREG_END(ID_AA64SMFR0_EL1) =20 IDREG_START(ID_AA64ZFR0_EL1) - IDREG_FIELD(ID_AA64ZFR0_EL1, F64MM, 56, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, F32MM, 52, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, F16MM, 48, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, I8MM, 44, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, SM4, 40, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, SHA3, 32, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, B16B16, 24, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, BF16, 20, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, BitPerm, 16, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, EltPerm, 12, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, AES, 4, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, SVEver, 0, 4) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, F64MM, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, F64MM) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, F32MM, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, F32MM) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, F16MM, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, F16MM) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, I8MM, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, I8MM) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, SM4, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, SM4) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, SHA3, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, SHA3) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, B16B16, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, B16B16) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, BF16, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, BF16) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, BitPerm, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, BitPerm) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, EltPerm, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, EltPerm) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, AES, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, AES) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, SVEver, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, SVEver) IDREG_END(ID_AA64ZFR0_EL1) =20 IDREG_START(ID_AFR0_EL1) IDREG_END(ID_AFR0_EL1) =20 IDREG_START(ID_DFR0_EL1) - IDREG_FIELD(ID_DFR0_EL1, TraceFilt, 28, 4) - IDREG_FIELD(ID_DFR0_EL1, PerfMon, 24, 4) - IDREG_FIELD(ID_DFR0_EL1, MProfDbg, 20, 4) - IDREG_FIELD(ID_DFR0_EL1, MMapTrc, 16, 4) - IDREG_FIELD(ID_DFR0_EL1, CopTrc, 12, 4) - IDREG_FIELD(ID_DFR0_EL1, MMapDbg, 8, 4) + IDREG_FIELD_START(ID_DFR0_EL1, TraceFilt, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_DFR0_EL1, TraceFilt) + IDREG_FIELD_START(ID_DFR0_EL1, PerfMon, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_DFR0_EL1, PerfMon) + IDREG_FIELD_START(ID_DFR0_EL1, MProfDbg, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_DFR0_EL1, MProfDbg) + IDREG_FIELD_START(ID_DFR0_EL1, MMapTrc, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_DFR0_EL1, MMapTrc) + IDREG_FIELD_START(ID_DFR0_EL1, CopTrc, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_DFR0_EL1, CopTrc) + IDREG_FIELD_START(ID_DFR0_EL1, MMapDbg, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_END(ID_DFR0_EL1, MMapDbg) IDREG_FIELD(ID_DFR0_EL1, CopSDbg, 4, 4) - IDREG_FIELD(ID_DFR0_EL1, CopDbg, 0, 4) + IDREG_FIELD_START(ID_DFR0_EL1, CopDbg, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_END(ID_DFR0_EL1, CopDbg) IDREG_END(ID_DFR0_EL1) =20 IDREG_START(ID_DFR1_EL1) - IDREG_FIELD(ID_DFR1_EL1, HPMN0, 4, 4) - IDREG_FIELD(ID_DFR1_EL1, MTPMU, 0, 4) + IDREG_FIELD_START(ID_DFR1_EL1, HPMN0, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_DFR1_EL1, HPMN0) + IDREG_FIELD_START(ID_DFR1_EL1, MTPMU, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_DFR1_EL1, MTPMU) IDREG_END(ID_DFR1_EL1) =20 IDREG_START(ID_ISAR0_EL1) - IDREG_FIELD(ID_ISAR0_EL1, Divide, 24, 4) - IDREG_FIELD(ID_ISAR0_EL1, Debug, 20, 4) - IDREG_FIELD(ID_ISAR0_EL1, Coproc, 16, 4) - IDREG_FIELD(ID_ISAR0_EL1, CmpBranch, 12, 4) - IDREG_FIELD(ID_ISAR0_EL1, BitField, 8, 4) - IDREG_FIELD(ID_ISAR0_EL1, BitCount, 4, 4) - IDREG_FIELD(ID_ISAR0_EL1, Swap, 0, 4) + IDREG_FIELD_START(ID_ISAR0_EL1, Divide, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR0_EL1, Divide) + IDREG_FIELD_START(ID_ISAR0_EL1, Debug, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR0_EL1, Debug) + IDREG_FIELD_START(ID_ISAR0_EL1, Coproc, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_ISAR0_EL1, Coproc) + IDREG_FIELD_START(ID_ISAR0_EL1, CmpBranch, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR0_EL1, CmpBranch) + IDREG_FIELD_START(ID_ISAR0_EL1, BitField, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR0_EL1, BitField) + IDREG_FIELD_START(ID_ISAR0_EL1, BitCount, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR0_EL1, BitCount) + IDREG_FIELD_START(ID_ISAR0_EL1, Swap, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR0_EL1, Swap) IDREG_END(ID_ISAR0_EL1) =20 IDREG_START(ID_ISAR1_EL1) - IDREG_FIELD(ID_ISAR1_EL1, Jazelle, 28, 4) - IDREG_FIELD(ID_ISAR1_EL1, Interwork, 24, 4) - IDREG_FIELD(ID_ISAR1_EL1, Immediate, 20, 4) - IDREG_FIELD(ID_ISAR1_EL1, IfThen, 16, 4) - IDREG_FIELD(ID_ISAR1_EL1, Extend, 12, 4) - IDREG_FIELD(ID_ISAR1_EL1, Except_AR, 8, 4) - IDREG_FIELD(ID_ISAR1_EL1, Except, 4, 4) - IDREG_FIELD(ID_ISAR1_EL1, Endian, 0, 4) + IDREG_FIELD_START(ID_ISAR1_EL1, Jazelle, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR1_EL1, Jazelle) + IDREG_FIELD_START(ID_ISAR1_EL1, Interwork, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_ISAR1_EL1, Interwork) + IDREG_FIELD_START(ID_ISAR1_EL1, Immediate, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR1_EL1, Immediate) + IDREG_FIELD_START(ID_ISAR1_EL1, IfThen, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR1_EL1, IfThen) + IDREG_FIELD_START(ID_ISAR1_EL1, Extend, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR1_EL1, Extend) + IDREG_FIELD_START(ID_ISAR1_EL1, Except_AR, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR1_EL1, Except_AR) + IDREG_FIELD_START(ID_ISAR1_EL1, Except, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR1_EL1, Except) + IDREG_FIELD_START(ID_ISAR1_EL1, Endian, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR1_EL1, Endian) IDREG_END(ID_ISAR1_EL1) =20 IDREG_START(ID_ISAR2_EL1) - IDREG_FIELD(ID_ISAR2_EL1, Reversal, 28, 4) - IDREG_FIELD(ID_ISAR2_EL1, PSR_AR, 24, 4) - IDREG_FIELD(ID_ISAR2_EL1, MultU, 20, 4) - IDREG_FIELD(ID_ISAR2_EL1, MultS, 16, 4) - IDREG_FIELD(ID_ISAR2_EL1, Mult, 12, 4) - IDREG_FIELD(ID_ISAR2_EL1, MultiAccessInt, 8, 4) - IDREG_FIELD(ID_ISAR2_EL1, MemHint, 4, 4) - IDREG_FIELD(ID_ISAR2_EL1, LoadStore, 0, 4) + IDREG_FIELD_START(ID_ISAR2_EL1, Reversal, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR2_EL1, Reversal) + IDREG_FIELD_START(ID_ISAR2_EL1, PSR_AR, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR2_EL1, PSR_AR) + IDREG_FIELD_START(ID_ISAR2_EL1, MultU, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR2_EL1, MultU) + IDREG_FIELD_START(ID_ISAR2_EL1, MultS, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_ISAR2_EL1, MultS) + IDREG_FIELD_START(ID_ISAR2_EL1, Mult, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR2_EL1, Mult) + IDREG_FIELD_START(ID_ISAR2_EL1, MultiAccessInt, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR2_EL1, MultiAccessInt) + IDREG_FIELD_START(ID_ISAR2_EL1, MemHint, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_ISAR2_EL1, MemHint) + IDREG_FIELD_START(ID_ISAR2_EL1, LoadStore, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR2_EL1, LoadStore) IDREG_END(ID_ISAR2_EL1) =20 IDREG_START(ID_ISAR3_EL1) - IDREG_FIELD(ID_ISAR3_EL1, T32EE, 28, 4) - IDREG_FIELD(ID_ISAR3_EL1, TrueNOP, 24, 4) - IDREG_FIELD(ID_ISAR3_EL1, T32Copy, 20, 4) - IDREG_FIELD(ID_ISAR3_EL1, TabBranch, 16, 4) - IDREG_FIELD(ID_ISAR3_EL1, SynchPrim, 12, 4) - IDREG_FIELD(ID_ISAR3_EL1, SVC, 8, 4) - IDREG_FIELD(ID_ISAR3_EL1, SIMD, 4, 4) - IDREG_FIELD(ID_ISAR3_EL1, Saturate, 0, 4) + IDREG_FIELD_START(ID_ISAR3_EL1, T32EE, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR3_EL1, T32EE) + IDREG_FIELD_START(ID_ISAR3_EL1, TrueNOP, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR3_EL1, TrueNOP) + IDREG_FIELD_START(ID_ISAR3_EL1, T32Copy, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR3_EL1, T32Copy) + IDREG_FIELD_START(ID_ISAR3_EL1, TabBranch, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR3_EL1, TabBranch) + IDREG_FIELD_START(ID_ISAR3_EL1, SynchPrim, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR3_EL1, SynchPrim) + IDREG_FIELD_START(ID_ISAR3_EL1, SVC, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR3_EL1, SVC) + IDREG_FIELD_START(ID_ISAR3_EL1, SIMD, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_ISAR3_EL1, SIMD) + IDREG_FIELD_START(ID_ISAR3_EL1, Saturate, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR3_EL1, Saturate) IDREG_END(ID_ISAR3_EL1) =20 IDREG_START(ID_ISAR4_EL1) - IDREG_FIELD(ID_ISAR4_EL1, SWP_frac, 28, 4) - IDREG_FIELD(ID_ISAR4_EL1, PSR_M, 24, 4) - IDREG_FIELD(ID_ISAR4_EL1, SynchPrim_frac, 20, 4) - IDREG_FIELD(ID_ISAR4_EL1, Barrier, 16, 4) - IDREG_FIELD(ID_ISAR4_EL1, SMC, 12, 4) - IDREG_FIELD(ID_ISAR4_EL1, Writeback, 8, 4) - IDREG_FIELD(ID_ISAR4_EL1, WithShifts, 4, 4) - IDREG_FIELD(ID_ISAR4_EL1, Unpriv, 0, 4) + IDREG_FIELD_START(ID_ISAR4_EL1, SWP_frac, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR4_EL1, SWP_frac) + IDREG_FIELD_START(ID_ISAR4_EL1, PSR_M, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR4_EL1, PSR_M) + IDREG_FIELD_START(ID_ISAR4_EL1, SynchPrim_frac, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_ISAR4_EL1, SynchPrim_frac) + IDREG_FIELD_START(ID_ISAR4_EL1, Barrier, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR4_EL1, Barrier) + IDREG_FIELD_START(ID_ISAR4_EL1, SMC, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR4_EL1, SMC) + IDREG_FIELD_START(ID_ISAR4_EL1, Writeback, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR4_EL1, Writeback) + IDREG_FIELD_START(ID_ISAR4_EL1, WithShifts, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_ISAR4_EL1, WithShifts) + IDREG_FIELD_START(ID_ISAR4_EL1, Unpriv, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR4_EL1, Unpriv) IDREG_END(ID_ISAR4_EL1) =20 IDREG_START(ID_ISAR5_EL1) - IDREG_FIELD(ID_ISAR5_EL1, VCMA, 28, 4) - IDREG_FIELD(ID_ISAR5_EL1, RDM, 24, 4) - IDREG_FIELD(ID_ISAR5_EL1, CRC32, 16, 4) - IDREG_FIELD(ID_ISAR5_EL1, SHA2, 12, 4) - IDREG_FIELD(ID_ISAR5_EL1, SHA1, 8, 4) - IDREG_FIELD(ID_ISAR5_EL1, AES, 4, 4) - IDREG_FIELD(ID_ISAR5_EL1, SEVL, 0, 4) + IDREG_FIELD_START(ID_ISAR5_EL1, VCMA, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR5_EL1, VCMA) + IDREG_FIELD_START(ID_ISAR5_EL1, RDM, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR5_EL1, RDM) + IDREG_FIELD_START(ID_ISAR5_EL1, CRC32, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR5_EL1, CRC32) + IDREG_FIELD_START(ID_ISAR5_EL1, SHA2, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR5_EL1, SHA2) + IDREG_FIELD_START(ID_ISAR5_EL1, SHA1, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR5_EL1, SHA1) + IDREG_FIELD_START(ID_ISAR5_EL1, AES, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR5_EL1, AES) + IDREG_FIELD_START(ID_ISAR5_EL1, SEVL, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR5_EL1, SEVL) IDREG_END(ID_ISAR5_EL1) =20 IDREG_START(ID_ISAR6_EL1) - IDREG_FIELD(ID_ISAR6_EL1, CLRBHB, 28, 4) - IDREG_FIELD(ID_ISAR6_EL1, I8MM, 24, 4) - IDREG_FIELD(ID_ISAR6_EL1, BF16, 20, 4) - IDREG_FIELD(ID_ISAR6_EL1, SPECRES, 16, 4) - IDREG_FIELD(ID_ISAR6_EL1, SB, 12, 4) - IDREG_FIELD(ID_ISAR6_EL1, FHM, 8, 4) - IDREG_FIELD(ID_ISAR6_EL1, DP, 4, 4) - IDREG_FIELD(ID_ISAR6_EL1, JSCVT, 0, 4) + IDREG_FIELD_START(ID_ISAR6_EL1, CLRBHB, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, CLRBHB) + IDREG_FIELD_START(ID_ISAR6_EL1, I8MM, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, I8MM) + IDREG_FIELD_START(ID_ISAR6_EL1, BF16, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, BF16) + IDREG_FIELD_START(ID_ISAR6_EL1, SPECRES, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR6_EL1, SPECRES) + IDREG_FIELD_START(ID_ISAR6_EL1, SB, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, SB) + IDREG_FIELD_START(ID_ISAR6_EL1, FHM, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, FHM) + IDREG_FIELD_START(ID_ISAR6_EL1, DP, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, DP) + IDREG_FIELD_START(ID_ISAR6_EL1, JSCVT, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, JSCVT) IDREG_END(ID_ISAR6_EL1) =20 IDREG_START(ID_MMFR0_EL1) - IDREG_FIELD(ID_MMFR0_EL1, InnerShr, 28, 4) - IDREG_FIELD(ID_MMFR0_EL1, FCSE, 24, 4) - IDREG_FIELD(ID_MMFR0_EL1, AuxReg, 20, 4) - IDREG_FIELD(ID_MMFR0_EL1, TCM, 16, 4) - IDREG_FIELD(ID_MMFR0_EL1, ShareLvl, 12, 4) - IDREG_FIELD(ID_MMFR0_EL1, OuterShr, 8, 4) - IDREG_FIELD(ID_MMFR0_EL1, PMSA, 4, 4) - IDREG_FIELD(ID_MMFR0_EL1, VMSA, 0, 4) + IDREG_FIELD_START(ID_MMFR0_EL1, InnerShr, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_MMFR0_EL1, InnerShr) + IDREG_FIELD_START(ID_MMFR0_EL1, FCSE, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR0_EL1, FCSE) + IDREG_FIELD_START(ID_MMFR0_EL1, AuxReg, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR0_EL1, AuxReg) + IDREG_FIELD_START(ID_MMFR0_EL1, TCM, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_MMFR0_EL1, TCM) + IDREG_FIELD_START(ID_MMFR0_EL1, ShareLvl, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR0_EL1, ShareLvl) + IDREG_FIELD_START(ID_MMFR0_EL1, OuterShr, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_MMFR0_EL1, OuterShr) + IDREG_FIELD_START(ID_MMFR0_EL1, PMSA, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_MMFR0_EL1, PMSA) + IDREG_FIELD_START(ID_MMFR0_EL1, VMSA, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_END(ID_MMFR0_EL1, VMSA) IDREG_END(ID_MMFR0_EL1) =20 IDREG_START(ID_MMFR1_EL1) - IDREG_FIELD(ID_MMFR1_EL1, BPred, 28, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1TstCln, 24, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1Uni, 20, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1Hvd, 16, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1UniSW, 12, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1HvdSW, 8, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1UniVA, 4, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1HvdVA, 0, 4) + IDREG_FIELD_START(ID_MMFR1_EL1, BPred, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_MMFR1_EL1, BPred) + IDREG_FIELD_START(ID_MMFR1_EL1, L1TstCln, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR1_EL1, L1TstCln) + IDREG_FIELD_START(ID_MMFR1_EL1, L1Uni, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR1_EL1, L1Uni) + IDREG_FIELD_START(ID_MMFR1_EL1, L1Hvd, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_MMFR1_EL1, L1Hvd) + IDREG_FIELD_START(ID_MMFR1_EL1, L1UniSW, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_MMFR1_EL1, L1UniSW) + IDREG_FIELD_START(ID_MMFR1_EL1, L1HvdSW, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_MMFR1_EL1, L1HvdSW) + IDREG_FIELD_START(ID_MMFR1_EL1, L1UniVA, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR1_EL1, L1UniVA) + IDREG_FIELD_START(ID_MMFR1_EL1, L1HvdVA, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR1_EL1, L1HvdVA) IDREG_END(ID_MMFR1_EL1) =20 IDREG_START(ID_MMFR2_EL1) - IDREG_FIELD(ID_MMFR2_EL1, HWAccFlg, 28, 4) - IDREG_FIELD(ID_MMFR2_EL1, WFIStall, 24, 4) - IDREG_FIELD(ID_MMFR2_EL1, MemBarr, 20, 4) - IDREG_FIELD(ID_MMFR2_EL1, UniTLB, 16, 4) + IDREG_FIELD_START(ID_MMFR2_EL1, HWAccFlg, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR2_EL1, HWAccFlg) + IDREG_FIELD_START(ID_MMFR2_EL1, WFIStall, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR2_EL1, WFIStall) + IDREG_FIELD_START(ID_MMFR2_EL1, MemBarr, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR2_EL1, MemBarr) + IDREG_FIELD_START(ID_MMFR2_EL1, UniTLB, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_END(ID_MMFR2_EL1, UniTLB) IDREG_FIELD(ID_MMFR2_EL1, HvdTLB, 12, 4) - IDREG_FIELD(ID_MMFR2_EL1, L1HvdRng, 8, 4) - IDREG_FIELD(ID_MMFR2_EL1, L1HvdBG, 4, 4) - IDREG_FIELD(ID_MMFR2_EL1, L1HvdFG, 0, 4) + IDREG_FIELD_START(ID_MMFR2_EL1, L1HvdRng, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR2_EL1, L1HvdRng) + IDREG_FIELD_START(ID_MMFR2_EL1, L1HvdBG, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR2_EL1, L1HvdBG) + IDREG_FIELD_START(ID_MMFR2_EL1, L1HvdFG, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR2_EL1, L1HvdFG) IDREG_END(ID_MMFR2_EL1) =20 IDREG_START(ID_MMFR3_EL1) - IDREG_FIELD(ID_MMFR3_EL1, Supersec, 28, 4) - IDREG_FIELD(ID_MMFR3_EL1, CMemSz, 24, 4) - IDREG_FIELD(ID_MMFR3_EL1, CohWalk, 20, 4) - IDREG_FIELD(ID_MMFR3_EL1, PAN, 16, 4) - IDREG_FIELD(ID_MMFR3_EL1, MaintBcst, 12, 4) - IDREG_FIELD(ID_MMFR3_EL1, BPMaint, 8, 4) - IDREG_FIELD(ID_MMFR3_EL1, CMaintSW, 4, 4) - IDREG_FIELD(ID_MMFR3_EL1, CMaintVA, 0, 4) + IDREG_FIELD_START(ID_MMFR3_EL1, Supersec, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_MMFR3_EL1, Supersec) + IDREG_FIELD_START(ID_MMFR3_EL1, CMemSz, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR3_EL1, CMemSz) + IDREG_FIELD_START(ID_MMFR3_EL1, CohWalk, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR3_EL1, CohWalk) + IDREG_FIELD_START(ID_MMFR3_EL1, PAN, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR3_EL1, PAN) + IDREG_FIELD_START(ID_MMFR3_EL1, MaintBcst, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR3_EL1, MaintBcst) + IDREG_FIELD_START(ID_MMFR3_EL1, BPMaint, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR3_EL1, BPMaint) + IDREG_FIELD_START(ID_MMFR3_EL1, CMaintSW, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR3_EL1, CMaintSW) + IDREG_FIELD_START(ID_MMFR3_EL1, CMaintVA, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR3_EL1, CMaintVA) IDREG_END(ID_MMFR3_EL1) =20 IDREG_START(ID_MMFR4_EL1) - IDREG_FIELD(ID_MMFR4_EL1, EVT, 28, 4) - IDREG_FIELD(ID_MMFR4_EL1, CCIDX, 24, 4) - IDREG_FIELD(ID_MMFR4_EL1, LSM, 20, 4) - IDREG_FIELD(ID_MMFR4_EL1, HPDS, 16, 4) - IDREG_FIELD(ID_MMFR4_EL1, CnP, 12, 4) - IDREG_FIELD(ID_MMFR4_EL1, XNX, 8, 4) - IDREG_FIELD(ID_MMFR4_EL1, AC2, 4, 4) - IDREG_FIELD(ID_MMFR4_EL1, SpecSEI, 0, 4) + IDREG_FIELD_START(ID_MMFR4_EL1, EVT, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR4_EL1, EVT) + IDREG_FIELD_START(ID_MMFR4_EL1, CCIDX, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR4_EL1, CCIDX) + IDREG_FIELD_START(ID_MMFR4_EL1, LSM, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR4_EL1, LSM) + IDREG_FIELD_START(ID_MMFR4_EL1, HPDS, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR4_EL1, HPDS) + IDREG_FIELD_START(ID_MMFR4_EL1, CnP, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR4_EL1, CnP) + IDREG_FIELD_START(ID_MMFR4_EL1, XNX, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR4_EL1, XNX) + IDREG_FIELD_START(ID_MMFR4_EL1, AC2, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR4_EL1, AC2) + IDREG_FIELD_START(ID_MMFR4_EL1, SpecSEI, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR4_EL1, SpecSEI) IDREG_END(ID_MMFR4_EL1) =20 IDREG_START(ID_MMFR5_EL1) - IDREG_FIELD(ID_MMFR5_EL1, nTLBPA, 4, 4) - IDREG_FIELD(ID_MMFR5_EL1, ETS, 0, 4) + IDREG_FIELD_START(ID_MMFR5_EL1, nTLBPA, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR5_EL1, nTLBPA) + IDREG_FIELD_START(ID_MMFR5_EL1, ETS, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_MMFR5_EL1, ETS) IDREG_END(ID_MMFR5_EL1) =20 IDREG_START(ID_PFR0_EL1) - IDREG_FIELD(ID_PFR0_EL1, RAS, 28, 4) - IDREG_FIELD(ID_PFR0_EL1, DIT, 24, 4) - IDREG_FIELD(ID_PFR0_EL1, AMU, 20, 4) - IDREG_FIELD(ID_PFR0_EL1, CSV2, 16, 4) - IDREG_FIELD(ID_PFR0_EL1, State3, 12, 4) - IDREG_FIELD(ID_PFR0_EL1, State2, 8, 4) - IDREG_FIELD(ID_PFR0_EL1, State1, 4, 4) - IDREG_FIELD(ID_PFR0_EL1, State0, 0, 4) + IDREG_FIELD_START(ID_PFR0_EL1, RAS, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_PFR0_EL1, RAS) + IDREG_FIELD_START(ID_PFR0_EL1, DIT, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR0_EL1, DIT) + IDREG_FIELD_START(ID_PFR0_EL1, AMU, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR0_EL1, AMU) + IDREG_FIELD_START(ID_PFR0_EL1, CSV2, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR0_EL1, CSV2) + IDREG_FIELD_START(ID_PFR0_EL1, State3, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR0_EL1, State3) + IDREG_FIELD_START(ID_PFR0_EL1, State2, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR0_EL1, State2) + IDREG_FIELD_START(ID_PFR0_EL1, State1, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_PFR0_EL1, State1) + IDREG_FIELD_START(ID_PFR0_EL1, State0, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR0_EL1, State0) IDREG_END(ID_PFR0_EL1) =20 IDREG_START(ID_PFR1_EL1) - IDREG_FIELD(ID_PFR1_EL1, GIC, 28, 4) - IDREG_FIELD(ID_PFR1_EL1, Virt_frac, 24, 4) - IDREG_FIELD(ID_PFR1_EL1, Sec_frac, 20, 4) - IDREG_FIELD(ID_PFR1_EL1, GenTimer, 16, 4) - IDREG_FIELD(ID_PFR1_EL1, Virtualization, 12, 4) - IDREG_FIELD(ID_PFR1_EL1, MProgMod, 8, 4) - IDREG_FIELD(ID_PFR1_EL1, Security, 4, 4) - IDREG_FIELD(ID_PFR1_EL1, ProgMod, 0, 4) + IDREG_FIELD_START(ID_PFR1_EL1, GIC, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_PFR1_EL1, GIC) + IDREG_FIELD_START(ID_PFR1_EL1, Virt_frac, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR1_EL1, Virt_frac) + IDREG_FIELD_START(ID_PFR1_EL1, Sec_frac, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR1_EL1, Sec_frac) + IDREG_FIELD_START(ID_PFR1_EL1, GenTimer, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR1_EL1, GenTimer) + IDREG_FIELD_START(ID_PFR1_EL1, Virtualization, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR1_EL1, Virtualization) + IDREG_FIELD_START(ID_PFR1_EL1, MProgMod, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR1_EL1, MProgMod) + IDREG_FIELD_START(ID_PFR1_EL1, Security, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR1_EL1, Security) + IDREG_FIELD_START(ID_PFR1_EL1, ProgMod, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR1_EL1, ProgMod) IDREG_END(ID_PFR1_EL1) =20 IDREG_START(ID_PFR2_EL1) - IDREG_FIELD(ID_PFR2_EL1, RAS_frac, 8, 4) - IDREG_FIELD(ID_PFR2_EL1, SSBS, 4, 4) - IDREG_FIELD(ID_PFR2_EL1, CSV3, 0, 4) + IDREG_FIELD_START(ID_PFR2_EL1, RAS_frac, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR2_EL1, RAS_frac) + IDREG_FIELD_START(ID_PFR2_EL1, SSBS, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR2_EL1, SSBS) + IDREG_FIELD_START(ID_PFR2_EL1, CSV3, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR2_EL1, CSV3) IDREG_END(ID_PFR2_EL1) =20 IDREG_START(MIDR_EL1) - IDREG_FIELD(MIDR_EL1, Implementer, 24, 8) + IDREG_FIELD_START(MIDR_EL1, Implementer, 24, 8) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(65) + IDREG_FIELD_ARCH_VAL(66) + IDREG_FIELD_ARCH_VAL(67) + IDREG_FIELD_ARCH_VAL(68) + IDREG_FIELD_ARCH_VAL(70) + IDREG_FIELD_ARCH_VAL(73) + IDREG_FIELD_ARCH_VAL(77) + IDREG_FIELD_ARCH_VAL(78) + IDREG_FIELD_ARCH_VAL(80) + IDREG_FIELD_ARCH_VAL(81) + IDREG_FIELD_ARCH_VAL(86) + IDREG_FIELD_ARCH_VAL(105) + IDREG_FIELD_ARCH_VAL(192) + IDREG_FIELD_END(MIDR_EL1, Implementer) IDREG_FIELD(MIDR_EL1, Variant, 20, 4) - IDREG_FIELD(MIDR_EL1, Architecture, 16, 4) + IDREG_FIELD_START(MIDR_EL1, Architecture, 16, 4) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(MIDR_EL1, Architecture) IDREG_FIELD(MIDR_EL1, PartNum, 4, 12) IDREG_FIELD(MIDR_EL1, Revision, 0, 4) IDREG_END(MIDR_EL1) =20 IDREG_START(MPIDR_EL1) IDREG_FIELD(MPIDR_EL1, Aff3, 32, 8) - IDREG_FIELD(MPIDR_EL1, U, 30, 1) - IDREG_FIELD(MPIDR_EL1, MT, 24, 1) + IDREG_FIELD_START(MPIDR_EL1, U, 30, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MPIDR_EL1, U) + IDREG_FIELD_START(MPIDR_EL1, MT, 24, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MPIDR_EL1, MT) IDREG_FIELD(MPIDR_EL1, Aff2, 16, 8) IDREG_FIELD(MPIDR_EL1, Aff1, 8, 8) IDREG_FIELD(MPIDR_EL1, Aff0, 0, 8) IDREG_END(MPIDR_EL1) =20 IDREG_START(MVFR0_EL1) - IDREG_FIELD(MVFR0_EL1, FPRound, 28, 4) - IDREG_FIELD(MVFR0_EL1, FPShVec, 24, 4) - IDREG_FIELD(MVFR0_EL1, FPSqrt, 20, 4) - IDREG_FIELD(MVFR0_EL1, FPDivide, 16, 4) - IDREG_FIELD(MVFR0_EL1, FPTrap, 12, 4) - IDREG_FIELD(MVFR0_EL1, FPDP, 8, 4) - IDREG_FIELD(MVFR0_EL1, FPSP, 4, 4) - IDREG_FIELD(MVFR0_EL1, SIMDReg, 0, 4) + IDREG_FIELD_START(MVFR0_EL1, FPRound, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR0_EL1, FPRound) + IDREG_FIELD_START(MVFR0_EL1, FPShVec, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR0_EL1, FPShVec) + IDREG_FIELD_START(MVFR0_EL1, FPSqrt, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR0_EL1, FPSqrt) + IDREG_FIELD_START(MVFR0_EL1, FPDivide, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR0_EL1, FPDivide) + IDREG_FIELD_START(MVFR0_EL1, FPTrap, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR0_EL1, FPTrap) + IDREG_FIELD_START(MVFR0_EL1, FPDP, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(MVFR0_EL1, FPDP) + IDREG_FIELD_START(MVFR0_EL1, FPSP, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(MVFR0_EL1, FPSP) + IDREG_FIELD_START(MVFR0_EL1, SIMDReg, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(MVFR0_EL1, SIMDReg) IDREG_END(MVFR0_EL1) =20 IDREG_START(MVFR1_EL1) - IDREG_FIELD(MVFR1_EL1, SIMDFMAC, 28, 4) - IDREG_FIELD(MVFR1_EL1, FPHP, 24, 4) - IDREG_FIELD(MVFR1_EL1, SIMDHP, 20, 4) - IDREG_FIELD(MVFR1_EL1, SIMDSP, 16, 4) - IDREG_FIELD(MVFR1_EL1, SIMDInt, 12, 4) - IDREG_FIELD(MVFR1_EL1, SIMDLS, 8, 4) - IDREG_FIELD(MVFR1_EL1, FPDNaN, 4, 4) - IDREG_FIELD(MVFR1_EL1, FPFtZ, 0, 4) + IDREG_FIELD_START(MVFR1_EL1, SIMDFMAC, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR1_EL1, SIMDFMAC) + IDREG_FIELD_START(MVFR1_EL1, FPHP, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(MVFR1_EL1, FPHP) + IDREG_FIELD_START(MVFR1_EL1, SIMDHP, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(MVFR1_EL1, SIMDHP) + IDREG_FIELD_START(MVFR1_EL1, SIMDSP, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR1_EL1, SIMDSP) + IDREG_FIELD_START(MVFR1_EL1, SIMDInt, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR1_EL1, SIMDInt) + IDREG_FIELD_START(MVFR1_EL1, SIMDLS, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR1_EL1, SIMDLS) + IDREG_FIELD_START(MVFR1_EL1, FPDNaN, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR1_EL1, FPDNaN) + IDREG_FIELD_START(MVFR1_EL1, FPFtZ, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR1_EL1, FPFtZ) IDREG_END(MVFR1_EL1) =20 IDREG_START(MVFR2_EL1) - IDREG_FIELD(MVFR2_EL1, FPMisc, 4, 4) - IDREG_FIELD(MVFR2_EL1, SIMDMisc, 0, 4) + IDREG_FIELD_START(MVFR2_EL1, FPMisc, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(MVFR2_EL1, FPMisc) + IDREG_FIELD_START(MVFR2_EL1, SIMDMisc, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(MVFR2_EL1, SIMDMisc) IDREG_END(MVFR2_EL1) =20 IDREG_START(REVIDR_EL1) IDREG_END(REVIDR_EL1) =20 IDREG_START(SMIDR_EL1) - IDREG_FIELD(SMIDR_EL1, NSMC, 56, 4) - IDREG_FIELD(SMIDR_EL1, HIP, 52, 4) + IDREG_FIELD_START(SMIDR_EL1, NSMC, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_ARCH_VAL(12) + IDREG_FIELD_ARCH_VAL(13) + IDREG_FIELD_ARCH_VAL(14) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(SMIDR_EL1, NSMC) + IDREG_FIELD_START(SMIDR_EL1, HIP, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_ARCH_VAL(12) + IDREG_FIELD_ARCH_VAL(13) + IDREG_FIELD_ARCH_VAL(14) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(SMIDR_EL1, HIP) IDREG_FIELD(SMIDR_EL1, Affinity2, 32, 20) - IDREG_FIELD(SMIDR_EL1, Implementer, 24, 8) + IDREG_FIELD_START(SMIDR_EL1, Implementer, 24, 8) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(65) + IDREG_FIELD_ARCH_VAL(66) + IDREG_FIELD_ARCH_VAL(67) + IDREG_FIELD_ARCH_VAL(68) + IDREG_FIELD_ARCH_VAL(70) + IDREG_FIELD_ARCH_VAL(73) + IDREG_FIELD_ARCH_VAL(77) + IDREG_FIELD_ARCH_VAL(78) + IDREG_FIELD_ARCH_VAL(80) + IDREG_FIELD_ARCH_VAL(81) + IDREG_FIELD_ARCH_VAL(86) + IDREG_FIELD_ARCH_VAL(105) + IDREG_FIELD_ARCH_VAL(192) + IDREG_FIELD_END(SMIDR_EL1, Implementer) IDREG_FIELD(SMIDR_EL1, Revision, 16, 8) - IDREG_FIELD(SMIDR_EL1, SMPS, 15, 1) - IDREG_FIELD(SMIDR_EL1, SH, 13, 2) + IDREG_FIELD_START(SMIDR_EL1, SMPS, 15, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(SMIDR_EL1, SMPS) + IDREG_FIELD_START(SMIDR_EL1, SH, 13, 2) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(SMIDR_EL1, SH) IDREG_FIELD(SMIDR_EL1, Affinity, 0, 12) IDREG_END(SMIDR_EL1) =20 diff --git a/scripts/update-aarch64-cpu-sysreg-properties.py b/scripts/upda= te-aarch64-cpu-sysreg-properties.py index 6f5edb88d2..96f8aa2d64 100644 --- a/scripts/update-aarch64-cpu-sysreg-properties.py +++ b/scripts/update-aarch64-cpu-sysreg-properties.py @@ -9,7 +9,12 @@ # # IDREG_START(REG) # IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) -# ... +# or for fields with enum values +# IDREG_FIELD_START(REG, FIELD, SHIFT, LENGTH) +# IDREG_FIELD_ARCH_VAL(VALUE) +# ../.. +# IDREG_FIELD_END(REG, FIELD) +# ../..=20 # IDREG_END(REG) # # Copyright (C) 2026 Red Hat, Inc. @@ -97,6 +102,59 @@ def collect_fields(item, bit_offset=3D0): =20 return fields =20 +def parse_raw_val(val_obj): + """Helper to unwrap int values from strings, ints, or nested dicts.""" + if isinstance(val_obj, dict): + val_obj =3D val_obj.get("value") + + if val_obj is None: + return None + + raw_val_str =3D str(val_obj).strip().replace("'", "") + try: + return int(raw_val_str, 2) + except ValueError: + try: + return int(raw_val_str, 0) + except ValueError: + return None + +def extract_field_enums(field): + enums =3D [] + if not isinstance(field, dict): + return enums + + value_obj =3D field.get("value") + if not isinstance(value_obj, dict): + return enums + + constraints =3D value_obj.get("constraints") + if not isinstance(constraints, dict): + return enums + + val_entries =3D constraints.get("values", []) + if not isinstance(val_entries, list): + return enums + + for val_entry in val_entries: + if not isinstance(val_entry, dict): + continue + =20 + entry_type =3D val_entry.get("_type") + if entry_type =3D=3D "Values.Value": + int_val =3D parse_raw_val(val_entry.get("value")) + if int_val is not None: + enums.append({'value': int_val}) + =20 + elif entry_type =3D=3D "Values.ValueRange": + s =3D parse_raw_val(val_entry.get("start")) + e =3D parse_raw_val(val_entry.get("end")) + + if s is not None and e is not None: + for v in range(s, e + 1): + enums.append({'value': v}) + =20 + return enums =20 def generate_sysreg_properties_from_registers_json(id_reg_names, raw_json_= path): with open(raw_json_path, 'r') as f: @@ -128,16 +186,32 @@ def generate_sysreg_properties_from_registers_json(id= _reg_names, raw_json_path): # Only keep the fields with the highest MSB # needed fir CCSIDR_EL1 if name not in unique_fields or msb > unique_fields[na= me]['msb']: - unique_fields[name] =3D {'lsb': lsb, 'msb': msb, '= width': width} + # extract enum values if any + enums =3D extract_field_enums(val) + unique_fields[name] =3D {'lsb': lsb, 'msb': msb, '= width': width, 'enums': enums} =20 # Sort decreasing lsbs sorted_fields =3D sorted(unique_fields.items(), key=3Dlambda x: x[1]['lsb'], reverse=3DTrue) =20 for name, bits in sorted_fields: - line =3D (f" IDREG_FIELD({reg_name}, " - f"{name}, {bits['lsb']}, {bits['width']})\n") + enums_list =3D bits.get('enums', []) + + if enums_list: + line =3D (f" IDREG_FIELD_START({reg_name}, " + f"{name}, {bits['lsb']}, {bits['width']})\n") + else: + line =3D (f" IDREG_FIELD({reg_name}, " + f"{name}, {bits['lsb']}, {bits['width']})\n") final_output +=3D line + # generate enum value or range if any + for enum_item in enums_list: + final_output +=3D (f" IDREG_FIELD_ARCH_VAL({enu= m_item['value']})\n") + + if enums_list: + line =3D (f" IDREG_FIELD_END({reg_name}, {name})\n") + final_output +=3D line + =20 final_output +=3D f"IDREG_END({reg_name})\n" final_output +=3D "\n" =20 @@ -147,7 +221,11 @@ def generate_sysreg_properties_from_registers_json(id_= reg_names, raw_json_path): f.write("/* SPDX-License-Identifier: GPL-2.0-or-later */\n\n") f.write("/* IDREG_START(REG) */\n") f.write("/* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */\n") + f.write("/* or for fields with enum values */\n") + f.write("/* IDREG_FIELD_START(REG, FIELD, SHIFT, LENGTH) */\n") + f.write("/* IDREG_FIELD_ARCH_VAL(VALUE) */\n") f.write("/* ... */\n") + f.write("/* IDREG_FIELD_END(REG, FIELD) */\n") f.write("/* IDREG_END(REG) */\n\n") f.write(final_output) =20 --=20 2.53.0 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peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 09/20] target/arm/cpu_idregs: generate tables for Arm64 ID registers and fields Date: Wed, 26 Aug 2026 11:36:14 +0200 Message-ID: <20260826093747.1670077-10-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737161334158500 Content-Type: text/plain; charset="utf-8" From: Shaju Abraham Include cpu-idregs.h.inc multiple times with different definitions for the X-macros. This will generate tables for all Arm64 ID registers and their fields. Additionally, initialize the tables with all architecturally defined values. These tables will be consumed by the property layer in future patches. Note: This triggers a minot checkpatch error but I prefer to keep the coma in the macro. ERROR: Macros with complex values should be enclosed in parenthesis +#define IDREG_FIELD_ARCH_VAL(v) (v), Co-authored-by: Khushit Shah Signed-off-by: Khushit Shah Signed-off-by: Shaju Abraham Signed-off-by: Eric Auger --- v7 -> v8 Adaptation after removal of struct ArmIdRegArchVal v5 -> v6 - restored support of enum values --- target/arm/cpu-idregs.c | 96 +++++++++++++++++++++++++++++++++++++++++ target/arm/meson.build | 1 + 2 files changed, 97 insertions(+) create mode 100644 target/arm/cpu-idregs.c diff --git a/target/arm/cpu-idregs.c b/target/arm/cpu-idregs.c new file mode 100644 index 0000000000..199d593153 --- /dev/null +++ b/target/arm/cpu-idregs.c @@ -0,0 +1,96 @@ +/* + * ARM ID register field table. + * + * Builds the per-id-register field descriptor arrays and the global + * arm_idregs[] table. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "cpu.h" +#include "cpu-idregs.h" + +/* + * Generate an array of architecturely defined values for each field + * associated with enum values + */ + +#define IDREG_START(reg) +#define IDREG_END(reg) +#define IDREG_FIELD(reg, field, shift, length) +#define IDREG_FIELD_START(reg, field, shift, length) \ + static const uint64_t reg##_##field##_arch_vals[] =3D { +#define IDREG_FIELD_ARCH_VAL(v) (v), +#define IDREG_FIELD_END(reg, field) \ + }; + +#include "cpu-idregs.h.inc" + +#undef IDREG_START +#undef IDREG_END +#undef IDREG_FIELD +#undef IDREG_FIELD_START +#undef IDREG_FIELD_END +#undef IDREG_FIELD_ARCH_VAL + +/* generate an array of per-register ArmIdRegField[] descriptors */ + +#define IDREG_START(reg) \ + static ARM64SysRegField reg##_fields[] =3D { + +#define IDREG_END(reg) \ + }; + +#define IDREG_FIELD_START(reg, field, _shift, _length) \ + { \ + .name =3D #field, \ + .index =3D reg##_IDX, \ + .shift =3D (_shift), \ + .length =3D (_length), \ + .arch_vals =3D (uint64_t *)reg##_##field##_arch_vals, \ + .arch_vals_count =3D ARRAY_SIZE(reg##_##field##_arch_vals), \ + }, + +#define IDREG_FIELD(reg, field, _shift, _length) \ + { \ + .name =3D #field, \ + .index =3D reg##_IDX, \ + .shift =3D (_shift), \ + .length =3D (_length), \ + }, + +#define IDREG_FIELD_ARCH_VAL(v) + +#define IDREG_FIELD_END(reg, field) + +#include "cpu-idregs.h.inc" + +#undef IDREG_START +#undef IDREG_END +#undef IDREG_FIELD +#undef IDREG_FIELD_START +#undef IDREG_FIELD_END +#undef IDREG_FIELD_ARCH_VAL + +/* generate an array of top level ID registers */ + +#define IDREG_END(reg) +#define IDREG_FIELD(reg, field, shift, length) +#define IDREG_FIELD_START(reg, field, shift, length) +#define IDREG_FIELD_ARCH_VAL(v) +#define IDREG_FIELD_END(reg, field) + +#define IDREG_START(reg) \ + [reg##_IDX] =3D { \ + .name =3D #reg, \ + .index =3D reg##_IDX, \ + .fields =3D reg##_fields, \ + .fields_count =3D ARRAY_SIZE(reg##_fields), \ + }, + +ARM64SysReg arm64_id_regs[NUM_ID_IDX] =3D { +#include "cpu-idregs.h.inc" +}; + diff --git a/target/arm/meson.build b/target/arm/meson.build index 0369f96b4c..384d90c530 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -30,6 +30,7 @@ arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_= true: files( =20 arm_common_system_ss.add(files( 'arm-qmp-cmds.c', + 'cpu-idregs.c', )) arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm= .c')) arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1787737162; cv=none; d=zohomail.com; s=zohoarc; b=OrJMq5r329ZVgCaMjCf3tmyFNAOvuSUC9eVmt8VFL4r+Md2UfaMHxtm6qGP06wdE3+gSh9tCxOm0kX5eDY2J//WST0lDdPqpswJoFz93VkhvXkrhNVFiXi9bVqXflw9fNg1eP/6dxXWmfzAim3bsHKDjmiTmWEK6vUQdONWFnSo= ARC-Message-Signature: i=1; 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Wed, 26 Aug 2026 09:39:03 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.48.93]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 060431955F05; Wed, 26 Aug 2026 09:38:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737149; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=otoUEY57Qj4hJp3qf+4Qj2LsqyB2wYRV1YS7nrlnur0=; b=bYcDfkSaXu8d0mIjYCMdwONctuNlf01ujZRT6BoB1GcSR03qE5HfybQsoX4vHbsJFFNZpd 9CWfi/0fIt2et+xsZx6hW6XzMLDHMKP5JuiG1Y4XpHYw5fJK5fjbEev4ozZwGC1EejqkZ4 OESfQX4Qc+ZVJwvRXI1ePDsVcaOJZrQ= X-MC-Unique: 1PXeVloyMuWP-kg92ybDhg-1 X-Mimecast-MFC-AGG-ID: 1PXeVloyMuWP-kg92ybDhg_1787737144 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 10/20] target/arm/kvm: Retrieve writable ID reg map Date: Wed, 26 Aug 2026 11:36:15 +0200 Message-ID: <20260826093747.1670077-11-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737163344158500 Content-Type: text/plain; charset="utf-8" From: Cornelia Huck Add an helper to retrieve the writable id reg bitmask. then retrieve the writable_map array and dispatch it in the writable_map fields of arm64_id_regs[] elements. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- v7 -> v8 - added kvm_enabled() v5 -> v6 - use arm64_id_regs[].writable_map - squashed 2 commits (helper + user) - removed stub --- target/arm/kvm.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index d40a6a9859..2ecb324358 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -28,6 +28,7 @@ #include "kvm_arm.h" #include "cpu.h" #include "cpu-sysregs.h" +#include "cpu-idregs.h" #include "trace.h" #include "internals.h" #include "hw/pci/pci.h" @@ -51,6 +52,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = =3D { static bool cap_has_mp_state; static bool cap_has_inject_serror_esr; static bool cap_has_inject_ext_dabt; +static bool writable_map_dispatched; =20 /** * ARMHostCPUFeatures: information about the host CPU (identified @@ -273,6 +275,21 @@ static uint32_t kvm_arm_sve_get_vls(int fd) return vls[0] & MAKE_64BIT_MASK(0, ARM_MAX_VQ); } =20 +static int kvm_feature_idx_to_idregs_idx(int kidx) +{ + int op1, crm, op2; + ARMSysRegs sysreg; + + op1 =3D kidx / 64; + if (op1 =3D=3D 2) { + op1 =3D 3; + } + crm =3D (kidx % 64) / 8; + op2 =3D kidx % 8; + sysreg =3D ENCODE_ID_REG(3, op1, 0, crm, op2); + return get_sysreg_idx(sysreg); +} + static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -480,9 +497,53 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) ahcf->features =3D features; } =20 +static int kvm_arm_get_writable_id_regs(uint64_t *idregmap) +{ + int cap_writable_id_regs; + struct reg_mask_range range =3D { + .range =3D KVM_ARM_FEATURE_ID_RANGE, + .reserved =3D {0}, + .addr =3D (uint64_t)idregmap, + }; + + cap_writable_id_regs =3D + kvm_check_extension(kvm_state, KVM_CAP_ARM_SUPPORTED_REG_MASK_RANG= ES); + + if (!cap_writable_id_regs || + !(cap_writable_id_regs & (1 << KVM_ARM_FEATURE_ID_RANGE))) { + return -ENOSYS; + } + + if (kvm_vm_ioctl(kvm_state, KVM_ARM_GET_REG_WRITABLE_MASKS, &range)) { + return -errno; + } + return 0; +} + void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; + uint64_t *writable_map; + + writable_map =3D g_new(uint64_t, KVM_ARM_FEATURE_ID_RANGE_SIZE); + + if (kvm_enabled() && !writable_map_dispatched && + !kvm_arm_get_writable_id_regs(writable_map)) { + for (int i =3D 0; i < KVM_ARM_FEATURE_ID_RANGE_SIZE; i++) { + uint64_t mask =3D writable_map[i]; + + if (mask) { + int idx =3D kvm_feature_idx_to_idregs_idx(i); + + if (idx < 0 || idx > ARRAY_SIZE(arm64_id_regs)) { + continue; + } + arm64_id_regs[idx].writable_mask =3D mask; + } + } + writable_map_dispatched =3D true; + } + g_free(writable_map); =20 if (!arm_host_cpu_features.dtb_compatible) { kvm_arm_get_host_cpu_features(&arm_host_cpu_features); --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=jLGdRMTW/8i/YmqFjNYUQJ4Y5e/O4rZyZEZTS1jKmXdfzfT1yVLYDHOgt/qWgM0xJhxS+s 70ztpoaXHL1hBCDOYAi1iNJMckZqsRVIUG6e8fU5AfMwTyUBZyOAWLB6Jywh/xzJG7x/Su RL42VLiUQYcVEFamzATGm+foWPFbo28= X-MC-Unique: DBq3-a9lNe-9D3WJSSkCUg-1 X-Mimecast-MFC-AGG-ID: DBq3-a9lNe-9D3WJSSkCUg_1787737150 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 11/20] arm/kvm: Initialize all writable ID registers from host Date: Wed, 26 Aug 2026 11:36:16 +0200 Message-ID: <20260826093747.1670077-12-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737181420158500 Content-Type: text/plain; charset="utf-8" We want to allow overwriting writable fields of some ID registers. However currently some of them are never touched, neither read nor w. Examples are CLIDR_EL1, CTR_EL0, REVIDR_EL1, MIDR_EL1. We want to initialize them from the host value, allow overwrite and write back for kvm afterwards. This patch implements the initialization. Introduce a new get_host_cpu_idregs() helper that gets the host values for all writable ID regs and store them in isar.idregs[]. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Khushit Shah --- v7 -> v8 - fix indent and added Khushit's R-b v6 -> v7 - remove vcpu from prototypes (Khushit) v5 -> v6 - do not check writable_map anymore --- target/arm/kvm.c | 96 ++++++++++++++++++++++++++++++++++++++++- target/arm/trace-events | 2 + 2 files changed, 96 insertions(+), 2 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 2ecb324358..683f9efb88 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -43,6 +43,7 @@ #include "hw/acpi/ghes.h" #include "target/arm/gtimer.h" #include "migration/blocker.h" +#include "cpu-idregs.h" =20 const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_INFO(DEVICE_CTRL), @@ -290,7 +291,44 @@ static int kvm_feature_idx_to_idregs_idx(int kidx) return get_sysreg_idx(sysreg); } =20 -static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +/* + * get_host_cpu_idregs: Read all the writable ID reg host values + * + * Need to be called once the writable mask has been populated + * Note we may want to read all the known id regs but some of them are not + * writable and return an error, hence the choice of reading only those wh= ich + * are writable. Those are also readable! + */ +static int get_host_cpu_idregs(int fd, ARMHostCPUFeatures *ahcf) +{ + int err =3D 0; + int i; + + for (i =3D 0; i < NUM_ID_IDX; i++) { + ARM64SysReg *sysregdesc =3D &arm64_id_regs[i]; + ARMSysRegs sysreg =3D id_register_sysreg[i]; + uint64_t *reg; + int ret; + + if (!sysregdesc->writable_mask) { + continue; + } + + reg =3D &ahcf->isar.idregs[i]; + ret =3D read_sys_reg64(fd, reg, idregs_sysreg_to_kvm_reg(sysreg)); + trace_get_host_cpu_idregs(sysregdesc->name, *reg); + if (ret) { + error_report("%s error reading value of host %s register (%m)", + __func__, sysregdesc->name); + + err =3D ret; + } + } + return err; +} + +static void +kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this @@ -376,6 +414,16 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) SET_IDREG(&ahcf->isar, ID_AA64PFR0, 0x00000011); /* EL1&0, AArch64= only */ err =3D 0; } else { + /* Make sure all writable ID reg values are initialized */ + err |=3D get_host_cpu_idregs(fd, ahcf); + + /* + * temporarily override the CLIDR_EL1 value since some host values + * trigger "Unified type is not implemented at level n" error in + * fdt_add_cpu_nodes() + */ + SET_IDREG(&ahcf->isar, CLIDR, 0x0); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR2_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64SMFR0_EL1_IDX); @@ -1161,6 +1209,34 @@ bool kvm_arm_cpu_post_load(ARMCPU *cpu) return true; } =20 +/* + * Copy writable ID regs from isar.idregs[] to cpreg_list + * in case their value differs from the original init cpreg value + */ +static void kvm_arm_writable_idregs_to_cpreg_list(ARMCPU *cpu) +{ + for (int i =3D 0; i < NUM_ID_IDX; i++) { + ARM64SysReg *sysregdesc =3D &arm64_id_regs[i]; + ARMSysRegs sysreg =3D id_register_sysreg[i]; + uint64_t previous, new; + uint64_t *cpreg; + + if (!sysregdesc->writable_mask) { + continue; + } + + cpreg =3D kvm_arm_get_cpreg_ptr(cpu, idregs_sysreg_to_kvm_reg(sysr= eg)); + previous =3D *cpreg; + new =3D cpu->isar.idregs[i]; + + if (previous !=3D new) { + *cpreg =3D new; + trace_kvm_arm_writable_idregs_to_cpreg_list(sysregdesc->name, + previous, new); + } + } +} + void kvm_arm_reset_vcpu(ARMCPU *cpu) { int ret; @@ -2115,7 +2191,23 @@ int kvm_arch_init_vcpu(CPUState *cs) } cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; =20 - return kvm_arm_init_cpreg_list(cpu); + ret =3D kvm_arm_init_cpreg_list(cpu); + if (ret) { + return ret; + } + /* overwrite writable ID regs with their updated property values */ + kvm_arm_writable_idregs_to_cpreg_list(cpu); + ret =3D write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE); + if (!ret) { + return -1; + } + /* + * modified values may have changed the visibility of some regs, + * reinitialize the cpreg_list accordingly + */ + ret =3D kvm_arm_init_cpreg_list(cpu); + + return ret; } =20 int kvm_arch_destroy_vcpu(CPUState *cs) diff --git a/target/arm/trace-events b/target/arm/trace-events index 8502fb3265..c25d2a1191 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -13,6 +13,8 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" =20 # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 +get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host v= alue for %s is 0x%"PRIx64 +kvm_arm_writable_idregs_to_cpreg_list(const char *name, uint64_t previous,= uint64_t new) "%s overwrite default 0x%"PRIx64" with 0x%"PRIx64 =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=Apv/gEUqSQO5ijB2/awb2TNDx5MzX9VbQk7Ghepfs+pP6elIWB2DVfLT7uVHXK+C1ykeqr 7SLi3wSVZ5E/BEPa25zNSgvaHb0KqNBPYivkB6kaD+RD3L16xNH1zQ+TZyDSH85cEJ7yCv kmlUGcTCP2x6VddVIHPID9oqx+abLEk= X-MC-Unique: DOsqQznRNleHd2LcUgX7zA-1 X-Mimecast-MFC-AGG-ID: DOsqQznRNleHd2LcUgX7zA_1787737156 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 12/20] target/arm/kvm: Introduce kvm_arm_expose_idreg_properties Date: Wed, 26 Aug 2026 11:36:17 +0200 Message-ID: <20260826093747.1670077-13-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737183468158500 Content-Type: text/plain; charset="utf-8" This helper decode the ID reg writable mask, matches it against ID reg fields defined in target/arm/cpu-idregs.h.inc and for each writable named field, generates a uint64 property. REVIDR_EL1 and AIDR_EL1 are writable but they do not expose any field. They will be handled separately. Signed-off-by: Eric Auger --- v7 -> v8 - scratch the '!' in the error_setg - addapt to the removal of struct ArmIdRegArchVal v5 -> v6 - for enum values, check against value value when setting the prop - do not check writable_map flag anymore v4 -> v5: - free prop_name - check cpu->writable_map as a preamble in kvm_arm_expose_idreg_properties --- target/arm/kvm_arm.h | 10 +++ target/arm/kvm.c | 143 ++++++++++++++++++++++++++++++++++++++++ target/arm/trace-events | 4 ++ 3 files changed, 157 insertions(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index e7c40fb003..2b3474cc36 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -142,6 +142,16 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); */ void kvm_arm_add_vcpu_properties(ARMCPU *cpu); =20 +typedef struct ARM64SysReg ARM64SysReg; +/** + * kvm_arm_expose_idreg_properties: + * @cpu: The CPU object to generate the properties for + * @reg: registers from the host + * + * analyze the writable mask and generate properties for writable fields + */ +void kvm_arm_expose_idreg_properties(ARMCPU *cpu, ARM64SysReg *regs); + /** * kvm_arm_steal_time_finalize: * @cpu: ARMCPU for which to finalize kvm-steal-time diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 683f9efb88..2557d7b0d9 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -327,6 +327,149 @@ static int get_host_cpu_idregs(int fd, ARMHostCPUFeat= ures *ahcf) return err; } =20 +static ARM64SysRegField *get_field(int i, ARM64SysReg *reg) +{ + for (int f =3D 0; f < reg->fields_count; f++) { + struct ARM64SysRegField *field =3D ®->fields[f]; + int upper =3D field->shift + field->length - 1; + + if (i >=3D field->shift && i <=3D upper) { + return field; + } + } + return NULL; +} + +static void set_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARM64SysRegField *field =3D (ARM64SysRegField *)opaque; + ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t *idregs =3D cpu->isar.idregs; + uint64_t old, value, mask; + int lower =3D field->shift; + int length =3D field->length; + int index =3D field->index; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (length < 64 && value > ((1 << length) - 1)) { + error_setg(errp, + "idreg %s set value (0x%lx) exceeds length of field (%d= )!", + name, value, length); + return; + } + + if (field->arch_vals) { + /* this field has some enum values */ + for (int i =3D 0; i < field->arch_vals_count; i++) { + if (value =3D=3D field->arch_vals[i]) { + goto valid; + } + } + error_setg(errp, + "idreg %s set value (0x%lx) does not match any " + "arch valid enum value", name, value); + return; + } + +valid: + + mask =3D MAKE_64BIT_MASK(lower, length); + value =3D value << lower; + old =3D idregs[index]; + idregs[index] =3D old & ~mask; + idregs[index] |=3D value; + trace_set_sysreg_prop(name, old, mask, value, idregs[index]); +} + +static void get_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARM64SysRegField *field =3D (ARM64SysRegField *)opaque; + ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t *idregs =3D cpu->isar.idregs; + uint64_t value, mask; + int lower =3D field->shift; + int length =3D field->length; + int index =3D field->index; + + mask =3D MAKE_64BIT_MASK(lower, length); + value =3D (idregs[index] & mask) >> lower; + visit_type_uint64(v, name, &value, errp); + trace_get_sysreg_prop(name, value); +} + +/* + * decode_idreg_writemap: Generate props for writable fields + * + * @obj: CPU object + * @reg: description of the sysreg + */ +static int +decode_idreg_writemap(Object *obj, ARM64SysReg *reg) +{ + uint64_t map =3D reg->writable_mask; + int i =3D ctz64(map); + int nb_sysreg_props =3D 0; + + while (map) { + ARM64SysRegField *field =3D get_field(i, reg); + int lower, upper; + char *prop_name; + uint64_t field_mask; + + if (!field) { + warn_report("%s bit %d of %s is writable but no named field " + "in target/arm/cpu-idregs.h.inc", + __func__, i, reg->name); + map =3D map & ~BIT_ULL(i); + i =3D ctz64(map); + continue; + } + lower =3D field->shift; + upper =3D field->shift + field->length - 1; + prop_name =3D g_strdup_printf("SYSREG_%s_%s", reg->name, field->na= me); + trace_decode_idreg_writemap(field->name, lower, upper, prop_name); + object_property_add(obj, prop_name, "uint64", + get_sysreg_prop, set_sysreg_prop, NULL, field); + g_free(prop_name); + nb_sysreg_props++; + + field_mask =3D MAKE_64BIT_MASK(lower, field->length); + map =3D map & ~field_mask; + i =3D ctz64(map); + } + trace_nb_sysreg_props(reg->name, nb_sysreg_props); + return 0; +} + +/* analyze the writable mask and generate properties for writable fields */ +void kvm_arm_expose_idreg_properties(ARMCPU *cpu, ARM64SysReg *regs) +{ + Object *obj =3D OBJECT(cpu); + + for (int i =3D 0; i < NUM_ID_IDX; i++) { + ARM64SysReg *sysregdesc =3D ®s[i]; + + if (sysregdesc->writable_mask) { + /* + * special case REVIDR_EL1 and AIDR_EL1 which are writable but + * do not expose named fields. They will need to be handled + * separately + */ + if (strcmp(sysregdesc->name, "REVIDR_EL1") && + strcmp(sysregdesc->name, "AIDR_EL1")) { + decode_idreg_writemap(obj, sysregdesc); + } + } + } +} + static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { diff --git a/target/arm/trace-events b/target/arm/trace-events index c25d2a1191..d72ad6b671 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -15,6 +15,10 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_ir= q: timer %d irqstate %d" kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host v= alue for %s is 0x%"PRIx64 kvm_arm_writable_idregs_to_cpreg_list(const char *name, uint64_t previous,= uint64_t new) "%s overwrite default 0x%"PRIx64" with 0x%"PRIx64 +decode_idreg_writemap(const char* name, int lower, int upper, char *prop_n= ame) "%s [%d:%d] is writable (prop %s)" +get_sysreg_prop(const char *name, uint64_t value) "%s 0x%"PRIx64 +set_sysreg_prop(const char *name, uint64_t old, uint64_t mask, uint64_t fi= eld_value, uint64_t new) "%s old reg value=3D0x%"PRIx64" mask=3D0x%"PRIx64"= new field value=3D0x%"PRIx64" new reg value=3D0x%"PRIx64 +nb_sysreg_props(const char *name, int count) "%s: %d SYSREG properties" =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1787737186; cv=none; d=zohomail.com; s=zohoarc; b=n3cpQeH5dvCFWb1Lql4H6cGiNS/jsS6x5lX5Y4kVzkD6CDc/XPWEP2I9Q9qSEpvT7A/MJcCRCPwjd0hvQzsbytdXIJ/5dfCkTP0oF4Zn8sAjQFzinsA6BBflK2IUyG+yODcy4vsw64rxMyKcLxKIA8lBW+GM2y0kZVk8jdyByh8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787737186; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gBiQ/WZ8FDSS7QTiXrmQ5xLbPQJvAU6T5QyffYoE+7o=; b=O6mrktTtXlYlRsDzGHkYLK/XF2OvYZZ7aFkjgmX8HBXoOBqvLnKFYaBBCJPlTOPred+mydlW9oYJPZwX+othdm2gMvrXkf6sXOMHSys7dkP6QE0l2QqAqXP2lsja3GYruXzqvlWTeCag0PmfbT5Qg5efuJqhEaCge+E0QRfHpCI= ARC-Authentication-Results: i=1; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737170; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gBiQ/WZ8FDSS7QTiXrmQ5xLbPQJvAU6T5QyffYoE+7o=; b=RdQaLyQYbT41zBArkYT1dCDeqskYyaKaajoQA9ve6nIyikmsjHlLRbQ49/26PsPAK3b5xQ DGkd2iCzPPH+Eb0lSiQgGIHk/kvJVjiMzIz1DacxvY4eflCkDMkdY2TXRhSbUUgquKZBGX 7jTN8lPFCU2XGA1XJOTx3R3dR5uP/XA= X-MC-Unique: Heccs6UcOpCnlujPZ9KGsA-1 X-Mimecast-MFC-AGG-ID: Heccs6UcOpCnlujPZ9KGsA_1787737163 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 13/20] target/arm/cpu: Expose writable ID reg field properties on the kvm host vcpu model Date: Wed, 26 Aug 2026 11:36:18 +0200 Message-ID: <20260826093747.1670077-14-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737187483158500 Content-Type: text/plain; charset="utf-8" If the host supports KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES and KVM_ARM_GET_REG_WRITABLE_MASKS ioctl successfully retrieved the mask of writable fields for all ID regs, expose uint64 SYSREG properties for all the writable ID reg fields exposed by the host kernel which can be matched in target/arm/cpu-idregs.h.inc. Properties are named SYSREG__ with REG and FIELD being those used ARCHMRS Registers.json. When such properties are set, they override the default field value retrieved from the host and reinjected into KVM. Then the actual value being applied at KVM depends on the register, ie. it can be sanitized. In case the field value is rejected by KVM, the vpcu init fails. Anyway there is a first attempt to write back this value into KVM. Then legacy CPU options (virtualization, secure, ...) can still override the previous value. So low level IDREG field properties apply before the legacy ones. An example of invocation is: -cpu host,SYSREG_ID_AA64MMFR0_EL1_ECV=3D0x0 which sets ECV field of ID_AA64MMFR0_EL1 to 0 (enhanced counter virtualization). Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Sebastian Ott --- v5 -> v6: - do not check writable_map anymore v4 -> v5: - get rid of ret local variable, dynamically allocate and free writable_map here --- target/arm/cpu64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4e8c472530..e04062e848 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -37,6 +37,7 @@ #include "hw/core/qdev-properties.h" #include "internals.h" #include "cpu-features.h" +#include "cpu-idregs.h" =20 /* convert between _IDX and SYS_ */ #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ @@ -807,6 +808,10 @@ void aarch64_host_initfn(Object *obj) kvm_arm_set_cpreg_mig_tolerances(cpu); kvm_arm_set_cpu_features_from_host(cpu); aarch64_add_sve_properties(obj); + + /* generate SYSREG properties according to writable masks */ + kvm_arm_expose_idreg_properties(cpu, arm64_id_regs); + #elif defined(CONFIG_HVF) hvf_arm_set_cpu_features_from_host(cpu); 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737175; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8lbJTdftQ32/6ElYZVmkeNO/8uGOKiFYhP6lbO4BtAo=; b=cq/sU0QHyXWdoE2EdJOny+W21uf+7DYOXBpsVyYq+Pzyu89IEYLhYt8utgqDIKO/3wMiIF 85Sc96q1quYUe2z9/zYsUttIsLzITJ4nOhZ6N5ecyPS+tO1iEOOW/kF7EcuOS/IG34tTPp HqlElOz7UuFtl+myk/ztho/vJkoxD5Y= X-MC-Unique: lmN34gD8N--TP5Qc9eJG_g-1 X-Mimecast-MFC-AGG-ID: lmN34gD8N--TP5Qc9eJG_g_1787737170 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 14/20] target/arm/cpu-idregs.h.inc: Generate reserved fields Date: Wed, 26 Aug 2026 11:36:19 +0200 Message-ID: <20260826093747.1670077-15-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Extract reserved fields: RES0, RES1, RAZ, ... Signed-off-by: Eric Auger --- v7 -> v8: - fix WithShifts issue --- target/arm/cpu-idregs.h.inc | 62 ++++++++++++++ .../update-aarch64-cpu-sysreg-properties.py | 83 +++++++++++++++---- 2 files changed, 131 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu-idregs.h.inc b/target/arm/cpu-idregs.h.inc index 10ddfdf43a..c7e93c48b7 100644 --- a/target/arm/cpu-idregs.h.inc +++ b/target/arm/cpu-idregs.h.inc @@ -15,6 +15,7 @@ IDREG_START(AIDR_EL1) IDREG_END(AIDR_EL1) =20 IDREG_START(CLIDR_EL1) + IDREG_FIELD(CLIDR_EL1, RES0, 47, 17) IDREG_FIELD(CLIDR_EL1, Ttype7, 45, 2) IDREG_FIELD(CLIDR_EL1, Ttype6, 43, 2) IDREG_FIELD(CLIDR_EL1, Ttype5, 41, 2) @@ -45,7 +46,10 @@ IDREG_START(CLIDR_EL1) IDREG_END(CLIDR_EL1) =20 IDREG_START(CTR_EL0) + IDREG_FIELD(CTR_EL0, RES0, 38, 26) IDREG_FIELD(CTR_EL0, TminLine, 32, 6) + IDREG_FIELD(CTR_EL0, RES1, 31, 1) + IDREG_FIELD(CTR_EL0, RES0, 30, 1) IDREG_FIELD_START(CTR_EL0, DIC, 29, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -63,23 +67,28 @@ IDREG_START(CTR_EL0) IDREG_FIELD_ARCH_VAL(2) IDREG_FIELD_ARCH_VAL(3) IDREG_FIELD_END(CTR_EL0, L1Ip) + IDREG_FIELD(CTR_EL0, RES0, 4, 10) IDREG_FIELD(CTR_EL0, IminLine, 0, 4) IDREG_END(CTR_EL0) =20 IDREG_START(DCZID_EL0) + IDREG_FIELD(DCZID_EL0, RES0, 9, 55) IDREG_FIELD(DCZID_EL0, TBS, 5, 4) IDREG_FIELD(DCZID_EL0, DZP, 4, 1) IDREG_FIELD(DCZID_EL0, BS, 0, 4) IDREG_END(DCZID_EL0) =20 IDREG_START(GMID_EL1) + IDREG_FIELD(GMID_EL1, RES0, 4, 60) IDREG_FIELD(GMID_EL1, BS, 0, 4) IDREG_END(GMID_EL1) =20 IDREG_START(ID_AA64AFR0_EL1) + IDREG_FIELD(ID_AA64AFR0_EL1, RES0, 32, 32) IDREG_END(ID_AA64AFR0_EL1) =20 IDREG_START(ID_AA64AFR1_EL1) + IDREG_FIELD(ID_AA64AFR1_EL1, RES0, 0, 64) IDREG_END(ID_AA64AFR1_EL1) =20 IDREG_START(ID_AA64DFR0_EL1) @@ -141,6 +150,7 @@ IDREG_START(ID_AA64DFR0_EL1) IDREG_FIELD_ARCH_VAL(14) IDREG_FIELD_ARCH_VAL(15) IDREG_FIELD_END(ID_AA64DFR0_EL1, CTX_CMPs) + IDREG_FIELD(ID_AA64DFR0_EL1, RES0, 24, 4) IDREG_FIELD_START(ID_AA64DFR0_EL1, WRPs, 20, 4) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_ARCH_VAL(2) @@ -531,6 +541,7 @@ IDREG_START(ID_AA64DFR1_EL1) IDREG_END(ID_AA64DFR1_EL1) =20 IDREG_START(ID_AA64DFR2_EL1) + IDREG_FIELD(ID_AA64DFR2_EL1, RES0, 28, 36) IDREG_FIELD_START(ID_AA64DFR2_EL1, TRBE_EXC, 24, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -543,6 +554,7 @@ IDREG_START(ID_AA64DFR2_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64DFR2_EL1, SPE_EXC) + IDREG_FIELD(ID_AA64DFR2_EL1, RES0, 8, 8) IDREG_FIELD_START(ID_AA64DFR2_EL1, BWE, 4, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -555,6 +567,7 @@ IDREG_START(ID_AA64DFR2_EL1) IDREG_END(ID_AA64DFR2_EL1) =20 IDREG_START(ID_AA64FPFR0_EL1) + IDREG_FIELD(ID_AA64FPFR0_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8CVT, 31, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -579,10 +592,13 @@ IDREG_START(ID_AA64FPFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8MM4) + IDREG_FIELD(ID_AA64FPFR0_EL1, RES0, 16, 10) IDREG_FIELD_START(ID_AA64FPFR0_EL1, F16MM2, 15, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64FPFR0_EL1, F16MM2) + IDREG_FIELD(ID_AA64FPFR0_EL1, RES0, 8, 7) + IDREG_FIELD(ID_AA64FPFR0_EL1, RAZ, 2, 6) IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8E4M3, 1, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -634,6 +650,7 @@ IDREG_START(ID_AA64ISAR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64ISAR0_EL1, RDM) + IDREG_FIELD(ID_AA64ISAR0_EL1, RES0, 24, 4) IDREG_FIELD_START(ID_AA64ISAR0_EL1, Atomic, 20, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(2) @@ -657,6 +674,7 @@ IDREG_START(ID_AA64ISAR0_EL1) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_ARCH_VAL(2) IDREG_FIELD_END(ID_AA64ISAR0_EL1, AES) + IDREG_FIELD(ID_AA64ISAR0_EL1, RES0, 0, 4) IDREG_END(ID_AA64ISAR0_EL1) =20 IDREG_START(ID_AA64ISAR1_EL1) @@ -820,6 +838,7 @@ IDREG_START(ID_AA64ISAR2_EL1) IDREG_END(ID_AA64ISAR2_EL1) =20 IDREG_START(ID_AA64ISAR3_EL1) + IDREG_FIELD(ID_AA64ISAR3_EL1, RES0, 48, 16) IDREG_FIELD_START(ID_AA64ISAR3_EL1, LSCP, 44, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -883,6 +902,7 @@ IDREG_START(ID_AA64MMFR0_EL1) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_ARCH_VAL(2) IDREG_FIELD_END(ID_AA64MMFR0_EL1, FGT) + IDREG_FIELD(ID_AA64MMFR0_EL1, RES0, 48, 8) IDREG_FIELD_START(ID_AA64MMFR0_EL1, ExS, 44, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1035,6 +1055,7 @@ IDREG_START(ID_AA64MMFR2_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64MMFR2_EL1, TTL) + IDREG_FIELD(ID_AA64MMFR2_EL1, RES0, 44, 4) IDREG_FIELD_START(ID_AA64MMFR2_EL1, FWB, 40, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1100,6 +1121,7 @@ IDREG_START(ID_AA64MMFR3_EL1) IDREG_FIELD_ARCH_VAL(2) IDREG_FIELD_ARCH_VAL(3) IDREG_FIELD_END(ID_AA64MMFR3_EL1, SDERR) + IDREG_FIELD(ID_AA64MMFR3_EL1, RES0, 48, 4) IDREG_FIELD_START(ID_AA64MMFR3_EL1, ANERR, 44, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1353,6 +1375,7 @@ IDREG_START(ID_AA64PFR1_EL1) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_ARCH_VAL(2) IDREG_FIELD_END(ID_AA64PFR1_EL1, SME) + IDREG_FIELD(ID_AA64PFR1_EL1, RES0, 20, 4) IDREG_FIELD_START(ID_AA64PFR1_EL1, MPAM_frac, 16, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1380,6 +1403,7 @@ IDREG_START(ID_AA64PFR1_EL1) IDREG_END(ID_AA64PFR1_EL1) =20 IDREG_START(ID_AA64PFR2_EL1) + IDREG_FIELD(ID_AA64PFR2_EL1, RES0, 48, 16) IDREG_FIELD_START(ID_AA64PFR2_EL1, VMTETCL, 44, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1439,6 +1463,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64SMFR0_EL1, FA64) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 62, 1) IDREG_FIELD_START(ID_AA64SMFR0_EL1, LUT6, 61, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1458,6 +1483,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(15) IDREG_FIELD_END(ID_AA64SMFR0_EL1, I16I64) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 49, 3) IDREG_FIELD_START(ID_AA64SMFR0_EL1, F64F64, 48, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1502,6 +1528,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64SMFR0_EL1, F32F32) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 31, 1) IDREG_FIELD_START(ID_AA64SMFR0_EL1, SF8FMA, 30, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1514,6 +1541,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64SMFR0_EL1, SF8DP2) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 26, 2) IDREG_FIELD_START(ID_AA64SMFR0_EL1, SBitPerm, 25, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1526,10 +1554,12 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64SMFR0_EL1, SFEXPA) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 17, 6) IDREG_FIELD_START(ID_AA64SMFR0_EL1, STMOP, 16, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64SMFR0_EL1, STMOP) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 1, 15) IDREG_FIELD_START(ID_AA64SMFR0_EL1, SMOP4, 0, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1537,6 +1567,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_END(ID_AA64SMFR0_EL1) =20 IDREG_START(ID_AA64ZFR0_EL1) + IDREG_FIELD(ID_AA64ZFR0_EL1, RES0, 60, 4) IDREG_FIELD_START(ID_AA64ZFR0_EL1, F64MM, 56, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1557,10 +1588,12 @@ IDREG_START(ID_AA64ZFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64ZFR0_EL1, SM4) + IDREG_FIELD(ID_AA64ZFR0_EL1, RES0, 36, 4) IDREG_FIELD_START(ID_AA64ZFR0_EL1, SHA3, 32, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64ZFR0_EL1, SHA3) + IDREG_FIELD(ID_AA64ZFR0_EL1, RES0, 28, 4) IDREG_FIELD_START(ID_AA64ZFR0_EL1, B16B16, 24, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1580,6 +1613,7 @@ IDREG_START(ID_AA64ZFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64ZFR0_EL1, EltPerm) + IDREG_FIELD(ID_AA64ZFR0_EL1, RES0, 8, 4) IDREG_FIELD_START(ID_AA64ZFR0_EL1, AES, 4, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1596,9 +1630,11 @@ IDREG_START(ID_AA64ZFR0_EL1) IDREG_END(ID_AA64ZFR0_EL1) =20 IDREG_START(ID_AFR0_EL1) + IDREG_FIELD(ID_AFR0_EL1, RES0, 0, 64) IDREG_END(ID_AFR0_EL1) =20 IDREG_START(ID_DFR0_EL1) + IDREG_FIELD(ID_DFR0_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_DFR0_EL1, TraceFilt, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1650,6 +1686,7 @@ IDREG_START(ID_DFR0_EL1) IDREG_END(ID_DFR0_EL1) =20 IDREG_START(ID_DFR1_EL1) + IDREG_FIELD(ID_DFR1_EL1, RES0, 8, 56) IDREG_FIELD_START(ID_DFR1_EL1, HPMN0, 4, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1662,6 +1699,7 @@ IDREG_START(ID_DFR1_EL1) IDREG_END(ID_DFR1_EL1) =20 IDREG_START(ID_ISAR0_EL1) + IDREG_FIELD(ID_ISAR0_EL1, RES0, 28, 36) IDREG_FIELD_START(ID_ISAR0_EL1, Divide, 24, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1697,6 +1735,7 @@ IDREG_START(ID_ISAR0_EL1) IDREG_END(ID_ISAR0_EL1) =20 IDREG_START(ID_ISAR1_EL1) + IDREG_FIELD(ID_ISAR1_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_ISAR1_EL1, Jazelle, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1735,6 +1774,7 @@ IDREG_START(ID_ISAR1_EL1) IDREG_END(ID_ISAR1_EL1) =20 IDREG_START(ID_ISAR2_EL1) + IDREG_FIELD(ID_ISAR2_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_ISAR2_EL1, Reversal, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1780,6 +1820,7 @@ IDREG_START(ID_ISAR2_EL1) IDREG_END(ID_ISAR2_EL1) =20 IDREG_START(ID_ISAR3_EL1) + IDREG_FIELD(ID_ISAR3_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_ISAR3_EL1, T32EE, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1817,6 +1858,7 @@ IDREG_START(ID_ISAR3_EL1) IDREG_END(ID_ISAR3_EL1) =20 IDREG_START(ID_ISAR4_EL1) + IDREG_FIELD(ID_ISAR4_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_ISAR4_EL1, SWP_frac, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1855,6 +1897,7 @@ IDREG_START(ID_ISAR4_EL1) IDREG_END(ID_ISAR4_EL1) =20 IDREG_START(ID_ISAR5_EL1) + IDREG_FIELD(ID_ISAR5_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_ISAR5_EL1, VCMA, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1863,6 +1906,7 @@ IDREG_START(ID_ISAR5_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_ISAR5_EL1, RDM) + IDREG_FIELD(ID_ISAR5_EL1, RES0, 20, 4) IDREG_FIELD_START(ID_ISAR5_EL1, CRC32, 16, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1887,6 +1931,7 @@ IDREG_START(ID_ISAR5_EL1) IDREG_END(ID_ISAR5_EL1) =20 IDREG_START(ID_ISAR6_EL1) + IDREG_FIELD(ID_ISAR6_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_ISAR6_EL1, CLRBHB, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1923,6 +1968,7 @@ IDREG_START(ID_ISAR6_EL1) IDREG_END(ID_ISAR6_EL1) =20 IDREG_START(ID_MMFR0_EL1) + IDREG_FIELD(ID_MMFR0_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_MMFR0_EL1, InnerShr, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1969,6 +2015,7 @@ IDREG_START(ID_MMFR0_EL1) IDREG_END(ID_MMFR0_EL1) =20 IDREG_START(ID_MMFR1_EL1) + IDREG_FIELD(ID_MMFR1_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_MMFR1_EL1, BPred, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2017,6 +2064,7 @@ IDREG_START(ID_MMFR1_EL1) IDREG_END(ID_MMFR1_EL1) =20 IDREG_START(ID_MMFR2_EL1) + IDREG_FIELD(ID_MMFR2_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_MMFR2_EL1, HWAccFlg, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2055,6 +2103,7 @@ IDREG_START(ID_MMFR2_EL1) IDREG_END(ID_MMFR2_EL1) =20 IDREG_START(ID_MMFR3_EL1) + IDREG_FIELD(ID_MMFR3_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_MMFR3_EL1, Supersec, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(15) @@ -2094,6 +2143,7 @@ IDREG_START(ID_MMFR3_EL1) IDREG_END(ID_MMFR3_EL1) =20 IDREG_START(ID_MMFR4_EL1) + IDREG_FIELD(ID_MMFR4_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_MMFR4_EL1, EVT, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2131,6 +2181,7 @@ IDREG_START(ID_MMFR4_EL1) IDREG_END(ID_MMFR4_EL1) =20 IDREG_START(ID_MMFR5_EL1) + IDREG_FIELD(ID_MMFR5_EL1, RES0, 8, 56) IDREG_FIELD_START(ID_MMFR5_EL1, nTLBPA, 4, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2144,6 +2195,7 @@ IDREG_START(ID_MMFR5_EL1) IDREG_END(ID_MMFR5_EL1) =20 IDREG_START(ID_PFR0_EL1) + IDREG_FIELD(ID_PFR0_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_PFR0_EL1, RAS, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2185,6 +2237,7 @@ IDREG_START(ID_PFR0_EL1) IDREG_END(ID_PFR0_EL1) =20 IDREG_START(ID_PFR1_EL1) + IDREG_FIELD(ID_PFR1_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_PFR1_EL1, GIC, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2224,6 +2277,7 @@ IDREG_START(ID_PFR1_EL1) IDREG_END(ID_PFR1_EL1) =20 IDREG_START(ID_PFR2_EL1) + IDREG_FIELD(ID_PFR2_EL1, RES0, 12, 52) IDREG_FIELD_START(ID_PFR2_EL1, RAS_frac, 8, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2271,11 +2325,14 @@ IDREG_START(MIDR_EL1) IDREG_END(MIDR_EL1) =20 IDREG_START(MPIDR_EL1) + IDREG_FIELD(MPIDR_EL1, RES0, 40, 24) IDREG_FIELD(MPIDR_EL1, Aff3, 32, 8) + IDREG_FIELD(MPIDR_EL1, RES1, 31, 1) IDREG_FIELD_START(MPIDR_EL1, U, 30, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(MPIDR_EL1, U) + IDREG_FIELD(MPIDR_EL1, RES0, 25, 5) IDREG_FIELD_START(MPIDR_EL1, MT, 24, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2286,6 +2343,7 @@ IDREG_START(MPIDR_EL1) IDREG_END(MPIDR_EL1) =20 IDREG_START(MVFR0_EL1) + IDREG_FIELD(MVFR0_EL1, RES0, 32, 32) IDREG_FIELD_START(MVFR0_EL1, FPRound, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2324,6 +2382,7 @@ IDREG_START(MVFR0_EL1) IDREG_END(MVFR0_EL1) =20 IDREG_START(MVFR1_EL1) + IDREG_FIELD(MVFR1_EL1, RES0, 32, 32) IDREG_FIELD_START(MVFR1_EL1, SIMDFMAC, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2362,6 +2421,7 @@ IDREG_START(MVFR1_EL1) IDREG_END(MVFR1_EL1) =20 IDREG_START(MVFR2_EL1) + IDREG_FIELD(MVFR2_EL1, RES0, 8, 56) IDREG_FIELD_START(MVFR2_EL1, FPMisc, 4, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2381,6 +2441,7 @@ IDREG_START(REVIDR_EL1) IDREG_END(REVIDR_EL1) =20 IDREG_START(SMIDR_EL1) + IDREG_FIELD(SMIDR_EL1, RES0, 60, 4) IDREG_FIELD_START(SMIDR_EL1, NSMC, 56, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2445,6 +2506,7 @@ IDREG_START(SMIDR_EL1) IDREG_FIELD_ARCH_VAL(2) IDREG_FIELD_ARCH_VAL(3) IDREG_FIELD_END(SMIDR_EL1, SH) + IDREG_FIELD(SMIDR_EL1, RES0, 12, 1) IDREG_FIELD(SMIDR_EL1, Affinity, 0, 12) IDREG_END(SMIDR_EL1) =20 diff --git a/scripts/update-aarch64-cpu-sysreg-properties.py b/scripts/upda= te-aarch64-cpu-sysreg-properties.py index 96f8aa2d64..0b4e4d3e0c 100644 --- a/scripts/update-aarch64-cpu-sysreg-properties.py +++ b/scripts/update-aarch64-cpu-sysreg-properties.py @@ -81,9 +81,13 @@ def collect_fields(item, bit_offset=3D0): =20 # Normal Field Types leaf_types =3D ['Fields.Field', 'Fields.ConstantField', - 'Fields.EnumeratedField', 'Fields.Bitfield'] + 'Fields.EnumeratedField', 'Fields.Bitfield', 'Fields.Res= erved'] if _type in leaf_types: field_copy =3D item.copy() + + if _type =3D=3D 'Fields.Reserved' and not field_copy.get('name'): + field_copy['name'] =3D item.get('value', 'RES0') + if field_copy.get('rangeset'): new_ranges =3D [] for r in field_copy['rangeset']: @@ -96,7 +100,7 @@ def collect_fields(item, bit_offset=3D0): return fields =20 # Traverse the hierarchy for other cases - for key in ['fields', 'values', 'fieldsets']: + for key in ['fields', 'values', 'fieldsets', 'constants']: for nested in item.get(key, []): fields.extend(collect_fields(nested, bit_offset)) =20 @@ -171,45 +175,96 @@ def generate_sysreg_properties_from_registers_json(id= _reg_names, raw_json_path): =20 final_output +=3D f"IDREG_START({reg_name})\n" =20 - unique_fields =3D {} + fieldset_variants =3D [] + for fieldset in register.get('fieldsets', []): + current_fieldset_fields =3D {} candidates =3D collect_fields(fieldset) + for val in candidates: - name =3D (val.get('name') or val.get('label', '')).strip() - if not name or "RESERVED" in name.upper(): + raw_name =3D val.get('name') or val.get('label') or val.ge= t('value') or '' + name =3D raw_name.strip() + if not name: continue + + name_upper =3D name.upper() + + # Check for architectural target states, including UNKNOWN= remapping + base_reserved =3D None + for r_type in ["RES0", "RES1", "RAZ", "RAO", "WI", "UNKNOW= N"]: + if r_type =3D=3D name_upper: + base_reserved =3D "RES0" if r_type =3D=3D "UNKNOWN= " else r_type + break + + is_valid_reserved =3D base_reserved is not None + if "RESERVED" in name_upper and not is_valid_reserved: + continue + + # Force naming uniformity across padding blocks + if is_valid_reserved: + name =3D base_reserved + for r in val.get('rangeset', []): lsb =3D int(r.get('start')) width =3D r.get('width') msb =3D lsb + int(width) - 1 =20 - # Only keep the fields with the highest MSB - # needed fir CCSIDR_EL1 - if name not in unique_fields or msb > unique_fields[na= me]['msb']: - # extract enum values if any + if is_valid_reserved: + unique_key =3D f"{name}_{lsb}" + else: + unique_key =3D name + + if unique_key not in current_fieldset_fields or \ + msb > current_fieldset_fields[unique_key]['msb']: enums =3D extract_field_enums(val) - unique_fields[name] =3D {'lsb': lsb, 'msb': msb, '= width': width, 'enums': enums} + current_fieldset_fields[unique_key] =3D { + 'raw_name': name, + 'lsb': lsb, + 'msb': msb, + 'width': width, + 'enums': enums + } + + if current_fieldset_fields: + fieldset_variants.append(current_fieldset_fields) + + best_fieldset =3D {} + max_total_width =3D -1 + + for variant in fieldset_variants: + total_width =3D sum(f['width'] for f in variant.values()) + # prioritize layout variants with the highest MSB coverage + max_msb =3D max(f['msb'] for f in variant.values()) if variant= else 0 + + # Combine width and max_msb into a fitness score tuple + if (total_width, max_msb) > (max_total_width, max_total_width): + max_total_width =3D total_width + best_fieldset =3D variant + + unique_fields =3D best_fieldset =20 # Sort decreasing lsbs sorted_fields =3D sorted(unique_fields.items(), key=3Dlambda x: x[1]['lsb'], reverse=3DTrue) =20 - for name, bits in sorted_fields: + for unique_key, bits in sorted_fields: enums_list =3D bits.get('enums', []) =20 + clean_name =3D bits.get('raw_name', unique_key) + if enums_list: line =3D (f" IDREG_FIELD_START({reg_name}, " - f"{name}, {bits['lsb']}, {bits['width']})\n") + f"{clean_name}, {bits['lsb']}, {bits['width']})\n") else: line =3D (f" IDREG_FIELD({reg_name}, " - f"{name}, {bits['lsb']}, {bits['width']})\n") + f"{clean_name}, {bits['lsb']}, {bits['width']})\n") final_output +=3D line # generate enum value or range if any for enum_item in enums_list: final_output +=3D (f" IDREG_FIELD_ARCH_VAL({enu= m_item['value']})\n") =20 if enums_list: - line =3D (f" IDREG_FIELD_END({reg_name}, {name})\n") + line =3D (f" IDREG_FIELD_END({reg_name}, {clean_name})\n= ") final_output +=3D line =20 final_output +=3D f"IDREG_END({reg_name})\n" --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org 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2026 09:39:36 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.48.93]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 745A11955F05; Wed, 26 Aug 2026 09:39:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737185; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S9NW8uY0H3t/xMF0HVs8RIaDYTYa9wgmnjlDh5j8iNs=; b=PJOlYetlX5l0NvLAyzgQwbfoFtV5UORJcs1uWwBc2bn5xbaLXGWAWIEcSbgBVqoY9ugI4i XHBTcSKN/P23kYm12QioN99Kvwyd6wfKDEaxd0YGZvwcwBGGeQpZ57EZ0GbC5dew79rGVP tlNO4srs5FwtyTKwVliE82GeQH7YyyI= X-MC-Unique: WoproYHEMNCcFKubrG-GRA-1 X-Mimecast-MFC-AGG-ID: WoproYHEMNCcFKubrG-GRA_1787737176 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 15/20] target/arm/kvm: Ignore and trace unexpected writable reserved fields Date: Wed, 26 Aug 2026 11:36:20 +0200 Message-ID: <20260826093747.1670077-16-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737193434158500 Content-Type: text/plain; charset="utf-8" KVM currently reports some bits as writable whereas they are RES0 or RAZ. The code easily allows to do some sanity checking for such inconsistencies. Let's add a trace event when this is encountered and skip the field Signed-off-by: Eric Auger --- target/arm/kvm.c | 8 ++++++++ target/arm/trace-events | 1 + 2 files changed, 9 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 2557d7b0d9..8ec9bc51cd 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -433,6 +433,14 @@ decode_idreg_writemap(Object *obj, ARM64SysReg *reg) } lower =3D field->shift; upper =3D field->shift + field->length - 1; + + /* Sanity check the field is not a reserved field */ + if (strstr(field->name, "RES0") || strstr(field->name, "RES1") || + strstr(field->name, "RAZ")) { + trace_unexpected_writable_reserved_field(reg->name, field->nam= e, + lower, upper); + continue; + } prop_name =3D g_strdup_printf("SYSREG_%s_%s", reg->name, field->na= me); trace_decode_idreg_writemap(field->name, lower, upper, prop_name); object_property_add(obj, prop_name, "uint64", diff --git a/target/arm/trace-events b/target/arm/trace-events index d72ad6b671..e67730de6b 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -19,6 +19,7 @@ decode_idreg_writemap(const char* name, int lower, int up= per, char *prop_name) " get_sysreg_prop(const char *name, uint64_t value) "%s 0x%"PRIx64 set_sysreg_prop(const char *name, uint64_t old, uint64_t mask, uint64_t fi= eld_value, uint64_t new) "%s old reg value=3D0x%"PRIx64" mask=3D0x%"PRIx64"= new field value=3D0x%"PRIx64" new reg value=3D0x%"PRIx64 nb_sysreg_props(const char *name, int count) "%s: %d SYSREG properties" +unexpected_writable_reserved_field(const char *reg_name, const char *field= _name, int lower, int upper) "Unexpected writable reserved field: %s.%s [%d= ,%d], skip it ..." =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737188; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7t3/6OthMgSGaRs8vrnLHPfTMlQhBxcgyyk0T/BvuEc=; b=Qt1yr5hPq36zA+gf06MxWYFwV8sOBRQ/ckNjkXkddEw17tmYPibsHnS7X3RU/a+xtvsKI5 MO3gr6MCvzQSktUGf3fyZVx2jgoWPKwsY4pRW1YTgZQf9QqUsPTQYf0FxXkomzq+iuDQhq sZ2BffwuITdVHxo3nBfiJxkLyjXiTF0= X-MC-Unique: fHTHykNoM_y9GBVVYCw2jQ-1 X-Mimecast-MFC-AGG-ID: fHTHykNoM_y9GBVVYCw2jQ_1787737183 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 16/20] arm/cpu-features: document ID reg properties Date: Wed, 26 Aug 2026 11:36:21 +0200 Message-ID: <20260826093747.1670077-17-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737197616158500 Content-Type: text/plain; charset="utf-8" From: Cornelia Huck Add some documentation for how individual ID registers can be configured with the host cpu model. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Sebastian Ott --- docs/system/arm/cpu-features.rst | 106 ++++++++++++++++++++++++++++--- 1 file changed, 98 insertions(+), 8 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 10b0eff27e..3a07a87bc3 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -2,7 +2,10 @@ Arm CPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 CPU features are optional features that a CPU of supporting type may -choose to implement or not. In QEMU, optional CPU features have +choose to implement or not. QEMU provides two different mechanisms +to configure those features: + +1. For most CPU models, optional CPU features may have corresponding boolean CPU proprieties that, when enabled, indicate that the feature is implemented, and, conversely, when disabled, indicate that it is not implemented. An example of an Arm CPU feature @@ -31,6 +34,18 @@ running guests in AArch32. CPU features that are inherently specific to KVM are prefixed with "kvm-" and are described in "KVM VCPU Features". =20 +2. Additionally, the ``host`` CPU model on KVM allows to configure optional +CPU features via the corresponding ID registers. The host kernel allows +to write a subset of ID register fields. The host model exposes +properties for each writable ID register field. Those options are named +SYSREG__. IDREG and FIELD names are those used in the +ARM Architecture Reference Manual. Their availability depend on the host +capability to let the userspace write those fields. Values set with those +properties override the initial values retrieved from the host. They are +written back to KVM and the eventual value applied by KVM depends on wheth= er +the value is sanitized or not by the host kernel. Then those field values +are likely to be overriden again by legacy CPU options which apply at the = end. + CPU Feature Probing =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -126,13 +141,20 @@ A note about CPU models and KVM =20 Named CPU models generally do not work with KVM. There are a few cases that do work, e.g. using the named CPU model ``cortex-a57`` with KVM on a -seattle host, but mostly if KVM is enabled the ``host`` CPU type must be -used. This means the guest is provided all the same CPU features as the -host CPU type has. And, for this reason, the ``host`` CPU type should -enable all CPU features that the host has by default. Indeed it's even -a bit strange to allow disabling CPU features that the host has when using -the ``host`` CPU type, but in the absence of CPU models it's the best we c= an -do if we want to launch guests without all the host's CPU features enabled. +seattle host, but mostly if KVM is enabled, the ``host`` CPU model must be +used. + +Using the ``host`` type means the guest is provided all the same CPU +features as the host CPU type has. And, for this reason, the ``host`` +CPU type should enable all CPU features that the host has by default. + +In case some features need to be hidden from the guest, and the host kernel +supports it, the ``host`` model can be instructed to disable individual +ID register values. This is especially useful for migration purposes. +However, this interface will not allow configuring an arbitrary set of +features; the ID registers must describe a subset of the host's features, +and all differences to the host's configuration must actually be supported +by the kernel to be deconfigured. =20 Enabling KVM also affects the ``query-cpu-model-expansion`` QMP command. = The affect is not only limited to specific features, as pointed out in example @@ -169,6 +191,13 @@ disabling many SVE vector lengths would be quite verbo= se, the ``sve`` CPU properties have special semantics (see "SVE CPU Property Parsing Semantics"). =20 +Additionally, if supported by KVM on the host kernel, the ``host`` CPU mod= el +may be configured via individual ID register field properties, for example= :: + + $ qemu-system-aarch64 -M virt -cpu host,SYSREG_ID_AA64ISAR0_EL1_DP=3D0x0 + +This forces ID_AA64ISAR0_EL1 DP field to 0. + KVM VCPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -495,3 +524,64 @@ Legal values for ``S`` are 30, 34, 36, and 39; the def= ault is 30. =20 As with ``x-rme``, the ``x-l0gptsz`` property may be renamed or removed in some future QEMU release. + +Configuring CPU features via ID register fields +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Note that this is currently only supported under KVM, and with the +``host`` CPU model. + +Querying available ID register fields +------------------------------------- + +QEMU will create properties for all ID register fields that are +reported as being writable by the kernel, and that are known to the +QEMU instance. Therefore, the same QEMU binary may expose different +properties when run under a different kernel. + +To find out all available writable ID register fields, use the +``query-cpu-model-expansion`` QMP command:: + + (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host"} + {"return": { + "model": {"name": "host", "props": { + "SYSREG_ID_AA64PFR0_EL1_EL3": 1, "SYSREG_ID_AA64ISAR2_EL1_CLRBHB": 0, + "SYSREG_CTR_EL0_L1Ip": 3, "SYSREG_CTR_EL0_DminLine": 4, + "SYSREG_ID_AA64MMFR0_EL1_BIGEND": 1, "SYSREG_ID_AA64MMFR1_EL1_ECBHB": 0, + "SYSREG_ID_AA64MMFR2_EL1_CnP": 1, "SYSREG_ID_DFR0_EL1_PerfMon": 4, + "SYSREG_ID_AA64PFR0_EL1_DIT": 0, "SYSREG_ID_AA64MMFR1_EL1_HAFDBS": 2, + "SYSREG_ID_AA64ISAR0_EL1_FHM": 0, "SYSREG_ID_AA64ISAR2_EL1_CSSC": 0, + "SYSREG_ID_AA64ISAR0_EL1_DP": 1, (...) + }}}} + +If a certain field in an ID register does not show up in this list, it +is not writable with the specific host kernel. + +A note on compatibility +----------------------- + +A common use case for providing a defined set of ID register values is +to be able to present a fixed set of features to a guest, often referred +to as "stable guest ABI". This may take the form of ironing out differences +between two similar CPUs with the intention of being able to migrate +between machines with those CPUs, or providing the same CPU across Linux +kernel updates on the host. + +Over the course of time, the Linux kernel is changing the set of ID regist= er +fields that are writable by userspace. Newly introduced writable ID +registers should be initialized to 0 to ensure compatibility. However, ID +registers that have already been introduced that undergo a change as to +which fields are writable may introduce incompatibilities that need to be +addressed on a case-by-case basis for the systems that you wish to migrate +inbetween. + +A note on Arm CPU features (FEAT_xxx) +------------------------------------- + +Configuring CPUs is done on a feature level on other architectures, and th= is +would imply configuring FEAT_xxx values on Arm. However, differences betwe= en +CPUs may not map to FEAT_xxx, but to differences in other registers in the +ID register range; for example, differences in the cache architecture expo= sed +via ``CTR_EL0``. We therefore cannot rely on configuration via FEAT_xxx. A +feature-based interface more similar to other architectures may be impleme= nted +on top of the ID register interface in the future. --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1787737221; cv=none; d=zohomail.com; s=zohoarc; b=EM/rNH4FOhFc+U2Naj3nocxbqaEN4HrIwEk8CW2LcRUZPG91Prsr7Bd6inYqSP7WhOJ9d/pmiUqCqHDUjGoGVSrVf+ZvgcWm1W465tIUG4bkVhi9OH6jmbYxunZM9zKHrDWeMnbFcYFNMg4bp7DDChGtGhuOkwiDtwzJPysntZM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787737221; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 26 Aug 2026 09:39:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737195; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=akwd9qnyOgB/+NOpR7ufAEDjrr9laviPT/bwUHPvhIQ=; b=UVtMRDWAQvpTHa5LEgnCAg8hiI8iFpyIUG7rTln5L5ytd3tlPRFXbiqSdFQ0go07EWak2Q 0cElCu/aU/04Dm/N48t/fuq1Mji1Dhl/FfqMno32QG9I8nyyyp5jVrYivqBEfjHcKJEbID sH8OXVgD+AobKkUkySVvJ9w5ZK7+ysI= X-MC-Unique: W-BwHplmNR-QufqqTa6UgQ-1 X-Mimecast-MFC-AGG-ID: W-BwHplmNR-QufqqTa6UgQ_1787737189 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 17/20] target/arm/kvm: add utility to write idregs in scratch vcpu Date: Wed, 26 Aug 2026 11:36:22 +0200 Message-ID: <20260826093747.1670077-18-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737221659158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Eric Auger --- target/arm/kvm_arm.h | 3 +++ target/arm/kvm-stub.c | 6 +++++ target/arm/kvm.c | 51 +++++++++++++++++++++++++++++++++++++++++ target/arm/trace-events | 1 + 4 files changed, 61 insertions(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 2b3474cc36..68e0597ac6 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -250,4 +250,7 @@ void arm_gic_cap_kvm_probe(GICCapability *v2, GICCapabi= lity *v3); */ char *kvm_print_register_name(uint64_t regidx); =20 +bool kvm_idreg_write_scratch_vcpu(int cpufd, Visitor *v, const char *name, + void *opaque, Error **errp); + #endif diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 88cbe8d85c..264938d2c5 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -119,3 +119,9 @@ char *kvm_print_register_name(uint64_t regidx) { g_assert_not_reached(); } + +bool kvm_idreg_write_scratch_vcpu(int cpufd, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + g_assert_not_reached(); +} diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 8ec9bc51cd..bb1c49d44e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -340,6 +340,57 @@ static ARM64SysRegField *get_field(int i, ARM64SysReg = *reg) return NULL; } =20 +bool kvm_idreg_write_scratch_vcpu(int cpufd, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARM64SysRegField *field =3D (ARM64SysRegField *)opaque; + uint64_t mask, old_reg_val, new_reg_val, oldfv, newfv; + struct kvm_one_reg reg; + int lower =3D field->shift; + int length =3D field->length; + int index =3D field->index; + uint64_t kidx; + int ret; + + mask =3D MAKE_64BIT_MASK(lower, length); + + if (!visit_type_uint64(v, name, &newfv, errp)) { + return false; + } + + kidx =3D idregs_sysreg_to_kvm_reg(id_register_sysreg[index]); + ret =3D read_sys_reg64(cpufd, &old_reg_val, kidx); + if (ret) { + error_setg(errp, "failed to read the scratch vcpu value for field = %s %m", + field->name); + return false; + } + oldfv =3D (old_reg_val & mask) >> lower; + + new_reg_val =3D old_reg_val & ~mask; + new_reg_val |=3D newfv << lower; + + reg.id =3D kidx; + reg.addr =3D (uintptr_t)&new_reg_val; + ret =3D ioctl(cpufd, KVM_SET_ONE_REG, ®); + if (ret) { + error_setg(errp, "failed to apply new value 0x%"PRIx64" for field = %s " + "(previous is 0x%"PRIx64"): %m", newfv, field->name, ol= dfv); + return false; + } else { + uint64_t check_val, actualfv; + + ret =3D read_sys_reg64(cpufd, &check_val, kidx); + if (ret) { + error_setg(errp, "failed to read the new reg value: %m"); + return false; + } + actualfv =3D (check_val & mask) >> lower; + trace_kvm_idreg_write_scratch_vcpu(field->name, oldfv, newfv, actu= alfv); + } + return true; +} + static void set_sysreg_prop(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) diff --git a/target/arm/trace-events b/target/arm/trace-events index e67730de6b..71a2f5770c 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -20,6 +20,7 @@ get_sysreg_prop(const char *name, uint64_t value) "%s 0x%= "PRIx64 set_sysreg_prop(const char *name, uint64_t old, uint64_t mask, uint64_t fi= eld_value, uint64_t new) "%s old reg value=3D0x%"PRIx64" mask=3D0x%"PRIx64"= new field value=3D0x%"PRIx64" new reg value=3D0x%"PRIx64 nb_sysreg_props(const char *name, int count) "%s: %d SYSREG properties" unexpected_writable_reserved_field(const char *reg_name, const char *field= _name, int lower, int upper) "Unexpected writable reserved field: %s.%s [%d= ,%d], skip it ..." +kvm_idreg_write_scratch_vcpu(const char *name, uint64_t oldfv, uint64_t ne= wfv, uint64_t actualfv) "successful dry-run for %s old=3D0x%"PRIx64" new=3D= 0x%"PRIx64" actual=3D0x%"PRIx64 =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1787737201; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zFQHAYBHdMrAddfCZsE2VY/tTxCJjg9UL5w6n7EyOeI=; b=PrTxAaAKJwdMyWvIZIQuXDDTc2Yv/7wxXzdK6hEK1hxsaAoAxAoAGL2g18XyOFIxBIXnA9 OXZt/ktJIyicODMd/G0/bxhA9Y/sotC/Fupp18q40Ma4i6zwPa/Il2AuGHc4hXXkSg36Xs bysYRvj5B+K9yJfP4NlK8Zco68Tcng0= X-MC-Unique: X06uXtpaP-W0K_KVH06BYQ-1 X-Mimecast-MFC-AGG-ID: X06uXtpaP-W0K_KVH06BYQ_1787737195 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 18/20] target/arm/kvm: Add an error handle to kvm_arm_create_scratch_host_vcpu Date: Wed, 26 Aug 2026 11:36:23 +0200 Message-ID: <20260826093747.1670077-19-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1787737237689158500 Content-Type: text/plain; charset="utf-8" This allows to report a precise error message if any error occurs. Signed-off-by: Eric Auger --- target/arm/kvm_arm.h | 3 ++- target/arm/kvm.c | 15 ++++++++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 68e0597ac6..d049334d6d 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -105,6 +105,7 @@ struct kvm_vcpu_init; * @init: filled in with the necessary values for creating a host * vcpu. If NULL is provided, will not init the vCPU (though the cpufd * will still be set up). + * @errp: Error handle * * Create a scratch vcpu in its own VM of the type preferred by the host * kernel (as would be used for '-cpu host'), for purposes of probing it @@ -114,7 +115,7 @@ struct kvm_vcpu_init; * false on failure (and fdarray and init are not valid). */ bool kvm_arm_create_scratch_host_vcpu(int *fdarray, - struct kvm_vcpu_init *init); + struct kvm_vcpu_init *init, Error **= errp); =20 /** * kvm_arm_destroy_scratch_host_vcpu: diff --git a/target/arm/kvm.c b/target/arm/kvm.c index bb1c49d44e..8a7f5982fb 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -107,13 +107,14 @@ static int kvm_arm_vcpu_finalize(ARMCPU *cpu, int fea= ture) } =20 bool kvm_arm_create_scratch_host_vcpu(int *fdarray, - struct kvm_vcpu_init *init) + struct kvm_vcpu_init *init, Error **= errp) { int ret =3D 0, kvmfd =3D -1, vmfd =3D -1, cpufd =3D -1; int max_vm_pa_size; =20 kvmfd =3D qemu_open_old("/dev/kvm", O_RDWR); if (kvmfd < 0) { + error_setg(errp, "Failed opening /dev/kvm"); goto err; } max_vm_pa_size =3D ioctl(kvmfd, KVM_CHECK_EXTENSION, KVM_CAP_ARM_VM_IP= A_SIZE); @@ -124,6 +125,7 @@ bool kvm_arm_create_scratch_host_vcpu(int *fdarray, vmfd =3D ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size); } while (vmfd =3D=3D -1 && errno =3D=3D EINTR); if (vmfd < 0) { + error_setg(errp, "Failed creating the scratch VM"); goto err; } =20 @@ -143,6 +145,7 @@ bool kvm_arm_create_scratch_host_vcpu(int *fdarray, =20 cpufd =3D ioctl(vmfd, KVM_CREATE_VCPU, 0); if (cpufd < 0) { + error_setg(errp, "Failed creating the scratch VCPU"); goto err; } =20 @@ -156,12 +159,14 @@ bool kvm_arm_create_scratch_host_vcpu(int *fdarray, =20 ret =3D ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, &preferred); if (ret < 0) { + error_setg(errp, "Failed getting the preferred target"); goto err; } init->target =3D preferred.target; } ret =3D ioctl(cpufd, KVM_ARM_VCPU_INIT, init); if (ret < 0) { + error_setg(errp, "Failed the init of the scratch vcpu"); goto err; } =20 @@ -542,6 +547,7 @@ kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) bool el2_supported; bool pmu_supported =3D false; uint64_t features =3D 0; + Error *local_err =3D NULL; int err; =20 ahcf->target =3D QEMU_KVM_ARM_TARGET_NONE; @@ -589,7 +595,8 @@ kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) features |=3D 1ULL << ARM_FEATURE_PMU; } =20 - if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init)) { + if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init, &local_err)) { + error_report_err(local_err); return; } =20 @@ -2956,8 +2963,10 @@ void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int= level) void arm_gic_cap_kvm_probe(GICCapability *v2, GICCapability *v3) { int fdarray[3]; + Error *err =3D NULL; =20 - if (!kvm_arm_create_scratch_host_vcpu(fdarray, NULL)) { + if (!kvm_arm_create_scratch_host_vcpu(fdarray, NULL, &err)) { + error_report_err(err); return; } =20 --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" This helper calls kvm_arm_create_scratch_host_vcpu() with preferred target and kvm_vcpu_init.features[0] set with SVE, EL2, PMUv3 and PAUTH if the associated feature caps are advertised by KVM. The new helper gets used in kvm_arm_get_host_cpu_features for now. Signed-off-by: Eric Auger --- target/arm/kvm_arm.h | 20 ++++++++ target/arm/kvm-stub.c | 7 +++ target/arm/kvm.c | 108 +++++++++++++++++++++++------------------- 3 files changed, 86 insertions(+), 49 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index d049334d6d..aafb3cd232 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -125,6 +125,26 @@ bool kvm_arm_create_scratch_host_vcpu(int *fdarray, */ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); =20 +/** + * kvm_arm_create_scratch_max_host_vcpu: + * @fdarray: filled in with kvmfd, vmfd, cpufd file descriptors in that or= der + * @init_features0: kvm_vcpu_init.features[0] feature flags used during + * the init + * @target: target eventually chosen + * @errp: Error handle + * + * calls kvm_arm_create_scratch_host_vcpu() with kvm_vcpu_init initialized + * with all max kvm capabilities supported by the platform among + * KVM_CAP_ARM_PMU_V3, KVM_CAP_ARM_SVE, KVM_CAP_ARM_PTRAUTH_ADDRESS, + * KVM_CAP_ARM_PTRAUTH_GENERIC, KVM_CAP_ARM_EL2 + * + * Returns: true on success (and fdarray and init are filled in), + * false on failure (and fdarray and init are not valid). + */ +bool kvm_arm_create_scratch_max_host_vcpu(int *fdarray, + uint32_t *init_features0, + uint32_t *target, Error **errp); + /** * kvm_arm_set_cpu_features_from_host: * @cpu: ARMCPU to set the features for diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 264938d2c5..0d6c841a24 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -125,3 +125,10 @@ bool kvm_idreg_write_scratch_vcpu(int cpufd, Visitor *= v, const char *name, { g_assert_not_reached(); } + +bool kvm_arm_create_scratch_max_host_vcpu(int *fdarray, + uint32_t *init_features0, + uint32_t *target, Error **errp) +{ + g_assert_not_reached(); +} diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 8a7f5982fb..e3a0dc07de 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -200,6 +200,46 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) } } =20 +static bool kvm_arm_pauth_supported(void) +{ + return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) && + kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); +} + +bool kvm_arm_create_scratch_max_host_vcpu(int *fdarray, + uint32_t *init_features, + uint32_t *target, Error **errp) +{ + struct kvm_vcpu_init init =3D { .target =3D -1, }; + bool ret; + + if (!kvm_enabled()) { + return false; + } + + if (kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE)) { + init.features[0] |=3D 1 << KVM_ARM_VCPU_SVE; + } + if (kvm_arm_el2_supported()) { + init.features[0] |=3D 1 << KVM_ARM_VCPU_HAS_EL2; + } + if (kvm_arm_pauth_supported()) { + init.features[0] |=3D (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | + 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); + } + if (kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3)) { + init.features[0] |=3D 1 << KVM_ARM_VCPU_PMU_V3; + } + + ret =3D kvm_arm_create_scratch_host_vcpu(fdarray, &init, errp); + + if (ret) { + *init_features =3D init.features[0]; + *target =3D init.target; + } + return ret; +} + static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) { uint64_t ret; @@ -223,13 +263,6 @@ static int read_sys_reg64(int fd, uint64_t *pret, uint= 64_t id) return ioctl(fd, KVM_GET_ONE_REG, &idreg); } =20 -static bool kvm_arm_pauth_supported(void) -{ - return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) && - kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); -} - - static uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg) { return ARM64_SYS_REG((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> CP_REG= _ARM64_SYSREG_OP0_SHIFT, @@ -543,11 +576,11 @@ kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahc= f) * and then query that CPU for the relevant ID registers. */ int fdarray[3]; - bool sve_supported; - bool el2_supported; - bool pmu_supported =3D false; + bool sve_supported, pmu_supported; + uint32_t init_features0 =3D 0; uint64_t features =3D 0; Error *local_err =3D NULL; + uint32_t target; int err; =20 ahcf->target =3D QEMU_KVM_ARM_TARGET_NONE; @@ -558,48 +591,25 @@ kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahc= f) } =20 /* - * target =3D -1 informs kvm_arm_create_scratch_host_vcpu() - * to use the preferred target + * Instantiate a scratch vcpu of preferred target with the following + * features, if advertised by KVM: + * SVE (so that ID_AA64ZFR0 can be queried, otherwise RAS), PMUv3, EL2, + * PAUTH (to get the unsanitized field values for AA64ISAR1_EL1) */ - struct kvm_vcpu_init init =3D { .target =3D -1, }; - - /* - * Ask for SVE if supported, so that we can query ID_AA64ZFR0, - * which is otherwise RAZ. - */ - sve_supported =3D kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); - if (sve_supported) { - init.features[0] |=3D 1 << KVM_ARM_VCPU_SVE; - } - - /* - * Ask for EL2 if supported. - */ - el2_supported =3D kvm_arm_el2_supported(); - if (el2_supported) { - init.features[0] |=3D 1 << KVM_ARM_VCPU_HAS_EL2; - } - - /* - * Ask for Pointer Authentication if supported, so that we get - * the unsanitized field values for AA64ISAR1_EL1. - */ - if (kvm_arm_pauth_supported()) { - init.features[0] |=3D (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | - 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); - } - - if (kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3)) { - init.features[0] |=3D 1 << KVM_ARM_VCPU_PMU_V3; - pmu_supported =3D true; - features |=3D 1ULL << ARM_FEATURE_PMU; - } - - if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init, &local_err)) { + if (!kvm_arm_create_scratch_max_host_vcpu(fdarray, + &init_features0, &target, + &local_err)) { error_report_err(local_err); return; } =20 + pmu_supported =3D init_features0 & (1 << KVM_ARM_VCPU_PMU_V3); + sve_supported =3D init_features0 & (1 << KVM_ARM_VCPU_SVE); + + if (pmu_supported) { + features |=3D 1ULL << ARM_FEATURE_PMU; + } + int fd =3D fdarray[2]; =20 err =3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR0_EL1_IDX); @@ -746,11 +756,11 @@ kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahc= f) features |=3D 1ULL << ARM_FEATURE_AARCH64; features |=3D 1ULL << ARM_FEATURE_GENERIC_TIMER; =20 - if (el2_supported) { + if (init_features0 & (1 << KVM_ARM_VCPU_HAS_EL2)) { features |=3D 1ULL << ARM_FEATURE_EL2; } =20 - ahcf->target =3D init.target; + ahcf->target =3D target; ahcf->features =3D features; } =20 --=20 2.53.0 From nobody Sat Sep 26 23:03:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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b=SrJVfuIufVTEMIHtwEgJghlcVVt5BZ4+yLbdAyBtieAsg6+nojf9ZuiT1sTBJaeiqixILO iqNliePTl2wfZj6TnTEerwyy+2bNnOVzKOJgunaf/xlAJpbu0ahtITDGFeJTYXX84TCBAf AHKebt5oLEHdTFRSOHISTPAtHSS2Z8c= X-MC-Unique: 9uPRfy80NEqVJnmcp7WuyA-1 X-Mimecast-MFC-AGG-ID: 9uPRfy80NEqVJnmcp7WuyA_1787737208 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v8 20/20] arm-qmp-cmds: introspection for ID register props Date: Wed, 26 Aug 2026 11:36:25 +0200 Message-ID: <20260826093747.1670077-21-eric.auger@redhat.com> In-Reply-To: <20260826093747.1670077-1-eric.auger@redhat.com> References: <20260826093747.1670077-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Cornelia Huck Implement the capability to query available ID register values by adding SYSREG_* options and values to the cpu model expansion for the host model, if available. Here are some qmp-shell examples: (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host"} {"return": {"model": {"name": "host", "props": {"SYSREG_ID_AA64PFR0_EL1_EL3= ": 1, "SYSREG_ID_AA64ISAR2_EL1_CLRBHB": 0, "SYSREG_CTR_EL0_L1Ip": 3, "SYSREG_MIDR_EL1_PartNum": 3407, "SYSREG_CTR_EL0_DminLine": 4, "SYSREG_ID_AA64MMFR0_EL1_PARange": 5, "SYSREG_ID_AA64MMFR1_EL1_ECBHB": 0 ../.. This allows the upper stack to detect available writable ID regs and the "host passthrough model" values. It also allows to test some ID reg field values: (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host","props"= :{"SYSREG_ID_AA64ISAR0_EL1_DP":0x13}} {"error": {"class": "GenericError", "desc": "idreg SYSREG_ID_AA64ISAR0_EL1_= DP set value (0x13) exceeds length of field (4)!"}} (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host","props"= :{"SYSREG_ID_AA64ISAR0_EL1_DP":0x2}} {"error": {"class": "GenericError", "desc": "idreg SYSREG_ID_AA64ISAR0_EL1_= DP set value (0x2) does not match any arch valid enum value!"}} The following checks are performed: - the value does not exceed the field size - if the field is associated to enum values, the set value must be one of those enum values - the value is applied against a scratch vcpu making sure the setting is not rejected for this host Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- v7 -> v8: - do not check if the prop exists (this is checked elsewhere with a different error message) - clarify that examples given in the commit msg are based on qmp-shell v5 -> v6: - add the write capability --- target/arm/arm-qmp-cmds.c | 73 +++++++++++++++++++++++++++++++++++++++ target/arm/kvm-stub.c | 5 +++ 2 files changed, 78 insertions(+) diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index 83ec95c290..5fbdca3253 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -21,6 +21,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qemu/target-info.h" #include "hw/core/boards.h" #include "kvm_arm.h" @@ -30,7 +31,10 @@ #include "qapi/qapi-commands-machine.h" #include "qapi/qapi-commands-misc-arm.h" #include "qobject/qdict.h" +#include "qobject/qnum.h" #include "qom/qom-qobject.h" +#include +#include "system/kvm.h" #include "cpu.h" =20 static GICCapability *gic_cap_new(int version) @@ -84,11 +88,14 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(Cp= uModelExpansionType type, Error **errp) { CpuModelExpansionInfo *expansion_info; + ObjectPropertyIterator iter; const QDict *qdict_in; + ObjectProperty *idregprop; QDict *qdict_out; ObjectClass *oc; Object *obj; const char *name; + int fdarray[3]; int i; =20 if (type !=3D CPU_MODEL_EXPANSION_TYPE_FULL) { @@ -133,6 +140,17 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, =20 obj =3D object_new(object_class_get_name(oc)); =20 + if (kvm_enabled()) { + uint32_t init_features0, target; + bool success; + + success =3D kvm_arm_create_scratch_max_host_vcpu(fdarray, &init_fe= atures0, + &target, errp); + if (!success) { + return NULL; + } + } + if (model->props) { Visitor *visitor; Error *err =3D NULL; @@ -145,6 +163,45 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, } =20 qdict_in =3D qobject_to(QDict, model->props); + + for (const QDictEntry *entry =3D qdict_first(qdict_in); + entry !=3D NULL; entry =3D qdict_next(qdict_in, entry)) { + const char *key =3D qdict_entry_key(entry); + QObject *val_obj =3D qdict_entry_value(entry); + ObjectProperty *prop; + Visitor *v; + bool success; + uint64_t val; + + prop =3D object_property_find(obj, key); + + if (!g_str_has_prefix(key, "SYSREG_")) { + continue; + } + + /* consume the prop to avoid unexpected parameter */ + if (!visit_type_uint64(visitor, key, &val, errp)) { + return NULL; + } + + v =3D qobject_input_visitor_new(val_obj); + + if (!object_property_set(obj, key, v, errp)) { + visit_free(v); + return NULL; + } + + if (kvm_enabled()) { + success =3D kvm_idreg_write_scratch_vcpu(fdarray[2], v, ke= y, + prop->opaque, errp); + if (!success) { + visit_free(v); + return NULL; + } + } + visit_free(v); + } + i =3D 0; while ((name =3D cpu_model_advertised_features[i++]) !=3D NULL) { if (qdict_get(qdict_in, name)) { @@ -160,6 +217,10 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, if (!err) { arm_cpu_finalize_features(ARM_CPU(obj), &err); } + + if (kvm_enabled()) { + kvm_arm_destroy_scratch_host_vcpu(fdarray); + } visit_end_struct(visitor, NULL); visit_free(visitor); if (err) { @@ -190,6 +251,18 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, } } =20 + object_property_iter_init(&iter, obj); + + while ((idregprop =3D object_property_iter_next(&iter))) { + QObject *value; + + if (!g_str_has_prefix(idregprop->name, "SYSREG_")) { + continue; + } + value =3D object_property_get_qobject(obj, idregprop->name, &error= _abort); + qdict_put_obj(qdict_out, idregprop->name, value); + } + if (!qdict_size(qdict_out)) { qobject_unref(qdict_out); } else { diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 0d6c841a24..eae2e1ec2c 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -132,3 +132,8 @@ bool kvm_arm_create_scratch_max_host_vcpu(int *fdarray, { g_assert_not_reached(); } + +void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) +{ + g_assert_not_reached(); +} --=20 2.53.0