From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787734182111739.2247562117806; Wed, 26 Aug 2026 01:49:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wz9Jf-00081R-Vh; Wed, 26 Aug 2026 04:49:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wz9Je-00080o-HX for qemu-devel@nongnu.org; Wed, 26 Aug 2026 04:49:02 -0400 Received: from mx1.zhaoxin.com ([210.0.225.12]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wz9Jc-0001ZO-0n for qemu-devel@nongnu.org; Wed, 26 Aug 2026 04:49:02 -0400 Received: from zhaoxin.com (unknown [127.0.0.1]) by mx1.zhaoxin.com (MTA) with ESMTP id 4hVJGQ6cVHzcYn0Y; Wed, 26 Aug 2026 16:48:46 +0800 (CST) Received: from zhaoxin.com (unknown [10.28.208.166]) by mx1.zhaoxin.com (MTA) with ESMTP id 4hVJGP4DjLzbQJxB; Wed, 26 Aug 2026 16:48:45 +0800 (CST) Received: from ewan-server.tailb932da.ts.net (ewan-server.tailb932da.ts.net [10.28.24.2]) by zhaoxin.com (8.30) with ESMTP2ef6ef4893586330462470398f1a50d3 Wed, 26 Aug 2026 16:48:45 +0800 X-Eyou-Smtpauth: ewanhai-oc@zhaoxin.com X-Eyou-EnvelopeSender: ewanhai-oc@zhaoxin.com X-Eyou-From: Ewan Hai From: "=?UTF-8?B?RXdhbiBIYWktb2M=?=" To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, zhao1.liu@intel.com, ewanhai@zhaoxin.com, cobechen@zhaoxin.com, Ewan Hai Subject: [PATCH v4 1/4] target/i386: Add cache model for Zhaoxin Shijidadao vCPUs Date: Wed, 26 Aug 2026 16:48:35 +0800 Message-Id: <20260826084838.2107629-2-ewanhai-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260826084838.2107629-1-ewanhai-oc@zhaoxin.com> References: <20260826084838.2107629-1-ewanhai-oc@zhaoxin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Eyou-Sender: Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=210.0.225.12; envelope-from=ewanhai-oc@zhaoxin.com; helo=mx1.zhaoxin.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, FROM_EXCESS_BASE64=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1787734186008158500 Content-Type: text/plain; charset="utf-8" Zhaoxin "Shijidadao" vCPUs require built-in cache enumeration in QEMU to properly report CPUID leaf 0x4 and 0x80000005/0x80000006 when 'host-cache-info' is disabled. This patch defines the L1/L2/L3 cache parameters for the Shijidadao architecture, preparing for use in both client and server models. Reviewed-by: Zhao Liu Signed-off-by: Ewan Hai --- target/i386/cpu.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e5ffb10d15..5408d851d1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3512,6 +3512,105 @@ static const CPUCaches yongfeng_cache_info =3D { }, }; =20 +static const CPUCaches shijidadao_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x0.EAX */ + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x0.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x0.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x0.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + /* CPUID 0x80000005.ECX */ + .lines_per_tag =3D 1, + .size =3D 32 * KiB, + + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x1.EAX */ + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x1.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x1.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x1.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + /* CPUID 0x80000005.EDX */ + .lines_per_tag =3D 1, + .size =3D 64 * KiB, + + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x2.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + /* CPUID 0x4.0x2.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x2.ECX */ + .sets =3D 1024, + + /* CPUID 0x4.0x2.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D true, + .complex_indexing =3D false, + + /* CPUID 0x80000006.ECX */ + .size =3D 512 * KiB, + + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x3.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + /* CPUID 0x4.0x3.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x3.ECX */ + .sets =3D 32768, + + /* CPUID 0x4.0x3.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D true, + .complex_indexing =3D false, + + .size =3D 32 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + }, +}; + /* The following VMX features are not supported by KVM and are left out in= the * CPU definitions: * --=20 2.34.1 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787734185266404.2138752499168; Wed, 26 Aug 2026 01:49:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wz9Jh-000825-EX; Wed, 26 Aug 2026 04:49:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wz9Je-00080v-P8 for qemu-devel@nongnu.org; Wed, 26 Aug 2026 04:49:02 -0400 Received: from mx1.zhaoxin.com ([210.0.225.12]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wz9Jc-0001ZT-IL for qemu-devel@nongnu.org; Wed, 26 Aug 2026 04:49:02 -0400 Received: from zhaoxin.com (unknown [127.0.0.1]) by mx1.zhaoxin.com (MTA) with ESMTP id 4hVJGQ6cdCzcYn0c; Wed, 26 Aug 2026 16:48:46 +0800 (CST) Received: from zhaoxin.com (unknown [10.28.208.166]) by mx1.zhaoxin.com (MTA) with ESMTP id 4hVJGQ4GZwzcYn0Y; Wed, 26 Aug 2026 16:48:46 +0800 (CST) Received: from ewan-server.tailb932da.ts.net (ewan-server.tailb932da.ts.net [10.28.24.2]) by zhaoxin.com (8.30) with ESMTPb7ffbebd428b1f166471ea09aacd50d3 Wed, 26 Aug 2026 16:48:45 +0800 X-Eyou-Smtpauth: ewanhai-oc@zhaoxin.com X-Eyou-EnvelopeSender: ewanhai-oc@zhaoxin.com X-Eyou-From: Ewan Hai From: "=?UTF-8?B?RXdhbiBIYWktb2M=?=" To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, zhao1.liu@intel.com, ewanhai@zhaoxin.com, cobechen@zhaoxin.com, Ewan Hai Subject: [PATCH v4 2/4] target/i386: Add Zhaoxin cryptographic CPUID features Date: Wed, 26 Aug 2026 16:48:36 +0800 Message-Id: <20260826084838.2107629-3-ewanhai-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260826084838.2107629-1-ewanhai-oc@zhaoxin.com> References: <20260826084838.2107629-1-ewanhai-oc@zhaoxin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Eyou-Sender: Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=210.0.225.12; envelope-from=ewanhai-oc@zhaoxin.com; helo=mx1.zhaoxin.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, FROM_EXCESS_BASE64=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1787734187795158500 Content-Type: text/plain; charset="utf-8" Add QEMU feature names and masks for the SM2, CCS, RNG2, PHE2 and RSA feature pairs in CPUID 0xC0000001 EDX. The matching KVM support exposes these bits through KVM_GET_SUPPORTED_CPUID. TCG does not currently implement these instructions. Keep TCG_EXT4_FEATURES at zero so QEMU filters the bits from realized TCG CPUs. Link: https://lore.kernel.org/all/20260610023512.3690734-1-ewanhai-oc@zhaox= in.com/ Signed-off-by: Ewan Hai Reviewed-by: Zhao Liu --- target/i386/cpu.c | 10 +++++----- target/i386/cpu.h | 20 ++++++++++++++++++++ 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5408d851d1..1107d1243c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1120,14 +1120,14 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = =3D { [FEAT_C000_0001_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { - NULL, NULL, "xstore", "xstore-en", - NULL, NULL, "xcrypt", "xcrypt-en", + "sm2", "sm2-en", "xstore", "xstore-en", + "ccs", "ccs-en", "xcrypt", "xcrypt-en", "ace2", "ace2-en", "phe", "phe-en", "pmm", "pmm-en", NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, "rng2", "rng2-en", + NULL, "phe2", "phe2-en", "rsa", + "rsa-en", NULL, NULL, NULL, }, .cpuid =3D { .eax =3D 0xC0000001, .reg =3D R_EDX, }, .tcg_features =3D TCG_EXT4_FEATURES, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 641f3ee5c2..60327688f4 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1243,10 +1243,18 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU = *cpu, FeatureWord w); /* CPUID[0x80000007].EDX flags: */ #define CPUID_APM_INVTSC (1U << 8) =20 +/* SM2 algorithm */ +#define CPUID_C000_0001_EDX_SM2 (1U << 0) +/* SM2 enabled */ +#define CPUID_C000_0001_EDX_SM2_EN (1U << 1) /* "rng" RNG present (xstore) */ #define CPUID_C000_0001_EDX_XSTORE (1U << 2) /* "rng_en" RNG enabled */ #define CPUID_C000_0001_EDX_XSTORE_EN (1U << 3) +/* SM3 and SM4 algorithms */ +#define CPUID_C000_0001_EDX_CCS (1U << 4) +/* CCS enabled */ +#define CPUID_C000_0001_EDX_CCS_EN (1U << 5) /* "ace" on-CPU crypto (xcrypt) */ #define CPUID_C000_0001_EDX_XCRYPT (1U << 6) /* "ace_en" on-CPU crypto enabled */ @@ -1263,6 +1271,18 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *= cpu, FeatureWord w); #define CPUID_C000_0001_EDX_PMM (1U << 12) /* PMM enabled */ #define CPUID_C000_0001_EDX_PMM_EN (1U << 13) +/* Random Number Generator v2 */ +#define CPUID_C000_0001_EDX_RNG2 (1U << 22) +/* RNG2 enabled */ +#define CPUID_C000_0001_EDX_RNG2_EN (1U << 23) +/* PadLock Hash Engine v2 */ +#define CPUID_C000_0001_EDX_PHE2 (1U << 25) +/* PHE2 enabled */ +#define CPUID_C000_0001_EDX_PHE2_EN (1U << 26) +/* Big-number arithmetic */ +#define CPUID_C000_0001_EDX_RSA (1U << 27) +/* RSA enabled */ +#define CPUID_C000_0001_EDX_RSA_EN (1U << 28) =20 #define CPUID_VENDOR_SZ 12 #define CPUID_MODEL_ID_SZ 48 --=20 2.34.1 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178773417790475.04210541424413; Wed, 26 Aug 2026 01:49:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wz9Jf-00080n-N7; Wed, 26 Aug 2026 04:49:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wz9Jd-00080d-9z for qemu-devel@nongnu.org; Wed, 26 Aug 2026 04:49:01 -0400 Received: from mx1.zhaoxin.com ([210.0.225.12]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wz9Ja-0001ZN-H2 for qemu-devel@nongnu.org; Wed, 26 Aug 2026 04:49:01 -0400 Received: from zhaoxin.com (unknown [127.0.0.1]) by mx1.zhaoxin.com (MTA) with ESMTP id 4hVJGQ6cjJzcYn0d; Wed, 26 Aug 2026 16:48:46 +0800 (CST) Received: from zhaoxin.com (unknown [10.28.208.166]) by mx1.zhaoxin.com (MTA) with ESMTP id 4hVJGQ4CHxzbQJxB; Wed, 26 Aug 2026 16:48:46 +0800 (CST) Received: from ewan-server.tailb932da.ts.net (ewan-server.tailb932da.ts.net [10.28.24.2]) by zhaoxin.com (8.30) with ESMTP86b39bd78b002a7930acc90d38cf50d3 Wed, 26 Aug 2026 16:48:45 +0800 X-Eyou-Smtpauth: ewanhai-oc@zhaoxin.com X-Eyou-EnvelopeSender: ewanhai-oc@zhaoxin.com X-Eyou-From: Ewan Hai From: "=?UTF-8?B?RXdhbiBIYWktb2M=?=" To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, zhao1.liu@intel.com, ewanhai@zhaoxin.com, cobechen@zhaoxin.com, Ewan Hai Subject: [PATCH v4 3/4] target/i386: Introduce Zhaoxin Shijidadao CPU model Date: Wed, 26 Aug 2026 16:48:37 +0800 Message-Id: <20260826084838.2107629-4-ewanhai-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260826084838.2107629-1-ewanhai-oc@zhaoxin.com> References: <20260826084838.2107629-1-ewanhai-oc@zhaoxin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Eyou-Sender: Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=210.0.225.12; envelope-from=ewanhai-oc@zhaoxin.com; helo=mx1.zhaoxin.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, FROM_EXCESS_BASE64=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1787734182107158500 Content-Type: text/plain; charset="utf-8" Introduce the Zhaoxin Shijidadao CPU model with two versions: - v1 (alias: Shijidadao-Server) - Server variant with CORE_CAPABILITY and SPLIT_LOCK_DETECT support - v2 (alias: Shijidadao-Client) - Client variant with different FMS (model=3D0x6b, stepping=3D1), with neither CORE_CAPABILITY features nor the ACE2 feature pair Both versions include the SM2, CCS, RNG2, PHE2 and RSA feature pairs exposed by KVM. The model_id for both variants is 'Zhaoxin Shijidadao Processor'. Signed-off-by: Ewan Hai Reviewed-by: Zhao Liu --- target/i386/cpu.c | 153 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1107d1243c..70904810b5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7409,6 +7409,159 @@ static const X86CPUDefinition builtin_x86_defs[] = =3D { { /* end of list */ } } }, + { + .name =3D "Shijidadao", + .level =3D 0x1f, + .vendor =3D CPUID_VENDOR_ZHAOXIN1, + .family =3D 7, + .model =3D 0x7b, + .stepping =3D 0, + .cpuid_0x1f =3D true, + /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */ + .features[FEAT_1_EDX] =3D + CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_C= MOV | + CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | + CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | + CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87, + /* + * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2, + * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX + */ + .features[FEAT_1_ECX] =3D + CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | + CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER= | + CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC | + CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID | + CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | + CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_RDSEE= D | + CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_SME= P | + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_FSGSBA= SE, + /* missing: CPUID_7_0_ECX_OSPKE */ + .features[FEAT_7_0_ECX] =3D + CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP, + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL | + CPUID_7_0_EDX_CORE_CAPABILITY, + .features[FEAT_CORE_CAPABILITY] =3D + MSR_CORE_CAP_SPLIT_LOCK_DETECT, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | + CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, + .features[FEAT_8000_0007_EDX] =3D CPUID_APM_INVTSC, + /* missing: PARALLAX/PARALLAX_EN, TM3/TM3_EN */ + .features[FEAT_C000_0001_EDX] =3D + CPUID_C000_0001_EDX_RSA_EN | CPUID_C000_0001_EDX_RSA | + CPUID_C000_0001_EDX_PHE2_EN | CPUID_C000_0001_EDX_PHE2 | + CPUID_C000_0001_EDX_RNG2_EN | CPUID_C000_0001_EDX_RNG2 | + CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM | + CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE | + CPUID_C000_0001_EDX_ACE2_EN | CPUID_C000_0001_EDX_ACE2 | + CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT | + CPUID_C000_0001_EDX_CCS_EN | CPUID_C000_0001_EDX_CCS | + CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE | + CPUID_C000_0001_EDX_SM2_EN | CPUID_C000_0001_EDX_SM2, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV= 1 | + CPUID_XSAVE_XSAVES, + .features[FEAT_ARCH_CAPABILITIES] =3D + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | + MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO | + MSR_ARCH_CAP_SSB_NO, + .features[FEAT_VMX_PROCBASED_CTLS] =3D + VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING= | + VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING= | + VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING | + VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING | + VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITI= NG | + VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW | + VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITI= NG | + VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS= | + VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAP= S | + VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | + VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, + /* + * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING, + * VMX_SECONDARY_EXEC_TSC_SCALING + */ + .features[FEAT_VMX_SECONDARY_CTLS] =3D + VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | + VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | + VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID | + VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | + VMX_SECONDARY_EXEC_WBINVD_EXITING | + VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | + VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | + VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | + VMX_SECONDARY_EXEC_RDRAND_EXITING | + VMX_SECONDARY_EXEC_ENABLE_INVPCID | + VMX_SECONDARY_EXEC_ENABLE_VMFUNC | + VMX_SECONDARY_EXEC_SHADOW_VMCS | + VMX_SECONDARY_EXEC_XSAVES | + VMX_SECONDARY_EXEC_ENABLE_PML, + .features[FEAT_VMX_PINBASED_CTLS] =3D + VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | + VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIME= R | + VMX_PIN_BASED_POSTED_INTR, + .features[FEAT_VMX_EXIT_CTLS] =3D + VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_= SIZE | + VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | + VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | + VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_T= IMER, + /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */ + .features[FEAT_VMX_ENTRY_CTLS] =3D + VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | + VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | + VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, + /* + * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN, + * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI + */ + .features[FEAT_VMX_MISC] =3D + MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | + MSR_VMX_MISC_VMWRITE_VMEXIT, + /* missing: MSR_VMX_EPT_UC */ + .features[FEAT_VMX_EPT_VPID_CAPS] =3D + MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | + MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | + MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | + MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CON= TEXT | + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID | + MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_A= DDR | + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, + .features[FEAT_VMX_BASIC] =3D + MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, + .features[FEAT_VMX_VMFUNC] =3D MSR_VMX_VMFUNC_EPT_SWITCHING, + .xlevel =3D 0x80000008, + .model_id =3D "Zhaoxin Shijidadao Processor", + .cache_info =3D &shijidadao_cache_info, + .versions =3D (X86CPUVersionDefinition[]) { + { + .version =3D 1, + .alias =3D "Shijidadao-Server", + }, + { + .version =3D 2, + .alias =3D "Shijidadao-Client", + .note =3D "client variant", + .props =3D (PropValue[]) { + { "model", "0x6b" }, + { "stepping", "1" }, + { "ace2", "off" }, + { "ace2-en", "off" }, + { "core-capability", "off" }, + { "split-lock-detect", "off" }, + { /* end of list */ } + }, + }, + { /* end of list */ } + } + }, }; =20 /* --=20 2.34.1 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787734185690970.3741692699389; Wed, 26 Aug 2026 01:49:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wz9Jh-000826-Fn; Wed, 26 Aug 2026 04:49:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wz9Jf-00081S-FH for qemu-devel@nongnu.org; Wed, 26 Aug 2026 04:49:03 -0400 Received: from mx1.zhaoxin.com ([210.0.225.12]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wz9Jd-0001ZM-MH for qemu-devel@nongnu.org; Wed, 26 Aug 2026 04:49:03 -0400 Received: from zhaoxin.com (unknown [127.0.0.1]) by mx1.zhaoxin.com (MTA) with ESMTP id 4hVJGR0b2KzcYn0h; Wed, 26 Aug 2026 16:48:47 +0800 (CST) Received: from zhaoxin.com (unknown [10.28.208.166]) by mx1.zhaoxin.com (MTA) with ESMTP id 4hVJGQ4LhyzcYn0Y; Wed, 26 Aug 2026 16:48:46 +0800 (CST) Received: from ewan-server.tailb932da.ts.net (ewan-server.tailb932da.ts.net [10.28.24.2]) by zhaoxin.com (8.30) with ESMTP0ad83d5e363ad6b33aa432858fcc50d3 Wed, 26 Aug 2026 16:48:45 +0800 X-Eyou-Smtpauth: ewanhai-oc@zhaoxin.com X-Eyou-EnvelopeSender: ewanhai-oc@zhaoxin.com X-Eyou-From: Ewan Hai From: "=?UTF-8?B?RXdhbiBIYWktb2M=?=" To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, zhao1.liu@intel.com, ewanhai@zhaoxin.com, cobechen@zhaoxin.com, Ewan Hai Subject: [PATCH v4 4/4] target/i386: Enable new cryptographic features in YongFeng-v4 Date: Wed, 26 Aug 2026 16:48:38 +0800 Message-Id: <20260826084838.2107629-5-ewanhai-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260826084838.2107629-1-ewanhai-oc@zhaoxin.com> References: <20260826084838.2107629-1-ewanhai-oc@zhaoxin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Eyou-Sender: Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=210.0.225.12; envelope-from=ewanhai-oc@zhaoxin.com; helo=mx1.zhaoxin.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, FROM_EXCESS_BASE64=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1787734187784158500 Content-Type: text/plain; charset="utf-8" Add YongFeng-v4 with the SM2, CCS, RNG2, PHE2 and RSA feature pairs enabled. Link: https://lore.kernel.org/all/20260610023512.3690734-1-ewanhai-oc@zhaox= in.com/ Signed-off-by: Ewan Hai Reviewed-by: Zhao Liu --- target/i386/cpu.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 70904810b5..0e842d0c80 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7208,10 +7208,7 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { .features[FEAT_8000_0001_ECX] =3D CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, .features[FEAT_8000_0007_EDX] =3D CPUID_APM_INVTSC, - /* - * TODO: When the Linux kernel introduces other existing definitio= ns - * for this leaf, remember to update the definitions here. - */ + /* missing: PARALLAX/PARALLAX_EN, TM3/TM3_EN */ .features[FEAT_C000_0001_EDX] =3D CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM | CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE | @@ -7309,6 +7306,23 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ }, } }, + { + .version =3D 4, + .note =3D "with additional cryptographic features", + .props =3D (PropValue[]) { + { "sm2", "on" }, + { "sm2-en", "on" }, + { "ccs", "on" }, + { "ccs-en", "on" }, + { "rng2", "on" }, + { "rng2-en", "on" }, + { "phe2", "on" }, + { "phe2-en", "on" }, + { "rsa", "on" }, + { "rsa-en", "on" }, + { /* end of list */ }, + } + }, { /* end of list */ } } }, --=20 2.34.1