From nobody Sat Sep 26 21:37:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787567389; cv=none; d=zohomail.com; s=zohoarc; b=HDP1uTJJfk+Yg2OnhfL0FPeP0VhdxbAd7YBhqzAvOsBJVaBRBgtlVQ0iHandqEQzibsRruc8Sbzj3owjLZSNrtPMH057gRsVhDGygCLuVks/3E1gtsoHE68agh17eQVA44G3rxuZemFsbmrn+VkqqVVEFzy4Q/3G8KL1hrgSUac= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787567389; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=I0r2nXlXjUB7wD1f3dT3ydAdxG7m+kDY629ovNa4ajA=; b=JLXupmpvIWGi6hp4sWK22/A5MjBD3jylVLMa2/yjn+TA56tRQds15eXLBkd93+htTOeo73Yrlq8WXPpujmGBoRybnbNTLNBCiPbrbQ+EAjDkF5WrrleggLWo1UpYG+gnemkFTK46piQWvwtQLxIxKYg92pe11Xu5PFc8d2lpIjA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787567389313469.74717348606816; Mon, 24 Aug 2026 03:29:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wyRuc-00033n-JJ; Mon, 24 Aug 2026 06:28:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wyRuZ-00032u-DX for qemu-devel@nongnu.org; Mon, 24 Aug 2026 06:28:16 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wyRuW-0001pe-EK for qemu-devel@nongnu.org; Mon, 24 Aug 2026 06:28:15 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-49554ebb87dso30201655e9.3 for ; Mon, 24 Aug 2026 03:28:10 -0700 (PDT) Received: from lanath.. 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We were missing this check, and instead trusted the guest-provided address to be sufficiently aligned already; add the alignment enforcement. The GICv5 spec defines the masking to be used with the expressions quoted above, which work with the raw field values from the IRS_IST_CFGR register; these simplify down to some straightforward expressions based on the sanitized values we've already extracted form those fields. You can get to the expressions we use here either by working through the simplification of the GIC spec expressions, or from first principles (the number of bits needed for the size of the table in bytes is the number of bits that index it plus the number of bits specifying the size of an individual table entry). Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 08878193dfc..cdc6c9d3466 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1313,6 +1313,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain= domain, uint64_t value) */ GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; uint8_t istbits, l2bits, l2_idx_bits; + int tableszbits; uint8_t id_bits =3D FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, LPI_ID_BITS); id_bits =3D MIN(MAX(id_bits, QEMU_GICV5_MIN_LPI_ID_BITS), QEMU_GIC= V5_ID_BITS); @@ -1359,6 +1360,33 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domai= n domain, uint64_t value) cfg->l2_idx_bits =3D l2_idx_bits; cfg->structure =3D FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, STRUCTURE); + + /* + * Bits [N:0] of the base addr are ignored, to enforce that in a + * 1-level IST it is aligned to the size of the ISTE array, + * and in a 2-level IST it is aligned to the size of the L1 table. + * The spec defines N in terms of the raw L2SZ, ISTSZ and LPI_ID_B= ITS + * fields, but we have already sanitized these to + * istbits =3D ISTSZ + 2 + * l2bits =3D (L2SZ * 2) + 12 + * id_bits =3D LPI_ID_BITS + * We have also already enforced the "bottom 6 bits are 0" via + * R_IRS_IST_BASER_ADDR_MASK, so can skip the Max() operation. + * We want tableszbits =3D=3D the number of bits to zero, which is= N + 1. + */ + if (cfg->structure) { + /* + * L1 table is indexed by the (id_bits - l2_idx_bits) bits in + * the ID, so has 2^(id_bits - l2_idx_bits) entries, and each + * entry is 8 bytes =3D=3D 2^3. + */ + tableszbits =3D id_bits - l2_idx_bits + 3; + } else { + /* table has 2^id_bits entries of 2^istbits size each */ + tableszbits =3D id_bits + istbits; + } + cfg->base &=3D MAKE_64BIT_MASK(0, tableszbits); + if (!cfg->lpi_cache) { /* * Keys are GINT_TO_POINTER(intid), so we want the g_direct_ha= sh --=20 2.43.0 From nobody Sat Sep 26 21:37:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787567360; cv=none; d=zohomail.com; s=zohoarc; b=iBmqbRVPcK0I4j4M7cfyCSrzrgKuiCfMjZzCHxLVaHB777jasKdc0Nj8ltCRf9PRvz/CC8hTAT79qzUEbedPlsazBnGInmRv8bpakIa1WgRxerOuW1PhwmiWv1w1s8ry/teT/nHkVv3milInJgXx6fEvRj+arU5FUPieuzK2NfQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787567360; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=xag12ub1bcuK3t8iRdQzufeU8tr65Q5N7+Ogw4oNi1g=; b=jApq4JkC0VAnbZ3DElm+r3H8gs4RjSlFf3La+3WiW6sDIZy/s/6IW7OH/PYgvy9QuutJ92v6jAxklfmkg9qJZyvAxFCpvcs9PdWiEI6STmTVBlzKPuwZz/++Dqj3YxT2C72hppZKgk2x2XtLf2NH0KXP7/Ffl0avuSQjj/1H4tM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787567360196405.29339458858567; Mon, 24 Aug 2026 03:29:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wyRuc-00033s-Jd; Mon, 24 Aug 2026 06:28:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wyRua-00033B-QX for qemu-devel@nongnu.org; Mon, 24 Aug 2026 06:28:17 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wyRuY-0001pn-Ih for qemu-devel@nongnu.org; Mon, 24 Aug 2026 06:28:16 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-47f96c5b722so1358317f8f.0 for ; Mon, 24 Aug 2026 03:28:11 -0700 (PDT) Received: from lanath.. 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Add the missing masking of low bits. We already needed to calculate the number of bits needed to index each byte in the L2 table, so add it to the GICv5ISTConfig to save having to re-calculate it later. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 6 ++++++ include/hw/intc/arm_gicv5.h | 1 + 2 files changed, 7 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index cdc6c9d3466..20680a5c225 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -595,6 +595,11 @@ static bool get_l2_iste_addr(GICv5Common *cs, const GI= Cv5ISTConfig *cfg, return false; } l2_base =3D l1_iste & R_L1_ISTE_L2_ADDR_MASK; + /* + * The effective base address of the L2 table is always + * aligned to the size of the L2 table. + */ + l2_base &=3D MAKE_64BIT_MASK(0, cfg->l2bits); id =3D extract32(id, 0, cfg->l2_idx_bits); } else { /* 1-level table */ @@ -1358,6 +1363,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain= domain, uint64_t value) cfg->id_bits =3D id_bits; cfg->istsz =3D 1 << istbits; cfg->l2_idx_bits =3D l2_idx_bits; + cfg->l2bits =3D l2bits; cfg->structure =3D FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, STRUCTURE); =20 diff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h index b8baf003ad6..d763a7939c7 100644 --- a/include/hw/intc/arm_gicv5.h +++ b/include/hw/intc/arm_gicv5.h @@ -23,6 +23,7 @@ typedef struct GICv5ISTConfig { uint8_t id_bits; /* number of bits in an ID for this table */ uint8_t l2_idx_bits; /* number of ID bits that index into L2 table */ uint8_t istsz; /* L2 ISTE size in bytes */ + uint8_t l2bits; /* bits needed to index L2 table in bytes */ bool structure; /* true if using 2-level table */ bool valid; /* true if this table is valid and usable */ /* This caches IST information about pending LPIs */ --=20 2.43.0 From nobody Sat Sep 26 21:37:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787567377; cv=none; d=zohomail.com; s=zohoarc; b=gzvI1+yTT25otK2D//LNV1kgeuEtiBR10nx1I0oohS1MbJQhHpOvIqLCoj+roeqAsZ52PunCJrDzbN3FszWSrR4qg8AVf26rhEZPYSRiJB7/GrfcJqyi24Rdey/1CxhfSkIrxT1rY2JD1WuPAWzMPCvG0x6aOUAGHtb8FjIV7bw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787567377; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=aqKROqzH1WTtSlOfECpDIdu6BBJpY3xxMUxQ+mbxfpw=; b=T5zRck1D2CsvZFV++ae/EBuXMsF0v/pfOiWo9TjTQnAZlo9rQiESgkZJRopvEJCrKIw4QoeYEWCjQ/X+lCuF4NWjIvKFkSKVWkimQp2oSg40TKBDCe0J7SOMvulf6NPfiTCrTwXQrS+P6aYqVIRxiBpn2Ih1AR9Bc4UxJp01CmU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787567377276695.2342845382715; Mon, 24 Aug 2026 03:29:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wyRud-00034v-PA; Mon, 24 Aug 2026 06:28:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wyRuc-00033p-AF for qemu-devel@nongnu.org; Mon, 24 Aug 2026 06:28:18 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wyRuY-0001q0-JL for qemu-devel@nongnu.org; Mon, 24 Aug 2026 06:28:17 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4921eed3fa2so25753145e9.0 for ; Mon, 24 Aug 2026 03:28:12 -0700 (PDT) Received: from lanath.. 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Delete the blank lines to make it consistent with itself and the rest of the file. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- I figured probably better to do this before adding a bunch more cases to the switch, which virt support will do. --- hw/intc/arm_gicv5.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 20680a5c225..7480c12413b 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1468,53 +1468,41 @@ static bool config_readl(GICv5 *s, GICv5Domain doma= in, hwaddr offset, v &=3D ~R_IRS_IDR0_VIRT_ONE_N_MASK; } return true; - case A_IRS_IDR1: *data =3D cs->irs_idr1; return true; - case A_IRS_IDR2: *data =3D cs->irs_idr2; return true; - case A_IRS_IDR3: /* In EL3 IDR0.VIRT is 0 so this is RES0 */ *data =3D domain =3D=3D GICV5_ID_EL3 ? 0 : cs->irs_idr3; return true; - case A_IRS_IDR4: /* In EL3 IDR0.VIRT is 0 so this is RES0 */ *data =3D domain =3D=3D GICV5_ID_EL3 ? 0 : cs->irs_idr4; return true; - case A_IRS_IDR5: *data =3D cs->irs_idr5; return true; - case A_IRS_IDR6: *data =3D cs->irs_idr6; return true; - case A_IRS_IDR7: *data =3D cs->irs_idr7; return true; - case A_IRS_IIDR: *data =3D cs->irs_iidr; return true; - case A_IRS_AIDR: *data =3D cs->irs_aidr; return true; - case A_IRS_IST_BASER: *data =3D extract64(cs->irs_ist_baser[domain], 0, 32); return true; - case A_IRS_IST_BASER + 4: *data =3D extract64(cs->irs_ist_baser[domain], 32, 32); return true; - case A_IRS_IST_STATUSR: /* * For QEMU writes to IRS_IST_BASER and IRS_MAP_L2_ISTR take effect @@ -1522,11 +1510,9 @@ static bool config_readl(GICv5 *s, GICv5Domain domai= n, hwaddr offset, */ *data =3D R_IRS_IST_STATUSR_IDLE_MASK; return true; - case A_IRS_IST_CFGR: *data =3D cs->irs_ist_cfgr[domain]; return true; - case A_IRS_SPI_STATUSR: /* * QEMU writes to IRS_SPI_{CFGR,DOMAINR,SELR,VMR} take effect @@ -1537,7 +1523,6 @@ static bool config_readl(GICv5 *s, GICv5Domain domain= , hwaddr offset, v =3D FIELD_DP32(v, IRS_SPI_STATUSR, IDLE, 1); *data =3D v; return true; - case A_IRS_SPI_CFGR: { GICv5SPIState *spi =3D spi_for_selr(cs, domain); --=20 2.43.0 From nobody Sat Sep 26 21:37:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787567378; cv=none; d=zohomail.com; s=zohoarc; b=iyxp3fcazxb8or8VZb27IwgjUfGdEs65yiL44C/Uc4rduECn+MTB4vgvf/j2kWBenJ7ok/Fu4HiatYfHLsXWPAFgSOWptUxo12zyntnGhYngxsRtBn7j0iX7BCl8gCyQONvMwx4jxl4IRMLzVpdxsqs7lYwIIR9QJ3jWkx4FTRs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787567378; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=aQngANFmgRclvGCJWhrJN0pPqpqgEwxPZ5cj+oiSFi0=; b=kg9fppy+7m9gxQrG8czpPdfiM436HjSbVDqWiG9VWkVzcCIic9heDLFSylKpwMk+x9GLa9k7kG/RBXJgQ/f9TyMVKfqxS7CStMW0noszp1KI4RfL3tCs2Ar5ikmHezGrJaNWWT5VNMzQ0v1Y5sqo1yw4aDKEfaZQPwUC0KYdKms= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787567378605435.85533639947016; Mon, 24 Aug 2026 03:29:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wyRus-00037e-UG; Mon, 24 Aug 2026 06:28:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wyRud-00034q-G5 for qemu-devel@nongnu.org; Mon, 24 Aug 2026 06:28:19 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wyRua-0001qB-HU for qemu-devel@nongnu.org; Mon, 24 Aug 2026 06:28:19 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4980dc26022so22068615e9.1 for ; Mon, 24 Aug 2026 03:28:14 -0700 (PDT) Received: from lanath.. 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In a few places we check whether the IST is valid by doing a bit extract on the register value; switch those to look at cfg->structure instead. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 7480c12413b..8ffb2a49020 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1223,8 +1223,7 @@ static void irs_map_l2_istr_write(GICv5 *s, GICv5Doma= in domain, uint64_t value) uint64_t l1_iste; MemTxResult res; =20 - if (!FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID) || - !cfg->structure) { + if (!cfg->valid || !cfg->structure) { /* WI if no IST set up or it is not 2-level */ return; } @@ -1294,7 +1293,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain= domain, uint64_t value) { GICv5Common *cs =3D ARM_GICV5_COMMON(s); =20 - if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { + if (s->phys_lpi_config[domain].valid) { /* If VALID is set, ADDR is RO and we can only update VALID */ bool valid =3D FIELD_EX64(value, IRS_IST_BASER, VALID); if (valid) { @@ -1604,7 +1603,7 @@ static bool config_writel(GICv5 *s, GICv5Domain domai= n, hwaddr offset, deposit64(cs->irs_ist_baser[domain], 32, 32, d= ata)); return true; case A_IRS_IST_CFGR: - if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { + if (s->phys_lpi_config[domain].valid) { qemu_log_mask(LOG_GUEST_ERROR, "guest tried to write IRS_IST_CFGR for %s config= frame " "while IST_BASER.VALID set\n", domain_name[domai= n]); --=20 2.43.0 From nobody Sat Sep 26 21:37:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787567404; cv=none; d=zohomail.com; s=zohoarc; b=LeqUMz4lzEOOyfJhmx7ZKStPIEAaNwcA9+ucWbdhSuueINNVRXl4pJK31sKNg7zG0knfTNy/Ow1pAhEpvd7ZJ+dSPSzedazQtRblPpYq1NXV3yMh+0WH6QrLqvHwx37/fdRhcQopyGcLKlDzFx8gn8EUt4ocgvOtFHh257nLG1U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787567404; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=b+5usmdHTznNDEGIvxe7BfpQfxtTJ2JOpHQUhBK8vMo=; b=QyzefqJ09xjG5u4GBEE1A3pjRjP4UpSKOCkrRvDUbBl6DZFVW6+EKDgDG4M82SJ1/mUQP4BicvVmAiTKeCZzJWkgNbur3FW3qPdSzDf4NRRdW2ekk3388neyJK5p39BS5PLdV25qZWYRp0Wo/zuhT4hQshlrcVyblnMHpJsJFhA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787567404382740.3554436105233; Mon, 24 Aug 2026 03:30:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wyRuv-00038N-S0; Mon, 24 Aug 2026 06:28:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wyRue-00035H-M4 for qemu-devel@nongnu.org; Mon, 24 Aug 2026 06:28:21 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wyRuc-0001qY-3F for qemu-devel@nongnu.org; Mon, 24 Aug 2026 06:28:20 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4953e04ef16so30369305e9.2 for ; Mon, 24 Aug 2026 03:28:16 -0700 (PDT) Received: from lanath.. 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Free those resources in finalize. Since the GICv5 is created at QEMU startup and remains in existence for the lifetime of the process, this isn't an in-practice leak, only a theoretical one. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 11 +++++++++++ hw/intc/arm_gicv5_common.c | 3 +++ 2 files changed, 14 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 8ffb2a49020..de0044df9c6 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1970,6 +1970,17 @@ static void gicv5_init(Object *obj) =20 static void gicv5_finalize(Object *obj) { + GICv5 *s =3D ARM_GICV5(obj); + + for (int i =3D 0; i < NUM_GICV5_DOMAINS; i++) { + GHashTable *ht =3D s->phys_lpi_config[i].lpi_cache; + + if (ht) { + g_hash_table_destroy(ht); + } + + g_free(s->hppi[i]); + } } =20 static void gicv5_class_init(ObjectClass *oc, const void *data) diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index b155486af65..cc67246686e 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -112,6 +112,9 @@ static void gicv5_common_init(Object *obj) =20 static void gicv5_common_finalize(Object *obj) { + GICv5Common *cs =3D ARM_GICV5_COMMON(obj); + + g_free(cs->spi); } =20 static void gicv5_common_realize(DeviceState *dev, Error **errp) --=20 2.43.0 From nobody Sat Sep 26 21:37:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787567395; cv=none; d=zohomail.com; s=zohoarc; b=gNNb+nFsewZA/Tmqf4engp/9w0NmiStY0WPml1GtCW9KmLrJgdAgfoQplbo4mxUqCbeO9fwxNmwP7r5/fPzvE9eVU7nfaDLPWdjeW934tJgmxPelJGv+9eDq2/ZZGaI7ml8K6YvcA3tDo1T62e+jGjDajytYUm4U1rVMdLpTWZI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787567395; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=so9t/+rpuCfxYBu/lHmsMNKcNwE90G7vRfHB5gvvk6E=; b=VxetIGv0AdlPvL0vDvXYJ1NgmRdoQgk6kAnPJAjzUOpOd148iI6jGuIjDYgVUqCCPOiZJ5cHNClrEjlP4uONMOgzHdj8asO1CJxJOtCWCPNxK53uLvN/shJkUCI8yMU04PvmalNcXFH+dHPnJNUxen07s9/vXlUC0X6lK2cacvI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787567395829119.72077433531888; Mon, 24 Aug 2026 03:29:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wyRuw-00038s-AV; Mon, 24 Aug 2026 06:28:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wyRuf-00035K-Ns for qemu-devel@nongnu.org; Mon, 24 Aug 2026 06:28:22 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wyRuc-0001r7-3c for qemu-devel@nongnu.org; Mon, 24 Aug 2026 06:28:20 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4954df200ddso18000055e9.0 for ; Mon, 24 Aug 2026 03:28:17 -0700 (PDT) Received: from lanath.. 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This is almost but not exactly what we do for GICv2/GICv3 external GPIO IRQ/FIQ line changes. Those are handled by arm_cpu_set_irq(), and as well as calling cpu_interrupt() or cpu_reset_interrupt() they also update env->irq_line_state. For IRQ and FIQ it doesn't matter whether we set and clear the bits in irq_line_state, because nothing looks at them. But for VIRQ and VFIQ it will matter, because VIRQ and VFIQ are the logical OR of the line state and some bits in HCR_EL2. We're going to need to call arm_cpu_set_irq() for VIRQ and VFIQ; for consistency, handle IRQ and FIQ that way too. Since arm_cpu_set_irq() is now a function called from other parts of the CPU code, we make its first argument a properly typed one, with a wrapper taking void* for when we need to use it as a qemu_irq_handler. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 14 +++++++++++--- target/arm/internals.h | 14 ++++++++++++++ target/arm/tcg/gicv5-cpuif.c | 35 ++++------------------------------- 3 files changed, 29 insertions(+), 34 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 77aa78f00e2..2b1b87b0ed4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -806,9 +806,8 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int= target_el) =20 =20 #ifndef CONFIG_USER_ONLY -static void arm_cpu_set_irq(void *opaque, int irq, int level) +void arm_cpu_set_irq(ARMCPU *cpu, int irq, int level) { - ARMCPU *cpu =3D opaque; CPUARMState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); static const int mask[] =3D { @@ -860,6 +859,15 @@ static void arm_cpu_set_irq(void *opaque, int irq, int= level) } } =20 +/* + * Wrapper of arm_cpu_set_irq with the right argument types to be a + * qemu_irq_handler function for our inbound GPIO lines. + */ +static void arm_cpu_gpio_set_irq(void *opaque, int irq, int level) +{ + arm_cpu_set_irq(opaque, irq, level); +} + static bool arm_cpu_internal_is_big_endian(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -1263,7 +1271,7 @@ static void arm_cpu_initfn(Object *obj) */ qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6); } else { - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6); + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_gpio_set_irq, 6); } =20 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, diff --git a/target/arm/internals.h b/target/arm/internals.h index f6b4e173a54..f6c9f984952 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1882,6 +1882,20 @@ void define_gcs_cpregs(ARMCPU *cpu); /* Add the cpreg definitions for OMAP CP15 regs */ void define_omap_cp_regs(ARMCPU *cpu); =20 +#ifndef CONFIG_USER_ONLY +/** + * arm_cpu_set_irq: Assert or clear an IRQ/FIQ/etc interrupt line + * @cpu: CPU to set interrupt on + * @irq: one of the ARM_CPU_IRQ/ARM_CPU_FIQ/ARM_CPU_VIRQ/etc values + * @level: 0 to deassert, non-zero to assert + * + * This function is called by the qemu_irq_handler function + * when IRQ etc are real inbound GPIO lines; it is also called + * directly by the GICv5 CPU interface. + */ +void arm_cpu_set_irq(ARMCPU *cpu, int irq, int level); +#endif + /* Add the cpreg definitions for the GICv5 CPU interface */ void define_gicv5_cpuif_regs(ARMCPU *cpu); =20 diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index a6e6c440849..517c780d1f7 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -173,33 +173,6 @@ static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv= 5Domain domain) return best; } =20 -static void cpu_interrupt_update(CPUARMState *env, int irqtype, bool new_s= tate) -{ - CPUState *cs =3D env_cpu(env); - - /* - * OPT: calling cpu_interrupt() and cpu_reset_interrupt() has the - * correct behaviour, but is not optimal for the case where we're - * setting the interrupt line to the same level it already has. - * - * Clearing an already clear interrupt is free (it's just doing an - * atomic AND operation). Signalling an already set interrupt is a - * bit less ideal (it might unnecessarily kick the CPU). - * - * We could potentially use cpu_test_interrupt(), like - * arm_cpu_update_{virq,vfiq,vinmi,vserr}, since we always hold - * the BQL here; or perhaps there is an abstraction we could - * provide in the core code that all these places could call. - * - * For now, this is simple and definitely correct. - */ - if (new_state) { - cpu_interrupt(cs, irqtype); - } else { - cpu_reset_interrupt(cs, irqtype); - } -} - static void gicv5_update_irq_fiq(CPUARMState *env) { /* @@ -243,12 +216,12 @@ static void gicv5_update_irq_fiq(CPUARMState *env) /* * Unlike a GICv3 or GICv2, there is no external IRQ or FIQ line * to the CPU. Instead we directly signal the interrupt via - * cpu_interrupt()/cpu_reset_interrupt(). + * arm_cpu_set_irq(). */ trace_gicv5_update_irq_fiq(irq, fiq, superpriority); - cpu_interrupt_update(env, CPU_INTERRUPT_HARD, irq); - cpu_interrupt_update(env, CPU_INTERRUPT_FIQ, fiq); - cpu_interrupt_update(env, CPU_INTERRUPT_NMI, superpriority); + arm_cpu_set_irq(env_archcpu(env), ARM_CPU_IRQ, irq); + arm_cpu_set_irq(env_archcpu(env), ARM_CPU_FIQ, fiq); + arm_cpu_set_irq(env_archcpu(env), ARM_CPU_NMI, superpriority); } =20 static void gic_recalc_ppi_hppi(CPUARMState *env) --=20 2.43.0