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Mon, 24 Aug 2026 02:34:12 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.10.3 mail.embedded-brains.de 38D04480153 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embedded-brains.de; s=34EE5404-8E36-11F0-B577-2ECCAB4968F5; t=1787531653; bh=dxWI6WGQFJ7EpG1oKNYr5GhcQ1+ZM7yjJSqMh2KHyaM=; h=From:To:Date:Message-ID:MIME-Version; b=IdU+aFaC+ygZTCAIGQpQGxHmgLCEPOuwSyefSOL7S9x/RDWetGCmKE9zMSHyQUTf0 igolZOTgQJ7A73YqyKp3burnG1E5PMfyviBX6qIcgR4q5rjCgtLoa+Tr5bF5soJXZY rnxFwszjlM+Sb4nz4dX5zXqxhWRxky/WwOYIWXH45VfFoUlAt66JSWiiNod5XMSufp YzsKpCGXcgrBO9TLd1a9B8iSR+Vy09e6mEUDsQTgHh2ubJxinkXRNDjW6ocd37KyXA NBn8stLpbnfAeS+0toNzJ6fTQjF5cpYqqPyUSrqc2rBUQmeuKmYnPQWAFbLm6c3HXF HXF6avUkMrslw== X-Virus-Scanned: amavis at zimbra.eb.localhost From: Sebastian Huber To: qemu-devel@nongnu.org Subject: [PATCH 1/2] hw/timer/xilinx_timer: Start on the enable edge Date: Mon, 24 Aug 2026 02:34:04 +0200 Message-ID: <20260824003405.616297-2-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260824003405.616297-1-sebastian.huber@embedded-brains.de> References: <20260824003405.616297-1-sebastian.huber@embedded-brains.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Status: pass [(embedded-brains.de) - 78.47.166.52] X-Virus-Scanned: Clear (ClamAV 1.4.3/28101/Sun Aug 23 08:26:53 2026) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=85.10.215.148; envelope-from=sebastian.huber@embedded-brains.de; helo=dedi548.your-server.de X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @embedded-brains.de) X-ZM-MESSAGEID: 1787531703627158500 Content-Type: text/plain; charset="utf-8" Every write to a control register which has the enable bit set restarted the count from the load value. A guest which clears the interrupt of a periodic timer writes that register with the enable bit still set, so every period gained the latency of the interrupt. Start the count only where the enable bit goes from zero to one. Signed-off-by: Sebastian Huber --- hw/timer/xilinx_timer.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 8a502dae0e..dff439c623 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -175,17 +175,25 @@ timer_write(void *opaque, hwaddr addr, addr &=3D 3; switch (addr)=20 { - case R_TCSR: + case R_TCSR: { + uint32_t old =3D xt->regs[R_TCSR]; + if (value & TCSR_TINT) value &=3D ~TCSR_TINT; =20 xt->regs[addr] =3D value & 0x7ff; - if (value & TCSR_ENT) { + /* + * Only a transition of the enable bit to one starts the count. + * A write which leaves the bit set, such as the acknowledge of + * an interrupt, does not restart it. + */ + if ((value & TCSR_ENT) && !(old & TCSR_ENT)) { ptimer_transaction_begin(xt->ptimer); timer_enable(xt); ptimer_transaction_commit(xt->ptimer); } break; + } =20 default: if (addr < ARRAY_SIZE(xt->regs)) --=20 2.51.0 From nobody Sat Sep 26 21:37:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 24 Aug 2026 02:34:13 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.10.3 mail.embedded-brains.de 191BA480153 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embedded-brains.de; s=34EE5404-8E36-11F0-B577-2ECCAB4968F5; t=1787531654; bh=5lQnvr/w0aQKUxL94xjZv+++DhvywaDZVxwDAzz9vlU=; h=From:To:Date:Message-ID:MIME-Version; b=LyyMw3p2FZ3wQkZMVyLCD/nBHjVcmq2YXTcgYQQV7k1+3wFYqLnU0DFyvSXQ/gMDH Z/cVh6oxMifengHuSyAlgppOEuJ+hNe199x7+SGp2ibS+Eq38BqqPInKhGUGOv2KNC lJ9wgqbHl4KNa+deJ1jAlbrjjfo4g7dlZnCR5LWQ7y0VDVczQ1R47brk5SwAlppuHf ONQde+bHGpq2nE4GvASA6SE1e/5mu9FJSmdB9Hy0c6GX9I9eL7+Vf0Ae5+sIbaWpVA Zz92+vH1Gxkbi1UqAW4My9lGP78guazQL5RihnMv0Zgse7rwabaTIQHQHxHMsEhBIv Le9W1txybFJjQ== X-Virus-Scanned: amavis at zimbra.eb.localhost From: Sebastian Huber To: qemu-devel@nongnu.org Subject: [PATCH 2/2] hw/timer/xilinx_timer: Reload at the expiry Date: Mon, 24 Aug 2026 02:34:05 +0200 Message-ID: <20260824003405.616297-3-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260824003405.616297-1-sebastian.huber@embedded-brains.de> References: <20260824003405.616297-1-sebastian.huber@embedded-brains.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Status: pass [(embedded-brains.de) - 78.47.166.52] X-Virus-Scanned: Clear (ClamAV 1.4.3/28101/Sun Aug 23 08:26:53 2026) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=85.10.215.148; envelope-from=sebastian.huber@embedded-brains.de; helo=dedi548.your-server.de X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @embedded-brains.de) X-ZM-MESSAGEID: 1787531703645158500 Content-Type: text/plain; charset="utf-8" The callback of a timer with the auto reload and hold bit set restarted the count. It restarted it at the moment the callback ran, so every period gained the latency of the callback and the period moved with the load of the host. Run the ptimer in the periodic mode, so that it reloads at the expiry. A write of the load register while the count runs sets the limit for the next reload, which keeps the load value live. Signed-off-by: Sebastian Huber --- hw/timer/xilinx_timer.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index dff439c623..7120c339ec 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -139,6 +139,14 @@ timer_read(void *opaque, hwaddr addr, unsigned int siz= e) return r; } =20 +static uint64_t timer_limit(struct xlx_timer *xt) +{ + if (xt->regs[R_TCSR] & TCSR_UDT) + return xt->regs[R_TLR]; + else + return ~0 - xt->regs[R_TLR]; +} + /* Must be called inside ptimer transaction block */ static void timer_enable(struct xlx_timer *xt) { @@ -149,12 +157,14 @@ static void timer_enable(struct xlx_timer *xt) =20 ptimer_stop(xt->ptimer); =20 - if (xt->regs[R_TCSR] & TCSR_UDT) - count =3D xt->regs[R_TLR]; - else - count =3D ~0 - xt->regs[R_TLR]; + count =3D timer_limit(xt); ptimer_set_limit(xt->ptimer, count, 1); - ptimer_run(xt->ptimer, 1); + /* + * The auto reload and hold bit makes the count periodic. Let the pti= mer + * carry the period, so that it reloads at the expiry rather than when= the + * callback runs. + */ + ptimer_run(xt->ptimer, !(xt->regs[R_TCSR] & TCSR_ARHT)); } =20 static void @@ -195,6 +205,19 @@ timer_write(void *opaque, hwaddr addr, break; } =20 + case R_TLR: + xt->regs[addr] =3D value; + /* + * A running periodic count takes the new load value at its ne= xt + * reload. + */ + if (xt->regs[R_TCSR] & TCSR_ENT) { + ptimer_transaction_begin(xt->ptimer); + ptimer_set_limit(xt->ptimer, timer_limit(xt), 0); + ptimer_transaction_commit(xt->ptimer); + } + break; + default: if (addr < ARRAY_SIZE(xt->regs)) xt->regs[addr] =3D value; @@ -226,9 +249,6 @@ static void timer_hit(void *opaque) XpsTimerState *t =3D xt->parent; D(fprintf(stderr, "%s %d\n", __func__, xt->nr)); xt->regs[R_TCSR] |=3D TCSR_TINT; - - if (xt->regs[R_TCSR] & TCSR_ARHT) - timer_enable(xt); timer_update_irq(t); } =20 --=20 2.51.0