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Sun, 23 Aug 2026 08:07:54 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Xianglai Li , Alistair Francis , Chinmay Rath , Sunil V L , qemu-riscv@nongnu.org, Alexander Bulekov , Zhao Liu , Eric Farman , Laurent Vivier , Peter Maydell , Chao Liu , Liu Zhiwei , Palmer Dabbelt , Song Gao <17746591750@163.com>, Harsh Prateek Bora , Glenn Miles , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Daniel Henrique Barboza , Pierrick Bouvier , qemu-s390x@nongnu.org, Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Igor Mammedov , Aleksandar Rikalo , Nicholas Piggin , Cornelia Huck , Richard Henderson , Ilya Leoshkevich , Fabiano Rosas , Aurelien Jarno , Paolo Bonzini , Ani Sinha , Bibo Mao , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Matthew Rosato , Weiwei Li , Darren Kenny Subject: [PATCH 01/12] accel: use a shared TYPE_ACCEL_CPU parent Date: Sun, 23 Aug 2026 23:07:19 +0800 Message-ID: <20260823150731.896-2-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260823150731.896-1-luoyonggang@gmail.com> References: <20260823150731.896-1-luoyonggang@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=luoyonggang@gmail.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787497797209158500 Content-Type: text/plain; charset="utf-8" - TYPE_ACCEL_CPU was "accel-" CPU_RESOLVING_TYPE, so each arch compiled a different parent (accel-arm-cpu, accel-riscv-cpu, ...). Common code registered only one of those names from target_cpu_type() at MODULE_INIT_QOM. - A combined binary still registers every linked AccelCPU subclass. RISC-V tcg-accel-riscv-cpu has parent accel-riscv-cpu even when the selected target is ARM, so the old one-parent type_init does not cover the other family. Creating the parent in the subclass register path would hide that, but it keeps per-arch parents that AccelCPUClass does not need. - AccelCPUClass is arch-independent. The parent only supplies class_size and ACCEL_CPU_CLASS(). Make TYPE_ACCEL_CPU the fixed abstract type accel-cpu and register it once next to TYPE_ACCEL. - Leaf names still encode the CPU type so accel_init_cpu_interfaces() can look up "-accel-" CPU_RESOLVING_TYPE (for example tcg-accel-arm-cpu). ACCEL_CPU_NAME() keeps that string; it is no longer derived from the parent type name. - Drop register_accel_target_type(). Subclasses keep type_register_static() with .parent =3D TYPE_ACCEL_CPU. Signed-off-by: Yonggang Luo --- accel/accel-common.c | 21 ++++++--------------- include/accel/accel-cpu-target.h | 3 +-- include/accel/accel-cpu.h | 2 ++ 3 files changed, 9 insertions(+), 17 deletions(-) diff --git a/accel/accel-common.c b/accel/accel-common.c index 00a400243f0..c4c365f38c7 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -126,21 +126,12 @@ static const TypeInfo accel_types[] =3D { .instance_size =3D sizeof(AccelState), .abstract =3D true, }, + { + .name =3D TYPE_ACCEL_CPU, + .parent =3D TYPE_OBJECT, + .abstract =3D true, + .class_size =3D sizeof(AccelCPUClass), + }, }; =20 DEFINE_TYPES(accel_types) - -static void register_accel_target_type(void) -{ - g_autofree char *name =3D g_strconcat("accel-", target_cpu_type(), NUL= L); - const TypeInfo accel_cpu_type =3D { - .name =3D name, - .parent =3D TYPE_OBJECT, - .abstract =3D true, - .class_size =3D sizeof(AccelCPUClass), - }; - - type_register_static(&accel_cpu_type); -} - -type_init(register_accel_target_type); diff --git a/include/accel/accel-cpu-target.h b/include/accel/accel-cpu-tar= get.h index 6feb344e29b..cf33ebd79fc 100644 --- a/include/accel/accel-cpu-target.h +++ b/include/accel/accel-cpu-target.h @@ -24,8 +24,7 @@ #include "accel/accel-cpu.h" #include "cpu.h" =20 -#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE -#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU) +#define ACCEL_CPU_NAME(name) (name "-accel-" CPU_RESOLVING_TYPE) DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) =20 #endif /* ACCEL_CPU_H */ diff --git a/include/accel/accel-cpu.h b/include/accel/accel-cpu.h index 9e7eede7c3c..5cfc2b24223 100644 --- a/include/accel/accel-cpu.h +++ b/include/accel/accel-cpu.h @@ -12,6 +12,8 @@ #include "qom/object.h" #include "hw/core/cpu.h" =20 +#define TYPE_ACCEL_CPU "accel-cpu" + typedef struct AccelCPUClass { ObjectClass parent_class; =20 --=20 2.52.0.windows.1 From nobody Thu Sep 10 13:25:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sun, 23 Aug 2026 08:08:03 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Xianglai Li , Alistair Francis , Chinmay Rath , Sunil V L , qemu-riscv@nongnu.org, Alexander Bulekov , Zhao Liu , Eric Farman , Laurent Vivier , Peter Maydell , Chao Liu , Liu Zhiwei , Palmer Dabbelt , Song Gao <17746591750@163.com>, Harsh Prateek Bora , Glenn Miles , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Daniel Henrique Barboza , Pierrick Bouvier , qemu-s390x@nongnu.org, Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Igor Mammedov , Aleksandar Rikalo , Nicholas Piggin , Cornelia Huck , Richard Henderson , Ilya Leoshkevich , Fabiano Rosas , Aurelien Jarno , Paolo Bonzini , Ani Sinha , Bibo Mao , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Matthew Rosato , Weiwei Li , Darren Kenny Subject: [PATCH 02/12] hw/riscv/virt: use unique QOM name and target filter Date: Sun, 23 Aug 2026 23:07:20 +0800 Message-ID: <20260823150731.896-3-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260823150731.896-1-luoyonggang@gmail.com> References: <20260823150731.896-1-luoyonggang@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=luoyonggang@gmail.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787497821262158500 Content-Type: text/plain; charset="utf-8" - Set TYPE_RISCV_VIRT_MACHINE to MACHINE_TYPE_NAME("riscv-virt") so RISC-V virt no longer collides with ARM virt-machine in one process. - Register TYPE_TARGET_SPECIFIC with is_available =3D target_base_riscv. - Keep -machine virt via mc->alias after the selected target is applied. Signed-off-by: Yonggang Luo --- hw/riscv/virt.c | 6 +++++- include/hw/riscv/virt.h | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2d242ef71a5..1b672b2169d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -22,6 +22,7 @@ #include "qemu/units.h" #include "qemu/error-report.h" #include "qemu/guest-random.h" +#include "qemu/target-info.h" #include "qapi/error.h" #include "hw/core/boards.h" #include "hw/core/loader.h" @@ -1718,7 +1719,9 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) MachineClass *mc =3D MACHINE_CLASS(oc); HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(oc); =20 + TARGET_SPECIFIC_CLASS(oc)->is_available =3D target_base_riscv; mc->desc =3D "RISC-V VirtIO board"; + mc->alias =3D "virt"; mc->init =3D virt_machine_init; mc->max_cpus =3D VIRT_CPUS_MAX; mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; @@ -1782,7 +1785,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) } =20 static const TypeInfo virt_machine_typeinfo =3D { - .name =3D MACHINE_TYPE_NAME("virt"), + .name =3D TYPE_RISCV_VIRT_MACHINE, .parent =3D TYPE_MACHINE, .class_init =3D virt_machine_class_init, .instance_init =3D virt_machine_instance_init, @@ -1790,6 +1793,7 @@ static const TypeInfo virt_machine_typeinfo =3D { .instance_size =3D sizeof(RISCVVirtState), .interfaces =3D (const InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, + { TYPE_TARGET_SPECIFIC }, { } }, }; diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 36a2def4109..5559783aebb 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -30,7 +30,7 @@ #define VIRT_SOCKETS_MAX_BITS 2 #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS) =20 -#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") +#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("riscv-virt") typedef struct RISCVVirtState RISCVVirtState; DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE, TYPE_RISCV_VIRT_MACHINE) --=20 2.52.0.windows.1 From nobody Thu Sep 10 13:25:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1787497748; cv=none; d=zohomail.com; s=zohoarc; b=eOY8Iz6c8GtUN6U1G8TbXS30Ta5PkliSrENPwT3uhmzEMX4dcFY/YgAVdGICMykww0b8SXx/2+64OW9xTBsHRDWZncmaiL0Kc8xgBJgkseUP+1/2TACrLC639myUs5ADPjo3Oao25I0f4JZcCPPjQXmphsmEJgiNQuBxd8N9CVU= ARC-Message-Signature: i=1; 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Sun, 23 Aug 2026 08:08:12 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Xianglai Li , Alistair Francis , Chinmay Rath , Sunil V L , qemu-riscv@nongnu.org, Alexander Bulekov , Zhao Liu , Eric Farman , Laurent Vivier , Peter Maydell , Chao Liu , Liu Zhiwei , Palmer Dabbelt , Song Gao <17746591750@163.com>, Harsh Prateek Bora , Glenn Miles , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Daniel Henrique Barboza , Pierrick Bouvier , qemu-s390x@nongnu.org, Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Igor Mammedov , Aleksandar Rikalo , Nicholas Piggin , Cornelia Huck , Richard Henderson , Ilya Leoshkevich , Fabiano Rosas , Aurelien Jarno , Paolo Bonzini , Ani Sinha , Bibo Mao , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Matthew Rosato , Weiwei Li , Darren Kenny Subject: [PATCH 03/12] hw/arm/virt: use unique QOM name and target filter Date: Sun, 23 Aug 2026 23:07:21 +0800 Message-ID: <20260823150731.896-4-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260823150731.896-1-luoyonggang@gmail.com> References: <20260823150731.896-1-luoyonggang@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=luoyonggang@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787497751462158500 Content-Type: text/plain; charset="utf-8" - Set TYPE_VIRT_MACHINE to MACHINE_TYPE_NAME("arm-virt") so ARM virt no longer collides with other virt-machine types in one process. - Register TYPE_TARGET_SPECIFIC with is_available =3D target_base_arm on the abstract parent. - Keep -machine virt via mc->alias on the latest versioned machine. Signed-off-by: Yonggang Luo --- hw/arm/virt.c | 2 ++ include/hw/arm/virt.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index daba9af79f1..c2ace7706f1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -4161,6 +4161,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) MachineClass *mc =3D MACHINE_CLASS(oc); HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(oc); =20 + TARGET_SPECIFIC_CLASS(oc)->is_available =3D target_base_arm; mc->init =3D machvirt_init; /* Start with max_cpus set to 512, which is the maximum supported by K= VM. * The value may be reduced later when we have more information about = the @@ -4431,6 +4432,7 @@ static const TypeInfo virt_machine_info =3D { .instance_finalize =3D virt_instance_finalize, .interfaces =3D (const InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, + { TYPE_TARGET_SPECIFIC }, { } }, }; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 22e66d1a113..383ee320948 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -215,7 +215,7 @@ struct VirtMachineState { =20 #define VIRT_ECAM_ID(high) (high ? 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Sun, 23 Aug 2026 08:08:21 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Xianglai Li , Alistair Francis , Chinmay Rath , Sunil V L , qemu-riscv@nongnu.org, Alexander Bulekov , Zhao Liu , Eric Farman , Laurent Vivier , Peter Maydell , Chao Liu , Liu Zhiwei , Palmer Dabbelt , Song Gao <17746591750@163.com>, Harsh Prateek Bora , Glenn Miles , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Daniel Henrique Barboza , Pierrick Bouvier , qemu-s390x@nongnu.org, Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Igor Mammedov , Aleksandar Rikalo , Nicholas Piggin , Cornelia Huck , Richard Henderson , Ilya Leoshkevich , Fabiano Rosas , Aurelien Jarno , Paolo Bonzini , Ani Sinha , Bibo Mao , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Matthew Rosato , Weiwei Li , Darren Kenny Subject: [PATCH 04/12] hw/arm/virt: prefix ACPI helpers with arm_virt_ Date: Sun, 23 Aug 2026 23:07:22 +0800 Message-ID: <20260823150731.896-5-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260823150731.896-1-luoyonggang@gmail.com> References: <20260823150731.896-1-luoyonggang@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=luoyonggang@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787497747360158500 Content-Type: text/plain; charset="utf-8" - virt_acpi_setup and virt_is_acpi_enabled are generic names also used by RISC-V and LoongArch virt. A combined binary cannot export two functions with the same C symbol. - Rename the ARM helpers to arm_virt_acpi_setup and arm_virt_is_acpi_enabled. Leave the trace event virt_acpi_setup unchanged; it is a separate identifier. Signed-off-by: Yonggang Luo Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/virt-acpi-build.c | 4 ++-- hw/arm/virt.c | 12 ++++++------ include/hw/arm/virt.h | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index f6386088b6f..a4a0d2c9997 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -1556,7 +1556,7 @@ static const VMStateDescription vmstate_virt_acpi_bui= ld =3D { }, }; =20 -void virt_acpi_setup(VirtMachineState *vms) +void arm_virt_acpi_setup(VirtMachineState *vms) { AcpiBuildTables tables; AcpiBuildState *build_state; @@ -1567,7 +1567,7 @@ void virt_acpi_setup(VirtMachineState *vms) return; } =20 - if (!virt_is_acpi_enabled(vms)) { + if (!arm_virt_is_acpi_enabled(vms)) { trace_virt_acpi_setup(); return; } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c2ace7706f1..4b9e1e50d44 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -770,7 +770,7 @@ static void fdt_add_cpu_nodes(VirtMachineState *vms) &bottom_node, CPU_TOPOLOGY_LEVEL_SOCKET); if (cache_at_topo_level) { - if (bottom_node =3D=3D 1 && !virt_is_acpi_enabled(vms)) + if (bottom_node =3D=3D 1 && !arm_virt_is_acpi_enabled(vms)) error_setg( &error_fatal, "Cannot share L1 at socket_id %d." @@ -810,7 +810,7 @@ static void fdt_add_cpu_nodes(VirtMachineState *vms) top_cluster, bottom_cluster, cp= u, &cluster_offset); - if (bottom_cluster =3D=3D 1 && !virt_is_acpi_enabled(vms))= { + if (bottom_cluster =3D=3D 1 && !arm_virt_is_acpi_enabled(v= ms)) { error_setg(&error_fatal, "Cannot share L1 at socket_id %d, cluster_id %d. " "DT limitation on sharing at cache level =3D 1.", @@ -2037,7 +2037,7 @@ static void create_smmuv3_dev_dtb(VirtMachineState *v= ms, DeviceState *dev, hwaddr base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); MachineState *ms =3D MACHINE(vms); =20 - if (!(vms->bootinfo.firmware_loaded && virt_is_acpi_enabled(vms))) { + if (!(vms->bootinfo.firmware_loaded && arm_virt_is_acpi_enabled(vms)))= { if (object_property_get_bool(OBJECT(dev), "accel", &error_abort)) { error_setg(errp, "SMMUv3 with accel=3Don not supported for DT"= ); return; @@ -2447,7 +2447,7 @@ void virt_machine_done(Notifier *notifier, void *data) pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus, &error_abort); =20 - virt_acpi_setup(vms); + arm_virt_acpi_setup(vms); virt_build_smbios(vms); } =20 @@ -3211,7 +3211,7 @@ static void machvirt_init(MachineState *machine) create_pcie(vms); create_cxl_host_reg_region(vms); =20 - if (aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { + if (aarch64 && firmware_loaded && arm_virt_is_acpi_enabled(vms)) { vms->acpi_dev =3D create_acpi_ged(vms); vms->generic_error_notifier.notify =3D virt_generic_error_req; notifier_list_add(&acpi_generic_error_notifiers, @@ -3561,7 +3561,7 @@ static void virt_set_oem_table_id(Object *obj, const = char *value, } =20 =20 -bool virt_is_acpi_enabled(const VirtMachineState *vms) +bool arm_virt_is_acpi_enabled(const VirtMachineState *vms) { if (vms->acpi =3D=3D ON_OFF_AUTO_OFF) { return false; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 383ee320948..2ee61cc5a06 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -218,8 +218,8 @@ struct VirtMachineState { #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("arm-virt") OBJECT_DECLARE_TYPE(VirtMachineState, VirtMachineClass, VIRT_MACHINE) =20 -void virt_acpi_setup(VirtMachineState *vms); -bool virt_is_acpi_enabled(const VirtMachineState *vms); +void arm_virt_acpi_setup(VirtMachineState *vms); +bool arm_virt_is_acpi_enabled(const VirtMachineState *vms); =20 #define CLIDR_CTYPE_NO_CACHE 0x00 #define CLIDR_CTYPE_I_CACHE 0x01 --=20 2.52.0.windows.1 From nobody Thu Sep 10 13:25:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sun, 23 Aug 2026 08:08:31 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Xianglai Li , Alistair Francis , Chinmay Rath , Sunil V L , qemu-riscv@nongnu.org, Alexander Bulekov , Zhao Liu , Eric Farman , Laurent Vivier , Peter Maydell , Chao Liu , Liu Zhiwei , Palmer Dabbelt , Song Gao <17746591750@163.com>, Harsh Prateek Bora , Glenn Miles , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Daniel Henrique Barboza , Pierrick Bouvier , qemu-s390x@nongnu.org, Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Igor Mammedov , Aleksandar Rikalo , Nicholas Piggin , Cornelia Huck , Richard Henderson , Ilya Leoshkevich , Fabiano Rosas , Aurelien Jarno , Paolo Bonzini , Ani Sinha , Bibo Mao , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Matthew Rosato , Weiwei Li , Darren Kenny Subject: [PATCH 05/12] hw/riscv/virt: prefix ACPI helpers with riscv_virt_ Date: Sun, 23 Aug 2026 23:07:23 +0800 Message-ID: <20260823150731.896-6-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260823150731.896-1-luoyonggang@gmail.com> References: <20260823150731.896-1-luoyonggang@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=luoyonggang@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787497877507158500 Content-Type: text/plain; charset="utf-8" - virt_acpi_setup and virt_is_acpi_enabled collide with ARM virt when both architectures are linked into one qemu-system binary. - Rename the RISC-V helpers to riscv_virt_acpi_setup and riscv_virt_is_acpi_enabled. Leave file-local virt_acpi_build* names unchanged. Signed-off-by: Yonggang Luo Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt-acpi-build.c | 2 +- hw/riscv/virt.c | 6 +++--- include/hw/riscv/virt.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 59c454f4f94..832261391d5 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -1017,7 +1017,7 @@ static const VMStateDescription vmstate_virt_acpi_bui= ld =3D { }, }; =20 -void virt_acpi_setup(RISCVVirtState *s) +void riscv_virt_acpi_setup(RISCVVirtState *s) { AcpiBuildTables tables; AcpiBuildState *build_state; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 1b672b2169d..16edad64f60 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1293,8 +1293,8 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) =20 virt_build_smbios(s); =20 - if (virt_is_acpi_enabled(s)) { - virt_acpi_setup(s); + if (riscv_virt_is_acpi_enabled(s)) { + riscv_virt_acpi_setup(s); } } =20 @@ -1652,7 +1652,7 @@ static void virt_set_iommu_sys(Object *obj, Visitor *= v, const char *name, visit_type_OnOffAuto(v, name, &s->iommu_sys, errp); } =20 -bool virt_is_acpi_enabled(RISCVVirtState *s) +bool riscv_virt_is_acpi_enabled(RISCVVirtState *s) { return s->acpi !=3D ON_OFF_AUTO_OFF; } diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 5559783aebb..38ad8b0097e 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -133,9 +133,9 @@ enum { #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 1 + FDT_APLIC_INT_CELLS) =20 -bool virt_is_acpi_enabled(RISCVVirtState *s); +bool riscv_virt_is_acpi_enabled(RISCVVirtState *s); bool virt_is_iommu_sys_enabled(RISCVVirtState *s); -void virt_acpi_setup(RISCVVirtState *vms); +void riscv_virt_acpi_setup(RISCVVirtState *vms); =20 /* * The virt machine physical address space used by some of the devices --=20 2.52.0.windows.1 From nobody Thu Sep 10 13:25:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Sun, 23 Aug 2026 08:08:43 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Xianglai Li , Alistair Francis , Chinmay Rath , Sunil V L , qemu-riscv@nongnu.org, Alexander Bulekov , Zhao Liu , Eric Farman , Laurent Vivier , Peter Maydell , Chao Liu , Liu Zhiwei , Palmer Dabbelt , Song Gao <17746591750@163.com>, Harsh Prateek Bora , Glenn Miles , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Daniel Henrique Barboza , Pierrick Bouvier , qemu-s390x@nongnu.org, Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Igor Mammedov , Aleksandar Rikalo , Nicholas Piggin , Cornelia Huck , Richard Henderson , Ilya Leoshkevich , Fabiano Rosas , Aurelien Jarno , Paolo Bonzini , Ani Sinha , Bibo Mao , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Matthew Rosato , Weiwei Li , Darren Kenny Subject: [PATCH 06/12] hw/loongarch/virt: prefix ACPI helper with loongarch_virt_ Date: Sun, 23 Aug 2026 23:07:24 +0800 Message-ID: <20260823150731.896-7-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260823150731.896-1-luoyonggang@gmail.com> References: <20260823150731.896-1-luoyonggang@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=luoyonggang@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787497759027158500 Content-Type: text/plain; charset="utf-8" - virt_acpi_setup is the same C symbol used by ARM and RISC-V virt. Rename it now so a later combined binary does not need meson -D prefixes for LoongArch. - Rename the file-local virt_is_acpi_enabled to loongarch_virt_is_acpi_enabled to match. Signed-off-by: Yonggang Luo Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Song Gao --- hw/loongarch/virt-acpi-build.c | 6 +++--- hw/loongarch/virt.c | 2 +- include/hw/loongarch/virt.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/loongarch/virt-acpi-build.c b/hw/loongarch/virt-acpi-build.c index a0b445f297b..bbbac289b49 100644 --- a/hw/loongarch/virt-acpi-build.c +++ b/hw/loongarch/virt-acpi-build.c @@ -674,7 +674,7 @@ static const VMStateDescription vmstate_acpi_build =3D { }, }; =20 -static bool virt_is_acpi_enabled(LoongArchVirtMachineState *lvms) +static bool loongarch_virt_is_acpi_enabled(LoongArchVirtMachineState *lvms) { if (lvms->acpi =3D=3D ON_OFF_AUTO_OFF) { return false; @@ -682,7 +682,7 @@ static bool virt_is_acpi_enabled(LoongArchVirtMachineSt= ate *lvms) return true; } =20 -void virt_acpi_setup(LoongArchVirtMachineState *lvms) +void loongarch_virt_acpi_setup(LoongArchVirtMachineState *lvms) { AcpiBuildTables tables; AcpiBuildState *build_state; @@ -692,7 +692,7 @@ void virt_acpi_setup(LoongArchVirtMachineState *lvms) return; } =20 - if (!virt_is_acpi_enabled(lvms)) { + if (!loongarch_virt_is_acpi_enabled(lvms)) { ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); return; } diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 6693dea647b..74c9668b6e6 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -242,7 +242,7 @@ static void virt_done(Notifier *notifier, void *data) LoongArchVirtMachineState *lvms =3D container_of(notifier, LoongArchVirtMachineState, machine_d= one); virt_build_smbios(lvms); - virt_acpi_setup(lvms); + loongarch_virt_acpi_setup(lvms); virt_fdt_setup(lvms); } =20 diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index d39a9bbf5dd..72268466def 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -132,7 +132,7 @@ struct LoongArchVirtMachineState { =20 #define TYPE_LOONGARCH_VIRT_MACHINE MACHINE_TYPE_NAME("virt") OBJECT_DECLARE_SIMPLE_TYPE(LoongArchVirtMachineState, LOONGARCH_VIRT_MACHI= NE) -void virt_acpi_setup(LoongArchVirtMachineState *lvms); +void loongarch_virt_acpi_setup(LoongArchVirtMachineState *lvms); void virt_fdt_setup(LoongArchVirtMachineState *lvms); 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Sun, 23 Aug 2026 08:08:51 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Xianglai Li , Alistair Francis , Chinmay Rath , Sunil V L , qemu-riscv@nongnu.org, Alexander Bulekov , Zhao Liu , Eric Farman , Laurent Vivier , Peter Maydell , Chao Liu , Liu Zhiwei , Palmer Dabbelt , Song Gao <17746591750@163.com>, Harsh Prateek Bora , Glenn Miles , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Daniel Henrique Barboza , Pierrick Bouvier , qemu-s390x@nongnu.org, Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Igor Mammedov , Aleksandar Rikalo , Nicholas Piggin , Cornelia Huck , Richard Henderson , Ilya Leoshkevich , Fabiano Rosas , Aurelien Jarno , Paolo Bonzini , Ani Sinha , Bibo Mao , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Matthew Rosato , Weiwei Li , Darren Kenny Subject: [PATCH 07/12] target/riscv: uniquify TCG crc32, crc32c, and wfi helper names Date: Sun, 23 Aug 2026 23:07:25 +0800 Message-ID: <20260823150731.896-8-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260823150731.896-1-luoyonggang@gmail.com> References: <20260823150731.896-1-luoyonggang@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=luoyonggang@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787497795700158500 Content-Type: text/plain; charset="utf-8" - ARM already exports helper_crc32, helper_crc32c, helper_wfi, and the matching helper_info_* objects. RISC-V used the same DEF_HELPER names, which collide in a combined qemu-system link. - Rename the RISC-V helpers to riscv_crc32, riscv_crc32c, and riscv_wfi so the generated C symbols are unique without meson -D prefixes. Signed-off-by: Yonggang Luo --- target/riscv/helper.h | 6 +++--- target/riscv/tcg/bitmanip_helper.c | 4 ++-- target/riscv/tcg/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/tcg/insn_trans/trans_xlrbr.c.inc | 4 ++-- target/riscv/tcg/op_helper.c | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 542b7c264fc..dd4623d2a79 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -84,8 +84,8 @@ DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(riscv_crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(riscv_crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl) =20 /* Floating Point - Half Precision */ DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64) @@ -135,7 +135,7 @@ DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(mnret, tl, env) DEF_HELPER_1(ctr_clear, void, env) -DEF_HELPER_1(wfi, void, env) +DEF_HELPER_1(riscv_wfi, void, env) DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) DEF_HELPER_1(tlb_flush_all, void, env) diff --git a/target/riscv/tcg/bitmanip_helper.c b/target/riscv/tcg/bitmanip= _helper.c index 1156a87dd31..18ad2fae1c9 100644 --- a/target/riscv/tcg/bitmanip_helper.c +++ b/target/riscv/tcg/bitmanip_helper.c @@ -132,7 +132,7 @@ target_ulong HELPER(xperm8)(target_ulong rs1, target_ul= ong rs2) return do_xperm(rs1, rs2, 3); } =20 -target_ulong HELPER(crc32)(target_ulong rs1, target_ulong sz) +target_ulong HELPER(riscv_crc32)(target_ulong rs1, target_ulong sz) { for (target_ulong i =3D 0; i < sz; i++) { rs1 =3D crc32_table[rs1 & 0xFF] ^ (rs1 >> 8); @@ -141,7 +141,7 @@ target_ulong HELPER(crc32)(target_ulong rs1, target_ulo= ng sz) return rs1; } =20 -target_ulong HELPER(crc32c)(target_ulong rs1, target_ulong sz) +target_ulong HELPER(riscv_crc32c)(target_ulong rs1, target_ulong sz) { for (target_ulong i =3D 0; i < sz; i++) { rs1 =3D crc32c_table[rs1 & 0xFF] ^ (rs1 >> 8); diff --git a/target/riscv/tcg/insn_trans/trans_privileged.c.inc b/target/ri= scv/tcg/insn_trans/trans_privileged.c.inc index a8eaccef67e..0df78e89745 100644 --- a/target/riscv/tcg/insn_trans/trans_privileged.c.inc +++ b/target/riscv/tcg/insn_trans/trans_privileged.c.inc @@ -144,7 +144,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a) #ifndef CONFIG_USER_ONLY decode_save_opc(ctx, 0); gen_update_pc(ctx, ctx->cur_insn_len); - gen_helper_wfi(tcg_env); + gen_helper_riscv_wfi(tcg_env); return true; #else return false; diff --git a/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc b/target/riscv/t= cg/insn_trans/trans_xlrbr.c.inc index 01da2b6ce1d..795231f0839 100644 --- a/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc +++ b/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc @@ -29,11 +29,11 @@ static bool gen_crc(DisasContext *ctx, arg_r2 *a, #define TRANS_CRC32(NAME, SIZE) \ static bool trans_crc32_##NAME(DisasContext *ctx, arg_r2 *a) \ { if (SIZE =3D=3D 8) { REQUIRE_64BIT(ctx); }; \ - return gen_crc(ctx, a, gen_helper_crc32, tcg_constant_tl(SIZE)); } + return gen_crc(ctx, a, gen_helper_riscv_crc32, tcg_constant_tl(SIZE)= ); } #define TRANS_CRC32C(NAME, SIZE) \ static bool trans_crc32c_##NAME(DisasContext *ctx, arg_r2 *a) \ { if (SIZE =3D=3D 8) { REQUIRE_64BIT(ctx); }; \ - return gen_crc(ctx, a, gen_helper_crc32c, tcg_constant_tl(SIZE)); } + return gen_crc(ctx, a, gen_helper_riscv_crc32c, tcg_constant_tl(SIZE= )); } =20 TRANS_CRC32(b, 1); TRANS_CRC32(h, 2); diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index ba3c7da375a..52bcedc7c6e 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -541,7 +541,7 @@ void helper_ctr_clear(CPURISCVState *env) riscv_ctr_clear(env); } =20 -void helper_wfi(CPURISCVState *env) +void HELPER(riscv_wfi)(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); bool rvs =3D riscv_has_ext(env, RVS); --=20 2.52.0.windows.1 From nobody Thu Sep 10 13:25:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1787497793; cv=none; d=zohomail.com; s=zohoarc; b=QSVbpcTUaQKwjUBWf2kZZN5Mo3FaJ+11mx7ghxATXhDCsnmEAiOPModzE37Q2spo1RihfIqpUWuM2WqxRRo1GdkwCUS8g4Pn4tbo7BSBN+tM0+1FH456vWR9/QjG1nI+Zhd1WMw99qdtOYCLpS28fbeunKSDdbAuZHcF/sn+usQ= ARC-Message-Signature: i=1; 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Sun, 23 Aug 2026 08:09:00 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Xianglai Li , Alistair Francis , Chinmay Rath , Sunil V L , qemu-riscv@nongnu.org, Alexander Bulekov , Zhao Liu , Eric Farman , Laurent Vivier , Peter Maydell , Chao Liu , Liu Zhiwei , Palmer Dabbelt , Song Gao <17746591750@163.com>, Harsh Prateek Bora , Glenn Miles , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Daniel Henrique Barboza , Pierrick Bouvier , qemu-s390x@nongnu.org, Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Igor Mammedov , Aleksandar Rikalo , Nicholas Piggin , Cornelia Huck , Richard Henderson , Ilya Leoshkevich , Fabiano Rosas , Aurelien Jarno , Paolo Bonzini , Ani Sinha , Bibo Mao , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Matthew Rosato , Weiwei Li , Darren Kenny Subject: [PATCH 08/12] target/riscv: seed cfg.big_endian from TargetInfo Date: Sun, 23 Aug 2026 23:07:26 +0800 Message-ID: <20260823150731.896-9-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260823150731.896-1-luoyonggang@gmail.com> References: <20260823150731.896-1-luoyonggang@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=luoyonggang@gmail.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787497795723158500 Content-Type: text/plain; charset="utf-8" GDB register packets use target_big_endian() only (gdb_get_reg16/32/64). RISC-V gdbstub already goes through those helpers, so future GDB big-endian support does not need a second endian source in the CPU gdbstub. It needs TargetInfo and the hart to agree. Hart endian is cpu->cfg.big_endian, copied into mstatus MBE/SBE/UBE at reset. The CPU property still defaults to little-endian, so a big-endian TargetInfo would make GDB swap as BE while the hart stayed LE. - Initialize cfg.big_endian from target_big_endian() in cpu init so a big-endian TargetInfo also sets the hart. - Fail realize when -cpu big-endian=3D disagrees with that selection. GDB cannot follow a per-CPU override, so a split would silently corrupt register byte order. Signed-off-by: Yonggang Luo --- target/riscv/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5a82e6563bf..0681bec0bef 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -29,6 +29,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "qemu/error-report.h" +#include "qemu/target-info.h" #include "qemu/timer.h" #include "hw/core/qdev-properties.h" #include "hw/core/qdev-prop-internal.h" @@ -1226,6 +1227,13 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 + if (cpu->cfg.big_endian !=3D target_big_endian()) { + error_setg(errp, + "CPU big-endian=3D%s does not match selected target end= ian", + cpu->cfg.big_endian ? "on" : "off"); + return; + } + cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -1407,6 +1415,8 @@ static void riscv_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; =20 + cpu->cfg.big_endian =3D target_big_endian(); + env->misa_mxl =3D mcc->def->misa_mxl_max; =20 #ifndef CONFIG_USER_ONLY --=20 2.52.0.windows.1 From nobody Thu Sep 10 13:25:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1787497865; cv=none; d=zohomail.com; s=zohoarc; b=EozrwTtPIUNZi5l9fLPRkz0sLFhrA7IhdKnkVwzkjLyiF3lrv/Hrx/H7e2IWfcqatoJPLb90vNdu2EJ0FCVXuWHz+uZST80BPBNhZOkQMQp8nd7/V7R6G7EsSk4b/O7URjO0XHt4VtJWmxrryvMqAtcko4obj1+OkGo9UVfG8g0= ARC-Message-Signature: i=1; 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Sun, 23 Aug 2026 08:09:09 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Xianglai Li , Alistair Francis , Chinmay Rath , Sunil V L , qemu-riscv@nongnu.org, Alexander Bulekov , Zhao Liu , Eric Farman , Laurent Vivier , Peter Maydell , Chao Liu , Liu Zhiwei , Palmer Dabbelt , Song Gao <17746591750@163.com>, Harsh Prateek Bora , Glenn Miles , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Daniel Henrique Barboza , Pierrick Bouvier , qemu-s390x@nongnu.org, Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Igor Mammedov , Aleksandar Rikalo , Nicholas Piggin , Cornelia Huck , Richard Henderson , Ilya Leoshkevich , Fabiano Rosas , Aurelien Jarno , Paolo Bonzini , Ani Sinha , Bibo Mao , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Matthew Rosato , Weiwei Li , Darren Kenny Subject: [PATCH 09/12] target-info: register le and be TargetInfo variants Date: Sun, 23 Aug 2026 23:07:27 +0800 Message-ID: <20260823150731.896-10-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260823150731.896-1-luoyonggang@gmail.com> References: <20260823150731.896-1-luoyonggang@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=luoyonggang@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787497865802158500 Content-Type: text/plain; charset="utf-8" - Register target-info--le and -be from one system target-info-def.c unit, sharing arch fields. - Mark is_default from TARGET_BIG_ENDIAN so riscv/arm stay LE and ppc/s390x stay BE when -target is omitted. - Pick the unique default in target_info_qom_set_target() when more than one TargetInfo is registered. Leave user-mode as a single target_info(). Signed-off-by: Yonggang Luo --- include/qemu/target-info-impl.h | 6 ++++ include/qemu/target-info-init.h | 29 +++++++++++++--- target-info-def.c | 61 +++++++++++++++++++++++++-------- target-info-qom.c | 33 ++++++++++++++---- 4 files changed, 104 insertions(+), 25 deletions(-) diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-imp= l.h index de329ec2b86..b4222e4455e 100644 --- a/include/qemu/target-info-impl.h +++ b/include/qemu/target-info-impl.h @@ -23,6 +23,12 @@ typedef struct TargetInfo { const char *cpu_type; /* related to TARGET_BIG_ENDIAN definition */ EndianMode endianness; + /* + * True on the endian variant that matches this translation unit's + * TARGET_BIG_ENDIAN. target_info_qom_set_target() uses this when + * more than one TargetInfo is registered and -target is omitted. + */ + bool is_default; /* * runtime equivalent of * TARGET_PAGE_BITS_VARY ? TARGET_PAGE_BITS_LEGACY : TARGET_PAGE_BITS diff --git a/include/qemu/target-info-init.h b/include/qemu/target-info-ini= t.h index b7024c9faef..25d00adcc66 100644 --- a/include/qemu/target-info-init.h +++ b/include/qemu/target-info-init.h @@ -37,15 +37,34 @@ const TargetInfo *target_info(void) \ #include "qemu/target-info-qom.h" #include "qom/object.h" =20 -#define target_info_init(ti_var) = \ -static const TypeInfo target_info_qom_target_type_info =3D { = \ - .name =3D TYPE_TARGET_INFO"-"TARGET_NAME, = \ +/* + * QOM type names are target-info--le and -be so both + * endian variants can be registered from one system translation unit. + */ +#define TARGET_INFO_QOM_SUFFIX_0 "-le" +#define TARGET_INFO_QOM_SUFFIX_1 "-be" + +#define TARGET_INFO_QOM_NAME(sel) = \ + TYPE_TARGET_INFO "-" TARGET_NAME glue(TARGET_INFO_QOM_SUFFIX_, sel) + +#define TARGET_INFO_QOM_TYPEINFO(ti_var, sel) = \ +static const TypeInfo glue(target_info_qom_type_, sel) =3D { = \ + .name =3D TARGET_INFO_QOM_NAME(sel), = \ .parent =3D TYPE_TARGET_INFO, = \ .instance_size =3D sizeof(TargetInfoQom), = \ .class_size =3D sizeof(TargetInfoQomClass), = \ .class_data =3D &ti_var, = \ -}; = \ -DEFINE_TARGET_INFO_TYPE(target_info_qom_target_type_info) +} + +#define target_info_init_le_be(ti_le, ti_be) = \ +TARGET_INFO_QOM_TYPEINFO(ti_le, 0); = \ +TARGET_INFO_QOM_TYPEINFO(ti_be, 1); = \ +static void do_qemu_init_target_info(void) = \ +{ = \ + type_register_static(&target_info_qom_type_0); = \ + type_register_static(&target_info_qom_type_1); = \ +} = \ +module_init(do_qemu_init_target_info, MODULE_INIT_TARGET_INFO) =20 #endif /* CONFIG_USER_ONLY */ #endif /* COMPILING_PER_TARGET */ diff --git a/target-info-def.c b/target-info-def.c index 5d38e405735..6722c43a08f 100644 --- a/target-info-def.c +++ b/target-info-def.c @@ -28,39 +28,72 @@ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) !=3D sizeof(CP= UState)); QEMU_BUILD_BUG_ON(TARGET_PAGE_BITS < TARGET_PAGE_BITS_MIN); #endif =20 -static const TargetInfo target_info_def =3D { - .target_name =3D TARGET_NAME, - .target_arch =3D glue(SYS_EMU_TARGET_, TARGET_ARCH), - .long_bits =3D TARGET_LONG_BITS, - .cpu_type =3D CPU_RESOLVING_TYPE, - .endianness =3D TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG : ENDIAN_MODE_LITT= LE, #ifdef TARGET_PAGE_BITS_VARY - .page_bits_vary =3D true, # ifdef TARGET_PAGE_BITS_LEGACY +# define TARGET_INFO_PAGE_BITS \ + .page_bits_vary =3D true, \ .page_bits_init =3D TARGET_PAGE_BITS_LEGACY, +# else +# define TARGET_INFO_PAGE_BITS \ + .page_bits_vary =3D true, # endif #else - .page_bits_vary =3D false, +# define TARGET_INFO_PAGE_BITS \ + .page_bits_vary =3D false, \ .page_bits_init =3D TARGET_PAGE_BITS, #endif =20 #ifndef CONFIG_USER_ONLY # ifdef CONFIG_MULTIPROCESS - .config_multiprocess =3D true, +# define TARGET_INFO_CONFIG_MULTIPROCESS .config_multiprocess =3D true, # else - .config_multiprocess =3D false, +# define TARGET_INFO_CONFIG_MULTIPROCESS .config_multiprocess =3D false, # endif # ifdef CONFIG_NITRO - .config_nitro =3D true, +# define TARGET_INFO_CONFIG_NITRO .config_nitro =3D true, # else - .config_nitro =3D false, +# define TARGET_INFO_CONFIG_NITRO .config_nitro =3D false, # endif # ifdef CONFIG_XEN - .config_xen =3D true, +# define TARGET_INFO_CONFIG_XEN .config_xen =3D true, # else - .config_xen =3D false, +# define TARGET_INFO_CONFIG_XEN .config_xen =3D false, # endif +# define TARGET_INFO_CONFIG \ + TARGET_INFO_CONFIG_MULTIPROCESS \ + TARGET_INFO_CONFIG_NITRO \ + TARGET_INFO_CONFIG_XEN +#else +# define TARGET_INFO_CONFIG #endif + +#define TARGET_INFO_COMMON = \ + .target_name =3D TARGET_NAME, = \ + .target_arch =3D glue(SYS_EMU_TARGET_, TARGET_ARCH), = \ + .long_bits =3D TARGET_LONG_BITS, = \ + .cpu_type =3D CPU_RESOLVING_TYPE, = \ + TARGET_INFO_PAGE_BITS = \ + TARGET_INFO_CONFIG + +#ifdef CONFIG_USER_ONLY +static const TargetInfo target_info_def =3D { + TARGET_INFO_COMMON + .endianness =3D TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG : ENDIAN_MODE_LITT= LE, }; =20 target_info_init(target_info_def) +#else +static const TargetInfo target_info_le =3D { + TARGET_INFO_COMMON + .endianness =3D ENDIAN_MODE_LITTLE, + .is_default =3D !TARGET_BIG_ENDIAN, +}; + +static const TargetInfo target_info_be =3D { + TARGET_INFO_COMMON + .endianness =3D ENDIAN_MODE_BIG, + .is_default =3D TARGET_BIG_ENDIAN, +}; + +target_info_init_le_be(target_info_le, target_info_be) +#endif diff --git a/target-info-qom.c b/target-info-qom.c index 68ad734049c..2c1c57b05fd 100644 --- a/target-info-qom.c +++ b/target-info-qom.c @@ -90,13 +90,34 @@ const TargetInfo *target_info(void) void target_info_qom_set_target(void) { g_autoptr(GSList) targets =3D object_class_get_list(TYPE_TARGET_INFO, = false); - + const TargetInfo *chosen =3D NULL; size_t num_found =3D g_slist_length(targets); - if (num_found !=3D 1) { - error_setg(&error_fatal, num_found =3D=3D 0 ? - "no target-info is available" : - "more than one target-info is available"); + size_t num_default =3D 0; + + if (num_found =3D=3D 0) { + error_setg(&error_fatal, "no target-info is available"); + } + + if (num_found =3D=3D 1) { + target_info_ptr =3D TARGET_INFO_CLASS(targets->data)->target_info; + return; + } + + for (GSList *l =3D targets; l; l =3D l->next) { + const TargetInfo *ti =3D TARGET_INFO_CLASS(l->data)->target_info; + + if (ti->is_default) { + num_default++; + chosen =3D ti; + } + } + + if (num_default !=3D 1) { + error_setg(&error_fatal, num_default =3D=3D 0 ? + "no default target-info is available" : + "more than one default target-info " + "is available"); } =20 - target_info_ptr =3D TARGET_INFO_CLASS(targets->data)->target_info; + target_info_ptr =3D chosen; } --=20 2.52.0.windows.1 From nobody Thu Sep 10 13:25:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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Sun, 23 Aug 2026 08:09:17 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Xianglai Li , Alistair Francis , Chinmay Rath , Sunil V L , qemu-riscv@nongnu.org, Alexander Bulekov , Zhao Liu , Eric Farman , Laurent Vivier , Peter Maydell , Chao Liu , Liu Zhiwei , Palmer Dabbelt , Song Gao <17746591750@163.com>, Harsh Prateek Bora , Glenn Miles , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Daniel Henrique Barboza , Pierrick Bouvier , qemu-s390x@nongnu.org, Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Igor Mammedov , Aleksandar Rikalo , Nicholas Piggin , Cornelia Huck , Richard Henderson , Ilya Leoshkevich , Fabiano Rosas , Aurelien Jarno , Paolo Bonzini , Ani Sinha , Bibo Mao , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Matthew Rosato , Weiwei Li , Darren Kenny Subject: [PATCH 10/12] target-info: add -target and program-name selection Date: Sun, 23 Aug 2026 23:07:28 +0800 Message-ID: <20260823150731.896-11-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260823150731.896-1-luoyonggang@gmail.com> References: <20260823150731.896-1-luoyonggang@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=luoyonggang@gmail.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787497903658158500 Content-Type: text/plain; charset="utf-8" - Parse -target before TargetInfo is fixed; CLI overrides the program basename. - Tokens are target_name or target_name-be / -le; -target help lists registered names in sorted order. - When -target is omitted, infer the token from g_get_prgname(): strip .exe, take the longest dash-separated registered suffix, and retry without a trailing w for Windows GUI binaries. - A basename that matches no registered token falls through to the unique default. Combined binaries with no suffix require -target when more than one default TargetInfo is registered. Signed-off-by: Yonggang Luo --- include/qemu/target-info-qom.h | 10 +- qemu-options.hx | 13 +++ system/vl.c | 28 ++++-- target-info-qom.c | 167 ++++++++++++++++++++++++++++++--- tests/qtest/fuzz/fuzz.c | 2 +- 5 files changed, 197 insertions(+), 23 deletions(-) diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h index 842cf241e0a..3b59cf82d65 100644 --- a/include/qemu/target-info-qom.h +++ b/include/qemu/target-info-qom.h @@ -40,7 +40,15 @@ typedef struct TargetInfoQomClass { =20 OBJECT_DECLARE_TYPE(TargetInfoQom, TargetInfoQomClass, TARGET_INFO) =20 -void target_info_qom_set_target(void); +/** + * target_info_qom_set_target: + * @name: -target token, or NULL/%empty to infer from the program + * basename or the unique default + * + * Tokens are target_name (arch default endian) or target_name-be / + * target_name-le. -target overrides the program basename. + */ +void target_info_qom_set_target(const char *name); =20 /** * get_machine_types_available: diff --git a/qemu-options.hx b/qemu-options.hx index 34970fffc94..638b531aa49 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -223,6 +223,19 @@ SRST as -machine. ERST =20 +DEF("target", HAS_ARG, QEMU_OPTION_target, + "-target name select target ('-target help' for list)\n", QEMU_ARCH= _ALL) +SRST +``-target name`` + Select the emulation target (``-target help`` for the list). The + default endian is the architecture default (``riscv64`` is little + endian). The other endian uses a ``-be`` or ``-le`` suffix + (``riscv64-be``, ``ppc64-le``). If omitted, a matching suffix of + the program basename is used (``qemu-system-riscv64-be``, and + ``qemu-system-aarch64w.exe`` on Windows). ``-target`` overrides + the program name. +ERST + DEF("cpu", HAS_ARG, QEMU_OPTION_cpu, "-cpu cpu select CPU ('-cpu help' for list)\n", QEMU_ARCH_ALL) SRST diff --git a/system/vl.c b/system/vl.c index 83b9425de9b..405f434e036 100644 --- a/system/vl.c +++ b/system/vl.c @@ -166,6 +166,7 @@ typedef struct DeviceOption { QTAILQ_ENTRY(DeviceOption) next; } DeviceOption; =20 +static const char *target_option; static const char *cpu_option; static const char *mem_path; static const char *incoming; @@ -2899,19 +2900,12 @@ void qemu_init(int argc, char **argv) =20 os_setup_limits(); =20 - module_call_init(MODULE_INIT_TARGET_INFO); - target_info_qom_set_target(); - - module_init_info(qemu_modinfo); - module_allow_arch(target_name()); - - qemu_init_subsystems(); - - /* first pass of option parsing */ + /* + * First pass: options needed before TargetInfo is fixed. + */ optind =3D 1; while (optind < argc) { if (argv[optind][0] !=3D '-') { - /* disk image */ optind++; } else { const QEMUOption *popt; @@ -2921,10 +2915,21 @@ void qemu_init(int argc, char **argv) case QEMU_OPTION_nouserconfig: userconfig =3D false; break; + case QEMU_OPTION_target: + target_option =3D optarg; + break; } } } =20 + module_call_init(MODULE_INIT_TARGET_INFO); + target_info_qom_set_target(target_option); + + module_init_info(qemu_modinfo); + module_allow_arch(target_name()); + + qemu_init_subsystems(); + machine_opts_dict =3D qdict_new(); if (userconfig) { qemu_read_default_config_file(&error_fatal); @@ -3687,6 +3692,9 @@ void qemu_init(int argc, char **argv) case QEMU_OPTION_nouserconfig: /* Nothing to be parsed here. Especially, do not error out= below. */ break; + case QEMU_OPTION_target: + /* Parsed before TargetInfo is selected. */ + break; #if defined(CONFIG_POSIX) && !defined(EMSCRIPTEN) case QEMU_OPTION_daemonize: os_set_daemonize(true); diff --git a/target-info-qom.c b/target-info-qom.c index 2c1c57b05fd..be03573a699 100644 --- a/target-info-qom.c +++ b/target-info-qom.c @@ -7,6 +7,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/help_option.h" #include "qapi/error.h" #include "qom/object.h" #include "qemu/target-info-impl.h" @@ -87,7 +88,139 @@ const TargetInfo *target_info(void) return target_info_ptr; } =20 -void target_info_qom_set_target(void) +static const TargetInfo *target_info_from_class(ObjectClass *oc) +{ + return TARGET_INFO_CLASS(oc)->target_info; +} + +/* Default token is target_name; the other endian is target_name-le or -be= . */ +static char *target_info_option_name(const TargetInfo *ti) +{ + if (ti->is_default) { + return g_strdup(ti->target_name); + } + if (ti->endianness =3D=3D ENDIAN_MODE_BIG) { + return g_strdup_printf("%s-be", ti->target_name); + } + return g_strdup_printf("%s-le", ti->target_name); +} + +static gint target_info_token_name_cmp(gconstpointer a, gconstpointer b, + gpointer data) +{ + const TargetInfo *ta =3D target_info_from_class((ObjectClass *)a); + const TargetInfo *tb =3D target_info_from_class((ObjectClass *)b); + g_autofree char *na =3D target_info_option_name(ta); + g_autofree char *nb =3D target_info_option_name(tb); + + return strcmp(na, nb); +} + +static void G_NORETURN target_info_list_and_exit(GSList *targets) +{ + printf("Supported targets:\n"); + for (GSList *l =3D targets; l; l =3D l->next) { + const TargetInfo *ti =3D target_info_from_class(l->data); + g_autofree char *opt_name =3D target_info_option_name(ti); + + printf(" %s%s\n", opt_name, ti->is_default ? " (default)" : ""); + } + exit(0); +} + +static const TargetInfo *target_info_find_default(GSList *targets, + size_t *num_default) +{ + const TargetInfo *chosen =3D NULL; + + *num_default =3D 0; + for (GSList *l =3D targets; l; l =3D l->next) { + const TargetInfo *ti =3D target_info_from_class(l->data); + + if (ti->is_default) { + (*num_default)++; + chosen =3D ti; + } + } + return chosen; +} + +static const TargetInfo *target_info_find_token(GSList *targets, + const char *token) +{ + for (GSList *l =3D targets; l; l =3D l->next) { + const TargetInfo *ti =3D target_info_from_class(l->data); + g_autofree char *opt_name =3D target_info_option_name(ti); + + if (!strcmp(opt_name, token)) { + return ti; + } + } + return NULL; +} + +static bool target_info_base_match_token(const char *base, const char *tok= en) +{ + size_t nlen =3D strlen(token); + size_t blen; + + if (!base || !token[0] || !g_str_has_suffix(base, token)) { + return false; + } + blen =3D strlen(base); + return blen =3D=3D nlen || base[blen - nlen - 1] =3D=3D '-'; +} + +static const TargetInfo *target_info_find_prgname(GSList *targets, + const char *base) +{ + const TargetInfo *chosen =3D NULL; + size_t best_len =3D 0; + + if (!base || !base[0]) { + return NULL; + } + + for (GSList *l =3D targets; l; l =3D l->next) { + const TargetInfo *ti =3D target_info_from_class(l->data); + g_autofree char *opt_name =3D target_info_option_name(ti); + size_t nlen =3D strlen(opt_name); + + if (nlen > best_len && + target_info_base_match_token(base, opt_name)) { + chosen =3D ti; + best_len =3D nlen; + } + } + return chosen; +} + +static const TargetInfo *target_info_from_prgname(GSList *targets) +{ + const char *prg =3D g_get_prgname(); + g_autofree char *base =3D NULL; + char *dot; + const TargetInfo *chosen; + + if (!prg || !prg[0]) { + return NULL; + } + + base =3D g_path_get_basename(prg); + dot =3D strrchr(base, '.'); + if (dot && g_ascii_strcasecmp(dot, ".exe") =3D=3D 0) { + *dot =3D '\0'; + } + + chosen =3D target_info_find_prgname(targets, base); + if (!chosen && strlen(base) > 1 && g_str_has_suffix(base, "w")) { + base[strlen(base) - 1] =3D '\0'; + chosen =3D target_info_find_prgname(targets, base); + } + return chosen; +} + +void target_info_qom_set_target(const char *name) { g_autoptr(GSList) targets =3D object_class_get_list(TYPE_TARGET_INFO, = false); const TargetInfo *chosen =3D NULL; @@ -98,25 +231,37 @@ void target_info_qom_set_target(void) error_setg(&error_fatal, "no target-info is available"); } =20 - if (num_found =3D=3D 1) { - target_info_ptr =3D TARGET_INFO_CLASS(targets->data)->target_info; + if (name && is_help_option(name)) { + targets =3D g_slist_sort_with_data(targets, target_info_token_name= _cmp, + NULL); + target_info_list_and_exit(targets); + } + + if (name && name[0]) { + chosen =3D target_info_find_token(targets, name); + if (!chosen) { + error_setg(&error_fatal, "unknown target '%s'", name); + } + target_info_ptr =3D chosen; return; } =20 - for (GSList *l =3D targets; l; l =3D l->next) { - const TargetInfo *ti =3D TARGET_INFO_CLASS(l->data)->target_info; + chosen =3D target_info_from_prgname(targets); + if (chosen) { + target_info_ptr =3D chosen; + return; + } =20 - if (ti->is_default) { - num_default++; - chosen =3D ti; - } + if (num_found =3D=3D 1) { + target_info_ptr =3D target_info_from_class(targets->data); + return; } =20 + chosen =3D target_info_find_default(targets, &num_default); if (num_default !=3D 1) { error_setg(&error_fatal, num_default =3D=3D 0 ? "no default target-info is available" : - "more than one default target-info " - "is available"); + "multiple default targets; use -target"); } =20 target_info_ptr =3D chosen; diff --git a/tests/qtest/fuzz/fuzz.c b/tests/qtest/fuzz/fuzz.c index a3a131c80f8..489c7138bb9 100644 --- a/tests/qtest/fuzz/fuzz.c +++ b/tests/qtest/fuzz/fuzz.c @@ -174,7 +174,7 @@ int LLVMFuzzerInitialize(int *argc, char ***argv, char = ***envp) /* Initialize qgraph and modules */ qos_graph_init(); module_call_init(MODULE_INIT_TARGET_INFO); - target_info_qom_set_target(); + target_info_qom_set_target(NULL); module_call_init(MODULE_INIT_FUZZ_TARGET); module_call_init(MODULE_INIT_QOM); module_call_init(MODULE_INIT_LIBQOS); --=20 2.52.0.windows.1 From nobody Thu Sep 10 13:25:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Sun, 23 Aug 2026 08:09:26 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Xianglai Li , Alistair Francis , Chinmay Rath , Sunil V L , qemu-riscv@nongnu.org, Alexander Bulekov , Zhao Liu , Eric Farman , Laurent Vivier , Peter Maydell , Chao Liu , Liu Zhiwei , Palmer Dabbelt , Song Gao <17746591750@163.com>, Harsh Prateek Bora , Glenn Miles , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Daniel Henrique Barboza , Pierrick Bouvier , qemu-s390x@nongnu.org, Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Igor Mammedov , Aleksandar Rikalo , Nicholas Piggin , Cornelia Huck , Richard Henderson , Ilya Leoshkevich , Fabiano Rosas , Aurelien Jarno , Paolo Bonzini , Ani Sinha , Bibo Mao , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Matthew Rosato , Weiwei Li , Darren Kenny Subject: [PATCH 11/12] target-info: dispatch CPU QMP, dump, and Angel semihosting Date: Sun, 23 Aug 2026 23:07:29 +0800 Message-ID: <20260823150731.896-12-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260823150731.896-1-luoyonggang@gmail.com> References: <20260823150731.896-1-luoyonggang@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=luoyonggang@gmail.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787497855718158500 Content-Type: text/plain; charset="utf-8" - Combined binaries cannot keep one global C symbol per arch for query-cpu-definitions, dump notes, or Angel semihosting. Put those handlers on a process-wide TargetCpuOps table and fill one member at a time. - TARGET_INFO_CPU_OP is type_init (MODULE_INIT_QOM). That runs after target_info_qom_set_target(), so ELF constructors only queue the callback. target_info_register_cpu_op() stores the impl only when cpu_type matches the selected TargetInfo; a duplicate slot is reported and ignored. A NULL member means this target has no handler, not "too early". - Keep the table in target-info.c (common_ss) and filter with target_info()->cpu_type so user-mode can resolve TARGET_INFO_CPU_OP. Take the address of the impl so the same macro stores both function pointers and ops tables. - QMP query-cpu-definitions and query-cpu-model-expansion dispatch from hw/core/machine-qmp-cmds.c. Dump cpu_get_dump_info and cpu_get_note_size dispatch from hw/core/cpu-system.c. Arch handlers are static with an arch prefix (s390_query_*, arm_get_dump_info, ...). ppc and mips drop expansion stubs; the dispatcher errors instead. - Angel semihosting uses CPUSemihostingOps on TargetCpuOps.semihosting. ARM and RISC-V keep a static ops table in common-semi-target.c and register it with TARGET_INFO_CPU_OP. Wrappers in common-semi.h call target_info_cpu_ops()->semihosting. Always compile those files so both tables exist in a combined link. - Drop stubs/qmp-cpu.c and stubs/dump.c: every system binary has the wrappers, and tools do not implement these commands. Keep stubs/qmp-cpu-s390x.c for comparison/baseline. Signed-off-by: Yonggang Luo --- MAINTAINERS | 1 - hw/core/cpu-system.c | 23 +++++++++++ hw/core/machine-qmp-cmds.c | 26 +++++++++++++ include/qemu/target-info-qom.h | 41 ++++++++++++++++++++ include/semihosting/common-semi.h | 56 ++++++++++++++++++++++++--- stubs/dump.c | 27 ------------- stubs/meson.build | 2 - stubs/qmp-cpu.c | 21 ---------- target-info.c | 32 +++++++++++++++ target/arm/arch_dump.c | 8 +++- target/arm/arm-qmp-cmds.c | 15 +++++-- target/arm/common-semi-target.c | 23 ++++++++--- target/arm/meson.build | 7 +--- target/i386/arch_dump.c | 8 +++- target/i386/cpu-system.c | 12 ++++-- target/i386/cpu.c | 6 ++- target/loongarch/arch_dump.c | 8 +++- target/loongarch/loongarch-qmp-cmds.c | 15 +++++-- target/mips/system/mips-qmp-cmds.c | 15 +++---- target/ppc/arch_dump.c | 8 +++- target/ppc/ppc-qmp-cmds.c | 15 +++---- target/riscv/arch_dump.c | 8 +++- target/riscv/common-semi-target.c | 25 ++++++++---- target/riscv/meson.build | 4 +- target/riscv/riscv-qmp-cmds.c | 15 +++++-- target/s390x/arch_dump.c | 8 +++- target/s390x/cpu_models_system.c | 15 +++++-- 27 files changed, 313 insertions(+), 131 deletions(-) delete mode 100644 stubs/dump.c delete mode 100644 stubs/qmp-cpu.c diff --git a/MAINTAINERS b/MAINTAINERS index 902db77218e..08e84e4ac6d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3348,7 +3348,6 @@ F: include/system/dump-arch.h F: include/system/dump.h F: qapi/dump.json F: scripts/dump-guest-memory.py -F: stubs/dump.c F: docs/specs/vmcoreinfo.rst F: tests/qtest/vmcoreinfo-test.c F: tests/qtest/dump-test.c diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 14eb4ed87f8..6dfbbac7f24 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -24,7 +24,9 @@ #include "exec/cputlb.h" #include "exec/target_page.h" #include "system/memory.h" +#include "system/dump-arch.h" #include "qemu/target-info.h" +#include "qemu/target-info-qom.h" #include "hw/core/qdev.h" #include "hw/core/qdev-properties.h" #include "hw/core/sysemu-cpu-ops.h" @@ -127,6 +129,27 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUS= tate *cpu, return (*cpu->cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque); } =20 +int cpu_get_dump_info(ArchDumpInfo *info, + const struct GuestPhysBlockList *guest_phys_blocks) +{ + const TargetCpuOps *ops =3D target_info_cpu_ops(); + + if (!ops->get_dump_info) { + return -1; + } + return ops->get_dump_info(info, guest_phys_blocks); +} + +ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +{ + const TargetCpuOps *ops =3D target_info_cpu_ops(); + + if (!ops->get_note_size) { + return -1; + } + return ops->get_note_size(class, machine, nr_cpus); +} + bool cpu_internal_is_big_endian(CPUState *cpu) { if (cpu->cc->sysemu_ops->internal_is_big_endian) { diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index e6e6ecc31e3..f8297203848 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -449,3 +449,29 @@ void qmp_dump_skeys(const char *filename, Error **errp) } DUMP_SKEYS_INTERFACE_CLASS(oc)->qmp_dump_skeys(filename, errp); } + +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +{ + const TargetCpuOps *ops =3D target_info_cpu_ops(); + + if (!ops->query_cpu_definitions) { + error_setg(errp, + "CPU model definitions are not supported on this target= "); + return NULL; + } + return ops->query_cpu_definitions(errp); +} + +CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType= type, + CpuModelInfo *model, + Error **errp) +{ + const TargetCpuOps *ops =3D target_info_cpu_ops(); + + if (!ops->query_cpu_model_expansion) { + error_setg(errp, + "CPU model expansion is not supported on this target"); + return NULL; + } + return ops->query_cpu_model_expansion(type, model, errp); +} diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h index 3b59cf82d65..0f0f49faaa8 100644 --- a/include/qemu/target-info-qom.h +++ b/include/qemu/target-info-qom.h @@ -10,8 +10,12 @@ #define QEMU_TARGET_INFO_QOM_H =20 #include "qemu/target-info-impl.h" +#include "qapi/error.h" +#include "qemu/compiler.h" #include "qom/object.h" =20 +#include + #define TYPE_TARGET_INFO "target-info" =20 #define TYPE_TARGET_SPECIFIC "target-specific" @@ -40,6 +44,43 @@ typedef struct TargetInfoQomClass { =20 OBJECT_DECLARE_TYPE(TargetInfoQom, TargetInfoQomClass, TARGET_INFO) =20 +typedef struct ArchDumpInfo ArchDumpInfo; +struct GuestPhysBlockList; +typedef struct CPUSemihostingOps CPUSemihostingOps; + +typedef struct TargetCpuOps { + CpuDefinitionInfoList *(*query_cpu_definitions)(Error **errp); + CpuModelExpansionInfo *(*query_cpu_model_expansion)( + CpuModelExpansionType type, CpuModelInfo *model, Error **errp); + int (*get_dump_info)(ArchDumpInfo *info, + const struct GuestPhysBlockList *guest_phys_block= s); + ssize_t (*get_note_size)(int class, int machine, int nr_cpus); + const CPUSemihostingOps *semihosting; +} TargetCpuOps; + +/** + * target_info_register_cpu_op: + * @cpu_type: CPU_RESOLVING_TYPE of the registering architecture + * @offset: offsetof(TargetCpuOps, member) for the slot being filled + * @impl: handler or ops table stored at that offset + * + * Combined binaries merge one member at a time so QMP, dump, and + * semihosting (or split QMP files) can register independently. + * MODULE_INIT_QOM runs after target_info_qom_set_target(), so only + * the selected cpu_type is stored. + */ +void target_info_register_cpu_op(const char *cpu_type, size_t offset, + void *impl); +const TargetCpuOps *target_info_cpu_ops(void); + +#define TARGET_INFO_CPU_OP(cpu_type, member, impl) = \ +static void glue(target_info_cpu_op_, impl)(void) = \ +{ = \ + target_info_register_cpu_op((cpu_type), offsetof(TargetCpuOps, member)= , \ + (void *)&(impl)); = \ +} = \ +type_init(glue(target_info_cpu_op_, impl)) + /** * target_info_qom_set_target: * @name: -target token, or NULL/%empty to infer from the program diff --git a/include/semihosting/common-semi.h b/include/semihosting/common= -semi.h index aa511a46f42..f86a855a3dd 100644 --- a/include/semihosting/common-semi.h +++ b/include/semihosting/common-semi.h @@ -34,12 +34,56 @@ #ifndef COMMON_SEMI_H #define COMMON_SEMI_H =20 +#include "exec/cpu-common.h" +#include "qemu/target-info-qom.h" + +typedef struct CPUSemihostingOps { + uint64_t (*arg)(CPUState *cs, int argno); + void (*set_ret)(CPUState *cs, uint64_t ret); + bool (*is_64bit)(CPUArchState *env); + bool (*sys_exit_is_extended)(CPUState *cs); + uint64_t (*stack_bottom)(CPUState *cs); + bool (*has_synccache)(CPUArchState *env); +} CPUSemihostingOps; + void do_common_semihosting(CPUState *cs); -uint64_t common_semi_arg(CPUState *cs, int argno); -void common_semi_set_ret(CPUState *cs, uint64_t ret); -bool is_64bit_semihosting(CPUArchState *env); -bool common_semi_sys_exit_is_extended(CPUState *cs); -uint64_t common_semi_stack_bottom(CPUState *cs); -bool common_semi_has_synccache(CPUArchState *env); + +static inline const CPUSemihostingOps *cpu_semihosting_ops(void) +{ + const CPUSemihostingOps *ops =3D target_info_cpu_ops()->semihosting; + + g_assert(ops); + return ops; +} + +static inline uint64_t common_semi_arg(CPUState *cs, int argno) +{ + return cpu_semihosting_ops()->arg(cs, argno); +} + +static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) +{ + cpu_semihosting_ops()->set_ret(cs, ret); +} + +static inline bool is_64bit_semihosting(CPUArchState *env) +{ + return cpu_semihosting_ops()->is_64bit(env); +} + +static inline bool common_semi_sys_exit_is_extended(CPUState *cs) +{ + return cpu_semihosting_ops()->sys_exit_is_extended(cs); +} + +static inline uint64_t common_semi_stack_bottom(CPUState *cs) +{ + return cpu_semihosting_ops()->stack_bottom(cs); +} + +static inline bool common_semi_has_synccache(CPUArchState *env) +{ + return cpu_semihosting_ops()->has_synccache(env); +} =20 #endif /* COMMON_SEMI_H */ diff --git a/stubs/dump.c b/stubs/dump.c deleted file mode 100644 index df7897b72b1..00000000000 --- a/stubs/dump.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * QEMU dump - * - * Copyright Fujitsu, Corp. 2011, 2012 - * - * Authors: - * Wen Congyang - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ - -#include "qemu/osdep.h" -#include "system/dump-arch.h" - -int cpu_get_dump_info(ArchDumpInfo *info, - const struct GuestPhysBlockList *guest_phys_blocks) -{ - return -1; -} - -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) -{ - return -1; -} - diff --git a/stubs/meson.build b/stubs/meson.build index 3b2f2680b19..94024aef868 100644 --- a/stubs/meson.build +++ b/stubs/meson.build @@ -68,7 +68,6 @@ if have_system # adding more of these. If the symbol is used in specific_ss, # in particular, consider defining a preprocessor macro via # Kconfig or configs/targets/. - stub_ss.add(files('dump.c')) stub_ss.add(files('cmos.c')) stub_ss.add(files('fw_cfg.c')) if igvm.found() @@ -82,7 +81,6 @@ if have_system stub_ss.add(files('qmp-i386-sev.c')) stub_ss.add(files('qmp-i386-sgx.c')) stub_ss.add(files('qmp-i386-xen.c')) - stub_ss.add(files('qmp-cpu.c')) stub_ss.add(files('qmp-cpu-s390x.c')) stub_ss.add(files('qmp-cpu-s390x-kvm.c')) stub_ss.add(files('hmp-cmd-info_mem.c')) diff --git a/stubs/qmp-cpu.c b/stubs/qmp-cpu.c deleted file mode 100644 index a8c7ee89b9d..00000000000 --- a/stubs/qmp-cpu.c +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "qapi/qapi-commands-machine.h" - -CpuModelExpansionInfo * -qmp_query_cpu_model_expansion(CpuModelExpansionType type, - CpuModelInfo *model, - Error **errp) -{ - error_setg(errp, "CPU model expansion is not supported on this target"= ); - return NULL; -} - -CpuDefinitionInfoList * -qmp_query_cpu_definitions(Error **errp) -{ - error_setg(errp, "CPU model definitions are not supported on this targ= et"); - return NULL; -} diff --git a/target-info.c b/target-info.c index ce7f9797dce..aa4be08bb94 100644 --- a/target-info.c +++ b/target-info.c @@ -7,9 +7,11 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qemu/target-info.h" #include "qemu/target-info-qapi.h" #include "qemu/target-info-impl.h" +#include "qemu/target-info-qom.h" #include "qapi/error.h" =20 const char *target_name(void) @@ -124,3 +126,33 @@ bool target_config_xen(void) { return target_info()->config_xen; } + +static TargetCpuOps target_cpu_ops; + +void target_info_register_cpu_op(const char *cpu_type, size_t offset, + void *impl) +{ + const TargetInfo *ti =3D target_info(); + void **slot; + + g_assert(ti); + g_assert(offset + sizeof(void *) <=3D sizeof(TargetCpuOps)); + g_assert((offset % sizeof(void *)) =3D=3D 0); + + if (strcmp(cpu_type, ti->cpu_type)) { + return; + } + + slot =3D (void **)((char *)&target_cpu_ops + offset); + if (*slot) { + error_report("TargetCpuOps already registered for type '%s' (offse= t %zu)", + cpu_type, offset); + return; + } + *slot =3D impl; +} + +const TargetCpuOps *target_info_cpu_ops(void) +{ + return &target_cpu_ops; +} diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 1dd79849c13..e072516bdac 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -24,6 +24,7 @@ #include "system/dump.h" #include "cpu-features.h" #include "internals.h" +#include "qemu/target-info-qom.h" =20 /* struct user_pt_regs from arch/arm64/include/uapi/asm/ptrace.h */ struct aarch64_user_regs { @@ -385,7 +386,7 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, C= PUState *cs, return 0; } =20 -int cpu_get_dump_info(ArchDumpInfo *info, +static int arm_get_dump_info(ArchDumpInfo *info, const GuestPhysBlockList *guest_phys_blocks) { ARMCPU *cpu; @@ -439,7 +440,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, return 0; } =20 -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +static ssize_t arm_get_note_size(int class, int machine, int nr_cpus) { ARMCPU *cpu =3D ARM_CPU(first_cpu); size_t note_size; @@ -459,3 +460,6 @@ ssize_t cpu_get_note_size(int class, int machine, int n= r_cpus) =20 return note_size * nr_cpus; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_dump_info, arm_get_dump_info); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_note_size, arm_get_note_size); diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index 83ec95c290f..c85bde5d79d 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -32,6 +32,7 @@ #include "qobject/qdict.h" #include "qom/qom-qobject.h" #include "cpu.h" +#include "qemu/target-info-qom.h" =20 static GICCapability *gic_cap_new(int version) { @@ -79,9 +80,10 @@ static const char *cpu_model_advertised_features[] =3D { NULL }; =20 -CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType= type, - CpuModelInfo *model, - Error **errp) +static CpuModelExpansionInfo * +arm_query_cpu_model_expansion(CpuModelExpansionType type, + CpuModelInfo *model, + Error **errp) { CpuModelExpansionInfo *expansion_info; const QDict *qdict_in; @@ -216,7 +218,7 @@ static void arm_cpu_add_definition(gpointer data, gpoin= ter user_data) QAPI_LIST_PREPEND(*cpu_list, info); } =20 -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *arm_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list =3D NULL; GSList *list; @@ -227,3 +229,8 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error = **errp) =20 return cpu_list; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_definitions, + arm_query_cpu_definitions); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_model_expansion, + arm_query_cpu_model_expansion); diff --git a/target/arm/common-semi-target.c b/target/arm/common-semi-targe= t.c index 2b77ce9c17b..eccd3735df8 100644 --- a/target/arm/common-semi-target.c +++ b/target/arm/common-semi-target.c @@ -12,7 +12,7 @@ #include "semihosting/common-semi.h" #include "target/arm/cpu-qom.h" =20 -uint64_t common_semi_arg(CPUState *cs, int argno) +static uint64_t arm_common_semi_arg(CPUState *cs, int argno) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -23,7 +23,7 @@ uint64_t common_semi_arg(CPUState *cs, int argno) } } =20 -void common_semi_set_ret(CPUState *cs, uint64_t ret) +static void arm_common_semi_set_ret(CPUState *cs, uint64_t ret) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -34,25 +34,36 @@ void common_semi_set_ret(CPUState *cs, uint64_t ret) } } =20 -bool common_semi_sys_exit_is_extended(CPUState *cs) +static bool arm_common_semi_sys_exit_is_extended(CPUState *cs) { return is_a64(cpu_env(cs)); } =20 -bool is_64bit_semihosting(CPUArchState *env) +static bool arm_is_64bit_semihosting(CPUArchState *env) { return is_a64(env); } =20 -uint64_t common_semi_stack_bottom(CPUState *cs) +static uint64_t arm_common_semi_stack_bottom(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; return is_a64(env) ? env->xregs[31] : env->regs[13]; } =20 -bool common_semi_has_synccache(CPUArchState *env) +static bool arm_common_semi_has_synccache(CPUArchState *env) { /* Ok for A64, invalid for A32/T32 */ return is_a64(env); } + +static const CPUSemihostingOps arm_semihosting_ops =3D { + .arg =3D arm_common_semi_arg, + .set_ret =3D arm_common_semi_set_ret, + .is_64bit =3D arm_is_64bit_semihosting, + .sys_exit_is_extended =3D arm_common_semi_sys_exit_is_extended, + .stack_bottom =3D arm_common_semi_stack_bottom, + .has_synccache =3D arm_common_semi_has_synccache, +}; + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, semihosting, arm_semihosting_ops); diff --git a/target/arm/meson.build b/target/arm/meson.build index 0369f96b4cc..dfcec55bd97 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -44,13 +44,10 @@ arm_stubs_ss.add(files( arm_user_ss.add(files( 'el2-stubs.c', 'cpregs-omap-stub.c', + 'common-semi-target.c', )) -arm_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', - if_true: files('common-semi-target.c')) =20 -arm_common_system_ss.add(files('cpu.c')) -arm_common_system_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', - if_true: files('common-semi-target.c')) +arm_common_system_ss.add(files('cpu.c', 'common-semi-target.c')) arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', diff --git a/target/i386/arch_dump.c b/target/i386/arch_dump.c index 16e47c4747d..c060b2b4ccb 100644 --- a/target/i386/arch_dump.c +++ b/target/i386/arch_dump.c @@ -16,6 +16,7 @@ #include "system/dump.h" #include "elf.h" #include "system/memory_mapping.h" +#include "qemu/target-info-qom.h" =20 #define ELF_NOTE_SIZE(hdr_size, name_size, desc_size) \ ((DIV_ROUND_UP((hdr_size), 4) \ @@ -394,7 +395,7 @@ int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction = f, CPUState *cs, return cpu_write_qemu_note(f, &cpu->env, s, 0); } =20 -int cpu_get_dump_info(ArchDumpInfo *info, +static int x86_get_dump_info(ArchDumpInfo *info, const GuestPhysBlockList *guest_phys_blocks) { bool lma =3D false; @@ -429,7 +430,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, return 0; } =20 -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +static ssize_t x86_get_note_size(int class, int machine, int nr_cpus) { int name_size =3D 5; /* "CORE" or "QEMU" */ size_t elf_note_size =3D 0; @@ -459,3 +460,6 @@ ssize_t cpu_get_note_size(int class, int machine, int n= r_cpus) =20 return (elf_note_size + qemu_note_size) * nr_cpus; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_dump_info, x86_get_dump_info); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_note_size, x86_get_note_size); diff --git a/target/i386/cpu-system.c b/target/i386/cpu-system.c index c8bbf0cbafd..d2babd1ba09 100644 --- a/target/i386/cpu-system.c +++ b/target/i386/cpu-system.c @@ -29,6 +29,7 @@ #include "qapi/qapi-commands-machine.h" =20 #include "cpu-internal.h" +#include "qemu/target-info-qom.h" =20 /* Return a QDict containing keys for all properties that can be included * in static expansion of CPU models. All properties set by x86_cpu_load_m= odel() @@ -188,10 +189,10 @@ out: return xc; } =20 -CpuModelExpansionInfo * -qmp_query_cpu_model_expansion(CpuModelExpansionType type, - CpuModelInfo *model, - Error **errp) +static CpuModelExpansionInfo * +x86_query_cpu_model_expansion(CpuModelExpansionType type, + CpuModelInfo *model, + Error **errp) { X86CPU *xc =3D NULL; Error *err =3D NULL; @@ -241,6 +242,9 @@ out: return ret; } =20 +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_model_expansion, + x86_query_cpu_model_expansion); + void cpu_clear_apic_feature(CPUX86State *env) { env->features[FEAT_1_EDX] &=3D ~CPUID_APIC; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5805d33ab92..4e31b8a2a60 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -48,6 +48,7 @@ #include "system/address-spaces.h" #include "hw/core/boards.h" #include "hw/i386/sgx-epc.h" +#include "qemu/target-info-qom.h" #endif #include "system/qtest.h" #include "tcg/tcg-cpu.h" @@ -8191,7 +8192,7 @@ static void x86_cpu_definition_entry(gpointer data, g= pointer user_data) QAPI_LIST_PREPEND(*cpu_list, info); } =20 -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *x86_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list =3D NULL; GSList *list =3D get_sorted_cpu_model_list(); @@ -8200,6 +8201,9 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Erro= r **errp) return cpu_list; } =20 +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_definitions, + x86_query_cpu_definitions); + #endif /* !CONFIG_USER_ONLY */ =20 static uint8_t x86_cpu_get_host_avx10_version(void) diff --git a/target/loongarch/arch_dump.c b/target/loongarch/arch_dump.c index 9d84faef969..af4ab5df5b5 100644 --- a/target/loongarch/arch_dump.c +++ b/target/loongarch/arch_dump.c @@ -22,6 +22,7 @@ #include "elf.h" #include "system/dump.h" #include "internals.h" +#include "qemu/target-info-qom.h" =20 /* struct user_pt_regs from arch/loongarch/include/uapi/asm/ptrace.h */ struct loongarch_user_regs { @@ -142,7 +143,7 @@ int loongarch_cpu_write_elf64_note(WriteCoreDumpFunctio= n f, CPUState *cs, return ret; } =20 -int cpu_get_dump_info(ArchDumpInfo *info, +static int loongarch_get_dump_info(ArchDumpInfo *info, const GuestPhysBlockList *guest_phys_blocks) { info->d_machine =3D EM_LOONGARCH; @@ -152,7 +153,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, return 0; } =20 -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +static ssize_t loongarch_get_note_size(int class, int machine, int nr_cpus) { size_t note_size =3D 0; =20 @@ -162,3 +163,6 @@ ssize_t cpu_get_note_size(int class, int machine, int n= r_cpus) =20 return note_size * nr_cpus; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_dump_info, loongarch_get_dump_i= nfo); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_note_size, loongarch_get_note_s= ize); diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loong= arch-qmp-cmds.c index f053f22bb8c..848ad640aee 100644 --- a/target/loongarch/loongarch-qmp-cmds.c +++ b/target/loongarch/loongarch-qmp-cmds.c @@ -14,6 +14,7 @@ #include "qobject/qdict.h" #include "qapi/qobject-input-visitor.h" #include "qom/qom-qobject.h" +#include "qemu/target-info-qom.h" =20 static void loongarch_cpu_add_definition(gpointer data, gpointer user_data) { @@ -28,7 +29,7 @@ static void loongarch_cpu_add_definition(gpointer data, g= pointer user_data) QAPI_LIST_PREPEND(*cpu_list, info); } =20 -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *loongarch_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list =3D NULL; GSList *list; @@ -45,9 +46,10 @@ static const char *cpu_model_advertised_features[] =3D { "ptw", NULL }; =20 -CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType= type, - CpuModelInfo *model, - Error **errp) +static CpuModelExpansionInfo * +loongarch_query_cpu_model_expansion(CpuModelExpansionType type, + CpuModelInfo *model, + Error **errp) { Visitor *visitor; CpuModelExpansionInfo *expansion_info; @@ -133,3 +135,8 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(Cp= uModelExpansionType type, =20 return expansion_info; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_definitions, + loongarch_query_cpu_definitions); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_model_expansion, + loongarch_query_cpu_model_expansion); diff --git a/target/mips/system/mips-qmp-cmds.c b/target/mips/system/mips-q= mp-cmds.c index b6a2874f2dd..ff78487423b 100644 --- a/target/mips/system/mips-qmp-cmds.c +++ b/target/mips/system/mips-qmp-cmds.c @@ -11,15 +11,7 @@ #include "qapi/error.h" #include "qapi/qapi-commands-machine.h" #include "cpu.h" - -CpuModelExpansionInfo * -qmp_query_cpu_model_expansion(CpuModelExpansionType type, - CpuModelInfo *model, - Error **errp) -{ - error_setg(errp, "CPU model expansion is not supported on this target"= ); - return NULL; -} +#include "qemu/target-info-qom.h" =20 static void mips_cpu_add_definition(gpointer data, gpointer user_data) { @@ -36,7 +28,7 @@ static void mips_cpu_add_definition(gpointer data, gpoint= er user_data) QAPI_LIST_PREPEND(*cpu_list, info); } =20 -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *mips_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list =3D NULL; GSList *list; @@ -47,3 +39,6 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **= errp) =20 return cpu_list; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_definitions, + mips_query_cpu_definitions); diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c index 80ac6c3e320..07f0c75c45e 100644 --- a/target/ppc/arch_dump.c +++ b/target/ppc/arch_dump.c @@ -17,6 +17,7 @@ #include "elf.h" #include "system/dump.h" #include "system/kvm.h" +#include "qemu/target-info-qom.h" =20 #ifdef TARGET_PPC64 #define ELFCLASS ELFCLASS64 @@ -229,7 +230,7 @@ static const struct NoteFuncDescStruct { =20 typedef struct NoteFuncDescStruct NoteFuncDesc; =20 -int cpu_get_dump_info(ArchDumpInfo *info, +static int ppc_get_dump_info(ArchDumpInfo *info, const struct GuestPhysBlockList *guest_phys_blocks) { PowerPCCPU *cpu; @@ -257,7 +258,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, return 0; } =20 -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +static ssize_t ppc_get_note_size(int class, int machine, int nr_cpus) { int name_size =3D 8; /* "CORE" or "QEMU" rounded */ size_t elf_note_size =3D 0; @@ -313,3 +314,6 @@ int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f,= CPUState *cs, PowerPCCPU *cpu =3D POWERPC_CPU(cs); return ppc_write_all_elf_notes("CORE", f, cpu, cpuid, s); } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_dump_info, ppc_get_dump_info); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_note_size, ppc_get_note_size); diff --git a/target/ppc/ppc-qmp-cmds.c b/target/ppc/ppc-qmp-cmds.c index 96228919966..70fca0170b1 100644 --- a/target/ppc/ppc-qmp-cmds.c +++ b/target/ppc/ppc-qmp-cmds.c @@ -29,15 +29,7 @@ #include "qapi/qapi-commands-machine.h" #include "cpu-models.h" #include "cpu-qom.h" - -CpuModelExpansionInfo * -qmp_query_cpu_model_expansion(CpuModelExpansionType type, - CpuModelInfo *model, - Error **errp) -{ - error_setg(errp, "CPU model expansion is not supported on this target"= ); - return NULL; -} +#include "qemu/target-info-qom.h" =20 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) { @@ -53,7 +45,7 @@ static void ppc_cpu_defs_entry(gpointer data, gpointer us= er_data) QAPI_LIST_PREPEND(*first, info); } =20 -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *ppc_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list =3D NULL; GSList *list; @@ -82,3 +74,6 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **= errp) =20 return cpu_list; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_definitions, + ppc_query_cpu_definitions); diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c index 12b68799070..7e4b584faa0 100644 --- a/target/riscv/arch_dump.c +++ b/target/riscv/arch_dump.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "elf.h" #include "system/dump.h" +#include "qemu/target-info-qom.h" =20 /* struct user_regs_struct from arch/riscv/include/uapi/asm/ptrace.h */ struct riscv64_user_regs { @@ -161,7 +162,7 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f,= CPUState *cs, return ret; } =20 -int cpu_get_dump_info(ArchDumpInfo *info, +static int riscv_get_dump_info(ArchDumpInfo *info, const GuestPhysBlockList *guest_phys_blocks) { RISCVCPU *cpu; @@ -187,7 +188,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, return 0; } =20 -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +static ssize_t riscv_get_note_size(int class, int machine, int nr_cpus) { size_t note_size; =20 @@ -199,3 +200,6 @@ ssize_t cpu_get_note_size(int class, int machine, int n= r_cpus) =20 return note_size * nr_cpus; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_dump_info, riscv_get_dump_info); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_note_size, riscv_get_note_size); diff --git a/target/riscv/common-semi-target.c b/target/riscv/common-semi-t= arget.c index aeaeb88d536..aed9dfc5b68 100644 --- a/target/riscv/common-semi-target.c +++ b/target/riscv/common-semi-target.c @@ -12,38 +12,49 @@ #include "cpu.h" #include "semihosting/common-semi.h" =20 -uint64_t common_semi_arg(CPUState *cs, int argno) +static uint64_t riscv_common_semi_arg(CPUState *cs, int argno) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; return env->gpr[xA0 + argno]; } =20 -void common_semi_set_ret(CPUState *cs, uint64_t ret) +static void riscv_common_semi_set_ret(CPUState *cs, uint64_t ret) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; env->gpr[xA0] =3D ret; } =20 -bool is_64bit_semihosting(CPUArchState *env) +static bool riscv_is_64bit_semihosting(CPUArchState *env) { return riscv_cpu_mxl(env) !=3D MXL_RV32; } =20 -bool common_semi_sys_exit_is_extended(CPUState *cs) +static bool riscv_common_semi_sys_exit_is_extended(CPUState *cs) { - return is_64bit_semihosting(cpu_env(cs)); + return riscv_is_64bit_semihosting(cpu_env(cs)); } =20 -uint64_t common_semi_stack_bottom(CPUState *cs) +static uint64_t riscv_common_semi_stack_bottom(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; return env->gpr[xSP]; } =20 -bool common_semi_has_synccache(CPUArchState *env) +static bool riscv_common_semi_has_synccache(CPUArchState *env) { return true; } + +static const CPUSemihostingOps riscv_semihosting_ops =3D { + .arg =3D riscv_common_semi_arg, + .set_ret =3D riscv_common_semi_set_ret, + .is_64bit =3D riscv_is_64bit_semihosting, + .sys_exit_is_extended =3D riscv_common_semi_sys_exit_is_extended, + .stack_bottom =3D riscv_common_semi_stack_bottom, + .has_synccache =3D riscv_common_semi_has_synccache, +}; + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, semihosting, riscv_semihosting_ops); diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 42d0f6d538a..5adb6d1c9e7 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -11,12 +11,10 @@ gen =3D [ riscv_ss =3D ss.source_set() riscv_ss.add(gen) =20 -riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', - if_true: files('common-semi-target.c')) - riscv_ss.add(files( 'cpu.c', 'gdbstub.c', + 'common-semi-target.c', )) =20 riscv_system_ss =3D ss.source_set() diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 2647deef916..248e6a0eaf0 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -36,6 +36,7 @@ #include "cpu-qom.h" #include "cpu.h" #include "target/riscv/tcg/csr.h" +#include "qemu/target-info-qom.h" =20 static void riscv_cpu_add_definition(gpointer data, gpointer user_data) { @@ -54,7 +55,7 @@ static void riscv_cpu_add_definition(gpointer data, gpoin= ter user_data) QAPI_LIST_PREPEND(*cpu_list, info); } =20 -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *riscv_query_cpu_definitions(Error **errp) { CpuDefinitionInfoList *cpu_list =3D NULL; GSList *list =3D object_class_get_list(TYPE_RISCV_CPU, false); @@ -154,9 +155,10 @@ err: visit_free(visitor); } =20 -CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType= type, - CpuModelInfo *model, - Error **errp) +static CpuModelExpansionInfo * +riscv_query_cpu_model_expansion(CpuModelExpansionType type, + CpuModelInfo *model, + Error **errp) { CpuModelExpansionInfo *expansion_info; QDict *qdict_out; @@ -225,3 +227,8 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(Cp= uModelExpansionType type, =20 return expansion_info; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_definitions, + riscv_query_cpu_definitions); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_model_expansion, + riscv_query_cpu_model_expansion); diff --git a/target/s390x/arch_dump.c b/target/s390x/arch_dump.c index 2c26e992959..c0334baa72f 100644 --- a/target/s390x/arch_dump.c +++ b/target/s390x/arch_dump.c @@ -18,6 +18,7 @@ #include "elf.h" #include "system/dump.h" #include "kvm/kvm_s390x.h" +#include "qemu/target-info-qom.h" #include "target/s390x/kvm/pv.h" =20 struct S390xUserRegsStruct { @@ -449,7 +450,7 @@ static void arch_cleanup(DumpState *s) } } =20 -int cpu_get_dump_info(ArchDumpInfo *info, +static int s390_get_dump_info(ArchDumpInfo *info, const struct GuestPhysBlockList *guest_phys_blocks) { info->d_machine =3D EM_S390; @@ -469,7 +470,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, return 0; } =20 -ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +static ssize_t s390_get_note_size(int class, int machine, int nr_cpus) { int name_size =3D 8; /* "LINUX" or "CORE" + pad */ size_t elf_note_size =3D 0; @@ -495,3 +496,6 @@ ssize_t cpu_get_note_size(int class, int machine, int n= r_cpus) =20 return (elf_note_size) * nr_cpus; } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_dump_info, s390_get_dump_info); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, get_note_size, s390_get_note_size); diff --git a/target/s390x/cpu_models_system.c b/target/s390x/cpu_models_sys= tem.c index 5b846048675..5470bf55e20 100644 --- a/target/s390x/cpu_models_system.c +++ b/target/s390x/cpu_models_system.c @@ -20,6 +20,7 @@ #include "qapi/qobject-input-visitor.h" #include "qobject/qdict.h" #include "qapi/qapi-commands-machine.h" +#include "qemu/target-info-qom.h" =20 static void list_add_feat(const char *name, void *opaque); =20 @@ -82,7 +83,7 @@ static void create_cpu_model_list(ObjectClass *klass, voi= d *opaque) QAPI_LIST_PREPEND(*cpu_list, info); } =20 -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *s390_query_cpu_definitions(Error **errp) { struct CpuDefinitionInfoListData list_data =3D { .list =3D NULL, @@ -208,9 +209,10 @@ static void cpu_info_from_model(CpuModelInfo *info, co= nst S390CPUModel *model, } } =20 -CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType= type, - CpuModelInfo *model, - Error **errp) +static CpuModelExpansionInfo * +s390_query_cpu_model_expansion(CpuModelExpansionType type, + CpuModelInfo *model, + Error **errp) { Error *err =3D NULL; CpuModelExpansionInfo *expansion_info =3D NULL; @@ -434,3 +436,8 @@ void apply_cpu_model(const S390CPUModel *model, Error *= *errp) applied_model =3D *model; } } + +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_definitions, + s390_query_cpu_definitions); +TARGET_INFO_CPU_OP(CPU_RESOLVING_TYPE, query_cpu_model_expansion, + s390_query_cpu_model_expansion); --=20 2.52.0.windows.1 From nobody Thu Sep 10 13:25:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sun, 23 Aug 2026 08:09:35 -0700 (PDT) From: Yonggang Luo To: qemu-devel@nongnu.org Cc: Xianglai Li , Alistair Francis , Chinmay Rath , Sunil V L , qemu-riscv@nongnu.org, Alexander Bulekov , Zhao Liu , Eric Farman , Laurent Vivier , Peter Maydell , Chao Liu , Liu Zhiwei , Palmer Dabbelt , Song Gao <17746591750@163.com>, Harsh Prateek Bora , Glenn Miles , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Daniel Henrique Barboza , Pierrick Bouvier , qemu-s390x@nongnu.org, Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Igor Mammedov , Aleksandar Rikalo , Nicholas Piggin , Cornelia Huck , Richard Henderson , Ilya Leoshkevich , Fabiano Rosas , Aurelien Jarno , Paolo Bonzini , Ani Sinha , Bibo Mao , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Matthew Rosato , Weiwei Li , Darren Kenny Subject: [PATCH 12/12] meson: link ARM and RISC-V into qemu-system Date: Sun, 23 Aug 2026 23:07:30 +0800 Message-ID: <20260823150731.896-13-luoyonggang@gmail.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260823150731.896-1-luoyonggang@gmail.com> References: <20260823150731.896-1-luoyonggang@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=luoyonggang@gmail.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787497887553158500 Content-Type: text/plain; charset="utf-8" - Build qemu-system (and qemu-systemw on Windows) from aarch64 common/system objects plus RISC-V arch objects taken from the existing riscv64 lib. - Pull 32-bit TargetInfo and 32-only boards from the arm/riscv32 libs so hw/arm and target/riscv are not compiled twice. - Skip linking qemu-system-{arm,aarch64,riscv32,riscv64} and the Windows *w variants; symlink those names to qemu-system so argv[0] still selects TargetInfo. Signed-off-by: Yonggang Luo --- meson.build | 156 +++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 147 insertions(+), 9 deletions(-) diff --git a/meson.build b/meson.build index 449d50f2983..b4f435f6a22 100644 --- a/meson.build +++ b/meson.build @@ -4250,6 +4250,10 @@ endif =20 traceable =3D [] emulators =3D {} +target_softmmu =3D {} +combo_softmmu =3D ['aarch64-softmmu', 'arm-softmmu', 'riscv32-softmmu', 'r= iscv64-softmmu'] +have_qemu_system_combo =3D ('aarch64-softmmu' in target_dirs + and 'riscv64-softmmu' in target_dirs) foreach target : target_dirs config_target =3D config_target_mak[target] target_name =3D config_target['TARGET_NAME'] @@ -4399,20 +4403,37 @@ foreach target : target_dirs c_args: c_args, build_by_default: false) =20 + if target in combo_softmmu + target_softmmu +=3D {target: { + 'lib': lib, + 'arch_srcs': arch_srcs, + 'arch_deps': arch_deps, + 'c_args': c_args, + 'link_args': link_args, + 'target_stubs': target_stubs, + 'main_rs': main_rs, + 'config_target': config_target, + 'target_base_arch': target_base_arch, + }} + endif + if target.endswith('-softmmu') - execs =3D [{ - 'name': 'qemu-system-' + target_name, - 'win_subsystem': 'console', - 'sources': [main_rs, files('system/main.c')], - 'dependencies': [sdl, target_stubs], - }] - if host_os =3D=3D 'windows' and (sdl.found() or gtk.found()) + execs =3D [] + if not (have_qemu_system_combo and target in combo_softmmu) execs +=3D [{ - 'name': 'qemu-system-' + target_name + 'w', - 'win_subsystem': 'windows', + 'name': 'qemu-system-' + target_name, + 'win_subsystem': 'console', 'sources': [main_rs, files('system/main.c')], 'dependencies': [sdl, target_stubs], }] + if host_os =3D=3D 'windows' and (sdl.found() or gtk.found()) + execs +=3D [{ + 'name': 'qemu-system-' + target_name + 'w', + 'win_subsystem': 'windows', + 'sources': [main_rs, files('system/main.c')], + 'dependencies': [sdl, target_stubs], + }] + endif endif if get_option('fuzzing') specific_fuzz =3D specific_fuzz_ss.apply(config_target, strict: fals= e) @@ -4481,6 +4502,123 @@ foreach target : target_dirs endforeach endforeach =20 +# Combined ARM + RISC-V system emulator (32 and 64). +# Common/system objects come from aarch64. RISC-V arch objects come +# from the existing riscv64 lib. 32-bit TargetInfo and 32-only boards +# come from the arm/riscv32 libs. Per-target qemu-system-* names are +# symlinks to qemu-system (argv[0] selects TargetInfo). +if have_qemu_system_combo + a64 =3D target_softmmu['aarch64-softmmu'] + rv =3D target_softmmu['riscv64-softmmu'] + extra_objs =3D [] + target_info_def =3D files('target-info-def.c') + foreach spec : [[common_ss, common_all], [system_ss, libsystem]] + rv_src =3D spec[0].apply(rv['config_target'], strict: false) + a64_src =3D spec[0].apply(a64['config_target'], strict: false) + extra =3D [] + foreach f : rv_src.sources() + if f not in a64_src.sources() and not f.full_path().endswith('_stubs= .c') + extra +=3D f + endif + endforeach + if extra.length() > 0 + extra_objs +=3D spec[1].extract_objects(extra) + endif + endforeach + rv_base =3D rv['target_base_arch'] + if rv_base in target_common_arch_libs + src =3D target_common_arch[rv_base].apply(rv['config_target'], strict:= false) + extra_objs +=3D target_common_arch_libs[rv_base].extract_objects(src.s= ources()) + endif + if rv_base in target_common_system_arch_libs + src =3D target_common_system_arch[rv_base].apply(rv['config_target'], = strict: false) + extra_objs +=3D target_common_system_arch_libs[rv_base].extract_object= s(src.sources()) + endif + foreach pair : [['arm-softmmu', 'aarch64-softmmu'], ['riscv32-softmmu', = 'riscv64-softmmu']] + t32 =3D pair[0] + t64 =3D pair[1] + if t32 in target_softmmu + extra_objs +=3D target_softmmu[t32]['lib'].extract_objects(target_in= fo_def) + base32 =3D target_softmmu[t32]['target_base_arch'] + if base32 in hw_arch + hw32 =3D hw_arch[base32].apply(target_softmmu[t32]['config_target'= ], strict: false) + hw64 =3D hw_arch[base32].apply(target_softmmu[t64]['config_target'= ], strict: false) + extra_hw =3D [] + foreach f : hw32.sources() + if f not in hw64.sources() + extra_hw +=3D f + endif + endforeach + if extra_hw.length() > 0 + extra_objs +=3D target_softmmu[t32]['lib'].extract_objects(extra= _hw) + endif + endif + endif + endforeach + combo_objects =3D extra_objs + combo_objects +=3D a64['lib'].extract_all_objects(recursive: true) + combo_objects +=3D rv['lib'].extract_objects(rv['arch_srcs']) + combo_deps =3D a64['arch_deps'] + rv['arch_deps'] + [sdl, a64['target_st= ubs'], rv['target_stubs']] + if 'arm-softmmu' in target_softmmu + combo_deps +=3D target_softmmu['arm-softmmu']['arch_deps'] + endif + if 'riscv32-softmmu' in target_softmmu + combo_deps +=3D target_softmmu['riscv32-softmmu']['arch_deps'] + endif + combo_execs =3D [{ + 'name': 'qemu-system', + 'win_subsystem': 'console', + }] + if host_os =3D=3D 'windows' and (sdl.found() or gtk.found()) + combo_execs +=3D [{ + 'name': 'qemu-systemw', + 'win_subsystem': 'windows', + }] + endif + combo_exe_suffix =3D host_os =3D=3D 'windows' ? '.exe' : '' + combo_alias_py =3D 'import os, sys; src, dst =3D sys.argv[1:3]; os.path.= exists(dst) and os.remove(dst); os.symlink(os.path.basename(src), dst)' + foreach exe : combo_execs + emulator =3D executable(exe['name'], [a64['main_rs'], files('system/ma= in.c')], + install: true, + c_args: a64['c_args'], + dependencies: combo_deps, + objects: combo_objects, + link_depends: [block_syms, qemu_syms], + link_args: a64['link_args'], + win_subsystem: exe['win_subsystem']) + emulators +=3D {exe['name']: emulator} + traceable +=3D [{ + 'exe': exe['name'], + 'probe-prefix': 'qemu.system.multi', + }] + foreach t : combo_softmmu + if t not in target_softmmu + continue + endif + tname =3D target_softmmu[t]['config_target']['TARGET_NAME'] + if exe['name'] =3D=3D 'qemu-systemw' + alias =3D 'qemu-system-' + tname + 'w' + else + alias =3D 'qemu-system-' + tname + endif + alias_tgt =3D custom_target(alias, + input: emulator, + output: alias + combo_exe_suffix, + command: [python, '-c', combo_alias_py, '@= INPUT@', '@OUTPUT@'], + build_by_default: true, + install: false) + emulators +=3D {alias: alias_tgt} + install_symlink(alias + combo_exe_suffix, + pointing_to: exe['name'] + combo_exe_suffix, + install_dir: get_option('bindir')) + traceable +=3D [{ + 'exe': alias, + 'probe-prefix': 'qemu.system.' + tname, + }] + endforeach + endforeach +endif + # Other build targets =20 if get_option('plugins') --=20 2.52.0.windows.1