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[35.229.176.202]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d676895799sm5892715ad.38.2026.08.22.12.43.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Aug 2026 12:43:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787427816; x=1788032616; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=TH0PJsVypITU/9irrzyoneF3uRtdmouDSRl9TezlEGQ=; b=bHCxZToaooiW8sxefIO2UxULPxJniD//W+VUOs5RCIcfFXq9WO9/Nr6iL7TYVNf+Aq s8fIysm0PfXRWK8DH597r/pFHy88zraRsLYKaEvWrGMmbDOOxRrLgDD4OFy4Y6b047xz y3CXUGfoLlEH7arVVIW9NnoAqXXbYRpTvlFDhAxBTDnyzybOaviJBxgwwhyCwZBzVCVT U3tA56SHjn/VjhQ3lgHOkbq87xYWwwPQADOLx+VDM8bNUDyeGIY3G5L5+qtbjDCetj8i v+Is7G76zuHi/3tLIIN/Yi9m+VHcP6o6cD55vm0CAhI0pfJRYvXi0G4xADlmimoL5l6V guKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787427816; x=1788032616; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=TH0PJsVypITU/9irrzyoneF3uRtdmouDSRl9TezlEGQ=; b=nkyU5oc7TQYszuSRoeQXyALtmBMgcqd3ceAN6gf3+H2Cfho07QUQZW9exGIg+0T6AI ocJr3qyOtcMY3aHjB2F0QvkU2FlN4Zl0NlHtYiQvm5YQh7ZW9OW//vStRZ3uJNBAMSds HNHufXMrE7H+Qc18TsG03n//Mocttqch/A3b3nb75F2aNQ0QIDAt/GS4eUvWqU16esPs rVaJyZUNbq1gbBoQ0qEq5H2wKUhjpP6WD5UPrsBjTvvbTSjBdEbNoKROJvhcSz7i/GyE HI6GDzvdBAlErKteDVlef5dAoEVK8kHdDhCzzbC83xgizr5mIFqiHdUckfi9fjgchsYD IRnA== X-Forwarded-Encrypted: i=1; AHgh+RqKpDhWHe5vVbgaPPe6zHW/yNJavIfOBp+72epvrfbkbKLEyPDbYACRPH/2ucfR0zmGj1tEsjdr0g7E@nongnu.org X-Gm-Message-State: AFuF++kbxcsm4s8GAE7cFwPGJiR+xghXJmUXIW6ruwyBvRJR2z9gtCNg F334vXmQqkNOMzQ0+xAoW3CIB3GF5LY9jMGgC/2IUZsa1HgkGVa1Szdj X-Gm-Gg: AR+sD11cGutH1WF0NNimaFN3ZLsAJi0lRfwkHxUeYVDkFlqshrttd2pT0d9DXNnX6Mq PzA/6rbCgq7og1F1uL0BCbNb/QSZJZrogWaqgnkdh9EHNz/ROCG/RbhADTgyvQbpxa1F2au2exv mgbSzS23CkPssU0t/J8LJW3TwBmCpjqzbJ6K9SfoFJ/63mGElvpAEGVpQTXb7r/Nq+sIWdP2YRT fBYRZPwKS4WHlYmBlCdqKB8B0nAAr6P7RueyJklSt7rw9riRKQGZB2TfGbxfcfZvAK/xn15pWC7 Rr5Y5LhDQY2uH+7GHnSppES8w4GhCTBuxHKD/WvfYy6ylV5SucWj+Kx/ULRdnFgyIIi/VphnQjE j8g2APzZ+l1wJbQRMUpTMcGLA0lHcJgBCKwz/XN+vr7Kum19Xxm/+toNdXv+duAVafrbIQ+r6oP AlHiFlrfOoJlAxhqo7j8QmW6rsGUit+u+bSkoEw4PhoyQ1XXfl0OswHND0iA6ALYL8kFC44Sj66 hWXs2SkasVcl1TOel7RCsWEXXRlr2mulvzo+6NT4KhVxITUW7Plc/XFFB9x61X4Gw== X-Received: by 2002:a17:903:26c3:b0:2cf:4339:aaa with SMTP id d9443c01a7336-2d64b0c72d2mr311380235ad.12.1787427815821; Sat, 22 Aug 2026 12:43:35 -0700 (PDT) From: Kuan-Wei Chiu To: pierrick.bouvier@oss.qualcomm.com, almer@dabbelt.com, alistair.francis@wdc.com, pbonzini@redhat.com, marcandre.lureau@redhat.com, farosas@suse.de, lvivier@redhat.com Cc: liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, wxchen0913@gmail.com, jserv@ccns.ncku.edu.tw, marscheng@google.com, eleanor15x@gmail.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Kuan-Wei Chiu , Chao Liu Subject: [PATCH v4 1/7] hw/char: Add dw8250 UART Date: Sat, 22 Aug 2026 19:43:08 +0000 Message-ID: <20260822194315.2550260-2-visitorckw@gmail.com> X-Mailer: git-send-email 2.55.0.766.g2966f0265a-goog In-Reply-To: <20260822194315.2550260-1-visitorckw@gmail.com> References: <20260822194315.2550260-1-visitorckw@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=visitorckw@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787427873862158500 Content-Type: text/plain; charset="utf-8" Add the dw8250 uart support. This hardware is a widely used 16550A derivative that includes additional registers. Without this specific device support, the Linux 8250_dw driver fails to probe the extended registers (UCV, CPR, etc.), which are essential for correct feature detection. Signed-off-by: Kuan-Wei Chiu Reviewed-by: Chao Liu Reviewed-by: Alistair Francis --- hw/char/Kconfig | 4 ++ hw/char/dw8250.c | 131 +++++++++++++++++++++++++++++++++++++++ hw/char/meson.build | 1 + include/hw/char/dw8250.h | 27 ++++++++ 4 files changed, 163 insertions(+) create mode 100644 hw/char/dw8250.c create mode 100644 include/hw/char/dw8250.h diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 020c0a84bb..418d99b757 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -95,3 +95,7 @@ config IP_OCTAL_232 bool default y depends on IPACK + +config DW8250 + bool + select SERIAL diff --git a/hw/char/dw8250.c b/hw/char/dw8250.c new file mode 100644 index 0000000000..ccf05dd9ad --- /dev/null +++ b/hw/char/dw8250.c @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Synopsys DesignWare APB UART (DW 8250) + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/char/dw8250.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/qdev-properties-system.h" + +#define DW_UART_REGION_SIZE 0x100 + +#define DW_UART_RE_EN (0xB4 >> 2) /* Receiver Output Enable Register */ +#define DW_UART_DLF (0xC0 >> 2) /* Divisor Latch Fraction Register */ +#define DW_UART_CPR (0xF4 >> 2) /* Component Parameter Register */ +#define DW_UART_UCV (0xF8 >> 2) /* UART Component Version */ +#define DW_UART_CTR (0xFC >> 2) /* Component Type Register */ + +#define DW_UART_UCV_VALUE 0x3332332A /* "323*" -> v3.23a */ +#define DW_UART_CTR_VALUE 0x44570110 /* "DW" */ + +static uint64_t dw8250_ext_read(void *opaque, hwaddr addr, unsigned int si= ze) +{ + DW8250State *s =3D opaque; + + switch (addr >> s->regshift) { + case DW_UART_UCV: + return DW_UART_UCV_VALUE; + case DW_UART_CPR: + return 0x00000000; /* No advanced features (DMA, extra FIFOs) */ + case DW_UART_CTR: + return DW_UART_CTR_VALUE; + + case DW_UART_RE_EN: + case DW_UART_DLF: + /* + * Return 0 to indicate these optional features + * (RS485 and Fractional Divisor) are not implemented. + */ + return 0x00000000; + + default: + return 0; + } +} + +static void dw8250_ext_write(void *opaque, hwaddr addr, uint64_t val, unsi= gned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented write to address 0x%" HWAD= DR_PRIx "\n", + __func__, addr); +} + +static const MemoryRegionOps dw8250_ext_ops =3D { + .read =3D dw8250_ext_read, + .write =3D dw8250_ext_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void dw8250_instance_init(Object *obj) +{ + DW8250State *s =3D DW8250(obj); + + s->serial_mm =3D qdev_new("serial-mm"); + object_property_add_child(obj, "serial-mm", OBJECT(s->serial_mm)); + object_property_add_alias(obj, "chardev", OBJECT(s->serial_mm), "chard= ev"); +} + +static void dw8250_realize(DeviceState *dev, Error **errp) +{ + DW8250State *s =3D DW8250(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + SysBusDevice *serial_sbd =3D SYS_BUS_DEVICE(s->serial_mm); + + memory_region_init(&s->container, OBJECT(dev), "dw8250-container", + DW_UART_REGION_SIZE); + sysbus_init_mmio(sbd, &s->container); + + qdev_prop_set_uint8(s->serial_mm, "regshift", s->regshift); + qdev_prop_set_uint8(s->serial_mm, "endianness", DEVICE_LITTLE_ENDIAN); + if (!sysbus_realize(serial_sbd, errp)) { + return; + } + + memory_region_init_io(&s->ext_iomem, OBJECT(dev), &dw8250_ext_ops, s, + "dw8250-ext", DW_UART_REGION_SIZE); + memory_region_add_subregion(&s->container, 0, &s->ext_iomem); + + memory_region_add_subregion_overlap(&s->container, 0, + sysbus_mmio_get_region(serial_sbd,= 0), 1); + + sysbus_pass_irq(sbd, serial_sbd); +} + +static const Property dw8250_properties[] =3D { + DEFINE_PROP_UINT8("regshift", DW8250State, regshift, 2), +}; + +static void dw8250_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D dw8250_realize; + device_class_set_props(dc, dw8250_properties); +} + +static const TypeInfo dw8250_info =3D { + .name =3D TYPE_DW8250, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(DW8250State), + .instance_init =3D dw8250_instance_init, + .class_init =3D dw8250_class_init, +}; + +static void dw8250_register_types(void) +{ + type_register_static(&dw8250_info); +} + +type_init(dw8250_register_types) diff --git a/hw/char/meson.build b/hw/char/meson.build index fc3d7ee506..b2250ee6ae 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -38,6 +38,7 @@ system_ss.add(when: 'CONFIG_STM32L4X5_USART', if_true: fi= les('stm32l4x5_usart.c' system_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc= _mmuart.c')) system_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c')) system_ss.add(when: 'CONFIG_GOLDFISH_TTY', if_true: files('goldfish_tty.c'= )) +system_ss.add(when: 'CONFIG_DW8250', if_true: files('dw8250.c')) =20 specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.= c')) specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c')) diff --git a/include/hw/char/dw8250.h b/include/hw/char/dw8250.h new file mode 100644 index 0000000000..59396ad202 --- /dev/null +++ b/include/hw/char/dw8250.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Synopsys DesignWare APB UART (DW 8250) + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#ifndef HW_CHAR_DW8250_H +#define HW_CHAR_DW8250_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" + +#define TYPE_DW8250 "dw8250" +OBJECT_DECLARE_SIMPLE_TYPE(DW8250State, DW8250) + +struct DW8250State { + SysBusDevice parent_obj; + + MemoryRegion container; + MemoryRegion ext_iomem; + DeviceState *serial_mm; + + uint8_t regshift; +}; + +#endif --=20 2.55.0.766.g2966f0265a-goog From nobody Mon Sep 28 00:09:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1787427913; cv=none; d=zohomail.com; s=zohoarc; b=TL+xbxKB0xDCmjjO7/ONyMuJ9u1qMxTaXDFXMnZD6mpnIgj7dqUE+sh8d2V9UakgNfA9aWS1xh4d/wNasWghztbxKLiPDSMswKwFY7L041YbPVSdIxapYKv/yf/dHfAKamgW+Xk+NT4V/7gr72Ew+dnrA7Vv57jC6L/xI82ptHQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787427913; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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This is specifically required for the SDHCI controller to function correctly under Linux. The Linux 'sophgo,cv1800-clk' driver probes this device to determine the clock tree configuration. This implementation sets the bypass registers (CLK_BYP_0 and CLK_BYP_1) to 0xFFFFFFFF during reset, matching the POR default state. This bypasses the PLLs and allows the SDHCI and other peripherals to operate using the 25MHz reference clock. Without this device, the SD card driver fails to initialize, preventing the system from mounting the root filesystem from the SD card. Signed-off-by: Kuan-Wei Chiu --- hw/misc/Kconfig | 3 ++ hw/misc/cv1800b_clk.c | 90 +++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + include/hw/misc/cv1800b_clk.h | 26 ++++++++++ 4 files changed, 120 insertions(+) create mode 100644 hw/misc/cv1800b_clk.c create mode 100644 include/hw/misc/cv1800b_clk.h diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index b8860dd3e7..2325ddd348 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -260,4 +260,7 @@ config XLNX_ZYNQ_DDRC config AXIADO_CLK bool =20 +config SOPHGO_CV1800B_CLK + bool + source macio/Kconfig diff --git a/hw/misc/cv1800b_clk.c b/hw/misc/cv1800b_clk.c new file mode 100644 index 0000000000..b92f0889a3 --- /dev/null +++ b/hw/misc/cv1800b_clk.c @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Sophgo CV1800B Clock Controller + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/misc/cv1800b_clk.h" + +#define REG_BYTE_WIDTH (4) +#define REG_CLK_BYP_0 (0x030 / REG_BYTE_WIDTH) +#define REG_CLK_BYP_1 (0x034 / REG_BYTE_WIDTH) + +static uint64_t cv1800b_clk_read(void *opaque, hwaddr addr, unsigned int s= ize) +{ + CV1800BClkState *s =3D opaque; + uint32_t val =3D 0; + + if ((addr / REG_BYTE_WIDTH) < ARRAY_SIZE(s->regs)) { + val =3D s->regs[addr / REG_BYTE_WIDTH]; + } + + return val; +} + +static void cv1800b_clk_write(void *opaque, hwaddr addr, uint64_t val, uns= igned int size) +{ + CV1800BClkState *s =3D opaque; + + if ((addr / REG_BYTE_WIDTH) < ARRAY_SIZE(s->regs)) { + s->regs[addr / REG_BYTE_WIDTH] =3D val; + } +} + +static const MemoryRegionOps cv1800b_clk_ops =3D { + .read =3D cv1800b_clk_read, + .write =3D cv1800b_clk_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void cv1800b_clk_reset_hold(Object *obj, ResetType type) +{ + CV1800BClkState *s =3D CV1800B_CLK(obj); + + memset(s->regs, 0, sizeof(s->regs)); + + /* + * TODO: Implement proper PLL state machines. + * For now, use POR default to bypass PLLs and boot via 25MHz XTAL. + */ + s->regs[REG_CLK_BYP_0] =3D 0xFFFFFFFF; + s->regs[REG_CLK_BYP_1] =3D 0xFFFFFFFF; +} + +static void cv1800b_clk_init(Object *obj) +{ + CV1800BClkState *s =3D CV1800B_CLK(obj); + + memory_region_init_io(&s->iomem, obj, &cv1800b_clk_ops, s, + TYPE_CV1800B_CLK, CV1800B_CLK_IOSIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); +} + +static void cv1800b_clk_class_init(ObjectClass *klass, const void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.hold =3D cv1800b_clk_reset_hold; +} + +static const TypeInfo cv1800b_clk_info =3D { + .name =3D TYPE_CV1800B_CLK, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(CV1800BClkState), + .instance_init =3D cv1800b_clk_init, + .class_init =3D cv1800b_clk_class_init, +}; + +static void cv1800b_clk_register_types(void) +{ + type_register_static(&cv1800b_clk_info); +} + +type_init(cv1800b_clk_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 858ca845a2..4c6ae551ba 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -37,6 +37,7 @@ system_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: file= s('sifive_e_prci.c')) system_ss.add(when: 'CONFIG_SIFIVE_E_AON', if_true: files('sifive_e_aon.c'= )) system_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'= )) system_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.= c')) +system_ss.add(when: 'CONFIG_SOPHGO_CV1800B_CLK', if_true: files('cv1800b_c= lk.c')) =20 subdir('macio') =20 diff --git a/include/hw/misc/cv1800b_clk.h b/include/hw/misc/cv1800b_clk.h new file mode 100644 index 0000000000..4d03d887c6 --- /dev/null +++ b/include/hw/misc/cv1800b_clk.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Sophgo CV1800B Clock Controller + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#ifndef HW_MISC_CV1800B_CLK_H +#define HW_MISC_CV1800B_CLK_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" + +#define TYPE_CV1800B_CLK "cv1800b-clk" +OBJECT_DECLARE_SIMPLE_TYPE(CV1800BClkState, CV1800B_CLK) + +#define CV1800B_CLK_IOSIZE 0x1000 + +struct CV1800BClkState { + SysBusDevice parent_obj; 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[35.229.176.202]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d676895799sm5892715ad.38.2026.08.22.12.43.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Aug 2026 12:43:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787427828; x=1788032628; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=7YbGtFyJghBds0X81b0zsMRETgJDjhhcMH3+PLcidE8=; b=DvvBOnrk9Vk3O09nZtkL4hqS4N04cdl+T69gY+AuHyJJt6J1ZFwqPfNyM3/cJKfSOv z4GSxPpNZPKhzkMaV90SaA8bLVMZ15YoqDDjoRYVQFkFhe4r3rd/eEg4/lDA0KdeLg14 VvGoXa4rA1H+85AifoiT7liWsvi/VkrFCdDE9dTnEXOuBrt+Y1kzZ1+Lt72Gh4rcsJHd fXJVQDEzAoGHRg9QY8HcORMt3mJegCDyYyI/nH2GIVj2FhznjCAgbpx4gfKw0cBcyB3y d0mXRX2XDTOjZIhtRo21xCuYmTslhCE2RUjfTgzgncRPlNwwdF2igK0HkrVuoCgm4jW+ 6kmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787427828; x=1788032628; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=7YbGtFyJghBds0X81b0zsMRETgJDjhhcMH3+PLcidE8=; b=kCksEyx+1pu97a0JHJ9nKw04bDdB4XMd6evEjE3o08EQ+qvIHjnXClUA2fdC7Mdc62 5Va2oIW3PFNesi+y9TDCw71gOCmC0Xdpy4YYAFddNQch+6KYHJS6C1GVpefqJwDWRL/B kUOzQpdw0csILVh7R9x0GrEkEjh1rVzXb0CPagQyfbzVnmHpqSuGEHodiAOgCwh0SzY9 bs2+4xWgRpxdakSRmc2MoPXwvNPl4ld/1oScEwReoa9t1skDdYLyjD2zbMuOdaFtRJhQ EW6qHIAiFSpNVzj7IZ1M2LbgqcBnqSm0sRT2lr5TyDACxiBOnnKNqlEX2jSElDyA7/L3 v/3g== X-Forwarded-Encrypted: i=1; AHgh+RrOtXxlUkli/mAxnimSDQz8f+eGVucnAq21sjpJFEJHkyYjaY/RC00896s3+2n2hW1GSnoiEWzbSngC@nongnu.org X-Gm-Message-State: AFuF++nzW+4yleSqf8ReUSVzIdoBaIQb+JJDhgzNYYlvMnATyzYxL5nA EoRJ0piI0YSxPAYn+VsJ0eRba2Eod9E+RNTrtQd9qkCjGcDynUYu91ee X-Gm-Gg: AR+sD131d+DqL98W/Dd32jLEm+YnOXvrRafBLPLLT7MGI9cIj5gub5qXO3yM2RykN2X /z9uOU8j8wjFhU7orua5slnt5c4rvIF6cDo2ORRTD84XV+bzPNJxKEUu9ZYoaUber6StC6Ht2lc b+qkIxa23iZU9zRkdRaogxZ5mihWR8pt6THJdlX4TQTPP6Mhglm3ycO7sgx/Nzdi096ZnboLa3b zrMRADEQEDlZMapRWkyVclGYUMuwqeaIgNLNDxC9DeCbZh6OT2jMs+U5q2mpbOzHta3Xz4/IQzO STOjG/l+B/apLVT2xsNKq7cB+yG7bSThq2dCvk0rrEs1AnvEgWYtLihmTiVvXvIdYHUQ1CyGeXy rn7jbajxD8TqqnzlciZKknlVal2qGiQJ4RLe0A8r69HSFLQwVqQg1JgaCPK8Shle0x5cKlSr+so jUFUlxLHLr+kSX1MdB8E3kGMEEHZVXknjV8wTfIWwfBrC/OXFRI1MFWywoPo6TYliarw8cw1WKb o8Xv6Isi4wdTd/xvzkSeLN7+zWEcVUPk50Zo0bGEul6Yrb0Po1AbxIpFKP92Q1THg== X-Received: by 2002:a17:902:cf0e:b0:2c9:aae1:a61a with SMTP id d9443c01a7336-2d670dd98d6mr139833495ad.14.1787427827929; Sat, 22 Aug 2026 12:43:47 -0700 (PDT) From: Kuan-Wei Chiu To: pierrick.bouvier@oss.qualcomm.com, almer@dabbelt.com, alistair.francis@wdc.com, pbonzini@redhat.com, marcandre.lureau@redhat.com, farosas@suse.de, lvivier@redhat.com Cc: liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, wxchen0913@gmail.com, jserv@ccns.ncku.edu.tw, marscheng@google.com, eleanor15x@gmail.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Kuan-Wei Chiu Subject: [PATCH v4 3/7] hw/riscv: Add Sophgo CV1800B SoC support Date: Sat, 22 Aug 2026 19:43:10 +0000 Message-ID: <20260822194315.2550260-4-visitorckw@gmail.com> X-Mailer: git-send-email 2.55.0.766.g2966f0265a-goog In-Reply-To: <20260822194315.2550260-1-visitorckw@gmail.com> References: <20260822194315.2550260-1-visitorckw@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=visitorckw@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787427937604158500 Content-Type: text/plain; charset="utf-8" Add the Sophgo CV1800B SoC, which is the heart of the Milk-V Duo board. The SoC features a T-Head C906 CPU along with integrated PLIC, CLINT, and dw8250 UART. The memory map and interrupts are configured according to the CV1800B datasheet. [1] Several peripheral blocks are included as unimplemented devices to ensure that drivers can probe successfully without causing errors during boot. Link: https://github.com/milkv-duo/duo-files/tree/main/duo/datasheet [1] Signed-off-by: Kuan-Wei Chiu Acked-by: Alistair Francis --- hw/riscv/Kconfig | 8 ++ hw/riscv/cv1800b.c | 174 +++++++++++++++++++++++++++++++++++++ hw/riscv/meson.build | 2 + include/hw/riscv/cv1800b.h | 56 ++++++++++++ 4 files changed, 240 insertions(+) create mode 100644 hw/riscv/cv1800b.c create mode 100644 include/hw/riscv/cv1800b.h diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index de37c08cae..5ab38f228f 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -162,3 +162,11 @@ config K230 select SERIAL_MM select UNIMP select K230_WDT + +config SOPHGO_CV1800B + bool + depends on RISCV64 + select RISCV_ACLINT + select SIFIVE_PLIC + select SOPHGO_CV1800B_CLK + select DW8250 diff --git a/hw/riscv/cv1800b.c b/hw/riscv/cv1800b.c new file mode 100644 index 0000000000..32e46a4639 --- /dev/null +++ b/hw/riscv/cv1800b.c @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Sophgo CV1800B SoC + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/riscv/cv1800b.h" +#include "hw/core/qdev-properties.h" +#include "target/riscv/cpu-qom.h" +#include "system/system.h" +#include "hw/intc/riscv_aclint.h" +#include "system/address-spaces.h" +#include "hw/intc/sifive_plic.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/boot.h" +#include "hw/sd/sdhci.h" +#include "hw/misc/unimp.h" + +const MemMapEntry cv1800b_memmap[] =3D { + [CV1800B_DEV_TOP_MISC] =3D { 0x03000000, 0x1000 }, + [CV1800B_DEV_PINMUX] =3D { 0x03001000, 0x1000 }, + [CV1800B_DEV_CLK] =3D { 0x03002000, 0x1000 }, + [CV1800B_DEV_RST] =3D { 0x03003000, 0x1000 }, + [CV1800B_DEV_WDT] =3D { 0x03010000, 0x1000 }, + [CV1800B_DEV_GPIO] =3D { 0x03020000, 0x4000 }, + [CV1800B_DEV_UART0] =3D { 0x04140000, 0x10000 }, + [CV1800B_DEV_SD0] =3D { 0x04310000, 0x10000 }, + [CV1800B_DEV_ROM] =3D { 0x04400000, 0x10000 }, + [CV1800B_DEV_RTC_GPIO] =3D { 0x05021000, 0x1000 }, + [CV1800B_DEV_RTC_IO] =3D { 0x05027000, 0x1000 }, + [CV1800B_DEV_PLIC] =3D { 0x70000000, 0x4000000 }, + [CV1800B_DEV_CLINT] =3D { 0x74000000, 0x10000 }, + [CV1800B_DEV_DRAM] =3D { 0x80000000, 0x0 }, +}; + +static void cv1800b_soc_instance_init(Object *obj) +{ + CV1800BSoCState *s =3D CV1800B_SOC(obj); + + object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); + qdev_prop_set_uint32(DEVICE(&s->cpus), "hartid-base", 0); + qdev_prop_set_string(DEVICE(&s->cpus), "cpu-type", TYPE_RISCV_CPU_THEA= D_C906); + qdev_prop_set_uint64(DEVICE(&s->cpus), "resetvec", + cv1800b_memmap[CV1800B_DEV_ROM].base); + + object_initialize_child(obj, "clk", &s->clk, TYPE_CV1800B_CLK); + object_initialize_child(obj, "uart", &s->uart, TYPE_DW8250); + object_initialize_child(obj, "sdhci", &s->sdhci, TYPE_SYSBUS_SDHCI); +} + +static void cv1800b_soc_realize(DeviceState *dev, Error **errp) +{ + CV1800BSoCState *s =3D CV1800B_SOC(dev); + MachineState *ms =3D MACHINE(qdev_get_machine()); + uint32_t num_harts =3D ms->smp.cpus; + MemoryRegion *system_memory =3D get_system_memory(); + char *plic_hart_config; + + qdev_prop_set_uint32(DEVICE(&s->cpus), "num-harts", num_harts); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpus), errp)) { + return; + } + + memory_region_init_rom(&s->rom, OBJECT(dev), "cv1800b.rom", + cv1800b_memmap[CV1800B_DEV_ROM].size, &error_fa= tal); + memory_region_add_subregion(system_memory, + cv1800b_memmap[CV1800B_DEV_ROM].base, &s->= rom); + + riscv_aclint_swi_create(cv1800b_memmap[CV1800B_DEV_CLINT].base, + 0, num_harts, false); + riscv_aclint_mtimer_create(cv1800b_memmap[CV1800B_DEV_CLINT].base + + RISCV_ACLINT_SWI_SIZE, + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, + 0, num_harts, RISCV_ACLINT_DEFAULT_MTIMECMP, + RISCV_ACLINT_DEFAULT_MTIME, + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); + + plic_hart_config =3D riscv_plic_hart_config_string(num_harts); + s->plic =3D sifive_plic_create( + cv1800b_memmap[CV1800B_DEV_PLIC].base, + plic_hart_config, + num_harts, + 0, + CV1800B_PLIC_NUM_SOURCES, + CV1800B_PLIC_NUM_PRIORITIES, + 0x0, + 0x1000, + 0x2000, + 0x80, + 0x200000, + 0x1000, + cv1800b_memmap[CV1800B_DEV_PLIC].size); + + g_free(plic_hart_config); + + qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2); + qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, cv1800b_memmap[CV1800B_DE= V_UART0].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, + qdev_get_gpio_in(DEVICE(s->plic), CV1800B_UART0_IRQ)); + + qdev_prop_set_uint8(DEVICE(&s->sdhci), "sd-spec-version", 3); + qdev_prop_set_uint64(DEVICE(&s->sdhci), "capareg", 0x056900b9); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, cv1800b_memmap[CV1800B_D= EV_SD0].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, + qdev_get_gpio_in(DEVICE(s->plic), CV1800B_SD0_IRQ)); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->clk), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, + cv1800b_memmap[CV1800B_DEV_CLK].base); + + create_unimplemented_device("cv1800b.top_misc", + cv1800b_memmap[CV1800B_DEV_TOP_MISC].base, + cv1800b_memmap[CV1800B_DEV_TOP_MISC].size); + + create_unimplemented_device("cv1800b.pinmux", + cv1800b_memmap[CV1800B_DEV_PINMUX].base, + cv1800b_memmap[CV1800B_DEV_PINMUX].size); + + create_unimplemented_device("cv1800b.rst", + cv1800b_memmap[CV1800B_DEV_RST].base, + cv1800b_memmap[CV1800B_DEV_RST].size); + + create_unimplemented_device("cv1800b.wdt", + cv1800b_memmap[CV1800B_DEV_WDT].base, + cv1800b_memmap[CV1800B_DEV_WDT].size); + + create_unimplemented_device("cv1800b.gpio0_3", + cv1800b_memmap[CV1800B_DEV_GPIO].base, + cv1800b_memmap[CV1800B_DEV_GPIO].size); + + create_unimplemented_device("cv1800b.rtc_gpio", + cv1800b_memmap[CV1800B_DEV_RTC_GPIO].base, + cv1800b_memmap[CV1800B_DEV_RTC_GPIO].size); + + create_unimplemented_device("cv1800b.rtc_io", + cv1800b_memmap[CV1800B_DEV_RTC_IO].base, + cv1800b_memmap[CV1800B_DEV_RTC_IO].size); +} + +static void cv1800b_soc_class_init(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D cv1800b_soc_realize; + dc->user_creatable =3D false; +} + +static const TypeInfo cv1800b_soc_type_info =3D { + .name =3D TYPE_CV1800B_SOC, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(CV1800BSoCState), + .instance_init =3D cv1800b_soc_instance_init, + .class_init =3D cv1800b_soc_class_init, +}; + +static void cv1800b_soc_register_types(void) +{ + type_register_static(&cv1800b_soc_type_info); +} + +type_init(cv1800b_soc_register_types) diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 0d82ceacc4..b278b443b6 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -21,4 +21,6 @@ riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: file= s('cps.c')) riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'= )) riscv_ss.add(when: 'CONFIG_K230', if_true: files('k230.c')) =20 +riscv_ss.add(when: 'CONFIG_SOPHGO_CV1800B', if_true: files('cv1800b.c')) + hw_arch +=3D {'riscv': riscv_ss} diff --git a/include/hw/riscv/cv1800b.h b/include/hw/riscv/cv1800b.h new file mode 100644 index 0000000000..bde5eff96b --- /dev/null +++ b/include/hw/riscv/cv1800b.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Sophgo CV1800B SoC + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#ifndef HW_RISCV_CV1800B_H +#define HW_RISCV_CV1800B_H + +#include "hw/core/boards.h" +#include "hw/riscv/riscv_hart.h" +#include "hw/misc/cv1800b_clk.h" +#include "hw/char/dw8250.h" +#include "hw/sd/sdhci.h" + +#define TYPE_CV1800B_SOC "cv1800b-soc" +OBJECT_DECLARE_SIMPLE_TYPE(CV1800BSoCState, CV1800B_SOC) + +struct CV1800BSoCState { + DeviceState parent_obj; + + RISCVHartArrayState cpus; + MemoryRegion rom; + DeviceState *plic; + CV1800BClkState clk; + DW8250State uart; + SDHCIState sdhci; +}; + +#define CV1800B_PLIC_NUM_SOURCES 136 +#define CV1800B_PLIC_NUM_PRIORITIES 31 + +#define CV1800B_UART0_IRQ 44 +#define CV1800B_SD0_IRQ 36 + +enum { + CV1800B_DEV_TOP_MISC, + CV1800B_DEV_PINMUX, + CV1800B_DEV_CLK, + CV1800B_DEV_RST, + CV1800B_DEV_WDT, + CV1800B_DEV_GPIO, + CV1800B_DEV_UART0, + CV1800B_DEV_SD0, + CV1800B_DEV_ROM, + CV1800B_DEV_RTC_GPIO, + CV1800B_DEV_RTC_IO, + CV1800B_DEV_PLIC, + CV1800B_DEV_CLINT, + CV1800B_DEV_DRAM, +}; + +extern const MemMapEntry cv1800b_memmap[]; + +#endif --=20 2.55.0.766.g2966f0265a-goog From nobody Mon Sep 28 00:09:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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The implementation includes: - Board-level machine initialization with 64mb of default ram. - Integration of the CV1800B SoC. - Support for loading external FDT, kernel, and initrd images. - Proper setup of the reset vector to match the CV1800B's boot flow. Signed-off-by: Kuan-Wei Chiu Acked-by: Alistair Francis Reviewed-by: Chao Liu --- MAINTAINERS | 11 ++ configs/devices/riscv64-softmmu/default.mak | 1 + hw/riscv/Kconfig | 6 + hw/riscv/meson.build | 1 + hw/riscv/milkv_duo.c | 120 ++++++++++++++++++++ 5 files changed, 139 insertions(+) create mode 100644 hw/riscv/milkv_duo.c diff --git a/MAINTAINERS b/MAINTAINERS index 08017f4786..dde85ef420 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1851,6 +1851,17 @@ F: include/hw/watchdog/k230_wdt.h F: tests/functional/riscv64/test_k230.py F: tests/qtest/k230-wdt-test.c =20 +Milk-V Duo +M: Kuan-Wei Chiu +S: Maintained +F: hw/char/dw8250.c +F: hw/misc/cv1800b_clk.c +F: hw/riscv/cv1800b.c +F: hw/riscv/milkv_duo.c +F: include/hw/char/dw8250.h +F: include/hw/misc/cv1800b_clk.h +F: include/hw/riscv/cv1800b.h + RX Machines ----------- rx-gdbsim diff --git a/configs/devices/riscv64-softmmu/default.mak b/configs/devices/= riscv64-softmmu/default.mak index a8e4d0ab33..2ba91b14d4 100644 --- a/configs/devices/riscv64-softmmu/default.mak +++ b/configs/devices/riscv64-softmmu/default.mak @@ -13,3 +13,4 @@ # CONFIG_SHAKTI_C=3Dn # CONFIG_XIANGSHAN_KUNMINGHU=3Dn # CONFIG_MIPS_BOSTON_AIA=3Dn +# CONFIG_MILKV_DUO=3Dn diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 5ab38f228f..6360de4260 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -170,3 +170,9 @@ config SOPHGO_CV1800B select SIFIVE_PLIC select SOPHGO_CV1800B_CLK select DW8250 + +config MILKV_DUO + bool + depends on RISCV64 + default y + select SOPHGO_CV1800B diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index b278b443b6..0ab1baec88 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -22,5 +22,6 @@ riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: fil= es('boston-aia.c')) riscv_ss.add(when: 'CONFIG_K230', if_true: files('k230.c')) =20 riscv_ss.add(when: 'CONFIG_SOPHGO_CV1800B', if_true: files('cv1800b.c')) +riscv_ss.add(when: 'CONFIG_MILKV_DUO', if_true: files('milkv_duo.c')) =20 hw_arch +=3D {'riscv': riscv_ss} diff --git a/hw/riscv/milkv_duo.c b/hw/riscv/milkv_duo.c new file mode 100644 index 0000000000..ec09243bef --- /dev/null +++ b/hw/riscv/milkv_duo.c @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Milk-V Duo board + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "hw/core/boards.h" +#include "hw/riscv/cv1800b.h" +#include "hw/riscv/boot.h" +#include "target/riscv/cpu-qom.h" +#include "system/system.h" +#include "system/device_tree.h" +#include "qemu/error-report.h" +#include "hw/core/loader.h" +#include +#include "hw/riscv/machines-qom.h" + +struct MilkVDuoState { + MachineState parent_obj; + CV1800BSoCState soc; +}; + +#define TYPE_MILK_V_DUO MACHINE_TYPE_NAME("milkv-duo") +OBJECT_DECLARE_SIMPLE_TYPE(MilkVDuoState, MILK_V_DUO) + +static void milkv_duo_init(MachineState *machine) +{ + MilkVDuoState *s =3D MILK_V_DUO(machine); + MemoryRegion *system_memory =3D get_system_memory(); + RISCVBootInfo boot_info; + const char *firmware_name; + hwaddr firmware_load_addr, firmware_end_addr; + hwaddr fdt_load_addr =3D 0; + int fdt_size =3D 0; + uint64_t kernel_entry =3D 0; + + object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_CV1800B_= SOC); + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); + + memory_region_add_subregion(system_memory, + cv1800b_memmap[CV1800B_DEV_DRAM].base, + machine->ram); + + riscv_boot_info_init(&boot_info, &s->soc.cpus); + + firmware_name =3D riscv_default_firmware_name(&s->soc.cpus); + firmware_load_addr =3D cv1800b_memmap[CV1800B_DEV_DRAM].base; + firmware_end_addr =3D riscv_find_and_load_firmware(machine, &boot_info, + firmware_name, + &firmware_load_addr, = NULL); + + if (machine->dtb) { + machine->fdt =3D load_device_tree(machine->dtb, &fdt_size); + if (!machine->fdt) { + error_report("Failed to load device tree"); + exit(1); + } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + if (fdt_path_offset(machine->fdt, "/chosen") < 0) { + qemu_fdt_add_subnode(machine->fdt, "/chosen"); + } + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } + } + + if (machine->kernel_filename) { + hwaddr kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_in= fo, + firmware_e= nd_addr); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, true, NU= LL); + kernel_entry =3D boot_info.image_low_addr; + } + + if (machine->dtb) { + fdt_load_addr =3D riscv_compute_fdt_addr(cv1800b_memmap[CV1800B_DE= V_DRAM].base, + machine->ram_size, machine,= &boot_info); + riscv_load_fdt(fdt_load_addr, machine->fdt); + } + + riscv_setup_rom_reset_vec(machine, &s->soc.cpus, + firmware_load_addr, + cv1800b_memmap[CV1800B_DEV_ROM].base, + cv1800b_memmap[CV1800B_DEV_ROM].size, + kernel_entry, + fdt_load_addr); +} + +static void milkv_duo_machine_class_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + static const char *const valid_cpu_types[] =3D { + TYPE_RISCV_CPU_THEAD_C906, + NULL + }; + + mc->desc =3D "Milk-V Duo Board (CV1800B)"; + mc->init =3D milkv_duo_init; + mc->max_cpus =3D 2; + mc->default_cpu_type =3D TYPE_RISCV_CPU_THEAD_C906; + mc->valid_cpu_types =3D valid_cpu_types; + mc->default_ram_size =3D 64 * MiB; + mc->default_ram_id =3D "riscv.milkv_duo.ram"; +} + +static const TypeInfo milkv_duo_machine_type_infos[] =3D { + { + .name =3D TYPE_MILK_V_DUO, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(MilkVDuoState), + .class_init =3D milkv_duo_machine_class_init, + .interfaces =3D riscv64_machine_interfaces, + }, +}; + +DEFINE_TYPES(milkv_duo_machine_type_infos) --=20 2.55.0.766.g2966f0265a-goog From nobody Mon Sep 28 00:09:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Currently tested: - Verify DW8250 UART component version and type signatures. - Test read/write access to CV1800B clock bypass register. Tested with: $ meson test -C build -v qemu:qtest-riscv64/milkv-duo-test [...] Ok: 1 Fail: 0 Signed-off-by: Kuan-Wei Chiu Acked-by: Alistair Francis --- MAINTAINERS | 1 + tests/qtest/meson.build | 3 +- tests/qtest/milkv-duo-test.c | 70 ++++++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/milkv-duo-test.c diff --git a/MAINTAINERS b/MAINTAINERS index dde85ef420..245eb7bb58 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1861,6 +1861,7 @@ F: hw/riscv/milkv_duo.c F: include/hw/char/dw8250.h F: include/hw/misc/cv1800b_clk.h F: include/hw/riscv/cv1800b.h +F: tests/qtest/milkv-duo-test.c =20 RX Machines ----------- diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 12ed368997..d02dbf7433 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -299,7 +299,8 @@ qtests_riscv64 =3D ['riscv-csr-test'] + \ (config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') and config_all_devices.has_key('CONFIG_RISCV_IOMMU') ? ['iommu-riscv-test'] : []) + \ - (config_all_devices.has_key('CONFIG_K230') ? ['k230-wdt-test'] : []) + (config_all_devices.has_key('CONFIG_K230') ? ['k230-wdt-test'] : []) + \ + ['milkv-duo-test'] =20 qtests_hexagon =3D ['boot-serial-test', 'l2vic-test', 'qct-qtimer-test'] =20 diff --git a/tests/qtest/milkv-duo-test.c b/tests/qtest/milkv-duo-test.c new file mode 100644 index 0000000000..06064b8733 --- /dev/null +++ b/tests/qtest/milkv-duo-test.c @@ -0,0 +1,70 @@ +/* + * QTest for Milk-V Duo Board + * + * Copyright (c) 2026 Kuan-Wei Chiu + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +#define CV1800B_CLK_BASE 0x03002000 +#define CV1800B_CLK_BYPASS 0x030 +#define CV1800B_CLK_BYPASS_RESET 0xFFFFFFFF +#define TEST_PATTERN_5A 0x5A5A5A5A +#define TEST_PATTERN_A5 0xA5A5A5A5 + +#define CV1800B_UART0_BASE 0x04140000 +#define DW_UART_UCV 0xF8 +#define DW_UART_CTR 0xFC +#define DW_UART_VERSION_3_23A 0x3332332A +#define DW_UART_TYPE_SIGNATURE 0x44570110 + +static void test_milkv_duo_uart(void) +{ + QTestState *qts; + uint32_t component_version; + uint32_t component_type; + + qts =3D qtest_init("-M milkv-duo"); + + component_version =3D qtest_readl(qts, CV1800B_UART0_BASE + DW_UART_UC= V); + g_assert_cmphex(component_version, =3D=3D, DW_UART_VERSION_3_23A); + + component_type =3D qtest_readl(qts, CV1800B_UART0_BASE + DW_UART_CTR); + g_assert_cmphex(component_type, =3D=3D, DW_UART_TYPE_SIGNATURE); + + qtest_quit(qts); +} + +static void test_milkv_duo_clk(void) +{ + QTestState *qts; + uint32_t clk_bypass_val; + + qts =3D qtest_init("-M milkv-duo"); + + clk_bypass_val =3D qtest_readl(qts, CV1800B_CLK_BASE + CV1800B_CLK_BYP= ASS); + g_assert_cmphex(clk_bypass_val, =3D=3D, CV1800B_CLK_BYPASS_RESET); + + qtest_writel(qts, CV1800B_CLK_BASE + CV1800B_CLK_BYPASS, TEST_PATTERN_= 5A); + clk_bypass_val =3D qtest_readl(qts, CV1800B_CLK_BASE + CV1800B_CLK_BYP= ASS); + g_assert_cmphex(clk_bypass_val, =3D=3D, TEST_PATTERN_5A); + + qtest_writel(qts, CV1800B_CLK_BASE + CV1800B_CLK_BYPASS, TEST_PATTERN_= A5); + clk_bypass_val =3D qtest_readl(qts, CV1800B_CLK_BASE + CV1800B_CLK_BYP= ASS); + g_assert_cmphex(clk_bypass_val, =3D=3D, TEST_PATTERN_A5); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/riscv/milkv-duo/uart", test_milkv_duo_uart); + qtest_add_func("/riscv/milkv-duo/clk", test_milkv_duo_clk); + + return g_test_run(); +} --=20 2.55.0.766.g2966f0265a-goog From nobody Mon Sep 28 00:09:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1787427918; cv=none; d=zohomail.com; s=zohoarc; b=et/loGlKI+A9qhldfAOhmAPaaZnxrfbPZ/1XHRc5epKAmm8phG1WBbUJRUA8PBAwgZ0AkOrAyIp2xafp6+F6IKZcFIyUXQwCQFzdPbKitkH4sNsfvcSDa8EOEMZruAO+S7/zmbzwvBr8X5B8xtfLXPjCC1Pf9HIshuEs0Yzy6NE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787427918; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8WKVV9PziZHmSvQUMhJjnQhg2yjA+sQeyn79pi3JXQU=; b=Psi5Ur9ipMEggU3CLBInK3tiTKhtGtlwNNb/RTB8z2x+bRLdbFAn+EPOUI9a0DBwYNBqcIL4xiSS/un+MAyigQ+FXRnfJbsnbhe5KLiKa1h4p1z1no5HyZ0UKsMvQrMpGcxyWOw8pZkELTB/7n+30njUao/Qx4xpJAkrNEiDd4M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17874279183241015.190982551213; Sat, 22 Aug 2026 12:45:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxrdT-00022Y-8k; Sat, 22 Aug 2026 15:44:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxrdR-00020W-Lp for qemu-devel@nongnu.org; Sat, 22 Aug 2026 15:44:09 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxrdP-0007Bs-W4 for qemu-devel@nongnu.org; Sat, 22 Aug 2026 15:44:09 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-2d0407aedd6so23854365ad.0 for ; Sat, 22 Aug 2026 12:44:07 -0700 (PDT) Received: from visitorckw-work01.c.googlers.com.com (202.176.229.35.bc.googleusercontent.com. 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Sat, 22 Aug 2026 12:44:06 -0700 (PDT) From: Kuan-Wei Chiu To: pierrick.bouvier@oss.qualcomm.com, almer@dabbelt.com, alistair.francis@wdc.com, pbonzini@redhat.com, marcandre.lureau@redhat.com, farosas@suse.de, lvivier@redhat.com Cc: liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, wxchen0913@gmail.com, jserv@ccns.ncku.edu.tw, marscheng@google.com, eleanor15x@gmail.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Kuan-Wei Chiu Subject: [PATCH v4 6/7] tests/functional/riscv64: Add boot test for Milk-V Duo board Date: Sat, 22 Aug 2026 19:43:13 +0000 Message-ID: <20260822194315.2550260-7-visitorckw@gmail.com> X-Mailer: git-send-email 2.55.0.766.g2966f0265a-goog In-Reply-To: <20260822194315.2550260-1-visitorckw@gmail.com> References: <20260822194315.2550260-1-visitorckw@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=visitorckw@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787427920577158500 Content-Type: text/plain; charset="utf-8" Add a functional boot test for the Milk-V Duo board to validate the end-to-end boot flow. $ ./build/run ./tests/functional/riscv64/test_milkv_duo.py TAP version 13 ok 1 test_milkv_duo.MilkvDuoMachine.test_riscv64_milkv_duo 1..1 Signed-off-by: Kuan-Wei Chiu --- MAINTAINERS | 1 + tests/functional/riscv64/meson.build | 1 + tests/functional/riscv64/test_milkv_duo.py | 50 ++++++++++++++++++++++ 3 files changed, 52 insertions(+) create mode 100755 tests/functional/riscv64/test_milkv_duo.py diff --git a/MAINTAINERS b/MAINTAINERS index 245eb7bb58..3f79334c59 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1861,6 +1861,7 @@ F: hw/riscv/milkv_duo.c F: include/hw/char/dw8250.h F: include/hw/misc/cv1800b_clk.h F: include/hw/riscv/cv1800b.h +F: tests/functional/riscv64/test_milkv_duo.py F: tests/qtest/milkv-duo-test.c =20 RX Machines diff --git a/tests/functional/riscv64/meson.build b/tests/functional/riscv6= 4/meson.build index d1a3e6c2bf..8a4f1d00f9 100644 --- a/tests/functional/riscv64/meson.build +++ b/tests/functional/riscv64/meson.build @@ -18,4 +18,5 @@ tests_riscv64_system_thorough =3D [ 'sifive_u', 'tt_atlantis', 'tuxrun', + 'milkv_duo', ] diff --git a/tests/functional/riscv64/test_milkv_duo.py b/tests/functional/= riscv64/test_milkv_duo.py new file mode 100755 index 0000000000..aff247e61f --- /dev/null +++ b/tests/functional/riscv64/test_milkv_duo.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# +# Functional test that boots a Linux kernel on a Milk-V Duo machine +# +# Copyright (c) 2026 Kuan-Wei Chiu +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import LinuxKernelTest, Asset +from qemu_test import wait_for_console_pattern + +class MilkvDuoMachine(LinuxKernelTest): + + timeout =3D 120 + + ASSET_KERNEL =3D Asset( + 'https://github.com/visitorckw/milkv-duo-qemu-assets/releases/down= load/v1.0/Image', + '3f157ecfcb86d28bfcff9fd3c1a43f60a8513b1919739fdc9a4d946aba35b2af' + ) + ASSET_DTB =3D Asset( + 'https://github.com/visitorckw/milkv-duo-qemu-assets/releases/down= load/v1.0/cv1800b-milkv-duo.dtb', + '2a5d165f64c4b2d55bba282b2974941ab223f6f5220c2e7721e35ab81311c098' + ) + ASSET_ROOTFS =3D Asset( + 'https://github.com/visitorckw/milkv-duo-qemu-assets/releases/down= load/v1.0/rootfs.ext4', + '9e7de9222ab4a79d1291866453aa47cd67a543216df6159bf9b42d055240a676' + ) + + def test_riscv64_milkv_duo(self): + self.set_machine('milkv-duo') + + kernel_path =3D self.ASSET_KERNEL.fetch() + dtb_path =3D self.ASSET_DTB.fetch() + rootfs_path =3D self.ASSET_ROOTFS.fetch() + + self.vm.set_console() + self.vm.add_args('-bios', 'default', + '-kernel', kernel_path, + '-dtb', dtb_path, + '-drive', f'file=3D{rootfs_path},format=3Draw,id= =3Dsd-card,snapshot=3Don', + '-device', 'sd-card,drive=3Dsd-card', + '-append', 'console=3DttyS0,115200 root=3D/dev/mm= cblk0 rootwait earlycon') + + self.vm.launch() + + wait_for_console_pattern(self, 'Booting Linux on hartid') + wait_for_console_pattern(self, 'Run /sbin/init as init process') + +if __name__ =3D=3D '__main__': + LinuxKernelTest.main() --=20 2.55.0.766.g2966f0265a-goog From nobody Mon Sep 28 00:09:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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This includes a brief overview of the hardware, a list of supported devices, and practical instructions on how to boot the machine using OpenSBI and a Linux kernel with an emulated SD card. Signed-off-by: Kuan-Wei Chiu Acked-by: Alistair Francis --- MAINTAINERS | 1 + docs/system/riscv/milkv-duo.rst | 49 +++++++++++++++++++++++++++++++++ docs/system/target-riscv.rst | 1 + 3 files changed, 51 insertions(+) create mode 100644 docs/system/riscv/milkv-duo.rst diff --git a/MAINTAINERS b/MAINTAINERS index 3f79334c59..9750a39ca3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1854,6 +1854,7 @@ F: tests/qtest/k230-wdt-test.c Milk-V Duo M: Kuan-Wei Chiu S: Maintained +F: docs/system/riscv/milkv-duo.rst F: hw/char/dw8250.c F: hw/misc/cv1800b_clk.c F: hw/riscv/cv1800b.c diff --git a/docs/system/riscv/milkv-duo.rst b/docs/system/riscv/milkv-duo.= rst new file mode 100644 index 0000000000..1758db2c1e --- /dev/null +++ b/docs/system/riscv/milkv-duo.rst @@ -0,0 +1,49 @@ +Milk-V Duo board (``milkv-duo``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +The ``milkv-duo`` machine is compatible with the Milk-V Duo development bo= ard. + +The Milk-V Duo is an ultra-compact embedded development platform based on = the +Sophgo CV1800B SoC. The CV1800B features T-Head C906 RISC-V processing cor= es +along with integrated peripherals. + +For more information, see + +Supported devices +----------------- +The ``milkv-duo`` machine supports the following devices: + +* T-Head C906 cores +* Core Local Interruptor (CLINT) +* Platform-Level Interrupt Controller (PLIC) +* DesignWare APB UART (dw8250) +* SDHCI controller +* CV1800B clock controller + +Boot options +------------ +The ``milkv-duo`` machine supports direct boot using a generic RISC-V Open= SBI +firmware and a Linux kernel. The root filesystem can be provided via the +emulated SD card. + +Running +------- +To boot the machine, you need a Linux kernel (built with CV1800B support),= a +device tree blob (DTB), and a root filesystem image (e.g., built via BusyB= ox +or Buildroot). + +Use the following command to boot the system directly to the Linux shell: + +.. code-block:: bash + + $ qemu-system-riscv64 -M milkv-duo -nographic \ + -bios pc-bios/opensbi-riscv64-generic-fw_dynamic.bin \ + -dtb /path/to/linux/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dtb= \ + -kernel /path/to/linux/arch/riscv/boot/Image \ + -drive file=3D/path/to/rootfs.ext4,format=3Draw,id=3Dsd-card \ + -device sd-card,drive=3Dsd-card \ + -append "console=3DttyS0,115200 root=3D/dev/mmcblk0 rootwait earlyco= n" + +This command boots the generic OpenSBI firmware, loads the Linux Image and= the +specified DTB, and mounts the ext4 root filesystem from the emulated SD ca= rd. +The console output is routed to the ``ttyS0`` serial port. diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 2639866a3e..1e49055e29 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -69,6 +69,7 @@ undocumented; you can get a complete list by running riscv/k230 riscv/microblaze-v-generic riscv/microchip-icicle-kit + riscv/milkv-duo riscv/mips riscv/shakti-c riscv/sifive_u --=20 2.55.0.766.g2966f0265a-goog