From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310142; cv=none; d=zohomail.com; s=zohoarc; b=Ehd+qFuZP/SVkdnqI6bf+86fBos5sxIWPnmdgwiCqEaoW2QtHpes5cwVaNYRNQNeDk19UmejE048J3l4/rlPxNj0BxVRL3sZv63jlJczZ0iDjPIaGCtU8lXhPfbYdhMSOeTkZWTTVC8bwCO8z/oDtcxy2mYU7VSy/pcqLjmNLlc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310142; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Vo9PbbbPqYN1Ef4Ej8cwJZ2Oz8N8SbnTX3lrcCjaQzQ=; b=HMVThII6UPWpnuRAHwBvHH6JQ2+m7IRzGJVGRGJfQTEXfff1ZPJSY92JLVTEaBX1LWlluvDgSnjeZm7dwG1dhwi0W1cfeEBhotSqK7VaFEeV8Qxp9inVy8Oc7hqpIiePnc3adketgj9jLrEkRk/h5q+9yezcgCb8lfnHNa9YVOs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310142287775.3276784849463; Fri, 21 Aug 2026 04:02:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN0K-00064E-Jp; Fri, 21 Aug 2026 07:01:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN06-00061B-L4 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:30 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN05-0007Dl-3l for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:30 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-49557167508so7159145e9.1 for ; Fri, 21 Aug 2026 04:01:28 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.01.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:01:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310087; x=1787914887; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Vo9PbbbPqYN1Ef4Ej8cwJZ2Oz8N8SbnTX3lrcCjaQzQ=; b=skmfRxiHlpfER+/yM1Q7S7TeRFlgRjJbe77ovhqR4WABmsF1vQNgWcTyQccbThctSt RK5PW2lEQ0tK9PCdekvL8TrWTs1Ue/yVb/4inrPmyzlXaEr2fw3ZJ2JuQ/5PFEi2Of21 13Ni4Vzn8ufuQE7aMfjcJXxb3BFVOUYKcqHEn9KoOlHJqRgFGtVechMqvErqe3QLPvjL 3CmoxaXw87AP8mGcA+cW97z9rGFNEmeTVekEdKRi0jNMZ3OKWVuHVomT9RG1h5Mx1vD8 Erv/5SDxZcp+QwYe8UXdYVGcwGRK2hLKisBOhpxnJ3NinUpVFM2T2hY/MmO9PdPpaQdR KgTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310087; x=1787914887; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=Vo9PbbbPqYN1Ef4Ej8cwJZ2Oz8N8SbnTX3lrcCjaQzQ=; b=mKqBbQLyOyurA/dghZPX2I5aqXptYIdyu4HW2UVLcw2LVib5W/AIYwvHD4IQU7NugF 6DgHZI3BRslq7+b/bXj1NJCP7piBA+lJ5Ilk/G0CaSi1jul5B8NvGmj6QGq9zH1rBsPl 6nHLdDa4yzTzxBPG0ZpxhRwvdswlHo7JIs/AAsq0OeOgljOWyY5lVNIET39LEJSgAS6F ozLAXVRYRhTwCy0tPKucJAmQKn2jRgfv22AoYBrWu9Ooj+Ds0dRX2yGX7Nh8vPwTgtqW fDjggMFdIG+PTToMmRiCXE64XVZ46jCPpZ9qrc15KPgWIUgKMjNja104ORQnRw7eAFI9 2DDw== X-Gm-Message-State: AOJu0YzoR6Fur/botMECBTo4XXOrpebSeQfBZggpd0l0Zau2S9jM5zG6 KcV1OHVceqnFmIOLcLp/4H8FKsW+Bq5p9pJZ7Luxlsr40J2FB1OgshGz4Y5wsCXtHZkPO2VGHSn JYqnk X-Gm-Gg: AR+sD12gRTJEljctrgQfYhazcUNskyepgRQ5FC/1zxBVtwjOs/gvgf0UZEQ01F6gEVp ga1aqm2OgI62W+xJuNK4c+IftN8ifHWEsTlmWkjfed818+MlEyafsx9vQSUOrTxYnQqYKaH8vRY bs+fAmSpqfoTQFBfB14nlhdNtcDwEwbsdk8Mf609yFujo+saTmg+Gqwo1UEGEYK4pTiwJO2f1d5 hHZWXo08Q0N8iK1f4JuAto5Ib31uxY/gFGzElMjL6R2XPblFoQ61DpU+f2UDSCBIfLuqMFzRxKo +X2xNCaN7k3HZ7JLKnBkax1lZp/N9lNZMe/TEfT3TXKqS69YXCmpwk6RL46xUw5RbZTIGsoaqW5 fB/e8lKdwMKJ+e8OvxLUsWTJBi9LWZgo0eB1ppBlgu6FHe5h+k6+PBacKSrjFLs+ZAVnEkqS9w4 U83wNgLZZJ3N/BsJb8hXxlhD5Q+YUCmBlcSXqjAl82O/bJEakHKRBw3l1SCi73wwfNlEuV7DjtT 0o+JdrmlqzGthIYhpo5zXsTnvJml2VAW+yy+lQpMX5TInamQBrIzIPjwxwrM+lzA64ylw== X-Received: by 2002:a05:600c:64c6:b0:499:afcb:24c1 with SMTP id 5b1f17b1804b1-499b82e8528mr90396955e9.5.1787310073219; Fri, 21 Aug 2026 04:01:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/43] target/arm: Restrict arm_do_plugin_vcpu_discon_cb() to TCG Date: Fri, 21 Aug 2026 12:00:19 +0100 Message-ID: <20260821110101.3971391-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310144184158500 From: Philippe Mathieu-Daud=C3=A9 So far TCG plugins can only be used when TCG is available. Move the arm_do_plugin_vcpu_discon_cb() call within the 'if tcg_enabled' block and wrap the definition with #ifdef'ry. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Message-id: 20260814080507.23196-1-philmd@oss.qualcomm.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index af45234ad2a..adae2b2b8e5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8915,6 +8915,7 @@ static void take_aarch32_exception(CPUARMState *env, = int new_mode, } } =20 +#ifdef CONFIG_TCG void arm_do_plugin_vcpu_discon_cb(CPUState *cs, uint64_t from) { switch (cs->exception_index) { @@ -8932,6 +8933,7 @@ void arm_do_plugin_vcpu_discon_cb(CPUState *cs, uint6= 4_t from) qemu_plugin_vcpu_exception_cb(cs, from); } } +#endif =20 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) { @@ -9677,9 +9679,9 @@ void arm_cpu_do_interrupt(CPUState *cs) =20 if (tcg_enabled()) { cpu_set_interrupt(cs, CPU_INTERRUPT_EXITTB); - } =20 - arm_do_plugin_vcpu_discon_cb(cs, last_pc); + arm_do_plugin_vcpu_discon_cb(cs, last_pc); + } } #endif /* !CONFIG_USER_ONLY */ =20 --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310108; cv=none; d=zohomail.com; s=zohoarc; b=VbfKEN/CkFTYswYjAwZEf9fk9JuGz2VRN98kSSpXa8BKC7CgEcLt6t1PMywsrJMZweUJlzJBcoqxfn53s6dyKKRhw9wDs918HHVRb4E9E8M6viZhCBIX1ykKKQrp24iQuvEPtyp+vdHOQDQzyQbWxGIhWd5uvihLvN1BTe48vwI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310108; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=08MDgCUWYWGU9uq5tt94Th4yLxiaUJzZ7xRA/bIweYI=; b=ClxtQCfa3PetXDzR21pLSQDZPgLlDhY6y3ryzxjLS3H8Q8dUZA+BIAnrbgoD0XZXEO0BXb+BsM9L/AdZTVPLmqOPlRzuCFeFTDZ5tvMQAiNp8vw+RppTP7kt1GlpOm1yCJeACjuB12aaQ7gO4cYv2vYLDtAhfOwyNNdlVW2aPtQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178731010817563.827233679983124; Fri, 21 Aug 2026 04:01:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxMzz-0005yP-Gm; Fri, 21 Aug 2026 07:01:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMzw-0005xn-MW for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:20 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxMzv-0007Cc-0w for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:20 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4998590d392so7239265e9.0 for ; Fri, 21 Aug 2026 04:01:18 -0700 (PDT) Received: from lanath.. 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Cc: qemu-stable@nongnu.org Fixes: 39a8c3941e ("hw/intc/arm_gicv3: Fix ARM_GICV3 dependency for KVM / W= HPX") Signed-off-by: Richard Henderson Message-id: 20260812200308.289238-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 4373f16d0b3..0620b0792a1 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -48,7 +48,7 @@ specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: file= s('arm_gic_kvm.c')) specific_ss.add(when: ['CONFIG_WHPX', 'CONFIG_ARM_GICV3'], if_true: files(= 'arm_gicv3_whpx.c')) specific_ss.add(when: ['CONFIG_HVF', 'CONFIG_ARM_GICV3'], if_true: files('= arm_gicv3_hvf.c')) stub_ss.add(files('arm_gicv3_hvf_stub.c')) -specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'CONFIG_ARM_GICV3'], if_true:= files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) +specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gicv3_kvm.= c', 'arm_gicv3_its_kvm.c')) arm_common_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c')) --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310137; cv=none; d=zohomail.com; s=zohoarc; b=Sx0sqyl2oWAgfBerGj+gpbWJOyY7XK9xmMKQXlFP0vcBtsbpFIijXTy50wCwsY3fgyRgivKfj7xjgRsuU4W4F+U+fpJU4mlttYbEh5hkqtGJbLkjhFT6JTkXAE1VOXzJoglF6RfiNqvP6E8TO/FBWsUXBGuN0XjGMR4b6LTHosw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310137; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=QE965lMr/HTaAiZq82NVo2yDpUktkO6jaARbdLF3It8=; b=EooCOLKecY1eBRx3DBFsddwgSTGyH/5RxWpd+utkGe1b9zlUTdAqv0qCSGf0JfWTL6IIdp3XhbA6HYRHNt5IEeNNC6oXJoudswNphIQyALBu5ns/cUoZhzW0OuaXuJPhBXDz4FF5Broh0wDXWYOrV3Q8LsgmFx9vWNC7ZP+dCYI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310137476594.5177781895401; Fri, 21 Aug 2026 04:02:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN02-0005zi-7d; Fri, 21 Aug 2026 07:01:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN01-0005z8-6x for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:25 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxMzz-0007D7-QF for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:24 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-47fd4531020so509807f8f.3 for ; Fri, 21 Aug 2026 04:01:23 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.01.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:01:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310082; x=1787914882; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=QE965lMr/HTaAiZq82NVo2yDpUktkO6jaARbdLF3It8=; b=yeALE+Zv8G+0ixQ73k++cm9gpClnsYG7H6mkwC5DM7aKLPUF4ghGgOFRBTW9TA5BEI zL/bCW2XpV8VL7fMf0qzN7hXdPIpAkKcQYlDTp8KFxQ28Zl8eiDenEplVpHL31pieEva sD/Sh8uurR8GYJbU8w1E/KP4aLfbaAqF5jIj0zyNZkSon2EGOGO8xU4WjTb9fZL0/9N+ W1yTd9ggjK7jayxhZT7pQLd1dPXJch33iU/4OEznsmdeE349iR6ZR0njGJd4dKjBRkqv NgRtbFsN1eEhnpd4aCbMEdvKzl2m8yU50876N98TYu8Rx0SUd6OteSFE5tNvrf92V7JL dWIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310082; x=1787914882; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=QE965lMr/HTaAiZq82NVo2yDpUktkO6jaARbdLF3It8=; b=DBM6VO4+Epz0/+IPjUHOft2CUvSwD4vUd0/nAzbjgmRckcfrx66TQUgKnvBuGbmKY+ 4B6bhHipiQit8XIiKN05EFZC70ivH6hnJsWBQWu+YTf19VR6BbJWG9x89k3iosUB304o xZnyLq3POIoN1fyDJ9mrNUxnolGHOD4YqEBeknXH9LcYCe5dC0ubRuNL6mcNa1C9WAak 0cG9aR0b7cQ5+uYR6vkn7jac4wrgihd40Z3KePpdbRDLKXRlCoXZp8ZLU/0J5MngD7RU jb729v3N63obWD4bPrE75OqOUiYVK1DKLeyLy4AspTDcwlpxP7TeO0MYat2RvDOT9o9G 7xsw== X-Gm-Message-State: AOJu0Yz8Cvap8r82NTkj0h/qgn9J9rQuKCyKIQFV1GKoceWfGp33oPRp m+leIH875OmTkNqsLAhCTXL8tS+VNkXWOdT85vju6PEWBeYjv++EeUA89ebB0Zh3dCJDLrnaGSP zI/kB X-Gm-Gg: AR+sD10GhixjhoJ48xI9fZVwRVHdOyKQv3oKprszI1leq+0dHsNwWOkUm0lbaK0dMcD Rz1mgv6az6LdSTCLhxoSoEZtKriZ9pXiLlJKTmMNjKVPnonzPRiv3VxN+mGswNVXdVlhTHuvncX 3jZFSUA/l5MBIR9KqYUUOAS5nDzumNOJWkcvq2b+xTqjMO46i4ebkO+fUJNqrMeIr7F/HETKf/c EfOrbZ5B8YgDRgCuWT5ZEghKO7rZxYzQGAU6JCotULGTwStGgyWHCWc1uA6l1PQ7t15iF390Wcq D60pC+3unY12xG3TgllamknDEyB9xVKGWig+m8+HGS6NPCEu2G5yC5ot3F1hq4JAT5ljLrldwGX kMo0qpOAi15ElfaQ6jX/xhDxy0M88ErAsMhBeJLJ56hXm5We7jpXN2w3DmS6u/B5GvYnSYKlK1e pDA3KblvpbudFNPmNDPBniNU1WhyDF93I59l7Vjbma48ITNRLJ1CoBY4bLa0kKaOXXGqEEWO2cr zOc03lQNz9uAM44EzJGaUW5b5reKF53P/r3SYAVzxpTwAE/pdd9v+RNjl1M/yY08DEsQziGJaYs ZEE6 X-Received: by 2002:a05:600c:c16f:b0:493:a623:d090 with SMTP id 5b1f17b1804b1-499b82e894emr82738655e9.10.1787310082219; Fri, 21 Aug 2026 04:01:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/43] hw/intc/arm_gicv3: Have GIC kconfig select GICv3 for HVF and WHPX Date: Fri, 21 Aug 2026 12:00:21 +0100 Message-ID: <20260821110101.3971391-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310138089158500 From: Philippe Mathieu-Daud=C3=A9 While trying to fix the GICv3 dependency on KVM and WHPX in commit 39a8c3941eb, we missed the Kconfig ARM_GIC symbol only selects GICv3 for TCG, not HVF and WHPX. Fix that. Cc: qemu-stable@nongnu.org Fixes: 39a8c3941eb ("hw/intc/arm_gicv3: Fix ARM_GICV3 dependency for KVM / = WHPX") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260812220816.94034-1-philmd@oss.qualcomm.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 097de4efc5d..05e697967d0 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -26,7 +26,7 @@ config APIC =20 config ARM_GIC bool - select ARM_GICV3 if TCG + select ARM_GICV3 if TCG || HVF || WHPX select ARM_GIC_KVM if KVM select MSI_NONBROKEN =20 --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310121; cv=none; d=zohomail.com; s=zohoarc; b=hGJ7EmLz6QNYwPjSf8ftNHyWqj4Jtya8r1iKFpxdworwWY+Sz2nNG35O944C0eJNMwnrNf1nbcb4g82EToPI9iqIJKf+RdC+AMb/eZZyA9aGeGxUvmYq81UrEiUT0c8UqiIe+xGQ+38OwGKbyEIwfq49LOHUCH+5AGFBg03qCDQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310121; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=M8ntjgm7jIcw+9TY3XDn9SgfpMJGB29k63pL7C9Qq9o=; b=OpBXFN34BXUFptZyg49NeyOF+uol+DPCd10bamIlK7NkltrErr1I8hhgAqKydgAlCel7SBN2Xfwi9N+SkHs+yM7Oe8S2oybbf3594qP07tmUCC2P1OfCk6d0mLsQbe8x/IpAnlYFL1QEmdKakPkO4KSToSWEE8uCL4q3Tejzz9I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310121305658.5629652356506; Fri, 21 Aug 2026 04:02:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN0J-00061X-JT; Fri, 21 Aug 2026 07:01:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN04-00060V-My for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:29 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN03-0007DN-2E for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:28 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-495437bb891so4354105e9.1 for ; Fri, 21 Aug 2026 04:01:26 -0700 (PDT) Received: from lanath.. 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Separate tcg from qtest initialization. Remove an assert on aarch64_enabled that is directly protected by a preceding if. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260812204435.295067-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-max.c | 39 +++++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 88b7c046333..0a310d1b15d 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -203,29 +203,32 @@ static void cpu_max_initfn(Object *obj) return; } =20 - if (tcg_enabled() || qtest_enabled()) { - aarch64_aa32_a57_init(obj, !aarch64_enabled); - } - - if (!aarch64_enabled) { - aa32_max_features(cpu); -#ifdef CONFIG_USER_ONLY - /* - * Break with true ARMv8 and add back old-style VFP short-vector - * support. Only do this for user-mode, where -cpu max is the defa= ult, - * so that older v6 and v7 programs are more likely to work without - * adjustment. - */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); -#endif - } else if (tcg_enabled()) { - assert(aarch64_enabled); + if (tcg_enabled()) { /* * '-cpu max' for TCG: we currently do this as * "A57 with extra things" */ - aarch64_max_tcg_initfn(obj); + aarch64_aa32_a57_init(obj, !aarch64_enabled); + if (!aarch64_enabled) { + aa32_max_features(cpu); +#ifdef CONFIG_USER_ONLY + /* + * Break with true ARMv8 and add back old-style VFP short-vect= or + * support. Only do this for user-mode, where -cpu max is the = default, + * so that older v6 and v7 programs are more likely to work wi= thout + * adjustment. + */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC= , 1); +#endif + } else { + aarch64_max_tcg_initfn(obj); + } + return; } + + /* Ultimate fallback: -cpu max as cortex-a57. */ + assert(qtest_enabled()); + aarch64_aa32_a57_init(obj, !aarch64_enabled); } =20 static const ARMCPUInfo arm_max_cpu =3D { --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310122; cv=none; d=zohomail.com; s=zohoarc; b=ginJ/4pD30J7JFpKy+mYrKRJlArEM1sl/VuFtwgy9evrS7nXdZOgY1zMHkUjpqhTlzHQE6RZsKj32PGSnB4iRZMwyjGsH0OASsMFoT/b9Jlnzj6e7E+jLoGek2tGkdahiod/1px+09CPGqGW+VvUBeh5XiX2/m0PmSz5UMaFzBg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310122; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=zATQX0WfZw8uVd/tDh0GkOsMfEIq683ZB8385k60BBE=; b=Ozy8lzVDW4eCVUL4An1O4LrkOVUW7ULKh7MZS94HJwMUO2eTUucymff6pmCLHyoZMiiLTV0dIIk9cRMDLuatNfKjEKF6/S49UZ8L9kOJCXrOpk2EXmxF1fCCoUeY/yzkqiW5BOpXPbIcDqZVt5d4xLJAArnZE6BnXJaGJZL3M14= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310122183885.6309034630768; Fri, 21 Aug 2026 04:02:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN0M-00068C-OY; Fri, 21 Aug 2026 07:01:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN08-00061b-19 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:39 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN06-0007Eh-FF for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:31 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4921eed3fa2so7633065e9.0 for ; Fri, 21 Aug 2026 04:01:30 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.01.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:01:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310089; x=1787914889; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=zATQX0WfZw8uVd/tDh0GkOsMfEIq683ZB8385k60BBE=; b=Y24moYCCTPkdzV3HzoZq9hFBW/QKOdsiC6QHA3sbSHqgqaWL8VfI+RiRfiv3Rcbl5R nT3iHjhW/IHS5Vl2IJhuAe8Tl3jRsN+3n8VR+tOagj3KzSOISaJ/AM2GK34QDT91qasx K4qMH6f8uTeKQvsiRWo/fyQx1N7oY0u9y7DaLzfMJLac2xVxi75FNfQkwnzcHexoavfO 6OUwkZARoz4/T5U4T15DQ+CmKjM+OiN1gUYBF+FM0tIghNUkCVZEvCoI4hABJK4CPvSj ppuJEL0wLSaQkezZZL0Ua82XLOvU972R9lfUxKHcPnCGh+jeL2BROqgtFOg3KAZQC8jL 3A5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310089; x=1787914889; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=zATQX0WfZw8uVd/tDh0GkOsMfEIq683ZB8385k60BBE=; b=XsIEAs5xojYYJ77m9xGc1wkRKguSc38iEJ8VJPwUqczj53RjFTZdfxtDYyZSuYiYCd ex53+R4cv+vtt4J78q6BxqqBNhatA25gvnmb+t50XrXphyZYxUadV8llqE3okDK9RF7P T9ZGoW2pxIW+Px9Sgkvhj5icdwSHX7ktI9hdb9XsKVF8LJW/OoEeFhJ1JuPrnIMkwx3N 9uamlAUBCq2y64wnITptqbvzt5RwpacSDdeQ3sFFztdghTJpf7BJRA3+FLUXjyu/QrjV PefkOz0pcZ+bP9BUF367FIWkwhUO5DJlT3bIIJ1yhBdNrVxVgwDGsJq+b+EQCPwvXyrJ 6zJw== X-Gm-Message-State: AOJu0YwwQ9I7OJuE/V6CC6M5fD8S01kcnCmlP2kkqYx6o5vb0UCuYIY+ 2iRAgUvG1VVZ9yH0Yw7wqxRTGFwN9HBbUHHBOj1/Ln5VANtNaQroPFZIdW3N8bUVIlSJjOmeqmh icIeQ X-Gm-Gg: AR+sD13OF9b5Mlb+tFhfv5K5swr77+tJix0zS58upmzm4Lf2D6YzhXeyS0lJW8b5Zdd idI+iAxZHdaeKtGYb5tEqcE5bIG+ODXGQum5UznwiErtVL8ZMlzWAg7TFrJxyjahXEO1gMvoOGZ mJkV6lfXkeBAbt/qqrSE3NpRljfuw44Bla8ZNdAE4n2aWaExF/ZzcohNgEaR22B512QUWwW55Hl 9gygD2nqVGa0DUXmd3KkP0dTCDGNbz2sGUemey2iy+LINF+tH3Jo4ABvL16VgVzo1ifHpof4vJ7 oof0t7NGn9Izp2h72az/3os6PwLdGrCOijDEda4h9UoFTj93B3e+AKjhfl145zDKQNiDsac2syE t1uzipjrM0XyBAyaCW4Q9JO+1mhG/v+uWmfCQC4t0rKwnobedT4dQq3UEMn/VJhK0t0lFaIGEfY pUpmJPGcxErLKxC3Oqx+g7kNmdJeuwCVi4wfPBfAMYhI1zrEM01h5Z9mY1O/9j2bIUPDhL+bbxY EWKZ1MboC/6q0oG0Yg/Nl5iurZWbPqoZ4hfM7LipZl/TzTF6YhazVs= X-Received: by 2002:a05:600c:5486:b0:499:a277:e8c8 with SMTP id 5b1f17b1804b1-499b8464cb8mr70840965e9.13.1787310088910; Fri, 21 Aug 2026 04:01:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/43] target/arm: Pass ARMCPU to aarch64_aa32_a57_init Date: Fri, 21 Aug 2026 12:00:23 +0100 Message-ID: <20260821110101.3971391-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310124145158500 From: Richard Henderson There's no reason to pass Object when ARMCPU is more appropriate. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-id: 20260812204435.295067-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu-max.c | 7 +++---- target/arm/cpu64.c | 2 +- target/arm/internals.h | 2 +- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 0a310d1b15d..bd858f010cd 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -16,9 +16,8 @@ #include "target/arm/internals.h" #include "target/arm/cpregs.h" =20 -void aarch64_aa32_a57_init(Object *obj, bool aa32_only) +void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa32_only) { - ARMCPU *cpu =3D ARM_CPU(obj); ARMISARegisters *isar =3D &cpu->isar; const bool aarch64_enabled =3D !aa32_only; =20 @@ -208,7 +207,7 @@ static void cpu_max_initfn(Object *obj) * '-cpu max' for TCG: we currently do this as * "A57 with extra things" */ - aarch64_aa32_a57_init(obj, !aarch64_enabled); + aarch64_aa32_a57_init(cpu, !aarch64_enabled); if (!aarch64_enabled) { aa32_max_features(cpu); #ifdef CONFIG_USER_ONLY @@ -228,7 +227,7 @@ static void cpu_max_initfn(Object *obj) =20 /* Ultimate fallback: -cpu max as cortex-a57. */ assert(qtest_enabled()); - aarch64_aa32_a57_init(obj, !aarch64_enabled); + aarch64_aa32_a57_init(cpu, !aarch64_enabled); } =20 static const ARMCPUInfo arm_max_cpu =3D { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 28167355773..e3ee0253a09 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -688,7 +688,7 @@ void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **err= p) =20 static void aarch64_a57_initfn(Object *obj) { - aarch64_aa32_a57_init(obj, false); + aarch64_aa32_a57_init(ARM_CPU(obj), false); } =20 static void aarch64_a53_initfn(Object *obj) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4026f67579e..9c9196475bd 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1813,7 +1813,7 @@ void aarch64_max_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); -void aarch64_aa32_a57_init(Object *obj, bool aa32_only); +void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa32_only); void aarch64_host_initfn(Object *obj); =20 /* Return true if the gdbstub is presenting an AArch64 CPU */ --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310187; cv=none; d=zohomail.com; s=zohoarc; b=WHYCYLeRa5rdRzmvMiaVyMxgsIGYY/U5pLk8jaPI9UDiFW466/+JwuN57ehvIC9mUj6o9Ddvyvzpuy7Mchb/E9x30kheokJvZaOnJHABmTos4yzyyPO0jhiHGSMtoBHCumbXmjgj2Zler4s6pd/rQyt+XKMppucLEiEMNPH0xuo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310187; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=xsRT6OD4srdGJd/K1CS+c7IiUzkXHHJdkUb3E/3eSzY=; b=bsl5H3MSu73B42Ml5Z5L/redPihk1eZUnmqpUBGwBGHCoH4Ptpd+RCO/GTaXQIWU8ZuphbLlT0R4q1Qy2cMJ+JgZDWgTT/3pFpzUzb3maPD2CKhYPHI8c0iStDKPwLBKtv9UqxABP566fS4YBI7evI1zPrvYlF7Q0qwd6MkNTEg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310186946298.45813075931915; Fri, 21 Aug 2026 04:03:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN0M-00064n-5M; Fri, 21 Aug 2026 07:01:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN0F-00062P-8a for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:43 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN09-0007FO-Uh for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:39 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-49954b88fffso7245975e9.0 for ; Fri, 21 Aug 2026 04:01:33 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.01.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:01:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310092; x=1787914892; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=xsRT6OD4srdGJd/K1CS+c7IiUzkXHHJdkUb3E/3eSzY=; b=ZxYMfs8/2AYHIwT9jSjn6DZbfSD9pQEfc/8Zs5qRjF2YXBYpbNV/1OrHbzkry4q6TY FuGXdshmGYyfvPPtw5x/Mf+nfrC3CZoJstSKHYjzty7S4r2LX0cbPccWTwQtBg52n3w9 77Z65jxOOfu4sfWXyU3UCtafziDIll0QnvOmUAdjJ/YjQtK6+J0NCL2sFTPZ409bxHEV FjGEqFiSvYEWrz/dBupNZzEf+SgvSUtD0qjrgiwEgF/IBvYydS7EWm99glZJ5rwzVlqm 5OwUq1wEgNd0ue7criy4Owu1zRa7TdTXygngOVxV3L978nQKfNmFKY0JzaXYgHh3rS5k DNAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310092; x=1787914892; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=xsRT6OD4srdGJd/K1CS+c7IiUzkXHHJdkUb3E/3eSzY=; b=US0hyIP6x4JHgtuAxsAHdwXautyNtq5JK1nn7iDOL68G0kWyoU137Oz2zuVcUaHwud WhGMfe9fpycjPZ996xR2SdETo4z4RJOw34bWxvJoAFehQGTqIyqh+egUUu7NbwrUFpPi DQ3lWhSO1SbCNjHh5jpici5zVgljn0nrHtCFjOc9STlOM06/FS4VuwT56pZkFWMZEEku 2mZAYWsMStsnWBIC4OmqQESyspAqHdt7a/zPJ3FWoJJ+GHIzIWmsXty3S3HHnkxZXqAa 3fBhmh+O7mk34u3NyGF0KIgj79laxn45odXa2s/YR7BMLFy9S0Ixeq4cx1iW/j89Tzzs pPFA== X-Gm-Message-State: AOJu0Yw8LZwIzRQu36fZfSawAHgB7dsHKYFRHMEWo9u0zmLV2n1kvuf5 ilyT5yOew8JDWDKhmF+b4goW/RbIhup7FMv3ycfO/cnh0bJ/lyS7nY1bgDbcT7iHoKy9wN5Bsi4 3f1Oo X-Gm-Gg: AR+sD10KsJc8xzN/pbODTYKg9rp/cYSBDmIUOBLsYoXjAjL0DxYe7g/8iiycsBsXHc0 akH1tqaNdfGSJ248e3z26C6v0wszjDXpSJJxMgPiue5I6kqJgDCEVJ8tsvhm5P4H0hgkw0tD+rX B+ZjP+0dSFFp2roB+ckKIJ8bTuMmJRbhw4rKo9DtGEj+xlq7sPRSB84HzH76eufUPgTOfdQGBo8 viAgCZv/S6sMm5SpP5lbRYDkj/iEnhTiWizoWDh/F8GQIUhA3awIWQxf8jfbarZgsLu2kRhr7MX CQRV47C1ZGc09c2c6yymc/nXVLOHsRUJ0K0/B3MLDt5El9Rzcnmkxg45A0G5k5qxnYAYaiOXof0 X8dZg+yKa2PT/slVtTPN/o2K/2s1vZRrcGxk9osh68ZLubaHplBBOW4UbOKRPub8s9oCFAhemy0 hoYiAnAMZTWJTLdkANhnrFJKaqQt/AvzVPNkJeqFBP7NA2LXFfeVVYxFB20wmJttQBcnll4T/qa Zn7qfzBSHcvGl2KvWgwQ27q72O4PySqa9+uHo1mm+gb/yLTbZZTBbym00jeywwTE08l9w== X-Received: by 2002:a05:600c:8108:b0:493:a966:d5b5 with SMTP id 5b1f17b1804b1-499b82f40b6mr88299185e9.2.1787310092503; Fri, 21 Aug 2026 04:01:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/43] target/arm: Pass aarch64_enabled to aarch64_aa32_a57_init Date: Fri, 21 Aug 2026 12:00:24 +0100 Message-ID: <20260821110101.3971391-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310188474158500 From: Richard Henderson Invert aa32_only argument to what is actually used. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-id: 20260812204435.295067-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu-max.c | 7 +++---- target/arm/cpu64.c | 2 +- target/arm/internals.h | 2 +- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index bd858f010cd..edb5b9e6c36 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -16,10 +16,9 @@ #include "target/arm/internals.h" #include "target/arm/cpregs.h" =20 -void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa32_only) +void aarch64_aa32_a57_init(ARMCPU *cpu, bool aarch64_enabled) { ARMISARegisters *isar =3D &cpu->isar; - const bool aarch64_enabled =3D !aa32_only; =20 cpu->dtb_compatible =3D "arm,cortex-a57"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -207,7 +206,7 @@ static void cpu_max_initfn(Object *obj) * '-cpu max' for TCG: we currently do this as * "A57 with extra things" */ - aarch64_aa32_a57_init(cpu, !aarch64_enabled); + aarch64_aa32_a57_init(cpu, aarch64_enabled); if (!aarch64_enabled) { aa32_max_features(cpu); #ifdef CONFIG_USER_ONLY @@ -227,7 +226,7 @@ static void cpu_max_initfn(Object *obj) =20 /* Ultimate fallback: -cpu max as cortex-a57. */ assert(qtest_enabled()); - aarch64_aa32_a57_init(cpu, !aarch64_enabled); + aarch64_aa32_a57_init(cpu, aarch64_enabled); } =20 static const ARMCPUInfo arm_max_cpu =3D { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e3ee0253a09..faaf3ab879d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -688,7 +688,7 @@ void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **err= p) =20 static void aarch64_a57_initfn(Object *obj) { - aarch64_aa32_a57_init(ARM_CPU(obj), false); + aarch64_aa32_a57_init(ARM_CPU(obj), true); } =20 static void aarch64_a53_initfn(Object *obj) diff --git a/target/arm/internals.h b/target/arm/internals.h index 9c9196475bd..5e7f41a50d1 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1813,7 +1813,7 @@ void aarch64_max_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); -void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa32_only); +void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa64_enabled); void aarch64_host_initfn(Object *obj); =20 /* Return true if the gdbstub is presenting an AArch64 CPU */ --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310136; cv=none; d=zohomail.com; s=zohoarc; b=Xc8AbN37zGeng7tIJSAC92B81FAr+PKxQv2fbM1JqcR3H/gYPXfBHemF3rH3urrtqWPPrtMYUe62Tlnb9DX03/ADeVe91/IR0Ou9Hfu9RbRgrT4HUdOsJH2LOtu88TAY96uL8uIIlC2DDFnxWABVpIRsdEs6Pvw24WNFCwh4HTY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310136; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=8g5mM9Q649/0dlg8XApcPPU1rZYvV51fpODLqJsuqBE=; b=hQQiyJoY4e6k/s6IS6gYZYw8gcDQuBk/uNq6mnDsz7NIlBuBnYocPqH6LzRJMRYZMPXFSV8TavWcNRydKl5FqnwMUXc90fbdUpKZDYYZZK3k85qNFaSqG3hJL/fCyH7Jhgd459kjj/ze1jNLhHf9+krpY2lDqKacYDVJBhm42V8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310136693827.9299355583707; Fri, 21 Aug 2026 04:02:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN0L-00064T-29; Fri, 21 Aug 2026 07:01:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN0H-00062a-D5 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:43 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN0F-0007Fz-Mc for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:41 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4980fe6b3beso15554105e9.0 for ; Fri, 21 Aug 2026 04:01:39 -0700 (PDT) Received: from lanath.. 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Fri, 21 Aug 2026 04:01:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/43] target/arm: Sink aarch64_aa32_a57_init into aarch64_max_tcg_initfn Date: Fri, 21 Aug 2026 12:00:25 +0100 Message-ID: <20260821110101.3971391-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310138106158500 From: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-id: 20260812204435.295067-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-max.c | 2 +- target/arm/tcg/cpu64.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index edb5b9e6c36..93f24114a52 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -206,8 +206,8 @@ static void cpu_max_initfn(Object *obj) * '-cpu max' for TCG: we currently do this as * "A57 with extra things" */ - aarch64_aa32_a57_init(cpu, aarch64_enabled); if (!aarch64_enabled) { + aarch64_aa32_a57_init(cpu, false); aa32_max_features(cpu); #ifdef CONFIG_USER_ONLY /* diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 24f34947eca..5649b853a7f 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1167,6 +1167,8 @@ void aarch64_max_tcg_initfn(Object *obj) uint64_t t; uint32_t u; =20 + aarch64_aa32_a57_init(cpu, true); + SET_IDREG(isar, CLIDR, 0x8200123); /* 64KB L1 dcache */ cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 7); --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310127; cv=none; d=zohomail.com; s=zohoarc; b=ZYI+sgdyOnxkhZHOZvIrT64hKTi+e0ja8j5MCwtFOsm2cRdt+AQn2qNYA2y03dNNJiZDnHkUD8NnH/K1lBVudHrD1MkofDlvGGm45+sk3LBirhwUS3HFBJPCq5WwAY95lAKpnWzF6Cbw9xl1LtK6jEYp51+fzvRACoEfnx1c5So= ARC-Message-Signature: i=1; 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Only do this for user-mode, where -cpu max is the = default, - * so that older v6 and v7 programs are more likely to work wi= thout - * adjustment. - */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC= , 1); -#endif + aarch32_max_tcg_init(cpu); } else { aarch64_max_tcg_initfn(obj); } diff --git a/target/arm/internals.h b/target/arm/internals.h index 5e7f41a50d1..f6b4e173a54 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1838,6 +1838,7 @@ uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool s= ecure, bool el_is_in_host(CPUARMState *env, int el); =20 void aa32_max_features(ARMCPU *cpu); +void aarch32_max_tcg_init(ARMCPU *cpu); int exception_target_el(CPUARMState *env); bool arm_singlestep_active(CPUARMState *env); bool arm_generate_debug_exceptions(CPUARMState *env); diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 8220d785f5b..e1ff074b470 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -748,3 +748,18 @@ static void arm_tcg_cpu_register_types(void) type_init(arm_tcg_cpu_register_types) =20 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ + +void aarch32_max_tcg_init(ARMCPU *cpu) +{ + aarch64_aa32_a57_init(cpu, false); + aa32_max_features(cpu); +#ifdef CONFIG_USER_ONLY + /* + * Break with true ARMv8 and add back old-style VFP short-vector + * support. Only do this for user-mode, where -cpu max is the default, + * so that older v6 and v7 programs are more likely to work without + * adjustment. + */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); +#endif +} --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310195; cv=none; d=zohomail.com; s=zohoarc; b=g+zglTmQ2/YMV+cKujWm/uXBNhbVQbgBpYNU+EJhO20/Kr3Ag1P7S0COJGlK6McineL69qnopqBw+2rEmbNyMIHehNs6azL/DX198HuZirZE7AP8uLkBO9bkw0UYetWUWYVta4jNXK8diCZI6kfv5mRGv8EwW2QswOM14hjkl3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310195; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=dO/6qESwbaAHk5GdWX7bdtKkcFwdVVLqAXUMZycPk2w=; b=ewQU1gASnjYMlbtjt9cbXHr0vrpGP8bDksts8tAF7RBYzMJ9GZeHXfBh9pbC0j5uqm4fmev4s7n131EP/tGCYaSVFSwtq4aQvx5I4aM6SVqP4rzcBaekSH+mskQjzj+VBQNwuPtHx+Y/sr/mPryVItcnsJyqg0NgXMQ8E8gEiZk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310195491269.44970674916067; Fri, 21 Aug 2026 04:03:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN0P-0006Cb-9U; Fri, 21 Aug 2026 07:01:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN0M-00068X-UR for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:46 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN0K-0007Gx-Ms for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:46 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-49556f97a9dso4656395e9.1 for ; Fri, 21 Aug 2026 04:01:44 -0700 (PDT) Received: from lanath.. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260812204435.295067-7-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu-max.c | 96 ------------------------------------------ target/arm/tcg/cpu32.c | 96 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+), 96 deletions(-) diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 7df7d015a91..8d968336a8b 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -85,102 +85,6 @@ void aarch64_aa32_a57_init(ARMCPU *cpu, bool aarch64_en= abled) define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 -/* Share AArch32 -cpu max features with AArch64. */ -void aa32_max_features(ARMCPU *cpu) -{ - uint32_t t; - ARMISARegisters *isar =3D &cpu->isar; - - /* Add additional features supported by QEMU */ - t =3D GET_IDREG(isar, ID_ISAR5); - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ - SET_IDREG(isar, ID_ISAR5, t); - - t =3D GET_IDREG(isar, ID_ISAR6); - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ - SET_IDREG(isar, ID_ISAR6, t); - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ - - t =3D GET_IDREG(isar, ID_MMFR4); - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ - t =3D FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */ - SET_IDREG(isar, ID_MMFR4, t); - - FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ - - t =3D GET_IDREG(isar, ID_PFR0); - t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ - SET_IDREG(isar, ID_PFR0, t); - - t =3D GET_IDREG(isar, ID_PFR2); - t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ - SET_IDREG(isar, ID_PFR2, t); - - t =3D GET_IDREG(isar, ID_DFR0); - t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ - SET_IDREG(isar, ID_DFR0, t); - - /* Debug ID registers. */ - - /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ - t =3D 0x00008000; - t =3D FIELD_DP32(t, DBGDIDR, SE_IMP, 1); - t =3D FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); - t =3D FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); - t =3D FIELD_DP32(t, DBGDIDR, BRPS, 5); - t =3D FIELD_DP32(t, DBGDIDR, WRPS, 3); - cpu->isar.dbgdidr =3D t; - - t =3D 0; - t =3D FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); - t =3D FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); - t =3D FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); - t =3D FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); - t =3D FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); - t =3D FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); - t =3D FIELD_DP32(t, DBGDEVID, AUXREGS, 0); - t =3D FIELD_DP32(t, DBGDEVID, CIDMASK, 0); - cpu->isar.dbgdevid =3D t; - - /* Bits[31:4] are RES0. */ - t =3D 0; - t =3D FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); - cpu->isar.dbgdevid1 =3D t; - - FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ -} - /* * -cpu max: a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index e1ff074b470..d5dd2361528 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -749,6 +749,102 @@ type_init(arm_tcg_cpu_register_types) =20 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ =20 +/* Share AArch32 -cpu max features with AArch64. */ +void aa32_max_features(ARMCPU *cpu) +{ + uint32_t t; + ARMISARegisters *isar =3D &cpu->isar; + + /* Add additional features supported by QEMU */ + t =3D GET_IDREG(isar, ID_ISAR5); + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ + SET_IDREG(isar, ID_ISAR5, t); + + t =3D GET_IDREG(isar, ID_ISAR6); + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ + SET_IDREG(isar, ID_ISAR6, t); + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ + + t =3D GET_IDREG(isar, ID_MMFR4); + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ + t =3D FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */ + SET_IDREG(isar, ID_MMFR4, t); + + FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ + + t =3D GET_IDREG(isar, ID_PFR0); + t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ + SET_IDREG(isar, ID_PFR0, t); + + t =3D GET_IDREG(isar, ID_PFR2); + t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ + SET_IDREG(isar, ID_PFR2, t); + + t =3D GET_IDREG(isar, ID_DFR0); + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ + SET_IDREG(isar, ID_DFR0, t); + + /* Debug ID registers. */ + + /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ + t =3D 0x00008000; + t =3D FIELD_DP32(t, DBGDIDR, SE_IMP, 1); + t =3D FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); + t =3D FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ + t =3D FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); + t =3D FIELD_DP32(t, DBGDIDR, BRPS, 5); + t =3D FIELD_DP32(t, DBGDIDR, WRPS, 3); + cpu->isar.dbgdidr =3D t; + + t =3D 0; + t =3D FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); + t =3D FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); + t =3D FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); + t =3D FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); + t =3D FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); + t =3D FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); + t =3D FIELD_DP32(t, DBGDEVID, AUXREGS, 0); + t =3D FIELD_DP32(t, DBGDEVID, CIDMASK, 0); + cpu->isar.dbgdevid =3D t; + + /* Bits[31:4] are RES0. */ + t =3D 0; + t =3D FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); + cpu->isar.dbgdevid1 =3D t; + + FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ +} + void aarch32_max_tcg_init(ARMCPU *cpu) { aarch64_aa32_a57_init(cpu, false); --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310352; cv=none; d=zohomail.com; s=zohoarc; b=ekJR9hif9RW/w8fe3Xy0dqotRMm4aqwdAOycOKKwUA6OGYZ1jKAhKDzKjeTz5fzSTb/7126DMTdEQEaCeo5PL1PJ3bY3oDH5EgTDC60XefsnuqZq9qQ//3nYFzvFztb98AhV25UCJomO1cJM+kds9dUdfxuOoqlJwNn/rY9SjFw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310352; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Modulo some sorting of properties at the end, comment changes only. Signed-off-by: Richard Henderson Message-id: 20260812204435.295067-10-richard.henderson@linaro.org [PMM: fixed two minor comment issues] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/cpu64.c | 303 +++++++++++++++++++++-------------------- 1 file changed, 159 insertions(+), 144 deletions(-) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 5649b853a7f..9ce514dda81 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1226,199 +1226,202 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, CTR_EL0, DIC, 1); cpu->ctr =3D t; =20 + /* + * Below, note the revision from which the feature is OPTIONAL. + */ t =3D GET_IDREG(isar, ID_AA64ISAR0); - t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 3); /* FEAT_LSE, FEAT_LSE1= 28 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* v8.0: FEAT_PMULL */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* v8.0: FEAT_SHA1 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* v8.1: FEAT_SHA512 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* v8.0: FEAT_CRC32 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 3); /* v9.3: FEAT_LSE128 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* v8.0: FEAT_RDM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* v8.1: FEAT_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* v8.1: FEAT_SM3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* v8.1: FEAT_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* v8.1: FEAT_DotProd = */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* v8.1: FEAT_FHM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.4: FEAT_FlagM2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* v8.3: FEAT_TLBIRANG= E */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* v8.4: FEAT_RNG */ SET_IDREG(isar, ID_AA64ISAR0, t); =20 t =3D GET_IDREG(isar, ID_AA64ISAR1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED); + t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* v8.1: FEAT_DPB2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED); /* v8.= 2 */ t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF= 16 */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* v8.2: FEAT_JSCVT */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* v8.2: FEAT_FCMA */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* v8.2: FEAT_LRCPC2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* v8.4: FEAT_FRINTTS = */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* v8.0: FEAT_SB */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* v8.0: FEAT_SPECRES = */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* v8.2: FEAT_EBF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* v8.0: FEAT_DGH */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* v8.1: FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* v8.6: FEAT_XS */ SET_IDREG(isar, ID_AA64ISAR1, t); =20 t =3D GET_IDREG(isar, ID_AA64ISAR2); - t =3D FIELD_DP64(t, ID_AA64ISAR2, RPRES, 1); /* FEAT_RPRES */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* FEAT_CSSC, FEAT_CMP= BR */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* FEAT_LUT */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* FEAT_ATS1A */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, RPRES, 1); /* v8.6: FEAT_RPRES */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* v8.7: FEAT_MOPS */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* v8.7: FEAT_HBC */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* v8.6: FEAT_WFxT */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* v9.3: FEAT_CMPBR */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* v9.2: FEAT_LUT */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* v8.8: FEAT_ATS1A */ SET_IDREG(isar, ID_AA64ISAR2, t); =20 t =3D GET_IDREG(isar, ID_AA64ISAR3); - t =3D FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* FEAT_FAMINMAX */ - t =3D FIELD_DP64(t, ID_AA64ISAR3, FPRCVT, 1); /* FEAT_FPRCVT */ + t =3D FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* v9.2: FEAT_FAMINMAX= */ + t =3D FIELD_DP64(t, ID_AA64ISAR3, FPRCVT, 1); /* v9.5: FEAT_FPRCVT */ SET_IDREG(isar, ID_AA64ISAR3, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR0); - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ - t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* v8.2: FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* v8.2: FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* v8.3: FEAT_DoubleFa= ult */ + t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); /* v8.2: FEAT_SVE */ + t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* v8.3: FEAT_SEL2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* v8.3: FEAT_DIT */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* v8.0: FEAT_CSV2_3 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* v8.0: FEAT_CSV3 */ SET_IDREG(isar, ID_AA64PFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR1); - t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ - t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* v8.4: FEAT_BTI */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* v8.0: FEAT_SSBS2 */ /* * Begin with full support for MTE. This will be downgraded to MTE=3D0 * during realize if the board provides no tag memory, much like * we do for EL2 with the virtualization=3Don property. */ - t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ - t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ - t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* FEAT_SME2 */ - t =3D FIELD_DP64(t, ID_AA64PFR1, RNDR_TRAP, 1); /* FEAT_RNG_TRAP */ - t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */ - t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ - t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* FEAT_GCS */ - /* FEAT_MTE_NO_ADDRESS_TAGS + FEAT_MTE_CANONICAL_TAGS */ + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* v8.5: FEAT_MTE3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* v8.3: FEAT_DoubleFa= ult */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* v9.2: FEAT_SME2 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, RNDR_TRAP, 1); /* v8.4: FEAT_RNG_TRAP= */ + t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* v8.0: FEAT_CSV2_3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* v8.7: FEAT_NMI */ + t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* v9.3: FEAT_GCS */ + /* v8.7: FEAT_MTE_NO_ADDRESS_TAGS + FEAT_MTE_CANONICAL_TAGS */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTEX, 1); SET_IDREG(isar, ID_AA64PFR1, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR2); - t =3D FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* FEAT_FPMR */ - t =3D FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 1); /* FEAT_MTE_TAGGED_FAR= */ - t =3D FIELD_DP64(t, ID_AA64PFR2, MTESTOREONLY, 1); /* FEAT_MTE_STORE= _ONLY */ - t =3D FIELD_DP64(t, ID_AA64PFR2, MTEPERM, 1); /* FEAT_MTE_PERM */ + t =3D FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* v9.2: FEAT_FPMR */ + t =3D FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 1); /* v8.7: FEAT_MTE_TAGG= ED_FAR */ + t =3D FIELD_DP64(t, ID_AA64PFR2, MTESTOREONLY, 1); /* v8.7: FEAT_MTE_S= TORE_ONLY */ + t =3D FIELD_DP64(t, ID_AA64PFR2, MTEPERM, 1); /* v8.7: FEAT_MTE_PERM= */ SET_IDREG(isar, ID_AA64PFR2, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR0); - t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supporte= d */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 support= ed */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 support= ed */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 support= ed */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* v8.1: FEAT_LPA: 52 = bits */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* v8.0: FEAT_TGran16= K */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* v8.0: FEAT_S2TGran= 16K */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* v8.0: FEAT_S2TGran= 64K */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* v8.0: FEAT_S2TGran= 4K */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* v8.5: FEAT_FGT */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* v8.5: FEAT_ECV_POFF= */ SET_IDREG(isar, ID_AA64MMFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* FEAT_ETS2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, AFP, 1); /* FEAT_AFP */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, CMOW, 1); /* FEAT_CMOW */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* v8.0: FEAT_HAFDBS */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* v8.0: FEAT_VMID16 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* v8.0: FEAT_VHE */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* v8.1: FEAT_HPDS2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* v8.0: FEAT_LOR */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* v8.1: FEAT_PAN3 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* v8.1: FEAT_XNX */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* v8.0: FEAT_ETS2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* v8.6: FEAT_HCX */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, AFP, 1); /* v8.6: FEAT_AFP */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* v8.7: FEAT_TIDCP1 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, CMOW, 1); /* v8.7: FEAT_CMOW */ SET_IDREG(isar, ID_AA64MMFR1, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR2); - t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, NV, 2); /* FEAT_NV2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2= */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* v8.1: FEAT_TTCNP */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* v8.1: FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* v8.1: FEAT_IESB */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* v8.1: FEAT_LVA */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, NV, 2); /* v8.3: FEAT_NV2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* v8.3: FEAT_TTST */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* v8.2: FEAT_LSE2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* v8.3: FEAT_IDST */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* v8.3: FEAT_S2FWB */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* v8.3: FEAT_TTL */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* v8.3: FEAT_BBML2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* v8.2: FEAT_EVT2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* v8.4: FEAT_E0PD */ SET_IDREG(isar, ID_AA64MMFR2, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR3); - t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* FEAT_MEC */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* FEAT_S1PIE */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* FEAT_S2PIE */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* FEAT_AIE */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* v8.0: FEAT_TCR2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* v8.0: FEAT_SCTLR2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* v9.2: FEAT_MEC */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* v8.2: FEAT_FPACC_= SPEC */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* v8.8: FEAT_S1PIE */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* v8.8: FEAT_S2PIE */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* v8.8: FEAT_AIE */ SET_IDREG(isar, ID_AA64MMFR3, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR4); - t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* FEAT_ASID2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* v9.4: FEAT_ASID2 */ SET_IDREG(isar, ID_AA64MMFR4, t); =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* FEAT_SVE2p1 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 2); /* FEAT_BF16, FEAT_EBF= 16 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* FEAT_SVE_B16B16 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* v9.2: FEAT_SVE2p1 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMUL= L128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitP= erm */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 2); /* v8.2: FEAT_EBF16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* v9.2: FEAT_SVE_B16B= 16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3= */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* v9.0: FEAT_SVE_SM4 = */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* v8.1: FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* v8.2: FEAT_F32MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* v8.2: FEAT_F64MM */ SET_IDREG(isar, ID_AA64ZFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64DFR0); - t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ - t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* v8.7: FEAT_Debugv8p= 8 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* v8.4: FEAT_PMUv3p5 = */ + t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* v8.5: FEAT_HPMN0 */ SET_IDREG(isar, ID_AA64DFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64SMFR0); - t =3D FIELD_DP64(t, ID_AA64SMFR0, SMOP4, 1); /* FEAT_SME_MOP4 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, STMOP, 1); /* FEAT_SME_TMOP */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SFEXPA, 1); /* FEAT_SSVE_FEXPA */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, AES, 1); /* FEAT_SSVE_AES */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP2, 1); /* FEAT_SSVE_FP8DOT2 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP4, 1); /* FEAT_SSVE_FP8DOT4 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8FMA, 1); /* FEAT_SSVE_FP8FMA */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, BI32I32, 1); /* FEAT_SME2 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F32, 1); /* FEAT_SME_F8F32 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F16, 1); /* FEAT_SME_F8F16 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F16, 1); /* FEAT_SME_F16F16 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, B16B16, 1); /* FEAT_SME_B16B16 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I32, 5); /* FEAT_SME2 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 2); /* FEAT_SME2p1 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, LUTv2, 1); /* FEAT_SME_LUTv2 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SMOP4, 1); /* v9.4: FEAT_SME_MOP4= */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, STMOP, 1); /* v9.4: FEAT_SME_TMOP= */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SFEXPA, 1); /* v9.4: FEAT_SSVE_FEX= PA */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, AES, 1); /* v9.5: FEAT_SSVE_AES= */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP2, 1); /* v9.2: FEAT_SSVE_FP8= DOT2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP4, 1); /* v9.2: FEAT_SSVE_FP8= DOT4 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8FMA, 1); /* v9.2: FEAT_SSVE_FP8= FMA */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* v9.2: FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, BI32I32, 1); /* v9.2: FEAT_SME2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* v9.2: FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* v9.2: FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* v9.2: FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F32, 1); /* v9.2: FEAT_SME_F8F3= 2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F16, 1); /* v9.2: FEAT_SME_F8F1= 6 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F16, 1); /* v9.2: FEAT_SME_F16F= 16 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, B16B16, 1); /* v9.2: FEAT_SME_B16B= 16 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I32, 5); /* v9.2: FEAT_SME2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* v9.2: FEAT_SME_F64F= 64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* v9.2: FEAT_SME_I16I= 64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 2); /* v9.2: FEAT_SME2p1 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, LUTv2, 1); /* v9.2: FEAT_SME_LUTv= 2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* v9.2: FEAT_SME_FA64= */ SET_IDREG(isar, ID_AA64SMFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64FPFR0); - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8E5M2, 1); /* FEAT_FP8 */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8E4M3, 1); /* FEAT_FP8 */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8MM4, 1); /* FEAT_F8F16MM */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8MM8, 1); /* FEAT_F8F32MM */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8DP2, 1); /* FEAT_FP8DOT2 */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8DP4, 1); /* FEAT_FP8DOT4 */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8FMA, 1); /* FEAT_FP8FMA */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8CVT, 1); /* FEAT_FP8 */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8E5M2, 1); /* v9.2: FEAT_FP8 */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8E4M3, 1); /* v9.2: FEAT_FP8 */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8MM4, 1); /* v9.2: FEAT_F8F16MM = */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8MM8, 1); /* v9.2: FEAT_F8F32MM = */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8DP2, 1); /* v9.2: FEAT_FP8DOT2 = */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8DP4, 1); /* v9.2: FEAT_FP8DOT4 = */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8FMA, 1); /* v9.2: FEAT_FP8FMA */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8CVT, 1); /* v9.2: FEAT_FP8 */ SET_IDREG(isar, ID_AA64FPFR0, t); =20 /* Replicate the same data to the 32-bit id registers. */ @@ -1432,19 +1435,31 @@ void aarch64_max_tcg_initfn(Object *obj) cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ set_dczid_bs(cpu, 7); /* 512 bytes */ #endif + + /* v8.4: FEAT_MTE2 */ cpu->gm_blocksize =3D 6; /* 256 bytes */ =20 + /* v8.2: FEAT_SVE */ cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); - cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; - - aarch64_add_pauth_properties(obj); aarch64_add_sve_properties(obj); - aarch64_add_sme_properties(obj); object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, cpu_max_set_sve_max_vq, NULL, NULL); + + /* v9.2: FEAT_SME */ + cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; + aarch64_add_sme_properties(obj); + + /* v8.2: FEAT_PAuth2 */ + aarch64_add_pauth_properties(obj); + + /* v9.1: FEAT_RME */ object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rm= e); + + /* v9.4: FEAT_RME_GPC2 */ object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz, cpu_max_set_l0gptsz, NULL, NULL); + + /* v8.6: FEAT_LPA2 */ qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); } =20 --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fixes: b3717c23e1c0 ("hw/misc/iotkit-secctl: Add handling for PPCs") Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/iotkit-secctl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c index 54bfe1ba597..93753c2ced2 100644 --- a/hw/misc/iotkit-secctl.c +++ b/hw/misc/iotkit-secctl.c @@ -195,7 +195,7 @@ static MemTxResult iotkit_secctl_s_read(void *opaque, h= waddr addr, case A_AHBSPPPCEXP1: case A_AHBSPPPCEXP2: case A_AHBSPPPCEXP3: - r =3D s->apbexp[offset_to_ppc_idx(offset)].sp; + r =3D s->ahbexp[offset_to_ppc_idx(offset)].sp; break; case A_APBSPPPC0: case A_APBSPPPC1: --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310139; cv=none; d=zohomail.com; s=zohoarc; b=UlnpRpRtRGKgrNIaR6z68kyyuZC2e3K4toDiCxDYMjGeNu+WTIr7YitHvPT3GjkI5tBT532Cu25VnVMGMgHBT9FlU6rJmbuoG0ktELAd0FbkIt2EHxTVWM+dablUWYfksiqamv07yOs4G66QaygdVznbkcCPlW4G7aSRhvATCIc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310139; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=yQ/G37RMTnfkm692k/xkc06juSJPOR7nps3h8OgUkOE=; b=FgBvrpKRJc3r8WcYhp4nC+XUCwqTRas3MMv38TkToBh/GjUNUTOcLcspdkbX7V4s5Ih0h2lDPPBCvRhYGquPz4YKw8CTnzp6aI0XvSn6n2NXBU9hAL7U43Y77bJaavt7J4lSjvg7w/uDY5WIoE0HqIxcerwq35uMwYOK8rMCi34= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310139244570.0739942426914; Fri, 21 Aug 2026 04:02:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN0Y-0006Ht-Dn; Fri, 21 Aug 2026 07:01:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN0X-0006Fg-Aa for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:57 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN0V-0007JD-H0 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:01:57 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4957eefd361so5573695e9.1 for ; Fri, 21 Aug 2026 04:01:55 -0700 (PDT) Received: from lanath.. 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Use a temporary, to cover the possibility of operand overlap. (Cc for stable as this is a prerequisite for the bug fix in the next commit.) Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260811191540.79882-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/tcg/tcg-op-common.h | 2 ++ include/tcg/tcg-op.h | 2 ++ tcg/tcg-op-gvec.c | 14 -------------- tcg/tcg-op.c | 20 ++++++++++++++++++++ 4 files changed, 24 insertions(+), 14 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index f7b6aadb508..9b321f959c0 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -163,6 +163,7 @@ void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32= arg2); void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_ussub_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); void tcg_gen_revbit8_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); @@ -276,6 +277,7 @@ void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64= arg2); void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_ussub_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); void tcg_gen_revbit8_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 568b78fe81d..37211642365 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -153,6 +153,7 @@ typedef TCGv_i64 TCGv; #define tcg_gen_umin_tl tcg_gen_umin_i64 #define tcg_gen_smax_tl tcg_gen_smax_i64 #define tcg_gen_umax_tl tcg_gen_umax_i64 +#define tcg_gen_ussub_tl tcg_gen_ussub_i64 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 @@ -275,6 +276,7 @@ typedef TCGv_i64 TCGv; #define tcg_gen_umin_tl tcg_gen_umin_i32 #define tcg_gen_smax_tl tcg_gen_smax_i32 #define tcg_gen_umax_tl tcg_gen_umax_i32 +#define tcg_gen_ussub_tl tcg_gen_ussub_i32 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index bc323e25009..27f3807b004 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2399,20 +2399,6 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs= , uint32_t aofs, tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); } =20 -static void tcg_gen_ussub_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_i32 min =3D tcg_constant_i32(0); - tcg_gen_sub_i32(d, a, b); - tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d); -} - -static void tcg_gen_ussub_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - TCGv_i64 min =3D tcg_constant_i64(0); - tcg_gen_sub_i64(d, a, b); - tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, min, d); -} - void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index e28944cf720..28d3b2a847c 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1328,6 +1328,16 @@ void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv= _i32 b) } } =20 +void tcg_gen_ussub_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t =3D tcg_temp_ebb_new_i32(); + TCGv_i32 z =3D tcg_constant_i32(0); + + tcg_gen_sub_i32(t, a, b); + tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, z, t); + tcg_temp_free_i32(t); +} + void tcg_gen_abs_i32(TCGv_i32 ret, TCGv_i32 a) { TCGv_i32 t =3D tcg_temp_ebb_new_i32(); @@ -2523,6 +2533,16 @@ void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv= _i64 b) } } =20 +void tcg_gen_ussub_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t =3D tcg_temp_ebb_new_i64(); + TCGv_i64 z =3D tcg_constant_i64(0); + + tcg_gen_sub_i64(t, a, b); + tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, z, t); + tcg_temp_free_i64(t); +} + void tcg_gen_abs_i64(TCGv_i64 ret, TCGv_i64 a) { TCGv_i64 t =3D tcg_temp_ebb_new_i64(); --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310174; cv=none; d=zohomail.com; s=zohoarc; b=hRAWTxDLMI9VmKnqI6WXHUUg+NEFLdCVooHxKNoNUGPtaJ80uAlh7/jkKuNokm5r1D3Us7u+wXCvdfRdAaokCN3outB6GiJGPciq2HwOW7GD1/aXdl3/rPKL2HiHRvAVIZ0hVmL+ZpqMZLNu5hk4k+YQj/Wl6pk7DMKm9RjQxNQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310174; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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This happens when the address difference is less than ESIZE but greater than zero. Fix by dropping direct comparisons of op0 vs op1, and instead testing the scaled diff vs 0. Merge with the bounding to the maximum vector length via wrapping arithmetic. Cc: qemu-stable@nongnu.org Fixes: 14f6dad168e ("target/arm: Implement SVE2 WHILERW, WHILEWR") Reported-by: YanjunYang Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260811191540.79882-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-sve.c | 38 +++++++++++++++++++++------------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index fc4cc8c479f..0becef16a94 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -3697,7 +3697,7 @@ TRANS_FEAT(WHILE_gt_cnt4, aa64_sme2_or_sve2p1, do_WHI= LE, =20 static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a) { - TCGv_i64 op0, op1, diff, t1, tmax; + TCGv_i64 op0, op1, diff, t1; TCGv_i32 t2; TCGv_ptr ptr; unsigned vsz =3D vec_full_reg_size(s); @@ -3713,7 +3713,6 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHIL= E_ptr *a) op0 =3D read_cpu_reg(s, a->rn, 1); op1 =3D read_cpu_reg(s, a->rm, 1); =20 - tmax =3D tcg_constant_i64(vsz >> a->esz); diff =3D tcg_temp_new_i64(); =20 if (a->rw) { @@ -3723,25 +3722,36 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WH= ILE_ptr *a) tcg_gen_sub_i64(diff, op0, op1); tcg_gen_sub_i64(t1, op1, op0); tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, diff, t1); - /* Divide, rounding down, by ESIZE. */ - tcg_gen_shri_i64(diff, diff, a->esz); - /* If op1 =3D=3D op0, diff =3D=3D 0, and the condition is always t= rue. */ - tcg_gen_movcond_i64(TCG_COND_EQ, diff, op0, op1, tmax, diff); } else { /* WHILEWR */ - tcg_gen_sub_i64(diff, op1, op0); - /* Divide, rounding down, by ESIZE. */ - tcg_gen_shri_i64(diff, diff, a->esz); - /* If op0 >=3D op1, diff <=3D 0, the condition is always true. */ - tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, tmax, diff); + /* Saturating subtraction maps diff <=3D 0 to diff =3D=3D 0. */ + tcg_gen_ussub_i64(diff, op1, op0); } =20 - /* Bound to the maximum. */ - tcg_gen_umin_i64(diff, diff, tmax); + /* Divide, rounding down, by ESIZE. */ + tcg_gen_shri_i64(diff, diff, a->esz); =20 - /* Since we're bounded, pass as a 32-bit type. */ + /* + * If diff =3D=3D 0, the condition is always true. Also, bound to max. + * Simplify + * diff =3D diff ? diff : max; + * diff =3D umin(diff, max); + * via + * diff -=3D 1; + * diff =3D umin(diff, max - 1); + * diff +=3D 1; + * via 0 - 1 =3D=3D UINT64_MAX. + */ + tcg_gen_addi_i64(diff, diff, -1); + tcg_gen_umin_i64(diff, diff, tcg_constant_i64((vsz >> a->esz) - 1)); + + /* + * Since we're bounded, pass as a 32-bit type. + * Sink the diff +=3D 1 from above into the 32-bit type. + */ t2 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, diff); + tcg_gen_addi_i32(t2, t2, 1); =20 desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); desc =3D FIELD_DP32(desc, PREDDESC, ESZ, a->esz); --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310171; cv=none; d=zohomail.com; s=zohoarc; b=Z/bOb8xRALeU30rTJmLGUW/iLxntvVEq9E5jdkvG5cascAOTxUxx2Ju3QHS25cUlmYw3Ke5WYnnaIJy6qpREadTaO/H/afpyLD7yn0r6cH1B+V5ZTsaqzjpYePx6pzwY0s0dV0XTkvT7Vs/EcLh7L0Lc9QdTo0x6YtpqDpcPMq8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310171; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=vgZGi3ojMLAhiJTCT4hqPiUIwr2tFKlpfDU4bFHaPo4=; b=ZpNCst74BrQ9xOvFGzBNgku9LTouke4sEAPg1BDAT1qGOfWyZJjc6q+BpHQemjoiRByVru/S1EcbWd5hlI5z6tzrLL0FnTIzEw0HvGuGvXyIO/z+o6mCZbkJ3r340ysOeWSmJvb8v7cLRAymUwOOCQt/3ZKqvmovSuavJPL06EE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310171415449.58244238804275; Fri, 21 Aug 2026 04:02:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN0g-0007Cd-5o; Fri, 21 Aug 2026 07:02:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN0c-0006oK-SZ for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:02 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN0a-0007K2-UE for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:02 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-498028b3d5eso9475535e9.1 for ; Fri, 21 Aug 2026 04:02:00 -0700 (PDT) Received: from lanath.. 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Fri, 21 Aug 2026 04:01:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/43] tests/tcg/aarch64: Add regression test for whilewr/whilerw Date: Fri, 21 Aug 2026 12:00:32 +0100 Message-ID: <20260821110101.3971391-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310172434158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260811191540.79882-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- tests/tcg/aarch64/Makefile.target | 5 +++-- tests/tcg/aarch64/sve-while-ptr.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/aarch64/sve-while-ptr.c diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 32f26892737..6cc81bf854f 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -203,8 +203,9 @@ endif endif =20 ifneq ($(CROSS_CC_HAS_SVE2),) -AARCH64_TESTS +=3D test-826 -test-826: CFLAGS +=3D $(CROSS_CC_HAS_SVE2) +SVE2_TESTS =3D test-826 sve-while-ptr +$(SVE2_TESTS): CFLAGS +=3D $(CROSS_CC_HAS_SVE2) +AARCH64_TESTS +=3D $(SVE2_TESTS) endif =20 TESTS +=3D $(AARCH64_TESTS) diff --git a/tests/tcg/aarch64/sve-while-ptr.c b/tests/tcg/aarch64/sve-whil= e-ptr.c new file mode 100644 index 00000000000..7db3b9cc035 --- /dev/null +++ b/tests/tcg/aarch64/sve-while-ptr.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* WHILEWR / WHILERW regression test */ + +#include +#include + +int main(int argc, char **argv) +{ + unsigned short p; + int set_vl_ret; + + set_vl_ret =3D prctl(PR_SVE_SET_VL, 16, 0, 0, 0, 0); + assert(set_vl_ret =3D=3D 16); + + p =3D 0xdead; + asm("whilewr p0.s, %0, %1\n\t" + "str p0, [%2]" + : : "r"(8), "r"(11), "r"(&p) : "memory", "p0"); + assert(p =3D=3D 0x1111); + + p =3D 0xdead; + asm("whilerw p0.s, %0, %1\n\t" + "str p0, [%2]" + : : "r"(8), "r"(11), "r"(&p) : "memory", "p0"); + assert(p =3D=3D 0x1111); + + return 0; +} --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310166; cv=none; d=zohomail.com; s=zohoarc; b=H2DKrZxZSW9bDYJGZhrE75rl8Xm2z8j5SyrRs/CleynA9R7JienYfxoXmeAo91yUmLuGjdUhuezhPnalzGpO6glpop8XRst6pqOCwRZibrT4Dl1/TINRJvS8Ty6XGxuZSSrQdfR9jawRRAu+abfUFFfcmHepZmcxQvRsZizFZOk= ARC-Message-Signature: i=1; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.01.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:01:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310122; x=1787914922; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=vnXUIz3SC8Ou6fd68xxg7mOuPxzgFf1mC6qX64/vths=; b=KGzBEBgNPcZHWv6eRr2PQLkqakAinwpP5f8MGhOaQd5YIh5LmM/vSI1e408IxA+Ofz AX3sMEfCQYeZdk/CfiItKF7cwOgy0Y84C/kfyGgdMYrTnyY8NnX+BL8VKIshVSEt8VIe XgH0ESsUWUDO0uX5CYYotYhpu2tliQmBOivNVBKdE/PVR1xEmZJ2OnX6c9Zj6oX3vXT6 AcPEIkM9krH+68wnp964ef6wJoU1zTGJ/PyKgupj3CgowtAcxmLBjBNLB3YrMWMHBN7Y PiivkKeDdQNm0sLr0dso1UYEYuHcbB4vpEF5Ml+67+bzm5wKrb/gh9lKbp6ckyZI4aYf c34A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310122; x=1787914922; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=vnXUIz3SC8Ou6fd68xxg7mOuPxzgFf1mC6qX64/vths=; b=UsgEfh9lnTxV/v7UxLRk+SkVh4uEsUPKZ0wlmid7xibdBETN2OylvL6px6XSOO4lph yKUNbcHPKVmdjegD/TXRZJWfFLKeDWYv5phqudz8vLkrIeMt/miDjtqquhiZgbbn2iut lJhpRfYBFOlOKuqpSnYdbotK/79uI68u35gs0SwWVs4kDBRwwtSh+/oP3ouPxWBxs8ZK H8AtmWQQ7rJ57GuPyKwp9IM9yrrnPr1DLxM/2/R3CAlAjXoI54LUQQS1dLS4URnTxl7m lNC6oebDrhlPCLj7uu50xCzz1TeBlp6rjykT4Urb/IY2De1Dp7k2T/3pmospEZRxdzCR wk9Q== X-Gm-Message-State: AOJu0YySm6SHVZ8bHagdK0zx5SV9DElkX3jTqn0OfFOB0X5elKXdZbRJ +G9wxU1ZT29tix34Mr8Qc4o+soUc+qtHzMkWSa8+oSJa9QiaQYNFgq0wuAdTJ9CKg4j3XneeA/0 VS0FW X-Gm-Gg: AR+sD11Q4UtRCfgwH573Kyh8akq8fvDW9nqqjydo1P1f04J34y7D8Z3Ht2uz+75N0o+ wVc2/Qjcf1M+4k2BQidIEIOIUZf4915VSIUuyT4rp2YdcA+awbilgWgzulQftX8TDQUZivOfgit cMTt/vGVRmZsBylKMQzzh0WH4lisHgxSqlXmq8GNmNp7KmZlSQcdv09Ekn9yWTS3gKU1wnv8/34 6kNAA283uV0zRVhzrZLaxGWOH/E9ovclAmg+NKZlS6yprErc690xQzVDD7TQ3ytUh1fL9cZeoKO ezlO4mCW+IL/twZRS0VxgLliQDexcwcr+qmEWyZb01BqcbZ61/n7AWuMP0mEyFs0HYSQEIURCdb gzGhVaOSBnArZY5QWKMdko4qOu32qPywyl1B/Fz3In4uPe+bOxB95mKoHXXcBCYmsUMfmcJHoKy /lmw6As0nMFWdIEk+4o01ZhZuOVPANbdkHg2GUk+GsY2nRBhcA9es506NuNZyWnmfglUEodXire b1EUQbzkKz8amRLTGc1u57G98d1tQUq3lddB0YbeoT47RzTGCBykQuBPpk+K7DC3G3nUw== X-Received: by 2002:a05:600c:3e1b:b0:499:a685:c10 with SMTP id 5b1f17b1804b1-499b82e5427mr86715255e9.4.1787310121633; Fri, 21 Aug 2026 04:02:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/43] hw/arm/ax3000-soc: fix heap overflow from missing class_size Date: Fri, 21 Aug 2026 12:00:33 +0100 Message-ID: <20260821110101.3971391-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310168429158500 Content-Type: text/plain; charset="utf-8" From: Doug Cook TYPE_AX3000_SOC declares an Ax3000SoCClass via OBJECT_DECLARE_TYPE() and ax3000_class_init() writes to it: Ax3000SoCClass *sc =3D AX3000_SOC_CLASS(oc); sc->num_cpus =3D AX3000_NUM_CPUS; but its TypeInfo omits .class_size, so type_initialize() only allocates class_size inherited from the parent, i.e. sizeof(SysBusDeviceClass). The store to sc->num_cpus therefore writes 4 bytes of the value 4 just past the end of the class allocation, corrupting whatever heap block follows it. Fix by setting class_size. Fixes: 33a71a68c6e1 ("hw/arm: Add Axiado SoC AX3000") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4197 Signed-off-by: Doug Cook Message-id: LVXPR21MB70090B04FF7397B0F2A201C8ADA72@LVXPR21MB7009.namprd21.p= rod.outlook.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/ax3000-soc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/ax3000-soc.c b/hw/arm/ax3000-soc.c index 71e31c6fb46..ebe174fb978 100644 --- a/hw/arm/ax3000-soc.c +++ b/hw/arm/ax3000-soc.c @@ -236,6 +236,7 @@ static const TypeInfo axiado_soc_types[] =3D { .instance_size =3D sizeof(Ax3000SoCState), .instance_init =3D ax3000_init, .class_init =3D ax3000_class_init, + .class_size =3D sizeof(Ax3000SoCClass), } }; =20 --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310136; cv=none; d=zohomail.com; s=zohoarc; b=PZrpaXWVOoLS1SzjKMBKMYautGV2WT0AHfY96oSNPDGTF/9s5OCvwtl3jIt2MnqAEx9Wt8OGwRIDfQY08PfsWw7QhiES2MHYEUys1kS2u86GdZ6Pdne6TjddNTCDZ6WUjGz+TquIKSDzL4ktNedvbu8gzkT6rhP+6kDDlJ5/iwc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310136; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=A8JHAqmDcN4O81D571sT2d4dAyJDQaqEm7zYyrqJnRE=; b=VUvLSO0BkUrNcEERLwRc4lRGw1PsaMndYnbggp8a8jwoRycEY201KmPQ8mUmOdu0e9k4NoRg16FhdQd+dWZKsS4uLcYrk5w3UGhl3lctDTG3EoVEg9R5uwjXqBAfk6ELxM6xYBHcvtdcjUOpQ+Y1/vYgMbjSF2t7X3gpLkhlV3c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310136401364.4822744476652; Fri, 21 Aug 2026 04:02:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN0k-0007fm-J8; Fri, 21 Aug 2026 07:02:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN0h-0007Nj-Ls for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:08 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN0f-0007L6-KQ for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:07 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4980fe6b3beso15556835e9.0 for ; Fri, 21 Aug 2026 04:02:05 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310124; x=1787914924; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=A8JHAqmDcN4O81D571sT2d4dAyJDQaqEm7zYyrqJnRE=; b=hNkVFvauIibw+jdXd9GIpPGGwzBt7JBvCx20fDpMTwE7YpQcbR2AFz3h+MYWfZ6Q7E 8No+VlNMRnjKC7Z9fn2IumJTRWzwLck9q9lK52+Zf3qP1/r5eglx5shIA9qHF/mpH/7B aqBbZqEH7Z+Dvwzhu4qR/WtF3B/JzHwbemXe3sPRoR6J/mLkFUxcwvc0k5kAoVysCnDP W/8/sI3ge7NmdgPge3q93ni/LbKKeO+NjPhOcv/zLrX20ZfsGBaTEm9Wwqe37vo5Sc9k c6oOoBMoC+nbVZTaPegBZ1QrVaO20zJ92LKzUhD2bg9ZtmEqwTbeiNl28Z7HmX4DkgjX GeiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310124; x=1787914924; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=A8JHAqmDcN4O81D571sT2d4dAyJDQaqEm7zYyrqJnRE=; b=SsldKHaL3RKZc/u2+0GKcWFkcFUsC29GPuOZm8LEzt427VaucH0beYudQMInI11D0J 9A73vaUbCX1CMpKzB/8Txk1BOJK/4i17COy5K2QM2bN5FwVabMtzlWz/DNJk1KXQ8Gcm dbJJMt5SAtFZaYk3EO7fDxAgytjtemX0N4eRiMtrh3VgD3ux0v00O30JntspuWpwfreH PCfWHeDFIL3DASH6m2iTrqYUm875wy2ZU4gpWuSTRaQWgmwuRv3Zm8/qz8gXkLk45Xza iZDdo2XOMlzJl2VpFHux6eDuQtXVj6l6EvL7ZX+bGPFX0LAgYBbLe4ZKJgC1OwBEklJu vG5g== X-Gm-Message-State: AOJu0YyCd9Rh8+J2S96bLcCV5HYzJ+5zRhwirSyLx2Ug1Fkz8c59QHK7 Vmm72147P2lRSUkCr6FHnscKV08OjYWHtP0q7TIytNKCkYRfD/QiHIAwO8E+4jbnnCn4ndRCBaQ QYUL1 X-Gm-Gg: AR+sD10aNfcS2HBGqxLrww5g3IPd09q1Z3a/a63T+TaJN/9BnqPBHbL0QRx14YIO2K2 LXY+d0fZytMxz5e9l2bNAcmeKL4APq7SErO+0QYSVGwYa9fdXWZGWD64AbqrOdx8TyOjfwlxtR8 JM8rl5s06cqT0OX4SkP0dOEIfRx11qZMQIHNQ7JKABxC77f0AvV3smQboPmgYR1LmYkN44dOhnZ N6xf3LWXz7XkKM4Yw2TzcCVePKxkIted482z84mjpqzkBMJMnHeJmNkpAENUbJpFhEMqr6U5ILK CBvnIhKIi4XtiR0Yf/N8Pg3y1Trf57EjxPozIBfjDenQEi2wR+88M4RxwSrLZCDOn5meSgm3m6l q8XA/AjOv7FPpV0tMXDdDKvrHr2uF4w76s3andRcU654jrJdN831hcB7id7ataFEvvIoqLTRljb zcfjZTmySPLX/boFyw2vk8HlutrbUsuz3A8AT25lP6OoULrniFdTDYdzmwtT/mE1KML3B+Qu9An Bm3KxpTLWryLYH3wbfAtAGoTFMssFm/BXT64hFWAaMB30wqDvagm7+zFxOCLzLpXAmb3w== X-Received: by 2002:a05:600c:1912:b0:499:8d9b:832c with SMTP id 5b1f17b1804b1-499b9182141mr45304635e9.4.1787310123715; Fri, 21 Aug 2026 04:02:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/43] target/arm: Handle NSACR.NSASEDIS in CPACR accesses Date: Fri, 21 Aug 2026 12:00:34 +0100 Message-ID: <20260821110101.3971391-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310138180158500 Content-Type: text/plain; charset="utf-8" In cpacr_read() and cpacr_write() we have code that implements the "CPACR.{cp10,cp11} behave as RAZ/WI from NonSecure when NSACR.cp10 is 0" behaviour. There is a similar requirement for CPACR.ASEDIS: if NSACR.NSASEDIS is 1 then CPACR.ASEDIS behaves as RAO/WI in NS. This doesn't matter to us yet because we don't currently implement ASEDIS or NSASEDIS. But we're about to do that, so add the handling to cpacr_read() and cpacr_write(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260817123838.1578060-2-peter.maydell@linaro.org --- target/arm/helper.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index adae2b2b8e5..6a707b80cff 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -588,11 +588,19 @@ static void cpacr_write(CPUARMState *env, const ARMCP= RegInfo *ri, /* * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR= .CP10 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. + * Similarly, if NSACR.NSASEDIS is 1 then CPACR.ASEDIS ignores writes + * and reads as 1. */ if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && - !arm_is_secure(env) && !FIELD_EX32(env->cp15.nsacr, NSACR, CP10)) { - mask =3D R_CPACR_CP11_MASK | R_CPACR_CP10_MASK; - value =3D (value & ~mask) | (env->cp15.cpacr_el1 & mask); + !arm_is_secure(env)) { + if (!FIELD_EX32(env->cp15.nsacr, NSACR, CP10)) { + mask =3D R_CPACR_CP11_MASK | R_CPACR_CP10_MASK; + value =3D (value & ~mask) | (env->cp15.cpacr_el1 & mask); + } + if (FIELD_EX32(env->cp15.nsacr, NSACR, NSASEDIS)) { + mask =3D R_CPACR_ASEDIS_MASK; + value =3D (value & ~mask) | (env->cp15.cpacr_el1 & mask); + } } =20 env->cp15.cpacr_el1 =3D value; @@ -603,12 +611,18 @@ static uint64_t cpacr_read(CPUARMState *env, const AR= MCPRegInfo *ri) /* * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR= .CP10 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. + * Similarly NSACR.NSASEDIS makes CPACR.ASEDIS read as 1. */ uint64_t value =3D env->cp15.cpacr_el1; =20 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && - !arm_is_secure(env) && !FIELD_EX32(env->cp15.nsacr, NSACR, CP10)) { - value =3D ~(R_CPACR_CP11_MASK | R_CPACR_CP10_MASK); + !arm_is_secure(env)) { + if (!FIELD_EX32(env->cp15.nsacr, NSACR, CP10)) { + value =3D ~(R_CPACR_CP11_MASK | R_CPACR_CP10_MASK); + } + if (FIELD_EX32(env->cp15.nsacr, NSACR, NSASEDIS)) { + value |=3D R_CPACR_ASEDIS_MASK; + } } return value; } --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310145; cv=none; d=zohomail.com; s=zohoarc; b=kE3KPgLMCmvD+0C87e7ksOjHNXcqC2dE0OEuvhfRbHeYg2a96pLxjT/XFnyvGTbLaqVt/mCamkH54CD0pYoOBopb1XFihcyz0wObFUvsmdVo+NFYtQcaOWyKtbv0LIeEjmn4nQY5zgWgoJWWmJJ73JclxNkwxH1xn0RctPAqblY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310145; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=LHJQk44yFfynPaUC5hQjyP5aA7i00MLZRfDUAfCRXcE=; b=kyUjTsYFRIOBQsC5w9+gzJD0F6OyWRT3wg5Z0Y4zrhgPbloLXOUGDIk4bTkI+o6NDOejSL936PdNYFUDxD5RxPyJyTBvh45GtdX0LSJyVIyLjB2ob3oOe//LQ9ZL6MgUnW73AECn9b2lnG0BayqxYqV+FB//capKlSIfR1rBnYQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310145108484.2211330320607; Fri, 21 Aug 2026 04:02:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN0o-0007yl-IE; Fri, 21 Aug 2026 07:02:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN0m-0007rA-Nx for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:12 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN0k-0007Mj-Tj for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:12 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4998e0916faso4894825e9.2 for ; Fri, 21 Aug 2026 04:02:10 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310129; x=1787914929; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=LHJQk44yFfynPaUC5hQjyP5aA7i00MLZRfDUAfCRXcE=; b=jKRFXFHwcaOOmCzLzlpi+GctkyT4Ow4ZuZcnu5foNcqDWvtgSMj7mjZMJ/pe3iwLUP 8Uba5FmztpvoNzY/JsFI5t/UtbygSG9Dwe8P1cVYnz7y5g1/AT5WdlXxJPsbXcLLriTw JaODd1Dz0f23ls+u5Zwg2bmYWmYvlim13Gh475Qly1uTSht17RhSR+cwp+udQ8RPXkXi P1Ob+QEKs3AWkSjOuBmE9jcDkLmdA5+8UjWHzFvXrRnv7wd5pYH6zTuMS/ba9SaxgH1W rZh/kS5rmKeSdc8+6aXM1gQvcGR6OlPCBdQKu9KrTubEoLuJtst/jS1i5E3DG/tLuYse HPjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310129; x=1787914929; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=LHJQk44yFfynPaUC5hQjyP5aA7i00MLZRfDUAfCRXcE=; b=EZp/9gkKx4Mfay1EOSd2CncUiA5LZEyzi5rNsSl1JhvJ7eFzpAeKF+To0FoUZ/sinE AZeVc1RVm49snHGXfmp1sTfqniudIy4N3RlaMELFl+EM1TAvI09uPfSd5e3jvB/ABTe4 +1web5PunMOuz44W4oVdMiaQTl2JhHx8xuawVjHxVUIXosIOA+jRKIOgCgleZZGzJqBG DiZtArL2JFwNNO7vwoZjgiOjILDmco60lhS1bBiLXHHWF7+GpYg0WW9CZTqfufmhe3od orw2yGTF78//nHr0uWibG07VUJ7o19p/ciVix+2PBBMfJhHh0p/7iAfqUH+MMGzLobTU EsUw== X-Gm-Message-State: AOJu0YytR8mRCtftdQZYx838NFy+FHz6qo2XNvPrH20W5ToLGbGGawSp S/M4LeGglar+GZGQNmDugOhfuqFx8kW0XRuLLO1jjXqYSmqi3cq74n/gCqYjIwBRD9ggG7KwmBb qDaFR X-Gm-Gg: AR+sD13OMhzgEe6k51WwJOVyIDyCw70u5Evk88niN/XbXODfg1zm3Hi6Cr2Zi6rxGXa 58xTvUXTC6wjsfLLlarIitlD/sXGU05AUWYcoLyGqmKP6k6KvTL1tHzLhlHNmbFdr/GFPew5Vuy 0N8GB3taWDwtIayTQR5iq4N1cbEizU38SGblDRSv1EnyeXL7+Xd2YqQ3qLXdgt/j6qUE9hdG4Nh qaa1pVAPTxcVwKi8jPd2i0VEpEyRtVtYGdGALc5RBlyZQbdMOoNDEc+J4kUzMBW3Lc4l6CMrjFv AwLf+k8wyizc9F/Qkpq6Pf2WHmqRkwYVN0F/wkkO3S6f0dlls58oqeXYC/4lqBjWGaRg1Y9Fbaf jVkQY6HCtGIuHLD6KnO0wwxq8dHI56j3lthgLQs+dRQGhAxLxgB0j3EnsBvQiQfQyYzBZ1iAcFn ornOX+7vWdQ4e1Q2J8CurSEgzcsmvo612vAYC7v/FGgwuTvr3aFhmPJxbQ7OpobBmOkFXe8SM2q d6/GUpo22ciGcwRyN/B+rMaFKDE45JMfxM4jnfekcq149kMb3O+18CQCap2xlE+tESEWw== X-Received: by 2002:a05:600c:8b6e:b0:499:a5fc:2087 with SMTP id 5b1f17b1804b1-499b8320523mr81641095e9.6.1787310129458; Fri, 21 Aug 2026 04:02:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/43] target/arm: Handle NSACR.NSASEDIS in HCPTR accesses Date: Fri, 21 Aug 2026 12:00:35 +0100 Message-ID: <20260821110101.3971391-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310146229158501 Content-Type: text/plain; charset="utf-8" In cptr_el2_read() and cptr_el2_write() we have code that implements the "HCPTR.{TCP10,TCP11} behave as RAO/WI from NonSecure when NSACR.cp10 is 0" behaviour. There is a similar requirement for HCPTR.TASE: if NSACR.NSASEDIS is 1 then CPACR.ASEDIS behaves as RAO/WI in NS. This doesn't matter to us yet because we don't currently implement ASEDIS or NSASEDIS. But we're about to do that, so add the handling to cptr_el2_read() and cptr_el2_write(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260817123838.1578060-3-peter.maydell@linaro.org --- target/arm/helper.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6a707b80cff..d582eeba577 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4117,11 +4117,18 @@ static void cptr_el2_write(CPUARMState *env, const = ARMCPRegInfo *ri, /* * For A-profile AArch32 EL3, if NSACR.CP10 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. + * Similarly, if NSACR.NSASEDIS is 1 then HCPTR.TASE behaves as RAO/WI. */ if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && - !arm_is_secure(env) && !FIELD_EX32(env->cp15.nsacr, NSACR, CP10)) { - uint64_t mask =3D R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; - value =3D (value & ~mask) | (env->cp15.cptr_el[2] & mask); + !arm_is_secure(env)) { + if (!FIELD_EX32(env->cp15.nsacr, NSACR, CP10)) { + uint64_t mask =3D R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; + value =3D (value & ~mask) | (env->cp15.cptr_el[2] & mask); + } + if (FIELD_EX32(env->cp15.nsacr, NSACR, NSASEDIS)) { + uint64_t mask =3D R_HCPTR_TASE_MASK; + value =3D (value & ~mask) | (env->cp15.cptr_el[2] & mask); + } } env->cp15.cptr_el[2] =3D value; } @@ -4131,12 +4138,18 @@ static uint64_t cptr_el2_read(CPUARMState *env, con= st ARMCPRegInfo *ri) /* * For A-profile AArch32 EL3, if NSACR.CP10 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. + * Similarly, if NSACR.NSASEDIS is 1 then HCPTR.TASE behaves as RAO/WI. */ uint64_t value =3D env->cp15.cptr_el[2]; =20 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && - !arm_is_secure(env) && !FIELD_EX32(env->cp15.nsacr, NSACR, CP10)) { - value |=3D R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; + !arm_is_secure(env)) { + if (!FIELD_EX32(env->cp15.nsacr, NSACR, CP10)) { + value |=3D R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; + } + if (!FIELD_EX32(env->cp15.nsacr, NSACR, NSASEDIS)) { + value |=3D R_HCPTR_TASE_MASK; + } } return value; } --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310149; cv=none; d=zohomail.com; s=zohoarc; b=jzPHVuiHz0JzKexzdzxR1j7Sfc86CSUe2aKZsU1sm35GDk44TBubUGya/39bfavWb5er96g20QYgw7tL01PheS0UMx1t9nwRq1hfoqifa2BixpuDQMY4Ge+zQ+T2AhN/ByBKcRjlHr3JMIzsCXHUdwobC8t6VNVoL6RRxRmutu0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310149; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=4fLZD1ZpuLL9G6fmiVIFQ4fHwh4kYhArYqzEkRdpzKM=; b=UBqQkw0AxmBQ1jHLhBpggxXp00/liqbjdp+6d6SmiwG2Ybr3dQxX8RLBmcIIHbTl/EJxHYkUjWBDC2Vomgrn8D6DeNUALqyHLLiL63EE0XdqgwnYRX8iBkmpiaLGZCAwSsrZOTRhOhWb0009VoCZHi16aiNXrXJb5uezxanND+E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310149355495.0277874803435; Fri, 21 Aug 2026 04:02:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN0s-0008TT-Ni; Fri, 21 Aug 2026 07:02:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN0q-0008Eo-Kr for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:16 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN0o-0007NK-Pc for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:16 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-499b6c02b02so3966675e9.1 for ; Fri, 21 Aug 2026 04:02:14 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310133; x=1787914933; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=4fLZD1ZpuLL9G6fmiVIFQ4fHwh4kYhArYqzEkRdpzKM=; b=njankd1rgqcDERk7dXvkIXbCL3cHYz+P58Is6jWP6+ulbNXAulAKfbZxhYZVZVrkyu 0RZUBAgC2aXLZzFUd9PukmU90bxakEDpZeAY82qDAmDGqxL1ojTTerwcTpqhlPaH+UPN Gq8LPzdrN3tpPL522MW1HHYP5zV3YuQlE5dDjkRwiq2el6YiD/he44f55NP1p5aD1j8K eGLMAjodpko3GJxhyO97ENw7Uc3DC+s6Gva6Bk4D7Epvm4aRWs/DGOFmpT8memxMyrko QHvOjTT7JkgIoJMgM4bsuXwu75xufEEzH5bgZkpDN0BlKRNZnVmgXL67zRZGeWpRsIVg Npuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310133; x=1787914933; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=4fLZD1ZpuLL9G6fmiVIFQ4fHwh4kYhArYqzEkRdpzKM=; b=Df8H0qCTAq+OG0bR5hUt3V9ketOM1WH81IP7weBo7XR6Olbsyto/JQAoVEAI9pUCmB fDPjwVUcKtJPzKyRb80KLo9/4RrTgsefZx1aZG9ADkZmqS27dhmPykdk45DmSkJ6yy6J +RfiomrYM9SAlKjr+m3ET3W6YuOgbahEUUBzBM2lFLuF8gNN2qIdw1+RdOSEQNSV87wq RNpGU1X8c5vzsrcy6iD+ffsCvxPQxMzj9+/ULiEISef88eE4PePUgUgLq8E5C3w9r++b GCMEB/g7XZCS9F9rv58pxM06xHiff/8wUnNJrbJE+K9u7O/UiDE4C8OsOUeMhsPSdyAd Ndaw== X-Gm-Message-State: AOJu0Yw3/ST2et8shLafHo+77YHxJ4uNn6XiQQk8iKnl48d/GUPMa+UR sg8eTqQDKH2KinXPi02Zz/33+gAmZs1k7E3Py6sddJARpq9ClHdzFEYlZagfkB4pM+2fJvG0Ytu 5H5Ea X-Gm-Gg: AR+sD12FovyncB3NcfSGKjF0/P0Pslzv4WwfYU6YRRiOrxRDrd/zBn+qQwTg8YqQ+cQ 1WSjCHR9TUqLotat8SOJuDM7M1KPaoitz8dRCOA4o6z0e9bXc8XdNBICEbAaEny0CI4kd7S6qhS 0LQhvl48Cjdv8yAnMTIsIdEPTRxb/7bRagh9nJDZSgwloty1E78I4F47QRprZw2syoYK4WZRq5C SQ6gqywtelcQkUtDsQpJrHxHe4aKY+idqpSX/uXztrBXwrpNjs+CsHi6PX8kQgoBYMu6AhUM9oB QU+kzkIE9hjr6ei2whmcaLOXBWiopPvNG5ZdRSj91Ck4ZbmN0FO/Xe/xxuMZ3oQl90v4bFhTU0f J/V269ObBKdaYRgpMDDb02mb4vEZKYurPgDIqwnHRHHl5mcQj/B9pla5Z6yPttGutfUey+1nGD+ A3Km9KVRMh9wQ2Gzk0Q0A9nd401H4xlZNb/eQYnkAbSd6VmVA9Q67wkQnKSmHrw/EEXrG8aGTo+ ZXFKn93/d8tyMc8U7vH6QB7tG6T8gnzATT0Dt5MuuhRi+jFFzXiGWitKFu1cm/1z+LTHA== X-Received: by 2002:a05:600c:6610:b0:499:a660:f926 with SMTP id 5b1f17b1804b1-499b8454bb5mr67077195e9.11.1787310133019; Fri, 21 Aug 2026 04:02:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/43] target/arm: Update confusing comment in cpacr_write() Date: Fri, 21 Aug 2026 12:00:36 +0100 Message-ID: <20260821110101.3971391-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310150312158500 Content-Type: text/plain; charset="utf-8" In cpacr_write() a comment says "In ARMv8 most bits of CPACR_EL1 are RES0", and the mask value is left at 0, implying that we enforce those RES0 bits. In fact we only enforce RES0 when ARM_FEATURE_V8 is not implemented, and for v8 and up we allow the guest to write any bits. The addition of architectural features in v8 and v9 has also resulted in the addition of new bits to CPACR_EL1, so "most bits are RES0" isn't really true any more. Update the comment to be a bit clearer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260817123838.1578060-4-peter.maydell@linaro.org --- target/arm/helper.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d582eeba577..7de38d82010 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -554,7 +554,17 @@ static void cpacr_write(CPUARMState *env, const ARMCPR= egInfo *ri, { uint32_t mask =3D 0; =20 - /* In ARMv8 most bits of CPACR_EL1 are RES0. */ + /* + * The AArch64 view of CPACR_EL1 has a different layout to the old + * AArch32 one. We also need to permit the old AArch32 bits to be + * read and written so that an AArch64 EL2 hypervisor can set up + * the register for an AArch32 EL1 guest. So we choose not to + * enforce any RAZ/WI or RAO/WI bits for v8 based on feature + * presence/absence. + * + * For v7 the situation is a bit simpler and there we do choose to + * enforce RAZ/WI and RAO/WI. + */ if (!arm_feature(env, ARM_FEATURE_V8)) { /* * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310216; cv=none; d=zohomail.com; s=zohoarc; b=U3f1CkuAwA6o6FDTxaBVkZuhFykRN3bvrUrctFD7Qx7zNypdfwtoaZVrEOvKg7kVpScXWe/fOWDmgiejua52RbsoOMl2UafqE7S686JmShLg6ADHBQ9V4JY+G+0zZFm77cQlGvhgjSlxA0WKuZbAtBeAEhyip32lRtnd/ANf7Do= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310216; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=smnV1wjK+FUh9d+GL27blggvLZu2iZmcr7IWs4JiVv8=; b=hw3W2T7PybqpMuiwgp0iyDu4hYrlmHkqED8cOUBiI9HKJlvalGk/hsDHLL9WGLaoK/XgH+C/5NnL0LZA0P/RWJ5JVatA6o4herSw0T5T9OtZsA+AwK1JI/Jb7aZc4COmS/HHCq1sBISnvf/+qOM7Nmsg03X3y/LI3fUXljo09wg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178731021681329.57487761010634; Fri, 21 Aug 2026 04:03:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN0u-0000EX-R3; Fri, 21 Aug 2026 07:02:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN0t-000078-HW for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:19 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN0r-0007RY-2O for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:19 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4980dc26022so6243415e9.1 for ; Fri, 21 Aug 2026 04:02:16 -0700 (PDT) Received: from lanath.. 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In practice, they are present on every implementation I have checked except for the Cortex-A8 (which was the first CPU with Neon). Add a new feature ARM_FEATURE_NEON_TRAPS which we set on every ARM_FEATURE_NEON CPU except the Cortex-A8, and make the CPACR.ASEDIS and HCPTR.TASE bits RAZ/WI unless the CPU has ARM_FEATURE_NEON and ARM_FEATURE_NEON_TRAPS. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260817123838.1578060-5-peter.maydell@linaro.org --- target/arm/cpu-max.c | 1 + target/arm/cpu.h | 7 +++++++ target/arm/cpu64.c | 1 + target/arm/helper.c | 17 +++++++++++++++-- target/arm/tcg/cpu32.c | 8 ++++++++ target/arm/tcg/cpu64.c | 10 ++++++++++ 6 files changed, 42 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 8d968336a8b..4df52bcb08e 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -23,6 +23,7 @@ void aarch64_aa32_a57_init(ARMCPU *cpu, bool aarch64_enab= led) cpu->dtb_compatible =3D "arm,cortex-a57"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); if (aarch64_enabled) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c0492c8dfbc..4f07332543d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2177,6 +2177,13 @@ enum arm_features { * CPU types added in future. */ ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ + /* + * ARM_FEATURE_NEON_TRAPS should be set if the CPU implements the + * CPACR.ASEDIS and HCPTR.TASE bits for trapping A32 Neon. This + * is architecturally IMPDEF, but seems to be implemented by all + * ARM_FEATURE_NEON CPUs except the Cortex-A8. + */ + ARM_FEATURE_NEON_TRAPS, }; =20 static inline int arm_feature(const CPUARMState *env, int feature) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index faaf3ab879d..4e8c4725308 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -699,6 +699,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->dtb_compatible =3D "arm,cortex-a53"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); diff --git a/target/arm/helper.c b/target/arm/helper.c index 7de38d82010..2dfbeae0efd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -573,14 +573,20 @@ static void cpacr_write(CPUARMState *env, const ARMCP= RegInfo *ri, */ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { /* VFP coprocessor: cp10 & cp11 [23:20] */ - mask |=3D R_CPACR_ASEDIS_MASK | - R_CPACR_D32DIS_MASK | + mask |=3D R_CPACR_D32DIS_MASK | R_CPACR_CP11_MASK | R_CPACR_CP10_MASK; =20 if (!arm_feature(env, ARM_FEATURE_NEON)) { /* ASEDIS [31] bit is RAO/WI */ value |=3D R_CPACR_ASEDIS_MASK; + mask |=3D R_CPACR_ASEDIS_MASK; + } else if (arm_feature(env, ARM_FEATURE_NEON_TRAPS)) { + /* + * bit is present unless CPU doesn't implement ASEDIS + * (in which case it is RAZ/WI; this is the Cortex-A8) + */ + mask |=3D R_CPACR_ASEDIS_MASK; } =20 /* @@ -4124,6 +4130,13 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env) static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + if (!arm_feature(env, ARM_FEATURE_NEON_TRAPS)) { + /* + * If CPU doesn't implement HCPTR.TASE it's RAZ/WI. Note that + * NSACR.NSASEDIS being 1 overrides this. + */ + value &=3D ~R_HCPTR_TASE_MASK; + } /* * For A-profile AArch32 EL3, if NSACR.CP10 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index d5dd2361528..724a9549347 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -251,6 +251,10 @@ static void cortex_a8_initfn(Object *obj) cpu->dtb_compatible =3D "arm,cortex-a8"; set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_NEON); + /* + * The Cortex-A8 doesn't have CPACR.ASEDIS and HCPTR.TASE, + * so don't set ARM_FEATURE_NEON_TRAPS. + */ set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_EL3); @@ -321,6 +325,7 @@ static void cortex_a9_initfn(Object *obj) cpu->dtb_compatible =3D "arm,cortex-a9"; set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); @@ -389,6 +394,7 @@ static void cortex_a7_initfn(Object *obj) cpu->dtb_compatible =3D "arm,cortex-a7"; set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); @@ -439,6 +445,7 @@ static void cortex_a15_initfn(Object *obj) cpu->dtb_compatible =3D "arm,cortex-a15"; set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); @@ -634,6 +641,7 @@ static void cortex_r52_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 9ce514dda81..b38c61ba623 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -37,6 +37,7 @@ static void aarch64_a35_initfn(Object *obj) cpu->dtb_compatible =3D "arm,cortex-a35"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -208,6 +209,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->dtb_compatible =3D "arm,cortex-a55"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -281,6 +283,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->dtb_compatible =3D "arm,cortex-a72"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -341,6 +344,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->dtb_compatible =3D "arm,cortex-a76"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -415,6 +419,7 @@ static void aarch64_a78ae_initfn(Object *obj) cpu->dtb_compatible =3D "arm,cortex-a78ae"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -488,6 +493,7 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->dtb_compatible =3D "arm,a64fx"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -662,6 +668,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->dtb_compatible =3D "arm,neoverse-n1"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -738,6 +745,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->dtb_compatible =3D "arm,neoverse-v1"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -965,6 +973,7 @@ static void aarch64_a710_initfn(Object *obj) cpu->dtb_compatible =3D "arm,cortex-a710"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -1067,6 +1076,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->dtb_compatible =3D "arm,neoverse-n2"; set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310215; cv=none; d=zohomail.com; s=zohoarc; b=kZFabUQWmMBDlTZ7d8ixFDzTL8y0R0PEbYQAk5o34ne4l+3sRZPQOeik2NjbJ/Mb3w3erNBcZeqj7mi72HxugLJmfM8dYitjCrBRm+e7WL1RhMSPjFU7pn21KvYMRu7mvoF6suK6FTt1wTesgndeihukysERBi1b4fbvJmWAI2w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310215; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310137; x=1787914937; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=iFa8vLi3xDZSUcOFrJ8xg6zhIdMmM3lcYUvKuPnGc/k=; b=rzJqDbOYc5odThnitrrxPdaP0iYrPQB3aGSkjsgN8M+IrtsmeDAQvXN3tSGQo29V13 XDDT2TeK4hFAsk+zoXfLVbyG8e3L03KLsDo0PCZIDnie/eewoaA1TEnSpcKeT1/UQKWt QvYuWkK3VYObFmD9cnd3sy6x4L+m+PcIVPnvxZ3zDZinUqFXg5bsPzpLwu88S73W89CC VkYELuCdQ9Y0VjnWrmR1Q5rNAPfk4OMNi5Lr5jR7WYsMxxoH0Kk43d6hHH9CW9iUZI6D poI1B2SYe0JdPsvBP//fl4fsKUexap8SflDgGwr4GGPZ3MHepku2l64T1ugSrdAMuWIH YkGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310137; x=1787914937; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=iFa8vLi3xDZSUcOFrJ8xg6zhIdMmM3lcYUvKuPnGc/k=; b=mZdPO3aPwYS5Faws8CSTi4YxK4BruRSJ0v4+F5spwNbDiN4tlVKiXJomGWeuaQpuby TLSwVpnxR0xhsOiVBvhkWmfwR2QYqi5geEvYVv3cdPLUupiTUaFsF0HYs/J9VP/kkPyq Lb7f8vhF1jGEumYQq+i6vA/zMeXPh89QRBi4zv+7fN8czMTEMUSuUA4fUsXllvn9zpTb oNTs0rSyCjWN0i9os8RMhLD2GB/4RSyTGYtJ3C4cgYyI4V3KNrtsnzWRHe1iuGq0rETP f9gcFeMRlZs4Yr0ISnFBhZ1ah4Dy1cnHdIrVwf1iMvhktm8ljdI0hWCVws1o6w/Tv+jQ 6Xzw== X-Gm-Message-State: AOJu0YxHxN0Stst47xk2jD9PvhJYT6o2imU2uSR8rtbaorbFJfR4UgM6 Uq5BrfkHZJOYtkA8Z7MhO2+dCTcoSN5Z0PNTkqa1NryFQGXM09XxBs32+vXLdmAbg0QYg3FvXj9 9fwSL X-Gm-Gg: AR+sD10NVThV5NYVyH2xyksTRP0pjWe12HAHumsrXyTMQxATIULEHicVRMYnzjpLTk/ vpJEzIA5zxphGcNgwNyprJhWv2+93zHUDDyZJ1pepxsG/A+6zGOkG/cd9Jvs5peMUO+OksZsUIq uamBktETOZJa8hMNatXZD3T77TqAViJUL6GMLlp8e/9z/S/+UqgCymqwYu2op3UomQqcGpykZy9 hjnzIL+TW6YsfWqvbbZeJu88vxcAygpjlwJ1dest6NdS5SXKW/N3s5k+eCwr9Ix9y4Y6hOAie8Z lAV9B4M+shiqb8SnAhXwm1Ih8yqLR6LkXGzIS5+vSEOvoaGMYv9IDL/0/mcFX0FyNIeQT+4G50Q zTAOx8vuQERA7ozh0AIcs8P0LhVjyJ91wpgbguWuQ1PqjqNp8sFwbznJhgKOCF8UJdE/yLZLCs3 h6CBSmSKzJ6A4Lm6TxzkD40kPMS1RxWRd6nTvLqzECh/CHyJuW7f59b/8xxHhUHj4i0EjQ6bQJj T2qed/P6LxJC39CJPi9Ewb2AHV7Nf5aX/Q+d78xQA44PKBI3LFBzNiIfg0shVFzbwOltaKzAcoX GXJy X-Received: by 2002:a05:600c:3550:b0:499:8777:ccba with SMTP id 5b1f17b1804b1-499b830156bmr79609715e9.12.1787310137158; Fri, 21 Aug 2026 04:02:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/43] target/arm: Implement CPACR.ASEDIS and HCPTR.TASE Date: Fri, 21 Aug 2026 12:00:38 +0100 Message-ID: <20260821110101.3971391-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310216782158500 Content-Type: text/plain; charset="utf-8" When executing at AArch32, there are optional trap bits for Neon instructions in CPACR and HCPTR. We don't currently implement these. Now we have a separate code path for access checks for Neon insns, we can straightforwardly add the check there. We need to track the target EL for Neon-specific trapping in a new TB flag. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/1499 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260817123838.1578060-6-peter.maydell@linaro.org --- target/arm/cpu.h | 6 +++ target/arm/tcg/hflags.c | 82 ++++++++++++++++++++++++++++++++++ target/arm/tcg/translate-vfp.c | 16 +++++-- target/arm/tcg/translate.c | 1 + target/arm/tcg/translate.h | 1 + 5 files changed, 103 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4f07332543d..afc3fda3b83 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2506,6 +2506,12 @@ FIELD(TBFLAG_A32, NS, 10, 1) * This requires an SME trap from AArch32 mode when using NEON. */ FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) +/* + * Target EL for a Neon-disabled exception via CPACR.ASEDIS, HCPTR.TASE. + * If FPEXC_EL indicates a trap to a lower EL than this, that will + * take precedence. + */ +FIELD(TBFLAG_A32, NEONEXC_EL, 12, 2) =20 /* * Bit usage when in AArch32 state, for M-profile only. diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 0716ca98fd7..14824e3dff1 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -164,6 +164,86 @@ static bool sme_fa64(CPUARMState *env, int el) return true; } =20 +static int neon_exception_el(CPUARMState *env, int cur_el) +{ + /* + * Return the EL to trap to for A32 Neon specific traps + * (CPACR.ASEDIS and HCPTR.TASE). In the pseudocode these are + * checked in the same function as the more general trap bits that + * we handle in fp_exception_el(). Fortunately it is always the + * case that if the trap/enable bits specify taking an exception + * to different ELs for the Neon-specific insns and the general fp + * insns then the trap to the lower of the two ELs has priority, + * so we can calculate the two target ELs separately and pick the + * right destination later. Compare AArch32_CheckAdvSIMDOrFPEnabled(). + * + * CPACR doesn't exist before v6, but neither does Neon, so we can + * assume that if we're here testing this then the register exists. + * HCPTR always exists if EL2 is present. + */ + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + bool cpacr_asedis =3D FIELD_EX64(env->cp15.cpacr_el1, CPACR, ASEDIS); + bool hcptr_tase =3D FIELD_EX64(env->cp15.cptr_el[2], HCPTR, TASE); + bool have_aarch32_el3 =3D + arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); + + if (!arm_feature(env, ARM_FEATURE_NEON_TRAPS)) { + /* This CPU doesn't implement the trap bits (Cortex-A8) */ + return 0; + } + + if (arm_feature(env, ARM_FEATURE_EL2) && arm_el_is_aa64(env, 2)) { + /* + * The AArch64 CPTR_EL2 has no equivalent to HCPTR.TASE; only + * an AArch32 EL2 can trap Neon specifically. + */ + hcptr_tase =3D false; + } + + /* + * We know we're in AArch32, but if this is EL0 and EL1 is AArch64 + * then CPACR_EL1 applies rather than CPACR, and it doesn't have + * ASEDIS (instead using the same bit for TCPAC). + */ + if (cur_el =3D=3D 0 && arm_el_is_aa64(env, 1)) { + cpacr_asedis =3D false; + } + + /* CPACR is ignored if E2H+TGE are both set */ + if ((hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + cpacr_asedis =3D false; + } + + /* + * NSACR.NSASEDIS makes the effective values of HCPTR.TASE and + * CPACR.ASEDIS be 1 in NonSecure state. NSACR has no + * effect unless EL3 exists and is AArch32. + */ + if (have_aarch32_el3 && cur_el <=3D 2 && !arm_is_secure_below_el3(env)= ) { + if (FIELD_EX32(env->cp15.nsacr, NSACR, NSASEDIS)) { + cpacr_asedis =3D true; + hcptr_tase =3D true; + } + } + + if (cpacr_asedis) { + if (have_aarch32_el3 && (cur_el =3D=3D 3 || arm_is_secure_below_el= 3(env))) { + /* Trap from Secure PL0 or PL1 to Secure PL1 */ + return 3; + } + if (cur_el <=3D 1) { + /* trap from EL0 or EL1 to EL1 */ + return 1; + } + } + + /* HCPTR.TASE traps to EL2, including for execution at EL2 */ + if (hcptr_tase && cur_el <=3D 2) { + return 2; + } + return 0; +} + static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { @@ -209,6 +289,8 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *en= v, int fp_el, DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); } =20 + DP_TBFLAG_A32(flags, NEONEXC_EL, neon_exception_el(env, el)); + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 6e944a0322a..4db4b14841d 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -306,15 +306,25 @@ bool vfp_access_check(DisasContext *s) =20 /* * Access check for Neon; this is for instructions which can be - * trapped by CPACR.ASEDIS and HCPTR.TASE. Support for those traps - * is optional and we currently do not implement them, so this - * is identical to a VFP access check for now. + * trapped by CPACR.ASEDIS and HCPTR.TASE. */ bool neon_access_check(DisasContext *s) { if (arm_dc_feature(s, ARM_FEATURE_M)) { return vfp_access_check_m(s, false); } else { + /* + * If the Neon-specific trap bits request a trap to a lower EL + * than the general FP trap bits, the trap to the lower EL + * has priority. + */ + if (s->neon_excp_el && + (!s->fp_excp_el || s->neon_excp_el < s->fp_excp_el)) { + uint32_t syn =3D syn_a32_fp_access_trap(1, 0xe, 1, 0); + + gen_exception_insn_el(s, 0, EXCP_UDEF, syn, s->neon_excp_el); + return false; + } return vfp_access_check_a(s, false, true); } } diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 1770428d3cc..7306a1389cc 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -6403,6 +6403,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->vec_stride =3D EX_TBFLAG_A32(tb_flags, VECSTRIDE); dc->sme_trap_nonstreaming =3D EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING); + dc->neon_excp_el =3D EX_TBFLAG_A32(tb_flags, NEONEXC_EL); } dc->lse2 =3D false; /* applies only to aarch64 */ dc->cp_regs =3D cpu->cp_regs; diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index a3d03159ad9..cce84f29c46 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -88,6 +88,7 @@ typedef struct DisasContext { int sve_excp_el; /* SVE exception EL or 0 if enabled */ int sme_excp_el; /* SME exception EL or 0 if enabled */ int zt0_excp_el; /* ZT0 exception EL or 0 if enabled */ + int neon_excp_el; /* A32 Neon exception EL or 0 if enabled */ int vl; /* current vector length in bytes */ int svl; /* current streaming vector length in bytes */ int max_svl; /* maximum implemented streaming vector length */ --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310186; cv=none; d=zohomail.com; s=zohoarc; b=Dq/MaAF8W2sAdmnYxLSlapurjQmcdXT8hPUbvhIyu+lFBDqBy9AqnfSIiQJKPrzgaGUuPRSTQs7L6l2KKbPRYkIkwuOjWDPUDHXclb/mzi6QFmjfWlLHBvaOjxtKQ/KS86LqXHUT7HFbxWv3OtTVsQixC+rfQAO0o9dnR7spbcw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310186; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ZhTa4gPey37Kb/POJTgaKRANSs+4AZwBwc9vJ063Ahw=; b=imcu4MY4m1b0JjVDl2CcLHkfXS84z5u5MlRHBWmBG0F+10Yk2GqS6FnRbgn7nDXdGFz83a7/s3ocqrXYvCQZiYFTvg5/MpszN2dgncpE2EeOJ3/QjmYk/gY5yfu/8h9BvB3HgF2nqarborg3rMVCHAqhrkFT/wW2yY/znRPyiVU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310186175919.9417529544953; Fri, 21 Aug 2026 04:03:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN16-0000h5-Fx; Fri, 21 Aug 2026 07:02:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN0z-0000WU-RJ for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:27 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN0u-0007U5-Qj for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:22 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-499840a2575so4775435e9.3 for ; Fri, 21 Aug 2026 04:02:20 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310139; x=1787914939; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=ZhTa4gPey37Kb/POJTgaKRANSs+4AZwBwc9vJ063Ahw=; b=qXjcDXUF5UaXH5cmBFdVm/vFgnKTT0HiytGGEaHvk7ff2RglLXy0qfecqpGPo+Wc27 oFb4PkV6aZ5W+Fk+GcbYeLBef/pWSsV16rMS9BeN/mtSTaoZ6AIVwxx+GI7NBVsDun6D P8VaCgC0Qqj1HAZITNplC7ZdJkkys28/ASxkcjyzJxOcT1JbJilu86t3ViLVBTMGYByO /kE2DlEEscD0d54XakErXEGVskbRd4wjsTYE5DsgaXgIkTvuB9+MD/bX5Cvh37rFRlwe LSkT0kgcPAyJksOORO1ADDxuWqBvnYnuFiTVpK98ZHab7PtVvQ2zyJqpzPeXLeFoS79G 9s0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310139; x=1787914939; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=ZhTa4gPey37Kb/POJTgaKRANSs+4AZwBwc9vJ063Ahw=; b=c/db8cMdIxxGMC+bQY3hO++A12ubk/7oIqhjkmnVK3mgIWFnA+Eyj2t9NBUaLTSNYi TE+lTXXLswgxQgqNBEPBG+oq/YdZdpaUGyoRlx8lMQ/w0ktIROVvWSjexdfoC1PTLjdL 9U3DcptYTy+ayEL8sXYDebWR3wSdz7wB1cNOsy2P3oLvku14MdEY3ZYh9om9/gGJpFDk +x+b2W4vT3ifXvRz8RLfngasbma7rEW57jmKuoFrnPteyggA56QPwXKo3JIzOEDHQIFw RwxlMH3VriXdo7rdPTSslCFckh+Kpuf99DKW1JWoGnNGw4dorTCs86r46LiaeyQyTr7x 6aUA== X-Gm-Message-State: AOJu0YwUWWpxH5tPh7w/qX1oSVoQ0/deBPTCUYCxGk04U7B+S2ywBpHM yhcQOx41T92yw6AnzBvr0Y6I6b4W9Zt8He6czO+K42ieueECnz3dX1SCwaj+ms7Vtq0QXR0xKXh OsUFX X-Gm-Gg: AR+sD10ACt5qhs0jnZScuU8TKq65+jHC+iZb1AAi6w0Bx1rupht1Es7CdBAwP+V4lng 4/jAqUU8K3Lh0c5qSpQA49kvVnL3fKWqLd6IioM2hoJyM2rW9CZS+MaCMM2sAJT5Dalml4JrQC7 W8vHfLfBY9VSJeBqVyCxmnty8gfjg0CDyUmJ/fTQdThPiYTm5Xm6WIO/mfOVU8wWEBsffJdr7Vf gXsYmAxnPTavKjsmU6elvjCclJLg/NL/+/iaKc0VRN4/QP7J7dMWLcgu3M/ncaFDmCWsaL1PlZD o4mL87YJsPBYMw5ZOnu1S4CcxnBOspRG2mRZaRg2447e33F0ZQCKULs0W5zd0/F1cVg9icGjAVf 87fuSvLyOz3ZMZzOsNCtmSXahZrzBiM498A/nLJDBbMP3Wgl+TtajCfHzyxpqwrGIBZcg1swlhn cuYMzQGr90kH+2JQhmf9wUPOVaz/f5eu2he+T189Orr2Ezp4igwR4myEOwJS6D6ETrppYgSTBdG nKqgj5N3c1Ai3jRzT23i6h9acxMsVt4Uc0w+l4oBJThxeh48daM+2hn1PHyebBiHuKaHQ== X-Received: by 2002:a05:600c:3492:b0:495:5890:8f6c with SMTP id 5b1f17b1804b1-499b8339418mr82912465e9.7.1787310139298; Fri, 21 Aug 2026 04:02:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/43] target/arm: Pull VFP dregs checks out into a function Date: Fri, 21 Aug 2026 12:00:39 +0100 Message-ID: <20260821110101.3971391-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310186541158500 Content-Type: text/plain; charset="utf-8" Currently we directly call dc_isar_feature(aa32_simd_r32, s) for VFP insns that use D16-D31 to see if they should UNDEF. For some v7A CPUs (Cortex-A7, Cortex-A9) there is also a CPACR.D32DIS trap bit that will make VFP (and only VFP, not Neon) insns using D16-D31 UNDEF. Abstract out the register check for VFP insns into a new function which will provide us a place where we can make this check. Since D32DIS takes precedence over traps to EL2 and EL3 and simply makes the insns UNDEF, we are OK to check it at the same point when we do the CPU feature check, rather than having to wait until vfp_access_check(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260817123838.1578060-7-peter.maydell@linaro.org --- target/arm/tcg/translate-vfp.c | 70 ++++++++++++++++++++-------------- 1 file changed, 42 insertions(+), 28 deletions(-) diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 4db4b14841d..a8d470ec49c 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -207,6 +207,23 @@ static void gen_update_fp_context(DisasContext *s) } } =20 +/* + * Return true if a VFP insn is OK to access the registers indicated + * by regmask, false if it should UNDEF. This checks whether the + * D16-D31 regs are implemented by the CPU. Eventually we will also check + * CPACR.D32DIS. + * Note that Neon insns accessing D16..D31 do not need to check D32DIS, + * so this function is for VFP insns only. + * + * @regmask should be the logical OR of the VFP Dregs being accessed. + */ +static bool vfp_dregs_ok(DisasContext *s, int dregmask) +{ + int invalid_dreg_mask =3D dc_isar_feature(aa32_simd_r32, s) ? 0 : 0x10; + + return !(dregmask & invalid_dreg_mask); +} + /* * Check that VFP access is enabled, A-profile specific version. * @@ -347,8 +364,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (sz =3D=3D 3 && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { + if (sz =3D=3D 3 && !vfp_dregs_ok(s, a->vm | a->vn | a->vd)) { return false; } =20 @@ -473,8 +489,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (sz =3D=3D 3 && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vd) & 0x10)) { + if (sz =3D=3D 3 && !vfp_dregs_ok(s, a->vm | a->vd)) { return false; } =20 @@ -541,7 +556,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (sz =3D=3D 3 && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10= )) { + if (sz =3D=3D 3 && !vfp_dregs_ok(s, a->vm)) { return false; } =20 @@ -662,7 +677,7 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_= to_gp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { + if (!vfp_dregs_ok(s, a->vn & 0x10)) { return false; } =20 @@ -709,7 +724,7 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMO= V_from_gp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { + if (!vfp_dregs_ok(s, a->vn & 0x10)) { return false; } =20 @@ -745,7 +760,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { + if (!vfp_dregs_ok(s, a->vn)) { return false; } =20 @@ -1030,7 +1045,7 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMO= V_64_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!vfp_dregs_ok(s, a->vm)) { return false; } =20 @@ -1132,7 +1147,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_V= LDR_VSTR_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!vfp_dregs_ok(s, a->vd)) { return false; } =20 @@ -1261,7 +1276,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd + n) > 16) { + if (!vfp_dregs_ok(s, a->vd + n - 1)) { return false; } =20 @@ -1513,7 +1528,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { + if (!vfp_dregs_ok(s, vd | vn | vm)) { return false; } =20 @@ -1685,7 +1700,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) /* Note that the caller must check the aa32_fpdp_v2 feature. */ =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { + if (!vfp_dregs_ok(s, vd | vm)) { return false; } =20 @@ -2252,8 +2267,7 @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a= , bool neg_n, bool neg_d) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!vfp_dregs_ok(s, a->vd | a->vn | a->vm)) { return false; } =20 @@ -2380,7 +2394,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { + if (!vfp_dregs_ok(s, vd)) { return false; } =20 @@ -2555,7 +2569,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_d= p *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { + if (!vfp_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -2621,7 +2635,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!vfp_dregs_ok(s, a->vd)) { return false; } =20 @@ -2702,7 +2716,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!vfp_dregs_ok(s, a->vm)) { return false; } =20 @@ -2777,7 +2791,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRIN= TR_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { + if (!vfp_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -2856,7 +2870,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRIN= TZ_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { + if (!vfp_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -2930,7 +2944,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRIN= TX_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { + if (!vfp_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -2956,7 +2970,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!vfp_dregs_ok(s, a->vd)) { return false; } =20 @@ -2982,7 +2996,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!vfp_dregs_ok(s, a->vm)) { return false; } =20 @@ -3063,7 +3077,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!vfp_dregs_ok(s, a->vd)) { return false; } =20 @@ -3100,7 +3114,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!vfp_dregs_ok(s, a->vm)) { return false; } =20 @@ -3240,7 +3254,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!vfp_dregs_ok(s, a->vd)) { return false; } =20 @@ -3369,7 +3383,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!vfp_dregs_ok(s, a->vm)) { return false; } =20 --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Whether the CPU implements this or not is IMPDEF, and the only two CPUs we implement which have this are the Cortex-A7 and Cortex-A9. In v8A the bit is no longer defined at all. Since the only kind of trapping that needs to be done is a simple UNDEF, this is straightforward enough to implement. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/1499 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260817123838.1578060-8-peter.maydell@linaro.org --- target/arm/cpu.h | 4 ++++ target/arm/helper.c | 19 ++++++++++++++++--- target/arm/tcg/cpu32.c | 2 ++ target/arm/tcg/hflags.c | 20 ++++++++++++++++++++ target/arm/tcg/translate-vfp.c | 7 ++----- target/arm/tcg/translate.c | 6 ++++++ target/arm/tcg/translate.h | 1 + 7 files changed, 51 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index afc3fda3b83..e8dfc3179f2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2184,6 +2184,8 @@ enum arm_features { * ARM_FEATURE_NEON CPUs except the Cortex-A8. */ ARM_FEATURE_NEON_TRAPS, + /* Does the CPU implement CPACR.D32DIS ? */ + ARM_FEATURE_D32DIS, }; =20 static inline int arm_feature(const CPUARMState *env, int feature) @@ -2512,6 +2514,8 @@ FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) * take precedence. */ FIELD(TBFLAG_A32, NEONEXC_EL, 12, 2) +/* Should VFP insns touching D16..D31 UNDEF? (CPACR.D32DIS) */ +FIELD(TBFLAG_A32, D32DIS, 14, 1) =20 /* * Bit usage when in AArch32 state, for M-profile only. diff --git a/target/arm/helper.c b/target/arm/helper.c index 2dfbeae0efd..4f30a94ecd3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -573,8 +573,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, */ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { /* VFP coprocessor: cp10 & cp11 [23:20] */ - mask |=3D R_CPACR_D32DIS_MASK | - R_CPACR_CP11_MASK | + mask |=3D R_CPACR_CP11_MASK | R_CPACR_CP10_MASK; =20 if (!arm_feature(env, ARM_FEATURE_NEON)) { @@ -596,6 +595,13 @@ static void cpacr_write(CPUARMState *env, const ARMCPR= egInfo *ri, if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ value |=3D R_CPACR_D32DIS_MASK; + mask |=3D R_CPACR_D32DIS_MASK; + } else if (arm_feature(env, ARM_FEATURE_D32DIS)) { + /* + * Bit is present unless CPU doesn't implement D32DIS, + * in which case it is RAZ/WI. + */ + mask |=3D R_CPACR_D32DIS_MASK; } } value &=3D mask; @@ -605,7 +611,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR= .CP10 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. * Similarly, if NSACR.NSASEDIS is 1 then CPACR.ASEDIS ignores writes - * and reads as 1. + * and reads as 1, and NSACR.NSD32DIS makes CPACR.D32DIS behave as RAO= /WI. */ if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && !arm_is_secure(env)) { @@ -617,6 +623,10 @@ static void cpacr_write(CPUARMState *env, const ARMCPR= egInfo *ri, mask =3D R_CPACR_ASEDIS_MASK; value =3D (value & ~mask) | (env->cp15.cpacr_el1 & mask); } + if (FIELD_EX32(env->cp15.nsacr, NSACR, NSD32DIS)) { + mask =3D R_CPACR_D32DIS_MASK; + value =3D (value & ~mask) | (env->cp15.cpacr_el1 & mask); + } } =20 env->cp15.cpacr_el1 =3D value; @@ -639,6 +649,9 @@ static uint64_t cpacr_read(CPUARMState *env, const ARMC= PRegInfo *ri) if (FIELD_EX32(env->cp15.nsacr, NSACR, NSASEDIS)) { value |=3D R_CPACR_ASEDIS_MASK; } + if (FIELD_EX32(env->cp15.nsacr, NSACR, NSD32DIS)) { + value |=3D R_CPACR_D32DIS_MASK; + } } return value; } diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 724a9549347..bc07e33877a 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -336,6 +336,7 @@ static void cortex_a9_initfn(Object *obj) */ set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_CBAR); + set_feature(&cpu->env, ARM_FEATURE_D32DIS); cpu->midr =3D 0x410fc090; cpu->reset_fpsid =3D 0x41033090; cpu->isar.mvfr0 =3D 0x11110222; @@ -403,6 +404,7 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); + set_feature(&cpu->env, ARM_FEATURE_D32DIS); cpu->midr =3D 0x410fc075; cpu->reset_fpsid =3D 0x41023075; cpu->isar.mvfr0 =3D 0x10110222; diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 14824e3dff1..296ec8101ab 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -244,6 +244,24 @@ static int neon_exception_el(CPUARMState *env, int cur= _el) return 0; } =20 +static bool arm_d32dis(CPUARMState *env, int cur_el) +{ + bool cpacr_d32dis =3D FIELD_EX64(env->cp15.cpacr_el1, CPACR, D32DIS); + + if (!arm_feature(env, ARM_FEATURE_D32DIS)) { + return false; + } + + /* If NSACR.NSD32DIS is set, CPACR.D32DIS acts as 1 in NonSecure */ + if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + cur_el <=3D 2 && !arm_is_secure_below_el3(env))) { + if (FIELD_EX32(env->cp15.nsacr, NSACR, NSD32DIS)) { + cpacr_d32dis =3D true; + } + } + return cpacr_d32dis; +} + static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { @@ -291,6 +309,8 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *en= v, int fp_el, =20 DP_TBFLAG_A32(flags, NEONEXC_EL, neon_exception_el(env, el)); =20 + DP_TBFLAG_A32(flags, D32DIS, arm_d32dis(env, el)); + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index a8d470ec49c..0a87a0165bd 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -210,8 +210,7 @@ static void gen_update_fp_context(DisasContext *s) /* * Return true if a VFP insn is OK to access the registers indicated * by regmask, false if it should UNDEF. This checks whether the - * D16-D31 regs are implemented by the CPU. Eventually we will also check - * CPACR.D32DIS. + * D16-D31 regs are implemented by the CPU and not disabled by CPACR.D32DI= S. * Note that Neon insns accessing D16..D31 do not need to check D32DIS, * so this function is for VFP insns only. * @@ -219,9 +218,7 @@ static void gen_update_fp_context(DisasContext *s) */ static bool vfp_dregs_ok(DisasContext *s, int dregmask) { - int invalid_dreg_mask =3D dc_isar_feature(aa32_simd_r32, s) ? 0 : 0x10; - - return !(dregmask & invalid_dreg_mask); + return !(dregmask & s->invalid_vfp_dreg_mask); } =20 /* diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 7306a1389cc..90eb6f30058 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -6342,6 +6342,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ARMCPU *cpu =3D env_archcpu(env); CPUARMTBFlags tb_flags =3D arm_tbflags_from_tb(dc->base.tb); uint32_t condexec, core_mmu_idx; + bool d32dis =3D false; =20 dc->isar =3D &cpu->isar; dc->condjmp =3D 0; @@ -6404,7 +6405,12 @@ static void arm_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) dc->sme_trap_nonstreaming =3D EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING); dc->neon_excp_el =3D EX_TBFLAG_A32(tb_flags, NEONEXC_EL); + d32dis =3D EX_TBFLAG_A32(tb_flags, D32DIS); } + + dc->invalid_vfp_dreg_mask =3D + (d32dis || !dc_isar_feature(aa32_simd_r32, dc)) ? 0x10 : 0; + dc->lse2 =3D false; /* applies only to aarch64 */ dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index cce84f29c46..b08bded3981 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -94,6 +94,7 @@ typedef struct DisasContext { int max_svl; /* maximum implemented streaming vector length */ int max_any_vl; /* maximum implemented vector length */ bool vfp_enabled; /* FP enabled via FPSCR.EN */ + int invalid_vfp_dreg_mask; /* mask for whether VFP D16..D31 should UND= EF */ int vec_len; int vec_stride; bool v7m_handler_mode; --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310227; cv=none; d=zohomail.com; s=zohoarc; b=X77WPgNuVpotb+U9pkW1XdbT9mSYdJM2PSek3gOFoRclTXk1Kl27K65O53USoGlUYaPkLw7YuUyQKZVStZRXkp0yyYZtELlHTVcHaz6U61s7qfPDT6yL4iR6+DALErbil7it5beyWB6aa3bFqwgtduqdDz7mQmMFPPpNF3TCZOw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310227; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=pwfXB2bdg1qQX8wSnPwGkq8fuWB+6wmYD1feA0ku2tc=; b=G1Ero+KjzxbYJKDoWMPAeNWNwxTo8T2UzyD+aTtbKkvZQFgdWmXWiPIMV/j5Jc8o8Tu5IRSoKbAGlVGmNY95+Fq/PElHneImdGv1fjPMlKmHcuXD2gOvvS8c3YZHeXhbUHhPtiuvIi1MWgMakdHADeA1ja6GIJaSNHyCvuwhqiQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310227305648.0983596554066; Fri, 21 Aug 2026 04:03:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1I-00010u-Jj; Fri, 21 Aug 2026 07:02:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN12-0000g8-Nt for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:30 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN0z-0007UW-H6 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:28 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-499a4d1d7f1so5211795e9.3 for ; Fri, 21 Aug 2026 04:02:23 -0700 (PDT) Received: from lanath.. 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We don't have any extra checks that we need to add here, but having a neon_dregs_ok() is cleaner and means the Neon decode isn't oddly different to the VFP decode. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260817123838.1578060-9-peter.maydell@linaro.org --- target/arm/tcg/translate-neon.c | 118 ++++++++++++++------------------ target/arm/tcg/translate.c | 1 + target/arm/tcg/translate.h | 1 + 3 files changed, 53 insertions(+), 67 deletions(-) diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neo= n.c index 50a44511d98..f811940f642 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -118,11 +118,24 @@ static void neon_store_element64(int reg, int ele, Me= mOp size, TCGv_i64 var) } } =20 +/* + * Return true if a Neon insn is OK to access the registers indicated + * by regmask, false if it should UNDEF. This checks whether the + * D16-D31 regs are implemented by the CPU. + * Note that Neon insns accessing D16..D31 do not need to check D32DIS. + * + * @regmask should be the logical OR of the Dregs being accessed. + */ +static bool neon_dregs_ok(DisasContext *s, int dregmask) +{ + return !(dregmask & s->invalid_neon_dreg_mask); +} + static bool do_neon_ddda(DisasContext *s, int q, int vd, int vn, int vm, int data, gen_helper_gvec_4 *fn_gvec) { /* UNDEF accesses to D16-D31 if they don't exist. */ - if (((vd | vn | vm) & 0x10) && !dc_isar_feature(aa32_simd_r32, s)) { + if (!neon_dregs_ok(s, vd | vn | vm)) { return false; } =20 @@ -152,7 +165,7 @@ static bool do_neon_ddda_env(DisasContext *s, int q, in= t vd, int vn, int vm, int data, gen_helper_gvec_4_ptr *fn_gvec) { /* UNDEF accesses to D16-D31 if they don't exist. */ - if (((vd | vn | vm) & 0x10) && !dc_isar_feature(aa32_simd_r32, s)) { + if (!neon_dregs_ok(s, vd | vn | vm)) { return false; } =20 @@ -184,7 +197,7 @@ static bool do_neon_ddda_fpst(DisasContext *s, int q, i= nt vd, int vn, int vm, gen_helper_gvec_4_ptr *fn_gvec_ptr) { /* UNDEF accesses to D16-D31 if they don't exist. */ - if (((vd | vn | vm) & 0x10) && !dc_isar_feature(aa32_simd_r32, s)) { + if (!neon_dregs_ok(s, vd | vn | vm)) { return false; } =20 @@ -240,8 +253,7 @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vn | a->vm)) { return false; } =20 @@ -310,8 +322,7 @@ static bool trans_VFML(DisasContext *s, arg_VFML *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - (a->vd & 0x10)) { + if (!neon_dregs_ok(s, a->vd)) { return false; } =20 @@ -398,14 +409,14 @@ static bool trans_VDOT_b16_scal(DisasContext *s, arg_= VDOT_b16_scal *a) static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a) { int opr_sz; + int dregmask =3D a->vd | (a->q ? a->vn : 0); =20 if (!dc_isar_feature(aa32_fhm, s)) { return false; } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) { + if (!neon_dregs_ok(s, dregmask)) { return false; } =20 @@ -478,7 +489,7 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_V= LDST_multiple *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!neon_dregs_ok(s, a->vd)) { return false; } if (a->itype > 10) { @@ -580,7 +591,7 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VL= D_all_lanes *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!neon_dregs_ok(s, a->vd)) { return false; } =20 @@ -672,7 +683,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLD= ST_single *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!neon_dregs_ok(s, a->vd)) { return false; } =20 @@ -789,8 +800,7 @@ static bool do_3same(DisasContext *s, arg_3same *a, GVe= cGen3Fn fn) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vn | a->vm)) { return false; } =20 @@ -1067,8 +1077,7 @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_s= hift *a, GVecGen2iFn *fn) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -1117,8 +1126,7 @@ static bool do_2shift_narrow_64(DisasContext *s, arg_= 2reg_shift *a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -1168,8 +1176,7 @@ static bool do_2shift_narrow_32(DisasContext *s, arg_= 2reg_shift *a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -1293,8 +1300,7 @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_sh= ift *a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -1383,8 +1389,7 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift= *a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -1428,7 +1433,7 @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm= *a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!neon_dregs_ok(s, a->vd)) { return false; } =20 @@ -1485,8 +1490,7 @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff= *a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vn | a->vm)) { return false; } =20 @@ -1592,8 +1596,7 @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *= a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vn | a->vm)) { return false; } =20 @@ -1682,8 +1685,7 @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vn | a->vm)) { return false; } =20 @@ -1944,8 +1946,7 @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3di= ff *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vn | a->vm)) { return false; } =20 @@ -2027,8 +2028,7 @@ static bool do_2scalar(DisasContext *s, arg_2scalar *= a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vn | a->vm)) { return false; } =20 @@ -2125,8 +2125,7 @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2s= calar *a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vn | a->vm)) { return false; } =20 @@ -2222,8 +2221,7 @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2sca= lar *a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vn | a->vm)) { return false; } =20 @@ -2293,8 +2291,7 @@ static bool do_2scalar_long(DisasContext *s, arg_2sca= lar *a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vn | a->vm)) { return false; } =20 @@ -2438,8 +2435,7 @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vn | a->vm)) { return false; } =20 @@ -2507,8 +2503,7 @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vn | a->vm)) { return false; } =20 @@ -2546,8 +2541,7 @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VD= UP_scalar *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -2577,8 +2571,7 @@ static bool do_zip_uzp(DisasContext *s, arg_2misc *a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -2647,8 +2640,7 @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -2711,8 +2703,7 @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -2755,8 +2746,7 @@ static bool trans_VCVT_B16_F32(DisasContext *s, arg_2= misc *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -2795,8 +2785,7 @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg_2= misc *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -2841,8 +2830,7 @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2= misc *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -2887,8 +2875,7 @@ static bool do_2misc_vec(DisasContext *s, arg_2misc *= a, GVecGen2Fn *fn) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -3015,8 +3002,7 @@ static bool do_2misc(DisasContext *s, arg_2misc *a, N= eonGenOneOpFn *fn) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -3219,8 +3205,7 @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 @@ -3292,8 +3277,7 @@ static bool trans_VTRN(DisasContext *s, arg_2misc *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { + if (!neon_dregs_ok(s, a->vd | a->vm)) { return false; } =20 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 90eb6f30058..c866148383f 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -6410,6 +6410,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) =20 dc->invalid_vfp_dreg_mask =3D (d32dis || !dc_isar_feature(aa32_simd_r32, dc)) ? 0x10 : 0; + dc->invalid_neon_dreg_mask =3D !dc_isar_feature(aa32_simd_r32, dc) ? 0= x10 : 0; =20 dc->lse2 =3D false; /* applies only to aarch64 */ dc->cp_regs =3D cpu->cp_regs; diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index b08bded3981..31f52a34a68 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -95,6 +95,7 @@ typedef struct DisasContext { int max_any_vl; /* maximum implemented vector length */ bool vfp_enabled; /* FP enabled via FPSCR.EN */ int invalid_vfp_dreg_mask; /* mask for whether VFP D16..D31 should UND= EF */ + int invalid_neon_dreg_mask; /* ditto, for Neon */ int vec_len; int vec_stride; bool v7m_handler_mode; --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Move the boot info into the existing AspeedMachineState. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260816131300.51799-2-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 17 +++++++---------- include/hw/arm/aspeed.h | 2 ++ 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a9238e6217d..8fa16b3831c 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -24,10 +24,6 @@ #include "hw/core/qdev-clock.h" #include "system/system.h" =20 -static struct arm_boot_info aspeed_board_binfo =3D { - .board_id =3D -1, /* device-tree-only board */ -}; - #define AST_SMP_MAILBOX_BASE 0x1e6e2180 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) @@ -206,13 +202,14 @@ static void aspeed_machine_init(MachineState *machine) memory_region_add_subregion(get_system_memory(), AST_SMP_MAILBOX_BASE, smpboot); =20 - aspeed_board_binfo.write_secondary_boot =3D aspeed_write_smpboot; - aspeed_board_binfo.secondary_cpu_reset_hook =3D aspeed_reset_secon= dary; - aspeed_board_binfo.smp_loader_start =3D AST_SMP_MBOX_CODE; + bmc->bootinfo.write_secondary_boot =3D aspeed_write_smpboot; + bmc->bootinfo.secondary_cpu_reset_hook =3D aspeed_reset_secondary; + bmc->bootinfo.smp_loader_start =3D AST_SMP_MBOX_CODE; } =20 - aspeed_board_binfo.ram_size =3D machine->ram_size; - aspeed_board_binfo.loader_start =3D sc->memmap[ASPEED_DEV_SDRAM]; + bmc->bootinfo.board_id =3D -1; /* device-tree-only board */ + bmc->bootinfo.ram_size =3D machine->ram_size; + bmc->bootinfo.loader_start =3D sc->memmap[ASPEED_DEV_SDRAM]; =20 if (amc->i2c_init) { amc->i2c_init(bmc); @@ -248,7 +245,7 @@ static void aspeed_machine_init(MachineState *machine) aspeed_load_vbootrom(bmc->soc, bios_name, &error_abort); } =20 - arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); + arm_load_kernel(ARM_CPU(first_cpu), machine, &bmc->bootinfo); } =20 void aspeed_create_pca9552(AspeedSoCState *soc, int bus_id, int addr) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index a00238ed74a..54f0d7643d7 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -12,6 +12,7 @@ #include "hw/core/boards.h" #include "qom/object.h" #include "hw/arm/aspeed_soc.h" +#include "hw/arm/boot.h" =20 typedef struct AspeedMachineState AspeedMachineState; =20 @@ -42,6 +43,7 @@ struct AspeedMachineState { char *fmc_model; char *spi_model; uint32_t hw_strap1; + struct arm_boot_info bootinfo; }; =20 struct AspeedMachineClass { --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310184; cv=none; d=zohomail.com; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310145; x=1787914945; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=ZW+43f0HNk0MlxWq71xFTJBbmIurAt5Kb0ZGOXTKsqY=; b=XHhDhJMAoVxz+ZRkz4nPmy225bSXfQ98qvyP43izXJfDmPd7AyipddGs5MdN3EDOo4 o9yk+PXv1aUCARjy2te9kBPNwN3asHw7sv+krcqXmtuWQ0Wy4JUytqIfSMzw7HTyaReo ZXYgVD3YV+az75e29lwfcw3nFKgRumgOiw2szJFbbF2zyw6U8dnf3uLrtE4TNyOVk/pn gck9+anTgWtxxtp/IrkeJ+9zyNq4IBKeJx39HQ9uatrdPL0OeVlkH2DHWuGxWN6jri4r Ks5h9Q8xPVjg4YKoDI8uUnF28VSMlQEXL7FZYBUz6r/uBXsaDfEfPcxBwX5DKFZCa8Uh s0XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310145; x=1787914945; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=ZW+43f0HNk0MlxWq71xFTJBbmIurAt5Kb0ZGOXTKsqY=; b=ApJJeFc2q4JxRH87bRZLA/w3dwc4fRK3ZIYGxNmkB2Vwb6Yo4GdX3ZY7LybBZsLoN9 tKT9utS9H2VBkglF050tFYQJTptvByGGcKCsBMCuvXYRswlXCxUm0QlP5sHQMPlJPHAM 8xFVLpdmzd8McYWzFlBmgpa9PFDFV+XD6bz9F1R3fcALpzZKMYxPkfCP5Ca8V2MkPcHH 8+lYCKIZFH59fLjOHoDWSUgetp4EOZjRjWO81KV48EGUBzfq2zceb00M1WjVmgO05bYG q3rLVF8DYeTTS+sr6W++XIpCAyFvy1YhqVXn3UspiVrzsUMO5OsaRLlj/1lZwHYr+w7h 3H9w== X-Gm-Message-State: AOJu0Yzzz+MqiwZyZ/TD+lKfWKB9DKuIpe7Hg28IUMJRVfeGTod8/8Wq obs6Hy7JhJ3uucoA+al1axsmfc+5seB6vXMkSyh9jJFadkKIqR+vAzKQDdmPFnBUhsIo1Pwacmo VP+rL X-Gm-Gg: AR+sD13vKT+OQClslTVL9Wlwb+WRpU6zt93ekYMDJdwaROjhVXrwDfj+pNYFl581XOL qe7PuRBOOMZNfbxvs5O4LknLce2aK/PgkOjU05t1v53T0BFxfCIacXG40fN/9Wg4Q9o4AnAFPco +mg/TG1BwlIsypVLtoRBOXTAcmJKRKEv9KReeeerHavTgqzy5KCwS5iAz+U1PxUu6CTNq4iQkUL s4jl3plPIbe9b0zg3T/8RU8O/qk4NbPzyoOPmZc6BlWa75PqME5WpdHEjQWEQjCSJPxT2L3XyCL 1kDhTLKDo+Blz3EfwcHHMaSLqHI9GzRkWIn6wjR29QuePz5bkz2eVmUlolLNR4vTPoZk0gdrYNV xHJuq2q1Hb8J+EYHVMXKwsIFkFAILI1bFkKLlJUDibwLq5fQ/kgFwF0YgoOUUi5X3BDPgcUFlHQ 8DjkxF4V4XLoA64+U9kuNCN95y7hWAgjEM9wlLClPy/HCjePSnanlnPnPTxzpO94sn7aThVJxwo xmP8VLjHB1rTXstOTvR1ChDLX5HT+2dEezYs5nspny95knbPGYhKBw8T8sO1zbIDHOL+2+qV4M2 5wz1 X-Received: by 2002:a05:600c:1548:b0:495:5fdf:2075 with SMTP id 5b1f17b1804b1-499b8277214mr79175265e9.0.1787310144998; Fri, 21 Aug 2026 04:02:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/43] hw/arm: aspeed_ast27x0-fc: Store boot info in the machine state Date: Fri, 21 Aug 2026 12:00:43 +0100 Message-ID: <20260821110101.3971391-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310186475158500 From: Bin Meng arm_load_kernel() keeps a pointer to the boot info struct for the lifetime of the VM, so the struct logically belongs to the machine rather than to a file scoped static object. Move the boot info into the existing Ast2700FCState. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260816131300.51799-3-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/aspeed_ast27x0-fc.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index 058cea42edc..ceeae336df1 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -27,10 +27,6 @@ #define TYPE_AST2700FC MACHINE_TYPE_NAME("ast2700fc") OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700FC); =20 -static struct arm_boot_info ast2700fc_board_info =3D { - .board_id =3D -1, /* device-tree-only board */ -}; - struct Ast2700FCState { MachineState parent_obj; =20 @@ -46,6 +42,8 @@ struct Ast2700FCState { Aspeed27x0SoCState ca35; Aspeed27x0CoprocessorState ssp; Aspeed27x0CoprocessorState tsp; + + struct arm_boot_info bootinfo; }; =20 #define AST2700FC_BMC_RAM_SIZE (2 * GiB) @@ -114,8 +112,9 @@ static bool ast2700fc_ca35_init(MachineState *machine, = Error **errp) aspeed_board_init_flashes(&soc->fmc, AST2700FC_FMC_MODEL, 2, 0); aspeed_board_init_flashes(&soc->spi[0], AST2700FC_SPI_MODEL, 1, 2); =20 - ast2700fc_board_info.ram_size =3D machine->ram_size; - ast2700fc_board_info.loader_start =3D sc->memmap[ASPEED_DEV_SDRAM]; + s->bootinfo.ram_size =3D machine->ram_size; + s->bootinfo.loader_start =3D sc->memmap[ASPEED_DEV_SDRAM]; + s->bootinfo.board_id =3D -1; /* device-tree-only board */ =20 dev =3D ssi_get_cs(soc->fmc.spi, 0); fmc0 =3D dev ? m25p80_get_blk(dev) : NULL; @@ -129,7 +128,7 @@ static bool ast2700fc_ca35_init(MachineState *machine, = Error **errp) bios_name =3D machine->firmware ?: VBOOTROM_FILE_NAME; aspeed_load_vbootrom(soc, bios_name, errp); =20 - arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info); + arm_load_kernel(ARM_CPU(first_cpu), machine, &s->bootinfo); =20 return true; } --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310315; cv=none; d=zohomail.com; s=zohoarc; b=hhawS5SQPhOXRpBpIPYREniLYWxLNSQGHE3mTexFmKSrIysKsQNSyqchrHdYJAUbvdDC9YX4hnUc15GBKpWs5Da1kbIs7zpn4lncMHNU5vnp8k0ZVkaVwWL0dLxorhaHFA3PH2sxkFDu2zkWAUSlvk4RvXh8UGR+qT+n4NWFdgc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310315; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=tdwp4aUV0FuWOV3NHOQRHCUGQ71NyoUxAiznLkuyZp4=; b=YutIXt8Tcimc3pWrBelSsKzvGDN1lb2ucqcPbqnMCXPhEAcOOj72NAF+R9NlWHH/jsJhGbIkPulj9FICMP+L4Eb98p96e2rdJGRs6AcmyV+HLCOL6ux1QOw/rhzyZZaE6r9lrtQ2vb+gl04KKKK7uNDVzX/KitABKjKQ8Cd4eYI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310315502785.2953223998991; Fri, 21 Aug 2026 04:05:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1M-0001QU-3i; Fri, 21 Aug 2026 07:02:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN14-0000j8-TG for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:32 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN12-0007VL-95 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:30 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-490cf322ed0so7648575e9.1 for ; Fri, 21 Aug 2026 04:02:27 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310147; x=1787914947; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=tdwp4aUV0FuWOV3NHOQRHCUGQ71NyoUxAiznLkuyZp4=; b=eYAL37Vb0p1Efp/JVEhRYFotQywEI/x7XSK88+fFxaRrP+0K8A5h0XZ15LnIws18kp dNrToZnnwCtsZIa9Rv74bjghEhAA8XfRU/XKXeoaRamLlfFe6xFauWi4Uk5+qei0xepZ tn/Z1gH4rOtwkxIrXznWpbpAZ8SByb3VsWSBc1hk1LluHXIkCxXBNdffT650XESMkycJ YlLMJOgd30It68ZQvf3uOw/c4wvlNEXXlD5SpoU8VdbuAZyNqcjGbCAFIC7k1F9cUhKN l3wc4KJrrJOf/WV/g0cUG6fyOnCLc3pO08CVc4gu2zXFbJ+KbclcXMpgom647jzTCSVQ AU2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310147; x=1787914947; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=tdwp4aUV0FuWOV3NHOQRHCUGQ71NyoUxAiznLkuyZp4=; b=KC13klx1Sy5D2b5xlq15olxF3c1frlJiv2V3QBEyMme7UAa5GqPGYO/tDbVQz7vSpU AL8ZfLd/VOUmomxzCrWWHmppyJpWThXMAJIGHTQQ/L5oKhThCC8cH+mtKN8N5QY6Nqhx YyrjAbGJnExj4QVforTnq5mqmrgZNXPLBNxvZsQNWUPVBNUJ/b3BouD/2DHqG/PyhmZ+ 5NlvjDHIuo5/HxiNNa38eZ8546LarkTNIybhxHQwccV9rSs9HYCu1PclwSnU7FpgGa6L iFszazJ8b7djqPg87alc2Ds69n2crNBCCstz7USoLFXOYuN2XCWtbo1BMYWzf3ObKaZR Yz3A== X-Gm-Message-State: AOJu0YzKpHDkxpS0lvq7a6Q7gcnaeM8MK5CoGEEhOgxVGi4T4EP/iroL vaL5r3AVwUEyNhvcVUzIbPmcvVT6t8Xz3AcXWLjhXoUph5xw/h1Q6bvKREgxplVomglrUfQtFIk Syl7J X-Gm-Gg: AR+sD10xKvvyfwz3aB7qyIQ/9ckr8cEW5HqTNF7jK9zlnIzMAHvZxUxAHkqwqV+gmxd ovcCl0fFYD4x6QxBlZ69ds7fP8j0mUwWwlX6+weSrR9kURBwpFzEgYmJ1fnMv4lsjh89LR8QQzi T6GzYYClovzt8hsoqpBWWE92CpD8oKprIWmDzTJhr5548G0p9IMtyfFcfC6UJRp/JYjB3YAWo8T JBUdPNQyGa342QMPrDHbujzNRAi7kUQviyk+7DUImpkaoA+1a9GJ/3owM7KZgIhy1goDLfu76rv ZDU8V++NddcGTDxqI1FWaTFJHISEAKzEwaxgWjPjrzqoMxBDf1uplKwVuAdhvOxDj9MOAi71EOj 0LRzDHApo9WBsnJIBPR2AL/7ayZca/teuEKkRYqfBpEWRoBXxxrfeO2hvYNUb3pjoIhTPP1Vhrs y5KuT4QpGcjf8aqEG42jIvNdaLNZxSPoP9R261czMqBE9GPmxq8g+m9jWQFg2Oq01eoZ3PJlRf5 +0UfMD6e1EJEYiRwIRpr/WdUCgM/+tcTi1gn3woPcDmS+hObKeqrOsP3q1MjaDTGK4IrA== X-Received: by 2002:a05:600c:628d:b0:499:795a:c5fc with SMTP id 5b1f17b1804b1-499b832643emr81034235e9.7.1787310146655; Fri, 21 Aug 2026 04:02:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/43] hw/arm: bananapi_m2u: Store boot info in the machine state Date: Fri, 21 Aug 2026 12:00:44 +0100 Message-ID: <20260821110101.3971391-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310317432158500 Content-Type: text/plain; charset="utf-8" From: Bin Meng arm_load_kernel() keeps a pointer to the boot info struct for the lifetime of the VM, so the struct logically belongs to the machine rather than to a file scoped static object. Move it into a new Bpim2uMachineState and register the machine type explicitly instead of through the DEFINE_MACHINE_ARM macro. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Message-id: 20260816131300.51799-4-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/bananapi_m2u.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index 9b468cd8ac8..0079aa1dd2b 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -29,7 +29,14 @@ #include "hw/arm/boot.h" #include "hw/arm/machines-qom.h" =20 -static struct arm_boot_info bpim2u_binfo; +#define TYPE_BPIM2U_MACHINE MACHINE_TYPE_NAME("bpim2u") +OBJECT_DECLARE_SIMPLE_TYPE(Bpim2uMachineState, BPIM2U_MACHINE) + +struct Bpim2uMachineState { + MachineState parent; + + struct arm_boot_info bootinfo; +}; =20 /* * R40 can boot from mmc0 and mmc2, and bpim2u has two mmc interface, one = is @@ -62,6 +69,7 @@ static void mmc_attach_drive(AwR40State *s, AwSdHostState= *mmc, int unit, =20 static void bpim2u_init(MachineState *machine) { + Bpim2uMachineState *bpms =3D BPIM2U_MACHINE(machine); bool bootroom_loaded =3D false; AwR40State *r40; I2CBus *i2c; @@ -120,10 +128,10 @@ static void bpim2u_init(MachineState *machine) memory_region_add_subregion(get_system_memory(), r40->memmap[AW_R40_DEV_SDRAM], machine->ra= m); =20 - bpim2u_binfo.loader_start =3D r40->memmap[AW_R40_DEV_SDRAM]; - bpim2u_binfo.ram_size =3D machine->ram_size; - bpim2u_binfo.psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; - arm_load_kernel(&r40->cpus[0], machine, &bpim2u_binfo); + bpms->bootinfo.loader_start =3D r40->memmap[AW_R40_DEV_SDRAM]; + bpms->bootinfo.ram_size =3D machine->ram_size; + bpms->bootinfo.psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; + arm_load_kernel(&r40->cpus[0], machine, &bpms->bootinfo); } =20 static void bpim2u_machine_init(MachineClass *mc) @@ -145,4 +153,5 @@ static void bpim2u_machine_init(MachineClass *mc) mc->auto_create_sdcard =3D true; } =20 -DEFINE_MACHINE_ARM("bpim2u", bpim2u_machine_init) +DEFINE_MACHINE_EXTENDED("bpim2u", MACHINE, Bpim2uMachineState, + bpim2u_machine_init, false, arm_machine_interfaces) --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310392; cv=none; d=zohomail.com; s=zohoarc; b=bqH3r/LJdX4czFfSO3IOEH2ZwgmUhRsxyRnX5Y2I9B1Um/Ea/0tNWACD7YM9uhcLDYPNQxqj2Mu3CsC6cXygCH7IzcVBOii8zposU4xEVaaz3aK1bTFW55mHen9EpIMTMDWKls2EYnA2HZjplM51ZC5TBTMykJ0yw2GyHQOUl7g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310392; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=SIQ95ChhMBEDMeksGTqzOnHzqdHd6VFFDSZ1sW5capc=; b=goXEEtccNLGsFtiGuvBF73KpvX7iEiG0iZTPZvDWulm6S4lZ/dyuqWBdaOAUD4fOOwx6Rf35lWFNxqUkwn50oLpKs3o5ZA+b/uPnKRhn0V3u0IyWuSJ2EXnBbvexupfiCcgiCI/Qhg4od7eyjYH3kVvvjJzb/K+Mo8SCTOE83D0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310392245192.144867936561; Fri, 21 Aug 2026 04:06:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1K-0001Hd-Ju; Fri, 21 Aug 2026 07:02:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN16-0000mU-5Y for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:32 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN13-0007Vn-Gl for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:31 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-49954b88fffso7253375e9.0 for ; Fri, 21 Aug 2026 04:02:29 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310148; x=1787914948; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=SIQ95ChhMBEDMeksGTqzOnHzqdHd6VFFDSZ1sW5capc=; b=SYouMwDTcaukeY8eP4XUidDZJ/b40uS0bYVf2Z/Wxhc+/aJRu3Wlcc4TtRDqhGSmzI KXGsJBmNboDsuFLOotn5fblmAUxQ0WwzqUAai7Uzj7Ib/VecyVapJ6ryCcd0vrXs51wU 4WegKJmmta8qPPjV+TmQNoHPi/eil3w+o03qbjhE3RSyi+cYr7CIigAsCyDOubsWWi7U 4ABq+yLIGb76f6yZnWAcGZ4feODdcrAilg2qhflv9twgHf2YJRkY123jCAKS3gDxO0A4 ShR+I4N650nJ0sYGHNMEzeHageqAf0tUE9/ruAHgG4W2zDCIw5zWpgensZ1dG7Clq2GZ tz6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310148; x=1787914948; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=SIQ95ChhMBEDMeksGTqzOnHzqdHd6VFFDSZ1sW5capc=; b=NWzEqINuFPCs9FpLm1VSTr3wSuaBdJH0/O2V5WQSmjodZ+vi8udL+HdgYPXB3VKw6F +w5MlDJCMMHoOjTgkwxI4LFImNARHhK5FKIXoscnIM22NTEmzOxuF0hFOvn3esNeQJZa bBxVVUe0VC30dxA95cRTVzpJVlha6HTDtNkk999tz447iky1WANIRRiamYyXmzZKHF5O O255m2fSJlQgls/ZUk+CzUBPhce/xo64GToCQT27eMRThanR3UTzKSseVZwsjpVHkbQZ tVMnYJjg4VjgqFRuY7vS9JXOHnTkVVbf+FUJk/T1CnSQgdWLOUel+mletK/dGzUonwN7 khwQ== X-Gm-Message-State: AOJu0YxTJnwTdkWSY2tQeKsVrXs7LzdG78oDHoVUIkeRq6UZKu0UnG1P EbnJJxZuy83McvpVNhRmdDOsmnJ6q/8KWq6bdCX9es9SnRe6i07WFwHK6nn7Wvcpmd80tpBRnQE ElMA1 X-Gm-Gg: AR+sD10muUoDVC6+I64YL1EJml/JYd5gSV0dlYBrrMU2e4O1VCLzj6CutG0+jToYym8 N0e9bDCcflgZcyDSd0c1Kah1XiRPKPvnGC1ViPr3ZtUzCxwQbKc5CViDd4b6fvRGFMJ0nuls/Au ZBHnzEAlZnDoy/BlDRW+JWV/HOxVvJzRpXde2EYKYRFZcsM+BT6EmsVKLstuD1TlOncFpoDiPgG 7HAHv25Ob5cCk7VDOhf1mZxkdsc39wqJZCrTHLtxt46BzKudwST6PRq9Yk7RkwkUNqxZ8j8tct1 1BQTA+ZNKzeFhgtD23b9H6TQuKnjnxLklL0FjaUWTUxjZXWQgmCridiv63V9KMcQ8hIMMwZg4uV N++LQRbYyntNF7612QyssJS7U8ZPErzm9R8T4zZP3KLYOu4EJNlRrvhqZiPe3gQiMsC1C8JsWou Tg8mr9oKjJLMMO4ldIy0z9VRuYapnWtgHGr6UyKSpsA19CCgR2uKGjNBBK9BkChu5IhAmcf6skK bvg2eB/IlZVyys5MGmXM+UuyNztVxxotoqUXeqvjlyJ367S/LZIQD56/Icoy2hSHMuVvA4+AS9J wagl X-Received: by 2002:a05:600c:c4a6:b0:499:726a:a017 with SMTP id 5b1f17b1804b1-499b82f4090mr88635515e9.1.1787310147728; Fri, 21 Aug 2026 04:02:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/43] hw/arm: collie: Store boot info in the machine state Date: Fri, 21 Aug 2026 12:00:45 +0100 Message-ID: <20260821110101.3971391-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310393904158500 Content-Type: text/plain; charset="utf-8" From: Bin Meng arm_load_kernel() keeps a pointer to the boot info struct for the lifetime of the VM, so the struct logically belongs to the machine rather than to a file scoped static object. Move the boot info into the existing CollieMachineState. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Message-id: 20260816131300.51799-5-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/collie.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/hw/arm/collie.c b/hw/arm/collie.c index 91f0a94b6ff..01d74ad38cd 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -30,16 +30,12 @@ struct CollieMachineState { MachineState parent; =20 StrongARMState *sa1110; + struct arm_boot_info bootinfo; }; =20 #define TYPE_COLLIE_MACHINE MACHINE_TYPE_NAME("collie") OBJECT_DECLARE_SIMPLE_TYPE(CollieMachineState, COLLIE_MACHINE) =20 -static struct arm_boot_info collie_binfo =3D { - .loader_start =3D SA_SDCS0, - .ram_size =3D RAM_SIZE, -}; - static void collie_init(MachineState *machine) { MachineClass *mc =3D MACHINE_GET_CLASS(machine); @@ -66,8 +62,10 @@ static void collie_init(MachineState *machine) =20 sysbus_create_simple("scoop", 0x40800000, NULL); =20 - collie_binfo.board_id =3D 0x208; - arm_load_kernel(cms->sa1110->cpu, machine, &collie_binfo); + cms->bootinfo.loader_start =3D SA_SDCS0; + cms->bootinfo.ram_size =3D RAM_SIZE; + cms->bootinfo.board_id =3D 0x208; + arm_load_kernel(cms->sa1110->cpu, machine, &cms->bootinfo); } =20 static void collie_machine_class_init(ObjectClass *oc, const void *data) --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310175; cv=none; d=zohomail.com; s=zohoarc; b=cp1VUxtkCjMLPR2ovwykIrPCW/N8Jeea43C2hHJb57fagtk6v8xSAPTQcLqTzvRGt2X9MAvjkjVsDGHyehFDBH857NxU+LlU86B1UE5vxdxq4mMd3Z6qbqUf9tIsV6d58zihgvUI/0VevVvNFGVVxoirtu5vxhTBmj+ybW2g4cE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310175; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=KYe/6B8tsxZ+nsgvyYwWpVH0krYt9p5V+gl6qmul/ng=; b=amYB6GmOy88YYcDZwl/3uYg8bJCT6CPzFPXNIXbyF4YIjgxBomWkov0OyrhNdE7DlLYlaDYa0Rc5LsWcqygZV2A+rXlXfWrVgiecXvHsksF4XjjbJ57vhdV0e5S5JWEj40P9KCvJ54yEleLNeA7ey7R8SOXSgdkM0SjY14LfvPI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310175485796.1402194286635; Fri, 21 Aug 2026 04:02:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1J-00019K-IG; Fri, 21 Aug 2026 07:02:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN16-0000mW-93 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:34 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN14-0007WO-IT for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:31 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4996f1ee4a4so5865365e9.2 for ; Fri, 21 Aug 2026 04:02:30 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310149; x=1787914949; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=KYe/6B8tsxZ+nsgvyYwWpVH0krYt9p5V+gl6qmul/ng=; b=slvwWR1oNpp5VHssdy8SZq3eaOVO5QqpPzAdTib6DYWMz+bG15fDJPsP1iOZ41+JQj EFQF91yaq5WzuEZnZ/38N8oTnc5fp4A/T2GCw+VLUn+mwV5xUatoO20+qcYv+op2rXP0 h8Y/srAtpcIsh0B72w9VRLFNAA2teaxu+Mcwbr1fucFtVLXhEOes30EZHa0+bdoZOhgQ GMtnl1VcOWavnr/TSh4s3otdt6zrkUsk0VlL1Zuu64jREwfkDHtcz8Qh+Kr0jGWymjIF pQLWOQcBpN8cMc8u78CW50UO9ClkGJVCH624XlxZrqhm+Bkb8c28ZFCPDKZPi5owhUDC +nyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310149; x=1787914949; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=KYe/6B8tsxZ+nsgvyYwWpVH0krYt9p5V+gl6qmul/ng=; b=L3xh4eh0DFjMgfdTWkGhbrJSQnns2QPCQ7ufELR5ahaRp3emIv7xB45OosOKiEUmTL 8kI1PGRLG8YgbXZFGHqGqWk8snWIaTCMjEDtz8XpGT434S4W0Twv7C3acITaYF/vkPI8 SxM3fIT+81aVIBGtwgrTZsiPXXD2HK3moXUf9GQMoODXbyKf6zLkhmcKAJZlDwkB8OqT 1LZSa0m1ReB/CIglAOf5l5/kQ4gNCz67wJwa3c7za3WYaESi9RvPlkZbMdfaETOOiZYa E4BRNbY4NwLxraiPwq3Vv2tQ6OEzbrpcMYJ9m0LkBsbGik668LuXqNuFWoAVQUHTgckD Vt6Q== X-Gm-Message-State: AOJu0YwZ4tEWRar5TQjKgzZ94Scoi6EjxUvpk/LoMaRUe5SxVNnUmg+z jX0tisx293/9CWPQDGK/lqe+xn5somgvw07pfdOoSu2Hx7h4Nd24vzMBxLk7Qm6I9XTtjAtMs5V zqvxX X-Gm-Gg: AR+sD133iEHA1yGIWax0JxOBxN1FW625XPfbos0GKxmfZ70f7mNCMnPg85xFX/hmwCY 1pcrQtHC7VM/dkoqHfimR/fo/tcCra2nL5ryHlt7txO3HumUvOVKsfUmx+KTaGEKuo2B9xBxEJQ LxQ3EaN2HJ+Mfmz9VkJiP23K2hDqUJjryXDtH1HDh0AOijppS34DJIlfa6ivF4oeZea8N5hro0F yHBzCgfsF4IyROlX0SsaMXDljyjFPC4JKEEUq949S8FhBwgoES1zEgBDrSqvxKW5InUQWyzOZHh +QSgXstmp/Nuhg3vr38/3oRlNGxIQxVyB6olESQeph/gAXi2Y5q0rvV3H81zIBzdC+E+LNfKwHV Q26d91g9oJgFKGZVTX7qvNqwUIYLq1gJ7iGw7dPYpWzk0ic1xHVM7+V5JChHLHB5MOpFz9gt8XQ L5f+UiErwV22qS9F+jaf6nN8dVgN1IGgdftMRKKGFnmysY6iWpZj0aTeKxL75Y6eRj6cogPfeno L+VN0oIQ50ygf7++lMLt+2tozvWLoyrCdpYK89TtUnaacW+yWqu+DsDI99pIxkRsaWGTA== X-Received: by 2002:a05:600c:638d:b0:497:fecd:5b00 with SMTP id 5b1f17b1804b1-499b8457084mr91558445e9.9.1787310149096; Fri, 21 Aug 2026 04:02:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/43] hw/arm: cubieboard: Store boot info in the machine state Date: Fri, 21 Aug 2026 12:00:46 +0100 Message-ID: <20260821110101.3971391-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310176443158501 Content-Type: text/plain; charset="utf-8" From: Bin Meng arm_load_kernel() keeps a pointer to the boot info struct for the lifetime of the VM, so the struct logically belongs to the machine rather than to a file scoped static object. Move it into a new CubieboardMachineState and register the machine type explicitly instead of through the DEFINE_MACHINE_ARM macro. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Message-id: 20260816131300.51799-6-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/cubieboard.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index a643ae4e27d..d59c1ebba7f 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -25,13 +25,18 @@ #include "hw/arm/machines-qom.h" #include "hw/i2c/i2c.h" =20 -static struct arm_boot_info cubieboard_binfo =3D { - .loader_start =3D AW_A10_SDRAM_BASE, - .board_id =3D 0x1008, +#define TYPE_CUBIEBOARD_MACHINE MACHINE_TYPE_NAME("cubieboard") +OBJECT_DECLARE_SIMPLE_TYPE(CubieboardMachineState, CUBIEBOARD_MACHINE) + +struct CubieboardMachineState { + MachineState parent; + + struct arm_boot_info bootinfo; }; =20 static void cubieboard_init(MachineState *machine) { + CubieboardMachineState *cbs =3D CUBIEBOARD_MACHINE(machine); AwA10State *a10; Error *err =3D NULL; DriveInfo *di; @@ -103,8 +108,10 @@ static void cubieboard_init(MachineState *machine) } /* TODO create and connect IDE devices for ide_drive_get() */ =20 - cubieboard_binfo.ram_size =3D machine->ram_size; - arm_load_kernel(&a10->cpu, machine, &cubieboard_binfo); + cbs->bootinfo.loader_start =3D AW_A10_SDRAM_BASE; + cbs->bootinfo.board_id =3D 0x1008; + cbs->bootinfo.ram_size =3D machine->ram_size; + arm_load_kernel(&a10->cpu, machine, &cbs->bootinfo); } =20 static void cubieboard_machine_init(MachineClass *mc) @@ -126,4 +133,6 @@ static void cubieboard_machine_init(MachineClass *mc) mc->auto_create_sdcard =3D true; } =20 -DEFINE_MACHINE_ARM("cubieboard", cubieboard_machine_init) +DEFINE_MACHINE_EXTENDED("cubieboard", MACHINE, CubieboardMachineState, + cubieboard_machine_init, false, + arm_machine_interfaces) --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310198; cv=none; d=zohomail.com; s=zohoarc; b=hTr/D1S2J7+er+QARoH/6y8CipJq6QoyOQTJdhbyF/Evu3INPPilt7+rb64uU7M9oX7KJxa8EUTyFRxBEhmF5bRZ1ngruTSTJngAK9p2rVTZJ5kpNabW44DmHiDMMXdCU4X6y1Lwo4cDqLLVYFGWyeCf/8eo5nlsltTT+bWLJYk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310198; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=s/wyPsdg26Mcr2gBRpwr42/AQikAx4ixxJ47kYT8ulc=; b=OdD3Bm2ba2KPmqtnbRFl7fAPLAX0xgENStjDn7ca0egIcAvEYHigUoX8gzA/s0Fcs3NX5/ZhC/zNrDOBSveCNBERB/VGOUXYKTaHPiBSSXab49OHYNuMGMpo8shA8XmVzextgzX7vLhnU+UzN4u6D6vRTEgtpgEI907NtdSU2OU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310198632232.40805395529298; Fri, 21 Aug 2026 04:03:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1G-0000zL-Jp; Fri, 21 Aug 2026 07:02:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN18-0000mw-Ac for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:34 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN16-0007XA-EE for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:34 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4980dc26022so6245265e9.1 for ; Fri, 21 Aug 2026 04:02:32 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310151; x=1787914951; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=s/wyPsdg26Mcr2gBRpwr42/AQikAx4ixxJ47kYT8ulc=; b=TMoAWOUenJl6+F+sSkr0y2ykgHPYdaghqCGFtMzkQ51nSbKByaT6IErC7odEreBCPq qpu8aiDcgA/6MYaNaY1mSPd2+LaT4DnMKvpj2R7X53eC7Sy+2v84jeD96wyHIPVZlQMP TFuj+jeRrwY8EzNW8RNwM6vPQT91Wy8y/CLtbNHkOhJ5TSF023fiqgVNbAsJTQxHgjff D6siQhl5EzdJUPZwnipvKQwsn+ZEceA7TzdSVO/HxxBj5s5f8tJBO/AudhhwT2ZBwLCF 3CJ7Wz20QSU9CsJsARkOH9QSf9vzQuHsnMeGTmdumB0yWbuVl10488Fp7+N3FTCwakgH x9KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310151; x=1787914951; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=s/wyPsdg26Mcr2gBRpwr42/AQikAx4ixxJ47kYT8ulc=; b=qtHxnZVpaSNis2RtNTkloZ9k2tX246xeXEOrb11l9a6SszAWRYQ+o1yOOctRtOpo/u TUdqqD9FehRBsTs7I9J7YSkSxo4uZOuW40n9/QXVqAHJG5MI+zyU8iKf22Tpn2Ewmb1U 5goEXDNMO89mMJyQyGm9WQIeoUfJ5Mt4LeWkzaScqAdPeSzNjA9hAhKDLoyldpFvsyLj olSD9A+Phd/fVB/N+RmsU81i715FF87UFatdWA/7mrKlmrlY6xO2hRapzf+/clvxyfsP Zxm97miw0LAb3xzT+P4gMim0XWIr8c0EavDLcM206uJjiFHZUdViSM1P9c4WO7IJQ/+V gkWQ== X-Gm-Message-State: AOJu0YwmzLLmVJCt8mpENOSs/Bzw2ueS90nPaI/28AsS1PIE8K3V6Np5 GxoxJxpQMRLVLls+0evnQXVlW/alwByiCpVFCksCHLtzROfyp/0lLDp1ZGrs7hp7aOoWYWq2r5D Iin7x X-Gm-Gg: AR+sD11KTbzeBOBq3ERxdPtuG1xJJIv6Y1DMNSICgfIjQLcqaieLhAshajaEf+XJrOP Z2Ln+PMHggqmAwo2Ll4FN7TP86a3Gm7vmUzRrtAFNtbWe/pZPgEVQ3ZYMWML7lOVvg7GD7LWJqW 4nDTwl2L5iwxQCfdoS/l6E8RdRhAxjRARgORN/BYrpHRPDEO/QkkwUclyOoDxGl4nTnYHiDD8pn mJNIlXJCcHDeloVZH4lg/1/GiFCiKntrETVWRc5iMD8cbn8qC13V4Wgo9sop5kyTY7eGl9j0/bZ +ccbo/GvmSiVu/TwFcV0Wpsxrp4FeFmuxxymp7XQ7K6Kyynh6B0NPX1eOKjLBmajC0GWinV8kpQ 3zi4FLZx1JSJYQyzOtCE3gjTlpVXWv5z+Bp9+e1yE/7hDvoO26Bn50K/C7LEHVV7yupItbiCPSk AAk5u00jGIa3kymO2V8mOKAx3fSXTFZkMQ6ol3hyrxNxJ5VfrXodWbbDqv1/tOdjndxhxeU3Qzn WcYsyiYXZQCsRb/DyW0Jkk8SPXkUmHWudv6raB0iot+sqHXTeXscc3gn997y9LTl+9t5w== X-Received: by 2002:a05:600c:c16f:b0:493:a623:d090 with SMTP id 5b1f17b1804b1-499b82e894emr82868985e9.10.1787310150999; Fri, 21 Aug 2026 04:02:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/43] hw/arm: exynos4_boards: Store boot info in the board state Date: Fri, 21 Aug 2026 12:00:47 +0100 Message-ID: <20260821110101.3971391-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310200602158500 From: Bin Meng arm_load_kernel() keeps a pointer to the boot info struct for the lifetime of the VM, so the struct logically belongs to the machine rather than to a file scoped static object. The Exynos4BoardState struct is already allocated per machine instance, so move the boot info there. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260816131300.51799-7-bin.meng@processmission.com Signed-off-by: Peter Maydell --- hw/arm/exynos4_boards.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 1b8c9b618f8..b7decdb2c7f 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -49,6 +49,7 @@ typedef struct Exynos4BoardState { Exynos4210State soc; MemoryRegion dram0_mem; MemoryRegion dram1_mem; + struct arm_boot_info bootinfo; } Exynos4BoardState; =20 static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] =3D { @@ -66,12 +67,6 @@ static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_= OF_BOARDS] =3D { [EXYNOS4_BOARD_SMDKC210] =3D 1 * GiB, }; =20 -static struct arm_boot_info exynos4_board_binfo =3D { - .loader_start =3D EXYNOS4210_BASE_BOOT_ADDR, - .smp_loader_start =3D EXYNOS4210_SMP_BOOT_ADDR, - .write_secondary_boot =3D exynos4210_write_secondary, -}; - static void lan9215_init(uint32_t base, qemu_irq irq) { DeviceState *dev; @@ -113,14 +108,15 @@ static Exynos4BoardState * exynos4_boards_init_common(MachineState *machine, Exynos4BoardType board_type) { - Exynos4BoardState *s =3D g_new(Exynos4BoardState, 1); + Exynos4BoardState *s =3D g_new0(Exynos4BoardState, 1); =20 - exynos4_board_binfo.ram_size =3D exynos4_board_ram_size[board_type]; - exynos4_board_binfo.board_id =3D exynos4_board_id[board_type]; - exynos4_board_binfo.smp_bootreg_addr =3D - exynos4_board_smp_bootreg_addr[board_type]; - exynos4_board_binfo.gic_cpu_if_addr =3D - EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100; + s->bootinfo.loader_start =3D EXYNOS4210_BASE_BOOT_ADDR; + s->bootinfo.smp_loader_start =3D EXYNOS4210_SMP_BOOT_ADDR; + s->bootinfo.write_secondary_boot =3D exynos4210_write_secondary; + s->bootinfo.ram_size =3D exynos4_board_ram_size[board_type]; + s->bootinfo.board_id =3D exynos4_board_id[board_type]; + s->bootinfo.smp_bootreg_addr =3D exynos4_board_smp_bootreg_addr[board_= type]; + s->bootinfo.gic_cpu_if_addr =3D EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x1= 00; =20 exynos4_boards_init_ram(s, get_system_memory(), exynos4_board_ram_size[board_type]); @@ -137,7 +133,7 @@ static void nuri_init(MachineState *machine) Exynos4BoardState *s =3D exynos4_boards_init_common(machine, EXYNOS4_BOARD_NURI); =20 - arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo); + arm_load_kernel(s->soc.cpu[0], machine, &s->bootinfo); } =20 static void smdkc210_init(MachineState *machine) @@ -147,7 +143,7 @@ static void smdkc210_init(MachineState *machine) =20 lan9215_init(SMDK_LAN9118_BASE_ADDR, qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)])); - arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo); + arm_load_kernel(s->soc.cpu[0], machine, &s->bootinfo); } =20 static const char * const valid_cpu_types[] =3D { --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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The IMX25PDK struct is already allocated per machine instance, so move the boot info there. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Message-id: 20260816131300.51799-8-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/imx25_pdk.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index 7ebd6c8eb9c..f7a51481af0 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -61,10 +61,9 @@ typedef struct IMX25PDK { FslIMX25State soc; MemoryRegion ram_alias; + struct arm_boot_info bootinfo; } IMX25PDK; =20 -static struct arm_boot_info imx25_pdk_binfo; - static void imx25_pdk_init(MachineState *machine) { IMX25PDK *s =3D g_new0(IMX25PDK, 1); @@ -114,9 +113,9 @@ static void imx25_pdk_init(MachineState *machine) alias_offset +=3D ram[i].size; } =20 - imx25_pdk_binfo.ram_size =3D machine->ram_size; - imx25_pdk_binfo.loader_start =3D FSL_IMX25_SDRAM0_ADDR; - imx25_pdk_binfo.board_id =3D 1771; + s->bootinfo.ram_size =3D machine->ram_size; + s->bootinfo.loader_start =3D FSL_IMX25_SDRAM0_ADDR; + s->bootinfo.board_id =3D 1771; =20 for (i =3D 0; i < FSL_IMX25_NUM_ESDHCS; i++) { BusState *bus; @@ -138,7 +137,7 @@ static void imx25_pdk_init(MachineState *machine) * fail. */ if (!qtest_enabled()) { - arm_load_kernel(&s->soc.cpu, machine, &imx25_pdk_binfo); + arm_load_kernel(&s->soc.cpu, machine, &s->bootinfo); } } =20 --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310304; cv=none; d=zohomail.com; s=zohoarc; b=V68SF/K5W5ZE0tIDfVQrktuhHviwFUMLPP3+GXLeMkm2qA2GPL/p7kUGdfw499b2QDOVY7iXP81nrHLXAfMRuvPop5zq0zeLBoI7bBCsWvy0SId1gk7qcMrZ1il2CAfTalq3z5jAPafedY9duCxCh8MhMOJky5JEidfJDB8NT3k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310304; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=VtCtqDJnzt5NurG6KBHFtJkEwweKFqZTgZ904LHAtlY=; b=n5pGlMC6B3+9vR8aOMSwsY7u3QeaUxRHedD5wP1OlqKkJw48sLK+n1YIysH64174cUDOF+nbdvCIkIBKJ7uD/MIzJ3fP1Ydx63jpjdMGFAQfyZgss/rjYWfObc+13hdqQq3Ky1NDCQ69yjXCi+5Co2EsvZJbfFobYdOtAamP1XI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310304033783.2425585705871; Fri, 21 Aug 2026 04:05:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1M-0001RG-8f; Fri, 21 Aug 2026 07:02:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN1B-0000ue-6k for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:39 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN18-0007Xf-Gm for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:36 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-47fe377a217so492093f8f.1 for ; Fri, 21 Aug 2026 04:02:34 -0700 (PDT) Received: from lanath.. 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Move it into a new Imx8mmEvkMachineState and register the machine type explicitly instead of through the DEFINE_MACHINE_AARCH64 macro. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Message-id: 20260816131300.51799-9-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/imx8mm-evk.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c index 6b7774d3e25..019c609c542 100644 --- a/hw/arm/imx8mm-evk.c +++ b/hw/arm/imx8mm-evk.c @@ -20,6 +20,15 @@ #include "qapi/error.h" #include =20 +#define TYPE_IMX8MM_EVK_MACHINE MACHINE_TYPE_NAME("imx8mm-evk") +OBJECT_DECLARE_SIMPLE_TYPE(Imx8mmEvkMachineState, IMX8MM_EVK_MACHINE) + +struct Imx8mmEvkMachineState { + MachineState parent; + + struct arm_boot_info bootinfo; +}; + static void imx8mm_evk_modify_dtb(const struct arm_boot_info *info, void *= fdt) { int i, offset; @@ -60,7 +69,7 @@ static void imx8mm_evk_modify_dtb(const struct arm_boot_i= nfo *info, void *fdt) =20 static void imx8mm_evk_init(MachineState *machine) { - static struct arm_boot_info boot_info; + Imx8mmEvkMachineState *ims =3D IMX8MM_EVK_MACHINE(machine); FslImx8mmState *s; =20 if (machine->ram_size > FSL_IMX8MM_RAM_SIZE_MAX) { @@ -69,13 +78,11 @@ static void imx8mm_evk_init(MachineState *machine) exit(1); } =20 - boot_info =3D (struct arm_boot_info) { - .loader_start =3D FSL_IMX8MM_RAM_START, - .board_id =3D -1, - .ram_size =3D machine->ram_size, - .psci_conduit =3D QEMU_PSCI_CONDUIT_SMC, - .modify_dtb =3D imx8mm_evk_modify_dtb, - }; + ims->bootinfo.loader_start =3D FSL_IMX8MM_RAM_START; + ims->bootinfo.board_id =3D -1; + ims->bootinfo.ram_size =3D machine->ram_size; + ims->bootinfo.psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; + ims->bootinfo.modify_dtb =3D imx8mm_evk_modify_dtb; =20 s =3D FSL_IMX8MM(object_new_with_props(TYPE_FSL_IMX8MM, OBJECT(machine= ), "soc", &error_fatal, NULL)); @@ -103,7 +110,7 @@ static void imx8mm_evk_init(MachineState *machine) } =20 if (!qtest_enabled()) { - arm_load_kernel(&s->cpu[0], machine, &boot_info); + arm_load_kernel(&s->cpu[0], machine, &ims->bootinfo); } } =20 @@ -127,4 +134,6 @@ static void imx8mm_evk_machine_init(MachineClass *mc) mc->get_default_cpu_type =3D imx8mm_evk_get_default_cpu_type; } =20 -DEFINE_MACHINE_AARCH64("imx8mm-evk", imx8mm_evk_machine_init) +DEFINE_MACHINE_EXTENDED("imx8mm-evk", MACHINE, Imx8mmEvkMachineState, + imx8mm_evk_machine_init, false, + aarch64_machine_interfaces) --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310241; cv=none; d=zohomail.com; s=zohoarc; b=PQ6nTy4mezrDDeF89SiiQvXOrmo1t3bskDKXcvqcKzDNPSnMXE3IpyhRuAdQAC7gDWTWrPQLimUl6/zCYpPTJJZSQIsz45tJ27X2aywFojqO4vtnj1WbNMt6rDgCh4g1lGIpyxXT0WHIxWAdzna39lTUS/9qgR2xYg6mlQpkLC8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310241; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=OORRY6R7krpOHz801JATma95E9xqPBNTjEyL2kX76xo=; b=MTey3xrZ77WIXGPrlwudvHu8IuHfodgx/i8mne/+jeobxnP1L6vl2DlFsPx6eLJwRgjT/fa+RaIOp4u/BivzFNiNC79ADBp1M8MEofoJVqHEVBrLYBLCrS6i7BeUiiyfv8GZxormutqsqbWJGNPi0tnReTtNwf535dPahQEXamU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310241634655.2093542972274; Fri, 21 Aug 2026 04:04:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1K-0001K7-Sd; Fri, 21 Aug 2026 07:02:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN1C-0000us-Ig for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:39 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN19-0007Xv-H8 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:38 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-495437bb891so4359935e9.1 for ; Fri, 21 Aug 2026 04:02:35 -0700 (PDT) Received: from lanath.. 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Move it into a new IntegratorcpMachineState and register the machine type explicitly instead of through the DEFINE_MACHINE_ARM macro. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Message-id: 20260816131300.51799-10-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/integratorcp.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index c25bbf3c82a..f8bcf42c615 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -581,13 +581,19 @@ static void icp_control_init(Object *obj) =20 /* Board init. */ =20 -static struct arm_boot_info integrator_binfo =3D { - .loader_start =3D 0x0, - .board_id =3D 0x113, +#define TYPE_INTEGRATORCP_MACHINE MACHINE_TYPE_NAME("integratorcp") +OBJECT_DECLARE_SIMPLE_TYPE(IntegratorcpMachineState, + INTEGRATORCP_MACHINE) + +struct IntegratorcpMachineState { + MachineState parent; + + struct arm_boot_info bootinfo; }; =20 static void integratorcp_init(MachineState *machine) { + IntegratorcpMachineState *icms =3D INTEGRATORCP_MACHINE(machine); ram_addr_t ram_size =3D machine->ram_size; Object *cpuobj; ARMCPU *cpu; @@ -680,8 +686,10 @@ static void integratorcp_init(MachineState *machine) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xc0000000); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[22]); =20 - integrator_binfo.ram_size =3D ram_size; - arm_load_kernel(cpu, machine, &integrator_binfo); + icms->bootinfo.loader_start =3D 0x0; + icms->bootinfo.board_id =3D 0x113; + icms->bootinfo.ram_size =3D ram_size; + arm_load_kernel(cpu, machine, &icms->bootinfo); } =20 static void integratorcp_machine_init(MachineClass *mc) @@ -696,7 +704,9 @@ static void integratorcp_machine_init(MachineClass *mc) machine_add_audiodev_property(mc); } =20 -DEFINE_MACHINE_ARM("integratorcp", integratorcp_machine_init) +DEFINE_MACHINE_EXTENDED("integratorcp", MACHINE, IntegratorcpMachineState, + integratorcp_machine_init, false, + arm_machine_interfaces) =20 static const Property core_properties[] =3D { DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310200; cv=none; d=zohomail.com; s=zohoarc; b=d48mCnZ7fRReHWx7lpsAjRxK5dPo7KjjwI/Xomw9yhoqDwPNesAokB+VL7mqIHBFqb+UrEv/1zBDiekx9WdOWOdrQg1LJgfmWx/2DVRpBzjp8oWiXhGsBF1KGJgW1ubaLtD/Bl3qkca5bebS6axvkD8IzTxcdFXfe7rtDf2Pn2I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310200; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=4rTL3SdYHRUqGgeIh0nHgD5mJ1eWi+Ul3pcLYk9c+W4=; b=nUjWPUxWwYb8dYIH2VL8PMKxF9bRhEQUlavmNFiQ4gYFETMQZXq+RBHLfziHYOmeBwi4cuDb5ijzXdshyNTdmV4ZvzxnjLbeYfbXcUe9v387gpXGn7w6jgQrfO1KPZ8i52wa/Q5LiPivLp3YoDnGPAnh/JM5lG58nb0A8yDTe58= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310200488505.6743011757162; Fri, 21 Aug 2026 04:03:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1L-0001NS-Bo; Fri, 21 Aug 2026 07:02:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN1D-0000vF-7Z for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:39 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN1B-0007YM-DX for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:38 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-496bb7cdf51so8319615e9.2 for ; Fri, 21 Aug 2026 04:02:37 -0700 (PDT) Received: from lanath.. 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The IMX31KZM struct is already allocated per machine instance, so move the boot info there. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Message-id: 20260816131300.51799-11-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/kzm.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index 168ecf35d09..1aa5b49de92 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -54,17 +54,13 @@ typedef struct IMX31KZM { FslIMX31State soc; MemoryRegion ram_alias; + struct arm_boot_info bootinfo; } IMX31KZM; =20 #define KZM_RAM_ADDR (FSL_IMX31_SDRAM0_ADDR) #define KZM_FPGA_ADDR (FSL_IMX31_CS4_ADDR + 0x1040) #define KZM_LAN9118_ADDR (FSL_IMX31_CS5_ADDR) =20 -static struct arm_boot_info kzm_binfo =3D { - .loader_start =3D KZM_RAM_ADDR, - .board_id =3D 1722, -}; - static void kzm_init(MachineState *machine) { IMX31KZM *s =3D g_new0(IMX31KZM, 1); @@ -125,10 +121,12 @@ static void kzm_init(MachineState *machine) 14745600, serial_hd(2), DEVICE_NATIVE_ENDIAN); } =20 - kzm_binfo.ram_size =3D machine->ram_size; + s->bootinfo.loader_start =3D KZM_RAM_ADDR; + s->bootinfo.board_id =3D 1722; + s->bootinfo.ram_size =3D machine->ram_size; =20 if (!qtest_enabled()) { - arm_load_kernel(&s->soc.cpu, machine, &kzm_binfo); + arm_load_kernel(&s->soc.cpu, machine, &s->bootinfo); } } =20 --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310197; cv=none; d=zohomail.com; s=zohoarc; b=e/P45yULqQBBy4N0DrhRQbkpiQfo0bohmIguo/SlOAiw41bkEqL77+HCqEI9yKbehsfFYY8yA7o0Fd6zhRsCyOG5qPTi8heALHcW4PLwOz1owrNOFsz3Vc9E5WQXN7UEWXuJ7d2Qxeio3wFM1gWkIKd1KW8NskJdAqAFlagx4so= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310197; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Qd+OWW3qU6A06engUu0NRn2PFP6Sh3jtFDKQxp24mZ4=; b=PvR+lmkxTuZ3J+N7sc9OAeb9HQSUhMK9lG+VMEng2oxEmMokooGUeyCccnvhvc2HC+E6cMb3Qsk/0VB3UMFGEubI6hBXrhh3Dy/vMq9SpRZQgLIS58l2lcRqTayo7VFWah9jyS3mkCakMyG0oGpJ4XKIl8L90BJYPEkNrvB0luw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310197678737.0455816472121; Fri, 21 Aug 2026 04:03:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1T-0001rT-Uf; Fri, 21 Aug 2026 07:02:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN1D-0000vG-81 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:39 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN1B-0007YL-Eb for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:38 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4954dff6536so6796105e9.0 for ; Fri, 21 Aug 2026 04:02:37 -0700 (PDT) Received: from lanath.. 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Move it into a new Mcimx7dSabreMachineState and register the machine type explicitly instead of through the DEFINE_MACHINE_ARM macro. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Message-id: 20260816131300.51799-12-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/mcimx7d-sabre.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index a0ac647c3df..22fe1fa932f 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -22,9 +22,19 @@ #include "qemu/error-report.h" #include "system/qtest.h" =20 +#define TYPE_MCIMX7D_SABRE_MACHINE MACHINE_TYPE_NAME("mcimx7d-sabre") +OBJECT_DECLARE_SIMPLE_TYPE(Mcimx7dSabreMachineState, + MCIMX7D_SABRE_MACHINE) + +struct Mcimx7dSabreMachineState { + MachineState parent; + + struct arm_boot_info bootinfo; +}; + static void mcimx7d_sabre_init(MachineState *machine) { - static struct arm_boot_info boot_info; + Mcimx7dSabreMachineState *msms =3D MCIMX7D_SABRE_MACHINE(machine); FslIMX7State *s; int i; =20 @@ -34,12 +44,10 @@ static void mcimx7d_sabre_init(MachineState *machine) exit(1); } =20 - boot_info =3D (struct arm_boot_info) { - .loader_start =3D FSL_IMX7_MMDC_ADDR, - .board_id =3D -1, - .ram_size =3D machine->ram_size, - .psci_conduit =3D QEMU_PSCI_CONDUIT_SMC, - }; + msms->bootinfo.loader_start =3D FSL_IMX7_MMDC_ADDR; + msms->bootinfo.board_id =3D -1; + msms->bootinfo.ram_size =3D machine->ram_size; + msms->bootinfo.psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; =20 s =3D FSL_IMX7(object_new(TYPE_FSL_IMX7)); object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); @@ -65,7 +73,7 @@ static void mcimx7d_sabre_init(MachineState *machine) } =20 if (!qtest_enabled()) { - arm_load_kernel(&s->cpu[0], machine, &boot_info); + arm_load_kernel(&s->cpu[0], machine, &msms->bootinfo); } } =20 @@ -78,4 +86,6 @@ static void mcimx7d_sabre_machine_init(MachineClass *mc) mc->auto_create_sdcard =3D true; } =20 -DEFINE_MACHINE_ARM("mcimx7d-sabre", mcimx7d_sabre_machine_init) +DEFINE_MACHINE_EXTENDED("mcimx7d-sabre", MACHINE, Mcimx7dSabreMachineState, + mcimx7d_sabre_machine_init, false, + arm_machine_interfaces) --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310324; cv=none; d=zohomail.com; s=zohoarc; b=ZjqDjO8CZsxWdib3OUAwfF7YBEK/GatfxYDTkz9ttDnJoyycNZ/vO+GRWB2z5O1Xj8Q3ppJLNI5rnp6FfgyMZTxz93eaOt+IaQkC344hi42hzwNZHqT+5uOMl68QF39N2/uLCIziOhmF9ub1ucBeMwRQ7YmjYEwLSzN418VibrM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310324; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=GawVdWQDHqb2VdR/tPStDoQ7Vl67lXfSjkdyFM0jSSE=; b=CNoDqa9EwLZ+nJr98NVIF63Rg6fG0uqhI4gT/XidF/mjHH9DIBlAIcCIlyiEL25ikhaniCwrKPo/n6IBX4KATOc7UCs4qIBcK4fBv+ef5wU491lh/d2KxPQPYYhwYpOGBv9TY/VHfzwUIQaRxlbEw0nbB8vkeSLYZ7/e9zd1PA8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310324492530.9173681859478; Fri, 21 Aug 2026 04:05:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1M-0001QM-2p; Fri, 21 Aug 2026 07:02:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN1E-0000xU-Ks for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:42 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN1C-0007Ya-By for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:40 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-499ac87c92bso7074055e9.1 for ; Fri, 21 Aug 2026 04:02:37 -0700 (PDT) Received: from lanath.. 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Move it into a new MusicPalMachineState and register the machine type explicitly instead of through the DEFINE_MACHINE_ARM macro. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Message-id: 20260816131300.51799-13-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/musicpal.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 69e83bdd973..8a70ed7377e 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1200,13 +1200,18 @@ static const TypeInfo musicpal_key_info =3D { =20 #define FLASH_SECTOR_SIZE (64 * KiB) =20 -static struct arm_boot_info musicpal_binfo =3D { - .loader_start =3D 0x0, - .board_id =3D 0x20e, +#define TYPE_MUSICPAL_MACHINE MACHINE_TYPE_NAME("musicpal") +OBJECT_DECLARE_SIMPLE_TYPE(MusicPalMachineState, MUSICPAL_MACHINE) + +struct MusicPalMachineState { + MachineState parent; + + struct arm_boot_info bootinfo; }; =20 static void musicpal_init(MachineState *machine) { + MusicPalMachineState *mpms =3D MUSICPAL_MACHINE(machine); ARMCPU *cpu; DeviceState *dev; DeviceState *pic; @@ -1341,8 +1346,10 @@ static void musicpal_init(MachineState *machine) sysbus_mmio_map(s, 0, MP_AUDIO_BASE); sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ)); =20 - musicpal_binfo.ram_size =3D MP_RAM_DEFAULT_SIZE; - arm_load_kernel(cpu, machine, &musicpal_binfo); + mpms->bootinfo.loader_start =3D 0x0; + mpms->bootinfo.board_id =3D 0x20e; + mpms->bootinfo.ram_size =3D MP_RAM_DEFAULT_SIZE; + arm_load_kernel(cpu, machine, &mpms->bootinfo); } =20 static void musicpal_machine_init(MachineClass *mc) @@ -1357,7 +1364,9 @@ static void musicpal_machine_init(MachineClass *mc) machine_add_audiodev_property(mc); } =20 -DEFINE_MACHINE_ARM("musicpal", musicpal_machine_init) +DEFINE_MACHINE_EXTENDED("musicpal", MACHINE, MusicPalMachineState, + musicpal_machine_init, false, + arm_machine_interfaces) =20 static void mv88w8618_wlan_class_init(ObjectClass *klass, const void *data) { --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310207; cv=none; d=zohomail.com; s=zohoarc; b=d/awiCr74vSCmYtbUp+6+QjXPAkJZkGjYQUzYIh4GtM4NQxZRuv4GewK/kIQmFRyOVTcVWv3mnO4zCdV0tfLwfVBNjGg/EYOv9VxtN/4pfQEo7cbQ+67HBTiFb3/y4nn7vhrMSL8KaRrfOFUZLySML8VZjbQZAqx4ZziEcRLnLg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310207; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=sk2+v2/9QdWzWPCYo+tcVu+g/i4C/qMtLjEeWY+x0ak=; b=EtFv8LkJCckvQtEpq2N2vIHcx6KzoaOQO645Z4nXGKAB92QbuXBMeU2bb3Xw3tRKEzj+k5YeEz1KYJ5HD2FL2BsQgLI3XljaHFQK+anxfw420TRH89AD8VTLPuMcBCTec+gRnHEfoyO+s9I3pDe6vTZJ1Cj7+c3B3F2n7ws/3FE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310207297704.7232434820573; Fri, 21 Aug 2026 04:03:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1U-0001yd-BV; Fri, 21 Aug 2026 07:02:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN1F-0000yE-CE for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:42 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN1D-0007Yj-C2 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:41 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-499acf0fb55so4588245e9.3 for ; Fri, 21 Aug 2026 04:02:38 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310158; x=1787914958; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=sk2+v2/9QdWzWPCYo+tcVu+g/i4C/qMtLjEeWY+x0ak=; b=PjDJOueHJYLsaZz/wzj5rIZ6qMb1rQsbHwnMRFr4E4OKsU9PDeUgMQMjeFOagea+Un w/7117yeoXVq02NBF5dgb0GOSuYpm1QgBgq4k+5bTu10R2sbglAG2URgr3XhmF+kmiNu 5MSWTBIMdg0RsKrosvOLAvMXEBsWQz5fXC7sFpDUZj+hfTScCSlh/JVdYo/1Vuijx9ho 22U3FkDPJR5ZiPQ3sJ7wXQYcKseQPgOvFK+7g8uValYQN43KpNMn3+TYcTPxCVhfg3iu v0EQN608jAjJ1MhcPmlMDN6QrRGX2BupHteFNuwjS1WEXFmHysTN79TcYC24oxB6p+7C TF0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310158; x=1787914958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=sk2+v2/9QdWzWPCYo+tcVu+g/i4C/qMtLjEeWY+x0ak=; b=ReLLY/qtv3hFlW99TE96MpPyEUDOxiw41A+4/YXS8LBgC351nkF+oxmYSWOOrbOvsW 80Ih7I0rvjV8pamTl3PxCHuT8jLdqGE0WQ2bax3Xbd/2+m0gROJCpxs+Hf9SmWpMSAC6 tBF/fF1UPA0HN0JVnI14fDf/0q52xysBeh49G2MxNdRNFrmFVhpyRLy4R86VSklkRR1J EXJ+AeNNcalf8nX0qNN9A21m6SgAu+OxRDxGjwXRVboZHgoxXFS7U43gAlX5FdfAuihk N7aLYi1beQhyU/R1xdnK28bx3cxm2p1MZluh9jMFfauSvgblWOifxY/UxcLIt0L4NwWa 6slA== X-Gm-Message-State: AOJu0YzGmsc1O0lB0yS7PwRaYwWRqvFkKc+xpfw5KcHbHcdiTET5VIns 2fPJjyeimizkSHPpt0WGkZS3TJDVf5vb36Y0heNAa5m2zXU2VT3XODwJALhvGWpAg6gIxPDjQNt JzTeI X-Gm-Gg: AR+sD12FKxvBuAhMYCGXnrXkQzX3HeTxQnwlLwpmUEGei1GWHqATRhkiXI0pmOTTqTN JV7VpPGe7tTirkwxEnbGQ7ygtfjKr9Lb562BcFAj4e3+QaUX0fdezPmTZGz37moLTPpZZaVN7Wc BN9+12/eaFA5M/oiIAAB5XetXedS6xBKvekjsnJqBzwev09FtLmHMYXTwNaXycur1peKuU1ZuJ8 j/G14PefU8YIZErD4KiBGsC7Q5i4Y5FN0YeyKGfhJMonEtyzty9MHWGlC4Ce2VFAHIx5ODjMewa fKEFNMUdIP+bbfaY9v1h+mb4M/BpkiGsVlw77/uE15A6Vu5WVM1CfSDEmdw60uYdhRDfNR2c+17 JHXpizpjJCnQph7+Ag0zKcmwK+JJzMRL0poENcfmkQ4cv9DWxrb8SaWV2spvxoNAl4ci/2zxRs3 ZGr5NrJdVyyYGflnYotOlQxCQq98AHFubLqB+RueeFcJGMRhkDDs3h7/TslctdkbCg9knQN26vW A+VF9mff9XYnp6m4nvoLHqTO761bxdZGIbNDZdwGcTL2d5876TbsXjYEUwzyjFpdQuo2Q== X-Received: by 2002:a05:600c:4e56:b0:499:728c:4704 with SMTP id 5b1f17b1804b1-499b8461b32mr82896775e9.12.1787310157941; Fri, 21 Aug 2026 04:02:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/43] hw/arm: npcm7xx: Store boot info in the machine state Date: Fri, 21 Aug 2026 12:00:54 +0100 Message-ID: <20260821110101.3971391-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310208665158500 Content-Type: text/plain; charset="utf-8" From: Bin Meng arm_load_kernel() keeps a pointer to the boot info struct for the lifetime of the VM, so the struct logically belongs to the machine rather than to a file scoped static object inside npcm7xx_load_kernel(). Let the caller own the boot info: the boards store it in their NPCM7xxMachine and pass it to npcm7xx_load_kernel(), which only fills in the SoC specific values. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Message-id: 20260816131300.51799-14-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/npcm7xx.c | 26 ++++++++++++-------------- hw/arm/npcm7xx_boards.c | 10 +++++----- include/hw/arm/npcm7xx.h | 10 ++++++++-- 3 files changed, 25 insertions(+), 21 deletions(-) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index c27f149c04a..695f30a0dc2 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -364,22 +364,20 @@ static void npcm7xx_write_secondary_boot(ARMCPU *cpu, NPCM7XX_SMP_LOADER_START); } =20 -static struct arm_boot_info npcm7xx_binfo =3D { - .loader_start =3D NPCM7XX_LOADER_START, - .smp_loader_start =3D NPCM7XX_SMP_LOADER_START, - .smp_bootreg_addr =3D NPCM7XX_SMP_BOOTREG_ADDR, - .gic_cpu_if_addr =3D NPCM7XX_GIC_CPU_IF_ADDR, - .write_secondary_boot =3D npcm7xx_write_secondary_boot, - .board_id =3D -1, - .board_setup_addr =3D NPCM7XX_BOARD_SETUP_ADDR, - .write_board_setup =3D npcm7xx_write_board_setup, -}; - -void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc) +void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc, + struct arm_boot_info *binfo) { - npcm7xx_binfo.ram_size =3D machine->ram_size; + binfo->loader_start =3D NPCM7XX_LOADER_START; + binfo->smp_loader_start =3D NPCM7XX_SMP_LOADER_START; + binfo->smp_bootreg_addr =3D NPCM7XX_SMP_BOOTREG_ADDR; + binfo->gic_cpu_if_addr =3D NPCM7XX_GIC_CPU_IF_ADDR; + binfo->write_secondary_boot =3D npcm7xx_write_secondary_boot; + binfo->board_id =3D -1; + binfo->board_setup_addr =3D NPCM7XX_BOARD_SETUP_ADDR; + binfo->write_board_setup =3D npcm7xx_write_board_setup; + binfo->ram_size =3D machine->ram_size; =20 - arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo); + arm_load_kernel(&soc->cpu[0], machine, binfo); } =20 static void npcm7xx_init_fuses(NPCM7xxState *s) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 57a8d3186e6..4f14d257465 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -374,7 +374,7 @@ static void npcm750_evb_init(MachineState *machine) npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0,= 0)); npcm750_evb_i2c_init(soc); npcm750_evb_fan_init(NPCM7XX_MACHINE(machine), soc); - npcm7xx_load_kernel(machine, soc); + npcm7xx_load_kernel(machine, soc, &NPCM7XX_MACHINE(machine)->bootinfo); } =20 static void quanta_gsj_init(MachineState *machine) @@ -390,7 +390,7 @@ static void quanta_gsj_init(MachineState *machine) drive_get(IF_MTD, 0, 0)); quanta_gsj_i2c_init(soc); quanta_gsj_fan_init(NPCM7XX_MACHINE(machine), soc); - npcm7xx_load_kernel(machine, soc); + npcm7xx_load_kernel(machine, soc, &NPCM7XX_MACHINE(machine)->bootinfo); } =20 static void quanta_gbs_init(MachineState *machine) @@ -408,7 +408,7 @@ static void quanta_gbs_init(MachineState *machine) =20 quanta_gbs_i2c_init(soc); sdhci_attach_drive(&soc->mmc.sdhci, 0); - npcm7xx_load_kernel(machine, soc); + npcm7xx_load_kernel(machine, soc, &NPCM7XX_MACHINE(machine)->bootinfo); } =20 static void kudo_bmc_init(MachineState *machine) @@ -427,7 +427,7 @@ static void kudo_bmc_init(MachineState *machine) =20 kudo_bmc_i2c_init(soc); sdhci_attach_drive(&soc->mmc.sdhci, 0); - npcm7xx_load_kernel(machine, soc); + npcm7xx_load_kernel(machine, soc, &NPCM7XX_MACHINE(machine)->bootinfo); } =20 static void mori_bmc_init(MachineState *machine) @@ -442,7 +442,7 @@ static void mori_bmc_init(MachineState *machine) npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f", drive_get(IF_MTD, 3, 0)); =20 - npcm7xx_load_kernel(machine, soc); + npcm7xx_load_kernel(machine, soc, &NPCM7XX_MACHINE(machine)->bootinfo); } =20 static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *typ= e) diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index eef7cc5332b..9f3dd489ecd 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -19,6 +19,7 @@ #include "hw/core/boards.h" #include "hw/adc/npcm7xx_adc.h" #include "hw/core/split-irq.h" +#include "hw/arm/boot.h" #include "hw/cpu/a9mpcore.h" #include "hw/gpio/npcm7xx_gpio.h" #include "hw/i2c/npcm7xx_smbus.h" @@ -62,6 +63,7 @@ struct NPCM7xxMachine { */ SplitIRQ fan_splitter[NPCM7XX_NR_PWM_MODULES * NPCM7XX_PWM_PER_MODULE]; + struct arm_boot_info bootinfo; }; =20 #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx") @@ -129,11 +131,15 @@ typedef struct NPCM7xxClass { * npcm7xx_load_kernel - Loads memory with everything needed to boot * @machine - The machine containing the SoC to be booted. * @soc - The SoC containing the CPU to be booted. + * @binfo - Caller owned boot info structure to be filled in. * * This will set up the ARM boot info structure for the specific NPCM7xx * derivative and call arm_load_kernel() to set up loading of the kernel, = etc. - * into memory, if requested by the user. + * into memory, if requested by the user. The boot info is owned by the + * caller because arm_load_kernel() keeps a pointer to it for the lifetime + * of the CPUs. */ -void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc); +void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc, + struct arm_boot_info *binfo); =20 #endif /* NPCM7XX_H */ --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310191; cv=none; d=zohomail.com; s=zohoarc; b=AhZUXrnvaOCFX5fh1oraYL0H9/slOm4Pl5DNVaUj4rAh98aXyoRWYrYJLuY5lqlmZAnsFgRqxEu7B8WcKaDJh3MYoODHslAsy1UMO1lEunBsERlPwmp0PM6BDwuSwVIq8AwCpeLYLNpI+mi8AznqEZLMxesyBb0kDEJe0ecA9Ak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310191; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Mra+QSr7xL4AJufg9b5eo4WZM7PgunenWDduQ/wz9f8=; b=koRxi3Zi3PW9gN6GyZgge5WCURMxTUHr1rnF15qlrCuRApK1QttIMbdCJSSoCV56+BO1rGyw6j+SF70f/ShyDdAOHZ3d6FG8qWoYh571gBrE0JTe+Bu72AzZP8HPHGALvSnCriFh6ei6L/dW6kC4exIfBi2x7BliZEDkHiUKV58= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310191814876.3241523132443; Fri, 21 Aug 2026 04:03:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1U-00020x-Nc; Fri, 21 Aug 2026 07:02:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN1G-0000zw-Gg for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:42 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN1E-0007Yz-KI for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:42 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-499b0eefa61so4871395e9.2 for ; Fri, 21 Aug 2026 04:02:40 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310159; x=1787914959; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=Mra+QSr7xL4AJufg9b5eo4WZM7PgunenWDduQ/wz9f8=; b=hrfF0tnp3KvJ0h4n5HOgMkqlwHN8xerg5gdvWopn2pwkBc1G2yfIFpPbi/8ZqD6MzD fjRiN4cVTjzLvPZASef0Yt4EGxBfNHqb0kEsfy7fI1xGucmFmoIXtzyBZs1TvIDC2PrH YGuY1Nez46r4jvMOWGFLWwUM9Crtcl2TPZe+tDq0akgzwyWld9VrqSuKs7Sb664Y9W5Y HnpCwZwXNky4Vzgav/ZREzHe2lY4JwXn/BA7f0/dOc8q72rFpaoCFl+V5CYnjq/mYen/ jmmvwwCaVMioZoAr3n5YrCglNvoyZI3KcY4+AYZD3mhoWm2h+uKGrLelKUr0O1s+5V8o 61lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310159; x=1787914959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=Mra+QSr7xL4AJufg9b5eo4WZM7PgunenWDduQ/wz9f8=; b=dXLxEMKO7fNxiUrMKdegakAgo0PbBvQYwJUFWEYh5P1thk2QZDOdfCehG88zDTIkI6 Fp5p2/h+NiLI6g+jok5KJiJtumCZ3NkmCDg7QTmL0yFMfCghx+WUGi1NNzWjJkMxLKJQ nKneBUpolsXx3xGMsEayvLjWsrrbx8kjWIuE4nUmC7sfxfqmylUh4k19P7egpxqFw7R9 pIuTXcAMmdpwQRtVxZTjVEobu1FLaEXIR12pZN2fcT4DV5xfZ0SBkfbSnm/xEK898vKt gPRX4/cuyzkAGB6wzWf8gGrN0sTKEEO7rdDDOmRU0T6hU2XERGre6ZCuvt1UrbHPh8ue d5yw== X-Gm-Message-State: AOJu0YyaTX0WCNTSZKlGkNw5f/C3FjyRP7iSkaWZChpWZWymKESaqJjL UcVtIWgoqjLFRHtWS+Zn5vWSviEME00f6nnLC9Lzw2/I6A8vKrfDCBBOeHlWFU9hC4Qhg5t25Fk OGJ8A X-Gm-Gg: AR+sD12VHrh2olb9Srhd4UvMEiq456eePOBgYhhPUpEjllZEEzxsp/x6fl0lavu5GOy CGbGJaLiSoHiQPlQFzmnNGVTDte4dNhxWKk4yr1kXpBXMvnnI0hUE628QojjDSbBHQhlwk0VCiK I0FpOqvsY6ukuO950RwBVjHngqZA26bOflX/NPVFcDqWaX9UMz4rH94K3T6ASzRPWD8z/PnNIiz LPvkt+NteLGN75WMHUEejYA761btwHT2b1XHN8b7EMcsduyl7bG8o8HdcSWMBVyFHbV0BN7cuJd XicrcqAfgq/rksgRbx/k56MAc2/hK8krjEKEPEyflcyl0DJjSMdh4eb6k70QJoUXfoC8m36u567 IJJntWYuDAIqFcrDtMJJ6J66J+yQwePi1kDT9NtQqoFZTjY6lrNl9fS8g5NeDPBacztSxPrPIC+ QDWzWorYktc+wcelW0xxmOAygPmIQAqElRRMowyJiZ9gf+mMnXwiaP3iNrkbctNMOap1U+Culiy MDgV38TE9DM1sP2GbNWqq81nU1wp6z3t24i9tCNdvQoVA9WjophsV9vBjmjcevdDSXAsw== X-Received: by 2002:a05:600c:1d1a:b0:499:7219:122f with SMTP id 5b1f17b1804b1-499b8303b86mr76863705e9.4.1787310158862; Fri, 21 Aug 2026 04:02:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/43] hw/arm: npcm8xx: Store boot info in the machine state Date: Fri, 21 Aug 2026 12:00:55 +0100 Message-ID: <20260821110101.3971391-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310192715158500 Content-Type: text/plain; charset="utf-8" From: Bin Meng arm_load_kernel() keeps a pointer to the boot info struct for the lifetime of the VM, so the struct logically belongs to the machine rather than to a file scoped static object inside npcm8xx_load_kernel(). Let the caller own the boot info: the board stores it in its NPCM8xxMachine and passes it to npcm8xx_load_kernel(), which only fills in the SoC specific values. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Message-id: 20260816131300.51799-15-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/npcm8xx.c | 26 ++++++++++++-------------- hw/arm/npcm8xx_boards.c | 2 +- include/hw/arm/npcm8xx.h | 10 ++++++++-- 3 files changed, 21 insertions(+), 17 deletions(-) diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c index 9ce6ea52d97..7d707a09b41 100644 --- a/hw/arm/npcm8xx.c +++ b/hw/arm/npcm8xx.c @@ -357,22 +357,20 @@ static const struct { }, }; =20 -static struct arm_boot_info npcm8xx_binfo =3D { - .loader_start =3D NPCM8XX_LOADER_START, - .smp_loader_start =3D NPCM8XX_SMP_LOADER_START, - .smp_bootreg_addr =3D NPCM8XX_SMP_BOOTREG_ADDR, - .gic_cpu_if_addr =3D NPCM8XX_GICC_BA, - .secure_boot =3D false, - .board_id =3D -1, - .board_setup_addr =3D NPCM8XX_BOARD_SETUP_ADDR, - .psci_conduit =3D QEMU_PSCI_CONDUIT_SMC, -}; - -void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc) +void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc, + struct arm_boot_info *binfo) { - npcm8xx_binfo.ram_size =3D machine->ram_size; + binfo->loader_start =3D NPCM8XX_LOADER_START; + binfo->smp_loader_start =3D NPCM8XX_SMP_LOADER_START; + binfo->smp_bootreg_addr =3D NPCM8XX_SMP_BOOTREG_ADDR; + binfo->gic_cpu_if_addr =3D NPCM8XX_GICC_BA; + binfo->secure_boot =3D false; + binfo->board_id =3D -1; + binfo->board_setup_addr =3D NPCM8XX_BOARD_SETUP_ADDR; + binfo->psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; + binfo->ram_size =3D machine->ram_size; =20 - arm_load_kernel(&soc->cpu[0], machine, &npcm8xx_binfo); + arm_load_kernel(&soc->cpu[0], machine, binfo); } =20 static void npcm8xx_init_fuses(NPCM8xxState *s) diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c index 042a928857c..f462369bea3 100644 --- a/hw/arm/npcm8xx_boards.c +++ b/hw/arm/npcm8xx_boards.c @@ -198,7 +198,7 @@ static void npcm845_evb_init(MachineState *machine) npcm8xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0,= 0)); npcm845_evb_i2c_init(soc); npcm845_evb_fan_init(NPCM8XX_MACHINE(machine), soc); - npcm8xx_load_kernel(machine, soc); + npcm8xx_load_kernel(machine, soc, &NPCM8XX_MACHINE(machine)->bootinfo); } =20 static void npcm8xx_set_soc_type(NPCM8xxMachineClass *nmc, const char *typ= e) diff --git a/include/hw/arm/npcm8xx.h b/include/hw/arm/npcm8xx.h index a8377db4905..676c82150db 100644 --- a/include/hw/arm/npcm8xx.h +++ b/include/hw/arm/npcm8xx.h @@ -23,6 +23,7 @@ #include "hw/i2c/npcm7xx_smbus.h" #include "hw/intc/arm_gic_common.h" #include "hw/mem/npcm7xx_mc.h" +#include "hw/arm/boot.h" #include "hw/misc/npcm_clk.h" #include "hw/misc/npcm_gcr.h" #include "hw/misc/npcm7xx_mft.h" @@ -62,6 +63,7 @@ struct NPCM8xxMachine { */ SplitIRQ fan_splitter[NPCM8XX_NR_PWM_MODULES * NPCM7XX_PWM_PER_MODULE]; + struct arm_boot_info bootinfo; }; =20 =20 @@ -122,11 +124,15 @@ OBJECT_DECLARE_TYPE(NPCM8xxState, NPCM8xxClass, NPCM8= XX) * npcm8xx_load_kernel - Loads memory with everything needed to boot * @machine - The machine containing the SoC to be booted. * @soc - The SoC containing the CPU to be booted. + * @binfo - Caller owned boot info structure to be filled in. * * This will set up the ARM boot info structure for the specific NPCM8xx * derivative and call arm_load_kernel() to set up loading of the kernel, = etc. - * into memory, if requested by the user. + * into memory, if requested by the user. The boot info is owned by the + * caller because arm_load_kernel() keeps a pointer to it for the lifetime + * of the CPUs. */ -void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc); +void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc, + struct arm_boot_info *binfo); =20 #endif /* NPCM8XX_H */ --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310222; cv=none; d=zohomail.com; s=zohoarc; b=C6hLkVpjWeuvoVDXlckdwEyAjinFStP8qHojyrkqmnU5lZ+1lQX2bZncYB2G/IvqoL6/OargwiqZBJJ0MGDiq8W9HCp3lMORnNJHqLlWEpZNO+vBXhGV02ESEqXaiwdtpa+bclyqPptX7t7P4XkocUhZ3KEHIQXaDNqVQ4iXM84= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310222; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=jDgg4EScB8bslHVWuzjdiznJQxcizlYwx+ib9GrZvI0=; b=eTv0u0W5IFdpc7fiM/Z9rSyLnAPZByR9N/zUYVl0nznW9wADgDYUUVZ6vIkZe+L5mpbvuq/PvVYrX0J9RUXDQ1BzddlcIrtPczW9eO2k97Lsn8mmK3vyCXGPYEtaIWlwerw1payKdBh0smUE9Z6bcREpd4LIeppXZvpWV4jDKpw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310222393415.6254077775367; Fri, 21 Aug 2026 04:03:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1M-0001Uv-PA; Fri, 21 Aug 2026 07:02:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN1H-00012S-0X for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:44 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN1F-0007Z8-8g for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:42 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4954f5e8020so3570575e9.2 for ; Fri, 21 Aug 2026 04:02:40 -0700 (PDT) Received: from lanath.. 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Give both the sx1 and sx1-v1 machine types the same Sx1MachineState instance struct and store the boot info there. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260816131300.51799-16-bin.meng@processmission.com Signed-off-by: Peter Maydell --- hw/arm/omap_sx1.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index bcb7105323f..3b628d13cbc 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -91,14 +91,16 @@ static const MemoryRegionOps static_ops =3D { #define FLASH1_SIZE (8 * MiB) #define FLASH2_SIZE (32 * MiB) =20 -static struct arm_boot_info sx1_binfo =3D { - .loader_start =3D OMAP_EMIFF_BASE, - .ram_size =3D SDRAM_SIZE, - .board_id =3D 0x265, -}; +typedef struct Sx1MachineState { + MachineState parent; + + struct arm_boot_info bootinfo; +} Sx1MachineState; =20 static void sx1_init(MachineState *machine, const int version) { + /* Both sx1 and sx1-v1 embed the same state as their first member */ + Sx1MachineState *sms =3D (Sx1MachineState *)machine; struct omap_mpu_state_s *mpu; MachineClass *mc =3D MACHINE_GET_CLASS(machine); MemoryRegion *address_space =3D get_system_memory(); @@ -187,7 +189,10 @@ static void sx1_init(MachineState *machine, const int = version) } =20 /* Load the kernel. */ - arm_load_kernel(mpu->cpu, machine, &sx1_binfo); + sms->bootinfo.loader_start =3D OMAP_EMIFF_BASE; + sms->bootinfo.ram_size =3D SDRAM_SIZE; + sms->bootinfo.board_id =3D 0x265; + arm_load_kernel(mpu->cpu, machine, &sms->bootinfo); =20 /* TODO: fix next line */ //~ qemu_console_resize(ds, 640, 480); @@ -220,6 +225,7 @@ static const TypeInfo sx1_machine_v2_type =3D { .name =3D MACHINE_TYPE_NAME("sx1"), .parent =3D TYPE_MACHINE, .class_init =3D sx1_machine_v2_class_init, + .instance_size =3D sizeof(Sx1MachineState), .interfaces =3D arm_machine_interfaces, }; =20 @@ -240,6 +246,7 @@ static const TypeInfo sx1_machine_v1_type =3D { .name =3D MACHINE_TYPE_NAME("sx1-v1"), .parent =3D TYPE_MACHINE, .class_init =3D sx1_machine_v1_class_init, + .instance_size =3D sizeof(Sx1MachineState), .interfaces =3D arm_machine_interfaces, }; =20 --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310343; cv=none; d=zohomail.com; s=zohoarc; b=hW5Df1TDoaFtrzRNOXkXCp4N6Z/3AcEqDLwv4MWP1qwVk2pbxfIPGYt3rDRADXvuqRuwLTJ1zcb/gcdXtOuyHo9iSUck2Ciec6d5i4d/jc/7G+VIOlAok+zy0XVYT5LluOIof+pbOAE9gPpSWi9o/IHtMFeBSUfmj3hkHlZPnHM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310343; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=AeyrW8w1ZGo0zpjO2gq6yEe2dJOSXGi87kFcV2lfD1I=; b=i2ElnHa/qjIOFZTb0tT3eIaeKLcQvtMtVjwYulUZWEwfJUhVD0R0cOsDKJtsmS8du/nP/qZFdDnu/y1VpsrfZWljRfH3USH0fBpNZKM2r5rDRhUIoGs6Uo6Em1A+cvvWeiqeMHx3mqmgvtRUa5bTbCC9zWyKHCBb7dO64Lep7qk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310343326287.8399068961078; Fri, 21 Aug 2026 04:05:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1V-000234-1P; Fri, 21 Aug 2026 07:02:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN1I-00012f-3L for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:44 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN1G-0007Zd-BH for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:43 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-49954b88fffso7255085e9.0 for ; Fri, 21 Aug 2026 04:02:41 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310161; x=1787914961; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=AeyrW8w1ZGo0zpjO2gq6yEe2dJOSXGi87kFcV2lfD1I=; b=N5R2SC91exkreL3r5zUddB39hIG6K05ENqYQfAbBwnpNtgvnOjmFWLBxr3F4RNSk3S U3QkA531gjPHdUEHlzo8MzW/OUddPBgn/vWB8t/Xw97P0jHeGwTa9N5u0xGMygap6H/4 bIdIsacZ2ysuovTbS2ZFUjpLYJS++/z7l62GTa4A2kgw54mfonNSK7Mw10tRSG5j6SVn oa09rsZISrHmUWIoWx+jLe773mFGT0I6yZGaY6WbvVv8lh9PmTpIyDBWRG7tbSE3kb4k l4wxhPnX9YGp78H4m2RwVgsMwGOC6tRAlmEOdGKugFJswUBmJwKWY/g+SpoMK6ZC69h/ spyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310161; x=1787914961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=AeyrW8w1ZGo0zpjO2gq6yEe2dJOSXGi87kFcV2lfD1I=; b=i/hvVD0kW5Uqt0un7MZBOEtOWH+sz3fnpyMDPp2ZJHl5VY/vXzFlHivE7PRjXIgk5Q +arVjfyjbZ3GqLoEsLUULlnHM463O2chrmxqDYL3G2HUcQCh9wxG3up6j0wdDl7m4Biw TGjtFK1ZCEfPaE7l2bHF2gF4Z6ghX25FgrK3qbTXG6D58Ut3bDIDzIyWcTiYcgfDPZi9 /v8I+a23kq/CCfb1eV3YvuOnlVX4kXDb0TpHaRVXajFb1jGdtXpIcpBn88KPdejtuWtN hGZxUK+OIqbMhiAnZF9/p3c0JRErOhkekgyo53frWuvYTgljFRkrlRRPKOF3htAxDth9 7NKw== X-Gm-Message-State: AOJu0Yx7c6aPzj7T/qy+cZ5WHCZu3luVVw/oW98YeXloJiCwebWygGhJ n/N7M0lKiAfHFwWp9udAUpWxjiWywX5xaTohA1KtMqOExqUPAQnZSxtf9o/npGjfP+LzzPOdEfd 7kQoD X-Gm-Gg: AR+sD13W6BKq/eq+fmZcyc/mukcfkDX7Lwc28c8H5eNi5kwmDvHtl4YCggHAtDcdMrF iWc6RiofC5y2ER7NFwAochK72cZNG0FQcg0PUtSGbGD/rU1wYd18qYDwe6A6zPFcbXFiBYukBgw FdYA5FHa/NuBdv1sfUV84Vq9EGMtathdwuwIb73LF2+mvTKVKLUPX2kk+kasmznqYH9qk9HGE3a dJ/dqSTvhFUnc6CIE+4+dBwl6yEpySFJp+5NHk7gYGIOwic+SB0+NuBdssBdog9dlmdV3PRpw+k TG0+tt4rKiwBZfQTzhr6+d5qRWe00yXOt3jWfSNLw20pZDxdl+8773R7vq0mTOo0GzRHpfelGf9 IYjEJcbmql3AFyT8aT3yqRivlyWvAlGnO5hFcTgTuHERJ6vwVGL/JDXh5Tl69XdXmFhMssoEvMQ uExH1ZmoBn0XdkRVHNavGjGzXsomjjSmwquv21UGTXtu5CyDm+7NvyTujSQ7UVaUhk4jo2YbBz5 c9nMSmissqcpG/rMpAzrikbelSgf9VDtdGMeU02iGyhh1l0XFcRCNduorwZRQrApKfISQ== X-Received: by 2002:a05:600c:354f:b0:499:a8bd:1930 with SMTP id 5b1f17b1804b1-499b830dd8amr73909405e9.5.1787310160989; Fri, 21 Aug 2026 04:02:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/43] hw/arm: orangepi: Store boot info in the machine state Date: Fri, 21 Aug 2026 12:00:57 +0100 Message-ID: <20260821110101.3971391-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310345605158500 Content-Type: text/plain; charset="utf-8" From: Bin Meng arm_load_kernel() keeps a pointer to the boot info struct for the lifetime of the VM, so the struct logically belongs to the machine rather than to a file scoped static object. Move it into a new OrangePiMachineState and register the machine type explicitly instead of through the DEFINE_MACHINE_ARM macro. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Reviewed-by: Niek Linnenbank Message-id: 20260816131300.51799-17-bin.meng@processmission.com Signed-off-by: Peter Maydell --- hw/arm/orangepi.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index d84443bb7b3..0e149ed6c98 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -28,10 +28,18 @@ #include "hw/arm/boot.h" #include "hw/arm/machines-qom.h" =20 -static struct arm_boot_info orangepi_binfo; +#define TYPE_ORANGEPI_MACHINE MACHINE_TYPE_NAME("orangepi-pc") +OBJECT_DECLARE_SIMPLE_TYPE(OrangePiMachineState, ORANGEPI_MACHINE) + +struct OrangePiMachineState { + MachineState parent; + + struct arm_boot_info bootinfo; +}; =20 static void orangepi_init(MachineState *machine) { + OrangePiMachineState *opms =3D ORANGEPI_MACHINE(machine); AwH3State *h3; DriveInfo *di; BlockBackend *blk; @@ -98,10 +106,10 @@ static void orangepi_init(MachineState *machine) /* Use Boot ROM to copy data from SD card to SRAM */ allwinner_h3_bootrom_setup(h3, blk); } - orangepi_binfo.loader_start =3D h3->memmap[AW_H3_DEV_SDRAM]; - orangepi_binfo.ram_size =3D machine->ram_size; - orangepi_binfo.psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; - arm_load_kernel(&h3->cpus[0], machine, &orangepi_binfo); + opms->bootinfo.loader_start =3D h3->memmap[AW_H3_DEV_SDRAM]; + opms->bootinfo.ram_size =3D machine->ram_size; + opms->bootinfo.psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; + arm_load_kernel(&h3->cpus[0], machine, &opms->bootinfo); } =20 static void orangepi_machine_init(MachineClass *mc) @@ -125,4 +133,6 @@ static void orangepi_machine_init(MachineClass *mc) mc->auto_create_sdcard =3D true; } =20 -DEFINE_MACHINE_ARM("orangepi-pc", orangepi_machine_init) +DEFINE_MACHINE_EXTENDED("orangepi-pc", MACHINE, OrangePiMachineState, + orangepi_machine_init, false, + arm_machine_interfaces) --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310221; cv=none; d=zohomail.com; s=zohoarc; b=K8C5pv4ppYClmDlQFmLLuI7RQ0i6M4A7RuPpxlZsEia7Nae9zFMtthUn4wZsOA49FjfgyxocacITBlel3otNxFymjCyS3WAObk9zB9/qbAepJRGUyH+2i+i/gInBDfJloMaQroUxw5SSS1G0I38kNlEVM05OpGz+k9XCz08HMxU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310221; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=gDfut0uAhYBlev9mWhTT7UDrgSY0wWCSRE5ndjMg/dU=; b=DxLBZ3zdTsp7XdbJUvJ0Vjqr9gU03Ij/Kkb8nK5gp5Ea0lq/4H0OAaMmYfBgJi1h6YPV1sD/1/F5bHEHsqVUIypqtO5GHuz4H+dGs9VkcajZ2G6VR/umhaQNjRmnMavk61QwslDOS5gv4vym2/ds6vhn9jZXdJxm2fQBsB97Yvs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310221422522.9025757800684; Fri, 21 Aug 2026 04:03:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1M-0001VP-V3; Fri, 21 Aug 2026 07:02:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN1J-00019X-G1 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:45 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN1H-0007Zx-IZ for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:45 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4996f1ee4a4so5866745e9.2 for ; Fri, 21 Aug 2026 04:02:43 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b90e7e20sm22875985e9.5.2026.08.21.04.02.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 04:02:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1787310162; x=1787914962; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=gDfut0uAhYBlev9mWhTT7UDrgSY0wWCSRE5ndjMg/dU=; b=W74ggF06lGfyaZ66P0cYlDtBgW1oqjGxuiVOvpHAt3nIXShhTI6Qvaa6Fmm+/hCBAL kRyObW2ZxhNtHi13oQvoRA2uz+kUGMTEOZOTAFHxaEgZ3iIDL7PgwZTt905ZzzCykSYF JdP7wVf+nqRluBC27MljYPsX7lSQ2XHO3wSW57DlsEPGqQCCR1aYtq3e2YbIhAm27d3F gpcfRf36zO1osfXBfehPNrcz0w8pgEfQmu8fUuuHpeyVOIwYSg0kZWGlRtUcyjeavC44 FhZqhm6T45gcfZT9kOvU0xNEgpgTlfY+oy/fWKfQaY50qCVq64wOJpYWV6ylj6mEQdsN hV2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787310162; x=1787914962; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=gDfut0uAhYBlev9mWhTT7UDrgSY0wWCSRE5ndjMg/dU=; b=SFQilVD12UwrMZW8qIKHCHakjcWu3HTlmjafNLwyzNM9vkkdUKt0J+CfJeB4NLpP6e RJpaMEEuPUVW2AY4NLtbSEIzP7hGAkJ3ZzmbJVlUGhjLOMk+bBLSEBI+jVytw0y8hK00 H3cyH31dPV8z83IV3Mz9FPyw1G2VsKZmgjiEtpOondyFBMIWIJbkTpwXtyKBRBstzxaL KBHhm2kJ8mPLYQOVaFH7zJoNzwPj2dxlfNgEqRY49kfhdWapgBt1sKObU7KISY+uqx1L ug1P4Xy7XGbERtmmE9ECZt+s7AW4ujeTyc+b4LXQfbLUXrCgPDmxQ0gMoN6WHgIhWV50 Rq3A== X-Gm-Message-State: AOJu0YwKkAz7jS0L4PWEj5Q6vjB4/tW8smR1oC0STwETzZPfseykeQ8x dqp9qYzFYHmLpeTAebVoKKRFWuu8omSUSoG4T9uTPGLSkTITuDPWFKqI2APJ+//Sz913HZmDOqg 3k6Fm X-Gm-Gg: AR+sD12vhByCzt2yHEJuhqyRsfCpfoZk7fJuuo7wysYKSouGKvK5YOdP/h4HgUwp1e0 D2VS81wfRB46PAIuNEyOoAIkSUpZHnkyZc7Z/xX+ofCY+P+4oMJxGzyoH8DlmsEjGSwKGBI78p0 J3DqfJazaQWq9HcL3mDmH2h9L8MFc6+/fi7TrQ8Pvo+sFwIn+CuBM0V8mFpJnZBqD9fSXvW7+qh kRnS/6WK+Us7IKvKoO0bOFwqWxQLZeaGpzigzaGozlzv4KpV8j0q4mpRpYijjieS6gx7VcUEeaE syfv3Cg7rl323p+XJmYWz6FWP91aQ0BchTxSfWt3lHI/OlCA2RD6bVkyy8FypS22raNVrhyRROh K+ppI2EWu9L5CyXWcbSJ5SgLSUM5vWjtQvQFT3s4B/bcRyikguiMIGT1MJOXvfE/jrSFjoLU5Io EBx6PcUP1fPGm0VWT9LVWUBnFZaKHUJFsM7ZC1qIl6oBaSC9zDgp7OdnUizaAdtPJZm+pGWKtFX 8mFqv0WvcWqBA1OpxWrT4u8Zgf7O21sfUX26wvJVC1rJsJnc6zUEqi9egfhfrz9IpiZFQ== X-Received: by 2002:a05:600c:1387:b0:499:7a4f:d13d with SMTP id 5b1f17b1804b1-499b8313ad3mr66282195e9.4.1787310161965; Fri, 21 Aug 2026 04:02:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/43] hw/arm: realview: Store boot info in the machine state Date: Fri, 21 Aug 2026 12:00:58 +0100 Message-ID: <20260821110101.3971391-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821110101.3971391-1-peter.maydell@linaro.org> References: <20260821110101.3971391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1787310222855158500 Content-Type: text/plain; charset="utf-8" From: Bin Meng arm_load_kernel() keeps a pointer to the boot info struct for the lifetime of the VM, so the struct logically belongs to the machine rather than to a file scoped static object. Give all four realview machine types the same RealViewMachineState instance struct and store the boot info there. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Message-id: 20260816131300.51799-18-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/realview.c | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 2b9f3271d62..0c2daf5c01f 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -39,10 +39,11 @@ =20 /* Board init. */ =20 -static struct arm_boot_info realview_binfo =3D { - .smp_loader_start =3D SMP_BOOT_ADDR, - .smp_bootreg_addr =3D SMP_BOOTREG_ADDR, -}; +typedef struct RealViewMachineState { + MachineState parent; + + struct arm_boot_info bootinfo; +} RealViewMachineState; =20 /* The following two lists must be consistent. */ enum realview_board_type { @@ -76,6 +77,8 @@ static void split_irq_from_named(DeviceState *src, const = char* outname, static void realview_init(MachineState *machine, enum realview_board_type board_type) { + /* All realview-* machines embed the same state as their first member = */ + RealViewMachineState *rvms =3D (RealViewMachineState *)machine; ARMCPU *cpu =3D NULL; CPUARMState *env; MemoryRegion *sysmem =3D get_system_memory(); @@ -202,7 +205,7 @@ static void realview_init(MachineState *machine, } sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ - realview_binfo.gic_cpu_if_addr =3D periphbase + 0x100; + rvms->bootinfo.gic_cpu_if_addr =3D periphbase + 0x100; } else { uint32_t gic_addr =3D is_pb ? 0x1e000000 : 0x10040000; /* For now just create the nIRQ GIC, and ignore the others. */ @@ -387,10 +390,12 @@ static void realview_init(MachineState *machine, &error_fatal); memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); =20 - realview_binfo.ram_size =3D ram_size; - realview_binfo.board_id =3D realview_board_id[board_type]; - realview_binfo.loader_start =3D (board_type =3D=3D BOARD_PB_A8 ? 0x700= 00000 : 0); - arm_load_kernel(cpu, machine, &realview_binfo); + rvms->bootinfo.smp_loader_start =3D SMP_BOOT_ADDR; + rvms->bootinfo.smp_bootreg_addr =3D SMP_BOOTREG_ADDR; + rvms->bootinfo.ram_size =3D ram_size; + rvms->bootinfo.board_id =3D realview_board_id[board_type]; + rvms->bootinfo.loader_start =3D board_type =3D=3D BOARD_PB_A8 ? 0x7000= 0000 : 0; + arm_load_kernel(cpu, machine, &rvms->bootinfo); } =20 static void realview_eb_init(MachineState *machine) @@ -431,6 +436,7 @@ static const TypeInfo realview_eb_type =3D { .name =3D MACHINE_TYPE_NAME("realview-eb"), .parent =3D TYPE_MACHINE, .class_init =3D realview_eb_class_init, + .instance_size =3D sizeof(RealViewMachineState), .interfaces =3D arm_machine_interfaces, }; =20 @@ -453,6 +459,7 @@ static const TypeInfo realview_eb_mpcore_type =3D { .name =3D MACHINE_TYPE_NAME("realview-eb-mpcore"), .parent =3D TYPE_MACHINE, .class_init =3D realview_eb_mpcore_class_init, + .instance_size =3D sizeof(RealViewMachineState), .interfaces =3D arm_machine_interfaces, }; =20 @@ -473,6 +480,7 @@ static const TypeInfo realview_pb_a8_type =3D { .name =3D MACHINE_TYPE_NAME("realview-pb-a8"), .parent =3D TYPE_MACHINE, .class_init =3D realview_pb_a8_class_init, + .instance_size =3D sizeof(RealViewMachineState), .interfaces =3D arm_machine_interfaces, }; =20 @@ -494,6 +502,7 @@ static const TypeInfo realview_pbx_a9_type =3D { .name =3D MACHINE_TYPE_NAME("realview-pbx-a9"), .parent =3D TYPE_MACHINE, .class_init =3D realview_pbx_a9_class_init, + .instance_size =3D sizeof(RealViewMachineState), .interfaces =3D arm_machine_interfaces, }; =20 --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310227; cv=none; d=zohomail.com; s=zohoarc; b=Jk4GTA0/dbNF7QCV40ooaMPpYBYdo/3VM3iOeOeYPNmXng+gqSoqtRa+uzhD/6CDWeaLmSg2pSBjOdQDt2JUVFHn0uMIZsLf2T/nE23OdjPz1TpnwBK5fQfHtpbDv7d2H8CgHodYZfAEvjTcmy8iBSEnRRt9KJlnUmGa3WDQGjI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310227; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=0NxFCkEldwQjcxLWI46OxLZ680eyIUHopOPMJytmotE=; b=WCOu9keQnvKooxSjnSp9oY9uXycarfiI6NM30Es083HRzW9Q/2xqVVkMfe+SUbbtOxqGILGHKm21FlMZhDe+rcKlcYduPptVHFU57vF90OC24rdmVuPA2igRCE6NDlkedMnDzbB3sWD4Wf2+tfXqUVjciqa/gPoxkC2TaKrJvto= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310227847115.37895902767775; Fri, 21 Aug 2026 04:03:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1M-0001UA-Nx; Fri, 21 Aug 2026 07:02:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN1K-0001FU-8H for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:46 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN1I-0007aA-G4 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:45 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4980fe6b3beso15561495e9.0 for ; Fri, 21 Aug 2026 04:02:43 -0700 (PDT) Received: from lanath.. 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Move the boot info into the existing SabreliteMachineState. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260816131300.51799-19-bin.meng@processmission.com Signed-off-by: Peter Maydell --- hw/arm/sabrelite.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 84bbc2f9798..140b2ecb9e2 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -25,18 +25,12 @@ struct SabreliteMachineState { =20 FslIMX6State soc; CanBusState *canbus[FSL_IMX6_NUM_CANS]; + struct arm_boot_info bootinfo; }; =20 #define TYPE_SABRELITE_MACHINE MACHINE_TYPE_NAME("sabrelite") OBJECT_DECLARE_SIMPLE_TYPE(SabreliteMachineState, SABRELITE_MACHINE) =20 -static struct arm_boot_info sabrelite_binfo =3D { - /* DDR memory start */ - .loader_start =3D FSL_IMX6_MMDC_ADDR, - /* No board ID, we boot from DT tree */ - .board_id =3D -1, -}; - /* No need to do any particular setup for secondary boot */ static void sabrelite_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) @@ -110,13 +104,17 @@ static void sabrelite_init(MachineState *machine) } } =20 - sabrelite_binfo.ram_size =3D machine->ram_size; - sabrelite_binfo.secure_boot =3D true; - sabrelite_binfo.write_secondary_boot =3D sabrelite_write_secondary; - sabrelite_binfo.secondary_cpu_reset_hook =3D sabrelite_reset_secondary; + /* DDR memory start */ + s->bootinfo.loader_start =3D FSL_IMX6_MMDC_ADDR; + /* No board ID, we boot from DT tree */ + s->bootinfo.board_id =3D -1; + s->bootinfo.ram_size =3D machine->ram_size; + s->bootinfo.secure_boot =3D true; + s->bootinfo.write_secondary_boot =3D sabrelite_write_secondary; + s->bootinfo.secondary_cpu_reset_hook =3D sabrelite_reset_secondary; =20 if (!qtest_enabled()) { - arm_load_kernel(&s->soc.cpu[0], machine, &sabrelite_binfo); + arm_load_kernel(&s->soc.cpu[0], machine, &s->bootinfo); } } =20 --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310204; cv=none; d=zohomail.com; s=zohoarc; b=Mgs6eksxRmnR4Se5fiPaRnfFSXB8HLBaNT0nXVGezrxrtW1sUDmJAaiJ1fV9XlbXslbwNq6RPh71gJrFfd3DSNeddS244jMo7PBMNkFd035bpym/mZQHace4YdEQY1FgS46MvLEPgxVK4dbt4Ni3CvoHS3NcHQwuAfwPTI9jWKc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310204; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=cBek9kLx+MkiFoIG2V0LBP5n+4hnmWgnu83ORFPB5T0=; b=bgaw3LLSopxy/50hEerDyfY3EurjvWL7miVd/XK6a2N0YPu+7wOFdau8Nkzw1QmqHC+DUesCXBJzXQWi1vsXEzQHF04+ipcy2uiX1DrtW0ajoTh71tdscvvs5doehbKdhS7FNQ09k9yH2ZANSyYPgKGHe9UMPgwBSPsaMEOItBI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310204963756.9964612989313; Fri, 21 Aug 2026 04:03:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1Q-0001kj-Fi; Fri, 21 Aug 2026 07:02:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN1L-0001Pg-Jp for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:47 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN1J-0007aV-Re for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:47 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-49800c6a846so7877545e9.3 for ; Fri, 21 Aug 2026 04:02:45 -0700 (PDT) Received: from lanath.. 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Give both machine types the same VersatileMachineState instance struct and store the boot info there. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Message-id: 20260816131300.51799-20-bin.meng@processmission.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/versatilepb.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index c6991a52e65..520af79c800 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -182,10 +182,16 @@ static void vpb_sic_init(Object *obj) peripherals and expansion busses. For now we emulate a subset of the PB peripherals and just change the board ID. */ =20 -static struct arm_boot_info versatile_binfo; +typedef struct VersatileMachineState { + MachineState parent; + + struct arm_boot_info bootinfo; +} VersatileMachineState; =20 static void versatile_init(MachineState *machine, int board_id) { + /* versatilepb and versatileab embed the same state as first member */ + VersatileMachineState *vms =3D (VersatileMachineState *)machine; Object *cpuobj; ARMCPU *cpu; MemoryRegion *sysmem =3D get_system_memory(); @@ -397,9 +403,9 @@ static void versatile_init(MachineState *machine, int b= oard_id) VERSATILE_FLASH_SECT_SIZE, 4, 0x0089, 0x0018, 0x0000, 0x0, 0); =20 - versatile_binfo.ram_size =3D machine->ram_size; - versatile_binfo.board_id =3D board_id; - arm_load_kernel(cpu, machine, &versatile_binfo); + vms->bootinfo.ram_size =3D machine->ram_size; + vms->bootinfo.board_id =3D board_id; + arm_load_kernel(cpu, machine, &vms->bootinfo); } =20 static void vpb_init(MachineState *machine) @@ -431,6 +437,7 @@ static const TypeInfo versatilepb_type =3D { .name =3D MACHINE_TYPE_NAME("versatilepb"), .parent =3D TYPE_MACHINE, .class_init =3D versatilepb_class_init, + .instance_size =3D sizeof(VersatileMachineState), .interfaces =3D arm_machine_interfaces, }; =20 @@ -453,6 +460,7 @@ static const TypeInfo versatileab_type =3D { .name =3D MACHINE_TYPE_NAME("versatileab"), .parent =3D TYPE_MACHINE, .class_init =3D versatileab_class_init, + .instance_size =3D sizeof(VersatileMachineState), .interfaces =3D arm_machine_interfaces, }; =20 --=20 2.43.0 From nobody Fri Aug 21 21:27:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1787310329; cv=none; d=zohomail.com; s=zohoarc; b=KxPL4WiqNEl7LkCY5U3Uj2Ra7m4X31Weu9YgM5j6A6NtE4nEODduTfid/PqA+rAWFzRSog+SbbhNnRDiwRcIhiqHbP3D8Ydtf5Y8J+/7bRUtjSgQTKWaNivlWODiwxclkmrDdN9wtN4X0qMu3t0uK7UsmyOKhGMqoED8MkuVx6s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787310329; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=OAAP3zU5qLV8bnrzcXkXKuYek438ivdUFWO5xk5urTk=; b=BKQIyy5SCyTAmywdoGEUsHfYOWFENwI4/3w+atSTavf5pV0aHA2LMh4r2vdPBh6a1duZ2W4eAjPM5E5yGrE3Jf6k5OjS9zMhA1we5ta1wmgv9XkM9uM3WYJlYvJbNnvquo0AbSTPVNSiSokHjmk8B6Uo+nc64N8CX3N6vIfyuLA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787310329592368.10344473439477; Fri, 21 Aug 2026 04:05:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxN1V-000272-L4; Fri, 21 Aug 2026 07:02:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxN1M-0001Vb-TB for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:48 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wxN1L-0007ak-2a for qemu-devel@nongnu.org; Fri, 21 Aug 2026 07:02:48 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-4798bea72f9so446914f8f.1 for ; Fri, 21 Aug 2026 04:02:46 -0700 (PDT) Received: from lanath.. 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Move the boot info into the existing ZynqMachineState. As in the xlnx-zcu102 and raspi machines, the boot info belongs to the machine rather than to a static object: 4d1ac883a7 ("hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102") 0f15c6e338 ("hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStat= e") Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20260816131300.51799-21-bin.meng@processmission.com Signed-off-by: Peter Maydell --- hw/arm/xilinx_zynq.c | 17 ++++++++--------- include/hw/arm/xilinx_zynq.h | 2 ++ 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 6c834390174..f3148975406 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -103,8 +103,6 @@ static void zynq_write_board_setup(ARMCPU *cpu, sizeof(board_setup_blob), BOARD_SETUP_ADDR); } =20 -static struct arm_boot_info zynq_binfo =3D {}; - static void gem_init(uint32_t base, qemu_irq irq) { DeviceState *dev; @@ -268,7 +266,7 @@ static void zynq_init(MachineState *machine) busdev =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); - zynq_binfo.gic_cpu_if_addr =3D MPCORE_PERIPHBASE + 0x100; + zynq_machine->bootinfo.gic_cpu_if_addr =3D MPCORE_PERIPHBASE + 0x100; sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL); for (n =3D 0; n < smp_cpus; n++) { /* See "hw/intc/arm_gic.h" for the IRQ line association */ @@ -444,13 +442,14 @@ static void zynq_init(MachineState *machine) create_unimplemented_device("zynq.qos301_dmac", 0xF8947000, 0x130); create_unimplemented_device("zynq.qos301_iou", 0xF8948000, 0x130); =20 - zynq_binfo.ram_size =3D machine->ram_size; - zynq_binfo.board_id =3D 0xd32; - zynq_binfo.loader_start =3D 0; - zynq_binfo.board_setup_addr =3D BOARD_SETUP_ADDR; - zynq_binfo.write_board_setup =3D zynq_write_board_setup; + zynq_machine->bootinfo.ram_size =3D machine->ram_size; + zynq_machine->bootinfo.board_id =3D 0xd32; + zynq_machine->bootinfo.loader_start =3D 0; + zynq_machine->bootinfo.board_setup_addr =3D BOARD_SETUP_ADDR; + zynq_machine->bootinfo.write_board_setup =3D zynq_write_board_setup; =20 - arm_load_kernel(zynq_machine->cpu[0], machine, &zynq_binfo); + arm_load_kernel(zynq_machine->cpu[0], machine, + &zynq_machine->bootinfo); } =20 static void zynq_machine_class_init(ObjectClass *oc, const void *data) diff --git a/include/hw/arm/xilinx_zynq.h b/include/hw/arm/xilinx_zynq.h index cefb7789ff8..669c516ad15 100644 --- a/include/hw/arm/xilinx_zynq.h +++ b/include/hw/arm/xilinx_zynq.h @@ -14,6 +14,7 @@ =20 #include "target/arm/cpu-qom.h" #include "hw/core/qdev-clock.h" +#include "hw/arm/boot.h" =20 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) @@ -25,6 +26,7 @@ struct ZynqMachineState { Clock *ps_clk; ARMCPU *cpu[ZYNQ_MAX_CPUS]; uint8_t boot_mode; + struct arm_boot_info bootinfo; }; =20 #endif /* QEMU_ARM_ZYNQ_H */ --=20 2.43.0