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Fri, 21 Aug 2026 03:50:01 -0700 (PDT) X-Received: by 2002:a05:622a:a11:b0:52d:918b:92e2 with SMTP id d75a77b69052e-52df56f1740mr49131911cf.6.1787309400169; Fri, 21 Aug 2026 03:50:00 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Helge Deller , Pierrick Bouvier Subject: [PATCH v3 01/15] linux-user: Uncast void pointer argument as Object in target_cpu_free() Date: Fri, 21 Aug 2026 12:49:35 +0200 Message-ID: <20260821104950.32108-2-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260821104950.32108-1-philmd@oss.qualcomm.com> References: <20260821104950.32108-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIxMDA4MSBTYWx0ZWRfXwnNagSfbRLpm QF0sOEsLcXzaahgwRsqg78LBuMhjBT6VcJ4L9ODoN/aIc/vH8jFPb0YktDPMDVCGMwsyySyzvm7 tYjFCS/IWWGsanjXfYVkjljxEwck4kZ5CRQw1wga3qbHNmd0G4nE7Ytd6koqHH67z7k+SjlITKs iGvg6VtXsRWidBvsEZOb6apaaGuI2bJj14yzj3ogdCyf4qgyIvXSz1uYle3Lwo29J349SI1wJuD ga8rdJN7eBzChnjO+k06xo5hHt7GIrBMGA08ZODRvgc8ioNi0c/fbfCoLZheSNiDhTtP6px3vqG SDjZbdmZynHSRdlcICOkKrLtCcYn8lNusv5WnTRvXzJVB/fvAI/qTZ6akukJFzzcAqClTxnVCDa F6Pdw/K4jYvFpsX9s798lUvQHPGD3iD4lolpOHD3oGvg9Rz9bR7HjtoF3PVzUK24p05lzv+gn+g vKMEzsDQM8iVVuRJ94g== X-Proofpoint-Spam-Info: AW1haW4tMjYwODIxMDA4MSBTYWx0ZWRfX5z/8cQkbz8a+ A5Jr46Z86KmifItGzHZc5atVSNgiK947Au4xFhvVZf3MovqUfLgiGB11JwGS4BigoxuW/Se4mJa pRfHBgdv8QecdRN781kasnKgLIxsBc0= X-Proofpoint-ORIG-GUID: HdWzm42_lOfD4TPNwT4yY5SoZ_NVj2t9 X-Authority-Analysis: v=2.4 cv=BJyDalQG c=1 sm=1 tr=0 ts=6a882d59 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=2RGiIWwp3e7TAFkeQGYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: HdWzm42_lOfD4TPNwT4yY5SoZ_NVj2t9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-21_03,2026-08-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 impostorscore=0 adultscore=0 phishscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608210081 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787309418554158500 init_main_thread() is registered as Object::free() hook, thus take an Object* argument. Uncast the void pointer as such. While now cpu_env() accept any pointer type, next commit will restrict it to CPUState* type. QOM-cast the Object to CPU type, otherwise we will get: ../linux-user/i386/cpu_loop.c: In function =E2=80=98target_cpu_free=E2=80= =99: include/hw/core/cpu.h:604:31: error: =E2=80=98_Generic=E2=80=99 selector = of type =E2=80=98void=E2=80=99 is not compatible with any association ../linux-user/x86_64/../i386/cpu_loop.c:331:19: note: in expansion of macro= =E2=80=98cpu_env=E2=80=99 331 | target_munmap(cpu_env(obj)->gdt.base, | ^~~~~~~ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- linux-user/i386/cpu_loop.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index fe922fceb5a..2f733b0b477 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -326,9 +326,10 @@ void cpu_loop(CPUX86State *env) } } =20 -static void target_cpu_free(void *obj) +static void target_cpu_free(void *ptr) { - target_munmap(cpu_env(obj)->gdt.base, + Object *obj =3D ptr; + target_munmap(X86_CPU(obj)->env.gdt.base, sizeof(uint64_t) * TARGET_GDT_ENTRIES); g_free(obj); } --=20 2.53.0 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787309565; cv=none; d=zohomail.com; s=zohoarc; b=ZcNG6o9SyC00OiWecRl69YSlXVmRROPXxwBJBQoRxPCKR+SLcKNuIM2fw43VYTBAozL/sTAktJ4jM5gNPqYf8EDnDX527xJZdYhQbrqLU0BQbJHnRHskGIAwyV34kT0Ro6KSWEI/gAD1uhWVBW7RAZ8PFAoZIZBLNrp21clI5n4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787309565; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Q+KDuQ2I/KnfM9bv8Lb05wGUziB13ZFXznw0mkhbS0g=; b=WtU3VQnUY/iS2eyd2ydgGxg5GZ9Hkuo4R8iZ673dZdR9WmG1Pb+c44062MMXRqivG9BMWy3WDHCGGdUMp7Y+NzqTJdyII3zyOTidIfSXRJYvi2K/VT/dP1k5AcAFZTXk4XoQMskjKiXOxVIpwufz9CuCLcj7+sGZFwS72HvNJqY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787309565188916.5384897870309; Fri, 21 Aug 2026 03:52:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxMpL-0004AF-Eg; Fri, 21 Aug 2026 06:50:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMpJ-00047S-2a for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:50:21 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMpH-00038P-Af for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:50:20 -0400 Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67L9M3PG2006429 for ; Fri, 21 Aug 2026 10:50:08 GMT Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g6gddh63k-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 21 Aug 2026 10:50:08 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-526da7e3c9dso8275431cf.1 for ; Fri, 21 Aug 2026 03:50:08 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787309567445158500 From: Philippe Mathieu-Daud=C3=A9 Use _Generic() controlling-expression to add the const-qualified variants of cpu_env(), env_cpu() and env_archcpu(). This allows to safely access CPU architecture state when it should not be modified. Alias env_cpu_const() which is still used. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- Following checkpatch.pl errors ignored: ERROR: spaces required around that ':' (ctx:VxE) #46: FILE: include/exec/cpu-common.h:89: + CPUArchState: \ ^ ERROR: spaces required around that ':' (ctx:VxE) #62: FILE: include/exec/cpu-common.h:101: + CPUArchState: \ ^ ERROR: spaces required around that ':' (ctx:VxE) #90: FILE: include/hw/core/cpu.h:605: + CPUState: \ ^ total: 3 errors, 0 warnings, 64 lines checked --- include/exec/cpu-common.h | 30 +++++++++++------------------- include/hw/core/cpu.h | 17 ++++++++++++----- 2 files changed, 23 insertions(+), 24 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 6594f7fa1be..bffef677607 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -85,21 +85,11 @@ static inline bool cpu_loop_exit_requested(const CPUSta= te *cpu) * * Return the ArchCPU associated with the environment. */ -static inline ArchCPU *env_archcpu(CPUArchState *env) -{ - return (void *)env - sizeof(CPUState); -} - -/** - * env_cpu_const(env) - * @env: The architecture environment - * - * Return the CPUState associated with the environment. - */ -static inline const CPUState *env_cpu_const(const CPUArchState *env) -{ - return (void *)env - sizeof(CPUState); -} +#define env_archcpu(env) _Generic(*(env), \ + CPUArchState: \ + (ArchCPU *)((void *)env - sizeof(CPUState)), \ + const CPUArchState: \ + (const ArchCPU *)((const void *)env - sizeof(CPUState))) =20 /** * env_cpu(env) @@ -107,9 +97,11 @@ static inline const CPUState *env_cpu_const(const CPUAr= chState *env) * * Return the CPUState associated with the environment. */ -static inline CPUState *env_cpu(CPUArchState *env) -{ - return (CPUState *)env_cpu_const(env); -} +#define env_cpu(env) _Generic(*(env), \ + CPUArchState: \ + (CPUState *)((void *)env - sizeof(CPUState)), \ + const CPUArchState: \ + (const CPUState *)((const void *)env - sizeof(CPUState))) +#define env_cpu_const(cpu) env_cpu(cpu) =20 #endif /* CPU_COMMON_H */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 81af7b9ee1a..0b5bb81b35d 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -594,11 +594,18 @@ struct CPUState { QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=3D sizeof(CPUState) - sizeof(CPUNegativeOffsetState)); =20 -static inline CPUArchState *cpu_env(CPUState *cpu) -{ - /* We validate that CPUArchState follows CPUState in cpu-target.c */ - return (CPUArchState *)(cpu + 1); -} +/** + * cpu_env(cpu) + * @cpu: The vCPU + * + * Return the CPUArchState associated with the CPU. + */ +#define cpu_env(cpu) _Generic(*(cpu), \ + /* We validate that CPUArchState follows CPUState in cpu-target.c = */ \ + CPUState: \ + (CPUArchState *)(cpu + 1), \ + const CPUState: \ + (const CPUArchState *)(cpu + 1)) =20 #ifdef CONFIG_TCG /* --=20 2.53.0 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787309682; cv=none; d=zohomail.com; s=zohoarc; b=QZJcgcc0ARn4NXQ01qdF7fOyhRl/ZzuLluDsTuVs9sgvkwYMJMPA3kjQY+GGASHbD0m5FM5UJ0Ncmi1X+OiyH0uSrRn0dZwi7JJpeS6baCIvJyGHPMQ7sTtv8kwXiLvDQ85WSNsoJ81MP4u7smJyhpBcMU4OG3rP56hLOFGXQss= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787309683794158500 Use the generic env_cpu() macro introduced in the previous commit and remove the few env_cpu_const() uses. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/exec/cpu-common.h | 1 - linux-user/elfload.c | 2 +- linux-user/i386/elfload.c | 2 +- linux-user/x86_64/elfload.c | 2 +- 4 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index bffef677607..d67d008236f 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -102,6 +102,5 @@ static inline bool cpu_loop_exit_requested(const CPUSta= te *cpu) (CPUState *)((void *)env - sizeof(CPUState)), \ const CPUArchState: \ (const CPUState *)((const void *)env - sizeof(CPUState))) -#define env_cpu_const(cpu) env_cpu(cpu) =20 #endif /* CPU_COMMON_H */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 88508deac50..c4bdaa146a7 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2128,7 +2128,7 @@ static int wmr_write_region(void *opaque, vaddr start, #endif static int elf_core_dump(int signr, const CPUArchState *env) { - const CPUState *cpu =3D env_cpu_const(env); + const CPUState *cpu =3D env_cpu(env); const TaskState *ts =3D (const TaskState *)get_task_state((CPUState *)= cpu); struct rlimit dumpsize; CountAndSizeRegions css; diff --git a/linux-user/i386/elfload.c b/linux-user/i386/elfload.c index 26b12001a3e..2e10f38a412 100644 --- a/linux-user/i386/elfload.c +++ b/linux-user/i386/elfload.c @@ -38,7 +38,7 @@ void elf_core_copy_regs(target_elf_gregset_t *r, const CP= UX86State *env) r->pt.es =3D tswapal(env->segs[R_ES].selector & 0xffff); r->pt.fs =3D tswapal(env->segs[R_FS].selector & 0xffff); r->pt.gs =3D tswapal(env->segs[R_GS].selector & 0xffff); - r->pt.orig_ax =3D tswapal(get_task_state(env_cpu_const(env))->orig_ax); + r->pt.orig_ax =3D tswapal(get_task_state(env_cpu(env))->orig_ax); r->pt.ip =3D tswapal(env->eip); r->pt.cs =3D tswapal(env->segs[R_CS].selector & 0xffff); r->pt.flags =3D tswapal(env->eflags); diff --git a/linux-user/x86_64/elfload.c b/linux-user/x86_64/elfload.c index 49a6f6180e0..121a8167acc 100644 --- a/linux-user/x86_64/elfload.c +++ b/linux-user/x86_64/elfload.c @@ -59,7 +59,7 @@ void elf_core_copy_regs(target_elf_gregset_t *r, const CP= UX86State *env) r->pt.dx =3D tswapal(env->regs[R_EDX]); r->pt.si =3D tswapal(env->regs[R_ESI]); r->pt.di =3D tswapal(env->regs[R_EDI]); - r->pt.orig_ax =3D tswapal(get_task_state(env_cpu_const(env))->orig_ax); + r->pt.orig_ax =3D tswapal(get_task_state(env_cpu(env))->orig_ax); r->pt.ip =3D tswapal(env->eip); r->pt.cs =3D tswapal(env->segs[R_CS].selector & 0xffff); r->pt.flags =3D tswapal(env->eflags); --=20 2.53.0 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787309485; cv=none; d=zohomail.com; s=zohoarc; b=VzM2jDosoBjcqae/+FXZ0o1WB3Yk2tkMGOs1886kNjOnRWam6gjAHQFRVxrcHfWlWdETAvWq3Gnb0DQt81WiYYb8k2zWSka/4hsfMfcSHgHMEHYWAN+PL57Qj6WLAxtkJpb9T30wAE9jsuSLHrz0RDQOaEKDYGaaCJ89Qibc7Cc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787309486716158500 Mark the CPUState structure const when it is only accessed read-only. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 4 ++-- include/system/cpus.h | 4 ++-- system/cpus.c | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 0b5bb81b35d..372485a2e54 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -900,7 +900,7 @@ void qemu_cpu_kick(CPUState *cpu); * Returns: %true if run state is not running or if artificially stopped; * %false otherwise. */ -bool cpu_is_stopped(CPUState *cpu); +bool cpu_is_stopped(const CPUState *cpu); =20 /** * do_run_on_cpu: @@ -1007,7 +1007,7 @@ void cpu_interrupt(CPUState *cpu, int mask); * * Checks if any of interrupts in @mask are pending on @cpu. */ -static inline bool cpu_test_interrupt(CPUState *cpu, int mask) +static inline bool cpu_test_interrupt(const CPUState *cpu, int mask) { return qatomic_load_acquire(&cpu->interrupt_request) & mask; } diff --git a/include/system/cpus.h b/include/system/cpus.h index 508444ccf1c..bf36b823769 100644 --- a/include/system/cpus.h +++ b/include/system/cpus.h @@ -13,10 +13,10 @@ const AccelOpsClass *cpus_get_accel(void); #define VCPU_THREAD_NAME_SIZE 16 =20 void cpus_kick_thread(CPUState *cpu); -bool cpu_work_list_empty(CPUState *cpu); +bool cpu_work_list_empty(const CPUState *cpu); bool cpu_thread_is_idle(CPUState *cpu); bool all_cpu_threads_idle(void); -bool cpu_can_run(CPUState *cpu); +bool cpu_can_run(const CPUState *cpu); void qemu_process_cpu_events_common(CPUState *cpu); void cpu_thread_signal_created(CPUState *cpu); void cpu_thread_signal_destroyed(CPUState *cpu); diff --git a/system/cpus.c b/system/cpus.c index f37e215c586..e11a5aab6a6 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -69,12 +69,12 @@ static QemuMutex bql; */ static const AccelOpsClass *cpus_accel; =20 -bool cpu_is_stopped(CPUState *cpu) +bool cpu_is_stopped(const CPUState *cpu) { return cpu->stopped || !runstate_is_running(); } =20 -bool cpu_work_list_empty(CPUState *cpu) +bool cpu_work_list_empty(const CPUState *cpu) { return QSIMPLEQ_EMPTY_ATOMIC(&cpu->work_list); } @@ -271,7 +271,7 @@ void cpu_interrupt(CPUState *cpu, int mask) cpus_accel->handle_interrupt(cpu, mask); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787309645180158500 Add the const qualifier to CPUAVRState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/avr/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index a818db753b2..1e4e839bd83 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -183,7 +183,7 @@ int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *= buf, int reg); int avr_print_insn(bfd_vma addr, disassemble_info *info); vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr); =20 -static inline int avr_feature(CPUAVRState *env, AVRFeature feature) +static inline int avr_feature(const CPUAVRState *env, AVRFeature feature) { return (env->features & (1U << feature)) !=3D 0; } @@ -204,12 +204,12 @@ enum { TB_FLAGS_SKIP =3D 2, }; =20 -static inline int cpu_interrupts_enabled(CPUAVRState *env) +static inline int cpu_interrupts_enabled(const CPUAVRState *env) { return env->sregI !=3D 0; } =20 -static inline uint8_t cpu_get_sreg(CPUAVRState *env) +static inline uint8_t cpu_get_sreg(const CPUAVRState *env) { return (env->sregC) << 0 | (env->sregZ) << 1 --=20 2.53.0 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787309545; cv=none; d=zohomail.com; s=zohoarc; b=fCw138vSai6fYLCPmIG8KEEW4Y+JLDT4bxctiNLNpflhMdxGpWUJk4KxD8gbmMk5JgVNdrBYMgjIsS/E1fzioiUrx/qwFwm2CuxSSzO5yIiw52TMJEOX5PdkEDKKhjb4Jx8nffFUaROJ9/0LGtfWzvTAQ+VE97aaBXI+nVEZYV8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787309545; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=uHmqw3PgQrwhWNplvoktCYvtMz6v2lpYN+dpIY29gRk=; b=PuHw5ucepzlaf1D/38EaZN8QkK9zeItYgbUGg5r7UoVGvK17J8PE/VPIaJU8xTMqyZVC15lxg1hKAak9ey58Ue21Mxbg1ZJGYGgi80sOQ/1few5M9axDZSXxt/K0eOutsenxb6qUYdUrD6rUe3yCJU31NGreTplZT3OaDOgrlS4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787309545501445.201060975151; Fri, 21 Aug 2026 03:52:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxMpn-0004ae-RL; Fri, 21 Aug 2026 06:50:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMpm-0004Ul-82 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:50:50 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMpk-0003RF-ML for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:50:49 -0400 Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67L9M0I9789894 for ; Fri, 21 Aug 2026 10:50:37 GMT Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g6ebusjhn-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 21 Aug 2026 10:50:37 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-52d33c89a29so10937011cf.1 for ; Fri, 21 Aug 2026 03:50:37 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Brian Cain --- target/hexagon/cpu.h | 2 +- target/hexagon/cpu.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index c50fbb3f72a..e4f120eda17 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -216,7 +216,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonS= tate *env, * @return true if the @a thread_env hardware thread is * not stopped. */ -bool hexagon_thread_is_enabled(CPUHexagonState *thread_env); +bool hexagon_thread_is_enabled(const CPUHexagonState *thread_env); uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg); void hexagon_cpu_soft_reset(CPUHexagonState *env); #endif diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 9765716b516..4cc6bd67c28 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -345,9 +345,9 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *c= s, } =20 #ifndef CONFIG_USER_ONLY -bool hexagon_thread_is_enabled(CPUHexagonState *env) +bool hexagon_thread_is_enabled(const CPUHexagonState *env) { - HexagonCPU *cpu =3D env_archcpu(env); + const HexagonCPU *cpu =3D env_archcpu(env); uint32_t modectl; uint32_t thread_enabled_mask; bool E_bit; --=20 2.53.0 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787309525; cv=none; d=zohomail.com; s=zohoarc; b=FI/i8O82u7qGSkV6r3cjp5YzDZWjy338bQyZuXGrqy6iMMXzjOcJsmf7kDQI9rPe0wDmC1eDDAZV3fWsTmK4GDEJGrGLDCy++jhDA1JKnOMQXYlX4TQ4J2N3Jt0gK8Hv26ocIhxl4ClzdaSrKz3Vk28A1rzWrPvcjgOMHTswJMk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787309525; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WWjKl8lE0l15HkiBp4oGylMn+2gkaoOjSN4ksHt/pc4=; b=nTm3Vsb6jASW/yPGMbpIqmHVmgMcYDJHHBki8RteF4iUfGEQoXDOHa/ObV91YpVXsMUQxbMQ7QaSMj9R8IMP/IOGyTvGQox3vjN7qudqnvfhQxaXSknGga21NMBpUJPB9v+MrppLrSziycx4egmxSuAnEcpxVsxy3hzmdgvXFpE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787309525935568.5245488174892; Fri, 21 Aug 2026 03:52:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxMpl-0004Tu-09; Fri, 21 Aug 2026 06:50:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMpk-0004TX-Cp for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:50:48 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMpi-0003T4-Ml for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:50:48 -0400 Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67L9LfKq3029206 for ; Fri, 21 Aug 2026 10:50:45 GMT Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g6fg9sae3-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 21 Aug 2026 10:50:45 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-51c21c01cf3so14415331cf.2 for ; Fri, 21 Aug 2026 03:50:44 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787309526654158500 x86_cpu_pending_interrupt() and x86_cpu_interrupts_enabled() only read CPU state without modification, add the const qualifiers to CPUState and CPUX86State parameters. Simplify directly using cpu_env() in x86_cpu_pending_interrupt. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/i386/cpu.h | 4 ++-- target/i386/cpu.c | 5 ++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 641f3ee5c2f..b0436dbf665 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2596,7 +2596,7 @@ void x86_cpu_gdb_init(CPUState *cs); int cpu_x86_support_mca_broadcast(CPUX86State *env); =20 #ifndef CONFIG_USER_ONLY -int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); +int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request); =20 bool x86_cpu_translate_for_debug(CPUState *cpu, vaddr addr, TranslateForDebugResult *result); @@ -3104,7 +3104,7 @@ static inline bool ctl_has_irq(CPUX86State *env) return (env->int_ctl & V_IRQ_MASK) && (int_prio >=3D tpr); } =20 -static inline bool x86_cpu_interrupts_enabled(CPUX86State *env) +static inline bool x86_cpu_interrupts_enabled(const CPUX86State *env) { return ((env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) || diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e5ffb10d156..1fc02cf94e6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10601,10 +10601,9 @@ static vaddr x86_cpu_get_pc(CPUState *cs) } =20 #if !defined(CONFIG_USER_ONLY) -int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) +int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + const CPUX86State *env =3D cpu_env(cs); =20 if (interrupt_request & CPU_INTERRUPT_POLL) { return CPU_INTERRUPT_POLL; --=20 2.53.0 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787309509; cv=none; d=zohomail.com; s=zohoarc; b=GOjPD/9ApZ6rIg9E6bcn5UGh++uMf4kccWhdnEOTxFmOHgdyJHzberwDni4w2S9Ywfr9yf5z5aVIgcxBdNGfBcJ/zyfWObNtSIoWog4tAjovsSrviUzMzAVEMTQlQ3X9Ht1gyUwM5+eYIPRDm29dVJ7/JPv+wprOWq3OJ5R2wlY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787309509; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VWq345a0G0XUYPJ8u6+lPJrThsdxHTF0ZV2AIgn58Tc=; b=Q8ylymy1rpqSs2yltiYE3KVd9O2rqGaeKhwtZc8YNd8N5mUb1LdIuBTQRX3MhOF6n0hJzc1nmh34S0Isd5ZKwunOw4i6Mt4x+lqXJwZhAISSoE8T80M3hXAJGv5Zv+uD+74oHrxM5RbTDAei/yytowpLMdEccYZQtUuYoN95Djw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787309509648125.27480338104726; Fri, 21 Aug 2026 03:51:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxMq5-00051t-0G; Fri, 21 Aug 2026 06:51:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMq2-0004vA-V9 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:51:07 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMq0-0003Uz-00 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:51:06 -0400 Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67L9M3iG789985 for ; Fri, 21 Aug 2026 10:50:53 GMT Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g6ebusjj6-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 21 Aug 2026 10:50:52 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-930edb4362dso84766485a.3 for ; Fri, 21 Aug 2026 03:50:52 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/loongarch/cpu.h | 6 +++--- target/loongarch/internals.h | 2 +- target/loongarch/cpu.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 97db3b453fe..ad8e7497279 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -486,7 +486,7 @@ struct LoongArchCPUClass { #define MMU_USER_IDX MMU_PLV_USER #define MMU_DA_IDX 4 =20 -static inline CPUSysState *env_sys(CPULoongArchState *env) +static inline CPUSysState *env_sys(const CPULoongArchState *env) { return env->sys_state; } @@ -496,12 +496,12 @@ static inline void set_sys_state(CPULoongArchState *e= nv, CPUSysState *sys) env->sys_state =3D sys; } =20 -static inline bool is_la64(CPULoongArchState *env) +static inline bool is_la64(const CPULoongArchState *env) { return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) =3D=3D CPUCFG1_ARCH_L= A64; } =20 -static inline bool is_va32(CPULoongArchState *env) +static inline bool is_va32(const CPULoongArchState *env) { /* VA32 if !LA64 or VA32L[1-3] */ bool va32 =3D !is_la64(env); diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index 50f0fe2e9be..d6f31161e85 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -38,7 +38,7 @@ uint64_t cpu_loongarch_get_constant_timer_counter(LoongAr= chCPU *cpu); uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu); void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu, uint64_t value); -bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env); +bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env); #endif /* !CONFIG_USER_ONLY */ =20 uint64_t read_fcc(CPULoongArchState *env); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index d9c1e871027..2dbe2203b20 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -82,7 +82,7 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int lev= el) } =20 /* Check if there is pending and not masked out interrupt */ -bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) +bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env) { uint32_t pending; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787309699632158500 Add the const qualifier to CPUMIPSState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/mips/cpu.h | 6 +++--- target/mips/internal.h | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 319147a948c..6404b342a5d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1372,19 +1372,19 @@ static inline bool ase_3d_available(const CPUMIPSSt= ate *env) } =20 /* Check presence of MSA implementation */ -static inline bool ase_msa_available(CPUMIPSState *env) +static inline bool ase_msa_available(const CPUMIPSState *env) { return env->CP0_Config3 & (1 << CP0C3_MSAP); } =20 /* Check presence of Loongson CSR instructions */ -static inline bool ase_lcsr_available(CPUMIPSState *env) +static inline bool ase_lcsr_available(const CPUMIPSState *env) { return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP); } =20 /* Check presence of multi-threading ASE implementation */ -static inline bool ase_mt_available(CPUMIPSState *env) +static inline bool ase_mt_available(const CPUMIPSState *env) { return env->CP0_Config3 & (1 << CP0C3_MT); } diff --git a/target/mips/internal.h b/target/mips/internal.h index c5c286872eb..7dba22300b1 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -165,7 +165,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val); =20 extern const VMStateDescription vmstate_mips_cpu; =20 -static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) +static inline bool cpu_mips_hw_interrupts_enabled(const CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && !(env->CP0_Status & (1 << CP0St_EXL)) && @@ -180,7 +180,7 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMI= PSState *env) } =20 /* Check if there is pending and not masked out interrupt */ -static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) +static inline bool cpu_mips_hw_interrupts_pending(const CPUMIPSState *env) { int32_t pending; int32_t status; @@ -247,9 +247,9 @@ static inline void restore_pamask(CPUMIPSState *env) } } =20 -static inline int mips_vpe_active(CPUMIPSState *env) +static inline int mips_vpe_active(const CPUMIPSState *env) { - MIPSCPU *cpu =3D env_archcpu(env); + const MIPSCPU *cpu =3D env_archcpu(env); int active =3D 1; =20 /* Check that the VPE is enabled. */ @@ -281,7 +281,7 @@ static inline int mips_vpe_active(CPUMIPSState *env) return active; } =20 -static inline int mips_vp_active(CPUMIPSState *env) +static inline int mips_vp_active(const CPUMIPSState *env) { CPUState *cs; =20 --=20 2.53.0 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787309822; cv=none; d=zohomail.com; s=zohoarc; b=lktTSHxklVfIin4VVoUfQ5lxUpY1HP/C8TS0AdA3biKYrSlwFaRlRoJSCEC0z68SLcrPxShG9lRZww/vPSILZvzjKHK2J4QHewMWRncGzzVNt0NXAF4YnmFfGWxM2yXrKiiFx/11hsylCN34ScqWn9EvFyB5U9X3iQnKp/VpwA4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787309824130158500 Add the const qualifier to S390CPU when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Ilya Leoshkevich Reviewed-by: Marc-Andr=C3=A9 Lureau Acked-by: Eric Farman --- target/s390x/cpu.h | 2 +- target/s390x/s390x-internal.h | 12 ++++++------ target/s390x/interrupt.c | 22 +++++++++++----------- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index f55b79ef8ac..998bbb0d7ff 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -854,7 +854,7 @@ static inline unsigned int s390_cpu_set_state(uint8_t c= pu_state, S390CPU *cpu) return 0; } #endif /* CONFIG_USER_ONLY */ -static inline uint8_t s390_cpu_get_state(S390CPU *cpu) +static inline uint8_t s390_cpu_get_state(const S390CPU *cpu) { return cpu->env.cpu_state; } diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 50782fac3ce..ca4445e6474 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -333,12 +333,12 @@ void cpu_inject_clock_comparator(S390CPU *cpu); void cpu_inject_cpu_timer(S390CPU *cpu); void cpu_inject_emergency_signal(S390CPU *cpu, uint16_t src_cpu_addr); int cpu_inject_external_call(S390CPU *cpu, uint16_t src_cpu_addr); -bool s390_cpu_has_io_int(S390CPU *cpu); -bool s390_cpu_has_ext_int(S390CPU *cpu); -bool s390_cpu_has_mcck_int(S390CPU *cpu); -bool s390_cpu_has_int(S390CPU *cpu); -bool s390_cpu_has_restart_int(S390CPU *cpu); -bool s390_cpu_has_stop_int(S390CPU *cpu); +bool s390_cpu_has_io_int(const S390CPU *cpu); +bool s390_cpu_has_ext_int(const S390CPU *cpu); +bool s390_cpu_has_mcck_int(const S390CPU *cpu); +bool s390_cpu_has_int(const S390CPU *cpu); +bool s390_cpu_has_restart_int(const S390CPU *cpu); +bool s390_cpu_has_stop_int(const S390CPU *cpu); void cpu_inject_restart(S390CPU *cpu); void cpu_inject_stop(S390CPU *cpu); #endif /* CONFIG_USER_ONLY */ diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c index 1dca835c5d8..d7e3fd45e4b 100644 --- a/target/s390x/interrupt.c +++ b/target/s390x/interrupt.c @@ -139,10 +139,10 @@ void s390_crw_mchk(void) fsc->inject_crw_mchk(fs); } =20 -bool s390_cpu_has_mcck_int(S390CPU *cpu) +bool s390_cpu_has_mcck_int(const S390CPU *cpu) { QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 if (!(env->psw.mask & PSW_MASK_MCHECK)) { return false; @@ -157,10 +157,10 @@ bool s390_cpu_has_mcck_int(S390CPU *cpu) return false; } =20 -bool s390_cpu_has_ext_int(S390CPU *cpu) +bool s390_cpu_has_ext_int(const S390CPU *cpu) { QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 if (!(env->psw.mask & PSW_MASK_EXT)) { return false; @@ -199,10 +199,10 @@ bool s390_cpu_has_ext_int(S390CPU *cpu) return false; } =20 -bool s390_cpu_has_io_int(S390CPU *cpu) +bool s390_cpu_has_io_int(const S390CPU *cpu) { QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 if (!(env->psw.mask & PSW_MASK_IO)) { return false; @@ -211,21 +211,21 @@ bool s390_cpu_has_io_int(S390CPU *cpu) return qemu_s390_flic_has_io(flic, env->cregs[6]); } =20 -bool s390_cpu_has_restart_int(S390CPU *cpu) +bool s390_cpu_has_restart_int(const S390CPU *cpu) { - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 return env->pending_int & INTERRUPT_RESTART; } =20 -bool s390_cpu_has_stop_int(S390CPU *cpu) +bool s390_cpu_has_stop_int(const S390CPU *cpu) { - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 return env->pending_int & INTERRUPT_STOP; } =20 -bool s390_cpu_has_int(S390CPU *cpu) +bool s390_cpu_has_int(const S390CPU *cpu) { if (!tcg_enabled()) { return false; --=20 2.53.0 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 376cff656fa..bb4c8563554 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -642,7 +642,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env); int riscv_cpu_vsirq_pending(CPURISCVState *env); int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_prio, - uint64_t pending, uint8_t *iprio); + uint64_t pending, const uint8_t *iprio); =20 =20 bool riscv_cpu_fp_enabled(CPURISCVState *env); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7bf098319f8..858fbf865fd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -866,7 +866,7 @@ uint8_t riscv_cpu_default_priority(int irq) =20 int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_prio, - uint64_t pending, uint8_t *iprio) + uint64_t pending, const uint8_t *iprio) { int irq, best_irq =3D RISCV_EXCP_NONE; unsigned int prio, best_prio =3D UINT_MAX; --=20 2.53.0 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787309780; cv=none; d=zohomail.com; s=zohoarc; b=UVrrxbCMKFsCu5yFNE8Vree8sy3lqNXKj4uj6fJGlJbVK1XjdtSFYVGqKhXVRkHJGevIdAmv6nzul+EIa4hVZnRnkq/X957QMmfwiSJmjjxd+zUJ7oFk+iEUo9rtZ67fSRU2no1tlpD/hNi7LCqlQCy6nwFqGmy++rGPgjdSUkI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787309780; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LWQwdDV2fkgFjhmKLwyo93xfsCf8ZqnI4jIB05mjxx8=; b=b64tPdwABa/eaiU8YgbDaPuXkS+0lVWhJrUS/X4G9kGr8DS4I8Ps7fUO8EOztogDZy93L51klHQK1T829zX5nqpXNhPjNUB0GLV43fu+l5PZ6A8d6kVKoDIWybkYFD007icO9i0C3kG2zEcg0XJaGKe33z/4KPHJZKtSCGcL1Co= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178730978061899.5291458949971; Fri, 21 Aug 2026 03:56:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxMqv-0006Ug-K0; Fri, 21 Aug 2026 06:52:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMqt-0006GB-5D for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:51:59 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMqp-0003j8-4c for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:51:58 -0400 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67L9LtO41799149 for ; Fri, 21 Aug 2026 10:51:39 GMT Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g6ecb9jnb-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 21 Aug 2026 10:51:39 +0000 (GMT) Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-52ce64c41efso15301701cf.3 for ; Fri, 21 Aug 2026 03:51:39 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787309782185158500 Add the const qualifier to CPURISCVState when the argument is accessed without modification. Simplify directly using cpu_env() in riscv_cpu_has_work(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/riscv/cpu.h | 27 ++++++++++++++------------- target/riscv/cpu.c | 13 ++++++------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bb4c8563554..c51e0d5f919 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -636,11 +636,11 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteA= rray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); uint8_t riscv_cpu_default_priority(int irq); -uint64_t riscv_cpu_all_pending(CPURISCVState *env); -int riscv_cpu_mirq_pending(CPURISCVState *env); -int riscv_cpu_sirq_pending(CPURISCVState *env); -int riscv_cpu_vsirq_pending(CPURISCVState *env); -int riscv_cpu_pending_to_irq(CPURISCVState *env, +uint64_t riscv_cpu_all_pending(const CPURISCVState *env); +int riscv_cpu_mirq_pending(const CPURISCVState *env); +int riscv_cpu_sirq_pending(const CPURISCVState *env); +int riscv_cpu_vsirq_pending(const CPURISCVState *env); +int riscv_cpu_pending_to_irq(const CPURISCVState *env, int extirq, unsigned int extirq_def_prio, uint64_t pending, const uint8_t *iprio); =20 @@ -746,20 +746,20 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) +static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env) { return env->misa_mxl; } #endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) =20 -static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) +static inline const RISCVCPUConfig *riscv_cpu_cfg(const CPURISCVState *env) { return &env_archcpu(env)->cfg; } =20 #if !defined(CONFIG_USER_ONLY) -static inline privilege_mode_t cpu_address_mode(CPURISCVState *env) +static inline privilege_mode_t cpu_address_mode(const CPURISCVState *env) { privilege_mode_t mode =3D env->priv; =20 @@ -769,7 +769,8 @@ static inline privilege_mode_t cpu_address_mode(CPURISC= VState *env) return mode; } =20 -static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mod= e) +static inline RISCVMXL cpu_get_xl(const CPURISCVState *env, + privilege_mode_t mode) { RISCVMXL xl =3D env->misa_mxl; /* @@ -797,7 +798,7 @@ static inline RISCVMXL cpu_get_xl(CPURISCVState *env, p= rivilege_mode_t mode) #if defined(TARGET_RISCV32) #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) +static inline RISCVMXL cpu_recompute_xl(const CPURISCVState *env) { #if !defined(CONFIG_USER_ONLY) return cpu_get_xl(env, env->priv); @@ -810,7 +811,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *= env) #if defined(TARGET_RISCV32) #define cpu_address_xl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL cpu_address_xl(CPURISCVState *env) +static inline RISCVMXL cpu_address_xl(const CPURISCVState *env) { #ifdef CONFIG_USER_ONLY return env->xl; @@ -822,7 +823,7 @@ static inline RISCVMXL cpu_address_xl(CPURISCVState *en= v) } #endif =20 -static inline uint16_t riscv_cpu_xlen(CPURISCVState *env) +static inline uint16_t riscv_cpu_xlen(const CPURISCVState *env) { return 16 << env->xl; } @@ -830,7 +831,7 @@ static inline uint16_t riscv_cpu_xlen(CPURISCVState *en= v) #ifdef TARGET_RISCV32 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) +static inline RISCVMXL riscv_cpu_sxl(const CPURISCVState *env) { #ifdef CONFIG_USER_ONLY return env->misa_mxl; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 858fbf865fd..4abf20d057a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -864,7 +864,7 @@ uint8_t riscv_cpu_default_priority(int irq) return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; }; =20 -int riscv_cpu_pending_to_irq(CPURISCVState *env, +int riscv_cpu_pending_to_irq(const CPURISCVState *env, int extirq, unsigned int extirq_def_prio, uint64_t pending, const uint8_t *iprio) { @@ -908,7 +908,7 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env, * using hvip bits 13:63 from HS-mode. Those are returned in * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending(). */ -uint64_t riscv_cpu_all_pending(CPURISCVState *env) +uint64_t riscv_cpu_all_pending(const CPURISCVState *env) { uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; @@ -917,7 +917,7 @@ uint64_t riscv_cpu_all_pending(CPURISCVState *env) return (env->mip | vsgein | vstip) & env->mie; } =20 -int riscv_cpu_mirq_pending(CPURISCVState *env) +int riscv_cpu_mirq_pending(const CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & ~env->mideleg & ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); @@ -926,7 +926,7 @@ int riscv_cpu_mirq_pending(CPURISCVState *env) irqs, env->miprio); } =20 -int riscv_cpu_sirq_pending(CPURISCVState *env) +int riscv_cpu_sirq_pending(const CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & ~env->hi= deleg; uint64_t irqs_f =3D env->mvip & env->mvien & ~env->mideleg & env->sie; @@ -935,7 +935,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env) irqs | irqs_f, env->siprio); } =20 -int riscv_cpu_vsirq_pending(CPURISCVState *env) +int riscv_cpu_vsirq_pending(const CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & env->hid= eleg; uint64_t irqs_f_vs =3D env->hvip & env->hvien & ~env->hideleg & env->v= sie; @@ -952,8 +952,7 @@ int riscv_cpu_vsirq_pending(CPURISCVState *env) =20 static bool riscv_cpu_has_work(CPUState *cs) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); /* * Definition of the WFI instruction requires it to ignore the privile= ge * mode and delegation registers, but respect individual enables --=20 2.53.0 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787309681; cv=none; d=zohomail.com; s=zohoarc; b=ioAG0ZU2ZNxoPLAHnQwK0by/1zLoXdyxKE7eroR03omZn5a6hiRFmHpJ7dO/mRSW+PNCOm9IvCaYLBw/1JyyKkpyFtFlIlGZ8kVaFF6ax6d/gDXe9/XuaX1vP+nmNAbIVSIZ3IX1qMB2mDoLJFMDxilzmpZyDW8gSgjdihMARvY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787309681; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GkfJ0DUVwjpw7Jql39GIYw8AYSod2OF3xVsMsf7lww4=; b=P9bmiNP32wu3g9WyLpVcUI/+1kkm4BiRJ8HKhVCjtQv7dyQie755Qisk7Sxh4b88izqABLG0WxDFB3u1GQ3ndA0QBE+aWH79b4ifSRqcF7SPfpbeBF56JODOwHYPy4SVVTHW1+x7jFdCiAsrWRpN2upC3Fw1/hRSMUbuxaWOkbU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787309681857110.59046853381255; Fri, 21 Aug 2026 03:54:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxMqm-0005kb-BB; Fri, 21 Aug 2026 06:51:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMqk-0005ca-9Q for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:51:50 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMqi-0003ki-Er for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:51:49 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67L9Lmk51474486 for ; Fri, 21 Aug 2026 10:51:47 GMT Received: from mail-qk1-f200.google.com (mail-qk1-f200.google.com [209.85.222.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g6fbw9bf5-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 21 Aug 2026 10:51:46 +0000 (GMT) Received: by mail-qk1-f200.google.com with SMTP id af79cd13be357-91931144870so102432185a.1 for ; Fri, 21 Aug 2026 03:51:46 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787309683807158500 Add the const qualifier to CPUSPARCState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/sparc/cpu.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 5f583ed9de2..31a16c2af03 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -680,28 +680,28 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, = target_ulong addr, #endif =20 #if defined (TARGET_SPARC64) -static inline int cpu_has_hypervisor(CPUSPARCState *env1) +static inline int cpu_has_hypervisor(const CPUSPARCState *env1) { return env1->def.features & CPU_FEATURE_HYPV; } =20 -static inline int cpu_hypervisor_mode(CPUSPARCState *env1) +static inline int cpu_hypervisor_mode(const CPUSPARCState *env1) { return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); } =20 -static inline int cpu_supervisor_mode(CPUSPARCState *env1) +static inline int cpu_supervisor_mode(const CPUSPARCState *env1) { return env1->pstate & PS_PRIV; } #else -static inline int cpu_supervisor_mode(CPUSPARCState *env1) +static inline int cpu_supervisor_mode(const CPUSPARCState *env1) { return env1->psrs; } #endif =20 -static inline int cpu_interrupts_enabled(CPUSPARCState *env1) +static inline int cpu_interrupts_enabled(const CPUSPARCState *env1) { #if !defined (TARGET_SPARC64) if (env1->psret !=3D 0) @@ -715,7 +715,7 @@ static inline int cpu_interrupts_enabled(CPUSPARCState = *env1) return 0; } =20 -static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) +static inline int cpu_pil_allowed(const CPUSPARCState *env1, int pil) { #if !defined(TARGET_SPARC64) /* level 15 is non-maskable on sparc v8 */ --=20 2.53.0 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787309771; cv=none; d=zohomail.com; s=zohoarc; b=lQSxqpLURabTcuL9UxMBxuA+4HZmtztTYzIEaP2xGj2IrLcjSuU989zL91y6cQfPvPl+jCSW7UmfiH5RCPMQqjRejpfZ7HF80v0lg0sCdd0hmoSMztC7AmiOEAalJaESDQ9yOVnt6VyLu6+VXESN8DuOk6n1kkc0YxI3XtotcG8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787309771; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iDP7SSBBed9OilMDhZqOv3xXCrS8V81wrx791E5ihCQ=; b=JooZEyUlmvG37xHWG6XcYYFhlR6FzepeWz7/q4rFpnO2EFEDqyCHYIA91Ebyk7kqiJ5C9YBbo6Bi26pnRCWSEaVz35Hqhp2cO4adnsAWueh1SPfs7J54V3jVUqDK7DDHE/c3rWjC7XnvMtjOeBzVurxftljGtbauVUW5TC1Ss3U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787309770968405.99394620374767; Fri, 21 Aug 2026 03:56:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxMqx-0006cc-MC; Fri, 21 Aug 2026 06:52:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMqv-0006TV-B1 for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:52:01 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMqp-0003o1-EJ for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:52:01 -0400 Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67L9Lhi11983011 for ; Fri, 21 Aug 2026 10:51:54 GMT Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g6cdshx51-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 21 Aug 2026 10:51:53 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-936708f129aso70879185a.0 for ; Fri, 21 Aug 2026 03:51:53 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Fri, 21 Aug 2026 03:51:52 -0700 (PDT) X-Received: by 2002:a05:620a:f0d:b0:930:f337:ebeb with SMTP id af79cd13be357-93739574e95mr408163385a.12.1787309512544; Fri, 21 Aug 2026 03:51:52 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 14/15] target/tricore: Document architectural interrupts as not implemented Date: Fri, 21 Aug 2026 12:49:48 +0200 Message-ID: <20260821104950.32108-15-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260821104950.32108-1-philmd@oss.qualcomm.com> References: <20260821104950.32108-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: q6kFTTPrrxR3jjC68IjLWq2vgxiyrI0M X-Proofpoint-GUID: q6kFTTPrrxR3jjC68IjLWq2vgxiyrI0M X-Proofpoint-Spam-Info: AW1haW4tMjYwODIxMDA4MSBTYWx0ZWRfX7Lsrec6TVLP+ 5p5CH3Dg0URQPWNhwCOoVIgyolslZsRUQ6qZwWkcQvL5MqzUCslmHnfnUe8bHYjRJaM1oifCux2 fqaXDL4Ly5FeER33PGu5sR7+gBcNeDg= X-Authority-Analysis: v=2.4 cv=RN2D2Yi+ c=1 sm=1 tr=0 ts=6a882dc9 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=Cu_OB6cER5A0ZMY7a4UA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIxMDA4MSBTYWx0ZWRfX1B9qvUfc9jMK 4Q612Epr0KVcZBmF9iUcTru7ZCgRqWEwQScpj1kveh2y0HIZt5+4/n/hVYeYl8VQO9npWqqF32P VkvIrMTpjaHEap1cnG+FJcrYMesIuaBFWWZ8Xvr3GjCoZkz2zVVWwciT+F2/BQOGB4JAOEY1yQ9 BaMnm2BxhqmcdA5NrxwVwXyvsH4jvwL/MDBYNwVCRzEaWk89e0+x5WAKT9TlmZXCnAxeMOLTPci 84Pk48rT3gofFnH3bLJGgL3H+qHx2mORItDrLp/ZwP+0cPjc8eS4RhEXbOMGwmXYk4xgjdXPFZr 2wpY3sa9EqpAwZQU/TNsRcIcX0bu0jxT84JyNwZm7PVsa6ks/Ylp68SnaVUb1RObI/rsp7CKGeF vTiJW6DP9V0XjytbWmW7CaYh9FalbTw2DU/EKf2c15CEHU4s9fhfr8ApuOznPb9GcwiRhSqDONy h1zLS4WcUVuNfZVui9g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-21_03,2026-08-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608210081 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787309771855158500 As mentioned in commit de680286b52 ("accel/tcg: Make cpu_exec_interrupt hook mandatory"): > Tricore doesn't currently implement the architectural > interrupt handling. Add a comment to help understanding why this SysemuCPUOps has_work() handler is simply always returning %true. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/tricore/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 6d448727005..82b56c3cd56 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -113,6 +113,7 @@ static void tricore_cpu_reset_hold(Object *obj, ResetTy= pe type) =20 static bool tricore_cpu_has_work(CPUState *cs) { + /* Interrupts are not implemented */ return true; } =20 --=20 2.53.0 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787309797; cv=none; d=zohomail.com; s=zohoarc; b=LVU827k7m6nfFujL4vlnBH13wfQr0ucn06vQ4Kx4I3HezLmleCSMEtAk+dDf3BBLEPx6dV4+Sqw6cN8Q5dmPQpDP48LLgRMe8G10/7IvYdTQ1/V/zF1dSRS2yiGg74VIE2F7QfesJh1oFXJ1LD4NdAvlxHkvvTwQ0K34GcsfwyU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787309797; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=v0jRSni95ip9s5P+6XUNJn9C/EPniwNloVe3wNAKBxI=; b=Jjvf23L7vhZtmWZjJgnKSWAqPVYsoNapspT5JhUdCth/HzVDgSWpjqJ/yHPl2ceFJY3yc+7UxGEksk+9cD7tJuqRfFrJcbiM/CF/Y8QGtWbpWQcwnS07SgtHrkfJTrA8vGfmg5KtzgW1uHg4htEuld6NfOR2xfEH7pGYjKLSKGo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787309797969557.7369959570374; Fri, 21 Aug 2026 03:56:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wxMrE-00077T-Kq; Fri, 21 Aug 2026 06:52:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMrD-00072T-Ef for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:52:19 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wxMr9-0003sD-Bd for qemu-devel@nongnu.org; Fri, 21 Aug 2026 06:52:19 -0400 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67L9LrPq1799100 for ; Fri, 21 Aug 2026 10:52:04 GMT Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g6ecb9jq3-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 21 Aug 2026 10:52:04 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-51c0e702df8so10563161cf.2 for ; Fri, 21 Aug 2026 03:52:04 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Cornelia Huck , Eric Farman , Matthew Rosato , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v3 15/15] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Date: Fri, 21 Aug 2026 12:49:49 +0200 Message-ID: <20260821104950.32108-16-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260821104950.32108-1-philmd@oss.qualcomm.com> References: <20260821104950.32108-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIxMDA4MSBTYWx0ZWRfX5ccoI1lj1wc+ gV1KpJOGIdFtHvZlfbgQByfH3DwmqLtDx7HQC/1gAKN1xB4btCrGEc5zZGH5dWjwIlOqUligKGc lN0I9N2Wekh3bxOXVaftC/v2K4NMJYbTJy94F/tDEb5QeOpSjjHKI6sKeuAIHPcX2/gcQdghb84 VvQPqlnOHJAgN8xqSiPiUQ9i7D7IntATT+2Iga3wpTZi0bk3vQh1KMHS4BmZtrtwU8ghYZKTrod rMFcsUndLbcSbjNGXd5hZAImzS5aG6MDHzuKCgUdflzpdQE2556Gl0TmhLwsLR+7ui8Dmdsp/SG KwA2mbQmD1K5B3L/28jcm819vDzE/kZwCiJwuWduOa387+km5PNkN5jQ7fzSRUO3QP1y/lQKmaG C7JVyGr9h5TeKGus0x1pM+O8LccFaTwusiOsdXbi5vrsEBvFUxhRkDY0Hfpc9a+HCtouaVC4d4X DKIknbbjPrLE41jBTvQ== X-Authority-Analysis: v=2.4 cv=e/s2j6p/ c=1 sm=1 tr=0 ts=6a882dd4 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=hf0YJCTCBZPsvBMCq-cA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: 8jeDNqfbTBoPo3LmEU66OFN89cbDuRIj X-Proofpoint-Spam-Info: AW1haW4tMjYwODIxMDA4MSBTYWx0ZWRfX4QEU0n4uwjq7 q22Q9g12EH9FKDhetJxTjVqEr7mCNvHdQRT7+QyFjSdEdA8de7dpcwFaMcRuGKq8Byx4JysWQiT TVmjQSJm17nAZpp6s8VPQ5vxguKOENc= X-Proofpoint-ORIG-GUID: 8jeDNqfbTBoPo3LmEU66OFN89cbDuRIj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-21_03,2026-08-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 suspectscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608210081 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787309800520158500 All functions called by target has_work() handler take a const @cpu argument. We can now fulfill the comment added in commit c2804566f6 ("target/arm: do not clear halting reason in has_work helper"), qualifying the handler const to denote its idempotency. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/sysemu-cpu-ops.h | 4 ++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 4 ++-- target/avr/cpu.c | 3 ++- target/hexagon/cpu.c | 4 ++-- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 4 ++-- target/or1k/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu-system.c | 4 ++-- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 4 ++-- 20 files changed, 27 insertions(+), 26 deletions(-) diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 9a45596169a..095bdcd997a 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -19,10 +19,10 @@ typedef struct SysemuCPUOps { /** * @has_work: Callback for checking if there is work to do. * - * This function should be idempotent (i.e. not change state) as + * This function is idempotent (i.e. not change state) as * it will likely be queried multiple times before a CPU resumes. */ - bool (*has_work)(CPUState *cpu); /* MANDATORY NON-NULL */ + bool (*has_work)(const CPUState *cpu); /* MANDATORY NON-NULL */ /** * @get_memory_mapping: Callback for obtaining the memory mappings. */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 7d1d036e1d3..21d4f8ac23b 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -77,7 +77,7 @@ static void alpha_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool alpha_cpu_has_work(CPUState *cs) +static bool alpha_cpu_has_work(const CPUState *cs) { /* Here we are checking to see if the CPU should wake up from HALT. We will have gotten into this state only for WTINT from PALmode. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9761bb173c1..ba66359d410 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -141,9 +141,9 @@ int arm_cpu_mmu_index(CPUState *cs, bool ifetch) * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here * unconditionally. */ -static bool arm_cpu_has_work(CPUState *cs) +static bool arm_cpu_has_work(const CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); + const ARMCPU *cpu =3D ARM_CPU(cs); =20 /* * Only another PSCI call can wake the CPU up in which case the diff --git a/target/avr/cpu.c b/target/avr/cpu.c index a01e6fa4751..a96bef46ff1 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -23,6 +23,7 @@ #include "qemu/qemu-print.h" #include "exec/translation-block.h" #include "system/address-spaces.h" +#include "hw/core/cpu.h" #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" @@ -43,7 +44,7 @@ static vaddr avr_cpu_get_pc(CPUState *cs) return cpu->env.pc_w * 2; } =20 -static bool avr_cpu_has_work(CPUState *cs) +static bool avr_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET) && cpu_interrupts_enabled(cpu_env(cs)); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 4cc6bd67c28..868aef0cde4 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -364,9 +364,9 @@ bool hexagon_thread_is_enabled(const CPUHexagonState *e= nv) return E_bit; } =20 -static bool hexagon_cpu_has_work(CPUState *cs) +static bool hexagon_cpu_has_work(const CPUState *cs) { - CPUHexagonState *env =3D cpu_env(cs); + const CPUHexagonState *env =3D cpu_env(cs); =20 return hexagon_thread_is_enabled(env) && (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 7b1309a7c38..dbf58466c24 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -134,7 +134,7 @@ static void hppa_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool hppa_cpu_has_work(CPUState *cs) +static bool hppa_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1fc02cf94e6..0606ac16664 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10638,7 +10638,7 @@ int x86_cpu_pending_interrupt(const CPUState *cs, i= nt interrupt_request) return 0; } =20 -static bool x86_cpu_has_work(CPUState *cs) +static bool x86_cpu_has_work(const CPUState *cs) { return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; } diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 2dbe2203b20..7bf7596172b 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -96,7 +96,7 @@ bool cpu_loongarch_hw_interrupts_pending(const CPULoongAr= chState *env) #endif =20 #ifndef CONFIG_USER_ONLY -static bool loongarch_cpu_has_work(CPUState *cs) +static bool loongarch_cpu_has_work(const CPUState *cs) { bool has_work =3D false; =20 diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 523694d8fbf..da3681fab1f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -76,7 +76,7 @@ static void m68k_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool m68k_cpu_has_work(CPUState *cs) +static bool m68k_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6013a8def8e..d1d2f0ec7e3 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -127,7 +127,7 @@ static void mb_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool mb_cpu_has_work(CPUState *cs) +static bool mb_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c069aa1c0b7..0f39f8fe0a5 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -134,9 +134,9 @@ static vaddr mips_cpu_get_pc(CPUState *cs) } =20 #if !defined(CONFIG_USER_ONLY) -static bool mips_cpu_has_work(CPUState *cs) +static bool mips_cpu_has_work(const CPUState *cs) { - CPUMIPSState *env =3D cpu_env(cs); + const CPUMIPSState *env =3D cpu_env(cs); bool has_work =3D false; =20 /* diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c index 42d9351b6d7..10b13ae69cd 100644 --- a/target/or1k/cpu.c +++ b/target/or1k/cpu.c @@ -76,7 +76,7 @@ static void openrisc_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool openrisc_cpu_has_work(CPUState *cs) +static bool openrisc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER= ); } diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 85a91ff4bb6..fd63cd6ab09 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7224,7 +7224,7 @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetc= h) #endif /* CONFIG_TCG */ =20 #ifndef CONFIG_USER_ONLY -static bool ppc_cpu_has_work(CPUState *cs) +static bool ppc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4abf20d057a..3560fbd445e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -950,7 +950,7 @@ int riscv_cpu_vsirq_pending(const CPURISCVState *env) (irqs | irqs_f_vs), env->hviprio); } =20 -static bool riscv_cpu_has_work(CPUState *cs) +static bool riscv_cpu_has_work(const CPUState *cs) { CPURISCVState *env =3D cpu_env(cs); /* diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 69946928995..dfa09a85bce 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -73,7 +73,7 @@ static void rx_restore_state_to_opc(CPUState *cs, cpu->env.pc =3D data[0]; } =20 -static bool rx_cpu_has_work(CPUState *cs) +static bool rx_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c index 84faceb3338..3a0ff46e144 100644 --- a/target/s390x/cpu-system.c +++ b/target/s390x/cpu-system.c @@ -39,9 +39,9 @@ #include "system/tcg.h" #include "hw/core/sysemu-cpu-ops.h" =20 -static bool s390_cpu_has_work(CPUState *cs) +static bool s390_cpu_has_work(const CPUState *cs) { - S390CPU *cpu =3D S390_CPU(cs); + const S390CPU *cpu =3D S390_CPU(cs); =20 /* STOPPED cpus can never wake up */ if (s390_cpu_get_state(cpu) !=3D S390_CPU_STATE_LOAD && diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 55c73a1da35..b0ed356d0f7 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -107,7 +107,7 @@ static bool superh_io_recompile_replay_branch(CPUState = *cs, return false; } =20 -static bool superh_cpu_has_work(CPUState *cs) +static bool superh_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 2baa5036871..8dd9b0d5ee3 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -783,7 +783,7 @@ static void sparc_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool sparc_cpu_has_work(CPUState *cs) +static bool sparc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && cpu_interrupts_enabled(cpu_env(cs)); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 82b56c3cd56..357f3737053 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -111,7 +111,7 @@ static void tricore_cpu_reset_hold(Object *obj, ResetTy= pe type) cpu_state_reset(cpu_env(cs)); } =20 -static bool tricore_cpu_has_work(CPUState *cs) +static bool tricore_cpu_has_work(const CPUState *cs) { /* Interrupts are not implemented */ return true; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 99c8bd4b5fb..1b299568776 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -140,9 +140,9 @@ static void xtensa_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool xtensa_cpu_has_work(CPUState *cs) +static bool xtensa_cpu_has_work(const CPUState *cs) { - CPUXtensaState *env =3D cpu_env(cs); + const CPUXtensaState *env =3D cpu_env(cs); =20 return !env->runstall && env->pending_irq_level; } --=20 2.53.0