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Fri, 21 Aug 2026 16:20:02 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1787300403; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=7kYP1SmE4po1NHX60o1wn5jt4JN1ovNWLbqMRiHorT8=; b=ZteR+t0/97UWbV235VFI3/awPGp18I6cAef4AcRapRBhPZRQfqB2SIao2EwhLgJz99DKXSMBsLHwg9qZDfu1beaa5qJ2Q+7npV+jwegrO+C67wmU4HQBpXfauGqSA6vCH5CtwIg3K/oF7IoqGpNHh5ZYpDO7qVWv+NFKjUO8MLE= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R181e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045098064; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=19; SR=0; TI=SMTPD_---0X9LmLtZ_1787300402; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH 1/4] hw/riscv/virt: Add CXL support to the RISC-V virt machine Date: Fri, 21 Aug 2026 16:19:51 +0800 Message-ID: <20260821081954.1171-2-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821081954.1171-1-cp0613@linux.alibaba.com> References: <20260821081954.1171-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.118 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Enable CXL support on the RISC-V virt machine following the same approach used by the ARM virt machine: - Add PXB and ACPI_CXL Kconfig selections - Add CXLState and PCIBus pointer to RISCVVirtState - Register CXL machine properties via cxl_machine_init() - Create CXL host register region above the PCIe high MMIO region - Call cxl_hook_up_pxb_registers() and cxl_fmws_link_targets() at machine_done time - Map Fixed Memory Windows above the CXL host register region - Add ACPI0017 device in DSDT and build CEDT table in virt-acpi-build.c Signed-off-by: Chen Pei --- hw/riscv/Kconfig | 2 ++ hw/riscv/virt-acpi-build.c | 20 ++++++++++++++++++++ hw/riscv/virt.c | 37 +++++++++++++++++++++++++++++++++++++ include/hw/riscv/virt.h | 3 +++ 4 files changed, 62 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index de37c08cae..0ba3cd9e15 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -66,8 +66,10 @@ config RISCV_VIRT select VIRTIO_MMIO select FW_CFG_DMA select PLATFORM_BUS + select PXB select ACPI select ACPI_PCI + select ACPI_CXL =20 config SHAKTI_C bool diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 59c454f4f9..3188cdc5bf 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -29,12 +29,16 @@ #include "hw/acpi/aml-build.h" #include "hw/acpi/pci.h" #include "hw/acpi/utils.h" +#include "hw/acpi/cxl.h" #include "hw/intc/riscv_aclint.h" #include "hw/nvram/fw_cfg_acpi.h" #include "hw/pci-host/gpex.h" +#include "hw/pci/pci_bus.h" #include "hw/riscv/virt.h" #include "hw/riscv/numa.h" #include "hw/virtio/virtio-acpi.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "kvm/kvm_riscv.h" #include "migration/vmstate.h" #include "qapi/error.h" @@ -514,6 +518,17 @@ static void build_dsdt(GArray *table_data, acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + s->num_sources * 2); } =20 + if (s->cxl_devices_state.is_enabled) { + Aml *cxl_dev =3D aml_device("CXLM"); + aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + Aml *method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0x0B))); + aml_append(cxl_dev, method); + build_cxl_dsm_method(cxl_dev); + + aml_append(scope, cxl_dev); + } + aml_append(dsdt, scope); =20 /* copy AML table into ACPI tables blob and patch header there */ @@ -921,6 +936,11 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBui= ldTables *tables) s->oem_table_id); } =20 + if (s->cxl_devices_state.is_enabled) { + cxl_build_cedt(table_offsets, tables_blob, tables->linker, + s->oem_id, s->oem_table_id, &s->cxl_devices_state); + } + if (ms->numa_state->num_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, s); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 51bac47a91..e08c76af4d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -55,6 +55,8 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "hw/acpi/aml-build.h" #include "qapi/qapi-visit-common.h" #include "hw/virtio/virtio-iommu.h" @@ -1101,9 +1103,33 @@ static inline DeviceState *gpex_pcie_init(MemoryRegi= on *sys_mem, } =20 GPEX_HOST(dev)->gpex_cfg.bus =3D PCI_HOST_BRIDGE(dev)->bus; + s->pci_bus =3D PCI_HOST_BRIDGE(dev)->bus; return dev; } =20 +static void cxl_host_state_init(RISCVVirtState *s) +{ + MemoryRegion *sysmem =3D get_system_memory(); + MemoryRegion *mr =3D &s->cxl_devices_state.host_mr; + hwaddr base; + + if (!s->cxl_devices_state.is_enabled) { + return; + } + + base =3D virt_high_pcie_memmap.base + virt_high_pcie_memmap.size; + base =3D ROUND_UP(base, 64 * KiB); + + memory_region_init(mr, OBJECT(s), "cxl_host_reg", 64 * KiB * 16); + memory_region_add_subregion(sysmem, base, mr); + + /* Map the Fixed Memory Windows above the CXL host register region. */ + base +=3D memory_region_size(mr); + base =3D ROUND_UP(base, 256 * MiB); + cxl_fmws_set_memmap(base, UINT64_MAX); + cxl_fmws_update_mmio(); +} + static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) { FWCfgState *fw_cfg; @@ -1205,6 +1231,13 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) machine_done); MachineState *machine =3D MACHINE(s); hwaddr start_addr =3D s->memmap[VIRT_DRAM].base; + + cxl_hook_up_pxb_registers(s->pci_bus, &s->cxl_devices_state, + &error_fatal); + + if (s->cxl_devices_state.is_enabled) { + cxl_fmws_link_targets(&error_fatal); + } hwaddr firmware_end_addr; vaddr kernel_start_addr; const char *firmware_name =3D riscv_default_firmware_name(&s->soc[0]); @@ -1451,6 +1484,8 @@ static void virt_machine_init(MachineState *machine) ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.siz= e); } =20 + cxl_host_state_init(s); + /* register system main memory (actual RAM) */ memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base, machine->ram); @@ -1558,6 +1593,8 @@ static void virt_machine_instance_init(Object *obj) s->acpi =3D ON_OFF_AUTO_AUTO; s->iommu_sys =3D ON_OFF_AUTO_AUTO; s->num_sources =3D VIRT_IRQCHIP_NUM_SOURCES; + + cxl_machine_init(obj, &s->cxl_devices_state); } =20 static char *virt_get_aia_guests(Object *obj, Error **errp) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 36a2def410..4cf930ab9f 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -24,6 +24,7 @@ #include "hw/core/sysbus.h" #include "hw/block/flash.h" #include "hw/intc/riscv_imsic.h" +#include "hw/cxl/cxl.h" =20 #define VIRT_CPUS_MAX_BITS 9 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) @@ -65,6 +66,8 @@ struct RISCVVirtState { OnOffAuto iommu_sys; uint16_t pci_iommu_bdf; uint16_t num_sources; + CXLState cxl_devices_state; + PCIBus *pci_bus; }; =20 enum { --=20 2.50.1 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1787300502; cv=none; d=zohomail.com; s=zohoarc; b=Ohw39W4zwSt60tVujY/JMq4XCB7YUY5FQyCSnbbQM9pDRyKOzPcmmFJKfUHbVZdnw5XSWTvpHYx6yBzJUMqBnAkxYb+8tuQxKvvIyqvw0Uba37oH9MKyaPiJlryggi2HndB5DQf/q/8V3crxlVomR74fU3Rj2LBM4LmBOhi9R+I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787300502; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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RN=20; SR=0; TI=SMTPD_---0X9LmLts_1787300403; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, Sunil V L Subject: [PATCH 2/4] hw/riscv/virt-acpi-build: Add _DEP to ACPI0017 for CXL host bridge dependency Date: Fri, 21 Aug 2026 16:19:52 +0800 Message-ID: <20260821081954.1171-3-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821081954.1171-1-cp0613@linux.alibaba.com> References: <20260821081954.1171-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.119 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" On RISC-V QEMU virt platform with CXL enabled, the probe ordering of acpi_pci_root (ACPI0016) and cxl_acpi (ACPI0017) is not guaranteed. If cxl_acpi probes before acpi_pci_root has attached the CXL host bridges, the CXL port topology will be incomplete because to_cxl_host_bridge() silently skips devices whose PCI root is not yet ready. Add a _DEP object to the ACPI0017 device in the DSDT, declaring its dependency on the ACPI0016 CXL host bridge devices. This tells the OS to defer ACPI0017 enumeration until all ACPI0016 devices have been attached by acpi_pci_root. This requires a corresponding kernel change to call acpi_dev_clear_dependencies() in acpi_pci_root_add(). Note on kernel compatibility: this is a "new QEMU feature requires a sufficiently new kernel" situation. Kernels that process _DEP but lack the acpi_dev_clear_dependencies() call will leave the CXLM device deferred, so CXL memory is unusable there; kernels old enough to ignore _DEP entirely behave exactly as before this change. In neither case is existing (non-CXL) PCIe affected. The resulting DSDT fragment (iasl -d output) for a single CXL host bridge at bus 0x01 looks like: Device (CXLM) { Name (_HID, "ACPI0017") Name (_DEP, Package (0x01) { \_SB.PC01 }) Method (_STA, 0, NotSerialized) { Return (0x0B) } ... } Reviewed-by: Sunil V L Signed-off-by: Chen Pei --- hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 3188cdc5bf..56292f04a7 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -521,6 +521,38 @@ static void build_dsdt(GArray *table_data, if (s->cxl_devices_state.is_enabled) { Aml *cxl_dev =3D aml_device("CXLM"); aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + + /* + * Declare a _DEP on every ACPI0016 CXL host bridge so the OS + * defers ACPI0017 enumeration until acpi_pci_root has attached + * the CXL host bridges. Without this, cxl_acpi may probe before + * to_cxl_host_bridge() can resolve the PCI root and the CXL + * port topology comes up empty. + */ + if (s->pci_bus) { + PCIBus *bus; + uint32_t num_cxl_hbs =3D 0; + + QLIST_FOREACH(bus, &s->pci_bus->child, sibling) { + if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) { + num_cxl_hbs++; + } + } + + if (num_cxl_hbs > 0) { + Aml *dep_pkg =3D aml_package(num_cxl_hbs); + + QLIST_FOREACH(bus, &s->pci_bus->child, sibling) { + if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) { + aml_append(dep_pkg, + aml_name("\\_SB.PC%.02X", + pci_bus_num(bus))); + } + } + aml_append(cxl_dev, aml_name_decl("_DEP", dep_pkg)); + } + } + Aml *method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); aml_append(method, aml_return(aml_int(0x0B))); aml_append(cxl_dev, method); --=20 2.50.1 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1787300405; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; bh=/23PizEp50RcPDZT+s3J0RsUX/+EgorfQW0a0MUxPNo=; b=cDGdWy8szQvOblSWVbDZw6fi+9olFbVs6blLcJIxoq9xw5yW5qXeiwvCtu5YLdXsBOxqy6BYtBRkiJWHZh7NmCRdYltCTV/vW27cuo62XvNy6zr8Eg3kQX19g1bAtYExMihBY4IWsMg+libWDChxa3mcPqhP1KrbV5HViD954n8= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R171e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037026112; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=19; SR=0; TI=SMTPD_---0X9LmLu9_1787300404; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH 3/4] hw/riscv/virt: Provide a 32-bit MMIO window for CXL host bridges Date: Fri, 21 Aug 2026 16:19:53 +0800 Message-ID: <20260821081954.1171-4-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821081954.1171-1-cp0613@linux.alibaba.com> References: <20260821081954.1171-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.119 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.30.119; envelope-from=cp0613@linux.alibaba.com; helo=out30-119.freemail.mail.aliyun.com X-Spam_score_int: -166 X-Spam_score: -16.7 X-Spam_bar: ---------------- X-Spam_report: (-16.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1787300460053158500 CXL component register BAR (BAR0 on CXL Root Port and Type3 device) and the CXL device register BAR (BAR2 on Type3 device) are declared as 64-bit non-prefetchable memory. Per the PCI-to-PCI Bridge Architecture Specification Rev 1.2 (PCI-SIG, 2003): - =C2=A73.2.5.8 (Memory Base/Limit): the non-prefetchable window covers only 32-bit addresses (AD[31:20]); the Type 1 header defines no upper-32-bit extension for it. - =C2=A73.2.5.9 (Prefetchable Memory Base/Limit): the bottom 4 bits encode 64-bit support (01h), but this applies exclusively to the *prefetchable* window. - =C2=A73.2.5.10 (Prefetchable Base/Limit Upper 32 Bits): optional registers for AD[63:32] of the prefetchable range only. The architecture therefore allows a 64-bit window only when it is also prefetchable; there is no 64-bit non-prefetchable form. PCIe inherits this Type 1 header layout unchanged. Linux thus places 64-bit non-prefetchable BARs in the 32-bit non-prefetchable bridge window, which requires the bridge to own enough address space below 4 GiB. On RISC-V virt the 32-bit PCIe MMIO range (1 GiB at 0x40000000) is currently consumed entirely by PCI0, so CXL host bridges (ACPI0016) have no non-prefetchable window and Linux fails to assign these BARs. Reserve the top 256 MiB of the 32-bit MMIO window exclusively for CXL host bridges, keeping all of the logic in the riscv code: - Reduce the FDT 'ranges' for PCI0 by 256 MiB so that device-tree driven firmware does not hand that range to PCI0. - The CXL host bridge _CRS is produced by the generic build_crs() path. EDK2's PciBusDxe only recurses into PCI-to-PCI bridges, while the pxb-cxl expander bridge presents as a class 0x0600 host bridge with a type-0 header, so firmware never enumerates behind it and leaves the CXL root port's window and bus-number registers unset; build_crs() would therefore return an empty _CRS. Simulate the firmware PCI initialization in virt_cxl_init_bridge_windows(): assign the reserved window to the root port's memory window, and allocate primary/secondary/subordinate bus numbers depth-first. build_crs() then emits both the memory range and a correct bus-range resource (without a bus range Linux only claims the host-bridge bus and cannot enumerate the devices behind the root port), and the range is excluded from PCI0's _CRS. A reset handler re-applies the state, as a PCI reset clears those registers. This targets a single pxb-cxl (one CXL host bridge), which matches the bios-tables test added later in the series. With more than one pxb-cxl the single reserved window would be claimed by every ACPI0016 bridge, so it would need to be partitioned per bridge; that is left as future work (see the TODO in virt_cxl_init_bridge_windows()). Verified by booting an RVA22 kernel: the CXL root port and Type3 device are enumerated (0000:0c:00.0 / 0000:0d:00.0) and 'cxl list' reports the memdev and the CFMWS root decoder. Signed-off-by: Chen Pei --- hw/riscv/virt.c | 154 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 153 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e08c76af4d..af83603293 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -48,11 +48,13 @@ #include "chardev/char.h" #include "system/device_tree.h" #include "system/system.h" +#include "system/reset.h" #include "system/tcg.h" #include "system/kvm.h" #include "system/tpm.h" #include "system/qtest.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" #include "hw/cxl/cxl.h" @@ -115,6 +117,9 @@ static const MemMapEntry virt_memmap[] =3D { /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) =20 +/* 32-bit MMIO range carved out of VIRT_PCIE_MMIO for CXL host bridges */ +#define VIRT_CXL_MMIO32_SIZE (256 * MiB) + static MemMapEntry virt_high_pcie_memmap; =20 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) @@ -727,6 +732,18 @@ static void create_fdt_pcie(RISCVVirtState *s, { g_autofree char *name =3D NULL; MachineState *ms =3D MACHINE(s); + /* + * When CXL is enabled, reserve the last 256 MiB of the 32-bit MMIO + * window for CXL host bridges and exclude it from the main PCIe host + * bridge's FDT 'ranges' so UEFI's PciHostBridgeDxe does not allocate + * that range to PCI0. The CXL host bridge _CRS declares this range + * independently. + */ + hwaddr mmio32_size =3D s->memmap[VIRT_PCIE_MMIO].size; + + if (s->cxl_devices_state.is_enabled) { + mmio32_size -=3D VIRT_CXL_MMIO32_SIZE; + } =20 name =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIx, s->memmap[VIRT_PCIE_ECAM].base); @@ -752,7 +769,7 @@ static void create_fdt_pcie(RISCVVirtState *s, 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size, 1, FDT_PCI_RANGE_MMIO, 2, s->memmap[VIRT_PCIE_MMIO].base, - 2, s->memmap[VIRT_PCIE_MMIO].base, 2, s->memmap[VIRT_PCIE_MMIO].si= ze, + 2, s->memmap[VIRT_PCIE_MMIO].base, 2, mmio32_size, 1, FDT_PCI_RANGE_MMIO_64BIT, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); @@ -1130,6 +1147,132 @@ static void cxl_host_state_init(RISCVVirtState *s) cxl_fmws_update_mmio(); } =20 +/* + * Assign PCI bus numbers to the bridges under @bus in depth-first order, + * the way firmware does during enumeration. QEMU leaves the secondary and + * subordinate bus registers at 0 until firmware programs them, so without + * this build_crs() would see an empty bus range for the CXL host bridge. + * @bus itself is numbered @bus_num. Returns the highest bus number used. + */ +static int virt_cxl_assign_bus_numbers(PCIBus *bus, int bus_num) +{ + int max_bus =3D bus_num; + int next_bus =3D bus_num + 1; + int devfn; + + for (devfn =3D 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { + PCIDevice *dev =3D bus->devices[devfn]; + PCIBus *sec_bus; + int subordinate; + + if (!dev) { + continue; + } + if ((dev->config[PCI_HEADER_TYPE] & + ~PCI_HEADER_TYPE_MULTI_FUNCTION) !=3D PCI_HEADER_TYPE_BRIDGE)= { + continue; + } + + sec_bus =3D pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); + subordinate =3D virt_cxl_assign_bus_numbers(sec_bus, next_bus); + + pci_set_byte(dev->config + PCI_PRIMARY_BUS, bus_num); + pci_set_byte(dev->config + PCI_SECONDARY_BUS, next_bus); + pci_set_byte(dev->config + PCI_SUBORDINATE_BUS, subordinate); + + if (subordinate > max_bus) { + max_bus =3D subordinate; + } + next_bus =3D subordinate + 1; + } + + return max_bus; +} + +/* + * Simulate the PCI resource initialization that firmware (UEFI) would + * normally perform for the CXL host bridge. + * + * EDK2's PciBusDxe only recurses into devices that look like PCI-to-PCI + * bridges, while the pxb-cxl expander bridge presents as a class 0x0600 + * host bridge with a standard (type 0) header, so the firmware neither + * enumerates behind it nor assigns it a memory window or bus numbers. As= a + * result the generic build_crs() path would produce an empty _CRS for the + * CXL host bridge (ACPI0016). + * + * Program each CXL root port the way firmware would: + * - assign the reserved 32-bit MMIO range (see create_fdt_pcie()) to its + * memory window, so build_crs() emits that range in the host bridge _C= RS + * and excludes it from PCI0's _CRS; + * - set the primary/secondary/subordinate bus numbers, so build_crs() + * emits a correct bus-range resource. Without a bus range Linux only + * claims the single host-bridge bus and cannot enumerate the devices + * behind the root port. + * + * TODO: this handles a single pxb-cxl with a single root port, which is + * the supported topology for now. With multiple CXL host bridges or root + * ports the reserved window would need to be partitioned per bridge. + */ +static void virt_cxl_init_bridge_windows(RISCVVirtState *s) +{ + hwaddr cxl_mmio_base, cxl_mmio_limit; + PCIBus *bus; + + if (!s->cxl_devices_state.is_enabled) { + return; + } + + cxl_mmio_base =3D s->memmap[VIRT_PCIE_MMIO].base + + s->memmap[VIRT_PCIE_MMIO].size - VIRT_CXL_MMIO32_SIZE; + cxl_mmio_limit =3D cxl_mmio_base + VIRT_CXL_MMIO32_SIZE - 1; + + QLIST_FOREACH(bus, &s->pci_bus->child, sibling) { + int devfn; + + if (!pci_bus_is_root(bus) || !pci_bus_is_cxl(bus)) { + continue; + } + + /* Assign bus numbers for the whole CXL subtree (firmware would). = */ + virt_cxl_assign_bus_numbers(bus, pci_bus_num(bus)); + + /* Assign the reserved MMIO window to the root-port bridge. */ + for (devfn =3D 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { + PCIDevice *dev =3D bus->devices[devfn]; + PCIBridge *br; + + if (!dev) { + continue; + } + if ((dev->config[PCI_HEADER_TYPE] & + ~PCI_HEADER_TYPE_MULTI_FUNCTION) !=3D PCI_HEADER_TYPE_BRI= DGE) { + continue; + } + + br =3D PCI_BRIDGE(dev); + + pci_set_word(dev->config + PCI_MEMORY_BASE, + (cxl_mmio_base >> 16) & PCI_MEMORY_RANGE_MASK); + pci_set_word(dev->config + PCI_MEMORY_LIMIT, + (cxl_mmio_limit >> 16) & PCI_MEMORY_RANGE_MASK); + pci_word_test_and_set_mask(dev->config + PCI_COMMAND, + PCI_COMMAND_MEMORY); + pci_bridge_update_mappings(br); + break; + } + } +} + +/* + * A PCI reset clears the bridge window and bus-number registers programmed + * above, so re-apply them after every reset, the way firmware would during + * its PCI enumeration. + */ +static void virt_cxl_reset_bridge_windows(void *opaque) +{ + virt_cxl_init_bridge_windows(RISCV_VIRT_MACHINE(opaque)); +} + static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) { FWCfgState *fw_cfg; @@ -1238,6 +1381,15 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) if (s->cxl_devices_state.is_enabled) { cxl_fmws_link_targets(&error_fatal); } + + /* + * Assign the CXL bridge memory window (simulating firmware) so the + * ACPI _CRS built for the CXL host bridge is populated. Do it here f= or + * the initial build, and register a reset handler so the window is + * re-applied after any PCI reset (which clears the bridge registers). + */ + virt_cxl_init_bridge_windows(s); + qemu_register_reset(virt_cxl_reset_bridge_windows, s); hwaddr firmware_end_addr; vaddr kernel_start_addr; const char *firmware_name =3D riscv_default_firmware_name(&s->soc[0]); --=20 2.50.1 From nobody Fri Aug 21 21:26:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1787300497; cv=none; d=zohomail.com; s=zohoarc; b=Ep9wc5zwlBvG6iosd9tVwKYZ8AsjUdPIiTcHdYNAqQ3n8aNyPUPfsXD602EA4cUU4H8omPE3G/JxHNMIDi0rxYwvuV3KBWnzS8v6XPvoo5dImMU95Car8HDj7H0sdOg8ABtkILIsKsIGyDldKtsL2Vp/XtfWm81meHjhU/GoCac= ARC-Message-Signature: i=1; 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BC=-1|-1; BR=01201311R151e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037009110; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=19; SR=0; TI=SMTPD_---0X9LmLuX_1787300405; From: Chen Pei To: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com, imammedo@redhat.com, sunilvl@ventanamicro.com, jic23@kernel.org Cc: pbonzini@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, anisinha@redhat.com, dave.jiang@intel.com, alison.schofield@intel.com, junjie.cao@intel.com, guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH 4/4] tests/qtest: Add RISC-V ACPI bios tables test for CXL Date: Fri, 21 Aug 2026 16:19:54 +0800 Message-ID: <20260821081954.1171-5-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821081954.1171-1-cp0613@linux.alibaba.com> References: <20260821081954.1171-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.97 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Add test_acpi_riscv64_virt_tcg_cxl() to verify that enabling CXL on the RISC-V virt machine produces correct ACPI tables, including the ACPI0017 CXLM device with _DEP in the DSDT and the CEDT table. The test boots with cxl=3Don, one pxb-cxl bus (bus_nr=3D12), a CXL root port, a cxl-type3 persistent memory device, and a fixed memory window, mirroring the existing x86 q35 CXL test pattern. Since pxb-cxl is a root bus, using -cdrom causes QEMU to auto-plug the cdrom drive into pxb-cxl, triggering "Only PCI/PCIe bridges can be plugged into pxb-cxl". The ISO is instead attached explicitly via a virtio-scsi-pci controller on pcie.0, following the same approach as test_acpi_aarch64_virt_tcg_pxb(). Acked-by: Alistair Francis Signed-off-by: Chen Pei --- tests/data/acpi/riscv64/virt/CEDT.cxl | Bin 0 -> 108 bytes tests/data/acpi/riscv64/virt/DSDT.cxl | Bin 0 -> 6212 bytes tests/qtest/bios-tables-test.c | 54 ++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) create mode 100644 tests/data/acpi/riscv64/virt/CEDT.cxl create mode 100644 tests/data/acpi/riscv64/virt/DSDT.cxl diff --git a/tests/data/acpi/riscv64/virt/CEDT.cxl b/tests/data/acpi/riscv6= 4/virt/CEDT.cxl new file mode 100644 index 0000000000000000000000000000000000000000..81d746dfb09ccb147e26bb64060= 404ca3191d097 GIT binary patch literal 108 zc-nJzbqUE~U|?VjaPoKd2v%^42yj*a0!E-1hz+6{7!(+IKx!BefCEf2LP-snumA^? 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Attach the ISO explicitly to a scsi control= ler + * on pcie.0 instead, following the same pattern as + * test_acpi_aarch64_virt_tcg_pxb(). + */ + params =3D g_strdup_printf("-cpu rva22s64" + " -machine cxl=3Don" + " -device pcie-root-port,chassis=3D1,id=3Dpci= .1,bus=3Dpcie.0" + " -device virtio-scsi-pci,id=3Dscsi0,bus=3Dpc= i.1" + " -drive file=3Dtests/data/uefi-boot-images/" + "bios-tables-test.riscv64.iso.qcow2," + "if=3Dnone,media=3Dcdrom,id=3Ddrive-scsi0-0-0= -1,readonly=3Don" + " -device scsi-cd,bus=3Dscsi0.0,scsi-id=3D0," + "drive=3Ddrive-scsi0-0-0-1,id=3Dscsi0-0-0-1,b= ootindex=3D1" + " -object memory-backend-file,id=3Dcxl-mem1,m= em-path=3D%s,size=3D256M" + " -object memory-backend-file,id=3Dlsa1,mem-p= ath=3D%s,size=3D256M" + " -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id= =3Dcxl.1" + " -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Drp= 1,chassis=3D0,slot=3D2" + " -device cxl-type3,bus=3Drp1,persistent-memd= ev=3Dcxl-mem1,lsa=3Dlsa1" + " -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.si= ze=3D4G," + "cxl-fmw.0.interleave-granularity=3D8k", + tmp_path, tmp_path); + test_acpi_one(params, &data); + + g_free(params); + g_assert(g_rmdir(tmp_path) =3D=3D 0); + g_free(tmp_path); + free_test_data(&data); +} +#endif /* CONFIG_POSIX */ + static void test_acpi_aarch64_virt_tcg(void) { test_data data =3D { @@ -2963,6 +3013,10 @@ int main(int argc, char *argv[]) test_acpi_riscv64_virt_tcg_numamem); qtest_add_func("acpi/virt/acpispcr", test_acpi_riscv64_virt_tcg_acpi_spcr); +#ifdef CONFIG_POSIX + qtest_add_func("acpi/virt/cxl", + test_acpi_riscv64_virt_tcg_cxl); +#endif } } else if (strcmp(arch, "loongarch64") =3D=3D 0) { if (has_tcg && qtest_has_machine("virt")) { --=20 2.50.1