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Thu, 20 Aug 2026 13:14:07 -0700 (PDT) X-Received: by 2002:ac8:6f14:0:b0:51c:b98a:2448 with SMTP id d75a77b69052e-52df56f9741mr10809231cf.9.1787256847450; Thu, 20 Aug 2026 13:14:07 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Peter Maydell , Paolo Bonzini , qemu-s390x@nongnu.org, Richard Henderson , qemu-ppc@nongnu.org, Pierrick Bouvier , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 01/15] target/tricore: Document architectural interrupts as not implemented Date: Thu, 20 Aug 2026 22:13:41 +0200 Message-ID: <20260820201356.29775-2-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260820201356.29775-1-philmd@oss.qualcomm.com> References: <20260820201356.29775-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwODIwMDE1MiBTYWx0ZWRfXxZgCCKj6NQcJ 2F7ELzW9ThdbjFr+Vec11BEBlHvDtDUITZEK5bskJm69ZYzuRIiiPDgm2ItF3kjseGGS6wnbhKD fXc7V3UH3NKOuLUJA+ay8M5PNQE+LWA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIwMDE1MiBTYWx0ZWRfX5tj0PSXSs3Tj 9QDTeBmr2AKJ6WkCb1MVZTZqT/RofAS3g0c8Ih4n2Y6bkCHpeW/7mpo/0kJgolCzILngOTgxl4k qlGxnAkelpe16+ZcVsR6+2tvzNo48YlG3QVuVIGrXuqITStDyf3HwwqhLo3jGsoPiQ8/r/kOSII 8emHdmhuce5B2TMMcS/eF634m6AeOILj+n0IIBI5i//EQSNZ5yYmsPE5t9kWhroWCUMPE0N/ADL ffFn+bNOBWi7haYYKNmL9pylXK/EbNQoAFiJOZNP/3Y1dP6pVQu7Whaimma8/zKQmSTEKzkqsln K2q/MSKAOsPHgWIubpsYSz2eLqJaG8BbP5CtGu1x0CLtgJbsPtM1bKwIzpyZEez+pm3qWJ5bZR6 ANg+ROt1B5hFcwy98yZjo7POVdyFbKxis5ZAyTuQQDG9cjKBSSuyGO80isSxwyjU/45ASeav4N7 QzBAeKLdlnHC7xKudyw== X-Authority-Analysis: v=2.4 cv=Y7/IdBeN c=1 sm=1 tr=0 ts=6a876010 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=Cu_OB6cER5A0ZMY7a4UA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: 8cDI_3LG-IBrjTyOHRFGHe_NUbJQlz09 X-Proofpoint-ORIG-GUID: 8cDI_3LG-IBrjTyOHRFGHe_NUbJQlz09 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-20_02,2026-08-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1015 phishscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608200152 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787257019520158500 As mentioned in commit de680286b52 ("accel/tcg: Make cpu_exec_interrupt hook mandatory"): > Tricore doesn't currently implement the architectural > interrupt handling. Add a comment to help understanding why this SysemuCPUOps has_work() handler is simply always returning %true. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/tricore/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 6d448727005..82b56c3cd56 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -113,6 +113,7 @@ static void tricore_cpu_reset_hold(Object *obj, ResetTy= pe type) =20 static bool tricore_cpu_has_work(CPUState *cs) { + /* Interrupts are not implemented */ return true; } =20 --=20 2.53.0 From nobody Fri Aug 21 21:26:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787256957; cv=none; d=zohomail.com; s=zohoarc; b=mQDtuQOTSKy/iL0oIz1E4+HViCnZkWK/1Ex7dp+112G+zqo5I3r2h9A/aQ1455LBiNqVop6bR0AhXrFdJwIcTV0emv0v2xqxXT2o8nUvK2ZHg2Y8JqVD8tbYJddrzCs/mzqWRwfEByP7CfEmYG0RxvfLbSgDbqwKimIfEc8czRI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787256957; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=b2hfNH6s7Qj+rSFk3xgTZrDK7N6/yTIPz+i0gRL62t4=; b=WxvigZoCEQ6PD7WC7ZmGPQ4FGFUvXWIixSb+FBZlRkiuneflxkQrxA1T+SSHxsi9RCvWtdQZJnG4sUIzPXV2rhvuCc2EyGVgX6hkDXfVbfd03kEOg3b97wWU6ffpA2qd01nfS7ti+kWXoZs5xo+ZbPUr1gJlfPWm/EpMr167FKY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787256957626291.8853068898467; Thu, 20 Aug 2026 13:15:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx99a-0005QE-S0; Thu, 20 Aug 2026 16:14:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx99Z-0005P1-EP for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:14:21 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx99V-00020N-Vo for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:14:21 -0400 Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67KK7tLg159042 for ; Thu, 20 Aug 2026 20:14:16 GMT Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5xuk2y9h-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 20:14:16 +0000 (GMT) Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-51bfe3fa93bso2384611cf.2 for ; Thu, 20 Aug 2026 13:14:16 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787256959858158500 Mark the CPUState structure const when it is only accessed read-only. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 4 ++-- include/system/cpus.h | 4 ++-- system/cpus.c | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 81af7b9ee1a..a16acf14370 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -893,7 +893,7 @@ void qemu_cpu_kick(CPUState *cpu); * Returns: %true if run state is not running or if artificially stopped; * %false otherwise. */ -bool cpu_is_stopped(CPUState *cpu); +bool cpu_is_stopped(const CPUState *cpu); =20 /** * do_run_on_cpu: @@ -1000,7 +1000,7 @@ void cpu_interrupt(CPUState *cpu, int mask); * * Checks if any of interrupts in @mask are pending on @cpu. */ -static inline bool cpu_test_interrupt(CPUState *cpu, int mask) +static inline bool cpu_test_interrupt(const CPUState *cpu, int mask) { return qatomic_load_acquire(&cpu->interrupt_request) & mask; } diff --git a/include/system/cpus.h b/include/system/cpus.h index 508444ccf1c..bf36b823769 100644 --- a/include/system/cpus.h +++ b/include/system/cpus.h @@ -13,10 +13,10 @@ const AccelOpsClass *cpus_get_accel(void); #define VCPU_THREAD_NAME_SIZE 16 =20 void cpus_kick_thread(CPUState *cpu); -bool cpu_work_list_empty(CPUState *cpu); +bool cpu_work_list_empty(const CPUState *cpu); bool cpu_thread_is_idle(CPUState *cpu); bool all_cpu_threads_idle(void); -bool cpu_can_run(CPUState *cpu); +bool cpu_can_run(const CPUState *cpu); void qemu_process_cpu_events_common(CPUState *cpu); void cpu_thread_signal_created(CPUState *cpu); void cpu_thread_signal_destroyed(CPUState *cpu); diff --git a/system/cpus.c b/system/cpus.c index f37e215c586..e11a5aab6a6 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -69,12 +69,12 @@ static QemuMutex bql; */ static const AccelOpsClass *cpus_accel; =20 -bool cpu_is_stopped(CPUState *cpu) +bool cpu_is_stopped(const CPUState *cpu) { return cpu->stopped || !runstate_is_running(); } =20 -bool cpu_work_list_empty(CPUState *cpu) +bool cpu_work_list_empty(const CPUState *cpu) { return QSIMPLEQ_EMPTY_ATOMIC(&cpu->work_list); } @@ -271,7 +271,7 @@ void cpu_interrupt(CPUState *cpu, int mask) cpus_accel->handle_interrupt(cpu, mask); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787256987401158500 Add the const qualifier to CPUAVRState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/avr/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index a818db753b2..1e4e839bd83 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -183,7 +183,7 @@ int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *= buf, int reg); int avr_print_insn(bfd_vma addr, disassemble_info *info); vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr); =20 -static inline int avr_feature(CPUAVRState *env, AVRFeature feature) +static inline int avr_feature(const CPUAVRState *env, AVRFeature feature) { return (env->features & (1U << feature)) !=3D 0; } @@ -204,12 +204,12 @@ enum { TB_FLAGS_SKIP =3D 2, }; =20 -static inline int cpu_interrupts_enabled(CPUAVRState *env) +static inline int cpu_interrupts_enabled(const CPUAVRState *env) { return env->sregI !=3D 0; } =20 -static inline uint8_t cpu_get_sreg(CPUAVRState *env) +static inline uint8_t cpu_get_sreg(const CPUAVRState *env) { return (env->sregC) << 0 | (env->sregZ) << 1 --=20 2.53.0 From nobody Fri Aug 21 21:26:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787256960; cv=none; d=zohomail.com; s=zohoarc; b=ApvpNM6qf1ojxWrVS4vKFozQm4mF5k7i7SMANR7NXLY8qNzqmDr4LiKSMAVhJknSlmWrETxUNr50LrDCg/udKGfZZeuUe82NqVQjNU7Uj5h+ka88ZhJLq5XJLHE4+9tvzKeW3emReVOaGda+xsROBkZwXm1cLEnJPqayC/NSljA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787256960; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=uHmqw3PgQrwhWNplvoktCYvtMz6v2lpYN+dpIY29gRk=; b=HAyDMk9bTnS7U3H5ERX6gWmThfnhJFEpLS3lHA0w09nLlfGujk59JCSy4L7upQgJR9Jwec/aqjpwON1cg9jx8KlalwMrPdtbx+LvUbJQuQYHXsBToGG+F6DaKSM9bRq4gqrCisucO159k482YPl1FB0nkyDPIYsCHzRJR7jvj7g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787256960985123.43134893645743; Thu, 20 Aug 2026 13:16:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx99z-0005fT-PH; Thu, 20 Aug 2026 16:14:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx99y-0005dY-19 for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:14:46 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx99w-00028J-4C for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:14:45 -0400 Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67KK8ace160944 for ; Thu, 20 Aug 2026 20:14:33 GMT Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5xuk2ya8-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 20:14:33 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-5276aa86d00so2407511cf.2 for ; Thu, 20 Aug 2026 13:14:32 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Brian Cain --- target/hexagon/cpu.h | 2 +- target/hexagon/cpu.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index c50fbb3f72a..e4f120eda17 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -216,7 +216,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonS= tate *env, * @return true if the @a thread_env hardware thread is * not stopped. */ -bool hexagon_thread_is_enabled(CPUHexagonState *thread_env); +bool hexagon_thread_is_enabled(const CPUHexagonState *thread_env); uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg); void hexagon_cpu_soft_reset(CPUHexagonState *env); #endif diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 9765716b516..4cc6bd67c28 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -345,9 +345,9 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *c= s, } =20 #ifndef CONFIG_USER_ONLY -bool hexagon_thread_is_enabled(CPUHexagonState *env) +bool hexagon_thread_is_enabled(const CPUHexagonState *env) { - HexagonCPU *cpu =3D env_archcpu(env); + const HexagonCPU *cpu =3D env_archcpu(env); uint32_t modectl; uint32_t thread_enabled_mask; bool E_bit; --=20 2.53.0 From nobody Fri Aug 21 21:26:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787257023; cv=none; d=zohomail.com; s=zohoarc; b=KH06QxCl1daBlHY8MLpnbZ3/eOTSHGecPKZFx5wJuNWhexRpvzj7urAxM0N4qGIG0I2dnKZcIl2TD+Jcfq9l0xBsOsQX37nwtTASxDh/oRGKLQWjkGmbHgSYCTEBzQFm7hYnTCOq+2xQDUw6CObjdsPHpZExaPpwY2c7MTkZwWA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787257023; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QNEBEIJmMwDoBD78bITdTVQWtGt4MTDyYliaVB+vU0I=; b=Hw5FCXelLpv9FM12zeKpLh8Il5fnkk96J+ljZFQWgTaszIsuhXANtEI48STC5UVps3Scfrb/X7Qx7dFUDNb7lCu9xMthCpVbGlTAq3T3ZDTjNuxxzTfP+xFkxyl6P9we+QVSnmSJdM8/B0AQgc5FMxnUaPF91N/do7qLJ89ZAys= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787257023510240.33232762141984; Thu, 20 Aug 2026 13:17:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx9A7-0005jm-HQ; Thu, 20 Aug 2026 16:14:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx9A5-0005iO-Li for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:14:53 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx9A3-0002Bx-A4 for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:14:53 -0400 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67KK87Xw067150 for ; Thu, 20 Aug 2026 20:14:40 GMT Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5yg0js2j-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 20:14:40 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-51c1a9764f0so2230911cf.1 for ; Thu, 20 Aug 2026 13:14:40 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787257025667158500 x86_cpu_pending_interrupt() and x86_cpu_interrupts_enabled() only read CPU state without modification, add the const qualifiers to CPUState and CPUX86State parameters. Simplify directly using cpu_env() in x86_cpu_pending_interrupt. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/i386/cpu.h | 4 ++-- target/i386/cpu.c | 5 ++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e6a197602d8..72adf075bfd 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2584,7 +2584,7 @@ void x86_cpu_gdb_init(CPUState *cs); int cpu_x86_support_mca_broadcast(CPUX86State *env); =20 #ifndef CONFIG_USER_ONLY -int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); +int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request); =20 bool x86_cpu_translate_for_debug(CPUState *cpu, vaddr addr, TranslateForDebugResult *result); @@ -3092,7 +3092,7 @@ static inline bool ctl_has_irq(CPUX86State *env) return (env->int_ctl & V_IRQ_MASK) && (int_prio >=3D tpr); } =20 -static inline bool x86_cpu_interrupts_enabled(CPUX86State *env) +static inline bool x86_cpu_interrupts_enabled(const CPUX86State *env) { return ((env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) || diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e5ffb10d156..1fc02cf94e6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10601,10 +10601,9 @@ static vaddr x86_cpu_get_pc(CPUState *cs) } =20 #if !defined(CONFIG_USER_ONLY) -int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) +int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + const CPUX86State *env =3D cpu_env(cs); =20 if (interrupt_request & CPU_INTERRUPT_POLL) { return CPU_INTERRUPT_POLL; --=20 2.53.0 From nobody Fri Aug 21 21:26:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787256958; cv=none; d=zohomail.com; s=zohoarc; b=i2CDmjfrO7rnhiiNzfJEH9Esm5mqxDVDZQCZmfCsoh7ypSTPgseXwH6rONy+4hdAYf9iahlpseeNp+UCdVvkmx7FqyAv1pGLBU5OCP3gd61RpWvi07rkFPdmj9XzOw0BksUSHnPNeJ+K1M0Q4yXlWZCKa4bTc7APKhdQR+13ha8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787256958; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=omys+sjzsI02iJIWLB5L11LGUGEpkxHVCWBpSv/GVBA=; b=f43+mZ95kgnLbCntFoUScHoHMbQEGPXh3tAJKK7/gFNnlJWFPGq71d+9a7ZqerC2qPeM++U+G9KCxVDeSSVgaSTN+K6nfGbgg6XRwhn9L3+MVJn7xRmqK+gy233XCsicgmyMJp31mHGO2h+nVKt8gLR2UMkMcoLpF9f0XK+CYEM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17872569583204.036843117793865; Thu, 20 Aug 2026 13:15:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx9AD-0005lM-Ct; Thu, 20 Aug 2026 16:15:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx9AB-0005kw-Of for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:14:59 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx9AA-0002JZ-69 for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:14:59 -0400 Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67KK7Y353491355 for ; Thu, 20 Aug 2026 20:14:57 GMT Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5ytcaqfw-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 20:14:56 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-52ce3c7cb2eso3616271cf.3 for ; Thu, 20 Aug 2026 13:14:56 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/loongarch/cpu.h | 6 +++--- target/loongarch/internals.h | 2 +- target/loongarch/cpu.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index ad30c73167e..494744788b8 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -485,7 +485,7 @@ struct LoongArchCPUClass { #define MMU_USER_IDX MMU_PLV_USER #define MMU_DA_IDX 4 =20 -static inline CPUSysState *env_sys(CPULoongArchState *env) +static inline CPUSysState *env_sys(const CPULoongArchState *env) { return env->sys_state; } @@ -495,12 +495,12 @@ static inline void set_sys_state(CPULoongArchState *e= nv, CPUSysState *sys) env->sys_state =3D sys; } =20 -static inline bool is_la64(CPULoongArchState *env) +static inline bool is_la64(const CPULoongArchState *env) { return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) =3D=3D CPUCFG1_ARCH_L= A64; } =20 -static inline bool is_va32(CPULoongArchState *env) +static inline bool is_va32(const CPULoongArchState *env) { /* VA32 if !LA64 or VA32L[1-3] */ bool va32 =3D !is_la64(env); diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index 50f0fe2e9be..d6f31161e85 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -38,7 +38,7 @@ uint64_t cpu_loongarch_get_constant_timer_counter(LoongAr= chCPU *cpu); uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu); void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu, uint64_t value); -bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env); +bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env); #endif /* !CONFIG_USER_ONLY */ =20 uint64_t read_fcc(CPULoongArchState *env); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 2e938d7880f..b638ac25040 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -82,7 +82,7 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int lev= el) } =20 /* Check if there is pending and not masked out interrupt */ -bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) +bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env) { uint32_t pending; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/mips/cpu.h | 6 +++--- target/mips/internal.h | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 319147a948c..6404b342a5d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1372,19 +1372,19 @@ static inline bool ase_3d_available(const CPUMIPSSt= ate *env) } =20 /* Check presence of MSA implementation */ -static inline bool ase_msa_available(CPUMIPSState *env) +static inline bool ase_msa_available(const CPUMIPSState *env) { return env->CP0_Config3 & (1 << CP0C3_MSAP); } =20 /* Check presence of Loongson CSR instructions */ -static inline bool ase_lcsr_available(CPUMIPSState *env) +static inline bool ase_lcsr_available(const CPUMIPSState *env) { return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP); } =20 /* Check presence of multi-threading ASE implementation */ -static inline bool ase_mt_available(CPUMIPSState *env) +static inline bool ase_mt_available(const CPUMIPSState *env) { return env->CP0_Config3 & (1 << CP0C3_MT); } diff --git a/target/mips/internal.h b/target/mips/internal.h index c5c286872eb..7dba22300b1 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -165,7 +165,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val); =20 extern const VMStateDescription vmstate_mips_cpu; =20 -static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) +static inline bool cpu_mips_hw_interrupts_enabled(const CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && !(env->CP0_Status & (1 << CP0St_EXL)) && @@ -180,7 +180,7 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMI= PSState *env) } =20 /* Check if there is pending and not masked out interrupt */ -static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) +static inline bool cpu_mips_hw_interrupts_pending(const CPUMIPSState *env) { int32_t pending; int32_t status; @@ -247,9 +247,9 @@ static inline void restore_pamask(CPUMIPSState *env) } } =20 -static inline int mips_vpe_active(CPUMIPSState *env) +static inline int mips_vpe_active(const CPUMIPSState *env) { - MIPSCPU *cpu =3D env_archcpu(env); + const MIPSCPU *cpu =3D env_archcpu(env); int active =3D 1; =20 /* Check that the VPE is enabled. */ @@ -281,7 +281,7 @@ static inline int mips_vpe_active(CPUMIPSState *env) return active; } =20 -static inline int mips_vp_active(CPUMIPSState *env) +static inline int mips_vp_active(const CPUMIPSState *env) { CPUState *cs; =20 --=20 2.53.0 From nobody Fri Aug 21 21:26:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787256999; cv=none; d=zohomail.com; s=zohoarc; b=gCTyXpJAjXGZIIbhMbYgk5Bc3Rgk+e3pcoUgeoT0k5tCHHTegILZJ+N+OjuttY5jZpcOy6kzw1lk1z4GK+WMtc+45UX02cZTaInsP8AZfEaDRO+QT48/KQxGhlyX5NMz11/B52Fl9trySCJsJcDTo+3rgdPajBr2P3nsi+U817A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787257001438158500 Add the const qualifier to S390CPU when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Ilya Leoshkevich Reviewed-by: Marc-Andr=C3=A9 Lureau Acked-by: Eric Farman --- target/s390x/cpu.h | 2 +- target/s390x/s390x-internal.h | 12 ++++++------ target/s390x/interrupt.c | 22 +++++++++++----------- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index f55b79ef8ac..998bbb0d7ff 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -854,7 +854,7 @@ static inline unsigned int s390_cpu_set_state(uint8_t c= pu_state, S390CPU *cpu) return 0; } #endif /* CONFIG_USER_ONLY */ -static inline uint8_t s390_cpu_get_state(S390CPU *cpu) +static inline uint8_t s390_cpu_get_state(const S390CPU *cpu) { return cpu->env.cpu_state; } diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 50782fac3ce..ca4445e6474 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -333,12 +333,12 @@ void cpu_inject_clock_comparator(S390CPU *cpu); void cpu_inject_cpu_timer(S390CPU *cpu); void cpu_inject_emergency_signal(S390CPU *cpu, uint16_t src_cpu_addr); int cpu_inject_external_call(S390CPU *cpu, uint16_t src_cpu_addr); -bool s390_cpu_has_io_int(S390CPU *cpu); -bool s390_cpu_has_ext_int(S390CPU *cpu); -bool s390_cpu_has_mcck_int(S390CPU *cpu); -bool s390_cpu_has_int(S390CPU *cpu); -bool s390_cpu_has_restart_int(S390CPU *cpu); -bool s390_cpu_has_stop_int(S390CPU *cpu); +bool s390_cpu_has_io_int(const S390CPU *cpu); +bool s390_cpu_has_ext_int(const S390CPU *cpu); +bool s390_cpu_has_mcck_int(const S390CPU *cpu); +bool s390_cpu_has_int(const S390CPU *cpu); +bool s390_cpu_has_restart_int(const S390CPU *cpu); +bool s390_cpu_has_stop_int(const S390CPU *cpu); void cpu_inject_restart(S390CPU *cpu); void cpu_inject_stop(S390CPU *cpu); #endif /* CONFIG_USER_ONLY */ diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c index 1dca835c5d8..d7e3fd45e4b 100644 --- a/target/s390x/interrupt.c +++ b/target/s390x/interrupt.c @@ -139,10 +139,10 @@ void s390_crw_mchk(void) fsc->inject_crw_mchk(fs); } =20 -bool s390_cpu_has_mcck_int(S390CPU *cpu) +bool s390_cpu_has_mcck_int(const S390CPU *cpu) { QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 if (!(env->psw.mask & PSW_MASK_MCHECK)) { return false; @@ -157,10 +157,10 @@ bool s390_cpu_has_mcck_int(S390CPU *cpu) return false; } =20 -bool s390_cpu_has_ext_int(S390CPU *cpu) +bool s390_cpu_has_ext_int(const S390CPU *cpu) { QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 if (!(env->psw.mask & PSW_MASK_EXT)) { return false; @@ -199,10 +199,10 @@ bool s390_cpu_has_ext_int(S390CPU *cpu) return false; } =20 -bool s390_cpu_has_io_int(S390CPU *cpu) +bool s390_cpu_has_io_int(const S390CPU *cpu) { QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 if (!(env->psw.mask & PSW_MASK_IO)) { return false; @@ -211,21 +211,21 @@ bool s390_cpu_has_io_int(S390CPU *cpu) return qemu_s390_flic_has_io(flic, env->cregs[6]); } =20 -bool s390_cpu_has_restart_int(S390CPU *cpu) +bool s390_cpu_has_restart_int(const S390CPU *cpu) { - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 return env->pending_int & INTERRUPT_RESTART; } =20 -bool s390_cpu_has_stop_int(S390CPU *cpu) +bool s390_cpu_has_stop_int(const S390CPU *cpu) { - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 return env->pending_int & INTERRUPT_STOP; } =20 -bool s390_cpu_has_int(S390CPU *cpu) +bool s390_cpu_has_int(const S390CPU *cpu) { if (!tcg_enabled()) { return false; --=20 2.53.0 From nobody Fri Aug 21 21:26:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 376cff656fa..bb4c8563554 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -642,7 +642,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env); int riscv_cpu_vsirq_pending(CPURISCVState *env); int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_prio, - uint64_t pending, uint8_t *iprio); + uint64_t pending, const uint8_t *iprio); =20 =20 bool riscv_cpu_fp_enabled(CPURISCVState *env); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7bf098319f8..858fbf865fd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -866,7 +866,7 @@ uint8_t riscv_cpu_default_priority(int irq) =20 int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_prio, - uint64_t pending, uint8_t *iprio) + uint64_t pending, const uint8_t *iprio) { int irq, best_irq =3D RISCV_EXCP_NONE; unsigned int prio, best_prio =3D UINT_MAX; --=20 2.53.0 From nobody Fri Aug 21 21:26:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787257059; cv=none; d=zohomail.com; s=zohoarc; b=jEx2dwDsGdBUlUPblP0Jr97J/gqKh0gwU2JN68Jw9AscWzG9UHndOhGonGIZN+GbMwJrmP5z/L5fZKu10l9VuidXACm2bFb4XUVso5lOWwPQNyz3gkv2zRynt9TzMz2nov10VdRPFIJhtrOiYUDuMXE4XKUwGB2v7sfvU63inx4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787257059; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LWQwdDV2fkgFjhmKLwyo93xfsCf8ZqnI4jIB05mjxx8=; b=OF3xtDXGbBc/9B9oXQ9Px9qzA7aElyGHFEO/Jf8u+aOHowMw72xdxzxmxmWaLw/3BPxMakZcTxQ4Ru3gcYq3E1WqLhSYPqeeqcTEOc14qZzSDHN7b70rBgDWT+KGPTPkXc1XMNxYAy8kAKR3tJf/7sOvmPq3qYvHhdLgXPQNgGM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787257058877907.7502446044895; Thu, 20 Aug 2026 13:17:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx9An-0006zx-3d; Thu, 20 Aug 2026 16:15:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx9Al-0006vn-BG for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:15:35 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx9Ah-0002hk-OE for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:15:35 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67KK7q0l3941379 for ; Thu, 20 Aug 2026 20:15:20 GMT Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5vh7ujmr-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 20:15:20 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-52cd0374265so3862891cf.1 for ; Thu, 20 Aug 2026 13:15:19 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787257059749158500 Add the const qualifier to CPURISCVState when the argument is accessed without modification. Simplify directly using cpu_env() in riscv_cpu_has_work(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/riscv/cpu.h | 27 ++++++++++++++------------- target/riscv/cpu.c | 13 ++++++------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bb4c8563554..c51e0d5f919 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -636,11 +636,11 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteA= rray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); uint8_t riscv_cpu_default_priority(int irq); -uint64_t riscv_cpu_all_pending(CPURISCVState *env); -int riscv_cpu_mirq_pending(CPURISCVState *env); -int riscv_cpu_sirq_pending(CPURISCVState *env); -int riscv_cpu_vsirq_pending(CPURISCVState *env); -int riscv_cpu_pending_to_irq(CPURISCVState *env, +uint64_t riscv_cpu_all_pending(const CPURISCVState *env); +int riscv_cpu_mirq_pending(const CPURISCVState *env); +int riscv_cpu_sirq_pending(const CPURISCVState *env); +int riscv_cpu_vsirq_pending(const CPURISCVState *env); +int riscv_cpu_pending_to_irq(const CPURISCVState *env, int extirq, unsigned int extirq_def_prio, uint64_t pending, const uint8_t *iprio); =20 @@ -746,20 +746,20 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) +static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env) { return env->misa_mxl; } #endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) =20 -static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) +static inline const RISCVCPUConfig *riscv_cpu_cfg(const CPURISCVState *env) { return &env_archcpu(env)->cfg; } =20 #if !defined(CONFIG_USER_ONLY) -static inline privilege_mode_t cpu_address_mode(CPURISCVState *env) +static inline privilege_mode_t cpu_address_mode(const CPURISCVState *env) { privilege_mode_t mode =3D env->priv; =20 @@ -769,7 +769,8 @@ static inline privilege_mode_t cpu_address_mode(CPURISC= VState *env) return mode; } =20 -static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mod= e) +static inline RISCVMXL cpu_get_xl(const CPURISCVState *env, + privilege_mode_t mode) { RISCVMXL xl =3D env->misa_mxl; /* @@ -797,7 +798,7 @@ static inline RISCVMXL cpu_get_xl(CPURISCVState *env, p= rivilege_mode_t mode) #if defined(TARGET_RISCV32) #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) +static inline RISCVMXL cpu_recompute_xl(const CPURISCVState *env) { #if !defined(CONFIG_USER_ONLY) return cpu_get_xl(env, env->priv); @@ -810,7 +811,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *= env) #if defined(TARGET_RISCV32) #define cpu_address_xl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL cpu_address_xl(CPURISCVState *env) +static inline RISCVMXL cpu_address_xl(const CPURISCVState *env) { #ifdef CONFIG_USER_ONLY return env->xl; @@ -822,7 +823,7 @@ static inline RISCVMXL cpu_address_xl(CPURISCVState *en= v) } #endif =20 -static inline uint16_t riscv_cpu_xlen(CPURISCVState *env) +static inline uint16_t riscv_cpu_xlen(const CPURISCVState *env) { return 16 << env->xl; } @@ -830,7 +831,7 @@ static inline uint16_t riscv_cpu_xlen(CPURISCVState *en= v) #ifdef TARGET_RISCV32 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) +static inline RISCVMXL riscv_cpu_sxl(const CPURISCVState *env) { #ifdef CONFIG_USER_ONLY return env->misa_mxl; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 858fbf865fd..4abf20d057a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -864,7 +864,7 @@ uint8_t riscv_cpu_default_priority(int irq) return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; }; =20 -int riscv_cpu_pending_to_irq(CPURISCVState *env, +int riscv_cpu_pending_to_irq(const CPURISCVState *env, int extirq, unsigned int extirq_def_prio, uint64_t pending, const uint8_t *iprio) { @@ -908,7 +908,7 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env, * using hvip bits 13:63 from HS-mode. Those are returned in * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending(). */ -uint64_t riscv_cpu_all_pending(CPURISCVState *env) +uint64_t riscv_cpu_all_pending(const CPURISCVState *env) { uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; @@ -917,7 +917,7 @@ uint64_t riscv_cpu_all_pending(CPURISCVState *env) return (env->mip | vsgein | vstip) & env->mie; } =20 -int riscv_cpu_mirq_pending(CPURISCVState *env) +int riscv_cpu_mirq_pending(const CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & ~env->mideleg & ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); @@ -926,7 +926,7 @@ int riscv_cpu_mirq_pending(CPURISCVState *env) irqs, env->miprio); } =20 -int riscv_cpu_sirq_pending(CPURISCVState *env) +int riscv_cpu_sirq_pending(const CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & ~env->hi= deleg; uint64_t irqs_f =3D env->mvip & env->mvien & ~env->mideleg & env->sie; @@ -935,7 +935,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env) irqs | irqs_f, env->siprio); } =20 -int riscv_cpu_vsirq_pending(CPURISCVState *env) +int riscv_cpu_vsirq_pending(const CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & env->hid= eleg; uint64_t irqs_f_vs =3D env->hvip & env->hvien & ~env->hideleg & env->v= sie; @@ -952,8 +952,7 @@ int riscv_cpu_vsirq_pending(CPURISCVState *env) =20 static bool riscv_cpu_has_work(CPUState *cs) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; + CPURISCVState *env =3D cpu_env(cs); /* * Definition of the WFI instruction requires it to ignore the privile= ge * mode and delegation registers, but respect individual enables --=20 2.53.0 From nobody Fri Aug 21 21:26:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787257031; cv=none; d=zohomail.com; s=zohoarc; b=eMuHe6og6fQVnNB2yq9Fsdn+AONTEWvnZrhpmvfC/nVXIP/p4hk48qBePgliH/VfcJe63z21bFN/p6CW7LijXByDJ+X1C99sBlhrwvLf4nn2iJiMjNWeysA1ts2IQPXbyke7hDvzPMzX9Pw07sAu3SBfpB0kHCiU0L/pgW6g3g4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787257031; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GkfJ0DUVwjpw7Jql39GIYw8AYSod2OF3xVsMsf7lww4=; b=hvxuvba3/moWddHfJA7naVKDj/pyXIZbC9tRQtWFAqr1Q2j3Xx46112EKyrdeP2aeCOqsDlcQYfnBFsw/rKPmCA3gkIYqtlvsNrK22S1sdDbsOAwkasHM+4btRnig7+HU8LlxItEfgx0cCvDqY/l0AFKKc/0tM+e622PjoJPEFE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787257031586250.89666050245114; Thu, 20 Aug 2026 13:17:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx9Ay-0007JM-2M; Thu, 20 Aug 2026 16:15:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx9Aq-00075c-61 for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:15:40 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx9Ao-0002jn-H9 for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:15:39 -0400 Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67KK7Y393491355 for ; Thu, 20 Aug 2026 20:15:27 GMT Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5ytcaqjm-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 20:15:27 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-51c1d137a68so3979771cf.3 for ; Thu, 20 Aug 2026 13:15:26 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787257033593158500 Add the const qualifier to CPUSPARCState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/sparc/cpu.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 5f583ed9de2..31a16c2af03 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -680,28 +680,28 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, = target_ulong addr, #endif =20 #if defined (TARGET_SPARC64) -static inline int cpu_has_hypervisor(CPUSPARCState *env1) +static inline int cpu_has_hypervisor(const CPUSPARCState *env1) { return env1->def.features & CPU_FEATURE_HYPV; } =20 -static inline int cpu_hypervisor_mode(CPUSPARCState *env1) +static inline int cpu_hypervisor_mode(const CPUSPARCState *env1) { return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); } =20 -static inline int cpu_supervisor_mode(CPUSPARCState *env1) +static inline int cpu_supervisor_mode(const CPUSPARCState *env1) { return env1->pstate & PS_PRIV; } #else -static inline int cpu_supervisor_mode(CPUSPARCState *env1) +static inline int cpu_supervisor_mode(const CPUSPARCState *env1) { return env1->psrs; } #endif =20 -static inline int cpu_interrupts_enabled(CPUSPARCState *env1) +static inline int cpu_interrupts_enabled(const CPUSPARCState *env1) { #if !defined (TARGET_SPARC64) if (env1->psret !=3D 0) @@ -715,7 +715,7 @@ static inline int cpu_interrupts_enabled(CPUSPARCState = *env1) return 0; } =20 -static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) +static inline int cpu_pil_allowed(const CPUSPARCState *env1, int pil) { #if !defined(TARGET_SPARC64) /* level 15 is non-maskable on sparc v8 */ --=20 2.53.0 From nobody Fri Aug 21 21:26:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787257013; cv=none; d=zohomail.com; s=zohoarc; b=k0ulZrEyubMKf+QtAyWsZwnYs9iqTTlnYm7bKvaJGzSIzaqa9/nnsTNN8g+NifRPumWBYT0LuELrZTGo1pxKW6VCWvJoVopWHZn9gAULWLI137aM5vh5uIGal04d75lC73H7vtwO/7AkMOZUf1ObAuspfisQm8y9fyDAL7612oI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787257013; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jGYx+C/wjSqKEH0TVOmY80sKiqo+hAS2MJzZs3J9eSY=; b=WhPbOSq7kCeo1Kl2/Vm4fO4uWi0BOzuFXob/ospGLIuishkcsgtlaQvAA15FoCLDLBw1L9Ws9+A8JLxAevywMWGXp4+uWCeY88lY375GsyNxkytgQdYc7YuHe2Yo1s3LB2N1PZaWXc4qjqg7ecYUKRx7qYRsce5+i+YA11WlTuI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787257013546485.125955889303; Thu, 20 Aug 2026 13:16:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx9BB-0007vz-7p; Thu, 20 Aug 2026 16:16:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx9Ay-0007MU-PZ for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:15:49 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx9Aw-0002ob-9n for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:15:48 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67KK7xui3941497 for ; Thu, 20 Aug 2026 20:15:35 GMT Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5vh7ujnu-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 20:15:34 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-52d7b3adda4so2316321cf.3 for ; Thu, 20 Aug 2026 13:15:34 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Thu, 20 Aug 2026 13:15:33 -0700 (PDT) X-Received: by 2002:a05:622a:e18d:10b0:52d:f700:6dea with SMTP id d75a77b69052e-52df7007ae6mr3007631cf.42.1787256933199; Thu, 20 Aug 2026 13:15:33 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Peter Maydell , Paolo Bonzini , qemu-s390x@nongnu.org, Richard Henderson , qemu-ppc@nongnu.org, Pierrick Bouvier , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Helge Deller Subject: [PATCH v2 12/15] linux-user: Uncast void pointer argument as Object in target_cpu_free() Date: Thu, 20 Aug 2026 22:13:52 +0200 Message-ID: <20260820201356.29775-13-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260820201356.29775-1-philmd@oss.qualcomm.com> References: <20260820201356.29775-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIwMDE1MiBTYWx0ZWRfX8+xolnvHLwIK 1yhWVHG1ktLQqFyzSIKukJtTcsZhgiPwxSh+dPg/ZW//qhGnRNE3sNS/wluj4WrJhL9acQgWq7Y 2WomFE0M1mzm6r/nR+lJNQHiK/twveFsa2Nc3d8ga09urW8QKSXxHU/PC0HvrSGx0c/fZIQ7Cvn JjFgMV0bjJ2GpI6etuNLk4MoTVEPosrUVVrNoJBg+2fmbFaprxG9R2GosVzUMyO5ZIoMCxL/FbN CRtHMo+SssD4ArsxBATgTrECMJCdZm+EXSM1kiet28Q3fA7hBLBR0hd2nbyTWVOEKPJLS2BqJK7 Xq4Yz7+NZDpLA+nnJ8bdg2l1bL8vFgt/AXvV1n56iZsHqbRm7zLeVc3F8BcW71BI6693RK1BGvH rQ49kQ0r3bxMEbdcdzu7FkIiEafu/mSlej4JyuAds4j+gZlfP3SR3L2cSPu7upEzyH7zSXx8vUY bhWWiNseGZ6Mgfo7x2Q== X-Proofpoint-ORIG-GUID: 0SwMg49Yt18LcHB915jFPifQU1p0Lx6U X-Authority-Analysis: v=2.4 cv=Y7fIdBeN c=1 sm=1 tr=0 ts=6a876066 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=2RGiIWwp3e7TAFkeQGYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODIwMDE1MiBTYWx0ZWRfX7MQ0bYCG3AP3 +88U0lb0Etf4vI/hWSVhSDwv9FMa56k+BzP6cVjdyHqnuXMHMAkIp/2uoZlxDY0S8giXHf3FUoB VAP15t9Px8v0fI2Auc+uBjTAwCf5Hxg= X-Proofpoint-GUID: 0SwMg49Yt18LcHB915jFPifQU1p0Lx6U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-20_02,2026-08-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 clxscore=1015 malwarescore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608200152 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787257015972158500 init_main_thread() is registered as Object::free() hook, thus take an Object* argument. Uncast the void pointer as such. While now cpu_env() accept any pointer type, next commit will restrict it to CPUState* type. QOM-cast the Object to CPU type, otherwise we will get: ../linux-user/i386/cpu_loop.c: In function =E2=80=98target_cpu_free=E2=80= =99: include/hw/core/cpu.h:604:31: error: =E2=80=98_Generic=E2=80=99 selector = of type =E2=80=98void=E2=80=99 is not compatible with any association ../linux-user/x86_64/../i386/cpu_loop.c:331:19: note: in expansion of macro= =E2=80=98cpu_env=E2=80=99 331 | target_munmap(cpu_env(obj)->gdt.base, | ^~~~~~~ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- linux-user/i386/cpu_loop.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index fe922fceb5a..a0790f3f352 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -326,9 +326,10 @@ void cpu_loop(CPUX86State *env) } } =20 -static void target_cpu_free(void *obj) +static void target_cpu_free(void *ptr) { - target_munmap(cpu_env(obj)->gdt.base, + Object *obj =3D ptr; + target_munmap(cpu_env(CPU(obj))->gdt.base, sizeof(uint64_t) * TARGET_GDT_ENTRIES); g_free(obj); } --=20 2.53.0 From nobody Fri Aug 21 21:26:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787256975; cv=none; d=zohomail.com; s=zohoarc; b=WX01nYmBWBWPdoPCZ2E4Mt+wPtIT8vs+q/YIusL5/kXS3NuIXhizUvWKe4Bq09T37/2GP1wG8HopvqR03f5eO1dfBeGBgPGTrWYLJoXnUmSv/LOoGbNWTEFgZo60FrN9FcifqBz/3LXYWpQ770tNU3PfGP2SCTLE70W38KioiNM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787256975; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Ab2jd4IOBsCwRWOGKRY93YvfazH7yBpjbYnktuG5p9Q=; b=bZNCNlAweFiOoGzMdTR1tPeiiDpE+QZHIIW2RSy4X8WbJb0E7KoElmQVNqEgPcZ5heaI94fwW6IO2KhKFWRtCyk8tGnGscWY3alUNtvtNTFOgEmxXjdAxV62Fw1u8RQviaT2cXpZVI2z3DSwUtKCIylhXuGAoFh6ku2ihU9oSz8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787256975477101.56115847961541; Thu, 20 Aug 2026 13:16:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx9BC-00086U-BY; Thu, 20 Aug 2026 16:16:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx9B8-0007jY-QG for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:16:00 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx9B6-0002su-Lf for qemu-devel@nongnu.org; Thu, 20 Aug 2026 16:15:58 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67KK7xhC4013159 for ; Thu, 20 Aug 2026 20:15:43 GMT Received: from mail-qv1-f71.google.com (mail-qv1-f71.google.com [209.85.219.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5x29k5p6-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 20:15:43 +0000 (GMT) Received: by mail-qv1-f71.google.com with SMTP id 6a1803df08f44-907ca5abf1bso2595496d6.0 for ; Thu, 20 Aug 2026 13:15:43 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787256977595158500 From: Philippe Mathieu-Daud=C3=A9 Use _Generic() controlling-expression to add the const-qualified variants of cpu_env(), env_cpu() and env_archcpu(). This allows to safely access CPU architecture state when it should not be modified. Alias env_cpu_const() which is still used. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- include/exec/cpu-common.h | 30 +++++++++++------------------- include/hw/core/cpu.h | 17 ++++++++++++----- 2 files changed, 23 insertions(+), 24 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 6594f7fa1be..bffef677607 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -85,21 +85,11 @@ static inline bool cpu_loop_exit_requested(const CPUSta= te *cpu) * * Return the ArchCPU associated with the environment. */ -static inline ArchCPU *env_archcpu(CPUArchState *env) -{ - return (void *)env - sizeof(CPUState); -} - -/** - * env_cpu_const(env) - * @env: The architecture environment - * - * Return the CPUState associated with the environment. - */ -static inline const CPUState *env_cpu_const(const CPUArchState *env) -{ - return (void *)env - sizeof(CPUState); -} +#define env_archcpu(env) _Generic(*(env), \ + CPUArchState: \ + (ArchCPU *)((void *)env - sizeof(CPUState)), \ + const CPUArchState: \ + (const ArchCPU *)((const void *)env - sizeof(CPUState))) =20 /** * env_cpu(env) @@ -107,9 +97,11 @@ static inline const CPUState *env_cpu_const(const CPUAr= chState *env) * * Return the CPUState associated with the environment. */ -static inline CPUState *env_cpu(CPUArchState *env) -{ - return (CPUState *)env_cpu_const(env); -} +#define env_cpu(env) _Generic(*(env), \ + CPUArchState: \ + (CPUState *)((void *)env - sizeof(CPUState)), \ + const CPUArchState: \ + (const CPUState *)((const void *)env - sizeof(CPUState))) +#define env_cpu_const(cpu) env_cpu(cpu) =20 #endif /* CPU_COMMON_H */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index a16acf14370..372485a2e54 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -594,11 +594,18 @@ struct CPUState { QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=3D sizeof(CPUState) - sizeof(CPUNegativeOffsetState)); =20 -static inline CPUArchState *cpu_env(CPUState *cpu) -{ - /* We validate that CPUArchState follows CPUState in cpu-target.c */ - return (CPUArchState *)(cpu + 1); -} +/** + * cpu_env(cpu) + * @cpu: The vCPU + * + * Return the CPUArchState associated with the CPU. + */ +#define cpu_env(cpu) _Generic(*(cpu), \ + /* We validate that CPUArchState follows CPUState in cpu-target.c = */ \ + CPUState: \ + (CPUArchState *)(cpu + 1), \ + const CPUState: \ + (const CPUArchState *)(cpu + 1)) =20 #ifdef CONFIG_TCG /* --=20 2.53.0 From nobody Fri Aug 21 21:26:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787256998; cv=none; d=zohomail.com; s=zohoarc; b=kNCbaaFxOtApdZ1HvOqAsAnKd6ars8AOO0TEh6kJB/Kl1B6gZpseMR+A4Bkce3CywRBEl8fXMDdTP97xzDpCf9fuDnjXpw0i4IEQ4E9wCjOj0GGgY+7V4aiPyyeHdA7LbzVpCOjWfPZIjObuKE9BBZfy2SWa8dydNbw+/yjVDfI= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787257001442158500 Use the generic env_cpu() macro introduced in the previous commit and remove the few env_cpu_const() uses. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/exec/cpu-common.h | 1 - linux-user/elfload.c | 2 +- linux-user/i386/elfload.c | 2 +- linux-user/x86_64/elfload.c | 2 +- 4 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index bffef677607..d67d008236f 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -102,6 +102,5 @@ static inline bool cpu_loop_exit_requested(const CPUSta= te *cpu) (CPUState *)((void *)env - sizeof(CPUState)), \ const CPUArchState: \ (const CPUState *)((const void *)env - sizeof(CPUState))) -#define env_cpu_const(cpu) env_cpu(cpu) =20 #endif /* CPU_COMMON_H */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 88508deac50..c4bdaa146a7 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2128,7 +2128,7 @@ static int wmr_write_region(void *opaque, vaddr start, #endif static int elf_core_dump(int signr, const CPUArchState *env) { - const CPUState *cpu =3D env_cpu_const(env); + const CPUState *cpu =3D env_cpu(env); const TaskState *ts =3D (const TaskState *)get_task_state((CPUState *)= cpu); struct rlimit dumpsize; CountAndSizeRegions css; diff --git a/linux-user/i386/elfload.c b/linux-user/i386/elfload.c index 26b12001a3e..2e10f38a412 100644 --- a/linux-user/i386/elfload.c +++ b/linux-user/i386/elfload.c @@ -38,7 +38,7 @@ void elf_core_copy_regs(target_elf_gregset_t *r, const CP= UX86State *env) r->pt.es =3D tswapal(env->segs[R_ES].selector & 0xffff); r->pt.fs =3D tswapal(env->segs[R_FS].selector & 0xffff); r->pt.gs =3D tswapal(env->segs[R_GS].selector & 0xffff); - r->pt.orig_ax =3D tswapal(get_task_state(env_cpu_const(env))->orig_ax); + r->pt.orig_ax =3D tswapal(get_task_state(env_cpu(env))->orig_ax); r->pt.ip =3D tswapal(env->eip); r->pt.cs =3D tswapal(env->segs[R_CS].selector & 0xffff); r->pt.flags =3D tswapal(env->eflags); diff --git a/linux-user/x86_64/elfload.c b/linux-user/x86_64/elfload.c index 49a6f6180e0..121a8167acc 100644 --- a/linux-user/x86_64/elfload.c +++ b/linux-user/x86_64/elfload.c @@ -59,7 +59,7 @@ void elf_core_copy_regs(target_elf_gregset_t *r, const CP= UX86State *env) r->pt.dx =3D tswapal(env->regs[R_EDX]); r->pt.si =3D tswapal(env->regs[R_ESI]); r->pt.di =3D tswapal(env->regs[R_EDI]); - r->pt.orig_ax =3D tswapal(get_task_state(env_cpu_const(env))->orig_ax); + r->pt.orig_ax =3D tswapal(get_task_state(env_cpu(env))->orig_ax); r->pt.ip =3D tswapal(env->eip); r->pt.cs =3D tswapal(env->segs[R_CS].selector & 0xffff); r->pt.flags =3D tswapal(env->eflags); --=20 2.53.0 From nobody Fri Aug 21 21:26:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787257023; cv=none; d=zohomail.com; s=zohoarc; b=XmX4rRWA0MnaKY+NIAp/uSGkRR01Oba4hTg461Q9hdkGvppRbI4ldIpaASr2Eh8jot37xuIORmU8vQn6mLSopX9cHNM1jI3p7Eff5mHc9ZUu6V5bQckVB++0nVMEDcrb0mEJG99sKitFvczVCNQUg7qbVLCr8cn3an8rxp7r0YU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 15/15] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Date: Thu, 20 Aug 2026 22:13:55 +0200 Message-ID: <20260820201356.29775-16-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260820201356.29775-1-philmd@oss.qualcomm.com> References: <20260820201356.29775-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: gNjbzxsqixJNTUKCjOX1awEcm8yj0YGC X-Authority-Analysis: v=2.4 cv=V8BNF+ni c=1 sm=1 tr=0 ts=6a876081 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=hf0YJCTCBZPsvBMCq-cA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIwMDE1MiBTYWx0ZWRfX+sa9wGH+2fuY vYWjl2u3yzasphPf04h+7QMEkMeV2hTRM/SpYg36D7BFALl8DZlWD62qys7y/QNQFqulwXdODD3 UfL6H1/HHqDV7J+Rdc7Bp9o9+edFnVJRY3HXz8jIpV5rC2DS90tu4/0XeXxzSSrYJni3C9uh/Ga T1mbpUptiXdUhl5AGf9+9VaedBtwmlDRmXac9tlcA72KYPPxUH2cEj6E4RJFccq/x51YciWxV9j qV1oBDp4jyEK/2Y8ENQ7TS/6U0MaOzKFVSEf+IisXuiOHfA7E7ed8JgGYmvNdBF0YOiN6gFdczE Z6IZZ8BYG9mhvhFcMnwmrnLao8QMPEjUOMlv7qoJ9VOM5oDeJwygd+4nFr+fykEtg2lpSvOj7vV OAzQmJlwSanVk51zJYC0fe2H0KTLYYKUY/xG9arC6IrOirHgjQw5JmPmRLQhzl6orQi18tkCwRS BQbVS5j4DCyVM727dKQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwODIwMDE1MiBTYWx0ZWRfX4YPT46MMTU7l O80iciQIPtBO1lZSgQlPpbO19gFMr7h33ex3tIBSESXlJEm7Onu2l+aK1YAa24AKz+SAdqr7Gen TqvZfahGoqRs9McoqjHYse3q+ibNH1s= X-Proofpoint-GUID: gNjbzxsqixJNTUKCjOX1awEcm8yj0YGC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-20_02,2026-08-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 clxscore=1015 bulkscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608200152 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787257026173158500 All functions called by target has_work() handler take a const @cpu argument. We can now fulfill the comment added in commit c2804566f6 ("target/arm: do not clear halting reason in has_work helper"), qualifying the handler const to denote its idempotency. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/sysemu-cpu-ops.h | 4 ++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 4 ++-- target/avr/cpu.c | 3 ++- target/hexagon/cpu.c | 4 ++-- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 4 ++-- target/or1k/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu-system.c | 4 ++-- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 4 ++-- 20 files changed, 27 insertions(+), 26 deletions(-) diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 9a45596169a..095bdcd997a 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -19,10 +19,10 @@ typedef struct SysemuCPUOps { /** * @has_work: Callback for checking if there is work to do. * - * This function should be idempotent (i.e. not change state) as + * This function is idempotent (i.e. not change state) as * it will likely be queried multiple times before a CPU resumes. */ - bool (*has_work)(CPUState *cpu); /* MANDATORY NON-NULL */ + bool (*has_work)(const CPUState *cpu); /* MANDATORY NON-NULL */ /** * @get_memory_mapping: Callback for obtaining the memory mappings. */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 7d1d036e1d3..21d4f8ac23b 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -77,7 +77,7 @@ static void alpha_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool alpha_cpu_has_work(CPUState *cs) +static bool alpha_cpu_has_work(const CPUState *cs) { /* Here we are checking to see if the CPU should wake up from HALT. We will have gotten into this state only for WTINT from PALmode. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9761bb173c1..ba66359d410 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -141,9 +141,9 @@ int arm_cpu_mmu_index(CPUState *cs, bool ifetch) * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here * unconditionally. */ -static bool arm_cpu_has_work(CPUState *cs) +static bool arm_cpu_has_work(const CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); + const ARMCPU *cpu =3D ARM_CPU(cs); =20 /* * Only another PSCI call can wake the CPU up in which case the diff --git a/target/avr/cpu.c b/target/avr/cpu.c index a01e6fa4751..a96bef46ff1 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -23,6 +23,7 @@ #include "qemu/qemu-print.h" #include "exec/translation-block.h" #include "system/address-spaces.h" +#include "hw/core/cpu.h" #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" @@ -43,7 +44,7 @@ static vaddr avr_cpu_get_pc(CPUState *cs) return cpu->env.pc_w * 2; } =20 -static bool avr_cpu_has_work(CPUState *cs) +static bool avr_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET) && cpu_interrupts_enabled(cpu_env(cs)); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 4cc6bd67c28..868aef0cde4 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -364,9 +364,9 @@ bool hexagon_thread_is_enabled(const CPUHexagonState *e= nv) return E_bit; } =20 -static bool hexagon_cpu_has_work(CPUState *cs) +static bool hexagon_cpu_has_work(const CPUState *cs) { - CPUHexagonState *env =3D cpu_env(cs); + const CPUHexagonState *env =3D cpu_env(cs); =20 return hexagon_thread_is_enabled(env) && (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 7b1309a7c38..dbf58466c24 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -134,7 +134,7 @@ static void hppa_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool hppa_cpu_has_work(CPUState *cs) +static bool hppa_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1fc02cf94e6..0606ac16664 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10638,7 +10638,7 @@ int x86_cpu_pending_interrupt(const CPUState *cs, i= nt interrupt_request) return 0; } =20 -static bool x86_cpu_has_work(CPUState *cs) +static bool x86_cpu_has_work(const CPUState *cs) { return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; } diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index b638ac25040..0ce18a89b63 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -96,7 +96,7 @@ bool cpu_loongarch_hw_interrupts_pending(const CPULoongAr= chState *env) #endif =20 #ifndef CONFIG_USER_ONLY -static bool loongarch_cpu_has_work(CPUState *cs) +static bool loongarch_cpu_has_work(const CPUState *cs) { bool has_work =3D false; =20 diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 523694d8fbf..da3681fab1f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -76,7 +76,7 @@ static void m68k_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool m68k_cpu_has_work(CPUState *cs) +static bool m68k_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6013a8def8e..d1d2f0ec7e3 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -127,7 +127,7 @@ static void mb_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool mb_cpu_has_work(CPUState *cs) +static bool mb_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c069aa1c0b7..0f39f8fe0a5 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -134,9 +134,9 @@ static vaddr mips_cpu_get_pc(CPUState *cs) } =20 #if !defined(CONFIG_USER_ONLY) -static bool mips_cpu_has_work(CPUState *cs) +static bool mips_cpu_has_work(const CPUState *cs) { - CPUMIPSState *env =3D cpu_env(cs); + const CPUMIPSState *env =3D cpu_env(cs); bool has_work =3D false; =20 /* diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c index 42d9351b6d7..10b13ae69cd 100644 --- a/target/or1k/cpu.c +++ b/target/or1k/cpu.c @@ -76,7 +76,7 @@ static void openrisc_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool openrisc_cpu_has_work(CPUState *cs) +static bool openrisc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER= ); } diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 85a91ff4bb6..fd63cd6ab09 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7224,7 +7224,7 @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetc= h) #endif /* CONFIG_TCG */ =20 #ifndef CONFIG_USER_ONLY -static bool ppc_cpu_has_work(CPUState *cs) +static bool ppc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4abf20d057a..3560fbd445e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -950,7 +950,7 @@ int riscv_cpu_vsirq_pending(const CPURISCVState *env) (irqs | irqs_f_vs), env->hviprio); } =20 -static bool riscv_cpu_has_work(CPUState *cs) +static bool riscv_cpu_has_work(const CPUState *cs) { CPURISCVState *env =3D cpu_env(cs); /* diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 69946928995..dfa09a85bce 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -73,7 +73,7 @@ static void rx_restore_state_to_opc(CPUState *cs, cpu->env.pc =3D data[0]; } =20 -static bool rx_cpu_has_work(CPUState *cs) +static bool rx_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c index 84faceb3338..3a0ff46e144 100644 --- a/target/s390x/cpu-system.c +++ b/target/s390x/cpu-system.c @@ -39,9 +39,9 @@ #include "system/tcg.h" #include "hw/core/sysemu-cpu-ops.h" =20 -static bool s390_cpu_has_work(CPUState *cs) +static bool s390_cpu_has_work(const CPUState *cs) { - S390CPU *cpu =3D S390_CPU(cs); + const S390CPU *cpu =3D S390_CPU(cs); =20 /* STOPPED cpus can never wake up */ if (s390_cpu_get_state(cpu) !=3D S390_CPU_STATE_LOAD && diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 55c73a1da35..b0ed356d0f7 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -107,7 +107,7 @@ static bool superh_io_recompile_replay_branch(CPUState = *cs, return false; } =20 -static bool superh_cpu_has_work(CPUState *cs) +static bool superh_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 2baa5036871..8dd9b0d5ee3 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -783,7 +783,7 @@ static void sparc_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool sparc_cpu_has_work(CPUState *cs) +static bool sparc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && cpu_interrupts_enabled(cpu_env(cs)); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 82b56c3cd56..357f3737053 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -111,7 +111,7 @@ static void tricore_cpu_reset_hold(Object *obj, ResetTy= pe type) cpu_state_reset(cpu_env(cs)); } =20 -static bool tricore_cpu_has_work(CPUState *cs) +static bool tricore_cpu_has_work(const CPUState *cs) { /* Interrupts are not implemented */ return true; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 99c8bd4b5fb..1b299568776 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -140,9 +140,9 @@ static void xtensa_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool xtensa_cpu_has_work(CPUState *cs) +static bool xtensa_cpu_has_work(const CPUState *cs) { - CPUXtensaState *env =3D cpu_env(cs); + const CPUXtensaState *env =3D cpu_env(cs); =20 return !env->runstall && env->pending_irq_level; } --=20 2.53.0