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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787222909421158500 Add the const qualifier to CPUAVRState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/avr/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index a818db753b2..1e4e839bd83 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -183,7 +183,7 @@ int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *= buf, int reg); int avr_print_insn(bfd_vma addr, disassemble_info *info); vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr); =20 -static inline int avr_feature(CPUAVRState *env, AVRFeature feature) +static inline int avr_feature(const CPUAVRState *env, AVRFeature feature) { return (env->features & (1U << feature)) !=3D 0; } @@ -204,12 +204,12 @@ enum { TB_FLAGS_SKIP =3D 2, }; =20 -static inline int cpu_interrupts_enabled(CPUAVRState *env) +static inline int cpu_interrupts_enabled(const CPUAVRState *env) { return env->sregI !=3D 0; } =20 -static inline uint8_t cpu_get_sreg(CPUAVRState *env) +static inline uint8_t cpu_get_sreg(const CPUAVRState *env) { return (env->sregC) << 0 | (env->sregZ) << 1 --=20 2.53.0 From nobody Fri Aug 21 21:26:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787223066; cv=none; d=zohomail.com; s=zohoarc; b=e40heZ5BFxVwygbl27JInsnHInPaIrZoDhK0FGh9DxTZmO9PvkxSAmaNU07qjec6+I2x2DELcXtAoGrzLhHqj0u4NNcgoJ1BRnWhIyiEOJkdNlkWd92u8DK3fIOXEunck6u43pg+LM8rwFY8ll0dCTCvNpC/El9JUiG6alEgQKg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787223066; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WVunpjLVA0I0Wfv3sDB+jNp2S9PTkMt6jmB8Jx0E2VM=; b=h3VO33A7reOTb/8ahwhuM7KKyTn+TQKmwDOkDkOhuBqWWhlU83R2T2N2mc5oFj7ngx3e3f1w7vFqCyrdQmVma1uztXggEmmmEfJ5zn3P2sPQNePmAmICKYr7Wt3ZAedLU9T9trCZ/6WDs1gybvAIbtI2uWFNJ7U64CUFbcZvkp4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787223066751450.91035028873193; Thu, 20 Aug 2026 03:51:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx0JT-0008HY-Uo; Thu, 20 Aug 2026 06:47:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0JM-0008DT-Cn for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:47:54 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0JK-0005ib-BH for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:47:51 -0400 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67KA2i172932659 for ; Thu, 20 Aug 2026 10:47:49 GMT Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5yg0g5vq-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 10:47:48 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-934979ee9f1so262969785a.2 for ; Thu, 20 Aug 2026 03:47:48 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787223068108158500 x86_cpu_pending_interrupt() and x86_cpu_interrupts_enabled() only read CPU state without modification, add the const qualifiers to CPUState and CPUX86State parameters. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/i386/cpu.h | 4 ++-- target/i386/cpu.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e6a197602d8..72adf075bfd 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2584,7 +2584,7 @@ void x86_cpu_gdb_init(CPUState *cs); int cpu_x86_support_mca_broadcast(CPUX86State *env); =20 #ifndef CONFIG_USER_ONLY -int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); +int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request); =20 bool x86_cpu_translate_for_debug(CPUState *cpu, vaddr addr, TranslateForDebugResult *result); @@ -3092,7 +3092,7 @@ static inline bool ctl_has_irq(CPUX86State *env) return (env->int_ctl & V_IRQ_MASK) && (int_prio >=3D tpr); } =20 -static inline bool x86_cpu_interrupts_enabled(CPUX86State *env) +static inline bool x86_cpu_interrupts_enabled(const CPUX86State *env) { return ((env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) || diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e5ffb10d156..8777bcbae85 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10601,10 +10601,10 @@ static vaddr x86_cpu_get_pc(CPUState *cs) } =20 #if !defined(CONFIG_USER_ONLY) -int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) +int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + const X86CPU *cpu =3D X86_CPU(cs); + const CPUX86State *env =3D &cpu->env; =20 if (interrupt_request & CPU_INTERRUPT_POLL) { return CPU_INTERRUPT_POLL; --=20 2.53.0 From nobody Fri Aug 21 21:26:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787222898; cv=none; d=zohomail.com; s=zohoarc; b=ab2s6mp5uF74SDqVV1+r/WtUM4dcO7mISLvUBU/8u6v97tGurM7AWino/E8jRZxO6xMNF1bhlemtVjI5NgzY8NXgl+QwRN47xuj+mbSZECV21IYRHqe6apibXOsXEcPN1RrhW34NCLWbnewOn49VJ0XbC8/eCWBgfSpWuqcPh6A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787222898; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vPkYOzjCZEx4JelHAd8fdNs4FoNuCoY284i0qko/5Zs=; b=O8NOTCyWEBOhKLU0PwY3DY7X1Py4MD7rhFeJUTWu2Ju0IRjupBPHSUyDyNNOp1+53I78TiwgoaZUbV9ouOTMvDxEWjA4Be1pCn0FOGbhnBqkWVAew1V3Zhv0+LtS3tLi86z/u6LIu0kJvIL5a/MKXMMJt8sp5sIZpRUkkPzZ9AA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787222898530626.8662414722332; Thu, 20 Aug 2026 03:48:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx0JZ-0008ME-C7; Thu, 20 Aug 2026 06:48:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0JS-0008Hf-80 for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:47:59 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0JQ-0005kI-Le for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:47:57 -0400 Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67K8jfMQ2529525 for ; Thu, 20 Aug 2026 10:47:55 GMT Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5xbv8fhm-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 10:47:55 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-52dd69b00cfso20188751cf.3 for ; Thu, 20 Aug 2026 03:47:55 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787222899594158500 Add the const qualifier to CPULoongArchStatCPUMIPSStatee when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/loongarch/cpu.h | 6 +++--- target/loongarch/internals.h | 2 +- target/loongarch/cpu.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index ad30c73167e..494744788b8 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -485,7 +485,7 @@ struct LoongArchCPUClass { #define MMU_USER_IDX MMU_PLV_USER #define MMU_DA_IDX 4 =20 -static inline CPUSysState *env_sys(CPULoongArchState *env) +static inline CPUSysState *env_sys(const CPULoongArchState *env) { return env->sys_state; } @@ -495,12 +495,12 @@ static inline void set_sys_state(CPULoongArchState *e= nv, CPUSysState *sys) env->sys_state =3D sys; } =20 -static inline bool is_la64(CPULoongArchState *env) +static inline bool is_la64(const CPULoongArchState *env) { return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) =3D=3D CPUCFG1_ARCH_L= A64; } =20 -static inline bool is_va32(CPULoongArchState *env) +static inline bool is_va32(const CPULoongArchState *env) { /* VA32 if !LA64 or VA32L[1-3] */ bool va32 =3D !is_la64(env); diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index e01dbed40f6..6a733e6c3a5 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -39,7 +39,7 @@ uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArch= CPU *cpu); void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu, uint64_t value); bool loongarch_cpu_has_work(CPUState *cs); -bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env); +bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env); #endif /* !CONFIG_USER_ONLY */ =20 uint64_t read_fcc(CPULoongArchState *env); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 8cd5bc18a3c..82ec35e081f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -82,7 +82,7 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int lev= el) } =20 /* Check if there is pending and not masked out interrupt */ -bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) +bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env) { uint32_t pending; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787222931875158500 Add the const qualifier to CPUMIPSState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/mips/cpu.h | 6 +++--- target/mips/internal.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 319147a948c..6404b342a5d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1372,19 +1372,19 @@ static inline bool ase_3d_available(const CPUMIPSSt= ate *env) } =20 /* Check presence of MSA implementation */ -static inline bool ase_msa_available(CPUMIPSState *env) +static inline bool ase_msa_available(const CPUMIPSState *env) { return env->CP0_Config3 & (1 << CP0C3_MSAP); } =20 /* Check presence of Loongson CSR instructions */ -static inline bool ase_lcsr_available(CPUMIPSState *env) +static inline bool ase_lcsr_available(const CPUMIPSState *env) { return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP); } =20 /* Check presence of multi-threading ASE implementation */ -static inline bool ase_mt_available(CPUMIPSState *env) +static inline bool ase_mt_available(const CPUMIPSState *env) { return env->CP0_Config3 & (1 << CP0C3_MT); } diff --git a/target/mips/internal.h b/target/mips/internal.h index c5c286872eb..66e8c599b43 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -165,7 +165,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val); =20 extern const VMStateDescription vmstate_mips_cpu; =20 -static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) +static inline bool cpu_mips_hw_interrupts_enabled(const CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && !(env->CP0_Status & (1 << CP0St_EXL)) && @@ -180,7 +180,7 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMI= PSState *env) } =20 /* Check if there is pending and not masked out interrupt */ -static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) +static inline bool cpu_mips_hw_interrupts_pending(const CPUMIPSState *env) { int32_t pending; int32_t status; @@ -281,7 +281,7 @@ static inline int mips_vpe_active(CPUMIPSState *env) return active; } =20 -static inline int mips_vp_active(CPUMIPSState *env) +static inline int mips_vp_active(const CPUMIPSState *env) { CPUState *cs; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787222981654158500 Add the const qualifier to S390CPU when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Eric Farman Reviewed-by: Ilya Leoshkevich Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/s390x/cpu.h | 2 +- target/s390x/s390x-internal.h | 12 ++++++------ target/s390x/interrupt.c | 22 +++++++++++----------- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index f55b79ef8ac..998bbb0d7ff 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -854,7 +854,7 @@ static inline unsigned int s390_cpu_set_state(uint8_t c= pu_state, S390CPU *cpu) return 0; } #endif /* CONFIG_USER_ONLY */ -static inline uint8_t s390_cpu_get_state(S390CPU *cpu) +static inline uint8_t s390_cpu_get_state(const S390CPU *cpu) { return cpu->env.cpu_state; } diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 35d1e34ef4d..54b62808d83 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -334,12 +334,12 @@ void cpu_inject_clock_comparator(S390CPU *cpu); void cpu_inject_cpu_timer(S390CPU *cpu); void cpu_inject_emergency_signal(S390CPU *cpu, uint16_t src_cpu_addr); int cpu_inject_external_call(S390CPU *cpu, uint16_t src_cpu_addr); -bool s390_cpu_has_io_int(S390CPU *cpu); -bool s390_cpu_has_ext_int(S390CPU *cpu); -bool s390_cpu_has_mcck_int(S390CPU *cpu); -bool s390_cpu_has_int(S390CPU *cpu); -bool s390_cpu_has_restart_int(S390CPU *cpu); -bool s390_cpu_has_stop_int(S390CPU *cpu); +bool s390_cpu_has_io_int(const S390CPU *cpu); +bool s390_cpu_has_ext_int(const S390CPU *cpu); +bool s390_cpu_has_mcck_int(const S390CPU *cpu); +bool s390_cpu_has_int(const S390CPU *cpu); +bool s390_cpu_has_restart_int(const S390CPU *cpu); +bool s390_cpu_has_stop_int(const S390CPU *cpu); void cpu_inject_restart(S390CPU *cpu); void cpu_inject_stop(S390CPU *cpu); #endif /* CONFIG_USER_ONLY */ diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c index 1dca835c5d8..d7e3fd45e4b 100644 --- a/target/s390x/interrupt.c +++ b/target/s390x/interrupt.c @@ -139,10 +139,10 @@ void s390_crw_mchk(void) fsc->inject_crw_mchk(fs); } =20 -bool s390_cpu_has_mcck_int(S390CPU *cpu) +bool s390_cpu_has_mcck_int(const S390CPU *cpu) { QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 if (!(env->psw.mask & PSW_MASK_MCHECK)) { return false; @@ -157,10 +157,10 @@ bool s390_cpu_has_mcck_int(S390CPU *cpu) return false; } =20 -bool s390_cpu_has_ext_int(S390CPU *cpu) +bool s390_cpu_has_ext_int(const S390CPU *cpu) { QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 if (!(env->psw.mask & PSW_MASK_EXT)) { return false; @@ -199,10 +199,10 @@ bool s390_cpu_has_ext_int(S390CPU *cpu) return false; } =20 -bool s390_cpu_has_io_int(S390CPU *cpu) +bool s390_cpu_has_io_int(const S390CPU *cpu) { QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 if (!(env->psw.mask & PSW_MASK_IO)) { return false; @@ -211,21 +211,21 @@ bool s390_cpu_has_io_int(S390CPU *cpu) return qemu_s390_flic_has_io(flic, env->cregs[6]); } =20 -bool s390_cpu_has_restart_int(S390CPU *cpu) +bool s390_cpu_has_restart_int(const S390CPU *cpu) { - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 return env->pending_int & INTERRUPT_RESTART; } =20 -bool s390_cpu_has_stop_int(S390CPU *cpu) +bool s390_cpu_has_stop_int(const S390CPU *cpu) { - CPUS390XState *env =3D &cpu->env; + const CPUS390XState *env =3D &cpu->env; =20 return env->pending_int & INTERRUPT_STOP; } =20 -bool s390_cpu_has_int(S390CPU *cpu) +bool s390_cpu_has_int(const S390CPU *cpu) { if (!tcg_enabled()) { return false; --=20 2.53.0 From nobody Fri Aug 21 21:26:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787222961661158500 @iprio[] is an array only accessed read-only. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 376cff656fa..bb4c8563554 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -642,7 +642,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env); int riscv_cpu_vsirq_pending(CPURISCVState *env); int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_prio, - uint64_t pending, uint8_t *iprio); + uint64_t pending, const uint8_t *iprio); =20 =20 bool riscv_cpu_fp_enabled(CPURISCVState *env); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e73ff53159c..68f5a620402 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -866,7 +866,7 @@ uint8_t riscv_cpu_default_priority(int irq) =20 int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_prio, - uint64_t pending, uint8_t *iprio) + uint64_t pending, const uint8_t *iprio) { int irq, best_irq =3D RISCV_EXCP_NONE; unsigned int prio, best_prio =3D UINT_MAX; --=20 2.53.0 From nobody Fri Aug 21 21:26:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787222990; cv=none; d=zohomail.com; s=zohoarc; b=IVlXj9sv0JIVi3c9mhoSJ2Kni3pWSOA2L9WdP5VHZiGW+OYYsh/nUulH6zGO2P2NWsesQzsZg7wRYkUURLCihb3re/1fv69v/XkN3QpK4G1SdqgKUWgUviPD9fwv3zF58koHT4FX60yuD7HonfMCvQ09ZZwfN5bn5RxQoVBpRK8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787222990; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nYEga+4OcEVia3VM7f85YtQuaKth7rLR95DfKAITOyo=; b=BMq0nFw/VQdep45bC75gyfovWlrybpUcztDBCMYFsp6/aQYWsqI2XkOZFCrJzIQscgX5lnKOqQeTGN02xIrU59jr00swezbjWqDsATW7XHnI4jLYCz382lLzYS28zA4u7kFDkXxDu7shGgC8qcTvEgYEJOMH3X1kr1yJAkSYAUU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787222990393970.3602074338174; Thu, 20 Aug 2026 03:49:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx0K9-0001WI-3F; Thu, 20 Aug 2026 06:48:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0K7-0001SJ-3j for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:48:39 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0K4-0005q3-GR for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:48:38 -0400 Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67K8tIsg3515473 for ; Thu, 20 Aug 2026 10:48:25 GMT Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5xgc8f4r-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 10:48:25 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-92e695a3b28so89941985a.1 for ; Thu, 20 Aug 2026 03:48:24 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/riscv/cpu.h | 17 +++++++++-------- target/riscv/cpu.c | 2 +- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bb4c8563554..2333dcecd8a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -636,7 +636,7 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArr= ay *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); uint8_t riscv_cpu_default_priority(int irq); -uint64_t riscv_cpu_all_pending(CPURISCVState *env); +uint64_t riscv_cpu_all_pending(const CPURISCVState *env); int riscv_cpu_mirq_pending(CPURISCVState *env); int riscv_cpu_sirq_pending(CPURISCVState *env); int riscv_cpu_vsirq_pending(CPURISCVState *env); @@ -746,7 +746,7 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) +static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env) { return env->misa_mxl; } @@ -759,7 +759,7 @@ static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURI= SCVState *env) } =20 #if !defined(CONFIG_USER_ONLY) -static inline privilege_mode_t cpu_address_mode(CPURISCVState *env) +static inline privilege_mode_t cpu_address_mode(const CPURISCVState *env) { privilege_mode_t mode =3D env->priv; =20 @@ -769,7 +769,8 @@ static inline privilege_mode_t cpu_address_mode(CPURISC= VState *env) return mode; } =20 -static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mod= e) +static inline RISCVMXL cpu_get_xl(const CPURISCVState *env, + privilege_mode_t mode) { RISCVMXL xl =3D env->misa_mxl; /* @@ -797,7 +798,7 @@ static inline RISCVMXL cpu_get_xl(CPURISCVState *env, p= rivilege_mode_t mode) #if defined(TARGET_RISCV32) #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) +static inline RISCVMXL cpu_recompute_xl(const CPURISCVState *env) { #if !defined(CONFIG_USER_ONLY) return cpu_get_xl(env, env->priv); @@ -810,7 +811,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *= env) #if defined(TARGET_RISCV32) #define cpu_address_xl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL cpu_address_xl(CPURISCVState *env) +static inline RISCVMXL cpu_address_xl(const CPURISCVState *env) { #ifdef CONFIG_USER_ONLY return env->xl; @@ -822,7 +823,7 @@ static inline RISCVMXL cpu_address_xl(CPURISCVState *en= v) } #endif =20 -static inline uint16_t riscv_cpu_xlen(CPURISCVState *env) +static inline uint16_t riscv_cpu_xlen(const CPURISCVState *env) { return 16 << env->xl; } @@ -830,7 +831,7 @@ static inline uint16_t riscv_cpu_xlen(CPURISCVState *en= v) #ifdef TARGET_RISCV32 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) +static inline RISCVMXL riscv_cpu_sxl(const CPURISCVState *env) { #ifdef CONFIG_USER_ONLY return env->misa_mxl; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 68f5a620402..a344daf62f8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -908,7 +908,7 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env, * using hvip bits 13:63 from HS-mode. Those are returned in * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending(). */ -uint64_t riscv_cpu_all_pending(CPURISCVState *env) +uint64_t riscv_cpu_all_pending(const CPURISCVState *env) { uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787222961655158500 Add the const qualifier to CPUSPARCState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/sparc/cpu.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 5f583ed9de2..31a16c2af03 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -680,28 +680,28 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, = target_ulong addr, #endif =20 #if defined (TARGET_SPARC64) -static inline int cpu_has_hypervisor(CPUSPARCState *env1) +static inline int cpu_has_hypervisor(const CPUSPARCState *env1) { return env1->def.features & CPU_FEATURE_HYPV; } =20 -static inline int cpu_hypervisor_mode(CPUSPARCState *env1) +static inline int cpu_hypervisor_mode(const CPUSPARCState *env1) { return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); } =20 -static inline int cpu_supervisor_mode(CPUSPARCState *env1) +static inline int cpu_supervisor_mode(const CPUSPARCState *env1) { return env1->pstate & PS_PRIV; } #else -static inline int cpu_supervisor_mode(CPUSPARCState *env1) +static inline int cpu_supervisor_mode(const CPUSPARCState *env1) { return env1->psrs; } #endif =20 -static inline int cpu_interrupts_enabled(CPUSPARCState *env1) +static inline int cpu_interrupts_enabled(const CPUSPARCState *env1) { #if !defined (TARGET_SPARC64) if (env1->psret !=3D 0) @@ -715,7 +715,7 @@ static inline int cpu_interrupts_enabled(CPUSPARCState = *env1) return 0; } =20 -static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) +static inline int cpu_pil_allowed(const CPUSPARCState *env1, int pil) { #if !defined(TARGET_SPARC64) /* level 15 is non-maskable on sparc v8 */ --=20 2.53.0 From nobody Fri Aug 21 21:26:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787223044; cv=none; d=zohomail.com; s=zohoarc; b=Bd0aMs3t6Zpfsz9foCg33B6tG2xoCmq2jmpG33QSg1BHYZcrX8ruyOiaBzqr29ejsY1O9iIDu1TTC2QUY9F+h1X9vKYUQuSwbttILp0H4J/Fa8PkzG0XWPOwcPEZ8krUqQ6VIST5ZihdBdRysduEAOf0tRLr6TGG885uEgr4uGE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787223044; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=n0X57WJLrSAfllLc3a+/YOYqBoRn9oR6RE40Y8FVcNQ=; b=NNHNw95BU9DjAs+dUJ5kgAimCALA/vtkwUXT641OowHAFudh5vl4O8iw+Z1gwyA/5hYxtjXlaIXRDuGUkV9bBFKAIiGdqYWCQoJoeRLdFBx3zGjB3745yjt/PHfDp25QMjN7MP9nsNh3xVRMhGRsO893c09v4fqVSajB5oS38s4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787223044585386.4290208282425; Thu, 20 Aug 2026 03:50:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx0KQ-0001vl-2q; Thu, 20 Aug 2026 06:49:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0KL-0001sc-5g for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:48:53 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0KJ-0005vX-4R for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:48:52 -0400 Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67K6n9Ie3732257 for ; Thu, 20 Aug 2026 10:48:39 GMT Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5vn88wsc-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 10:48:39 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-51bfe3fa93bso22039011cf.2 for ; Thu, 20 Aug 2026 03:48:39 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787223046133158500 Introduce const-qualified variants of cpu_env() and env_archcpu(), to safely access CPU architecture state when it should not be modified. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- include/exec/cpu-common.h | 11 +++++++++++ include/hw/core/cpu.h | 6 ++++++ 2 files changed, 17 insertions(+) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 6594f7fa1be..f3a3799f451 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -79,6 +79,17 @@ static inline bool cpu_loop_exit_requested(const CPUStat= e *cpu) } #endif /* CONFIG_TCG */ =20 +/** + * env_archcpu_const(env) + * @env: The architecture environment (const). + * + * Return the const ArchCPU associated with the environment. + */ +static inline const ArchCPU *env_archcpu_const(const CPUArchState *env) +{ + return (const void *)env - sizeof(CPUState); +} + /** * env_archcpu(env) * @env: The architecture environment diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 81af7b9ee1a..59f777f3f15 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -594,6 +594,12 @@ struct CPUState { QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=3D sizeof(CPUState) - sizeof(CPUNegativeOffsetState)); =20 +static inline const CPUArchState *cpu_env_const(const CPUState *cpu) +{ + /* We validate that CPUArchState follows CPUState in cpu-target.c */ + return (const CPUArchState *)(cpu + 1); +} + static inline CPUArchState *cpu_env(CPUState *cpu) { /* We validate that CPUArchState follows CPUState in cpu-target.c */ --=20 2.53.0 From nobody Fri Aug 21 21:26:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787222994; cv=none; d=zohomail.com; s=zohoarc; b=Z/srFSpZWqgEWfCUjO4bj/1E8b4UGIOB5ddPL4DtsGcC+8Kv8LOUIZapv60YoqXY2dsL04GbKk+o8VaLCOCKhNz7d46hRj/iUCQN+5blz2iAi746mvs02kQ5AgRxWUIdZETt4E9lRIZQjHIwF/dHZdYs24aJ7iZ/iKMkyOzQMos= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787222994; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DQfkNJ6kh6LohDBdsbWuKwhfmfdLvPKv9l7+7bK3h7k=; b=JDmpNUx+ZUW17dcnDHXXV2omkGG6CtW+pvleB+B882Al4bw2t93eYzB9vr0OmgenBLeAW/GZoz/r3UgFwdazcwlAdnFW9D/gaQYypzY7PJl6djaTKyxnqj84IoEfPNkokmA/L4u9oV3QtooMmgHBqePBNW3X77mh/SpBFxBAG5M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787222994041521.3160987618971; Thu, 20 Aug 2026 03:49:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx0Kc-0002E3-Rn; Thu, 20 Aug 2026 06:49:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0KU-00022O-C2 for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:49:03 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0KQ-0005xk-9N for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:49:01 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67K8PCiO2465324 for ; Thu, 20 Aug 2026 10:48:47 GMT Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5x29gjhb-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 10:48:46 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-934963b2bc0so216241285a.3 for ; Thu, 20 Aug 2026 03:48:46 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Thu, 20 Aug 2026 03:48:45 -0700 (PDT) X-Received: by 2002:a05:620a:d87:b0:92e:fc42:2c19 with SMTP id af79cd13be357-9371e24b0c5mr1024158785a.11.1787222925370; Thu, 20 Aug 2026 03:48:45 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Paolo Bonzini , Peter Maydell , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Subject: [RFC PATCH 10/13] target/riscv: Constify CPURISCVState for various cpu_*() getters Date: Thu, 20 Aug 2026 12:47:26 +0200 Message-ID: <20260820104730.25462-11-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260820104730.25462-1-philmd@oss.qualcomm.com> References: <20260820104730.25462-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: Cxuc_iMI5aKgwkVk5YxGbJN-lLyblngV X-Authority-Analysis: v=2.4 cv=V8BNF+ni c=1 sm=1 tr=0 ts=6a86db8e cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=W-temX7IfkLqO7pPVx4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIwMDA3OSBTYWx0ZWRfX0qOYuiucsMOI 213h2wvfTtdJZM142pKXQUoofdl16cTNHQ8ARddp6jsrs4A4esxaOaL7hlo8E2YJJdMIhRsyqIB Hgs4u3LPBhpIMy1DzhJgXhYISfkiwwEC/aNRQvK42nbIaPfb8WfVD1WPcTD5B+CQJoJraKOTSnI fU/5mM6Z9oSyl+n1pnaLwyElIWTjeLQMIMs1X4PBlWdtVJH4ng0rzRoUKN4GL26204G0Y+X4smY dLV7KLvQVFv2jRh28pUVR/0qiXn6P8pDkTiKtxTv6lpayC1KFI/TlXGZ/0euF9qrsi2JQfGISHJ mhf816fj1Ky/vujQBNdmwzWR/4ymFtgrcUjkj/Us9WASz7Z7sbY3vxhVUMR9XhXaE2SK/f+adaA vMtAaFoSReezrQtEdnDICYleeDPfnFSZn4bQod70XlEWD9ifgMe/YzRAab1wgXam189Wt7wiFv8 Xti6LBxFx+3bWC/VMIQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwODIwMDA3OSBTYWx0ZWRfXx71rl0Cgq3tb wv++y5faXUiQdRyuoxArE86wHMRu6md1mx+eT9PbpKTwLwK7kyCPN0MuKZ1lb2WI/KhzEJCwWvH p/GPt/OPrvGtBLJI1bb6gC5uptRko0g= X-Proofpoint-GUID: Cxuc_iMI5aKgwkVk5YxGbJN-lLyblngV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-19_06,2026-08-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 clxscore=1015 bulkscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608200079 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787222995903158500 Add the const qualifier to CPURISCVState when the argument is accessed without modification. Note we have to use the recently introduced env_archcpu_const() helper in riscv_cpu_cfg(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/riscv/cpu.h | 12 ++++++------ target/riscv/cpu.c | 8 ++++---- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2333dcecd8a..9fd9ba54147 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -637,10 +637,10 @@ int riscv_cpu_gdb_write_register(CPUState *cpu, uint8= _t *buf, int reg); int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); uint8_t riscv_cpu_default_priority(int irq); uint64_t riscv_cpu_all_pending(const CPURISCVState *env); -int riscv_cpu_mirq_pending(CPURISCVState *env); -int riscv_cpu_sirq_pending(CPURISCVState *env); -int riscv_cpu_vsirq_pending(CPURISCVState *env); -int riscv_cpu_pending_to_irq(CPURISCVState *env, +int riscv_cpu_mirq_pending(const CPURISCVState *env); +int riscv_cpu_sirq_pending(const CPURISCVState *env); +int riscv_cpu_vsirq_pending(const CPURISCVState *env); +int riscv_cpu_pending_to_irq(const CPURISCVState *env, int extirq, unsigned int extirq_def_prio, uint64_t pending, const uint8_t *iprio); =20 @@ -753,9 +753,9 @@ static inline RISCVMXL riscv_cpu_mxl(const CPURISCVStat= e *env) #endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) =20 -static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) +static inline const RISCVCPUConfig *riscv_cpu_cfg(const CPURISCVState *env) { - return &env_archcpu(env)->cfg; + return &env_archcpu_const(env)->cfg; } =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a344daf62f8..ab2868dc1e2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -864,7 +864,7 @@ uint8_t riscv_cpu_default_priority(int irq) return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; }; =20 -int riscv_cpu_pending_to_irq(CPURISCVState *env, +int riscv_cpu_pending_to_irq(const CPURISCVState *env, int extirq, unsigned int extirq_def_prio, uint64_t pending, const uint8_t *iprio) { @@ -917,7 +917,7 @@ uint64_t riscv_cpu_all_pending(const CPURISCVState *env) return (env->mip | vsgein | vstip) & env->mie; } =20 -int riscv_cpu_mirq_pending(CPURISCVState *env) +int riscv_cpu_mirq_pending(const CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & ~env->mideleg & ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); @@ -926,7 +926,7 @@ int riscv_cpu_mirq_pending(CPURISCVState *env) irqs, env->miprio); } =20 -int riscv_cpu_sirq_pending(CPURISCVState *env) +int riscv_cpu_sirq_pending(const CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & ~env->hi= deleg; uint64_t irqs_f =3D env->mvip & env->mvien & ~env->mideleg & env->sie; @@ -935,7 +935,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env) irqs | irqs_f, env->siprio); } =20 -int riscv_cpu_vsirq_pending(CPURISCVState *env) +int riscv_cpu_vsirq_pending(const CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & env->hid= eleg; uint64_t irqs_f_vs =3D env->hvip & env->hvien & ~env->hideleg & env->v= sie; --=20 2.53.0 From nobody Fri Aug 21 21:26:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787223021; cv=none; d=zohomail.com; s=zohoarc; b=OiwtpdrRjDWWjkqteALWdr5WG9fQfZnaYYkLZy9pNTOO6+eimRvmV/VJxG0/QMli8NIhD2mUh0nUR+NBJCzgOe2K0Bzgm7LFxjJ2Gdr9FRXsjF9/H/QcnLDqIsSBT6rLw7Uvapc5PI1LNSMsnirYTt5DKbz96vWLSZI7CF65++0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787223021; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QJSF2rPYmDquPvZ6e5qTsgWad+K5wpHwQLhcT52dtMI=; b=H7vn8/KI+c55SFTjPUCVpiXigjHe1n8w+72ERWUrxDf102QAGe+6rfUcIGsd4N9sQT7zyfSxsmEeB/+KqKWzq+4LbCLXESlyjRt0MsNiM7m16+Db1fmDSHoEuuzYFDIofbL2SpUDq/EPkQmOAWf9FpYEMPngC3aZksU8EcZyhb4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787223021947173.8181361458934; Thu, 20 Aug 2026 03:50:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx0Kf-0002Po-3h; Thu, 20 Aug 2026 06:49:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0Kc-0002F7-TI for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:49:11 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0KW-0005zc-Is for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:49:08 -0400 Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67KA3Jcq3454887 for ; Thu, 20 Aug 2026 10:48:53 GMT Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5yg885sf-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 10:48:53 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-92e63df032bso89678485a.0 for ; Thu, 20 Aug 2026 03:48:53 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787223023889158500 Use the recently introduced env_archcpu_const() helper and qualify @env as being const in hexagon_thread_is_enabled(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Brian Cain Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/hexagon/cpu.h | 2 +- target/hexagon/cpu.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index c50fbb3f72a..e4f120eda17 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -216,7 +216,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonS= tate *env, * @return true if the @a thread_env hardware thread is * not stopped. */ -bool hexagon_thread_is_enabled(CPUHexagonState *thread_env); +bool hexagon_thread_is_enabled(const CPUHexagonState *thread_env); uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg); void hexagon_cpu_soft_reset(CPUHexagonState *env); #endif diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 9765716b516..7ae5740899b 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -345,9 +345,9 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *c= s, } =20 #ifndef CONFIG_USER_ONLY -bool hexagon_thread_is_enabled(CPUHexagonState *env) +bool hexagon_thread_is_enabled(const CPUHexagonState *env) { - HexagonCPU *cpu =3D env_archcpu(env); + const HexagonCPU *cpu =3D env_archcpu_const(env); uint32_t modectl; uint32_t thread_enabled_mask; bool E_bit; --=20 2.53.0 From nobody Fri Aug 21 21:26:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787222981; cv=none; d=zohomail.com; s=zohoarc; b=WNBrvqL79BqkwS7LiWR9RkMaj3PQNXkF9pYIfdJDdtZaYwH62Tc0aSFm6Ze+8HA2So6fqQNUGpVLr47X5HV5vjV7giPrs2TJFGocpsN9mVJW/OeBZmAidHS8BvFUkVepivVtTYF0lxGaMg4kEGKI/qo1aC1vpux3ajnMBPIPrwE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787222981; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1lPeDKWhyf6BBMuDNMEYdwwD11UjrKI3mpFnJczn7hk=; b=TAC07FnHcMlE1EZII471NeH8HSWx5qtT6b2gyM+ek5Gjte7yqFNSrHw7ryBh+linAov6A+JxO7wuG3RTAxNEBDTF2n88TD/RN+nUM/5Y0iOs87G4xtiVM2sGt0J76u6dRJWHH3g/yTjBeo5vPsFFpTHItyCTHolmwK9HWGFV4GU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787222981038326.5465798720919; Thu, 20 Aug 2026 03:49:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx0Kh-0002Zt-8c; Thu, 20 Aug 2026 06:49:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0Kf-0002R3-No for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:49:13 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0Ke-000643-6k for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:49:13 -0400 Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67K9JBJw2927086 for ; Thu, 20 Aug 2026 10:49:01 GMT Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5xuk0bde-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 10:49:01 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-936d067836eso249117985a.0 for ; Thu, 20 Aug 2026 03:49:01 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787222982101158500 Use the recently introduced env_archcpu_const() helper and qualify @env as being const in mips_vpe_active(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/mips/internal.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 66e8c599b43..88459539866 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -247,9 +247,9 @@ static inline void restore_pamask(CPUMIPSState *env) } } =20 -static inline int mips_vpe_active(CPUMIPSState *env) +static inline int mips_vpe_active(const CPUMIPSState *env) { - MIPSCPU *cpu =3D env_archcpu(env); + const MIPSCPU *cpu =3D env_archcpu_const(env); int active =3D 1; =20 /* Check that the VPE is enabled. */ --=20 2.53.0 From nobody Fri Aug 21 21:26:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1787223025; cv=none; d=zohomail.com; s=zohoarc; b=CQGI9OJxvZbdobMbWFl2GfS62w2e5YILH8ftd9SgXk/w5zE+okPYHtwRIX29+ax1sZZhFc81QlYF79/nvLRgaY1ZVB87/WHbrfBN3X6Aed3TFpuLDb+QAQPsIpWwm3UL7dGbNQ/2sUKG68cGE39n4U01mxtAGF5ZWuT5xRITqiQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787223025; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TipPX5YNw3dRxG7nvDBKnheNZjk+0BKwSN/9tefKD8U=; b=HOUYPbkZWzI1/gjZbhbx8TABppfwjO0Hp2dcjijFi7FuEpmnMvQNTX/ywrMw7e5tYijG3Akp5w7kujf7JKERMBpJlAc54AnGVVKcU16VLqah4UluSNTYKu43Kl0whscqEAIFg/U6mG2KmefBviK7V+TEkVvCHNDQKMZT+bZUoZg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1787223025325232.72220627542538; Thu, 20 Aug 2026 03:50:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wx0Ku-0003nQ-BH; Thu, 20 Aug 2026 06:49:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0Ks-0003h6-BP for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:49:26 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wx0Ko-00067Q-Ct for qemu-devel@nongnu.org; Thu, 20 Aug 2026 06:49:26 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67K6eZCj2161130 for ; Thu, 20 Aug 2026 10:49:11 GMT Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g5vh7rx2j-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 20 Aug 2026 10:49:10 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-92e62e3459fso241083385a.0 for ; Thu, 20 Aug 2026 03:49:10 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Cornelia Huck , Eric Farman , Matthew Rosato , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [RFC PATCH 13/13] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Date: Thu, 20 Aug 2026 12:47:29 +0200 Message-ID: <20260820104730.25462-14-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260820104730.25462-1-philmd@oss.qualcomm.com> References: <20260820104730.25462-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIwMDA3OSBTYWx0ZWRfXxPN1Llm0fk99 ZasZALa70zANBbGx4hdyMxnQcay7pPOzK+Z21DSN+Jv3IDqhR2Va3vMmLcM79Ffq6Ee0W4exqjt TIezmPU9yo84UjdoESRPSxYso4reY7rEUwuXJY7liI1TgcvZb2HT/eHwJ6LM+NOgQMEuBoLKPZG 6OGyca6pk6Yup5+Faniv4pLfm80J+QnVAUaAUxQM5+zX6rhczfkj1xZNa3h7o/057fKNvJ6INT6 GeuQdjQF1O5AzpbWlF1r0R9IfyS2piRbxNhaoyvotsvM0Y3tvHBrNAwZFCHZoT1oH/giFQsJCoB 8bGAHS2xkWMG9qoWJggnW1EX/9LGIyvapMMt4/FVloBYm8tvGaFk8Ac0CtT9kgxhPcNEITEku5s 99UU9k9CPfpZBuOnbP2fWC/54ZAj8VK93JfEJUCO+Pm+F+6rXlo0GU7tLadAWpV7daWhO2uzHkR D26uSylLL48/LtmS3ww== X-Proofpoint-ORIG-GUID: x7Wn0V3HpNm6OVbK6H_62c4S8ECQvXJD X-Authority-Analysis: v=2.4 cv=Y7fIdBeN c=1 sm=1 tr=0 ts=6a86dba6 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=SERbGe8VzmIjvadycG8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODIwMDA3OSBTYWx0ZWRfX9QeNU/UnlOuC opKJQOtGyroIbMLHCS3TWQe2TO47WhHJfEODRR+a2mN2rprsBmjihQBJfkS4shUHCxUjWxB03ca jHHop9/ixB8LkLL+ELV9uVXu+xWy99M= X-Proofpoint-GUID: x7Wn0V3HpNm6OVbK6H_62c4S8ECQvXJD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-19_06,2026-08-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 clxscore=1015 malwarescore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608200079 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1787223026343158500 All functions called by target has_work() handler take a const @cpu argument. We can now fulfill the comment added in commit c2804566f6 ("target/arm: do not clear halting reason in has_work helper"), qualifying the handler const to denote its idempotency. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/sysemu-cpu-ops.h | 4 ++-- target/loongarch/internals.h | 2 +- target/riscv/internals.h | 2 +- target/s390x/s390x-internal.h | 2 +- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 4 ++-- target/avr/cpu.c | 5 +++-- target/hexagon/cpu.c | 4 ++-- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/loongarch/cpu.c | 4 ++-- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 4 ++-- target/or1k/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu-system.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 4 ++-- target/tricore/cpu.c | 4 ++-- target/xtensa/cpu.c | 4 ++-- 23 files changed, 33 insertions(+), 32 deletions(-) diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 9a45596169a..095bdcd997a 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -19,10 +19,10 @@ typedef struct SysemuCPUOps { /** * @has_work: Callback for checking if there is work to do. * - * This function should be idempotent (i.e. not change state) as + * This function is idempotent (i.e. not change state) as * it will likely be queried multiple times before a CPU resumes. */ - bool (*has_work)(CPUState *cpu); /* MANDATORY NON-NULL */ + bool (*has_work)(const CPUState *cpu); /* MANDATORY NON-NULL */ /** * @get_memory_mapping: Callback for obtaining the memory mappings. */ diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index 6a733e6c3a5..d86029bcb31 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -38,7 +38,7 @@ uint64_t cpu_loongarch_get_constant_timer_counter(LoongAr= chCPU *cpu); uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu); void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu, uint64_t value); -bool loongarch_cpu_has_work(CPUState *cs); +bool loongarch_cpu_has_work(const CPUState *cs); bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env); #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 5d84e4de960..782f12abfaf 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -203,7 +203,7 @@ static inline target_ulong get_xepc_mask(CPURISCVState = *env) =20 #ifndef CONFIG_USER_ONLY /* Our implementation of SysemuCPUOps::has_work */ -bool riscv_cpu_has_work(CPUState *cs); +bool riscv_cpu_has_work(const CPUState *cs); #endif =20 /* Zjpm addr masking routine */ diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 54b62808d83..00917473a54 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -248,7 +248,7 @@ bool s390_cpu_system_realize(DeviceState *dev, Error **= errp); void s390_cpu_finalize(Object *obj); void s390_cpu_system_class_init(CPUClass *cc); void s390_cpu_machine_reset_cb(void *opaque); -bool s390_cpu_has_work(CPUState *cs); +bool s390_cpu_has_work(const CPUState *cs); #endif /* CONFIG_USER_ONLY */ =20 =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 7d1d036e1d3..21d4f8ac23b 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -77,7 +77,7 @@ static void alpha_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool alpha_cpu_has_work(CPUState *cs) +static bool alpha_cpu_has_work(const CPUState *cs) { /* Here we are checking to see if the CPU should wake up from HALT. We will have gotten into this state only for WTINT from PALmode. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9761bb173c1..ba66359d410 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -141,9 +141,9 @@ int arm_cpu_mmu_index(CPUState *cs, bool ifetch) * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here * unconditionally. */ -static bool arm_cpu_has_work(CPUState *cs) +static bool arm_cpu_has_work(const CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); + const ARMCPU *cpu =3D ARM_CPU(cs); =20 /* * Only another PSCI call can wake the CPU up in which case the diff --git a/target/avr/cpu.c b/target/avr/cpu.c index a01e6fa4751..1024c0ae9a2 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -23,6 +23,7 @@ #include "qemu/qemu-print.h" #include "exec/translation-block.h" #include "system/address-spaces.h" +#include "hw/core/cpu.h" #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" @@ -43,10 +44,10 @@ static vaddr avr_cpu_get_pc(CPUState *cs) return cpu->env.pc_w * 2; } =20 -static bool avr_cpu_has_work(CPUState *cs) +static bool avr_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET) - && cpu_interrupts_enabled(cpu_env(cs)); + && cpu_interrupts_enabled(cpu_env_const(cs)); } =20 static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 7ae5740899b..4ad1cae354a 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -364,9 +364,9 @@ bool hexagon_thread_is_enabled(const CPUHexagonState *e= nv) return E_bit; } =20 -static bool hexagon_cpu_has_work(CPUState *cs) +static bool hexagon_cpu_has_work(const CPUState *cs) { - CPUHexagonState *env =3D cpu_env(cs); + const CPUHexagonState *env =3D cpu_env_const(cs); =20 return hexagon_thread_is_enabled(env) && (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 7b1309a7c38..dbf58466c24 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -134,7 +134,7 @@ static void hppa_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool hppa_cpu_has_work(CPUState *cs) +static bool hppa_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8777bcbae85..93b617f94dc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10639,7 +10639,7 @@ int x86_cpu_pending_interrupt(const CPUState *cs, i= nt interrupt_request) return 0; } =20 -static bool x86_cpu_has_work(CPUState *cs) +static bool x86_cpu_has_work(const CPUState *cs) { return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; } diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 82ec35e081f..4c1aae4fb01 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -96,12 +96,12 @@ bool cpu_loongarch_hw_interrupts_pending(const CPULoong= ArchState *env) #endif =20 #ifndef CONFIG_USER_ONLY -bool loongarch_cpu_has_work(CPUState *cs) +bool loongarch_cpu_has_work(const CPUState *cs) { bool has_work =3D false; =20 if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && - cpu_loongarch_hw_interrupts_pending(cpu_env(cs))) { + cpu_loongarch_hw_interrupts_pending(cpu_env_const(cs))) { has_work =3D true; } =20 diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 523694d8fbf..da3681fab1f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -76,7 +76,7 @@ static void m68k_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool m68k_cpu_has_work(CPUState *cs) +static bool m68k_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6013a8def8e..d1d2f0ec7e3 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -127,7 +127,7 @@ static void mb_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool mb_cpu_has_work(CPUState *cs) +static bool mb_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c069aa1c0b7..0f9374d98a9 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -134,9 +134,9 @@ static vaddr mips_cpu_get_pc(CPUState *cs) } =20 #if !defined(CONFIG_USER_ONLY) -static bool mips_cpu_has_work(CPUState *cs) +static bool mips_cpu_has_work(const CPUState *cs) { - CPUMIPSState *env =3D cpu_env(cs); + const CPUMIPSState *env =3D cpu_env_const(cs); bool has_work =3D false; =20 /* diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c index 42d9351b6d7..10b13ae69cd 100644 --- a/target/or1k/cpu.c +++ b/target/or1k/cpu.c @@ -76,7 +76,7 @@ static void openrisc_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool openrisc_cpu_has_work(CPUState *cs) +static bool openrisc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER= ); } diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 85a91ff4bb6..fd63cd6ab09 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7224,7 +7224,7 @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetc= h) #endif /* CONFIG_TCG */ =20 #ifndef CONFIG_USER_ONLY -static bool ppc_cpu_has_work(CPUState *cs) +static bool ppc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ab2868dc1e2..b455b997561 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -950,7 +950,7 @@ int riscv_cpu_vsirq_pending(const CPURISCVState *env) (irqs | irqs_f_vs), env->hviprio); } =20 -bool riscv_cpu_has_work(CPUState *cs) +bool riscv_cpu_has_work(const CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 69946928995..dfa09a85bce 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -73,7 +73,7 @@ static void rx_restore_state_to_opc(CPUState *cs, cpu->env.pc =3D data[0]; } =20 -static bool rx_cpu_has_work(CPUState *cs) +static bool rx_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c index cc9685221ae..22ed2b097bb 100644 --- a/target/s390x/cpu-system.c +++ b/target/s390x/cpu-system.c @@ -39,7 +39,7 @@ #include "system/tcg.h" #include "hw/core/sysemu-cpu-ops.h" =20 -bool s390_cpu_has_work(CPUState *cs) +bool s390_cpu_has_work(const CPUState *cs) { S390CPU *cpu =3D S390_CPU(cs); =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 55c73a1da35..b0ed356d0f7 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -107,7 +107,7 @@ static bool superh_io_recompile_replay_branch(CPUState = *cs, return false; } =20 -static bool superh_cpu_has_work(CPUState *cs) +static bool superh_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 2baa5036871..f7c04daf0c9 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -783,10 +783,10 @@ static void sparc_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool sparc_cpu_has_work(CPUState *cs) +static bool sparc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && - cpu_interrupts_enabled(cpu_env(cs)); + cpu_interrupts_enabled(cpu_env_const(cs)); } #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 6d448727005..33a5875ef24 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -111,9 +111,9 @@ static void tricore_cpu_reset_hold(Object *obj, ResetTy= pe type) cpu_state_reset(cpu_env(cs)); } =20 -static bool tricore_cpu_has_work(CPUState *cs) +static bool tricore_cpu_has_work(const CPUState *cs) { - return true; + return true; /* XXX */ } =20 static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 99c8bd4b5fb..fe7965651f4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -140,9 +140,9 @@ static void xtensa_restore_state_to_opc(CPUState *cs, } =20 #ifndef CONFIG_USER_ONLY -static bool xtensa_cpu_has_work(CPUState *cs) +static bool xtensa_cpu_has_work(const CPUState *cs) { - CPUXtensaState *env =3D cpu_env(cs); + const CPUXtensaState *env =3D cpu_env_const(cs); =20 return !env->runstall && env->pending_irq_level; } --=20 2.53.0