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Mon, 17 Aug 2026 09:03:33 -0700 (PDT) From: Mayuresh Chitale To: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Cc: Mayuresh Chitale , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [RFC PATCH 1/2] target/riscv: Add Sspesa extension and sample CSRs Date: Mon, 17 Aug 2026 21:33:16 +0530 Message-ID: <20260817160321.3313698-2-mayuresh.chitale@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260817160321.3313698-1-mayuresh.chitale@oss.qualcomm.com> References: <20260817160321.3313698-1-mayuresh.chitale@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 6NzQdgFxab3fL_BEKlnVGr2KkvByntg1 X-Proofpoint-Spam-Info: AW1haW4tMjYwODE3MDEyMyBTYWx0ZWRfX1P5v8WtrNEWh F/LWggfHWCxOPZ8Pe+8HTatSHUnfXGBrb9mjkmBOAT/99u9jzcPLLXKmCE5xzfFNCVTROPIdcWD YBcc2jZlpNGcR8OozFzszd1iqQ9YNsE= X-Authority-Analysis: v=2.4 cv=SuCgLvO0 c=1 sm=1 tr=0 ts=6a8330d7 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=l_Sd8zgwI-MehHJ8ahkA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-ORIG-GUID: 6NzQdgFxab3fL_BEKlnVGr2KkvByntg1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE3MDEyMyBTYWx0ZWRfX5JWXnHRzjE1B Je4P0GHGYmuUMER2BOQ+KO1HHQcDYBqQ89o4UfZP1jkYzXz1pcix/JwoffL0JJFCyFLAkfzzXTe 4z7vLSIaAHKn/3Gsv0mmHDmVmdApCeo+oDdz1X2rkOOCJakun5S5HN3HiVZC8PMm793p86XAViz tIu++orRahyhPQz9b/hd6qXG0BYLKx6BkHrCAhp5A/3afPAs54pzd8NacPcJw2bnleXSpu1yerw BRYPPA6j0BrN0DquLOIg3XO++94G1jL+itCRJ1T3jbXF8tbuTB89uj6QSp6KBXs1+foeuC3cw94 8Exx5TpMST4fB8OLL+j4HFIjtPG9lbrcRbkVwKVMlcqoJWuNvbxMB9uqd3A5rO/QxU+kYhGQkNk EfGB8IlbnbIsIq+lDH3hqz8qQzx8AU3kjh0K9Mmap6R3oQYjsgrc6JZ+4G4KZj7F633ybbPqzmQ RwLPKxMa/90tbRkg1aw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-17_02,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 priorityscore=1501 phishscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608170123 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=mayuresh.chitale@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1786982649198158500 Content-Type: text/plain; charset="utf-8" Add initial support for the Sspesa (Precise Event Sample Attribution) extension from the RISC-V Performance Event Sampling specification. Added the 'sspesa' and ssplcofi CPU properties, and the shpmspc and shpmsdata CSRs. Signed-off-by: Mayuresh Chitale Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 13 ++++++- target/riscv/cpu.h | 4 +++ target/riscv/cpu_bits.h | 7 ++++ target/riscv/cpu_cfg_fields.h.inc | 2 ++ target/riscv/tcg/csr.c | 59 +++++++++++++++++++++++++++++-- 5 files changed, 82 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5a82e6563b..f936cdeb68 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -278,6 +278,8 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(ssctr, PRIV_VERSION_1_12_0, ext_ssctr), ISA_EXT_DATA_ENTRY(ssdbltrp, PRIV_VERSION_1_13_0, ext_ssdbltrp), ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm), + ISA_EXT_DATA_ENTRY(sspesa, PRIV_VERSION_1_12_0, ext_sspesa), + ISA_EXT_DATA_ENTRY(ssplcofi, PRIV_VERSION_1_12_0, ext_ssplcofi), ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm), ISA_INTERNAL_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstat= een), ISA_INTERNAL_EXT_DATA_ENTRY(ssstrict, PRIV_VERSION_1_12_0, has_priv_1_= 12), @@ -2800,6 +2802,15 @@ static RISCVCPUImpliedExtsRule SSSTATEEN_IMPLIED =3D= { }, }; =20 +static RISCVCPUImpliedExtsRule SSPESA_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_sspesa), + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_ssplcofi), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED =3D { .ext =3D CPU_CFG_OFFSET(ext_zvfbfa), .implied_multi_exts =3D { @@ -2829,7 +2840,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rule= s[] =3D { &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SHA_IMPLIED, &SSCFG_IMPLIED, &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED, - &SSCTR_IMPLIED, &SSSTATEEN_IMPLIED, + &SSCTR_IMPLIED, &SSSTATEEN_IMPLIED, &SSPESA_IMPLIED, NULL }; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c9dfa7daff..fe56a6afd1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -470,6 +470,10 @@ struct CPUArchState { uint64_t sscratch; uint64_t mscratch; =20 + /* Sspesa CSRs */ + target_ulong shpmspc; + target_ulong shpmsdata; + /* Sstc CSRs */ uint64_t stimecmp; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 3f146a43fe..d3afc9cada 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -601,6 +601,13 @@ =20 #define CSR_SCOUNTOVF 0xda0 =20 + /* Temporary addresses for Sspesa (Precise Event Sample Attribution) CSRs= . */ +#define CSR_SHPMSPC 0x5d0 +#define CSR_SHPMSDATA 0x5d1 + +/* shpmsdata fields */ +#define SHPMSDATA_CNTRID 0x1f + /* Crypto Extension */ #define CSR_SEED 0x015 =20 diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 9eb47af0a7..05e0162b76 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -110,6 +110,8 @@ BOOL_FIELD(ext_ssaia) BOOL_FIELD(ext_smctr) BOOL_FIELD(ext_ssctr) BOOL_FIELD(ext_sscofpmf) +BOOL_FIELD(ext_sspesa) +BOOL_FIELD(ext_ssplcofi) BOOL_FIELD(ext_smepmp) BOOL_FIELD(ext_smrnmi) BOOL_FIELD(ext_ssnpm) diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index eb823b16b5..ea49d28aae 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -276,6 +276,28 @@ static RISCVException smcntrpmf(CPURISCVState *env, in= t csrno) return RISCV_EXCP_NONE; } =20 +static RISCVException sspesa(CPURISCVState *env, int csrno) +{ + bool menvcfg_cde; + + if (!riscv_cpu_cfg(env)->ext_sspesa) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (env->priv =3D=3D PRV_M) { + return RISCV_EXCP_NONE; + } + + menvcfg_cde =3D get_field(env->menvcfg, MENVCFG_CDE); + /* Access to shpmspc/shpmsdata from VS-mode always causes a fault */ + if (env->virt_enabled) { + return menvcfg_cde ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : + RISCV_EXCP_ILLEGAL_INST; + } + + return menvcfg_cde ? RISCV_EXCP_NONE : RISCV_EXCP_ILLEGAL_INST; +} + static RISCVException smcntrpmf_32(CPURISCVState *env, int csrno) { if (riscv_cpu_mxl(env) !=3D MXL_RV32) { @@ -1672,6 +1694,34 @@ static RISCVException read_scountovf(CPURISCVState *= env, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_shpmspc(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->shpmspc; + return RISCV_EXCP_NONE; +} + +static RISCVException write_shpmspc(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + env->shpmspc =3D val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_shpmsdata(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->shpmsdata; + return RISCV_EXCP_NONE; +} + +static RISCVException write_shpmsdata(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + env->shpmsdata =3D val; + return RISCV_EXCP_NONE; +} + static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) { @@ -3220,7 +3270,7 @@ static RISCVException write_menvcfg(CPURISCVState *en= v, int csrno, if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { mask |=3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_smcdeleg ? MENVCFG_CDE : 0) | + ((cfg->ext_smcdeleg || cfg->ext_sspesa) ? MENVCFG_CDE : 0)= | (cfg->ext_svadu ? MENVCFG_ADUE : 0) | (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); =20 @@ -3272,7 +3322,7 @@ static RISCVException write_menvcfgh(CPURISCVState *e= nv, int csrno, uint64_t mask =3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | (cfg->ext_svadu ? MENVCFG_ADUE : 0) | - (cfg->ext_smcdeleg ? MENVCFG_CDE : 0) | + ((cfg->ext_smcdeleg || cfg->ext_sspesa) ? MENVCFG_CDE = : 0) | (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); uint64_t valh =3D (uint64_t)val << 32; bool stce_changed =3D false; @@ -6771,6 +6821,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_mhpmcounterh }, [CSR_SCOUNTOVF] =3D { "scountovf", sscofpmf, read_scountovf, .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_SHPMSPC] =3D { "shpmspc", sspesa, read_shpmspc, write_sh= pmspc, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_SHPMSDATA] =3D { "shpmsdata", sspesa, read_shpmsdata, + write_shpmsdata, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 #endif /* !CONFIG_USER_ONLY */ }; --=20 2.43.0 From nobody Sat Sep 26 23:03:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1786982648; cv=none; d=zohomail.com; s=zohoarc; b=G86eaevtIjJqXsPM0rwHpqu0DggN17jX02aiuewbrhkQZ4NgQjGx7MQL3iJx/Sc3lk6P+pWIuagMWYOjfDQHhW3ROgr1AYH7mxmQHv0QlQ0xOpnj8sOXdtXtSFrc1avQ/YhNhdi+aJ6V277FEsSy0yJV7RKtXSTK5s61+uZBjHs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786982648; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IN5d9diPA+5gtrEwQvCPi+67EjQ5+TqAioWBC9q16SA=; b=JT9hY8wgb7v4E9ABuxWmEHzRP+xwFRfOBkplZ9bnyFg708uiO2RnrHxDTjG6uHO5NfqIymzmfBp2QynbGTcTwqQ3QWzvtM4xApTWLC8dNDuNAlvWrypKlcLwh9B3uRSz82pJrkhVD7FHOqYv774t+ZdHb/oFdij5m8BcoiyI+hc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178698264876357.669953082901884; Mon, 17 Aug 2026 09:04:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wvzoX-0002CF-KV; Mon, 17 Aug 2026 12:03:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wvzoO-0001vV-Bi for qemu-devel@nongnu.org; Mon, 17 Aug 2026 12:03:48 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wvzoK-0006xB-No for qemu-devel@nongnu.org; Mon, 17 Aug 2026 12:03:43 -0400 Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67HFYwOZ1530602 for ; Mon, 17 Aug 2026 16:03:39 GMT Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g3wke258m-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 17 Aug 2026 16:03:39 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-84e048a801dso4794105b3a.3 for ; Mon, 17 Aug 2026 09:03:39 -0700 (PDT) Received: from hu-mchitale-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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Mon, 17 Aug 2026 09:03:37 -0700 (PDT) From: Mayuresh Chitale To: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Cc: Mayuresh Chitale , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [RFC PATCH 2/2] target/riscv: Capture Sspesa sample PC and counter ID on overflow Date: Mon, 17 Aug 2026 21:33:17 +0530 Message-ID: <20260817160321.3313698-3-mayuresh.chitale@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260817160321.3313698-1-mayuresh.chitale@oss.qualcomm.com> References: <20260817160321.3313698-1-mayuresh.chitale@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE3MDEyMyBTYWx0ZWRfX7d2Nwr1OjW37 TDc5wAiF+NDkHRbFpSzjTAxIu8QpJ/5tD/4PHCj3yenKeKbNf72qMwhHrpVQ7GKZ7cOiseEo0ry 6wT93gP9j57OUrUjR6+U8UEt7i7EVBD5tMxrDj9TFiJQ1MVWJeOWZ2jA52CirL+czKiTnZYSfQd XG1z75dbXQnxhvhp90idr75juYcbU8cRhgp2cyj0Rt6MR5Tv3orISxDuTEy9L6B7ykc8H06h46l 2i548BxrwiG9PvvNGZDMnsoBV4WnAT4nKYqXbRHELv535hwvKOdkbME5YGV/kRmuyFYwtYHLyMo pj/OblY7q1v0VhA8qkuBZFlkCrj2w6R8TOBDYLRJWr6p9tbnkiGDUGMYv4PqMyG24cxhEE6l72o KCVng9+Yx/3Xsk29W4NiuaHjjdXFHXwRq230WAAwHiy1WiTR7V4qOoO1elbYFw1vVkom8O0FUYl lhaGtY58dHaflBR5KWw== X-Authority-Analysis: v=2.4 cv=QetWeMbv c=1 sm=1 tr=0 ts=6a8330db cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=DHycWIkPxntEYEsfrQ0A:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: vvqH8HDF1RGU3CwpQsq6HqmLZ5IiCs10 X-Proofpoint-GUID: vvqH8HDF1RGU3CwpQsq6HqmLZ5IiCs10 X-Proofpoint-Spam-Info: AW1haW4tMjYwODE3MDEyMyBTYWx0ZWRfXyTxmLSo/AZdV C37UxaIqN1ZhguOw9wkUkucEh4oks+f1sUQx8MFcG2o+Nr2dQc2ZRQU07+SlFoYjKhAPZ+9dBab Lsk1UxYUdaJNhrJ+dW28rbPJATR7qNQ= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-17_02,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608170123 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=mayuresh.chitale@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1786982651296158500 Content-Type: text/plain; charset="utf-8" On a Zihpm counter overflow and with LCOFIP asserted, record the overflowing counter ID in shpmsdata and arm a capture. When the LCOFI is actually delivered, the shpmspc register is populated with the address of the interrupted instruction. Capturing shpmspc at LCOFI delivery (rather than at overflow time) ensures the sample PC reflects the correct interrupted instruction. Signed-off-by: Mayuresh Chitale Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.h | 2 ++ target/riscv/tcg/cpu_helper.c | 6 ++++++ target/riscv/tcg/csr.c | 25 +++++++++++++++++++++++++ target/riscv/tcg/pmu.c | 27 +++++++++++++++++++++++++++ 4 files changed, 60 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fe56a6afd1..36425c3605 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -473,6 +473,8 @@ struct CPUArchState { /* Sspesa CSRs */ target_ulong shpmspc; target_ulong shpmsdata; + /* Capture shpmspc/shpmsdata only on the first overflow */ + bool sspesa_capture_pending; =20 /* Sstc CSRs */ uint64_t stimecmp; diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 07d9222652..15af3262ed 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -2255,6 +2255,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) sxlen =3D 16 << riscv_cpu_sxl(env); env->scause =3D cause | ((target_ulong)async << (sxlen - 1)); env->sepc =3D env->pc; + /* On LCOFI delivery, latch the sample PC to the interrupted PC. */ + if (riscv_cpu_cfg(env)->ext_sspesa && env->sspesa_capture_pending)= { + if (async && cause =3D=3D IRQ_PMU_OVF) { + env->shpmspc =3D env->pc; + } + } env->stval =3D tval; env->htval =3D htval; env->htinst =3D tinst; diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index ea49d28aae..e48c954359 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -1228,6 +1228,15 @@ static RISCVException write_minstretcfgh(CPURISCVSta= te *env, int csrno, return RISCV_EXCP_NONE; } =20 +static bool sspesa_is_captured_ctr(CPURISCVState *env, uint32_t evt_index) +{ + if (!riscv_cpu_cfg(env)->ext_sspesa || !env->sspesa_capture_pending) { + return false; + } + + return (env->shpmsdata & SHPMSDATA_CNTRID) =3D=3D evt_index; +} + static RISCVException read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1259,6 +1268,14 @@ static RISCVException write_mhpmevent(CPURISCVState = *env, int csrno, mhpmevt_val =3D val & inh_avail_mask; } =20 + /* Enable the sample capture when OF is cleared for the captured count= er. */ + if (sspesa_is_captured_ctr(env, evt_index)) { + if ((env->mhpmevent_val[evt_index] & MHPMEVENT_BIT_OF) && + !(mhpmevt_val & MHPMEVENT_BIT_OF)) { + env->sspesa_capture_pending =3D false; + } + } + env->mhpmevent_val[evt_index] =3D mhpmevt_val; riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); =20 @@ -1289,6 +1306,14 @@ static RISCVException write_mhpmeventh(CPURISCVState= *env, int csrno, inh_avail_mask |=3D (riscv_has_ext(env, RVH) && riscv_has_ext(env, RVS)) ? MHPMEVENTH_BIT_VSINH : 0; =20 + /* Enable the sample capture when OF is cleared for the captured count= er. */ + if (sspesa_is_captured_ctr(env, evt_index)) { + if ((env->mhpmevent_val[evt_index] & MHPMEVENT_BIT_OF) && + !((val & inh_avail_mask) & MHPMEVENTH_BIT_OF)) { + env->sspesa_capture_pending =3D false; + } + } + env->mhpmevent_val[evt_index] =3D deposit64(env->mhpmevent_val[evt_ind= ex], 32, 32, val & inh_avail_mask= ); =20 diff --git a/target/riscv/tcg/pmu.c b/target/riscv/tcg/pmu.c index 38ad2737e1..337e255da4 100644 --- a/target/riscv/tcg/pmu.c +++ b/target/riscv/tcg/pmu.c @@ -147,6 +147,31 @@ void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, riscv_pmu_icount_update_priv(env, newpriv, new_virt); } =20 +static void riscv_pmu_sspesa_capture(CPURISCVState *env, uint32_t ctr_idx) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_sspesa) { + return; + } + + /* + * Only the first overflow updates the sample CSRs. While a capture is + * pending, keep the lowest counter ID as required by the spec. + */ + if (env->sspesa_capture_pending) { + if ((ctr_idx & SHPMSDATA_CNTRID) < + (env->shpmsdata & SHPMSDATA_CNTRID)) { + env->shpmsdata =3D ctr_idx & SHPMSDATA_CNTRID; + } + return; + } + + /* shpmspc is latched later, on LCOFI delivery. */ + env->shpmsdata =3D ctr_idx & SHPMSDATA_CNTRID; + env->sspesa_capture_pending =3D true; +} + int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) { uint32_t ctr_idx; @@ -191,6 +216,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_ev= ent_idx event_idx) /* Generate interrupt only if OF bit is clear */ if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; + riscv_pmu_sspesa_capture(env, ctr_idx); riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); } } else { @@ -383,6 +409,7 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu, =20 if (cpu->pmu_avail_ctrs & BIT(ctr_idx)) { if (pmu_hpmevent_set_of_if_clear(env, ctr_idx)) { + riscv_pmu_sspesa_capture(env, ctr_idx); riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); } } --=20 2.43.0