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Sun, 16 Aug 2026 18:10:40 -0700 (PDT) From: Jacob Whitaker Abrams X-Google-Original-From: Jacob Whitaker Abrams To: qemu-devel@nongnu.org Cc: Jacob Whitaker Abrams Subject: [PATCH] hw/char/stm32l4x5_usart.c: Support writes smaller than 32-bit Date: Sun, 16 Aug 2026 18:10:08 -0700 Message-ID: <20260817011008.652105-1-satur9nine@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=jwhitakera@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 17 Aug 2026 01:02:37 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1786943009688158500 Content-Type: text/plain; charset="utf-8" Official STM32CubeL4 drivers use and require support for 16-bit writes to UART registers for proper function. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2540 Signed-off-by: Jacob Whitaker Abrams --- hw/char/stm32l4x5_usart.c | 93 +++++++++++++++++++++++------- tests/qtest/stm32l4x5_usart-test.c | 50 +++++++++++++++- 2 files changed, 120 insertions(+), 23 deletions(-) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index dd1b099195..88c4a3b5a7 100644 --- a/hw/char/stm32l4x5_usart.c +++ b/hw/char/stm32l4x5_usart.c @@ -154,8 +154,15 @@ REG32(RDR, 0x24) REG32(TDR, 0x28) FIELD(TDR, TDR, 0, 9) =20 +#define ISR_RESET_VALUE (0x020000C0) + static void stm32l4x5_update_isr(Stm32l4x5UsartBaseState *s) { + if (!(s->cr1 & R_CR1_UE_MASK)) { + s->isr =3D ISR_RESET_VALUE; + return; + } + if (s->cr1 & R_CR1_TE_MASK) { s->isr |=3D R_ISR_TEACK_MASK; } else { @@ -404,9 +411,11 @@ static uint64_t stm32l4x5_usart_base_read(void *opaque= , hwaddr addr, unsigned int size) { Stm32l4x5UsartBaseState *s =3D opaque; + hwaddr base =3D addr & ~0x3ULL; + unsigned int offset =3D addr & 0x3; uint64_t retvalue =3D 0; =20 - switch (addr) { + switch (base) { case A_CR1: retvalue =3D s->cr1; break; @@ -451,6 +460,13 @@ static uint64_t stm32l4x5_usart_base_read(void *opaque= , hwaddr addr, break; } =20 + /* Adjust for partial access */ + if (size =3D=3D 1) { + retvalue =3D (retvalue >> (offset * 8)) & 0xFF; + } else if (size =3D=3D 2) { + retvalue =3D (retvalue >> (offset * 8)) & 0xFFFF; + } + trace_stm32l4x5_usart_read(addr, retvalue); =20 return retvalue; @@ -460,55 +476,88 @@ static void stm32l4x5_usart_base_write(void *opaque, = hwaddr addr, uint64_t val64, unsigned int size) { Stm32l4x5UsartBaseState *s =3D opaque; - const uint32_t value =3D val64; + hwaddr base =3D addr & ~0x3ULL; + unsigned int offset =3D addr & 0x3; + uint32_t value =3D (uint32_t)val64; + + /* Build mask for partial access */ + uint32_t mask; + if (size =3D=3D 4) { + mask =3D 0xFFFFFFFF; + } else if (size =3D=3D 2) { + mask =3D 0xFFFF << (offset * 8); + } else if (size =3D=3D 1) { + mask =3D 0xFF << (offset * 8); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported access size %u\n",= __func__, size); + return; + } + value =3D (value << (offset * 8)) & mask; =20 trace_stm32l4x5_usart_write(addr, value); =20 - switch (addr) { - case A_CR1: - s->cr1 =3D value; + switch (base) { + case A_CR1: { + uint32_t old =3D s->cr1; + s->cr1 =3D (old & ~mask) | value; stm32l4x5_update_params(s); stm32l4x5_update_isr(s); stm32l4x5_update_irq(s); return; - case A_CR2: - s->cr2 =3D value; + } + case A_CR2: { + uint32_t old =3D s->cr2; + s->cr2 =3D (old & ~mask) | value; stm32l4x5_update_params(s); return; - case A_CR3: - s->cr3 =3D value; + } + case A_CR3: { + uint32_t old =3D s->cr3; + s->cr3 =3D (old & ~mask) | value; return; - case A_BRR: - s->brr =3D value; + } + case A_BRR: { + uint32_t old =3D s->brr; + s->brr =3D (old & ~mask) | value; stm32l4x5_update_params(s); return; - case A_GTPR: - s->gtpr =3D value; + } + case A_GTPR: { + uint32_t old =3D s->gtpr; + s->gtpr =3D (old & ~mask) | value; return; - case A_RTOR: - s->rtor =3D value; + } + case A_RTOR: { + uint32_t old =3D s->rtor; + s->rtor =3D (old & ~mask) | value; return; - case A_RQR: + } + case A_RQR: { + /* RQR is write-only, assume full 32-bit access */ usart_update_rqr(s, value); return; + } case A_ISR: qemu_log_mask(LOG_GUEST_ERROR, "%s: ISR is read only !\n", __func__); return; - case A_ICR: - /* Clear the status flags */ + case A_ICR: { + /* Clear flags: value is masked to written bytes */ s->isr &=3D ~value; stm32l4x5_update_irq(s); return; + } case A_RDR: qemu_log_mask(LOG_GUEST_ERROR, "%s: RDR is read only !\n", __func__); return; - case A_TDR: - s->tdr =3D value; + case A_TDR: { + uint32_t old =3D s->tdr; + s->tdr =3D (old & ~mask) | value; s->isr &=3D ~R_ISR_TXE_MASK; usart_transmit(NULL, G_IO_OUT, s); return; + } default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); @@ -521,12 +570,12 @@ static const MemoryRegionOps stm32l4x5_usart_base_ops= =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, .valid =3D { .max_access_size =3D 4, - .min_access_size =3D 4, + .min_access_size =3D 2, .unaligned =3D false }, .impl =3D { .max_access_size =3D 4, - .min_access_size =3D 4, + .min_access_size =3D 2, .unaligned =3D false }, }; diff --git a/tests/qtest/stm32l4x5_usart-test.c b/tests/qtest/stm32l4x5_usa= rt-test.c index a72c5a685d..86b36915ac 100644 --- a/tests/qtest/stm32l4x5_usart-test.c +++ b/tests/qtest/stm32l4x5_usart-test.c @@ -332,6 +332,53 @@ static void test_ack(void) qtest_quit(qts); } =20 +static void test_isr_reset(void) +{ + QTestState *qts =3D qtest_init("-M b-l475e-iot01a"); + init_uart(qts); + /* ISR should show TEACK/REACK after UART init */ + uint32_t isr =3D qtest_readl(qts, USART1_BASE_ADDR + A_ISR); + g_assert_true(isr & R_ISR_TEACK_MASK); + g_assert_true(isr & R_ISR_REACK_MASK); + + /* Clear UE bit in CR1 -> USART disabled */ + uint32_t cr1 =3D qtest_readl(qts, USART1_BASE_ADDR + A_CR1); + qtest_writel(qts, USART1_BASE_ADDR + A_CR1, cr1 & ~R_CR1_UE_MASK); + /* ISR must reset to reset value 0x020000C0 when UE is cleared */ + isr =3D qtest_readl(qts, USART1_BASE_ADDR + A_ISR); + g_assert_cmpuint(isr, =3D=3D, 0x020000C0); + + qtest_quit(qts); +} + +static void test_16bit_access(void) +{ + QTestState *qts =3D qtest_init("-M b-l475e-iot01a"); + + /* Test 16-bit write/read on RTOR */ + qtest_writel(qts, USART1_BASE_ADDR + A_RTOR, 0x00000000); + qtest_writew(qts, USART1_BASE_ADDR + A_RTOR, 0xABCD); + uint16_t rtor16 =3D qtest_readw(qts, USART1_BASE_ADDR + A_RTOR); + g_assert_cmpuint(rtor16, =3D=3D, 0xABCD); + uint32_t rtor32 =3D qtest_readl(qts, USART1_BASE_ADDR + A_RTOR); + g_assert_cmpuint(rtor32, =3D=3D, 0x0000ABCD); + + /* Test upper half 16-bit write */ + qtest_writew(qts, USART1_BASE_ADDR + A_RTOR + 2, 0x1234); + rtor32 =3D qtest_readl(qts, USART1_BASE_ADDR + A_RTOR); + g_assert_cmpuint(rtor32, =3D=3D, 0x1234ABCD); + + /* Test 16-bit write/read on CR1 */ + qtest_writel(qts, USART1_BASE_ADDR + A_CR1, 0x00000000); + qtest_writew(qts, USART1_BASE_ADDR + A_CR1, 0x00FF); + uint16_t cr116 =3D qtest_readw(qts, USART1_BASE_ADDR + A_CR1); + g_assert_cmpuint(cr116, =3D=3D, 0x00FF); + uint32_t cr132 =3D qtest_readl(qts, USART1_BASE_ADDR + A_CR1); + g_assert_cmpuint(cr132, =3D=3D, 0x000000FF); + + qtest_quit(qts); +} + static void check_clock(QTestState *qts, const char *path, uint32_t rcc_re= g, uint32_t reg_offset) { @@ -369,7 +416,8 @@ int main(int argc, char **argv) qtest_add_func("stm32l4x5/usart/receive_str", test_receive_str); qtest_add_func("stm32l4x5/usart/send_str", test_send_str); qtest_add_func("stm32l4x5/usart/ack", test_ack); + qtest_add_func("stm32l4x5/usart/isr_reset", test_isr_reset); + qtest_add_func("stm32l4x5/usart/16bit_access", test_16bit_access); qtest_add_func("stm32l4x5/usart/clock_enable", test_clock_enable); return g_test_run(); } - --=20 2.43.0